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MuChengerMuChenger
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[fix] 适配SPI轮询模式
1 parent e4331e9 commit c0d1dde

58 files changed

Lines changed: 3182 additions & 1262 deletions

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‎bsp/stm32/libraries/HAL_Drivers/drivers/drv_dma.h‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,7 +40,8 @@ struct dma_config {
4040
#endif
4141

4242
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WL) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32G4)\
43-
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5)
43+
|| defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32L5) \
44+
|| defined(SOC_SERIES_STM32N6)
4445
rt_uint32_t request;
4546
#endif
4647
};

‎bsp/stm32/libraries/HAL_Drivers/drivers/drv_spi.c‎

Lines changed: 52 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -160,6 +160,9 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
160160
}
161161
#endif /* SOC_SERIES_STM32H7) */
162162
#endif /* APBPERIPH_BASE */
163+
#if defined(SOC_SERIES_STM32N6)
164+
SPI_CLOCK = HSI_VALUE;
165+
#endif /* SOC_SERIES_STM32N6) */
163166

164167
if (cfg->max_hz >= SPI_CLOCK / 2)
165168
{
@@ -195,11 +198,11 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
195198
spi_handle->Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_256;
196199
}
197200

198-
LOG_D("sys freq: %d, pclk freq: %d, SPI limiting freq: %d, SPI usage freq: %d",
201+
rt_kprintf("sys freq: %d, pclk freq: %d, SPI limiting freq: %d, SPI usage freq: %d",
199202
#if defined(SOC_SERIES_STM32MP1)
200203
HAL_RCC_GetSystemCoreClockFreq(),
201204
#else
202-
HAL_RCC_GetSysClockFreq(),
205+
HAL_RCC_GetSysClockFreq(),
203206
#endif
204207
SPI_CLOCK,
205208
cfg->max_hz,
@@ -219,20 +222,22 @@ static rt_err_t stm32_spi_init(struct stm32_spi *spi_drv, struct rt_spi_configur
219222
spi_handle->State = HAL_SPI_STATE_RESET;
220223
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0) || defined(SOC_SERIES_STM32WB)
221224
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
222-
#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1)
225+
#elif defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32N6)
226+
spi_handle->Init.CRCPolynomial = 7;
223227
spi_handle->Init.Mode = SPI_MODE_MASTER;
224228
spi_handle->Init.NSS = SPI_NSS_SOFT;
225229
spi_handle->Init.NSSPMode = SPI_NSS_PULSE_DISABLE;
226230
spi_handle->Init.NSSPolarity = SPI_NSS_POLARITY_LOW;
227-
spi_handle->Init.CRCPolynomial = 7;
228-
spi_handle->Init.TxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
229-
spi_handle->Init.RxCRCInitializationPattern = SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN;
231+
spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
230232
spi_handle->Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE;
231233
spi_handle->Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE;
232234
spi_handle->Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE;
233235
spi_handle->Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_ENABLE;
234236
spi_handle->Init.IOSwap = SPI_IO_SWAP_DISABLE;
235-
spi_handle->Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA;
237+
#if defined(SOC_SERIES_STM32N6)
238+
spi_handle->Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY;
239+
spi_handle->Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH;
240+
#endif /* SOC_SERIES_STM32N6 */
236241
#endif
237242

238243
if (HAL_SPI_Init(spi_handle) != HAL_OK)
@@ -376,7 +381,7 @@ static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *m
376381
}
377382
else if ((spi_drv->spi_dma_flag & SPI_USING_RX_DMA_FLAG) && (send_length >= DMA_TRANS_MIN_LEN))
378383
{
379-
#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
384+
#if defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32F7)
380385
if (RT_IS_ALIGN((rt_uint32_t)recv_buf, 32) && recv_buf != RT_NULL) /* aligned with 32 bytes? */
381386
{
382387
p_txrx_buffer = (rt_uint32_t *)recv_buf; /* recv_buf aligns with 32 bytes, no more operations */
@@ -561,32 +566,47 @@ static int rt_hw_spi_bus_init(void)
561566
spi_bus_obj[i].dma.handle_rx.Instance = spi_config[i].dma_rx->Instance;
562567
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
563568
spi_bus_obj[i].dma.handle_rx.Init.Channel = spi_config[i].dma_rx->channel;
564-
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
569+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) \
570+
|| defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
565571
spi_bus_obj[i].dma.handle_rx.Init.Request = spi_config[i].dma_rx->request;
566572
#endif
567573
#ifndef SOC_SERIES_STM32U5
574+
#ifdef SOC_SERIES_STM32N6
568575
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
569-
spi_bus_obj[i].dma.handle_rx.Init.PeriphInc = DMA_PINC_DISABLE;
570-
spi_bus_obj[i].dma.handle_rx.Init.MemInc = DMA_MINC_ENABLE;
571-
spi_bus_obj[i].dma.handle_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
572-
spi_bus_obj[i].dma.handle_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
576+
spi_bus_obj[i].dma.handle_rx.Init.SrcInc = DMA_SINC_FIXED;
577+
spi_bus_obj[i].dma.handle_rx.Init.DestInc = DMA_DINC_INCREMENTED;
578+
spi_bus_obj[i].dma.handle_rx.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
579+
spi_bus_obj[i].dma.handle_rx.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
580+
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
581+
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_HIGH_PRIORITY;
582+
#else
583+
spi_bus_obj[i].dma.handle_rx.Init.Direction = DMA_PERIPH_TO_MEMORY;
584+
spi_bus_obj[i].dma.handle_rx.Init.SrcInc = DMA_SINC_FIXED;
585+
spi_bus_obj[i].dma.handle_rx.Init.DestInc = DMA_DINC_INCREMENTED;
586+
spi_bus_obj[i].dma.handle_rx.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
587+
spi_bus_obj[i].dma.handle_rx.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
573588
spi_bus_obj[i].dma.handle_rx.Init.Mode = DMA_NORMAL;
574589
spi_bus_obj[i].dma.handle_rx.Init.Priority = DMA_PRIORITY_HIGH;
590+
#endif /* SOC_SERIES_STM32N6 */
591+
575592
#endif
576593
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
577594
spi_bus_obj[i].dma.handle_rx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
578595
spi_bus_obj[i].dma.handle_rx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
579596
spi_bus_obj[i].dma.handle_rx.Init.MemBurst = DMA_MBURST_INC4;
580597
spi_bus_obj[i].dma.handle_rx.Init.PeriphBurst = DMA_PBURST_INC4;
598+
#elif defined(SOC_SERIES_STM32N6)
599+
spi_bus_obj[i].dma.handle_rx.Init.SrcBurstLength = 1;
600+
spi_bus_obj[i].dma.handle_rx.Init.DestBurstLength = 1;
581601
#endif
582-
583602
{
584603
rt_uint32_t tmpreg = 0x00U;
585604
#if defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32F0)
586605
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
587606
SET_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
588607
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_rx->dma_rcc);
589-
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
608+
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
609+
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32N6)
590610
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
591611
/* Delay after an RCC peripheral clock enabling */
592612
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_rx->dma_rcc);
@@ -605,23 +625,37 @@ static int rt_hw_spi_bus_init(void)
605625
spi_bus_obj[i].dma.handle_tx.Instance = spi_config[i].dma_tx->Instance;
606626
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7)
607627
spi_bus_obj[i].dma.handle_tx.Init.Channel = spi_config[i].dma_tx->channel;
608-
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
628+
#elif defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32G0) || defined(SOC_SERIES_STM32MP1) \
629+
|| defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32N6)
609630
spi_bus_obj[i].dma.handle_tx.Init.Request = spi_config[i].dma_tx->request;
610631
#endif
611632
#ifndef SOC_SERIES_STM32U5
633+
#ifdef SOC_SERIES_STM32N6
634+
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
635+
spi_bus_obj[i].dma.handle_tx.Init.SrcInc = DMA_SINC_INCREMENTED;
636+
spi_bus_obj[i].dma.handle_tx.Init.DestInc = DMA_DINC_FIXED;
637+
spi_bus_obj[i].dma.handle_tx.Init.SrcDataWidth = DMA_SRC_DATAWIDTH_BYTE;
638+
spi_bus_obj[i].dma.handle_tx.Init.DestDataWidth = DMA_DEST_DATAWIDTH_BYTE;
639+
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
640+
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_HIGH_PRIORITY;
641+
#else
612642
spi_bus_obj[i].dma.handle_tx.Init.Direction = DMA_MEMORY_TO_PERIPH;
613643
spi_bus_obj[i].dma.handle_tx.Init.PeriphInc = DMA_PINC_DISABLE;
614644
spi_bus_obj[i].dma.handle_tx.Init.MemInc = DMA_MINC_ENABLE;
615645
spi_bus_obj[i].dma.handle_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE;
616646
spi_bus_obj[i].dma.handle_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE;
617647
spi_bus_obj[i].dma.handle_tx.Init.Mode = DMA_NORMAL;
618648
spi_bus_obj[i].dma.handle_tx.Init.Priority = DMA_PRIORITY_LOW;
649+
#endif /* SOC_SERIES_STM32N6 */
619650
#endif
620651
#if defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32MP1) || defined(SOC_SERIES_STM32H7)
621652
spi_bus_obj[i].dma.handle_tx.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
622653
spi_bus_obj[i].dma.handle_tx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
623654
spi_bus_obj[i].dma.handle_tx.Init.MemBurst = DMA_MBURST_INC4;
624655
spi_bus_obj[i].dma.handle_tx.Init.PeriphBurst = DMA_PBURST_INC4;
656+
#elif defined(SOC_SERIES_STM32N6)
657+
spi_bus_obj[i].dma.handle_rx.Init.SrcBurstLength = 1;
658+
spi_bus_obj[i].dma.handle_rx.Init.DestBurstLength = 1;
625659
#endif
626660

627661
{
@@ -630,7 +664,8 @@ static int rt_hw_spi_bus_init(void)
630664
/* enable DMA clock && Delay after an RCC peripheral clock enabling*/
631665
SET_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
632666
tmpreg = READ_BIT(RCC->AHBENR, spi_config[i].dma_tx->dma_rcc);
633-
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) || defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7)
667+
#elif defined(SOC_SERIES_STM32F2) || defined(SOC_SERIES_STM32F4) || defined(SOC_SERIES_STM32F7) \
668+
|| defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32WB) || defined(SOC_SERIES_STM32H7) || defined(SOC_SERIES_STM32N6)
634669
SET_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);
635670
/* Delay after an RCC peripheral clock enabling */
636671
tmpreg = READ_BIT(RCC->AHB1ENR, spi_config[i].dma_tx->dma_rcc);

‎bsp/stm32/libraries/HAL_Drivers/drv_common.c‎

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -205,9 +205,7 @@ rt_weak void rt_hw_board_init(void)
205205
HAL_Init();
206206

207207
/* System clock initialization */
208-
#ifndef SOC_SERIES_STM32N6
209208
SystemClock_Config();
210-
#endif
211209

212210
#if defined(RT_USING_HEAP)
213211
/* Heap initialization */

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