Merge branch 'staging' into owr4-avenue-based

memo33 · memo33 · commit ce30352e17de · 2025-06-04T20:43:58.000+02:00
diff --git a/src/main/scala/module/Main.scala b/src/main/scala/module/Main.scala
@@ -30,6 +30,8 @@ abstract class AbstractMain {
     }
   }
 
+  private lazy val shouldIgnoreMirroredOrientations: Set[Int] = MirrorVariants.ignoreMirroredOrientations(resolve)
+
   def main(args: Array[String]): Unit = start()
 
   /** Creates a generator with a new context, runs its start method and outputs the resulting RUL2 code to file. */
@@ -54,6 +56,14 @@ abstract class AbstractMain {
           printer.println(rule.toRul2String)
         }
       }
+      // finally remove accumulated orientations that we want to ignore (like accidentally mirrored TLAs)
+      tileOrientationCache.accum.mapValuesInPlace { (id, repr) =>
+        if (shouldIgnoreMirroredOrientations(id)) repr.filterNot(_.flipped)
+        else repr
+      }
+      tileOrientationCache.accum.filterInPlace { (id, repr) =>  // remove from accum if equal to cache (so that regenerateTileOrientationCache stabilizes eventually)
+        !tileOrientationCache.cache.get(id).contains(repr)
+      }
     }
   }
 }
diff --git a/src/main/scala/module/MirrorVariants.scala b/src/main/scala/module/MirrorVariants.scala
@@ -54,23 +54,43 @@ object MirrorVariants {
     case _ => tile
   }
 
-  private val tlaPreprocessor: Rule[SymTile] => Iterator[Rule[SymTile]] = rule => {
-    if (!rule.exists(containsTlaFlags)) {
-      Iterator(rule)
-    } else if (rule.forall(shouldProjectTlaLeftOnly)) {
-      Iterator(rule.map(projectTlaLeft))
-    } else {
-      Iterator(rule.map(projectTlaLeft), rule.map(projectTlaRight))
-    }
+  val preprocessor: Rule[SymTile] => Iterator[Rule[SymTile]] = rule => {
+    val hasMirrorVariant = rule.exists(tile => mirrorVariants.contains(tile))
+    for {
+      rule <- if (hasMirrorVariant) Iterator(  // yield the two projected rules
+                rule.map(tile => mirrorVariants.get(tile).map(_._1).getOrElse(tile)),
+                rule.map(tile => mirrorVariants.get(tile).map(_._2).getOrElse(tile)),
+              )
+              else Iterator(rule)
+      hasTlaFlags = rule.exists(containsTlaFlags)
+      rule <- if (!hasTlaFlags) Iterator(rule)
+              else if (rule.forall(shouldProjectTlaLeftOnly)) Iterator(rule.map(projectTlaLeft))
+              else Iterator(rule.map(projectTlaLeft), rule.map(projectTlaRight))
+      // We duplicate the rule by its R2F1 variant if there are TLAs or mirror
+      // variants involved, as the left/right distinction can make them resolve
+      // to different IDs (and the generators do not necessarily account for
+      // this). For example, this is needed for Tla5/Avenue D×D.
+      rule <- if (hasMirrorVariant || hasTlaFlags) Iterator(rule, rule.map(_ * R2F1)).distinct
+              else Iterator(rule)
+    } yield rule
   }
 
-  val preprocessor: Rule[SymTile] => Iterator[Rule[SymTile]] = rule => {
-    if (!rule.exists(tile => mirrorVariants.contains(tile))) {
-      Iterator(rule)
-    } else {
-      Iterator(  // yield the two projected rules
-        rule.map(tile => mirrorVariants.get(tile).map(_._1).getOrElse(tile)),
-        rule.map(tile => mirrorVariants.get(tile).map(_._2).getOrElse(tile)))
+  /* For plain orthogonal and diagonal tiles of TLA networks, we ignore any
+   * remapping defined in `tileOrientationCache` that leads to mirroring, as
+   * that would amplify the mirroring problems due to the presence of turning
+   * lanes. Not a perfect solution, as occasional mirroring problems will remain.
+   */
+  def ignoreMirroredOrientations(resolve: IdResolver): Set[Int] = {
+    val ids = Set.newBuilder[Int]
+    for {
+      n <- Seq(Tla3, Tla5, Tla7m, Road, Onewayroad)  // TODO consider adding all the networks
+      dir <- Seq(NS, ES, SE)  // these are arbitrary orth/diag directions to allow us find the IDs
+      tile <- Seq(NetworkProperties.projectTlaLeft(n~dir), NetworkProperties.projectTlaRight(n~dir))
+      idTile <- resolve.lift(tile)
+    } {
+      ids += idTile.id
     }
-  }.flatMap(tlaPreprocessor)
+    ids.result()
+  }
+
 }
diff --git a/src/test/scala/meta/RuleTransducerSpec.scala b/src/test/scala/meta/RuleTransducerSpec.scala
@@ -4,6 +4,7 @@ import scala.collection.immutable.StringOps
 import org.scalatest.wordspec.AnyWordSpec
 import org.scalatest.matchers.should.Matchers
 import com.sc4nam.module, module.syntax._, Implicits._
+import com.sc4nam.module.{NetworkProperties => NP}
 import group._, RotFlip._, SymGroup._, Network._, Flags._
 import RuleTransducer._
 
@@ -21,46 +22,44 @@ class RuleTransducerSpec extends AnyWordSpec with Matchers {
 
       context.preprocess( Tla3~WE & Road~NS | (Road ~> Tla3)~WE ).toSeq should have size (1)
       val diag = context.preprocess( Tla3~WE & Road~WS | (Road ~> Tla3)~WE ).toSeq
-      diag should have size (2)
+      diag should have size (4)
       for (r <- diag) {
         createRules(r.map(_.toIdSymTile(resolver)), context.tileOrientationCache.cache, context.tileOrientationCache.accum).toSeq should have size (2)
       }
     }
   }
 
-  def makeTileLeft(t: Tile): Tile = Tile(t.segs map (s => if (!s.network.isTla) s else s.copy(flags = s.flags.spinLeft)))
-  def makeTileRight(t: Tile): Tile = Tile(t.segs map (s => if (!s.network.isTla) s else s.copy(flags = s.flags.spinRight)))
   "Resolver" should {
     "resolve left/right-spinned TLAs correctly" in {
       val tiles = Seq[Tile]( Tla3~WE & Road~ES, Tla3~WE & Ard3~ES, Tla3~WE & Tla3~ES )
       val tile2 = Seq[Tile]( Tla3~WE, Tla3~WE & Road~NS, Tla3~WE & Ard3~NS, Tla3~WE & Tla3~NS )
       for (t <- tiles) {
-        resolver(makeTileLeft(t)) should not be resolver(makeTileRight(t))
+        resolver(NP.projectTlaLeft(t)) should not be resolver(NP.projectTlaRight(t))
       }
       for (t <- tile2) {
-        resolver(makeTileLeft(t)) should be (resolver(makeTileRight(t)))
+        resolver(NP.projectTlaLeft(t)) should be (resolver(NP.projectTlaRight(t)))
       }
     }
     "handle flipped left/right-spinned TLAs correctly" in {
       val (t1, t2) = ( Tla3~WE & Road~ES, Tla3~WE & Road~WS )
-      resolver(makeTileLeft(t1)).id should not be (resolver(makeTileLeft(t2)).id)
+      resolver(NP.projectTlaLeft(t1)).id should not be (resolver(NP.projectTlaLeft(t2)).id)
       for ((t, i) <- Seq(t1, t2).zipWithIndex) {
-        makeTileLeft(t).toIdSymTile(resolver).repr.filter(_.flipped ^ (i!=0)) should be (Symbol("empty"))
-        makeTileRight(t).toIdSymTile(resolver).repr.filter(!_.flipped ^ (i!=0)) should be (Symbol("empty"))
+        NP.projectTlaLeft(t).toIdSymTile(resolver).repr.filter(_.flipped ^ (i!=0)) should be (Symbol("empty"))
+        NP.projectTlaRight(t).toIdSymTile(resolver).repr.filter(!_.flipped ^ (i!=0)) should be (Symbol("empty"))
       }
     }
     "find RHS for TLA" in {
-      val rule = (Tla3~WE | (Road ~> Tla3)~(2,0,11,0)) map makeTileLeft map (_.toIdSymTile(resolver))
+      val rule = (Tla3~WE | (Road ~> Tla3)~(2,0,11,0)) map NP.projectTlaLeft map (_.toIdSymTile(resolver))
       possibleMapOrientation(Set(R0F0, R1F0), R3F0/R2F1, Quotient.Dih4, R1F1/R2F1) should not be (Symbol("empty"))
       createRules(rule, context.tileOrientationCache.cache, context.tileOrientationCache.accum)
     }
     "resolve diagonal TLA intersections" in {
-      val t1 = makeTileLeft(Tla3~ES & Road~WS)
-      val t2 = makeTileRight(Tla3~ES & Road~WS)
-      val t3 = makeTileLeft(Tla3~WS & Road~ES)
+      val t1 = NP.projectTlaLeft(Tla3~ES & Road~WS)
+      val t2 = NP.projectTlaRight(Tla3~ES & Road~WS)
+      val t3 = NP.projectTlaLeft(Tla3~WS & Road~ES)
       resolver(t3) * R0F1 should be (resolver(t2))
       resolver(t1).id should not be (resolver(t2).id)
-      resolver(makeTileLeft(Tla3~ES & Tla3~WS)) should be (resolver(makeTileRight(Tla3~ES & Tla3~WS)))
+      resolver(NP.projectTlaLeft(Tla3~ES & Tla3~WS)) should be (resolver(NP.projectTlaRight(Tla3~ES & Tla3~WS)))
     }
   }
 }
diff --git a/src/test/scala/module/MirrorVariantsSpec.scala b/src/test/scala/module/MirrorVariantsSpec.scala
@@ -56,29 +56,29 @@ class MirrorVariantsSpec extends AnyWordSpec with Matchers {
 
     "produce expected results for TLA network crossings" in {
       implicit val context = RuleTransducer.Context(resolve, preprocess = MirrorVariants.preprocessor)
-      RuleTransducer(Tla3~WE | (Road~>Tla3)~WE & Rail~ES).toSeq shouldBe Seq(
+      RuleTransducer(Tla3~WE | (Road~>Tla3)~WE & Rail~ES).toSeq should contain theSameElementsAs Seq(
         Rule(0x51000000,1,0, 0x03010200,1,0, 0x51000000,1,0, 0x51005500,3,0),
         Rule(0x51000000,3,0, 0x03010200,1,0, 0x51000000,3,0, 0x51005500,3,0),
         Rule(0x51000000,3,0, 0x03020500,3,1, 0x51000000,3,0, 0x51005500,1,1),
         Rule(0x51000000,1,0, 0x03020500,3,1, 0x51000000,1,0, 0x51005500,1,1))
-      RuleTransducer(Tla5~WE | (Road~>Tla5)~WE & Rail~ES).toSeq shouldBe Seq(
+      RuleTransducer(Tla5~WE | (Road~>Tla5)~WE & Rail~ES).toSeq should contain theSameElementsAs Seq(
         Rule(0x51100000,3,0, 0x03010200,1,0, 0x51100000,3,0, 0x51105500,3,0),
         Rule(0x51100000,1,0, 0x03020500,3,1, 0x51100000,1,0, 0x51105500,1,1))
-      RuleTransducer(Tla5~WE | (Road~>Tla5)~WE & Road~ES).toSeq shouldBe Seq(
+      RuleTransducer(Tla5~WE | (Road~>Tla5)~WE & Road~ES).toSeq should contain theSameElementsAs Seq(
         Rule(0x51100000,3,0, 0x00003900,1,0, 0x51100000,3,0, 0x51105100,3,0),
         Rule(0x51100000,1,0, 0x00003900,3,1, 0x51100000,1,0, 0x71105100,1,1))  // 0x71... variant
-      RuleTransducer(Tla3~WE | (Road~>Tla3)~WE & Lightrail~ES).toSeq shouldBe Seq(
+      RuleTransducer(Tla3~WE | (Road~>Tla3)~WE & Lightrail~ES).toSeq should contain theSameElementsAs Seq(
         Rule(0x51000000,1,0, 0x08DD1600,1,1, 0x51000000,1,0, 0x51005600,3,0),
         Rule(0x51000000,3,0, 0x08DD1600,1,1, 0x51000000,3,0, 0x51005600,3,0),
         Rule(0x51000000,3,0, 0x08DD1600,3,0, 0x51000000,3,0, 0x51005600,1,1),
         Rule(0x51000000,1,0, 0x08DD1600,3,0, 0x51000000,1,0, 0x51005600,1,1))
-      RuleTransducer(Tla5~EW | (Avenue~>Tla5)~EW & Avenue~NS).toSet shouldBe Set(
+      RuleTransducer(Tla5~EW | (Avenue~>Tla5)~EW & Avenue~NS).toSeq should contain theSameElementsAs Seq(
         Rule(0x51100000,3,0, 0x04009000,0,0, 0x51100000,3,0, 0x71101300,2,1),
         Rule(0x51100000,1,0, 0x04009000,1,0, 0x51100000,1,0, 0x51101300,0,0))
-      RuleTransducer(Tla5~EW & Avenue~NS | (Avenue~>Tla5)~EW & Avenue~SN).toSet shouldBe Set(
+      RuleTransducer(Tla5~EW & Avenue~NS | (Avenue~>Tla5)~EW & Avenue~SN).toSeq should contain theSameElementsAs Seq(
         Rule(0x71101300,2,1, 0x04009000,3,0, 0x71101300,2,1, 0x51101300,2,0),
         Rule(0x51101300,0,0, 0x04009000,2,0, 0x51101300,0,0, 0x71101300,0,1))
-      RuleTransducer(Tla5~EW & Avenue~SN | (Avenue~>Tla5)~EW).toSet shouldBe Set(
+      RuleTransducer(Tla5~EW & Avenue~SN | (Avenue~>Tla5)~EW).toSeq should contain theSameElementsAs Seq(
         Rule(0x51101300,2,0, 0x04006100,3,0, 0x51101300,2,0, 0x51100000,3,0),
         Rule(0x71101300,0,1, 0x04006100,1,0, 0x71101300,0,1, 0x51100000,1,0))
     }

Original file line number	Diff line number	Diff line change
`@@ -30,6 +30,8 @@ abstract class AbstractMain {`
`30`	`30`	`}`
`31`	`31`	`}`
`32`	`32`
	`33`	`+ private lazy val shouldIgnoreMirroredOrientations: Set[Int] = MirrorVariants.ignoreMirroredOrientations(resolve)`
	`34`	`+`
`33`	`35`	`def main(args: Array[String]): Unit = start()`
`34`	`36`
`35`	`37`	`/** Creates a generator with a new context, runs its start method and outputs the resulting RUL2 code to file. */`
`@@ -54,6 +56,14 @@ abstract class AbstractMain {`
`54`	`56`	`printer.println(rule.toRul2String)`
`55`	`57`	`}`
`56`	`58`	`}`
	`59`	`+ // finally remove accumulated orientations that we want to ignore (like accidentally mirrored TLAs)`
	`60`	`+ tileOrientationCache.accum.mapValuesInPlace { (id, repr) =>`
	`61`	`+ if (shouldIgnoreMirroredOrientations(id)) repr.filterNot(_.flipped)`
	`62`	`+ else repr`
	`63`	`+ }`
	`64`	`+ tileOrientationCache.accum.filterInPlace { (id, repr) => // remove from accum if equal to cache (so that regenerateTileOrientationCache stabilizes eventually)`
	`65`	`+ !tileOrientationCache.cache.get(id).contains(repr)`
	`66`	`+ }`
`57`	`67`	`}`
`58`	`68`	`}`
`59`	`69`	`}`
Original file line number	Diff line number	Diff line change
`@@ -4,6 +4,7 @@ import scala.collection.immutable.StringOps`
`4`	`4`	`import org.scalatest.wordspec.AnyWordSpec`
`5`	`5`	`import org.scalatest.matchers.should.Matchers`
`6`	`6`	`import com.sc4nam.module, module.syntax._, Implicits._`
	`7`	`+import com.sc4nam.module.{NetworkProperties => NP}`
`7`	`8`	`import group._, RotFlip._, SymGroup._, Network._, Flags._`
`8`	`9`	`import RuleTransducer._`
`9`	`10`
`@@ -21,46 +22,44 @@ class RuleTransducerSpec extends AnyWordSpec with Matchers {`
`21`	`22`
`22`	`23`	`context.preprocess( Tla3~WE & Road~NS \| (Road ~> Tla3)~WE ).toSeq should have size (1)`
`23`	`24`	`val diag = context.preprocess( Tla3~WE & Road~WS \| (Road ~> Tla3)~WE ).toSeq`
`24`		`- diag should have size (2)`
	`25`	`+ diag should have size (4)`
`25`	`26`	`for (r <- diag) {`
`26`	`27`	`createRules(r.map(_.toIdSymTile(resolver)), context.tileOrientationCache.cache, context.tileOrientationCache.accum).toSeq should have size (2)`
`27`	`28`	`}`
`28`	`29`	`}`
`29`	`30`	`}`
`30`	`31`
`31`		`- def makeTileLeft(t: Tile): Tile = Tile(t.segs map (s => if (!s.network.isTla) s else s.copy(flags = s.flags.spinLeft)))`
`32`		`- def makeTileRight(t: Tile): Tile = Tile(t.segs map (s => if (!s.network.isTla) s else s.copy(flags = s.flags.spinRight)))`
`33`	`32`	`"Resolver" should {`
`34`	`33`	`"resolve left/right-spinned TLAs correctly" in {`
`35`	`34`	`val tiles = Seq[Tile]( Tla3~WE & Road~ES, Tla3~WE & Ard3~ES, Tla3~WE & Tla3~ES )`
`36`	`35`	`val tile2 = Seq[Tile]( Tla3~WE, Tla3~WE & Road~NS, Tla3~WE & Ard3~NS, Tla3~WE & Tla3~NS )`
`37`	`36`	`for (t <- tiles) {`
`38`		`- resolver(makeTileLeft(t)) should not be resolver(makeTileRight(t))`
	`37`	`+ resolver(NP.projectTlaLeft(t)) should not be resolver(NP.projectTlaRight(t))`
`39`	`38`	`}`
`40`	`39`	`for (t <- tile2) {`
`41`		`- resolver(makeTileLeft(t)) should be (resolver(makeTileRight(t)))`
	`40`	`+ resolver(NP.projectTlaLeft(t)) should be (resolver(NP.projectTlaRight(t)))`
`42`	`41`	`}`
`43`	`42`	`}`
`44`	`43`	`"handle flipped left/right-spinned TLAs correctly" in {`
`45`	`44`	`val (t1, t2) = ( Tla3~WE & Road~ES, Tla3~WE & Road~WS )`
`46`		`- resolver(makeTileLeft(t1)).id should not be (resolver(makeTileLeft(t2)).id)`
	`45`	`+ resolver(NP.projectTlaLeft(t1)).id should not be (resolver(NP.projectTlaLeft(t2)).id)`
`47`	`46`	`for ((t, i) <- Seq(t1, t2).zipWithIndex) {`
`48`		`- makeTileLeft(t).toIdSymTile(resolver).repr.filter(_.flipped ^ (i!=0)) should be (Symbol("empty"))`
`49`		`- makeTileRight(t).toIdSymTile(resolver).repr.filter(!_.flipped ^ (i!=0)) should be (Symbol("empty"))`
	`47`	`+ NP.projectTlaLeft(t).toIdSymTile(resolver).repr.filter(_.flipped ^ (i!=0)) should be (Symbol("empty"))`
	`48`	`+ NP.projectTlaRight(t).toIdSymTile(resolver).repr.filter(!_.flipped ^ (i!=0)) should be (Symbol("empty"))`
`50`	`49`	`}`
`51`	`50`	`}`
`52`	`51`	`"find RHS for TLA" in {`
`53`		`- val rule = (Tla3~WE \| (Road ~> Tla3)~(2,0,11,0)) map makeTileLeft map (_.toIdSymTile(resolver))`
	`52`	`+ val rule = (Tla3~WE \| (Road ~> Tla3)~(2,0,11,0)) map NP.projectTlaLeft map (_.toIdSymTile(resolver))`
`54`	`53`	`possibleMapOrientation(Set(R0F0, R1F0), R3F0/R2F1, Quotient.Dih4, R1F1/R2F1) should not be (Symbol("empty"))`
`55`	`54`	`createRules(rule, context.tileOrientationCache.cache, context.tileOrientationCache.accum)`
`56`	`55`	`}`
`57`	`56`	`"resolve diagonal TLA intersections" in {`
`58`		`- val t1 = makeTileLeft(Tla3~ES & Road~WS)`
`59`		`- val t2 = makeTileRight(Tla3~ES & Road~WS)`
`60`		`- val t3 = makeTileLeft(Tla3~WS & Road~ES)`
	`57`	`+ val t1 = NP.projectTlaLeft(Tla3~ES & Road~WS)`
	`58`	`+ val t2 = NP.projectTlaRight(Tla3~ES & Road~WS)`
	`59`	`+ val t3 = NP.projectTlaLeft(Tla3~WS & Road~ES)`
`61`	`60`	`resolver(t3) * R0F1 should be (resolver(t2))`
`62`	`61`	`resolver(t1).id should not be (resolver(t2).id)`
`63`		`- resolver(makeTileLeft(Tla3~ES & Tla3~WS)) should be (resolver(makeTileRight(Tla3~ES & Tla3~WS)))`
	`62`	`+ resolver(NP.projectTlaLeft(Tla3~ES & Tla3~WS)) should be (resolver(NP.projectTlaRight(Tla3~ES & Tla3~WS)))`
`64`	`63`	`}`
`65`	`64`	`}`
`66`	`65`	`}`