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| 1 | +/* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | +/* |
| 3 | + * Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved. |
| 4 | + * |
| 5 | + * This program is free software; you can redistribute it and/or modify it |
| 6 | + * under the terms and conditions of the GNU General Public License, |
| 7 | + * version 2, as published by the Free Software Foundation. |
| 8 | + * |
| 9 | + * This program is distributed in the hope it will be useful, but WITHOUT |
| 10 | + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | + * more details. |
| 13 | + */ |
| 14 | + |
| 15 | +#ifndef NVFS_H |
| 16 | +#define NVFS_H |
| 17 | + |
| 18 | +#include <linux/types.h> |
| 19 | +#include <linux/delay.h> |
| 20 | +#include <linux/blkdev.h> |
| 21 | +#include <linux/cpumask.h> |
| 22 | +#include <linux/scatterlist.h> |
| 23 | +#include <linux/percpu-defs.h> |
| 24 | +#include <linux/dma-direction.h> |
| 25 | + |
| 26 | +#define REGSTR2(x) x##_register_nvfs_dma_ops |
| 27 | +#define REGSTR(x) REGSTR2(x) |
| 28 | + |
| 29 | +#define UNREGSTR2(x) x##_unregister_nvfs_dma_ops |
| 30 | +#define UNREGSTR(x) UNREGSTR2(x) |
| 31 | + |
| 32 | +#define REGISTER_FUNC REGSTR(MODULE_PREFIX) |
| 33 | +#define UNREGISTER_FUNC UNREGSTR(MODULE_PREFIX) |
| 34 | + |
| 35 | +#define NVFS_IO_ERR -1 |
| 36 | +#define NVFS_CPU_REQ -2 |
| 37 | + |
| 38 | +#define NVFS_HOLD_TIME_MS 1000 |
| 39 | + |
| 40 | +extern struct nvfs_dma_rw_ops *nvfs_ops; |
| 41 | + |
| 42 | +extern atomic_t nvfs_shutdown; |
| 43 | + |
| 44 | +DECLARE_PER_CPU(long, nvfs_n_ops); |
| 45 | + |
| 46 | +static inline long nvfs_count_ops(void) |
| 47 | +{ |
| 48 | + int i; |
| 49 | + long sum = 0; |
| 50 | + |
| 51 | + for_each_possible_cpu(i) |
| 52 | + sum += per_cpu(nvfs_n_ops, i); |
| 53 | + return sum; |
| 54 | +} |
| 55 | + |
| 56 | +static inline bool nvfs_get_ops(void) |
| 57 | +{ |
| 58 | + if (nvfs_ops && !atomic_read(&nvfs_shutdown)) { |
| 59 | + this_cpu_inc(nvfs_n_ops); |
| 60 | + return true; |
| 61 | + } |
| 62 | + return false; |
| 63 | +} |
| 64 | + |
| 65 | +static inline void nvfs_put_ops(void) |
| 66 | +{ |
| 67 | + this_cpu_dec(nvfs_n_ops); |
| 68 | +} |
| 69 | + |
| 70 | +struct nvfs_dma_rw_ops { |
| 71 | + unsigned long long ft_bmap; // feature bitmap |
| 72 | + |
| 73 | + int (*nvfs_blk_rq_map_sg)(struct request_queue *q, |
| 74 | + struct request *req, |
| 75 | + struct scatterlist *sglist); |
| 76 | + |
| 77 | + int (*nvfs_dma_map_sg_attrs)(struct device *device, |
| 78 | + struct scatterlist *sglist, |
| 79 | + int nents, |
| 80 | + enum dma_data_direction dma_dir, |
| 81 | + unsigned long attrs); |
| 82 | + |
| 83 | + int (*nvfs_dma_unmap_sg)(struct device *device, |
| 84 | + struct scatterlist *sglist, |
| 85 | + int nents, |
| 86 | + enum dma_data_direction dma_dir); |
| 87 | + |
| 88 | + bool (*nvfs_is_gpu_page)(struct page *page); |
| 89 | + |
| 90 | + unsigned int (*nvfs_gpu_index)(struct page *page); |
| 91 | + |
| 92 | + unsigned int (*nvfs_device_priority)(struct device *dev, unsigned int gpu_index); |
| 93 | +}; |
| 94 | + |
| 95 | +// feature list for dma_ops, values indicate bit pos |
| 96 | +enum ft_bits { |
| 97 | + nvfs_ft_prep_sglist = 1ULL << 0, |
| 98 | + nvfs_ft_map_sglist = 1ULL << 1, |
| 99 | + nvfs_ft_is_gpu_page = 1ULL << 2, |
| 100 | + nvfs_ft_device_priority = 1ULL << 3, |
| 101 | +}; |
| 102 | + |
| 103 | +// check features for use in registration with vendor drivers |
| 104 | +#define NVIDIA_FS_CHECK_FT_SGLIST_PREP(ops) ((ops)->ft_bmap & nvfs_ft_prep_sglist) |
| 105 | +#define NVIDIA_FS_CHECK_FT_SGLIST_DMA(ops) ((ops)->ft_bmap & nvfs_ft_map_sglist) |
| 106 | +#define NVIDIA_FS_CHECK_FT_GPU_PAGE(ops) ((ops)->ft_bmap & nvfs_ft_is_gpu_page) |
| 107 | +#define NVIDIA_FS_CHECK_FT_DEVICE_PRIORITY(ops) ((ops)->ft_bmap & nvfs_ft_device_priority) |
| 108 | + |
| 109 | +int REGISTER_FUNC(struct nvfs_dma_rw_ops *ops); |
| 110 | + |
| 111 | +void UNREGISTER_FUNC(void); |
| 112 | + |
| 113 | +#endif /* NVFS_H */ |
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