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geertusmb49
geertu
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smb49
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pinctrl: renesas: r8a779g0: Fix Group 6/7 pin functions
BugLink: https://bugs.launchpad.net/bugs/2025067 [ Upstream commit 203734a ] According to R-Car V4H Series User’s Manual: Hardware Rev. 0.54, pin groups 6 and 7 do not use Module Select Registers to configure pin functions. Hence: - Remove the non-existent Module Select Registers (MODSEL[67]), - Correct the affected PINMUX definitions. Fixes: 36611d2 ("pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx") Fixes: ad9bb2f ("pinctrl: renesas: Initial R8A779G0 (R-Car V4H) PFC support") Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/06972cafd0efa4cfb395cfa76000a1bdae5e9e73.1669036423.git.geert+renesas@glider.be Signed-off-by: Sasha Levin <sashal@kernel.org> Signed-off-by: Kamal Mostafa <kamal@canonical.com> Signed-off-by: Stefan Bader <stefan.bader@canonical.com>
1 parent 3cb5a21 commit a85fea5

1 file changed

Lines changed: 49 additions & 122 deletions

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‎drivers/pinctrl/renesas/pfc-r8a779g0.c‎

Lines changed: 49 additions & 122 deletions
Original file line numberDiff line numberDiff line change
@@ -649,30 +649,6 @@ FM(IP0SR8_23_20) IP0SR8_23_20 FM(IP1SR8_23_20) IP1SR8_23_20 \
649649
FM(IP0SR8_27_24) IP0SR8_27_24 \
650650
FM(IP0SR8_31_28) IP0SR8_31_28
651651

652-
/* MOD_SEL6 */ /* 0 */ /* 1 */
653-
#define MOD_SEL6_18 FM(SEL_AVB1_TD3_0) FM(SEL_AVB1_TD3_1)
654-
#define MOD_SEL6_16 FM(SEL_AVB1_TD2_0) FM(SEL_AVB1_TD2_1)
655-
#define MOD_SEL6_13 FM(SEL_AVB1_TD0_0) FM(SEL_AVB1_TD0_1)
656-
#define MOD_SEL6_12 FM(SEL_AVB1_TD1_0) FM(SEL_AVB1_TD1_1)
657-
#define MOD_SEL6_10 FM(SEL_AVB1_AVTP_PPS_0) FM(SEL_AVB1_AVTP_PPS_1)
658-
#define MOD_SEL6_7 FM(SEL_AVB1_TX_CTL_0) FM(SEL_AVB1_TX_CTL_1)
659-
#define MOD_SEL6_6 FM(SEL_AVB1_TXC_0) FM(SEL_AVB1_TXC_1)
660-
#define MOD_SEL6_5 FM(SEL_AVB1_AVTP_MATCH_0) FM(SEL_AVB1_AVTP_MATCH_1)
661-
#define MOD_SEL6_2 FM(SEL_AVB1_MDC_0) FM(SEL_AVB1_MDC_1)
662-
#define MOD_SEL6_1 FM(SEL_AVB1_MAGIC_0) FM(SEL_AVB1_MAGIC_1)
663-
664-
/* MOD_SEL7 */ /* 0 */ /* 1 */
665-
#define MOD_SEL7_16 FM(SEL_AVB0_TX_CTL_0) FM(SEL_AVB0_TX_CTL_1)
666-
#define MOD_SEL7_15 FM(SEL_AVB0_TXC_0) FM(SEL_AVB0_TXC_1)
667-
#define MOD_SEL7_13 FM(SEL_AVB0_MDC_0) FM(SEL_AVB0_MDC_1)
668-
#define MOD_SEL7_11 FM(SEL_AVB0_TD0_0) FM(SEL_AVB0_TD0_1)
669-
#define MOD_SEL7_10 FM(SEL_AVB0_MAGIC_0) FM(SEL_AVB0_MAGIC_1)
670-
#define MOD_SEL7_7 FM(SEL_AVB0_TD1_0) FM(SEL_AVB0_TD1_1)
671-
#define MOD_SEL7_6 FM(SEL_AVB0_TD2_0) FM(SEL_AVB0_TD2_1)
672-
#define MOD_SEL7_3 FM(SEL_AVB0_TD3_0) FM(SEL_AVB0_TD3_1)
673-
#define MOD_SEL7_2 FM(SEL_AVB0_AVTP_MATCH_0) FM(SEL_AVB0_AVTP_MATCH_1)
674-
#define MOD_SEL7_0 FM(SEL_AVB0_AVTP_PPS_0) FM(SEL_AVB0_AVTP_PPS_1)
675-
676652
/* MOD_SEL8 */ /* 0 */ /* 1 */
677653
#define MOD_SEL8_11 FM(SEL_SDA5_0) FM(SEL_SDA5_1)
678654
#define MOD_SEL8_10 FM(SEL_SCL5_0) FM(SEL_SCL5_1)
@@ -689,23 +665,18 @@ FM(IP0SR8_31_28) IP0SR8_31_28
689665

690666
#define PINMUX_MOD_SELS \
691667
\
692-
MOD_SEL6_18 \
693-
MOD_SEL6_16 MOD_SEL7_16 \
694-
MOD_SEL7_15 \
695-
MOD_SEL6_13 MOD_SEL7_13 \
696-
MOD_SEL6_12 \
697-
MOD_SEL7_11 MOD_SEL8_11 \
698-
MOD_SEL6_10 MOD_SEL7_10 MOD_SEL8_10 \
699-
MOD_SEL8_9 \
700-
MOD_SEL8_8 \
701-
MOD_SEL6_7 MOD_SEL7_7 MOD_SEL8_7 \
702-
MOD_SEL6_6 MOD_SEL7_6 MOD_SEL8_6 \
703-
MOD_SEL6_5 MOD_SEL8_5 \
704-
MOD_SEL8_4 \
705-
MOD_SEL7_3 MOD_SEL8_3 \
706-
MOD_SEL6_2 MOD_SEL7_2 MOD_SEL8_2 \
707-
MOD_SEL6_1 MOD_SEL8_1 \
708-
MOD_SEL7_0 MOD_SEL8_0
668+
MOD_SEL8_11 \
669+
MOD_SEL8_10 \
670+
MOD_SEL8_9 \
671+
MOD_SEL8_8 \
672+
MOD_SEL8_7 \
673+
MOD_SEL8_6 \
674+
MOD_SEL8_5 \
675+
MOD_SEL8_4 \
676+
MOD_SEL8_3 \
677+
MOD_SEL8_2 \
678+
MOD_SEL8_1 \
679+
MOD_SEL8_0
709680

710681
enum {
711682
PINMUX_RESERVED = 0,
@@ -1092,23 +1063,23 @@ static const u16 pinmux_data[] = {
10921063
/* IP0SR6 */
10931064
PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
10941065

1095-
PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1),
1066+
PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
10961067

1097-
PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1),
1068+
PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
10981069

10991070
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
11001071

11011072
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
11021073
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
11031074

1104-
PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1),
1105-
PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0),
1075+
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
1076+
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
11061077

1107-
PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1),
1108-
PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0),
1078+
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
1079+
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
11091080

1110-
PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1),
1111-
PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0),
1081+
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
1082+
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
11121083

11131084
/* IP1SR6 */
11141085
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
@@ -1117,17 +1088,17 @@ static const u16 pinmux_data[] = {
11171088
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
11181089
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
11191090

1120-
PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1),
1121-
PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0),
1091+
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
1092+
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
11221093

11231094
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
11241095
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
11251096

1126-
PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1),
1127-
PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0),
1097+
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
1098+
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
11281099

1129-
PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1),
1130-
PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0),
1100+
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
1101+
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
11311102

11321103
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
11331104
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
@@ -1136,69 +1107,69 @@ static const u16 pinmux_data[] = {
11361107
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
11371108

11381109
/* IP2SR6 */
1139-
PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1),
1140-
PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0),
1110+
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
1111+
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
11411112

11421113
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
11431114
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
11441115

1145-
PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1),
1146-
PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0),
1116+
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
1117+
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
11471118

11481119
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
11491120
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),
11501121

11511122
PINMUX_IPSR_GPSR(IP2SR6_19_16, AVB1_TXCREFCLK),
11521123

11531124
/* IP0SR7 */
1154-
PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_AVTP_PPS, SEL_AVB0_AVTP_PPS_1),
1155-
PINMUX_IPSR_MSEL(IP0SR7_3_0, AVB0_MII_COL, SEL_AVB0_AVTP_PPS_0),
1125+
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_AVTP_PPS),
1126+
PINMUX_IPSR_GPSR(IP0SR7_3_0, AVB0_MII_COL),
11561127

11571128
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_AVTP_CAPTURE),
11581129
PINMUX_IPSR_GPSR(IP0SR7_7_4, AVB0_MII_CRS),
11591130

1160-
PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_AVTP_MATCH, SEL_AVB0_AVTP_MATCH_1),
1161-
PINMUX_IPSR_MSEL(IP0SR7_11_8, AVB0_MII_RX_ER, SEL_AVB0_AVTP_MATCH_0),
1162-
PINMUX_IPSR_MSEL(IP0SR7_11_8, CC5_OSCOUT, SEL_AVB0_AVTP_MATCH_0),
1131+
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_AVTP_MATCH),
1132+
PINMUX_IPSR_GPSR(IP0SR7_11_8, AVB0_MII_RX_ER),
1133+
PINMUX_IPSR_GPSR(IP0SR7_11_8, CC5_OSCOUT),
11631134

1164-
PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_TD3, SEL_AVB0_TD3_1),
1165-
PINMUX_IPSR_MSEL(IP0SR7_15_12, AVB0_MII_TD3, SEL_AVB0_TD3_0),
1135+
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_TD3),
1136+
PINMUX_IPSR_GPSR(IP0SR7_15_12, AVB0_MII_TD3),
11661137

11671138
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_LINK),
11681139
PINMUX_IPSR_GPSR(IP0SR7_19_16, AVB0_MII_TX_ER),
11691140

11701141
PINMUX_IPSR_GPSR(IP0SR7_23_20, AVB0_PHY_INT),
11711142

1172-
PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_TD2, SEL_AVB0_TD2_1),
1173-
PINMUX_IPSR_MSEL(IP0SR7_27_24, AVB0_MII_TD2, SEL_AVB0_TD2_0),
1143+
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_TD2),
1144+
PINMUX_IPSR_GPSR(IP0SR7_27_24, AVB0_MII_TD2),
11741145

1175-
PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_TD1, SEL_AVB0_TD1_1),
1176-
PINMUX_IPSR_MSEL(IP0SR7_31_28, AVB0_MII_TD1, SEL_AVB0_TD1_0),
1146+
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_TD1),
1147+
PINMUX_IPSR_GPSR(IP0SR7_31_28, AVB0_MII_TD1),
11771148

11781149
/* IP1SR7 */
11791150
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_RD3),
11801151
PINMUX_IPSR_GPSR(IP1SR7_3_0, AVB0_MII_RD3),
11811152

11821153
PINMUX_IPSR_GPSR(IP1SR7_7_4, AVB0_TXCREFCLK),
11831154

1184-
PINMUX_IPSR_MSEL(IP1SR7_11_8, AVB0_MAGIC, SEL_AVB0_MAGIC_1),
1155+
PINMUX_IPSR_GPSR(IP1SR7_11_8, AVB0_MAGIC),
11851156

1186-
PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_TD0, SEL_AVB0_TD0_1),
1187-
PINMUX_IPSR_MSEL(IP1SR7_15_12, AVB0_MII_TD0, SEL_AVB0_TD0_0),
1157+
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_TD0),
1158+
PINMUX_IPSR_GPSR(IP1SR7_15_12, AVB0_MII_TD0),
11881159

11891160
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_RD2),
11901161
PINMUX_IPSR_GPSR(IP1SR7_19_16, AVB0_MII_RD2),
11911162

1192-
PINMUX_IPSR_MSEL(IP1SR7_23_20, AVB0_MDC, SEL_AVB0_MDC_1),
1163+
PINMUX_IPSR_GPSR(IP1SR7_23_20, AVB0_MDC),
11931164

11941165
PINMUX_IPSR_GPSR(IP1SR7_27_24, AVB0_MDIO),
11951166

1196-
PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_TXC, SEL_AVB0_TXC_1),
1197-
PINMUX_IPSR_MSEL(IP1SR7_31_28, AVB0_MII_TXC, SEL_AVB0_TXC_0),
1167+
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_TXC),
1168+
PINMUX_IPSR_GPSR(IP1SR7_31_28, AVB0_MII_TXC),
11981169

11991170
/* IP2SR7 */
1200-
PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_TX_CTL, SEL_AVB0_TX_CTL_1),
1201-
PINMUX_IPSR_MSEL(IP2SR7_3_0, AVB0_MII_TX_EN, SEL_AVB0_TX_CTL_0),
1171+
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_TX_CTL),
1172+
PINMUX_IPSR_GPSR(IP2SR7_3_0, AVB0_MII_TX_EN),
12021173

12031174
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_RD1),
12041175
PINMUX_IPSR_GPSR(IP2SR7_7_4, AVB0_MII_RD1),
@@ -3641,50 +3612,6 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
36413612

36423613
#define F_(x, y) x,
36433614
#define FM(x) FN_##x,
3644-
{ PINMUX_CFG_REG_VAR("MOD_SEL6", 0xE6061100, 32,
3645-
GROUP(-13, 1, -1, 1, -2, 1, 1,
3646-
-1, 1, -2, 1, 1, 1, -2, 1, 1, -1),
3647-
GROUP(
3648-
/* RESERVED 31-19 */
3649-
MOD_SEL6_18
3650-
/* RESERVED 17 */
3651-
MOD_SEL6_16
3652-
/* RESERVED 15-14 */
3653-
MOD_SEL6_13
3654-
MOD_SEL6_12
3655-
/* RESERVED 11 */
3656-
MOD_SEL6_10
3657-
/* RESERVED 9-8 */
3658-
MOD_SEL6_7
3659-
MOD_SEL6_6
3660-
MOD_SEL6_5
3661-
/* RESERVED 4-3 */
3662-
MOD_SEL6_2
3663-
MOD_SEL6_1
3664-
/* RESERVED 0 */
3665-
))
3666-
},
3667-
{ PINMUX_CFG_REG_VAR("MOD_SEL7", 0xE6061900, 32,
3668-
GROUP(-15, 1, 1, -1, 1, -1, 1, 1, -2, 1, 1,
3669-
-2, 1, 1, -1, 1),
3670-
GROUP(
3671-
/* RESERVED 31-17 */
3672-
MOD_SEL7_16
3673-
MOD_SEL7_15
3674-
/* RESERVED 14 */
3675-
MOD_SEL7_13
3676-
/* RESERVED 12 */
3677-
MOD_SEL7_11
3678-
MOD_SEL7_10
3679-
/* RESERVED 9-8 */
3680-
MOD_SEL7_7
3681-
MOD_SEL7_6
3682-
/* RESERVED 5-4 */
3683-
MOD_SEL7_3
3684-
MOD_SEL7_2
3685-
/* RESERVED 1 */
3686-
MOD_SEL7_0))
3687-
},
36883615
{ PINMUX_CFG_REG_VAR("MOD_SEL8", 0xE6068100, 32,
36893616
GROUP(-20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1),
36903617
GROUP(

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