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1 | | -linux-nvidia-bos (7.0.0-2006.6) UNRELEASED; urgency=medium |
| 1 | +linux-nvidia-bos (7.0.0-2006.6) resolute; urgency=medium |
2 | 2 |
|
3 | | - CHANGELOG: Do not edit directly. Autogenerated at release. |
4 | | - CHANGELOG: Use the printchanges target to see the current changes. |
5 | | - CHANGELOG: Use the insertchanges target to create the final log. |
| 3 | + * resolute/linux-nvidia-bos: 7.0.0-2006.6 -proposed tracker (LP: #2153497) |
6 | 4 |
|
7 | | - -- Jacob Martin <jacob.martin@canonical.com> Thu, 21 May 2026 15:52:26 -0500 |
| 5 | + * Packaging resync (LP: #1786013) |
| 6 | + - [Packaging] debian.nvidia-bos/dkms-versions -- update from kernel- |
| 7 | + versions (adhoc/d2026.05.20) |
| 8 | + |
| 9 | + * Add CXL Type-2 device support, RAS error handling, reset, state |
| 10 | + save/restore, and interleaving support (LP: #2143032) // CXL: Backport |
| 11 | + Type-2, state save/restore, and reset support (LP: #2153819) |
| 12 | + - NVIDIA: VR: SAUCE: [Config] CXL config annotations for Type-2 device and |
| 13 | + RAS support |
| 14 | + - NVIDIA: VR: SAUCE: [Config] Enable CXL DAX and KMEM built-in for CXL |
| 15 | + memory access |
| 16 | + - NVIDIA: VR: SAUCE: [Config] Add PCI_CXL annotation for CXL state |
| 17 | + save/restore |
| 18 | + - NVIDIA: VR: SAUCE: PCI: Add CXL DVSEC control, lock, and range register |
| 19 | + definitions |
| 20 | + - NVIDIA: VR: SAUCE: cxl: Move HDM decoder and register map definitions to |
| 21 | + include/cxl/cxl.h |
| 22 | + - NVIDIA: VR: SAUCE: PCI: Add virtual extended cap save buffer for CXL |
| 23 | + state |
| 24 | + - NVIDIA: VR: SAUCE: PCI: Add cxl DVSEC state save/restore across resets |
| 25 | + - NVIDIA: VR: SAUCE: PCI: Add HDM decoder state save/restore |
| 26 | + - NVIDIA: VR: SAUCE: PCI: Add CXL DVSEC reset and capability register |
| 27 | + definitions |
| 28 | + - NVIDIA: VR: SAUCE: PCI: Export pci_dev_save_and_disable() and |
| 29 | + pci_dev_restore() |
| 30 | + - NVIDIA: VR: SAUCE: cxl: Add memory offlining and cache flush helpers |
| 31 | + - NVIDIA: VR: SAUCE: cxl: Add multi-function sibling coordination for CXL |
| 32 | + reset |
| 33 | + - NVIDIA: VR: SAUCE: cxl: Add CXL DVSEC reset sequence and flow |
| 34 | + orchestration |
| 35 | + - NVIDIA: VR: SAUCE: cxl: Add cxl_reset sysfs interface for PCI devices |
| 36 | + - NVIDIA: VR: SAUCE: Documentation: ABI: Add CXL PCI cxl_reset sysfs |
| 37 | + attribute |
| 38 | + |
| 39 | + * CXL: Backport Type-2, state save/restore, and reset support (LP: #2153819) |
| 40 | + - cxl: support Type2 when initializing cxl_dev_state |
| 41 | + - cxl: export internal structs for external Type2 drivers |
| 42 | + - cxl: Move pci generic code from cxl_pci to core/cxl_pci |
| 43 | + - cxl/pci: Remove redundant cxl_pci_find_port() call |
| 44 | + - NVIDIA: VR: SAUCE: sfc: add cxl support |
| 45 | + - NVIDIA: VR: SAUCE: cxl/sfc: Map cxl regs |
| 46 | + - NVIDIA: VR: SAUCE: cxl/sfc: Initialize dpa without a mailbox |
| 47 | + - NVIDIA: VR: SAUCE: cxl: Prepare memdev creation for type2 |
| 48 | + - NVIDIA: VR: SAUCE: sfc: create type2 cxl memdev |
| 49 | + - NVIDIA: VR: SAUCE: cxl: attach region to an accelerator/type2 memdev |
| 50 | + - NVIDIA: VR: SAUCE: cxl: Avoid dax creation for accelerators |
| 51 | + - NVIDIA: VR: SAUCE: sfc: support pio mapping based on cxl |
| 52 | + - NVIDIA: VR: SAUCE: dax/hmem: Request cxl_acpi and cxl_pci before walking |
| 53 | + Soft Reserved ranges |
| 54 | + - NVIDIA: VR: SAUCE: dax/hmem: Gate Soft Reserved deferral on DEV_DAX_CXL |
| 55 | + - NVIDIA: VR: SAUCE: cxl/region: Skip decoder reset on detach for |
| 56 | + autodiscovered regions |
| 57 | + - NVIDIA: VR: SAUCE: dax/cxl, hmem: Initialize hmem early and defer |
| 58 | + dax_cxl binding |
| 59 | + - NVIDIA: VR: SAUCE: dax: Track all dax_region allocations under a global |
| 60 | + resource tree |
| 61 | + - NVIDIA: VR: SAUCE: cxl/region: Add helper to check Soft Reserved |
| 62 | + containment by CXL regions |
| 63 | + - NVIDIA: VR: SAUCE: dax: Add deferred-work helpers for dax_hmem and |
| 64 | + dax_cxl coordination |
| 65 | + - NVIDIA: VR: SAUCE: dax/hmem, cxl: Defer and resolve ownership of Soft |
| 66 | + Reserved memory ranges |
| 67 | + - NVIDIA: VR: SAUCE: dax/hmem: Reintroduce Soft Reserved ranges back into |
| 68 | + the iomem tree |
| 69 | + - NVIDIA: VR: SAUCE: cxl/region: Support multi-level interleaving with |
| 70 | + smaller granularities for lower levels |
| 71 | + - NVIDIA: SAUCE: Revert "NVIDIA: VR: SAUCE: cxl: add support for cxl |
| 72 | + reset" |
| 73 | + |
| 74 | + * Installer fails internally with a RSync error due to page fault |
| 75 | + (LP: #2150640) |
| 76 | + - NVIDIA: SAUCE: ovl: keep err zero after successful ovl_cache_get() |
| 77 | + |
| 78 | + * Refresh series: Allow ATS to be always on for certain ATS-capable devices |
| 79 | + (LP: #2150727) |
| 80 | + - Revert "NVIDIA: VR: SAUCE: iommu/arm-smmu-v3: Allow ATS to be always on" |
| 81 | + - Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for non-CXL |
| 82 | + NVIDIA GPUs" |
| 83 | + - Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for CXL.cache |
| 84 | + capable devices" |
| 85 | + - NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for CXL.cache capable |
| 86 | + devices |
| 87 | + - NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for pre-CXL devices |
| 88 | + - NVIDIA: VR: SAUCE: iommu/arm-smmu-v3: Allow ATS to be always on |
| 89 | + |
| 90 | + * Pull CPPC mailing list patches for Spark (LP: #2131705) |
| 91 | + - ACPI: CPPC: Add cppc_get_perf() API to read performance controls |
| 92 | + - ACPI: CPPC: Warn on missing mandatory DESIRED_PERF register |
| 93 | + - ACPI: CPPC: Extend cppc_set_epp_perf() for FFH/SystemMemory |
| 94 | + - cpufreq: CPPC: Update cached perf_ctrls on sysfs write |
| 95 | + - cpufreq: cppc: Update MIN_PERF/MAX_PERF in target callbacks |
| 96 | + - ACPI: CPPC: add APIs and sysfs interface for perf_limited |
| 97 | + - cpufreq: CPPC: Add sysfs documentation for perf_limited |
| 98 | + - ACPI: CPPC: Move reference performance to capabilities |
| 99 | + - ACPI: CPPC: Fix uninitialized ref variable in cppc_get_perf_caps() |
| 100 | + - ACPI: CPPC: Check cpc_read() return values consistently |
| 101 | + - cpufreq: Remove max_freq_req update for pre-existing policy |
| 102 | + - cpufreq: Add boost_freq_req QoS request |
| 103 | + - cpufreq: Allocate QoS freq_req objects with policy |
| 104 | + - cpufreq/amd-pstate: Cache the max frequency in cpudata |
| 105 | + - NVIDIA: SAUCE: cpufreq: Extract cpufreq_policy_init_qos() function |
| 106 | + - NVIDIA: SAUCE: cpufreq: Set default policy->min/max values for all |
| 107 | + drivers |
| 108 | + - NVIDIA: SAUCE: cpufreq: Remove driver default policy->min/max init |
| 109 | + - NVIDIA: SAUCE: cpufreq: Use policy->min/max init as QoS request |
| 110 | + - NVIDIA: SAUCE: cpufreq: CPPC: add autonomous mode boot parameter support |
| 111 | + |
| 112 | + * Backport Vera PMU support (LP: #2149756) |
| 113 | + - Revert "NVIDIA: VR: SAUCE: perf vendor events arm64: Add Tegra410 |
| 114 | + Olympus PMU events" |
| 115 | + - Revert "NVIDIA: VR: SAUCE: perf: add NVIDIA Tegra410 C2C PMU" |
| 116 | + - Revert "NVIDIA: VR: SAUCE: perf: add NVIDIA Tegra410 CPU Memory Latency |
| 117 | + PMU" |
| 118 | + - Revert "NVIDIA: VR: SAUCE: perf/arm_cspmu: nvidia: Add Tegra410 PCIE-TGT |
| 119 | + PMU" |
| 120 | + - Revert "NVIDIA: VR: SAUCE: perf/arm_cspmu: nvidia: Add Tegra410 PCIE |
| 121 | + PMU" |
| 122 | + - Revert "NVIDIA: VR: SAUCE: perf/arm_cspmu: Add arm_cspmu_acpi_dev_get" |
| 123 | + - Revert "NVIDIA: VR: SAUCE: perf/arm_cspmu: nvidia: Add Tegra410 UCF PMU" |
| 124 | + - Revert "NVIDIA: VR: SAUCE: perf/arm_cspmu: nvidia: Rename doc to |
| 125 | + Tegra241" |
| 126 | + - perf/arm_cspmu: nvidia: Rename doc to Tegra241 |
| 127 | + - perf/arm_cspmu: nvidia: Add Tegra410 UCF PMU |
| 128 | + - perf/arm_cspmu: Add arm_cspmu_acpi_dev_get |
| 129 | + - perf/arm_cspmu: nvidia: Add Tegra410 PCIE PMU |
| 130 | + - perf/arm_cspmu: nvidia: Add Tegra410 PCIE-TGT PMU |
| 131 | + - perf: add NVIDIA Tegra410 CPU Memory Latency PMU |
| 132 | + - perf: add NVIDIA Tegra410 C2C PMU |
| 133 | + - perf vendor events arm64: Add Tegra410 Olympus PMU events |
| 134 | + - NVIDIA: VR: SAUCE: perf/arm_pmu: Skip PMCCNTR_EL0 on NVIDIA Olympus |
| 135 | + |
| 136 | + * Backport lan743x driver patches (LP: #2152064) |
| 137 | + - net: microchip: lan743x: add ethtool nway_reset support |
| 138 | + - net: lan743x: fix SGMII detection on PCI1xxxx B0+ during warm reset |
| 139 | + - net: lan743x: rename chip_rev to fpga_rev |
| 140 | + |
| 141 | + * Backport SMT-aware asymmetric CPU capacity idle selection (LP: #2150671) |
| 142 | + - NVIDIA: VR: SAUCE: sched/fair: Attach sched_domain_shared to |
| 143 | + sd_asym_cpucapacity |
| 144 | + - NVIDIA: VR: SAUCE: sched/fair: Prefer fully-idle SMT cores in asym- |
| 145 | + capacity idle selection |
| 146 | + - NVIDIA: VR: SAUCE: sched/fair: Reject misfit pulls onto busy SMT |
| 147 | + siblings on asym-capacity |
| 148 | + - NVIDIA: VR: SAUCE: sched/fair: Add SIS_UTIL support to |
| 149 | + select_idle_capacity() |
| 150 | + |
| 151 | + * Forward-port of the full Arm Live Firmware Activation (LFA) v2 series |
| 152 | + (LP: #2150652) |
| 153 | + - Revert "NVIDIA: VR: SAUCE: firmware: smccc: register as platform driver" |
| 154 | + - Revert "NVIDIA: VR: SAUCE: firmware: smccc: add timeout, touch wdt" |
| 155 | + - Revert "NVIDIA: VR: SAUCE: firmware: smccc: add support for Live |
| 156 | + Firmware Activation (LFA)" |
| 157 | + - NVIDIA: VR: SAUCE: dt-bindings: arm: Add Live Firmware Activation |
| 158 | + binding |
| 159 | + - NVIDIA: VR: SAUCE: firmware: smccc: Add support for Live Firmware |
| 160 | + Activation (LFA) |
| 161 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: Move image rescanning |
| 162 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: Add timeout and trigger |
| 163 | + watchdog |
| 164 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: Register ACPI notification |
| 165 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: Add auto_activate sysfs file |
| 166 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: Register DT interrupt |
| 167 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: introduce SMC access lock |
| 168 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: handle LFA_BUSY in PRIME and |
| 169 | + ACTIVATE |
| 170 | + - NVIDIA: VR: SAUCE: firmware: smccc: lfa: Emit a uevent on inventory |
| 171 | + updates |
| 172 | + |
| 173 | + * Introduce a sharded cache affinity scope (LP: #2150467) |
| 174 | + - workqueue: fix parse_affn_scope() prefix matching bug |
| 175 | + - workqueue: fix typo in WQ_AFFN_SMT comment |
| 176 | + - workqueue: add WQ_AFFN_CACHE_SHARD affinity scope |
| 177 | + - workqueue: set WQ_AFFN_CACHE_SHARD as the default affinity scope |
| 178 | + - tools/workqueue: add CACHE_SHARD support to wq_dump.py |
| 179 | + - workqueue: add test_workqueue benchmark module |
| 180 | + - docs: workqueue: document WQ_AFFN_CACHE_SHARD affinity scope |
| 181 | + - workqueue: avoid unguarded 64-bit division |
| 182 | + - workqueue: validate cpumask_first() result in |
| 183 | + llc_populate_cpu_shard_id() |
| 184 | + - [Config] nvidia: Defaults for CONFIG_TEST_WORKQUEUE |
| 185 | + |
| 186 | + * UBUNTU: [Config] nvidia: Disable default CMA reservation (LP: #2150898) |
| 187 | + - [Config] nvidia: Disable default CMA reservation |
| 188 | + |
| 189 | + * Backport Use device ID range for DGX Spark iGPU (LP: #2150487) |
| 190 | + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Use device ID range for DGX Spark iGPU |
| 191 | + iommu quirk |
| 192 | + |
| 193 | + * Backport NVIDIA: SAUCE: iommu/arm-smmu-v3: Use identity domain for ASPEED |
| 194 | + BMC devices (LP: #2150470) |
| 195 | + - NVIDIA: SAUCE: iommu/arm-smmu-v3: Use identity domain for ASPEED BMC |
| 196 | + devices |
| 197 | + |
| 198 | + * Update GDS/NVMe SAUCE for v6.17 (LP: #2134960) // [linux-nvidia-7.0]: |
| 199 | + Forward-port GDS/NVFS content (LP: #2150289) |
| 200 | + - NVIDIA: SAUCE: Patch NVMe/NVMeoF driver to support GDS on Linux 7.0 |
| 201 | + Kernel |
| 202 | + |
| 203 | + * Backport Set LED_HW_PLUGGABLE for NPEM and fix class init ordering issue |
| 204 | + of CXL/fwctl (LP: #2149918) |
| 205 | + - PCI/NPEM: Set LED_HW_PLUGGABLE for hotplug-capable ports |
| 206 | + - fwctl: Fix class init ordering to avoid NULL pointer dereference on |
| 207 | + device removal |
| 208 | + |
| 209 | + * gpio: tegra186: Simplify GPIO line name prefix and support multi-socket |
| 210 | + devices (LP: #2148664) |
| 211 | + - gpio: tegra186: Simplify GPIO line name prefix handling |
| 212 | + - gpio: tegra186: Support multi-socket devices |
| 213 | + - Revert "NVIDIA: SAUCE: serial: 8250_mtk: Add ACPI support" |
| 214 | + - NVIDIA: SAUCE: MEDIATEK: serial: 8250_mtk: Add ACPI support |
| 215 | + |
| 216 | + * fix r8169 vs r8127 contention for Spark (LP: #2144345) |
| 217 | + - NVIDIA: SAUCE: r8169: remove PCI IDs claimed by r8127 driver |
| 218 | + |
| 219 | + * Backport of the vfio/nvgrace-gpu Blackwell-Next GPU readiness check (v3) |
| 220 | + from LKML to 26.04_linux-nvidia. (LP: #2148701) |
| 221 | + - NVIDIA: SAUCE: vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check |
| 222 | + via CXL DVSEC |
| 223 | + |
| 224 | + [ Ubuntu: 7.0.0-15.15 ] |
| 225 | + |
| 226 | + * resolute/linux: 7.0.0-15.15 -proposed tracker (LP: #2148866) |
| 227 | + * Qualcomm X1E: Speaker overdrive causes hardware protection shutdown |
| 228 | + (LP: #2149808) |
| 229 | + - SAUCE: ASoC: qcom: x1e80100: limit speaker volumes |
| 230 | + * intel-ipu7 / intel-ipu7-isys modules are shipped unsigned in latest |
| 231 | + Resolute kernels, breaking Secure Boot systems (LP: #2148718) |
| 232 | + - [packaging] add intel-ipu7 to signature inclusion list |
| 233 | + |
| 234 | + -- Jacob Martin <jacob.martin@canonical.com> Thu, 21 May 2026 16:29:40 -0500 |
8 | 235 |
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9 | 236 | linux-nvidia-bos (7.0.0-2005.5) resolute; urgency=medium |
10 | 237 |
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