NVIDIA: VR: SAUCE: tegra: bpmp: Add sysfs for memory bandwidth QoS

BugLink: https://bugs.launchpad.net/bugs/2147212

Tegra410 exposes memory bandwidth QoS for PCIe and GPU UPHY traffic on the
path to DRAM. Each bandwidth group can cap PCIe read, PCIe write, or
combined GPU UPHY read and write traffic, with target limits.

The memory bandwidth QoS is not exposed as ordinary host MMIO and
cannot be controlled from the kernel. The bandwidth limits can be programmed
by sending the corresponding requests (MBWT MRQ) to the BPMP.

On Tegra410, an ACPI-based platform, Linux BPMP driver does not use the
device-tree mailbox path for communicating with the BPMP firmware.
As a result, there is no existing client driver or interface that can be
used to send the memory bandwidth requests to the BPMP.

This patch exposes a sysfs directory mbwt_control on the tegra-bpmp platform
device with pcie_instance_id, vc_type, and bandwidth.
Writing bandwidth issues an MBWT_SET for the selected group (pcie_instance_id)
and traffic class (vc_type).
A read issues MBWT_GET and returns the bandwidth value reported by firmware.

These attributes are exposed only if MBWT QUERY probe reports both
MBWT_SET and MBWT_GET commands as supported.

ABI documented in Documentation/ABI/testing/sys-platform-tegra-bpmp

Signed-off-by: Aniruddha Rao <anrao@nvidia.com>

(backported from V4 internal mail <20260423140823.2848045-4-anrao@nvidia.com>)
[kobak: Keep functional MRQ_SOCHUB_MBWT ABI definitions and sysfs
 interface from V4; condense verbose per-field ABI comments while
 preserving enum/struct layout and Documentation/ABI coverage; use
 refcounted kobject allocation for mbwt_control; validate
 pcie_instance_id/vc_type before staging; return only the bandwidth
 value from bandwidth reads; report BPMP SET rejections to userspace;
 fail BPMP probe on mbwt_control sysfs registration failure so 7.0-bos
 does not silently boot without the requested MBWT interface.]

Signed-off-by: Koba Ko <kobak@nvidia.com>
Acked-by: Carol L Soto <csoto@nvidia.com>
Acked-by: Matthew R. Ochs <mochs@nvidia.com>
Signed-off-by: Brad Figg <bfigg@nvidia.com>

Author: kobak2026

Documentation/ABI/testing/sys-platform-tegra-bpmp

@@ -0,0 +1,49 @@
+What:           /sys/bus/platform/devices/<bpmp-device>/mbwt_control/pcie_instance_id
+What:           /sys/bus/platform/devices/<bpmp-device>/mbwt_control/vc_type
+What:           /sys/bus/platform/devices/<bpmp-device>/mbwt_control/bandwidth
+Date:           March 2026
+KernelVersion:  6.18
+Contact:        Aniruddha TVS Rao <anrao@nvidia.com>
+Description:
+               On ACPI-based Tegra systems the BPMP driver does not use the
+               device-tree mailbox path; firmware interaction is via AML. This sysfs
+               interface is a userspace tuning knob for memory bandwidth throttler
+               (MBWT) settings.
+
+               On Tegra410, the PCIe bandwidth control path exposes QoS that caps
+               aggregate bandwidth for PCIe and for GPU traffic over UPHY. Each PCIe
+               bandwidth group has a single shared cap for all traffic in that group.
+               A group may contain only PCIe devices, only a GPU on UPHY, or PCIe and
+               GPU together in a bifurcated topology.
+
+               Following attributes appear under a kobject named mbwt_control on the
+               tegra-bpmp platform device (the same struct device as the driver
+               binds to), only when that device has an ACPI companion and BPMP
+               firmware reports support for both MBWT_GET and MBWT_SET via the MBWT
+               QUERY probe.
+
+               pcie_instance_id (RW):
+                       PCIe bandwidth group index: 0 = pcie0, 1 = pcie1, ..., 5 = pcie5.
+
+               vc_type (RW):
+                       Traffic type to cap for that group:
+                       0 = PCIe read
+                       1 = PCIe write
+                       2 = GPU UPHY read plus write (combined)
+
+               bandwidth (RW):
+                       Target bandwidth cap in GB/s for the pcie_instance_id and vc_type
+                       currently stored in the other two attributes. Intended range is
+                       1-110 GB/s; firmware validates the request (via MRQ MBWT_SET).
+
+                       When read, issues a MBWT_GET for that same pcie_instance_id and vc_type
+                       and returns the bandwidth value in GB/s returned by firmware.
+
+               Example:
+                       echo 0 > .../mbwt_control/pcie_instance_id
+                       echo 1 > .../mbwt_control/vc_type
+                       echo 100 > .../mbwt_control/bandwidth
+                       cat .../mbwt_control/bandwidth
+
+Users:         Customer tuning of PCIe and GPU UPHY bandwidth caps on
+               ACPI-based Tegra410 systems.

drivers/firmware/tegra/Makefile

@@ -7,4 +7,5 @@ tegra-bpmp-$(CONFIG_ARCH_TEGRA_234_SOC)	+= bpmp-tegra186.o
 tegra-bpmp-$(CONFIG_ARCH_TEGRA_264_SOC)	+= bpmp-tegra186.o
 tegra-bpmp-$(CONFIG_DEBUG_FS)	+= bpmp-debugfs.o
 obj-$(CONFIG_TEGRA_BPMP)	+= tegra-bpmp.o
+obj-$(CONFIG_TEGRA_BPMP)       += bpmp-tegra-sysfs.o
 obj-$(CONFIG_TEGRA_IVC)		+= ivc.o