Revert "NVIDIA: VR: SAUCE: PCI: Allow ATS to be always on for CXL.cache capable devices"

BugLink: https://bugs.launchpad.net/bugs/2150727

This reverts commit 967f9fe.

Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>
Acked-by: Jamie Nguyen <jamien@nvidia.com>
Acked-by: Carol L Soto <csoto@nvidia.com>
Acked-by: Matthew R. Ochs <mochs@nvidia.com>
Signed-off-by: Brad Figg <bfigg@nvidia.com>

Author: nirmoy

drivers/pci/ats.c

@@ -205,50 +205,6 @@ int pci_ats_page_aligned(struct pci_dev *pdev)
 	return 0;
 }
 
-/*
- * CXL r4.0, sec 3.2.5.13 Memory Type on CXL.cache notes: to source requests on
- * CXL.cache, devices need to get the Host Physical Address (HPA) from the Host
- * by means of an ATS request on CXL.io.
- *
- * In other world, CXL.cache devices cannot access physical memory without ATS.
- */
-static bool pci_cxl_ats_always_on(struct pci_dev *pdev)
-{
-	int offset;
-	u16 cap;
-
-	offset = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL,
-					   CXL_DVSEC_PCIE_DEVICE);
-	if (!offset)
-		return false;
-
-	pci_read_config_word(pdev, offset + CXL_DVSEC_CAP_OFFSET, &cap);
-	if (cap & CXL_DVSEC_CACHE_CAPABLE)
-		return true;
-
-	return false;
-}
-
-/**
- * pci_ats_always_on - Whether the PCI device requires ATS to be always enabled
- * @pdev: the PCI device
- *
- * Returns true, if the PCI device requires non-PASID ATS function on an IOMMU
- * bypassed configuration.
- */
-bool pci_ats_always_on(struct pci_dev *pdev)
-{
-	if (pci_ats_disabled() || !pci_ats_supported(pdev))
-		return false;
-
-	/* A VF inherits its PF's requirement for ATS function */
-	if (pdev->is_virtfn)
-		pdev = pci_physfn(pdev);
-
-	return pci_cxl_ats_always_on(pdev);
-}
-EXPORT_SYMBOL_GPL(pci_ats_always_on);
-
 #ifdef CONFIG_PCI_PRI
 void pci_pri_init(struct pci_dev *pdev)
 {

include/linux/pci-ats.h

@@ -12,7 +12,6 @@ int pci_prepare_ats(struct pci_dev *dev, int ps);
 void pci_disable_ats(struct pci_dev *dev);
 int pci_ats_queue_depth(struct pci_dev *dev);
 int pci_ats_page_aligned(struct pci_dev *dev);
-bool pci_ats_always_on(struct pci_dev *dev);
 #else /* CONFIG_PCI_ATS */
 static inline bool pci_ats_supported(struct pci_dev *d)
 { return false; }
@@ -25,8 +24,6 @@ static inline int pci_ats_queue_depth(struct pci_dev *d)
 { return -ENODEV; }
 static inline int pci_ats_page_aligned(struct pci_dev *dev)
 { return 0; }
-static inline bool pci_ats_always_on(struct pci_dev *dev)
-{ return false; }
 #endif /* CONFIG_PCI_ATS */
 
 #ifdef CONFIG_PCI_PRI

include/uapi/linux/pci_regs.h

@@ -1412,9 +1412,4 @@
 #define   PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_ID		__GENMASK(15, 8)
 #define   PCI_DVSEC_CXL_REG_LOCATOR_BLOCK_OFF_LOW	__GENMASK(31, 16)
 
-/* CXL 2.0 8.1.3: PCIe DVSEC for CXL Device */
-#define CXL_DVSEC_PCIE_DEVICE				0
-#define   CXL_DVSEC_CAP_OFFSET				0xA
-#define     CXL_DVSEC_CACHE_CAPABLE			BIT(0)
-
 #endif /* LINUX_PCI_REGS_H */