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perf vendor events arm64: Add Tegra410 Olympus PMU events
Add JSON files for NVIDIA Tegra410 Olympus core PMU events. Also updated the common-and-microarch.json. Signed-off-by: Besar Wicaksono <bwicaksono@nvidia.com> Reviewed-by: James Clark <james.clark@linaro.org> Signed-off-by: Namhyung Kim <namhyung@kernel.org> (cherry picked from commit 86ff690) Signed-off-by: Lee Trager <ltrager@nvidia.com> Acked-by: Seth Forshee <sforshee@nvidia.com> Acked-by: Matthew R. Ochs <mochs@nvidia.com> Signed-off-by: Matthew R. Ochs <mochs@nvidia.com>
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‎tools/perf/pmu-events/arch/arm64/common-and-microarch.json‎

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"EventName": "L2D_CACHE_REFILL_PRFM",
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"BriefDescription": "Level 2 data cache refill, software preload"
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},
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{
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"EventCode": "0x8150",
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"EventName": "L3D_CACHE_RW",
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"BriefDescription": "Level 3 data cache demand access."
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},
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{
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"EventCode": "0x8151",
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"EventName": "L3D_CACHE_PRFM",
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"BriefDescription": "Level 3 data cache software prefetch"
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},
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{
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"EventCode": "0x8152",
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"EventName": "L3D_CACHE_MISS",
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"BriefDescription": "Level 3 data cache demand access miss"
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},
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{
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"EventCode": "0x8153",
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"EventName": "L3D_CACHE_REFILL_PRFM",
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"BriefDescription": "Level 3 data cache refill, software prefetch."
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},
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{
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"EventCode": "0x8154",
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"EventName": "L1D_CACHE_HWPRF",
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"EventName": "L2D_CACHE_HWPRF",
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"BriefDescription": "Level 2 data cache hardware prefetch."
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},
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{
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"EventCode": "0x8156",
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"EventName": "L3D_CACHE_HWPRF",
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"BriefDescription": "Level 3 data cache hardware prefetch."
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},
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{
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"EventCode": "0x8158",
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"EventName": "STALL_FRONTEND_MEMBOUND",
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"EventName": "L2D_CACHE_REFILL_HWPRF",
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"BriefDescription": "Level 2 data cache refill, hardware prefetch."
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},
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{
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"EventCode": "0x81BE",
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"EventName": "L3D_CACHE_REFILL_HWPRF",
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"BriefDescription": "Level 3 data cache refill, hardware prefetch."
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},
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{
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"EventCode": "0x81C0",
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"EventName": "L1I_CACHE_HIT_RD",
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"EventName": "L1I_CACHE_HIT_RD_FPRFM",
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"BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by software preload"
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},
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{
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"EventCode": "0x81DC",
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"EventName": "L1D_CACHE_HIT_RW_FPRFM",
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"BriefDescription": "Level 1 data cache demand access first hit, fetched by software prefetch."
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},
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{
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"EventCode": "0x81E0",
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"EventName": "L1I_CACHE_HIT_RD_FHWPRF",
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"BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by hardware prefetcher"
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},
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{
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"EventCode": "0x81EC",
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"EventName": "L1D_CACHE_HIT_RW_FHWPRF",
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"BriefDescription": "Level 1 data cache demand access first hit, fetched by hardware prefetcher."
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},
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{
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"EventCode": "0x81F0",
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"EventName": "L1I_CACHE_HIT_RD_FPRF",
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"BriefDescription": "Level 1 instruction cache demand fetch first hit, fetched by prefetch."
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},
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{
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"EventCode": "0x81FC",
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"EventName": "L1D_CACHE_HIT_RW_FPRF",
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"BriefDescription": "Level 1 data cache demand access first hit, fetched by prefetch."
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},
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{
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"EventCode": "0x8200",
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"EventName": "L1I_CACHE_HIT",
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"EventName": "L1I_LFB_HIT_RD_FPRFM",
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"BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer first hit, recently fetched by software preload"
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},
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{
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"EventCode": "0x825C",
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"EventName": "L1D_LFB_HIT_RW_FPRFM",
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"BriefDescription": "Level 1 data cache demand access line-fill buffer first hit, recently fetched by software prefetch."
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},
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{
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"EventCode": "0x8260",
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"EventName": "L1I_LFB_HIT_RD_FHWPRF",
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"BriefDescription": "Level 1 instruction cache demand fetch line-fill buffer first hit, recently fetched by hardware prefetcher"
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},
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{
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"EventCode": "0x826C",
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"EventName": "L1D_LFB_HIT_RW_FHWPRF",
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"BriefDescription": "Level 1 data cache demand access line-fill buffer first hit, recently fetched by hardware prefetcher."
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},
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{
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"EventCode": "0x827C",
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"EventName": "L1D_LFB_HIT_RW_FPRF",
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"BriefDescription": "Level 1 data cache demand access line-fill buffer first hit, recently fetched by prefetch."
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},
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{
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"EventCode": "0x8280",
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"EventName": "L1I_CACHE_PRF",
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"EventName": "LL_CACHE_REFILL",
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"BriefDescription": "Last level cache refill"
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},
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{
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"EventCode": "0x828E",
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"EventName": "L3D_CACHE_REFILL_PRF",
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"BriefDescription": "Level 3 data cache refill, prefetch."
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},
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{
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"EventCode": "0x8320",
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"EventName": "L1D_CACHE_REFILL_PERCYC",
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"EventName": "FP_FP8_MIN_SPEC",
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"BriefDescription": "Floating-point operation speculatively_executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x8480",
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"EventName": "FP_SP_FIXED_MIN_OPS_SPEC",
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"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is single-precision floating-point."
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},
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{
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"EventCode": "0x8482",
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"EventName": "FP_HP_FIXED_MIN_OPS_SPEC",
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"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is half-precision floating-point."
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},
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{
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"EventCode": "0x8483",
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"EventName": "FP_BF16_FIXED_MIN_OPS_SPEC",
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"EventName": "FP_FP8_FIXED_MIN_OPS_SPEC",
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"BriefDescription": "Non-scalable element arithmetic operations speculatively executed, smallest type is 8-bit floating-point."
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},
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{
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"EventCode": "0x8488",
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"EventName": "FP_SP_SCALE_MIN_OPS_SPEC",
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"BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is single-precision floating-point."
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},
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{
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"EventCode": "0x848A",
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"EventName": "FP_HP_SCALE_MIN_OPS_SPEC",
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"BriefDescription": "Scalable element arithmetic operations speculatively executed, smallest type is half-precision floating-point."
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},
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{
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"EventCode": "0x848B",
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"EventName": "FP_BF16_SCALE_MIN_OPS_SPEC",

‎tools/perf/pmu-events/arch/arm64/mapfile.csv‎

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0x00000000500f0000,v1,ampere/emag,core
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0x00000000c00fac30,v1,ampere/ampereone,core
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0x00000000c00fac40,v1,ampere/ampereonex,core
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0x000000004e0f0100,v1,nvidia/t410,core

‎tools/perf/pmu-events/arch/arm64/nvidia/t410/branch.json‎

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[
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{
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"ArchStdEvent": "BR_MIS_PRED",
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"PublicDescription": "This event counts branches which are speculatively executed and mispredicted."
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},
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{
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"ArchStdEvent": "BR_PRED",
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"PublicDescription": "This event counts all speculatively executed branches."
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},
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{
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"EventCode": "0x017e",
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"EventName": "BR_PRED_BTB_CTX_UPDATE",
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"PublicDescription": "Branch context table update."
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},
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{
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"EventCode": "0x0188",
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"EventName": "BR_MIS_PRED_DIR_RESOLVED",
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"PublicDescription": "Number of branch misprediction due to direction misprediction."
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},
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{
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"EventCode": "0x0189",
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"EventName": "BR_MIS_PRED_DIR_UNCOND_RESOLVED",
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"PublicDescription": "Number of branch misprediction due to direction misprediction for unconditional branches."
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},
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{
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"EventCode": "0x018a",
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"EventName": "BR_MIS_PRED_DIR_UNCOND_DIRECT_RESOLVED",
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"PublicDescription": "Number of branch misprediction due to direction misprediction for unconditional direct branches."
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},
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{
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"EventCode": "0x018b",
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"EventName": "BR_PRED_MULTI_RESOLVED",
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"PublicDescription": "Number of resolved branch which made prediction by polymorphic indirect predictor."
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},
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{
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"EventCode": "0x018c",
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"EventName": "BR_MIS_PRED_MULTI_RESOLVED",
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"PublicDescription": "Number of branch misprediction which made prediction by polymorphic indirect predictor."
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},
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{
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"EventCode": "0x01e4",
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"EventName": "BR_RGN_RECLAIM",
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"PublicDescription": "This event counts the Indirect predictor entries flushed by region reclamation."
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}
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]

‎tools/perf/pmu-events/arch/arm64/nvidia/t410/brbe.json‎

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[
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{
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"ArchStdEvent": "BRB_FILTRATE",
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"PublicDescription": "This event counts each valid branch record captured in the branch record buffer. Branch records that are not captured because they are removed by filtering are not counted."
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}
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]

‎tools/perf/pmu-events/arch/arm64/nvidia/t410/bus.json‎

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[
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{
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"ArchStdEvent": "BUS_ACCESS",
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"PublicDescription": "This event counts the number of data-beat accesses between the CPU and the external bus. This count includes accesses due to read, write, and snoop. Each beat of data is counted individually."
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},
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{
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"ArchStdEvent": "BUS_CYCLES",
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"PublicDescription": "This event counts bus cycles in the CPU. Bus cycles represent a clock cycle in which a transaction could be sent or received on the interface from the CPU to the external bus. Since that interface is driven at the same clock speed as the CPU, this event increments at the rate of CPU clock. Regardless of the WFE/WFI state of the PE, this event increments on each processor clock."
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},
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{
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"ArchStdEvent": "BUS_ACCESS_RD",
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"PublicDescription": "This event counts memory Read transactions seen on the external bus. Each beat of data is counted individually."
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},
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{
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"ArchStdEvent": "BUS_ACCESS_WR",
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"PublicDescription": "This event counts memory Write transactions seen on the external bus. Each beat of data is counted individually."
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},
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{
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"EventCode": "0x0154",
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"EventName": "BUS_REQUEST_REQ",
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"PublicDescription": "Bus request, request."
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},
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{
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"EventCode": "0x0155",
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"EventName": "BUS_REQUEST_RETRY",
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"PublicDescription": "Bus request, retry."
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},
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{
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"EventCode": "0x0198",
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"EventName": "L2_CHI_CBUSY0",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 0."
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},
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{
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"EventCode": "0x0199",
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"EventName": "L2_CHI_CBUSY1",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 1."
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},
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{
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"EventCode": "0x019a",
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"EventName": "L2_CHI_CBUSY2",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 2."
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},
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{
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"EventCode": "0x019b",
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"EventName": "L2_CHI_CBUSY3",
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"PublicDescription": "Number of RXDAT or RXRSP response received width CBusy of 3."
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}
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]

‎tools/perf/pmu-events/arch/arm64/nvidia/t410/exception.json‎

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[
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{
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"ArchStdEvent": "EXC_TAKEN",
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"PublicDescription": "This event counts any taken architecturally visible exceptions such as IRQ, FIQ, SError, and other synchronous exceptions. Exceptions are counted whether or not they are taken locally."
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},
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{
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"ArchStdEvent": "EXC_RETURN",
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"PublicDescription": "This event counts any architecturally executed exception return instructions. For example: AArch64: ERET."
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},
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{
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"ArchStdEvent": "EXC_UNDEF",
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"PublicDescription": "This event counts the number of synchronous exceptions which are taken locally that are due to attempting to execute an instruction that is UNDEFINED.\nAttempting to execute instruction bit patterns that have not been allocated.\nAttempting to execute instructions when they are disabled.\nAttempting to execute instructions at an inappropriate Exception level.\nAttempting to execute an instruction when the value of PSTATE.IL is 1."
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},
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{
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"ArchStdEvent": "EXC_SVC",
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"PublicDescription": "This event counts SVC exceptions taken locally."
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},
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{
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"ArchStdEvent": "EXC_PABORT",
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"PublicDescription": "This event counts synchronous exceptions that are taken locally and caused by Instruction Aborts."
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},
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{
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"ArchStdEvent": "EXC_DABORT",
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"PublicDescription": "This event counts exceptions that are taken locally and are caused by data aborts or SErrors. Conditions that could cause those exceptions are attempting to read or write memory where the MMU generates a fault, attempting to read or write memory with a misaligned address, Interrupts from the nSEI inputs and internally generated SErrors."
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},
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{
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"ArchStdEvent": "EXC_IRQ",
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"PublicDescription": "This event counts IRQ exceptions including the virtual IRQs that are taken locally."
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},
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{
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"ArchStdEvent": "EXC_FIQ",
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"PublicDescription": "This event counts FIQ exceptions including the virtual FIQs that are taken locally."
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},
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{
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"ArchStdEvent": "EXC_SMC",
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"PublicDescription": "This event counts SMC exceptions taken to EL3."
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},
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{
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"ArchStdEvent": "EXC_HVC",
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"PublicDescription": "This event counts HVC exceptions taken to EL2."
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},
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{
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"ArchStdEvent": "EXC_TRAP_PABORT",
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"PublicDescription": "This event counts exceptions which are traps not taken locally and are caused by Instruction Aborts. For example, attempting to execute an instruction with a misaligned PC."
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},
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{
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"ArchStdEvent": "EXC_TRAP_DABORT",
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"PublicDescription": "This event counts exceptions which are traps not taken locally and are caused by Data Aborts or SError Interrupts. Conditions that could cause those exceptions are:\n* Attempting to read or write memory where the MMU generates a fault,\n* Attempting to read or write memory with a misaligned address,\n* Interrupts from the SEI input,\n* Internally generated SErrors."
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},
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{
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"ArchStdEvent": "EXC_TRAP_OTHER",
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"PublicDescription": "This event counts the number of synchronous trap exceptions which are not taken locally and are not SVC, SMC, HVC, Data Aborts, Instruction Aborts, or Interrupts."
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},
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{
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"ArchStdEvent": "EXC_TRAP_IRQ",
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"PublicDescription": "This event counts IRQ exceptions including the virtual IRQs that are not taken locally."
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},
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{
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"ArchStdEvent": "EXC_TRAP_FIQ",
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"PublicDescription": "This event counts FIQs which are not taken locally but taken from EL0, EL1, or EL2 to EL3 (which would be the normal behavior for FIQs when not executing in EL3)."
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}
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]

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