[for 26.04_linux-nvidia-bos]: NVIDIA: SAUCE: vfio/nvgrace-gpu: Add Blackwell-Next GPU readiness check via CXL DVSEC#382
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…ck via CXL DVSEC Add a CXL DVSEC-based readiness check for Blackwell-Next GPUs alongside the existing legacy BAR0 polling path. On probe and after reset, the driver reads the CXL Device DVSEC capability to determine whether the GPU memory is valid. This is checked by polling on the Memory_Active bit based on the Memory_Active_Timeout. Also check if MEM_INFO_VALID is set within 1 second per CXL spec 4.0 Tables 8-13. If not, return error. A static inline wrapper dispatches to the appropriate readiness check based on whether the CXL DVSEC capability is present. Add PCI_DVSEC_CXL_MEM_ACTIVE_TIMEOUT to pci_regs.h for the timeout field encoding. cc: Kevin Tian <kevin.tian@intel.com> Suggested-by: Alex Williamson <alex@shazbot.org> Signed-off-by: Ankit Agrawal <ankita@nvidia.com> (backported from https://lore.kernel.org/all/20260416014504.63067-1-ankita@nvidia.com/) [nirmoy: kept both egm_node (existing EGM SAUCE) and cxl_dvsec in struct to avoid conflict with EGM backport] Signed-off-by: Nirmoy Das <nirmoyd@nvidia.com>
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✅ Patchscan: No Missing FixesAll cherry-picked commits have been checked — no missing upstream fixes found. |
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Verified this matches v3 on LKML.
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Applied: Closing PR. |
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BugLink: https://bugs.launchpad.net/ubuntu/+source/linux-nvidia-7.0/+bug/2148701
Summary
Backport of the vfio/nvgrace-gpu Blackwell-Next (VR) GPU readiness check (v3) from LKML to
26.04_linux-nvidia-bos.Patch: https://lore.kernel.org/all/20260416014504.63067-1-ankita@nvidia.com/
Blackwell-Next (VR) GPUs report device readiness via the CXL DVSEC Range 1 Low register instead of the BAR0 HBM training register used by GB200. Adds runtime detection by checking the presence of the DVSEC register and routes to the new method if present, otherwise falls back to the legacy approach.
Jira: https://jirasw.nvidia.com/browse/DGX-16091
Tested with: GPU passthrough test on Blackwell-Next (VR) hardware.