Skip to content

Commit a1777fd

Browse files
authored
[https://nvbugs/5941242][fix] Fix SigLIP test failure (#12717)
Signed-off-by: tijyojwad <1127155+tijyojwad@users.noreply.github.com>
1 parent 5b475d7 commit a1777fd

2 files changed

Lines changed: 12 additions & 4 deletions

File tree

tests/integration/test_lists/waives.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -290,7 +290,6 @@ unittest/_torch/modules/test_fused_moe.py::test_fused_moe_triton_mxfp4[False-Fal
290290
full:RTXPro6000D/accuracy/test_llm_api_pytorch.py::TestGPTOSS::test_eagle3_4gpus[v2_kv_cache-cutlass-one_model-overlap_scheduler] SKIP (https://nvbugs/5945047)
291291
accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_nvfp4_4gpus[moe_backend=CUTLASS-mtp_nextn=0-pp4-fp8kv=False-attention_dp=False-cuda_graph=False-overlap_scheduler=False-low_precision_combine=False-torch_compile=False] SKIP (https://nvbugs/5945081)
292292
full:RTXPro6000D/accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_nvfp4_4gpus[moe_backend=CUTLASS-mtp_nextn=0-ep4-fp8kv=True-attention_dp=True-cuda_graph=True-overlap_scheduler=True-low_precision_combine=False-torch_compile=False] SKIP (https://nvbugs/5948435)
293-
unittest/_torch/modeling -k "modeling_siglip" SKIP (https://nvbugs/5941242)
294293
accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_bfloat16[mtp_nextn=2-attention_dp=True-cuda_graph=True-overlap_scheduler=True-torch_compile=False-enable_chunked_prefill=False-v2_kv_cache=False] SKIP (https://nvbugs/5955765)
295294
accuracy/test_llm_api_pytorch.py::TestDeepSeekV3Lite::test_no_kv_cache_reuse[quant_dtype=none-mtp_nextn=2-fp8kv=False-attention_dp=True-cuda_graph=True-overlap_scheduler=True] SKIP (https://nvbugs/5955773)
296295
accuracy/test_llm_api_pytorch.py::TestDeepSeekV32::test_fp8_blockscale[baseline_mtp1] SKIP (https://nvbugs/5955792)

tests/unittest/_torch/modeling/test_modeling_siglip.py

Lines changed: 12 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -135,10 +135,19 @@ def test_siglip_vision_allclose_to_hf(self, scenario: Scenario):
135135
attn_metadata=attn_metadata,
136136
)
137137

138-
# Compare all hidden states
138+
# Compare all hidden states.
139+
# TRT-LLM applies post_layernorm to the last encoder hidden state
140+
# (matching production usage), so the last element must be compared
141+
# against HF's post_layernormed last_hidden_state rather than the
142+
# raw hidden_states[-1].
143+
num_states = len(tllm_outputs)
144+
for i in range(num_states):
145+
tllm_hs = tllm_outputs[i]
146+
if i < num_states - 1:
147+
hf_hs = hf_outputs.hidden_states[i]
148+
else:
149+
hf_hs = hf_outputs.last_hidden_state
139150

140-
for i, (hf_hs, tllm_hs) in enumerate(
141-
zip(hf_outputs.hidden_states, tllm_outputs)):
142151
self.assertEqual(hf_hs.shape, tllm_hs.shape,
143152
f"Shape mismatch for hidden state {i}")
144153

0 commit comments

Comments
 (0)