Decap

Name

nf10_decap

Version

v1.00a

Author

Yilong Geng (Stanford University)

Type

pcore (HW)

Location

netfpga-10g/lib/hw/contrib/pcores/nf10_decap_v1_00_a/

Interface Types

AXI4-Stream & AXI4-Lite

Busses

S_AXIS: Slave AXI4-Stream bus, Variable width

M_AXIS: Master AXI4-Stream bus, Variable width

S_AXI: AXI4-Lite configuration register bus

Parameters

C_AXIS_DATA_WIDTH: Data width of the AXI4-Stream bus.

C_AXIS_TUSER_WIDTH: Data width of the TUSER field.

TOTAL_LENGTH_POS: The positon of the Total_Packet_Length field in TUSER.

SRC_PORT_POS: The position of the Source_Port field in TUSER.

DST_PORT_POS: The position of the Destination_Port field in TUSER.

Register map

This module has one 32-bit configuration register. It can be accessed via the base address of this module.

reg[0]: Enable bit of the Decap module.

reg[15:8]: 8-bit bit wise decap_ports field.

reg[23:16]: encap_protocol in the IP "protocol" field. This should be the same as the IP "protocol" field set in the nf10_encap module.

Description

This module is a part of the tunneling Openflow switch data path. This module is the counterpart of nf10_encap. It enables tunneling by stripping an IP header according to the configuration register.