NetFPGA 10G RLDRAM Test

RLDRAM Test

The RLDRAM Test validates the RLDRAMII ICs and the associated FPGA interface on the NetFPGA-10G board. A test sequence is written over the entire RLDRAM address space, read back and compared to a reference. The RLDRAM test results are reported continuously via the NetFPGA-10G's UART.

A Manual providing instructions to run the RLDRAM Test is available here. It is advised that you run both the RLDRAM Test and the Production Test to validate your board before attempting any development. As described in the manual, if the results of either test indicate a problem with your board, you should return it to HiTech Global (HTG) immediately.

Test Implementation

The test exercises the RLDRAM interface with 100% utilization @ 200MHz. The result is reported via the UART.

Reported error codes are to be decoded as follows: (pass = FF5A)

• status[4:0]: interface i1
  • status[4]: calibration passed
  • status[3]: init passed
  • status[2]: still in reset
  • status[1]: so far no bit errors
  • status[0]: bit error detected
• status[9:5]: interface i2
  • status[9]: calibration passed
  • status[8]: init passed
  • status[7]: still in reset
  • status[6]: so far no bit errors
  • status[5]: bit error detected