Hi guys!
I'm trying to integrate the LPM IP core included in SDNet 2018.2 inside a custom design but, on the custom (non-AXI) interface that the LPM exposes, I obtain only Xs whenever I try to lookup something.
Do you have any experience with that?
I'm configuring the core through the AXI Sim Transactor with the same configuration commands you find inside the p4-->NetFPGA project. I attach screenshots.
Hi guys!
I'm trying to integrate the LPM IP core included in SDNet 2018.2 inside a custom design but, on the custom (non-AXI) interface that the LPM exposes, I obtain only Xs whenever I try to lookup something.
Do you have any experience with that?
I'm configuring the core through the AXI Sim Transactor with the same configuration commands you find inside the p4-->NetFPGA project. I attach screenshots.