NMSIS/Core: add new __s_switch_mode API in core_feature_base.h

Signed-off-by: Huaqi Fang <578567190@qq.com>

Author: fanghuaqi

NMSIS/Core/Include/core_feature_base.h

@@ -897,6 +897,36 @@ __STATIC_INLINE void __switch_mode(uint8_t mode, uintptr_t stack, void(*entry_po
     __ASM volatile("mret");
 }
 
+/**
+ * \brief switch privilege from supervisor mode to others.
+ * \details
+ *  Execute into \ref entry_point in \ref mode(user) with given stack
+ * \param mode   privilege mode
+ * \param stack   predefined stack, size should set enough
+ * \param entry_point   a function pointer to execute
+ */
+__STATIC_INLINE void __s_switch_mode(uint8_t mode, uintptr_t stack, void(*entry_point)(void))
+{
+    unsigned long val = 0;
+
+    /* Set SPP to the requested privilege mode */
+    val = __RV_CSR_READ(CSR_SSTATUS);
+    val = __RV_INSERT_FIELD(val, SSTATUS_SPP, mode);
+
+    /* Set previous SIE disabled */
+    val = __RV_INSERT_FIELD(val, SSTATUS_SPIE, 0);
+
+    __RV_CSR_WRITE(CSR_SSTATUS, val);
+
+    /* Set the entry point in SEPC */
+    __RV_CSR_WRITE(CSR_SEPC, (unsigned long)entry_point);
+
+    /* Set the register file */
+    __ASM volatile("mv sp, %0" ::"r"(stack));
+
+    __ASM volatile("sret");
+}
+
 /**
  * \brief   Enable IRQ Interrupts
  * \details Enables IRQ interrupts by setting the MIE-bit in the MSTATUS Register.

NMSIS/Core/Include/core_feature_pmp.h

@@ -64,7 +64,7 @@ typedef struct PMP_CONFIG {
     /**
      * Size of memory region as power of 2, it has to be minimum 2 and maxium \ref __RISCV_XLEN according to the
      * hard-wired granularity 2^N bytes, if N = 12, then order has to be at least 12; if not, the order read out
-     * is N though you configure less than N.
+     * is N though you configure less than N. Generally, Nuclei CPU's pmp granularity is 2^12 = 4KBytes, you should refer to the databook.
      */
     unsigned long order;
     /**

NMSIS/Core/Include/core_feature_spmp.h

@@ -70,7 +70,7 @@ typedef struct SPMP_CONFIG {
     /**
      * Size of memory region as power of 2, it has to be minimum 2 and maxium \ref __RISCV_XLEN according to the
      * hardwired granularity 2^N bytes, if N = 12, then order has to be at least 12; if not, the order read out
-     * is N though you configure less than N.
+     * is N though you configure less than N. Generally, Nuclei CPU's smpu granularity is 2^12 = 4KBytes, you should refer to the databook.
      */
     unsigned long order;
     /**