NMSIS/Core: fix bugs and typos in core headers, update changelog

- Add boundary check in __CTZ for data == 0 to prevent infinite loop
- Fix __ECLIC_SetModeIRQ using wrong register (ECLIC->SCTRL to ECLIC->CTRL)
- Fix DisableSUCCM SMPCC bitmask clearing logic
- Fix ECC_IsTLBSupportECC incorrect PLIC dependency
- Fix TLB ECC error check using wrong RAM ID mask (DLM to TLB)
- Fix ECC typos (Maintainence, suppported)
- Add __ECLIC_VER macro with default value 1
- Fix CSR field comment typos (accesse, privilede, fisrt, nestting)
- Fix ssnpm field comment in core_feature_iinfo.h
- Improve PLIC memory map documentation and fix PLIC_SetThreshold macro
- Fix indentation of #include in nmsis_core.h
- Update changelog.rst with new V1.6.0 Core entries

Author: fanghuaqi

NMSIS/Core/Include/core_compatiable.h

@@ -258,6 +258,10 @@ __STATIC_INLINE unsigned long __CTZ(unsigned long data)
 {
     unsigned long ret = 0;
 
+    if (data == 0) {
+        return __RISCV_XLEN;
+    }
+
     while (!(data & 1UL)) {
         ret++;
         data = data >> 1;

NMSIS/Core/Include/core_feature_base.h

@@ -117,11 +117,11 @@ typedef union {
         rv_csr_t mie:1;                         /*!< bit: 3  machine mode interrupt enable flag */
         rv_csr_t _reserved2:1;                  /*!< bit: 4  Reserved */
         rv_csr_t spie:1;                        /*!< bit: 5  supervisor mode interrupt enable flag */
-        rv_csr_t ube:1;                         /*!< bit: 6  U-mode non-instruction-fetch memory accesse big-endian enable flag */
+        rv_csr_t ube:1;                         /*!< bit: 6  U-mode non-instruction-fetch memory access big-endian enable flag */
         rv_csr_t mpie:1;                        /*!< bit: 7  machine mode previous interrupt enable flag */
-        rv_csr_t spp:1;                         /*!< bit: 8  supervisor previous privilede mode */
+        rv_csr_t spp:1;                         /*!< bit: 8  supervisor previous privilege mode */
         rv_csr_t vs:2;                          /*!< bit: 9..10  vector status flag */
-        rv_csr_t mpp:2;                         /*!< bit: 11..12 machine previous privilede mode  */
+        rv_csr_t mpp:2;                         /*!< bit: 11..12 machine previous privilege mode  */
         rv_csr_t fs:2;                          /*!< bit: 13..14 FS status flag */
         rv_csr_t xs:2;                          /*!< bit: 15..16 XS status flag */
         rv_csr_t mprv:1;                        /*!< bit: 17 Modify PRiVilege */
@@ -136,8 +136,8 @@ typedef union {
         rv_csr_t _reserved3:7;                  /*!< bit: 25..31 Reserved  */
         rv_csr_t uxl:2;                         /*!< bit: 32..33 U-mode XLEN  */
         rv_csr_t sxl:2;                         /*!< bit: 34..35 S-mode XLEN  */
-        rv_csr_t sbe:1;                         /*!< bit: 36 S-mode non-instruction-fetch memory accesse big-endian enable flag */
-        rv_csr_t mbe:1;                         /*!< bit: 37 M-mode non-instruction-fetch memory accesse big-endian enable flag */
+        rv_csr_t sbe:1;                         /*!< bit: 36 S-mode non-instruction-fetch memory access big-endian enable flag */
+        rv_csr_t mbe:1;                         /*!< bit: 37 M-mode non-instruction-fetch memory access big-endian enable flag */
         rv_csr_t gva:1;                         /*!< bit: 38 Guest Virtual Address */
         rv_csr_t mpv:1;                         /*!< bit: 39 Machine Previous Virtualization Mode */
         rv_csr_t _reserved4:1;                  /*!< bit: 40 Reserved  */
@@ -160,8 +160,8 @@ typedef union {
 typedef union {
     struct {
         rv_csr_t _reserved0:4;                  /*!< bit: 0..3  Reserved */
-        rv_csr_t sbe:1;                         /*!< bit: 4 S-mode non-instruction-fetch memory accesse big-endian enable flag */
-        rv_csr_t mbe:1;                         /*!< bit: 5 M-mode non-instruction-fetch memory accesse big-endian enable flag */
+        rv_csr_t sbe:1;                         /*!< bit: 4 S-mode non-instruction-fetch memory access big-endian enable flag */
+        rv_csr_t mbe:1;                         /*!< bit: 5 M-mode non-instruction-fetch memory access big-endian enable flag */
         rv_csr_t gva:1;                         /*!< bit: 6 Guest Virtual Address */
         rv_csr_t mpv:1;                         /*!< bit: 7 Machine Previous Virtualization Mode */
         rv_csr_t _reserved1:1;                  /*!< bit: 8 Reserved  */
@@ -337,14 +337,14 @@ typedef CSR_MCACHECTL_Type CSR_MCACHE_CTL_Type;
  */
 typedef union {
     struct {
-        rv_csr_t mpie1:1;                       /*!< bit: 0     interrupt enable flag of fisrt level NMI/exception nestting */
-        rv_csr_t mpp1:2;                        /*!< bit: 1..2  privilede mode of fisrt level NMI/exception nestting */
+        rv_csr_t mpie1:1;                       /*!< bit: 0     interrupt enable flag of first level NMI/exception nesting */
+        rv_csr_t mpp1:2;                        /*!< bit: 1..2  privilede mode of first level NMI/exception nesting */
         rv_csr_t _reserved0:3;                  /*!< bit: 3..5  Reserved */
-        rv_csr_t ptyp1:2;                       /*!< bit: 6..7  NMI/exception type of before first nestting */
-        rv_csr_t mpie2:1;                       /*!< bit: 8     interrupt enable flag of second level NMI/exception nestting */
-        rv_csr_t mpp2:2;                        /*!< bit: 9..10 privilede mode of second level NMI/exception nestting */
+        rv_csr_t ptyp1:2;                       /*!< bit: 6..7  NMI/exception type of before first nesting */
+        rv_csr_t mpie2:1;                       /*!< bit: 8     interrupt enable flag of second level NMI/exception nesting */
+        rv_csr_t mpp2:2;                        /*!< bit: 9..10 privilede mode of second level NMI/exception nesting */
         rv_csr_t _reserved1:3;                  /*!< bit: 11..13     Reserved */
-        rv_csr_t ptyp2:2;                       /*!< bit: 14..15     NMI/exception type of before second nestting */
+        rv_csr_t ptyp2:2;                       /*!< bit: 14..15     NMI/exception type of before second nesting */
         rv_csr_t _reserved2:__RISCV_XLEN-16;    /*!< bit: 16..XLEN-1 Reserved */
     } b;                                        /*!< Structure used for bit  access */
     rv_csr_t w;                                 /*!< Type      used for csr data access */

NMSIS/Core/Include/core_feature_cache.h

@@ -220,8 +220,7 @@ __STATIC_FORCEINLINE void DisableSUCCM(void)
 {
     __RV_CSR_CLEAR(CSR_CCM_SUEN, CCM_SUEN_SUEN_Msk);
 #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1)
-    SMPCC_CMD->CC_CTRL &= ~_VAL2FLD(SMPCC_CMD_CTRL_SUP_EN, SMPCC_CMD_CTRL_SUP_EN_DISABLE) &
-                          ~_VAL2FLD(SMPCC_CMD_CTRL_USE_EN, SMPCC_CMD_CTRL_USE_EN_DISABLE);
+    SMPCC_CMD->CC_CTRL &= ~(SMPCC_CMD_CTRL_SUP_EN_Msk | SMPCC_CMD_CTRL_USE_EN_Msk); /* Clear SUP_EN and USE_EN bits */
 #endif /* #if defined(__SMPCC_PRESENT) && (__SMPCC_PRESENT == 1) */
 }
 

NMSIS/Core/Include/core_feature_ecc.h

@@ -31,7 +31,7 @@
  * 3. __DCACHE_PRESENT:  Define whether D-Cache Unit is present or not.
  *   * 0: Not present
  *   * 1: Present
- * 4. __CCM_PRESENT:  Define whether Nuclei Cache Control and Maintainence(CCM) Unit is present or not.
+ * 4. __CCM_PRESENT:  Define whether Nuclei Cache Control and Maintenance(CCM) Unit is present or not.
  *   * 0: Not present
  *   * 1: Present
  *
@@ -110,18 +110,14 @@ __STATIC_FORCEINLINE int32_t ECC_IsDCacheSupportECC(void)
 /**
  * \brief  Check if TLB supports ECC
  * \details
- * This function checks if both PLIC and TLB ECC are supported in the core.
- * Note: TLB is only present with MMU, and when PLIC is present, MMU will be present.
+ * This function checks if TLB ECC is supported in the core.
  * \return 1 if TLB supports ECC, 0 otherwise
  */
 __STATIC_FORCEINLINE int32_t ECC_IsTLBSupportECC(void)
 {
-    CSR_MCFGINFO_Type mcfginfo;
     CSR_MTLBCFGINFO_Type mtlbcfginfo;
-    mcfginfo.d = __RV_CSR_READ(CSR_MCFG_INFO);
     mtlbcfginfo.d = __RV_CSR_READ(CSR_MTLBCFG_INFO);
-    /* TLB only present with MMU, when PLIC present MMU will present */
-    return mcfginfo.b.plic && mtlbcfginfo.b.ecc;
+    return mtlbcfginfo.b.ecc;
 }
 
 /**
@@ -157,7 +153,7 @@ __STATIC_FORCEINLINE int32_t ECC_IsDLMSupportECC(void)
 /**
  * \brief  Check if XOR error injection mode is supported
  * \details
- * This function reads the machine ECC code CSR and checks if error injection mode is suppported.
+ * This function reads the machine ECC code CSR and checks if error injection mode is supported.
  * \return 1 if XOR error injection mode is enabled, 0 otherwise
  */
 __STATIC_FORCEINLINE int32_t ECC_IsXorErrorInjectMode(void)
@@ -707,7 +703,7 @@ __STATIC_FORCEINLINE int32_t ECC_IsTLBSingleBitErrorOccured(void)
 {
     CSR_MECC_CODE_Type mecc_code;
     mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
-    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_DLM;
+    return mecc_code.b.sramid & ECC_ERROR_RAMID_MASK_TLB;
 }
 
 /**
@@ -851,7 +847,7 @@ __STATIC_FORCEINLINE int32_t ECC_IsTLBDoubleBitErrorOccured(void)
 {
     CSR_MECC_CODE_Type mecc_code;
     mecc_code.d = __RV_CSR_READ(CSR_MECC_CODE);
-    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_DLM;
+    return mecc_code.b.ramid & ECC_ERROR_RAMID_MASK_TLB;
 }
 
 /**

NMSIS/Core/Include/core_feature_eclic.h

@@ -33,6 +33,9 @@
  * 5. __SMODE_PRESENT:  Define whether S-Mode present, if present, ECLIC will present with S-Mode ECLIC feature
  *   * 0: Not present
  *   * 1: Present
+ * 6. __ECLIC_VER:  Optional, define the ECLIC version, if not defined, defaults to 1
+ *   * 1: ECLICv1 (default)
+ *   * 2: ECLICv2 (supports hardware context saving and shadow registers)
  *
  */
 #ifdef __cplusplus
@@ -174,6 +177,11 @@ typedef enum ECLIC_TRIGGER {
 #define __ECLIC_INTCTLBITS                  (__ECLIC_GetInfoCtlbits())
 #endif
 
+#ifndef __ECLIC_VER
+/* Define __ECLIC_VER to 1 if not defined, assume ECLICv1 by default */
+#define __ECLIC_VER                         1U
+#endif
+
 /* ECLIC Memory mapping of Device */
 #define ECLIC_BASE                          __ECLIC_BASEADDR                            /*!< ECLIC Base Address */
 #define ECLIC                               ((CLIC_Type *) ECLIC_BASE)                  /*!< CLIC configuration struct */

NMSIS/Core/Include/core_feature_iinfo.h

@@ -121,7 +121,7 @@ typedef union {
         __IM uint32_t smcdeleg:1;                   /*!< bit: 9 support Smcdeleg extension */
         __IM uint32_t smmpm:1;                      /*!< bit: 10 support Smmpm extension */
         __IM uint32_t smnpm:1;                      /*!< bit: 11 support Smnpm extension */
-        __IM uint32_t ssnpm:1;                      /*!< bit: 12 support Smnpm extension */
+        __IM uint32_t ssnpm:1;                      /*!< bit: 12 support Ssnpm extension */
         __IM uint32_t smstateen:1;                  /*!< bit: 13 support Smstateen extension */
         __IM uint32_t sstateen:1;                   /*!< bit: 14 support Sstateen extension */
         __IM uint32_t smcsrind:1;                   /*!< bit: 15 support Smcsrind extension */

NMSIS/Core/Include/core_feature_plic.h

@@ -45,21 +45,72 @@
  * @{
  */
 
-/* 32 bits per source */
+/*
+ * PLIC Memory Map (per RISC-V PLIC spec):
+ *
+ *  Interrupt Source Priority (per-source, not per-context):
+ *    base + 0x000000: Source 0 (reserved, not exist)
+ *    base + 0x000004: Source 1 priority
+ *    ...
+ *    base + 0x000FFC: Source 1023 priority
+ *    addr = base + source * 4
+ *
+ *  Interrupt Pending Bits (per-source, not per-context):
+ *    base + 0x001000: Source 0-31 pending
+ *    base + 0x001004: Source 32-63 pending
+ *    ...
+ *    addr = base + 0x1000 + (source / 32) * 4
+ *
+ *  Interrupt Enable Bits (per-context, 0x80 bytes each):
+ *    base + 0x002000: Context 0, Source 0-31 enable
+ *    base + 0x002080: Context 1, Source 0-31 enable
+ *    ...
+ *    addr = base + 0x2000 + ctxid * 0x80 + (source / 32) * 4
+ *
+ *  Priority Threshold (per-context, 0x1000 bytes each):
+ *    base + 0x200000: Context 0 threshold
+ *    base + 0x201000: Context 1 threshold
+ *    ...
+ *    addr = base + 0x200000 + ctxid * 0x1000
+ *
+ *  Claim / Complete (per-context, same 4K block as threshold):
+ *    base + 0x200004: Context 0 claim/complete
+ *    base + 0x201004: Context 1 claim/complete
+ *    ...
+ *    addr = base + 0x200004 + ctxid * 0x1000
+ *    Claim: read returns highest-priority pending interrupt ID
+ *    Complete: write interrupt ID to signal handler completion
+ *
+ *  Context ID to Hart/Mode mapping (Nuclei RISC-V CPU, not in PLIC spec):
+ *    M-mode context ID = hartid * 2     (even: 0, 2, 4, 6, 8)
+ *    S-mode context ID = hartid * 2 + 1 (odd:  1, 3, 5, 7, 9)
+ *
+ *    Hart 0: M=ctxid 0, S=ctxid 1
+ *    Hart 1: M=ctxid 2, S=ctxid 3
+ *    Hart 2: M=ctxid 4, S=ctxid 5
+ *    Hart 3: M=ctxid 6, S=ctxid 7
+ *    Hart 4: M=ctxid 8, S=ctxid 9
+ *
+ * Reference: https://github.com/riscv/riscv-plic-spec
+ */
+
+/* Priority: 32 bits per source, addr = base + source * 4 */
 #define PLIC_PRIORITY_OFFSET                _AC(0x0000,UL)      /*!< PLIC Priority register offset */
-#define PLIC_PRIORITY_SHIFT_PER_SOURCE      2                   /*!< PLIC Priority register offset shift per source */
-/* 1 bit per source (1 address) */
+#define PLIC_PRIORITY_SHIFT_PER_SOURCE      2                   /*!< log2(4), shift per source */
+
+/* Pending: 1 bit per source, packed 32 per 32-bit register */
 #define PLIC_PENDING_OFFSET                 _AC(0x1000,UL)      /*!< PLIC Pending register offset */
-#define PLIC_PENDING_SHIFT_PER_SOURCE       0                   /*!< PLIC Pending register offset shift per source */
+#define PLIC_PENDING_SHIFT_PER_SOURCE       0                   /*!< bit index within word */
 
-/* 0x80 per context */
+/* Enable: 0x80 (128) bytes per context, packed 32 sources per 32-bit word */
 #define PLIC_ENABLE_OFFSET                  _AC(0x2000,UL)      /*!< PLIC Enable register offset */
-#define PLIC_ENABLE_SHIFT_PER_CONTEXT       7                   /*!< PLIC Enable register offset shift per context */
+#define PLIC_ENABLE_SHIFT_PER_CONTEXT       7                   /*!< log2(0x80), shift per context */
 
+/* Threshold: 0x1000 (4096) bytes per context */
 #define PLIC_THRESHOLD_OFFSET               _AC(0x200000,UL)    /*!< PLIC Threshold register offset */
-#define PLIC_CLAIM_OFFSET                   _AC(0x200004,UL)    /*!< PLIC Claim register offset */
-#define PLIC_THRESHOLD_SHIFT_PER_CONTEXT    12                  /*!< PLIC Threshold register offset shift per context */
-#define PLIC_CLAIM_SHIFT_PER_CONTEXT        12                  /*!< PLIC Claim register offset shift per context */
+#define PLIC_CLAIM_OFFSET                   _AC(0x200004,UL)    /*!< PLIC Claim/Complete register offset */
+#define PLIC_THRESHOLD_SHIFT_PER_CONTEXT    12                  /*!< log2(0x1000), shift per context */
+#define PLIC_CLAIM_SHIFT_PER_CONTEXT        12                  /*!< log2(0x1000), shift per context */
 
 #ifndef __PLIC_BASEADDR
 /* Base address of PLIC(__PLIC_BASEADDR) should be defined in <Device.h> */
@@ -84,8 +135,14 @@
 #define PLIC_GetHartID_S()                  (__PLIC_HARTID)
 #endif
 
+/*
+ * Context ID mapping (Nuclei RISC-V CPU convention):
+ *   M-mode: ctxid = hartid * 2   (even: 0, 2, 4, 6, 8)
+ *   S-mode: ctxid = hartid * 2 + 1 (odd:  1, 3, 5, 7, 9)
+ * This is NOT part of the RISC-V PLIC spec.
+ */
 #define PLIC_GetHartMContextID()            (PLIC_GetHartID() << 1)
-// TODO SMODE HARTID need to handle, maybe use a predefined variable of hartid
+// TODO SMODE HARTID need to handle, maybe use CSR shartid defined by Nuclei RISC-V CPU
 #define PLIC_GetHartSContextID()            ((PLIC_GetHartID_S() << 1) + 1)
 
 #define PLIC_PRIORITY_REGADDR(source)       ((PLIC_BASE) + (PLIC_PRIORITY_OFFSET)  + ((source) << PLIC_PRIORITY_SHIFT_PER_SOURCE))
@@ -317,8 +374,7 @@ __STATIC_FORCEINLINE uint32_t PLIC_ClaimContextInterrupt(uint32_t ctxid)
  * \details
  * This function complete interrupt for plic for selected context.
  * \param [in]    ctxid     selected context id
- * \return  the ID of the highest priority pending interrupt or
- *      zero if there is no pending interrupt
+ * \param [in]    source    interrupt source ID to complete
  * \remarks
  * The PLIC signals it has completed executing an interrupt handler by writing
  * the interrupt ID it received from the claim to the claim/complete register.
@@ -380,8 +436,8 @@ __STATIC_INLINE void PLIC_Context_Init(uint32_t ctxid, uint32_t num_sources, uin
 #define PLIC_DisableInterrupt(source)                   PLIC_DisableContextInterrupt(PLIC_GetHartMContextID(), (source))
 #define PLIC_DisableInterrupt_S(source)                 PLIC_DisableContextInterrupt(PLIC_GetHartSContextID(), (source))
 
-#define PLIC_SetThreshold(source, thresh)               PLIC_SetContextThreshold(PLIC_GetHartMContextID(), (source), (thresh))
-#define PLIC_SetThreshold_S(source, thresh)             PLIC_SetContextThreshold(PLIC_GetHartSContextID(), (source), (thresh))
+#define PLIC_SetThreshold(thresh)                       PLIC_SetContextThreshold(PLIC_GetHartMContextID(), (thresh))
+#define PLIC_SetThreshold_S(thresh)                     PLIC_SetContextThreshold(PLIC_GetHartSContextID(), (thresh))
 
 #define PLIC_GetThreshold()                             PLIC_GetContextThreshold(PLIC_GetHartMContextID())
 #define PLIC_GetThreshold_S()                           PLIC_GetContextThreshold(PLIC_GetHartSContextID())

NMSIS/Core/Include/nmsis_core.h

@@ -88,7 +88,7 @@
 /* Include core pmp feature header file */
 #include "core_feature_pmp.h"
 /* Include core spmp feature header file */
- #include "core_feature_spmp.h"
+#include "core_feature_spmp.h"
 /* Include core cache feature header file */
 #include "core_feature_cache.h"
 /* Include core cidu feature header file */

NMSIS/doc/source/changelog.rst

@@ -39,6 +39,16 @@ This is the version of ``V1.6.0`` release.
   - Add precise ECC injection support in ``core_feature_iinfo.h``: new ``IINFO_ECC_INJ_WAY_Type`` union, ``IINFO_IsPreciseECCInjSupported()`` and ``IINFO_SetPreciseECCInjWay()`` APIs
   - Extend ``core_feature_smpcc.h`` with new SMPCC register types (``CC_INV_RANGE_Type``, ``CC_ECC_INJ_WAY_Type``, ``CC_ECC_INJ_ADDR_Type``, ``CC_ECC_INJ_DATA_Type``, ``IOCP_ATTR_RMP_Type``), new ``SMPCC_ClearBusErrPending()`` API, and update ``SMPCC_CCacheTramErrInject()`` / ``SMPCC_CCacheDramErrInject()`` to support precise ECC injection with an additional ``way`` parameter
   - Fix instruction descriptions in ``core_feature_dsp.h``
+  - Add boundary check in ``__CTZ`` in ``core_compatiable.h`` to return ``__RISCV_XLEN`` when input is 0, preventing an infinite loop
+  - Fix typos in CSR field comments in ``core_feature_base.h``: ``accesse`` to ``access``, ``privilede`` to ``privilege``, ``fisrt`` to ``first``, ``nestting`` to ``nesting``
+  - Fix ``DisableSUCCM`` in ``core_feature_cache.h`` to use direct bitmask clearing (``SMPCC_CMD_CTRL_SUP_EN_Msk | SMPCC_CMD_CTRL_USE_EN_Msk``) instead of incorrect ``_VAL2FLD`` approach
+  - Fix ``ECC_IsTLBSupportECC`` in ``core_feature_ecc.h`` to remove incorrect PLIC dependency, now directly checks ``mtlbcfginfo.b.ecc``
+  - Fix ``ECC_IsTLBSingleBitErrorOccured`` and ``ECC_IsTLBDoubleBitErrorOccured`` in ``core_feature_ecc.h`` to use ``ECC_ERROR_RAMID_MASK_TLB`` instead of ``ECC_ERROR_RAMID_MASK_DLM``
+  - Fix typos in ``core_feature_ecc.h``: ``Maintainence`` to ``Maintenance``, ``suppported`` to ``supported``
+  - Add ``__ECLIC_VER`` macro in ``core_feature_eclic.h`` with default value of 1 for ECLIC version identification
+  - Fix ``ssnpm`` field comment in ``core_feature_iinfo.h`` to correctly reference ``Ssnpm`` extension instead of ``Smnpm``
+  - Improve PLIC memory map documentation and fix ``PLIC_SetThreshold`` macro signature (removed incorrect ``source`` parameter) and ``PLIC_CompleteContextInterrupt`` parameter description in ``core_feature_plic.h``
+  - Fix indentation of ``#include "core_feature_spmp.h"`` in ``nmsis_core.h``
 
 * **NMSIS-DSP**