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NMSIS/Core: Use 1UL for logical left shift
Signed-off-by: Huaqi Fang <578567190@qq.com>
1 parent d4ec791 commit f2d5cc6

6 files changed

Lines changed: 27 additions & 27 deletions

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‎NMSIS/Core/Include/core_feature_base.h‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -881,7 +881,7 @@ __STATIC_FORCEINLINE void __disable_sw_irq(void)
881881
*/
882882
__STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)
883883
{
884-
__RV_CSR_CLEAR(CSR_MIE, 1 << irq);
884+
__RV_CSR_CLEAR(CSR_MIE, 1UL << irq);
885885
}
886886

887887
/**
@@ -892,7 +892,7 @@ __STATIC_FORCEINLINE void __disable_core_irq(uint32_t irq)
892892
*/
893893
__STATIC_FORCEINLINE void __enable_core_irq(uint32_t irq)
894894
{
895-
__RV_CSR_SET(CSR_MIE, 1 << irq);
895+
__RV_CSR_SET(CSR_MIE, 1UL << irq);
896896
}
897897

898898
/**
@@ -914,7 +914,7 @@ __STATIC_FORCEINLINE uint32_t __get_core_irq_pending(uint32_t irq)
914914
*/
915915
__STATIC_FORCEINLINE void __clear_core_irq_pending(uint32_t irq)
916916
{
917-
__RV_CSR_CLEAR(CSR_MIP, 1 << irq);
917+
__RV_CSR_CLEAR(CSR_MIP, 1UL << irq);
918918
}
919919

920920
/**
@@ -1013,7 +1013,7 @@ __STATIC_FORCEINLINE void __disable_sw_irq_s(void)
10131013
*/
10141014
__STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)
10151015
{
1016-
__RV_CSR_CLEAR(CSR_SIE, 1 << irq);
1016+
__RV_CSR_CLEAR(CSR_SIE, 1UL << irq);
10171017
}
10181018

10191019
/**
@@ -1024,7 +1024,7 @@ __STATIC_FORCEINLINE void __disable_core_irq_s(uint32_t irq)
10241024
*/
10251025
__STATIC_FORCEINLINE void __enable_core_irq_s(uint32_t irq)
10261026
{
1027-
__RV_CSR_SET(CSR_SIE, 1 << irq);
1027+
__RV_CSR_SET(CSR_SIE, 1UL << irq);
10281028
}
10291029

10301030
/**
@@ -1046,7 +1046,7 @@ __STATIC_FORCEINLINE uint32_t __get_core_irq_pending_s(uint32_t irq)
10461046
*/
10471047
__STATIC_FORCEINLINE void __clear_core_irq_pending_s(uint32_t irq)
10481048
{
1049-
__RV_CSR_CLEAR(CSR_SIP, 1 << irq);
1049+
__RV_CSR_CLEAR(CSR_SIP, 1UL << irq);
10501050
}
10511051

10521052
/**
@@ -1463,7 +1463,7 @@ __STATIC_FORCEINLINE void __disable_minstret_counter(void)
14631463
*/
14641464
__STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)
14651465
{
1466-
__RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1 << idx));
1466+
__RV_CSR_CLEAR(CSR_MCOUNTINHIBIT, (1UL << idx));
14671467
}
14681468

14691469
/**
@@ -1474,7 +1474,7 @@ __STATIC_FORCEINLINE void __enable_mhpm_counter(unsigned long idx)
14741474
*/
14751475
__STATIC_FORCEINLINE void __disable_mhpm_counter(unsigned long idx)
14761476
{
1477-
__RV_CSR_SET(CSR_MCOUNTINHIBIT, (1 << idx));
1477+
__RV_CSR_SET(CSR_MCOUNTINHIBIT, (1UL << idx));
14781478
}
14791479

14801480
/**

‎NMSIS/Core/Include/core_feature_cache.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -261,12 +261,12 @@ __STATIC_FORCEINLINE int32_t GetICacheInfo(CacheInfo_Type *info)
261261
}
262262
CSR_MICFGINFO_Type csr_ccfg;
263263
csr_ccfg.d = __RV_CSR_READ(CSR_MICFG_INFO);
264-
info->setperway = (1 << csr_ccfg.b.set) << 3;
264+
info->setperway = (1UL << csr_ccfg.b.set) << 3;
265265
info->ways = (1 + csr_ccfg.b.way);
266266
if (csr_ccfg.b.lsize == 0) {
267267
info->linesize = 0;
268268
} else {
269-
info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
269+
info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
270270
}
271271
info->size = info->setperway * info->ways * info->linesize;
272272
return 0;
@@ -825,12 +825,12 @@ __STATIC_FORCEINLINE int32_t GetDCacheInfo(CacheInfo_Type *info)
825825
}
826826
CSR_MDCFGINFO_Type csr_ccfg;
827827
csr_ccfg.d = __RV_CSR_READ(CSR_MDCFG_INFO);
828-
info->setperway = (1 << csr_ccfg.b.set) << 3;
828+
info->setperway = (1UL << csr_ccfg.b.set) << 3;
829829
info->ways = (1 + csr_ccfg.b.way);
830830
if (csr_ccfg.b.lsize == 0) {
831831
info->linesize = 0;
832832
} else {
833-
info->linesize = (1 << (csr_ccfg.b.lsize - 1)) << 3;
833+
info->linesize = (1UL << (csr_ccfg.b.lsize - 1)) << 3;
834834
}
835835
info->size = info->setperway * info->ways * info->linesize;
836836
return 0;

‎NMSIS/Core/Include/core_feature_cidu.h‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ extern "C" {
6262
#endif
6363

6464
#define CIDU_BASE __CIDU_BASEADDR
65-
#define CIDU_RECEIVE_INTERRUPT_EN(core_id) (0x1U << core_id) /*!< Indicates the core can receive corresponding interrupt */
65+
#define CIDU_RECEIVE_INTERRUPT_EN(core_id) (0x1UL << core_id) /*!< Indicates the core can receive corresponding interrupt */
6666

6767
#define CIDU_CORE_INT_STATUS_OFS 0x0 /*!< Core n Inter Core Interrupt status register base offset */
6868
#define CIDU_SEMAPHORE_OFS 0x80 /*!< Semaphore n register base offset */
@@ -187,7 +187,7 @@ __STATIC_FORCEINLINE long CIDU_SetFirstClaimMode(uint32_t int_id, uint32_t core_
187187
{
188188
uint32_t val = 0;
189189
uint32_t* addr = (uint32_t*)CIDU_INT_MASK_ADDR(int_id);
190-
uint32_t mask = 1 << core_id;
190+
uint32_t mask = 1UL << core_id;
191191

192192
__SW(addr, mask);
193193
val = __LW(addr);
@@ -311,7 +311,7 @@ __STATIC_FORCEINLINE void CIDU_ClearInterCoreIntReq(uint32_t send_core_id, uint3
311311
uint32_t val = 0;
312312
uint32_t* addr = (uint32_t*)CIDU_CORE_INT_STATUS_ADDR(recv_core_id);
313313

314-
val = (uint32_t)(1 << send_core_id);
314+
val = (uint32_t)(1UL << send_core_id);
315315
__SW(addr, val);
316316
}
317317
/** @} */ /* End of Doxygen Group NMSIS_Core_ICI */

‎NMSIS/Core/Include/core_feature_eclic.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -652,7 +652,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ(IRQn_Type IRQn, uint8_t lvl_abs)
652652
if (nlbits > intctlbits) {
653653
nlbits = intctlbits;
654654
}
655-
uint8_t maxlvl = ((1 << nlbits) - 1);
655+
uint8_t maxlvl = ((1UL << nlbits) - 1);
656656
if (lvl_abs > maxlvl) {
657657
lvl_abs = maxlvl;
658658
}
@@ -710,7 +710,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ(IRQn_Type IRQn, uint8_t pri)
710710
uint8_t nlbits = __ECLIC_GetCfgNlbits();
711711
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
712712
if (nlbits < intctlbits) {
713-
uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
713+
uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);
714714
if (pri > maxpri) {
715715
pri = maxpri;
716716
}
@@ -1009,7 +1009,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetLevelIRQ_S(IRQn_Type IRQn, uint8_t lvl_abs)
10091009
if (nlbits > intctlbits) {
10101010
nlbits = intctlbits;
10111011
}
1012-
uint8_t maxlvl = ((1 << nlbits) - 1);
1012+
uint8_t maxlvl = ((1UL << nlbits) - 1);
10131013
if (lvl_abs > maxlvl) {
10141014
lvl_abs = maxlvl;
10151015
}
@@ -1068,7 +1068,7 @@ __STATIC_FORCEINLINE void __ECLIC_SetPriorityIRQ_S(IRQn_Type IRQn, uint8_t pri)
10681068
uint8_t nlbits = __ECLIC_GetCfgNlbits();
10691069
uint8_t intctlbits = (uint8_t)__ECLIC_INTCTLBITS;
10701070
if (nlbits < intctlbits) {
1071-
uint8_t maxpri = ((1 << (intctlbits - nlbits)) - 1);
1071+
uint8_t maxpri = ((1UL << (intctlbits - nlbits)) - 1);
10721072
if (pri > maxpri) {
10731073
pri = maxpri;
10741074
}

‎NMSIS/Core/Include/core_feature_plic.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -155,7 +155,7 @@ __STATIC_FORCEINLINE void PLIC_EnableContextInterrupt(uint32_t ctxid, uint32_t s
155155
volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
156156

157157
uint32_t current = *enable_reg;
158-
current = current | (1 << (source & 0x1F));
158+
current = current | (1UL << (source & 0x1F));
159159
*enable_reg = current;
160160
}
161161

@@ -174,7 +174,7 @@ __STATIC_FORCEINLINE void PLIC_DisableContextInterrupt(uint32_t ctxid, uint32_t
174174
volatile uint32_t *enable_reg = (uint32_t *)PLIC_ENABLE_REGADDR(ctxid, source);
175175

176176
uint32_t current = *enable_reg;
177-
current = current & (~(1 << (source & 0x1F)));
177+
current = current & (~(1UL << (source & 0x1F)));
178178
*enable_reg = current;
179179
}
180180

@@ -214,7 +214,7 @@ __STATIC_FORCEINLINE void PLIC_SetInterruptPending(uint32_t source)
214214
volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
215215

216216
uint32_t current = *pending_reg;
217-
current = current | (1 << (source & 0x1F));
217+
current = current | (1UL << (source & 0x1F));
218218
*pending_reg = current;
219219
}
220220

@@ -233,7 +233,7 @@ __STATIC_FORCEINLINE void PLIC_ClearInterruptPending(uint32_t source)
233233
volatile uint32_t *pending_reg = (uint32_t *)PLIC_PENDING_REGADDR(source);
234234

235235
uint32_t current = *pending_reg;
236-
current = current & (~(1 << (source & 0x1F)));
236+
current = current & (~(1UL << (source & 0x1F)));
237237
*pending_reg = current;
238238
}
239239

‎NMSIS/Core/Include/core_feature_pma.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -50,11 +50,11 @@
5050
* @{
5151
*/
5252

53-
#define PMA_REGION_TYPE_SECSHARE (0x1 << 3) /*!< Set this region shareable between secure world and non-secure world, or else default is invalid */
54-
#define PMA_REGION_TYPE_NC (0x1 << 2) /*!< Set this region Non-Cacheable, or else default is invalid */
55-
#define PMA_REGION_TYPE_DEV (0x1 << 1) /*!< Set this region Device, or else default is invalid */
53+
#define PMA_REGION_TYPE_SECSHARE (1UL << 3) /*!< Set this region shareable between secure world and non-secure world, or else default is invalid */
54+
#define PMA_REGION_TYPE_NC (1UL << 2) /*!< Set this region Non-Cacheable, or else default is invalid */
55+
#define PMA_REGION_TYPE_DEV (1UL << 1) /*!< Set this region Device, or else default is invalid */
5656
#define PMA_REGION_TYPE_CA (0) /*!< Set this region Cacheable, which is default */
57-
#define PMA_REGION_ENA (0x1 << 0) /*!< Enable this region, then the region type will take effect */
57+
#define PMA_REGION_ENA (1UL << 0) /*!< Enable this region, then the region type will take effect */
5858
#define PMA_REGION_DIS (0) /*!< Disable this region */
5959

6060
typedef struct PMA_CONFIG {

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