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matthewguimatthewgui
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conf/p0soc: add iomux and clk config for p0 soc 100M eth.
Signed-off-by: guibing <guibing@nucleisys.com>
1 parent 8c736f9 commit 7015651

1 file changed

Lines changed: 171 additions & 12 deletions

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‎conf/p0soc/opensbi/customsoc.c‎

Lines changed: 171 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -21,39 +21,198 @@ static const struct fdt_match nuclei_customsoc_match[] = {
2121
{ },
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};
2323

24-
#define NUCLEI_XEC_MISC_BASE 0xf9cdb0000
24+
#define NUCLEI_XEC1_MISC_BASE 0xf9cdb0000ULL
25+
#define NUCLEI_IOMUX_BASE 0xf9ca00000ULL
26+
#define NUCLEI_SYS_MISC_BASE 0xf9c880000ULL
27+
28+
#define LS_SRC_SEL_OFS(grp_id) (0x0000+grp_id*0x20000)
29+
#define HS_CHNL_SEL_OFS(grp_id) (0x2000+grp_id*0x20000)
30+
#define LS_SRC0_IVAL_SEL_OFS(grp_id) (0x4000+grp_id*0x20000)
31+
32+
#define PHY_CNTRL_OFS(grp_id) (0x6000+grp_id*0x20000)
33+
#define CNTRL_SEL_OFS(grp_id) (0x08000+grp_id*0x20000)
34+
35+
#define DO_SEL(regval) ((BIT(5)|BIT(6)) & ((u32)(regval) << 5))
36+
#define DO_SEL_PAD_PHYSICAL DO_SEL(0) /*!< DO_SEL_PHY */
37+
#define DO_SEL_HS DO_SEL(1) /*!< DO_SEL_HS*/
38+
#define DO_SEL_OE DO_SEL(2) /*!< DO_SEL_OE */
39+
40+
#define IE_SEL BIT(0)
41+
42+
#define OE_SEL(regval) ((BIT(3)|BIT(4)) & ((u32)(regval) << 3))
43+
#define OE_SEL_PAD_PHYSICAL OE_SEL(0) /*!< PAD_PHYSICAL */
44+
#define OE_SEL_HS_CHANNEL OE_SEL(1) /*!< OE_HS_CHANNEL */
45+
#define OE_SEL_OVAL_HS_CHANNEL OE_SEL(2) /*!< OVAL_HS_CHANNEL */
46+
47+
#define PAD_NUM 169
48+
49+
struct ls_grp_iof_t{
50+
u32 grp_iof_start_id;
51+
u32 grp_iof_end_id;
52+
};
53+
54+
struct ls_grp_iof_t ls_grp_iof[]={
55+
{.grp_iof_start_id = 0, .grp_iof_end_id=47},
56+
{.grp_iof_start_id = 1, .grp_iof_end_id=106},
57+
{.grp_iof_start_id = 2, .grp_iof_end_id=162},
58+
{.grp_iof_start_id = 163, .grp_iof_end_id=217},
59+
{.grp_iof_start_id = 218, .grp_iof_end_id=267},
60+
{.grp_iof_start_id = 268, .grp_iof_end_id=316},
61+
{.grp_iof_start_id = 317, .grp_iof_end_id=360},
62+
{.grp_iof_start_id = 361, .grp_iof_end_id=403},
63+
};
64+
65+
u32 pad_to_group[PAD_NUM] = {
66+
[0 ... 21] = 0, // pad 0-21 group 0
67+
[22 ... 42] = 1, // pad 22-42 group 1
68+
[43 ... 63] = 2, // pad 43-63 group 2
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[64 ... 84] = 3, // pad 64-84 group 3
70+
[85 ... 105] = 4, // pad 85-105 group 4
71+
[106 ... 126] = 5, // pad 106-126 group 5
72+
[127 ... 147] = 6, // pad 127-147 group 6
73+
[148 ... 168] = 7 // pad 148-168 group 7
74+
};
75+
76+
static u32 set_pad_ls_ival_tie0(unsigned long iomux_base,u32 pad_id)
77+
{
78+
u32 grp_id;
79+
80+
grp_id = pad_to_group[pad_id];
81+
for(u32 i = ls_grp_iof[grp_id].grp_iof_start_id ;i<ls_grp_iof[grp_id].grp_iof_end_id+1; i++)
82+
{
83+
if(readl((void *)(iomux_base + LS_SRC0_IVAL_SEL_OFS(grp_id) + 0x4 * i))== pad_id)
84+
{
85+
writel(PAD_NUM + 1, (void *)(iomux_base + LS_SRC0_IVAL_SEL_OFS(grp_id) + 0x4 * i));
86+
}
87+
}
88+
89+
return 0;
90+
}
91+
92+
static void config_hs_io_ival(unsigned long iomux_base, u32 per_iof_id,u32 pad_id, u32 hs_grp)
93+
{
94+
unsigned long val;
95+
96+
set_pad_ls_ival_tie0(iomux_base, pad_id);
97+
writel(hs_grp, (void *)(iomux_base + HS_CHNL_SEL_OFS(pad_to_group[pad_id]) + 0x4 * per_iof_id));
98+
99+
val = readl((void *)(iomux_base + CNTRL_SEL_OFS(pad_to_group[pad_id]) + 0x4 * per_iof_id));
100+
val |= DO_SEL_HS | IE_SEL;
101+
writel(val, (void *)(iomux_base + CNTRL_SEL_OFS(pad_to_group[pad_id]) + 0x4 * per_iof_id));
102+
}
103+
104+
static void config_hs_io_oval(unsigned long iomux_base, u32 per_iof_id,u32 pad_id, u32 hs_grp)
105+
{
106+
unsigned long val;
107+
108+
writel(hs_grp, (void *)(iomux_base + HS_CHNL_SEL_OFS(pad_to_group[pad_id]) + 0x4 * per_iof_id));
109+
val = readl((void *)(iomux_base + CNTRL_SEL_OFS(pad_to_group[pad_id]) + 0x4 * per_iof_id));
110+
val |= DO_SEL_HS | OE_SEL_HS_CHANNEL;
111+
writel(val, (void *)(iomux_base + CNTRL_SEL_OFS(pad_to_group[pad_id]) + 0x4 * per_iof_id));
112+
}
113+
114+
void config_iomux_xec0(void)
115+
{
116+
/* mdio ival */
117+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 16, 16, 1);
118+
/* mdc ival */
119+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 17, 17, 1);
120+
/* rxc */
121+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 26, 26, 1);
122+
/* rxd3 */
123+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 27, 27, 1);
124+
/* rxd2 */
125+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 28, 28, 1);
126+
/* rxd1 */
127+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 29, 29, 1);
128+
/* rxd0 */
129+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 30, 30, 1);
130+
/* rxdv */
131+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 31, 31, 1);
132+
/* rver */
133+
config_hs_io_ival(NUCLEI_IOMUX_BASE, 32, 32, 1);
134+
135+
/* mdio oval */
136+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 16, 16, 1);
137+
/* mdc oval */
138+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 17, 17, 1);
139+
/* txen oval */
140+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 18, 18, 1);
141+
/* txd3 oval */
142+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 21, 21, 1);
143+
/* txd2 oval */
144+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 22, 22, 1);
145+
/* txd1 oval */
146+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 23, 23, 1);
147+
/* txd0 oval */
148+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 24, 24, 1);
149+
/* txc oval */
150+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 25, 25, 1);
151+
/* col oval */
152+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 33, 33, 1);
153+
/* crs oval */
154+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 34, 34, 1);
155+
/* txer oval */
156+
config_hs_io_oval(NUCLEI_IOMUX_BASE, 35, 35, 1);
157+
}
25158

26159
static int nuclei_customsoc_final_init(bool cold_boot,
27160
const struct fdt_match *match)
28161
{
29162
if (cold_boot) { // Add cold boot initial steps
30163
u32 val;
31-
/* MISC_CTRL0_CLUSTER2_SYSRSTREQ_EN */
164+
/* enable cluster2 req sysrst */
32165
val = readl((void *)(0xf9c100000 + 0xc80));
33166
val |= 1 << 13;
34167
writel(val, (void *)(0xf9c100000 + 0xc80));
168+
/* init xec0 clk and reset xec0 ip */
169+
170+
/* config xec0 iomux */
171+
config_iomux_xec0();
172+
/* config xec_gen20_clk_i to 500M/(19+1) = 25MHZ */
173+
val = readl((void *)(NUCLEI_SYS_MISC_BASE + 0x2f8));
174+
val &= ~0xff;
175+
val |= 19;
176+
writel(val, (void *)(NUCLEI_SYS_MISC_BASE + 0x2f8));
177+
/* config rmii clk_ref_i to 500/(9+1)=50MHZ */
178+
val = readl((void *)(NUCLEI_SYS_MISC_BASE + 0x300));
179+
val &= ~0xff;
180+
val |= 0x9;
181+
writel(val, (void *)(NUCLEI_SYS_MISC_BASE + 0x300));
182+
/* enable xec0 clk */
183+
val = readl((void *)(NUCLEI_SYS_MISC_BASE + 0x48));
184+
val |= 1 << 2;
185+
writel(val, (void *)(NUCLEI_SYS_MISC_BASE + 0x48));
186+
/* reset xec0 ip */
187+
val = readl((void *)(NUCLEI_SYS_MISC_BASE + 0x28));
188+
val &= ~(1 << 2);
189+
writel(val, (void *)(NUCLEI_SYS_MISC_BASE + 0x28));
190+
val = readl((void *)(NUCLEI_SYS_MISC_BASE + 0x28));
191+
val |= (1 << 2);
192+
writel(val, (void *)(NUCLEI_SYS_MISC_BASE + 0x28));
193+
35194
/* init xec1 clk and reset xec1 ip */
36195
/* config xec_gen21_clk_i to 500M/(3+1) = 125MHZ */
37-
val = readl((void *)(NUCLEI_XEC_MISC_BASE + 0x2fc));
196+
val = readl((void *)(NUCLEI_XEC1_MISC_BASE + 0x2fc));
38197
val &= ~0xff;
39198
val |= 3;
40-
writel(val, (void *)(NUCLEI_XEC_MISC_BASE + 0x2fc));
199+
writel(val, (void *)(NUCLEI_XEC1_MISC_BASE + 0x2fc));
41200
/* config rmii clk_ref_i to 500/(9+1)=50MHZ */
42-
val = readl((void *)(NUCLEI_XEC_MISC_BASE + 0x300));
201+
val = readl((void *)(NUCLEI_XEC1_MISC_BASE + 0x300));
43202
val &= ~0xff;
44203
val |= 0x9;
45-
writel(val, (void *)(NUCLEI_XEC_MISC_BASE + 0x300));
204+
writel(val, (void *)(NUCLEI_XEC1_MISC_BASE + 0x300));
46205
/* enable xec1 clk */
47-
val = readl((void *)(NUCLEI_XEC_MISC_BASE + 0x48));
206+
val = readl((void *)(NUCLEI_XEC1_MISC_BASE + 0x48));
48207
val |= 1 << 3;
49-
writel(val, (void *)(NUCLEI_XEC_MISC_BASE + 0x48));
208+
writel(val, (void *)(NUCLEI_XEC1_MISC_BASE + 0x48));
50209
/* reset xec1 ip */
51-
val = readl((void *)(NUCLEI_XEC_MISC_BASE + 0x28));
210+
val = readl((void *)(NUCLEI_XEC1_MISC_BASE + 0x28));
52211
val &= ~(1 << 3);
53-
writel(val, (void *)(NUCLEI_XEC_MISC_BASE + 0x28));
54-
val = readl((void *)(NUCLEI_XEC_MISC_BASE + 0x28));
212+
writel(val, (void *)(NUCLEI_XEC1_MISC_BASE + 0x28));
213+
val = readl((void *)(NUCLEI_XEC1_MISC_BASE + 0x28));
55214
val |= (1 << 3);
56-
writel(val, (void *)(NUCLEI_XEC_MISC_BASE + 0x28));
215+
writel(val, (void *)(NUCLEI_XEC1_MISC_BASE + 0x28));
57216
}
58217

59218
// Check mcfg_info.tee to see whether tee present

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