Skip to content

Commit b08dd8d

Browse files
matthewguimatthewgui
committed
conf/evalsoc: update openocd.cfg file.
Signed-off-by: guibing <guibing@nucleisys.com>
1 parent 0e582ef commit b08dd8d

1 file changed

Lines changed: 127 additions & 37 deletions

File tree

‎conf/evalsoc/openocd.cfg‎

Lines changed: 127 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -1,59 +1,149 @@
1-
adapter_khz 1000
1+
# please use >= 2022.08 openocd
2+
# some commands are changed to match latest openocd changes
3+
adapter speed 1000
24

3-
interface ftdi
4-
ftdi_vid_pid 0x0403 0x6010
5-
ftdi_oscan1_mode off
6-
7-
## Bind ftdi device using ftdi_serial
8-
## the serial number could be checked using FT_Prog or dmesg
9-
# ftdi_serial "FT5Q5L33"
5+
adapter driver ftdi
6+
ftdi vid_pid 0x0403 0x6010
7+
# for 2023.10 openocd, change oscan1_mode to nscan1_mode
8+
ftdi oscan1_mode off
109

1110
## bindto 0.0.0.0 can be used to cover all available interfaces.
1211
## Uncomment bindto line to enable remote machine debug
13-
bindto 0.0.0.0
12+
# bindto 0.0.0.0
13+
14+
## you can also specify adapter serial to select a ftdi chip
15+
# adapter serial "FT6S9RD6"
1416

15-
## If ftdi_device_desc not specified, the device description is ignored during device selection.
16-
## So if you want to specify a dedicated FTDI device, you can select following device description:
17-
## "Dual RS232-HS" is for HummingBird Debugger V1
18-
## "USB <-> JTAG-DEBUGGER" is for HummingBird Debugger V2
19-
## Uncomment one which match your device description
20-
# ftdi_device_desc "Dual RS232-HS"
21-
# ftdi_device_desc "USB <-> JTAG-DEBUGGER"
17+
## Bind JTAG with specified serial number passed by JTAGSN
18+
# https://doc.nucleisys.com/nuclei_sdk/develop/buildsystem.html#jtagsn
19+
if { [ info exists JTAGSN ] } {
20+
puts "Bind JTAG with serial number $JTAGSN"
21+
adapter serial $JTAGSN
22+
}
2223

2324
transport select jtag
2425

25-
ftdi_layout_init 0x0008 0x001b
26-
ftdi_layout_signal nSRST -oe 0x0020 -data 0x0020
27-
ftdi_layout_signal TCK -data 0x0001
28-
ftdi_layout_signal TDI -data 0x0002
29-
ftdi_layout_signal TDO -input 0x0004
30-
ftdi_layout_signal TMS -data 0x0008
31-
ftdi_layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
26+
ftdi layout_init 0x0008 0x001b
27+
ftdi layout_signal nSRST -oe 0x0020 -data 0x0020
28+
ftdi layout_signal TCK -data 0x0001
29+
ftdi layout_signal TDI -data 0x0002
30+
ftdi layout_signal TDO -input 0x0004
31+
ftdi layout_signal TMS -data 0x0008
32+
ftdi layout_signal JTAG_SEL -data 0x0100 -oe 0x0100
33+
34+
# openocd variable set
35+
if { [ info exists BOOT_HARTID ] } {
36+
puts "boot hart id expected to be $BOOT_HARTID"
37+
set BOOTHART $BOOT_HARTID
38+
} else {
39+
puts "Set boot hart id to default 0"
40+
set BOOTHART 0
41+
}
42+
43+
if { [ info exists SMP ] } {
44+
puts "SMP CPU count expected to be $SMP"
45+
set CORECNT $SMP
46+
} else {
47+
puts "Set default SMP CPU count to default 1"
48+
set CORECNT 1
49+
}
50+
51+
# TODO: variables should be replaced by nuclei_gen
52+
set workmem_base 0x80000000
53+
set workmem_size 0x10000
54+
set flashxip_base 0x20000000
55+
set xipnuspi_base 0x10014000
56+
57+
# if NOFLASH variable exist or passed by openocd command
58+
# will not probe flash device
59+
set _noflash [ info exists NOFLASH ]
3260

61+
# Create JTAG chain
3362
set _CHIPNAME riscv
34-
jtag newtap $_CHIPNAME cpu -irlen 5
63+
if { [ info exists SPLITMODE ] } {
64+
# SPLIT MODE mainly for Nuclei NA product line
65+
# It can split the lock-step CPU into two standalone CPU core
66+
if { $SPLITMODE > 1 } { # when SPLITMODE > 1, it means you wan to expose two harts for gdb connections
67+
jtag newtap $_CHIPNAME.1 cpu -irlen 5
68+
jtag newtap $_CHIPNAME.0 cpu -irlen 5
69+
set _TARGETNAME $_CHIPNAME.1.cpu
70+
} else {
71+
# hart1 hart0 in split mode
72+
# only one hart will be exposed to be connnected via gdb
73+
# the hart is selected by BOOTHART
74+
if { $BOOTHART == 0 } {
75+
jtag newtap $_CHIPNAME.split cpu -irlen 5
76+
jtag newtap $_CHIPNAME cpu -irlen 5
77+
} else {
78+
jtag newtap $_CHIPNAME cpu -irlen 5
79+
jtag newtap $_CHIPNAME.split cpu -irlen 5
80+
}
81+
set _TARGETNAME $_CHIPNAME.cpu
82+
}
83+
} else {
84+
jtag newtap $_CHIPNAME cpu -irlen 5
85+
set _TARGETNAME $_CHIPNAME.cpu
86+
}
87+
88+
set _smp_command ""
3589

36-
set _TARGETNAME $_CHIPNAME.cpu
37-
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
38-
$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
90+
if { $CORECNT > 1 } {
91+
set _BOOTHARTNAME $_TARGETNAME.$BOOTHART
92+
for { set _core 0 } { $_core < $CORECNT } { incr _core } {
93+
set _command "target create $_TARGETNAME.$_core riscv -chain-position $_TARGETNAME"
94+
if { $_core == 0 } {
95+
set _command "$_command -rtos hwthread"
96+
set _smp_command "target smp $_TARGETNAME.$_core"
97+
} else {
98+
set _command "$_command -coreid $_core"
99+
set _smp_command "$_smp_command $_TARGETNAME.$_core"
100+
}
101+
# do target create for each cpu
102+
eval $_command
103+
}
104+
# do target smp for all cpus
105+
eval $_smp_command
106+
} else {
107+
set _BOOTHARTNAME $_TARGETNAME
108+
if { [ info exists SPLITMODE ] } {
109+
if { $SPLITMODE > 1 } {
110+
target create $_CHIPNAME.0.cpu riscv -chain-position $_CHIPNAME.0.cpu
111+
target create $_CHIPNAME.1.cpu riscv -chain-position $_CHIPNAME.1.cpu
112+
} else {
113+
# split mode coreid is always 0
114+
target create $_TARGETNAME riscv -chain-position $_TARGETNAME
115+
}
116+
} else {
117+
# create a single hart target with coreid = $BOOTHART
118+
target create $_TARGETNAME riscv -chain-position $_TARGETNAME -coreid $BOOTHART
119+
}
120+
}
39121

40-
set _FLASHNAME $_CHIPNAME.flash
41-
# Please use Nuclei OpenOCD >= 2022.01 release version
42-
flash bank $_FLASHNAME nuspi 0x20000000 0 0 0 $_TARGETNAME
43-
# Set the ILM space also as flash, to make sure it can be add breakpoint with hardware trigger
44-
#flash bank onboard_ilm nuspi 0x80000000 0 0 0 $_TARGETNAME
122+
$_BOOTHARTNAME configure -work-area-phys $workmem_base -work-area-size $workmem_size -work-area-backup 1
123+
124+
if { $_noflash == 0 } {
125+
set _FLASHNAME $_CHIPNAME.flash
126+
flash bank $_FLASHNAME nuspi $flashxip_base 0 0 0 $_BOOTHARTNAME $xipnuspi_base
127+
}
45128

46129
# Expose Nuclei self-defined CSRS
47130
# See https://github.com/riscv/riscv-gnu-toolchain/issues/319#issuecomment-358397306
48131
# Then user can view the csr register value in gdb using: info reg csr775 for CSR MTVT(0x307)
49-
riscv expose_csrs 416-496,770-800,835-850,1227-1231,1483-1486,1984-2032,2064-2070,2370-2380,2490-2500,4032-4040
132+
# No need to expose it now for openocd >= 2022.01
133+
# riscv expose_csrs 416-496,770-800,835-850,1227-1231,1483-1486,1984-2040,2064-2070,2370-2380,2490-2500,4032-4040
50134

51135
init
52136

53-
if {[ info exists pulse_srst]} {
54-
ftdi_set_signal nSRST 0
55-
ftdi_set_signal nSRST z
137+
if { [ info exists pulse_srst ] } {
138+
ftdi set_signal nSRST 0
139+
ftdi set_signal nSRST z
56140
}
141+
57142
halt
143+
58144
# We must turn on this because otherwise the IDE version debug cannot download the program into flash
59-
flash protect 0 0 last off
145+
if { $_noflash == 0 } {
146+
flash protect 0 0 last off
147+
}
148+
149+
arm semihosting enable

0 commit comments

Comments
 (0)