Reset is ignored

[rhinton]

I'm loving the AXI4 VIP in this repo. I'm using Axi4/src/Axi4MemoryVTI.vhd. I finally tracked down an Alert output to the fact that my design is issuing read and write transactions while the nReset port is asserted (low). And I can see in the debug transcript that Axi4MemoryVti is queueing these transactions. Also, a simple text search shows that nReset isn't used anywhere in Axi4MemoryVti.

Unfortunately, I can't submit a test bench showing this problem. Hopefully my description above is sufficient.

[Paebbels]

What would be a definition of a reset on a memory? Memory arrays can't be reset in ASIC and FPGAs. At maximum, you could reset a potential state in reader and writer logics.

[rhinton]

Good point. I don't care what happens in the storage. Instead, I need all the internal transaction FIFOs (write address channel, write data, read address, read data) cleared out. Also any transactions issued during the reset should be ignored. (Take "ready" low?)

The behavior I'm seeing is that I push in a write address, but the "Memory write" transaction actually happens at a different address. This happens because I pushed one or two extra write address transactions before / during the reset.

[JimLewis]

Hi Ryan,
So during reset, ignore memory function inputs. During reset, throw out anything in any FIFO that is in process?

Can I assume that your testbench is well enough behaved that I will not receive anything on the transaction interface during reset? Or do I need to ignore and flush that sort of stuff too?

Is this reset only at start up of the system, or could there be a reset later and the model would need to reinitialize anything that holds state information - this could get complicated due to delays in the system.

Best Regards,
Jim

[rhinton]

Hi, Jim. :-)

Ideally, I expect nReset to behave like a reset. So any previous requests / activity / internal state is canceled / cleared. Right? You could require a minimum pulse time if it makes the implementation w/ delays easier. (And it would be easy to verify the reset pulse width.)

I think my tb was well-behaved and didn't do anything on the transaction interface during reset. My philosophy is that you're allowed to make any assumption you check. :-) In my case, the reset was only at the beginning of the sim. In my particular case, I was happy with a delay of 0 ns.

• Ryan