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doc: Added cards per vendor.
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doc/ToolSpecific.rst

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Simulator Specifics
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###################
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.. rubric:: Support Simulators (in alphabetic order)
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.. grid:: 6
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.. grid-item-card:: Aldec
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:columns: 2
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* :ref:`SIM/Aldec/ActiveHDL`
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* :ref:`SIM/Aldec/RivieraPRO`
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.. grid-item-card:: AMD (Xilinx)
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:columns: 2
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* :ref:`SIM/AMD/xSim`
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.. grid-item-card:: Cadence
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:columns: 2
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* :ref:`SIM/Cadence/Xcelium`
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.. grid-item-card:: Open-Source
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:columns: 2
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* :ref:`SIM/GHDL`
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* :ref:`SIM/NVC`
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.. grid-item-card:: Siemens EDA
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:columns: 2
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* :ref:`SIM/Siemens/ModelSim`
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* :ref:`SIM/Siemens/Questa`
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* :ref:`SIM/Siemens/Visualizer`
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.. grid-item-card:: Synopsys
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:columns: 2
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* :ref:`SIM/Synopsys/VCS`
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Quick Overview
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**************
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source <path-to-OsvvmLibraries>/OsvvmLibraries/Scripts/StartUp.tcl
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.. _SIM/Aldec:
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Aldec
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*****
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.. _SIM/Aldec/ActiveHDL:
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Active-HDL
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==========
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Note, with 2021.02, you no longer need to set the "Start In" directory to the OSVVM Scripts directory.
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.. _SIM/Aldec/RivieraPRO:
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Riviera-PRO
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===========
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.. _SIM/AMD:
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.. _SIM/Xilinx:
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AMD (Xilinx)
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************
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.. _SIM/AMD/xSim:
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.. _SIM/Xilinx/xSim:
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xSim
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====
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.. _SIM/Cadence:
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Cadence
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*******
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.. _SIM/Cadence/Xcelium:
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Xcelium
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=======
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.. _SIM/GHDL:
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GHDL
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****
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.. _SIM/GHDL/Windows:
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GHDL on Windows in MSYS2/UCRT64
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===============================
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pacman -S ucrt64/mingw-w64-ucrt-x86_64-winpty
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pacman -S ucrt64/mingw-w64-ucrt-x86_64-tcl ucrt64/mingw-w64-ucrt-x86_64-tcllib
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.. _SIM/GHDL/Linux:
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.. _SIM/GHDL/macOS:
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GHDL on Linux/macOS
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===================
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To simplify this, put :file:`source <path-to-OsvvmLibraries>/OsvvmLibraries/Scripts/StartUp.tcl` in the :file:`.tclshrc`
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file and in Bash add ``alias gsim='rlwrap tclsh'`` to your :file:`.bashrc`.
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.. _SIM/NVC:
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NVC
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***
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.. _SIM/NVC/Windows:
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NVC on Windows in MSYS2/UCRT64
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==============================
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.. _SIM/NVC/Linux:
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.. _SIM/NVC/macOS:
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NVC on Linux
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============
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.. _SIM/Siemens:
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Siemens EDA
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***********
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.. _SIM/Siemens/ModelSim:
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ModelSim
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.. _SIM/Siemens/Questa:
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Questa / QuestaSim
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==================
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.. _SIM/Siemens/Visualizer:
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Visualizer
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==========
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.. _SIM/Synopsys:
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Synopsys
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********
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.. _SIM/Synopsys/VCS:
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VCS
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===

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