Merge branch 'main' into install-deps

Author: soumeh01

.github/workflows/ci.yml

@@ -321,7 +321,7 @@ jobs:
         working-directory: test-coverage
 
       - name: Attach packages
-        uses: softprops/action-gh-release@5be0e66d93ac7ed76da52eca8bb058f665c3a5fe # v2.4.2
+        uses: softprops/action-gh-release@153bb8e04406b158c6c84fc1615b65b24149a1fe # v2.6.1
         with:
           files: |
             **/*.vsix

.github/workflows/codeql.yml

@@ -51,16 +51,16 @@ jobs:
 
       - name: Initialize CodeQL
         id: initialize
-        uses: github/codeql-action/init@38697555549f1db7851b81482ff19f1fa5c4fedc # v4.34.1
+        uses: github/codeql-action/init@c10b8064de6f491fea524254123dbe5e09572f13 # v4.35.1
         with:
           queries: security-extended 
           languages: TypeScript
           source-root: src
 
       - name: Autobuild
         id: autobuild
-        uses: github/codeql-action/autobuild@38697555549f1db7851b81482ff19f1fa5c4fedc # v4.34.1
+        uses: github/codeql-action/autobuild@c10b8064de6f491fea524254123dbe5e09572f13 # v4.35.1
 
       - name: Perform CodeQL Analysis
         id: analyze
-        uses: github/codeql-action/analyze@38697555549f1db7851b81482ff19f1fa5c4fedc # v4.34.1
+        uses: github/codeql-action/analyze@c10b8064de6f491fea524254123dbe5e09572f13 # v4.35.1

.github/workflows/scorecard.yml

@@ -80,6 +80,6 @@ jobs:
       # Upload the results to GitHub's code scanning dashboard (optional).
       # Commenting out will disable the upload of results to your repo's Code Scanning dashboard
       - name: "Upload to code-scanning"
-        uses: github/codeql-action/upload-sarif@38697555549f1db7851b81482ff19f1fa5c4fedc # v4.34.1
+        uses: github/codeql-action/upload-sarif@c10b8064de6f491fea524254123dbe5e09572f13 # v4.35.1
         with:
           sarif_file: results.sarif

.qlty/qlty.toml

@@ -68,6 +68,7 @@ name = "ripgrep"          # Fast searching for pattern matching in codebase
 
 [[plugin]]
 name = "trivy"            # Scans for vulnerabilities in containers and dependencies
+version = "0.69.3"        # Pinned to secure version
 
 [[plugin]]
 name = "trufflehog"       # Detects secrets and sensitive data in code

CHANGELOG.md

@@ -1,5 +1,43 @@
 # Change Log
 
+## 1.5.1
+
+- Adds `Fault Reports` to the [Core Peripherals](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#core-peripherals) view.
+- Improves expand/collapse behavior with active filter in [Component Viewer](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#component-viewer) and
+[Core Peripherals](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#core-peripherals) views.
+- Includes updated pyOCD distribution ([pyOCD v0.44.0](https://github.com/pyocd/pyOCD/releases/tag/v0.44.0))
+    - Uses default debug sequences as defined in the
+    [Open-CMSIS-Pack specification](https://open-cmsis-pack.github.io/Open-CMSIS-Pack-Spec/main/html/debug_description.html#autotoc_md2).
+    - Adds missing sequence support for flash programming and holding hardware reset.
+    - Changes strategy of programming multiple flash memories from multiple erase-program-verify sequences per flash memory to a single
+    erase-program-verify sequence spannig all targeted flash memories.
+    - Renames RTT channel mode `telnet` to `server`.
+    - Adds Segger [SystemView](https://www.segger.com/products/development-tools/systemview/) server mode to support direct recording
+    from pyOCD via IP (TCP/IP connection) for [`run`](https://open-cmsis-pack.github.io/cmsis-toolbox/pyOCD-Debugger/#command-line-invocation)
+    subcommand.
+    - Improves robustness and logging of [Segger RTT](https://www.segger.com/products/debug-probes/j-link/technology/about-real-time-transfer/)
+    support.
+    - See [pyOCD v0.44.0](https://github.com/pyocd/pyOCD/releases/tag/v0.44.0) for a full list of ehancements and bug fixes.
+
+## 1.5.0
+
+- Pre-release with a preview of the new [Core Peripherals](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#core-peripherals) view that lives under
+  [Trace and Live View](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#trace-and-live-view).
+    - Early feedback is welcomed, please use [GitHub issues](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger/issues/new/choose) to raise enhancement requests or defects.
+- Fixes [Component Viewer](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#component-viewer) display and stability issues.
+- Included in this extension pre-release:
+    - [pyOCD v0.43.1](https://github.com/pyocd/pyOCD/releases/tag/v0.43.1)
+    - [arm-none-eabi-gdb v14.3.1](https://artifacts.tools.arm.com/arm-none-eabi-gdb/14.3.1/)
+- Full list of required minimum versions for correct functionality of the CMSIS Debugger v1.5.0 pre-release:
+    - [Arm CMSIS Solution extension v1.66.0](https://marketplace.visualstudio.com/items?itemName=Arm.cmsis-csolution)
+    - [CDT GDB Adapter extension v2.7.0](https://marketplace.visualstudio.com/items?itemName=eclipse-cdt.cdt-gdb-vscode)
+    - [Memory Inspector v1.2.0](https://marketplace.visualstudio.com/items?itemName=eclipse-cdt.memory-inspector)
+    - [Peripheral Inspector v1.9.0](https://marketplace.visualstudio.com/items?itemName=eclipse-cdt.peripheral-inspector)
+    - [Serial Monitor v0.13.1](https://marketplace.visualstudio.com/items?itemName=ms-vscode.vscode-serial-monitor)
+    - [RTOS Views v0.0.14](https://marketplace.visualstudio.com/items?itemName=mcu-debug.rtos-views)
+- See [v1.4.1...v1.5.0](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger/compare/v1.4.1...v1.5.0) for a full list
+of changes that went into this pre-release.
+
 ## 1.4.1
 
 - Fixes debugger run control intermittently becoming unresponsive when [Component Viewer](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger?tab=readme-ov-file#component-viewer) is active.

README.md

@@ -277,8 +277,8 @@ Most Arm Cortex-M processors (except Cortex-M0/M0+/M23) include a `DWT->CYCCNT`
 
 The **Trace and Live View**
 ![Trace and Live view](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger/raw/main/images/TraceLiveView.png)
-(available from the VS Code Activity Bar) currently contains the [**LIVE WATCH**](#live-watch) and the
-[**COMPONENT VIEWER**](#component-viewer) views.
+(available from the VS Code Activity Bar) currently contains the [**LIVE WATCH**](#live-watch), the
+[**COMPONENT VIEWER**](#component-viewer), and the [**CORE PERIPHERALS**](#core-peripherals) views.
 
 #### LIVE WATCH
 
@@ -304,6 +304,18 @@ The Component Viewer shows information about:
 
 ![Showing software component properties in the COMPONENT VIEWER](https://github.com/Open-CMSIS-Pack/vscode-cmsis-debugger/raw/main/images/component-viewer.png)
 
+#### CORE PERIPHERALS
+
+The **CORE PERIPHERALS** view gives insight into the programming of CPU specific core peripherals.
+
+The Core Peripherals view shows information about the following components if implemented by the CPU:
+
+- Memory Protection Unit
+- Nested Vectored Interrupt Controller
+- System Config and Control
+- System Tick Timer
+- Fault Reports
+
 ### PERIPHERALS
 
 The **PERIPHERALS** view shows the device peripheral registers and allows to change their values. It uses the CMSIS-SVD files that are provided by silicon vendors and distributed as part of the CMSIS Device Family Packs (DFP).

configs/core-peripherals/Fault_Reports.scvd

@@ -0,0 +1,120 @@
+<?xml version="1.0" encoding="utf-8"?>
+<!--
+   Copyright 2026 Arm Limited
+  
+   Licensed under the Apache License, Version 2.0 (the "License");
+   you may not use this file except in compliance with the License.
+   You may obtain a copy of the License at
+
+       https://www.apache.org/licenses/LICENSE-2.0
+
+   Unless required by applicable law or agreed to in writing, software
+   distributed under the License is distributed on an "AS IS" BASIS,
+   WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+   See the License for the specific language governing permissions and
+   limitations under the License.
+-->
+<component_viewer schemaVersion="0.1" xmlns:xs="https://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
+  <component name="FaultReportsComponent" version="1.0.0"/>
+  <typedefs>
+    <typedef name="StandardFaultRegisters_t" size="0x18">
+      <member name="MMFSR" type="uint8_t" offset="0x00"/>
+      <member name="BFSR" type="uint8_t" offset="0x01"/>
+      <member name="UFSR" type="uint16_t" offset="0x02"/>
+      <member name="HFSR" type="uint32_t" offset="0x04"/>
+      <member name="DFSR" type="uint32_t" offset="0x08"/>
+      <member name="MMFAR" type="uint32_t" offset="0x0C"/>
+      <member name="BFAR" type="uint32_t" offset="0x10"/>
+      <member name="AFSR" type="uint32_t" offset="0x14"/>
+    </typedef>
+    <typedef name="SecureFaultRegisters_t" size="0x08">
+      <member name="SFSR" type="uint32_t" offset="0x00"/>
+      <member name="SFAR" type="uint32_t" offset="0x04"/>
+    </typedef>
+  </typedefs>
+  <objects>
+    <object name="FaultReportsObject">
+      <read name="StandardFaultRegisters" type="StandardFaultRegisters_t" offset="0xE000ED28"/>
+      <read name="ID_PFR1" type="uint32_t" offset="0xE000ED44"/>
+      <var name="ShowSecureFaults" type="uint8_t" value="0"/>
+      <calc>
+        ShowSecureFaults=1&amp;&amp;(ID_PFR1&amp;0xF0);
+      </calc>
+      <read name="SecureFaultRegisters" cond="ShowSecureFaults" type="SecureFaultRegisters_t" offset="0xE000EDE4"/>
+      <out name="Fault Reports">
+       <item property="ID_PFR1" value="%x[ID_PFR1]"/>
+       <item property="Memory Manage Faults" value="">
+         <item property="Address (SCB->MMFAR)" value="%x[StandardFaultRegisters.MMFAR]">    
+         </item>       
+         <item property="Status (SCB->CFSR->MMFSR)" value="%x[StandardFaultRegisters.MMFSR]">    
+           <item property="IACCVIOL" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;0)&amp;0x1]"/>
+           <item property="DACCVIOL" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;1)&amp;0x1]"/>
+           <item property="MUNSTKERR" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;3)&amp;0x1]"/>
+           <item property="MSTKERR" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;4)&amp;0x1]"/>
+           <item property="MLSPERR" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;5)&amp;0x1]"/>
+           <item property="MMFARVALID" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;7)&amp;0x1]"/>
+         </item>       
+       </item>
+       <item property="Bus Faults" value="">
+         <item property="Address (SCB->BFAR)" value="%x[StandardFaultRegisters.BFAR]">    
+         </item>       
+         <item property="Status (SCB->CFSR->BFSR)" value="%x[StandardFaultRegisters.BFSR]">    
+           <item property="IBUSERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;0)&amp;0x1]"/>
+           <item property="PRECISERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;1)&amp;0x1]"/>
+           <item property="IMPRECISERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;2)&amp;0x1]"/>
+           <item property="UNSTKERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;3)&amp;0x1]"/>
+           <item property="STKERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;4)&amp;0x1]"/>
+           <item property="LSPERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;5)&amp;0x1]"/>
+           <item property="BFARVALID" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;7)&amp;0x1]"/>
+         </item>       
+       </item>
+       <item property="Usage Faults" value="">
+         <item property="Status (SCB->CFSR->UFSR)" value="%x[StandardFaultRegisters.UFSR]">    
+           <item property="UNDEFINSTR" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;0)&amp;0x1]"/>
+           <item property="INVSTATE" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;1)&amp;0x1]"/>
+           <item property="INVPC" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;2)&amp;0x1]"/>
+           <item property="NOCP" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;3)&amp;0x1]"/>
+           <item property="STKOF" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;4)&amp;0x1]"/>
+           <item property="UNALIGNED" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;8)&amp;0x1]"/>
+           <item property="DIVBYZERO" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;9)&amp;0x1]"/>
+         </item>       
+       </item>
+       <item property="Hard Faults" value="">
+         <item property="Status (SCB->HFSR)" value="%x[StandardFaultRegisters.HFSR]">    
+           <item property="VECTTBL" value="%d[(StandardFaultRegisters.HFSR&gt;&gt;1)&amp;0x1]"/>
+           <item property="FORCED" value="%d[(StandardFaultRegisters.HFSR&gt;&gt;30)&amp;0x1]"/>
+           <item property="DEBUGEVT" value="%d[(StandardFaultRegisters.HFSR&gt;&gt;31)&amp;0x1]"/>
+        </item>       
+       </item>
+       <item property="Debug Faults" value="">
+         <item property="Status (SCB->DFSR)" value="%x[StandardFaultRegisters.DFSR]">    
+           <item property="HALTED" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;0)&amp;0x1]"/>
+           <item property="BKPT" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;1)&amp;0x1]"/>
+           <item property="DWTTRAP" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;2)&amp;0x1]"/>
+           <item property="VCATCH" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;3)&amp;0x1]"/>
+           <item property="EXTERNAL" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;4)&amp;0x1]"/>
+           <item property="PMU" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;5)&amp;0x1]"/>
+        </item>       
+       </item>
+       <item property="Auxiliary Faults" value="">
+         <item property="Status (SCB->AFSR)" value="%x[StandardFaultRegisters.AFSR]">    
+         </item>       
+       </item>
+       <item property="Secure Faults" cond="ShowSecureFaults" value="">
+         <item property="Address (SCB->SFAR)" value="%x[SecureFaultRegisters.SFAR]">    
+         </item>       
+         <item property="Status (SCB->CFSR->BFSR)" value="%x[SecureFaultRegisters.SFSR]">    
+           <item property="INVEP" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;0)&amp;0x1]"/>
+           <item property="INVIS" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;1)&amp;0x1]"/>
+           <item property="INVER" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;2)&amp;0x1]"/>
+           <item property="AUVIOL" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;3)&amp;0x1]"/>
+           <item property="INVTRAN" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;4)&amp;0x1]"/>
+           <item property="LSPERR" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;5)&amp;0x1]"/>
+           <item property="SFARVALID" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;6)&amp;0x1]"/>
+           <item property="LSERR" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;7)&amp;0x1]"/>
+         </item>       
+       </item>
+     </out>
+   </object>
+  </objects>
+</component_viewer>

configs/core-peripherals/core-peripherals-index.yml

@@ -9,3 +9,5 @@ core-peripherals:
     cpu-type: "*"
   - file: System_Tick_Timer.scvd
     cpu-type: "*"
+  - file: Fault_Reports.scvd
+    cpu-type: "*"