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Core Peripherals SCVD Improvements (#954)
* Adds Fault_Reports.scvd * Adds Memory_Protection_Unit_V7M.scvd * Optimizations (NVIC) and aligned register names for display * Renames Memory_Protection_Unit.scvd -> Memory_Protection_Unit_V8M.scvd * Display also region related registers * ExtIRQ numbers from svd start with 0, and irqLines calculation corrected
1 parent 0075dac commit 8aecc37

7 files changed

Lines changed: 511 additions & 168 deletions

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‎configs/core-peripherals/Fault_Reports.scvd‎

Lines changed: 11 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -42,11 +42,10 @@
4242
</calc>
4343
<read name="SecureFaultRegisters" cond="ShowSecureFaults" type="SecureFaultRegisters_t" offset="0xE000EDE4"/>
4444
<out name="Fault Reports">
45-
<item property="ID_PFR1" value="%x[ID_PFR1]"/>
4645
<item property="Memory Manage Faults" value="">
47-
<item property="Address (SCB->MMFAR)" value="%x[StandardFaultRegisters.MMFAR]">
46+
<item property="Address (MMFAR)" value="%x[StandardFaultRegisters.MMFAR]">
4847
</item>
49-
<item property="Status (SCB->CFSR->MMFSR)" value="%x[StandardFaultRegisters.MMFSR]">
48+
<item property="Status (MMFSR)" value="%x[StandardFaultRegisters.MMFSR]">
5049
<item property="IACCVIOL" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;0)&amp;0x1]"/>
5150
<item property="DACCVIOL" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;1)&amp;0x1]"/>
5251
<item property="MUNSTKERR" value="%d[(StandardFaultRegisters.MMFSR&gt;&gt;3)&amp;0x1]"/>
@@ -56,9 +55,9 @@
5655
</item>
5756
</item>
5857
<item property="Bus Faults" value="">
59-
<item property="Address (SCB->BFAR)" value="%x[StandardFaultRegisters.BFAR]">
58+
<item property="Address (BFAR)" value="%x[StandardFaultRegisters.BFAR]">
6059
</item>
61-
<item property="Status (SCB->CFSR->BFSR)" value="%x[StandardFaultRegisters.BFSR]">
60+
<item property="Status (BFSR)" value="%x[StandardFaultRegisters.BFSR]">
6261
<item property="IBUSERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;0)&amp;0x1]"/>
6362
<item property="PRECISERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;1)&amp;0x1]"/>
6463
<item property="IMPRECISERR" value="%d[(StandardFaultRegisters.BFSR&gt;&gt;2)&amp;0x1]"/>
@@ -69,7 +68,7 @@
6968
</item>
7069
</item>
7170
<item property="Usage Faults" value="">
72-
<item property="Status (SCB->CFSR->UFSR)" value="%x[StandardFaultRegisters.UFSR]">
71+
<item property="Status (UFSR)" value="%x[StandardFaultRegisters.UFSR]">
7372
<item property="UNDEFINSTR" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;0)&amp;0x1]"/>
7473
<item property="INVSTATE" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;1)&amp;0x1]"/>
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<item property="INVPC" value="%d[(StandardFaultRegisters.UFSR&gt;&gt;2)&amp;0x1]"/>
@@ -80,14 +79,14 @@
8079
</item>
8180
</item>
8281
<item property="Hard Faults" value="">
83-
<item property="Status (SCB->HFSR)" value="%x[StandardFaultRegisters.HFSR]">
82+
<item property="Status (HFSR)" value="%x[StandardFaultRegisters.HFSR]">
8483
<item property="VECTTBL" value="%d[(StandardFaultRegisters.HFSR&gt;&gt;1)&amp;0x1]"/>
8584
<item property="FORCED" value="%d[(StandardFaultRegisters.HFSR&gt;&gt;30)&amp;0x1]"/>
8685
<item property="DEBUGEVT" value="%d[(StandardFaultRegisters.HFSR&gt;&gt;31)&amp;0x1]"/>
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</item>
8887
</item>
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<item property="Debug Faults" value="">
90-
<item property="Status (SCB->DFSR)" value="%x[StandardFaultRegisters.DFSR]">
89+
<item property="Status (DFSR)" value="%x[StandardFaultRegisters.DFSR]">
9190
<item property="HALTED" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;0)&amp;0x1]"/>
9291
<item property="BKPT" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;1)&amp;0x1]"/>
9392
<item property="DWTTRAP" value="%d[(StandardFaultRegisters.DFSR&gt;&gt;2)&amp;0x1]"/>
@@ -97,13 +96,13 @@
9796
</item>
9897
</item>
9998
<item property="Auxiliary Faults" value="">
100-
<item property="Status (SCB->AFSR)" value="%x[StandardFaultRegisters.AFSR]">
99+
<item property="Status (AFSR)" value="%x[StandardFaultRegisters.AFSR]">
101100
</item>
102101
</item>
103-
<item property="Secure Faults" cond="ShowSecureFaults" value="">
104-
<item property="Address (SCB->SFAR)" value="%x[SecureFaultRegisters.SFAR]">
102+
<item property="Secure Faults" cond="ShowSecureFaults">
103+
<item property="Address (SFAR)" value="%x[SecureFaultRegisters.SFAR]">
105104
</item>
106-
<item property="Status (SCB->CFSR->BFSR)" value="%x[SecureFaultRegisters.SFSR]">
105+
<item property="Status (SFSR)" value="%x[SecureFaultRegisters.SFSR]">
107106
<item property="INVEP" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;0)&amp;0x1]"/>
108107
<item property="INVIS" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;1)&amp;0x1]"/>
109108
<item property="INVER" value="%d[(SecureFaultRegisters.SFSR&gt;&gt;2)&amp;0x1]"/>

‎configs/core-peripherals/Memory_Protection_Unit_V7M.scvd‎

Lines changed: 230 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,230 @@
1+
<?xml version="1.0" encoding="utf-8"?>
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<!--
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Copyright 2026 Arm Limited
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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https://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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-->
17+
<component_viewer schemaVersion="0.1" xmlns:xs="https://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="Component_Viewer.xsd">
18+
<component name="MemoryProtectionUnitV7MComponent" version="1.0.0"/>
19+
<typedefs>
20+
<typedef name="MPU_Registers_t" size="20">
21+
<member name="MPU_TYPE" type="uint32_t" offset="0x00"/>
22+
<member name="MPU_CTRL" type="uint32_t" offset="0x04"/>
23+
<member name="MPU_RNR" type="uint32_t" offset="0x08"/>
24+
<member name="MPU_RBAR" type="uint32_t" offset="0x0C"/>
25+
<member name="MPU_RASR" type="uint32_t" offset="0x10"/>
26+
</typedef>
27+
<typedef name="MPU_Region_t">
28+
<var name="Number" type="uint8_t" size="1"/>
29+
<var name="Enable" type="uint8_t" size="1"/>
30+
<var name="StartAddress" type="uint32_t" size="1"/>
31+
<var name="RegionSize" type="uint8_t" size="1">
32+
<enum name="Reserved" value="0x00"/>
33+
<enum name="Reserved" value="0x01"/>
34+
<enum name="Reserved" value="0x02"/>
35+
<enum name="Reserved" value="0x03"/>
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<enum name="32B" value="0x04"/>
37+
<enum name="64B" value="0x05"/>
38+
<enum name="128B" value="0x06"/>
39+
<enum name="256B" value="0x07"/>
40+
<enum name="512B" value="0x08"/>
41+
<enum name="1KB" value="0x09"/>
42+
<enum name="2KB" value="0x0A"/>
43+
<enum name="4KB" value="0x0B"/>
44+
<enum name="8KB" value="0x0C"/>
45+
<enum name="16KB" value="0x0D"/>
46+
<enum name="32KB" value="0x0E"/>
47+
<enum name="64KB" value="0x0F"/>
48+
<enum name="128KB" value="0x10"/>
49+
<enum name="256KB" value="0x11"/>
50+
<enum name="512KB" value="0x12"/>
51+
<enum name="1MB" value="0x13"/>
52+
<enum name="2MB" value="0x14"/>
53+
<enum name="4MB" value="0x15"/>
54+
<enum name="8MB" value="0x16"/>
55+
<enum name="16MB" value="0x17"/>
56+
<enum name="32MB" value="0x18"/>
57+
<enum name="64MB" value="0x19"/>
58+
<enum name="128MB" value="0x1A"/>
59+
<enum name="256MB" value="0x1B"/>
60+
<enum name="512MB" value="0x1C"/>
61+
<enum name="1GB" value="0x1D"/>
62+
<enum name="2GB" value="0x1E"/>
63+
<enum name="4GB" value="0x1F"/>
64+
</var>
65+
<var name="SubregionDisable" type="uint8_t" size="1"/>
66+
<var name="ExecuteNever" type="uint8_t" size="1">
67+
<enum name="X" value="0x0"/>
68+
<enum name="XN" value="0x1"/>
69+
</var>
70+
<var name="AccessPermissions" type="uint8_t" size="1">
71+
<enum name="Any access generates a permission fault" value="0x0"/>
72+
<enum name="Privileged access only" value="0x1"/>
73+
<enum name="Any unprivileged write generates a permission fault" value="0x2"/>
74+
<enum name="Full access" value="0x3"/>
75+
<enum name="Reserved" value="0x4"/>
76+
<enum name="Privileged read-only" value="0x5"/>
77+
<enum name="Privileged and unprivileged read-only" value="0x6"/>
78+
<enum name="Privileged and unprivileged read-only" value="0x7"/>
79+
</var>
80+
<var name="Shareability" type="uint8_t" size="1">
81+
<enum name="Non-shareable" value="0x0"/>
82+
<enum name="Shareable" value="0x1"/>
83+
<enum name="Reserved" value="0x2"/>
84+
<enum name="IMPLEMENTATION DEFINED" value="0x3"/>
85+
</var>
86+
<var name="Memorytype" type="uint8_t">
87+
<enum name="Strongly-ordered" value="0x0"/>
88+
<enum name="Device" value="0x1"/>
89+
<enum name="Normal" value="0x2"/>
90+
<enum name="Reserved" value="0x3"/>
91+
<enum name="IMPLEMENTATION DEFINED" value="0x4"/>
92+
</var>
93+
<var name="OuterPolicy" type="uint8_t">
94+
<enum name="Outer Non-cacheable" value="0x0"/>
95+
<enum name="Outer Write-Back, write and read allocate" value="0x1"/>
96+
<enum name="Outer Write-Through, no write allocate" value="0x2"/>
97+
<enum name="Outer Write-Back, no write allocate" value="0x3"/>
98+
</var>
99+
<var name="InnerPolicy" type="uint8_t">
100+
<enum name="Inner Non-cacheable" value="0x0"/>
101+
<enum name="Inner Write-Back, write and read allocate" value="0x1"/>
102+
<enum name="Inner Write-Through, no write allocate" value="0x2"/>
103+
<enum name="Inner Write-Back, no write allocate" value="0x3"/>
104+
</var>
105+
</typedef>
106+
</typedefs>
107+
<objects>
108+
<object name="MemoryProtectionUnitV7MObject">
109+
<read name="MPU_Registers" type="MPU_Registers_t" offset="0xE000ED90"/>
110+
<var name="MPU_Region" type="MPU_Region_t" value="0"/>
111+
<var name="TEXCB_Bits" type="uint8_t" value="0"/>
112+
<var name="S_Bit" type="uint8_t" value="0"/>
113+
<calc>
114+
MPU_Region.Number=(MPU_Registers.MPU_RNR&gt;&gt;0)&amp;0xFF;
115+
MPU_Region.Enable=(MPU_Registers.MPU_RASR&gt;&gt;0)&amp;0x1;
116+
MPU_Region.StartAddress=(MPU_Registers.MPU_RBAR&amp;0xFFFFFFE0);
117+
MPU_Region.RegionSize=(MPU_Registers.MPU_RASR&gt;&gt;1)&amp;0x1F;
118+
MPU_Region.SubregionDisable=(MPU_Registers.MPU_RASR&gt;&gt;8)&amp;0xFF;
119+
MPU_Region.ExecuteNever=(MPU_Registers.MPU_RASR&gt;&gt;28)&amp;0x1;
120+
MPU_Region.AccessPermissions=(MPU_Registers.MPU_RASR&gt;&gt;24)&amp;0x7;
121+
TEXCB_Bits=((MPU_Registers.MPU_RASR&gt;&gt;17)&amp;0x1C)|((MPU_Registers.MPU_RASR&gt;&gt;16)&amp;0x2)|((MPU_Registers.MPU_RASR&gt;&gt;16)&amp;0x1);
122+
S_Bit=(MPU_Registers.MPU_RASR&gt;&gt;18)&amp;0x1;
123+
</calc>
124+
<!-- Strongly ordered memory -->
125+
<calc cond="TEXCB_Bits==0x00">
126+
MPU_Region.Memorytype=0x0;
127+
MPU_Region.Shareability=0x1;
128+
MPU_Region.OuterPolicy=0x4;
129+
MPU_Region.InnerPolicy=0x4;
130+
</calc>
131+
<!-- Shared device memory -->
132+
<calc cond="TEXCB_Bits==0x01">
133+
MPU_Region.Memorytype=0x1;
134+
MPU_Region.Shareability=0x1;
135+
MPU_Region.OuterPolicy=0x4;
136+
MPU_Region.InnerPolicy=0x4;
137+
</calc>
138+
<!-- Normal memory -->
139+
<calc cond="(TEXCB_Bits&gt;0x01)&amp;&amp;(TEXCB_Bits&lt;0x05)">
140+
MPU_Region.Memorytype=0x2;
141+
MPU_Region.Shareability=S_Bit;
142+
MPU_Region.OuterPolicy=TEXCB_Bits&amp;0x3;
143+
MPU_Region.InnerPolicy=TEXCB_Bits&amp;0x3;
144+
</calc>
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<!-- Reserved memory -->
146+
<calc cond="TEXCB_Bits==0x05">
147+
MPU_Region.Memorytype=0x3;
148+
MPU_Region.Shareability=0x2;
149+
MPU_Region.OuterPolicy=0x4;
150+
MPU_Region.InnerPolicy=0x4;
151+
</calc>
152+
<!-- IMPLEMENTATION DEFINED memory -->
153+
<calc cond="TEXCB_Bits==0x06">
154+
MPU_Region.Memorytype=0x4;
155+
MPU_Region.Shareability=0x3;
156+
MPU_Region.OuterPolicy=0x4;
157+
MPU_Region.InnerPolicy=0x4;
158+
</calc>
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<!-- Normal memory -->
160+
<calc cond="TEXCB_Bits==0x07">
161+
MPU_Region.Memorytype=0x2;
162+
MPU_Region.Shareability=S_Bit;
163+
MPU_Region.OuterPolicy=0x1;
164+
MPU_Region.InnerPolicy=0x1;
165+
</calc>
166+
<!-- Non-shared device memory -->
167+
<calc cond="TEXCB_Bits==0x08" info="">
168+
MPU_Region.Memorytype=0x1;
169+
MPU_Region.Shareability=0x0;
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MPU_Region.OuterPolicy=0x4;
171+
MPU_Region.InnerPolicy=0x4;
172+
</calc>
173+
<!-- Reserved memory -->
174+
<calc cond="(TEXCB_Bits&gt;0x08)&amp;&amp;(TEXCB_Bits&lt;0x10)">
175+
MPU_Region.Memorytype=0x3;
176+
MPU_Region.Shareability=0x2;
177+
MPU_Region.OuterPolicy=0x4;
178+
MPU_Region.InnerPolicy=0x4;
179+
</calc>
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<!-- Normal memory -->
181+
<calc cond="(TEXCB_Bits&gt;0x09)">
182+
MPU_Region.Memorytype=0x2;
183+
MPU_Region.Shareability=S_Bit;
184+
MPU_Region.OuterPolicy=(TEXCB_Bits&gt;&gt;2)&amp;0x3;
185+
MPU_Region.InnerPolicy=TEXCB_Bits&amp;0x3;
186+
</calc>
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<out name="Memory Protection Unit">
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<item property="Type (MPU_TYPE)" value="%x[MPU_Registers.MPU_TYPE]">
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<item property="DREGION" value="%d[(MPU_Registers.MPU_TYPE&gt;&gt;8)&amp;0xFF]" info="Number of regions supported by the MPU."/>
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</item>
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<item property="Control (MPU_CTRL)" value="%x[MPU_Registers.MPU_CTRL]">
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<item property="ENABLE" value="%d[(MPU_Registers.MPU_CTRL&gt;&gt;0)&amp;0x1]"/>
193+
<item property="HFNMIENA" value="%d[(MPU_Registers.MPU_CTRL&gt;&gt;1)&amp;0x1]"/>
194+
<item property="PRIVDEFENA" value="%d[(MPU_Registers.MPU_CTRL&gt;&gt;2)&amp;0x1]"/>
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</item>
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<item property="Region Number (MPU_RNR)" value="%x[MPU_Registers.MPU_RNR]">
197+
<item property="REGION" value="%d[(MPU_Registers.MPU_RNR&gt;&gt;0)&amp;0xFF]"/>
198+
</item>
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<item property="Region Base Address (MPU_RBAR)" value="%x[MPU_Registers.MPU_RBAR]">
200+
<item property="REGION" value="%d[(MPU_Registers.MPU_RBAR&gt;&gt;0)&amp;0xF]"/>
201+
<item property="VALID" value="%x[(MPU_Registers.MPU_RBAR&gt;&gt;4)&amp;0x1]"/>
202+
<item property="ADDR" value="%x[(MPU_Registers.MPU_RBAR&gt;&gt;5)&amp;0x7FFFFFF]"/>
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</item>
204+
<item property="Region Attribute and Size (MPU_RASR)" value="%x[MPU_Registers.MPU_RASR]">
205+
<item property="ENABLE" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;0)&amp;0x1]"/>
206+
<item property="SIZE" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;1)&amp;0x1F]"/>
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<item property="SRD" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;8)&amp;0xFF]"/>
208+
<item property="B" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;16)&amp;0x1]"/>
209+
<item property="C" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;17)&amp;0x1]"/>
210+
<item property="S" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;18)&amp;0x1]"/>
211+
<item property="TEX" value="%x[(MPU_Registers.MPU_RASR&gt;&gt;19)&amp;0x7]"/>
212+
<item property="AP" value="%x[(MPU_Registers.MPU_RASR&gt;&gt;24)&amp;0x7]"/>
213+
<item property="XN" value="%d[(MPU_Registers.MPU_RASR&gt;&gt;28)&amp;0x1]"/>
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</item>
215+
<item property="Current Region" value="">
216+
<item property="Number" value="%d[MPU_Region.Number]"/>
217+
<item property="Enable" value="%t[MPU_Region.Enable ? &quot;yes&quot; : &quot;no&quot;]"/>
218+
<item property="Start Address" value="%x[MPU_Region.StartAddress]"/>
219+
<item property="Region Size" value="%E[MPU_Region.RegionSize]"/>
220+
<item property="Subregion Disable" value="%x[MPU_Region.SubregionDisable]"/>
221+
<item property="Execute Never" value="%E[MPU_Region.ExecuteNever]"/>
222+
<item property="Access permissions" value="%E[MPU_Region.AccessPermissions]"/>
223+
<item property="Shareability" value="%E[MPU_Region.Shareability]"/>
224+
<item property="Memory Type" value="%E[MPU_Region.Memorytype]"/>
225+
<item property="Cacheability" cond="MPU_Region.Memorytype==2" value="%E[MPU_Region.OuterPolicy]; %E[MPU_Region.InnerPolicy]"/>
226+
</item>
227+
</out>
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</object>
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</objects>
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</component_viewer>

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