diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/MX_Device/Board/MX_Device.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/MX_Device/Board/MX_Device.h deleted file mode 100644 index f7616b48f..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/MX_Device/Board/MX_Device.h +++ /dev/null @@ -1,191 +0,0 @@ -/****************************************************************************** - * File Name : MX_Device.h - * Date : 26/04/2024 00:23:13 - * Description : STM32Cube MX parameter definitions - * Note : This file is generated with a generator out of the - * STM32CubeMX project and its generated files (DO NOT EDIT!) - ******************************************************************************/ - -#ifndef MX_DEVICE_H__ -#define MX_DEVICE_H__ - -/* MX_Device.h version */ -#define MX_DEVICE_VERSION 0x01000000 - - -/*------------------------------ I2C1 -----------------------------*/ -#define MX_I2C1 1 - -/* Filter Settings */ -#define MX_I2C1_ANF_ENABLE 1 -#define MX_I2C1_DNF 0 - -/* Pins */ - -/* I2C1_SCL */ -#define MX_I2C1_SCL_Pin PB8 -#define MX_I2C1_SCL_GPIO_Pin GPIO_PIN_8 -#define MX_I2C1_SCL_GPIOx GPIOB -#define MX_I2C1_SCL_GPIO_Mode GPIO_MODE_AF_OD -#define MX_I2C1_SCL_GPIO_PuPd GPIO_NOPULL -#define MX_I2C1_SCL_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_I2C1_SCL_GPIO_AF GPIO_AF4_I2C1 - -/* I2C1_SDA */ -#define MX_I2C1_SDA_Pin PB9 -#define MX_I2C1_SDA_GPIO_Pin GPIO_PIN_9 -#define MX_I2C1_SDA_GPIOx GPIOB -#define MX_I2C1_SDA_GPIO_Mode GPIO_MODE_AF_OD -#define MX_I2C1_SDA_GPIO_PuPd GPIO_NOPULL -#define MX_I2C1_SDA_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_I2C1_SDA_GPIO_AF GPIO_AF4_I2C1 - -/*------------------------------ I2C2 -----------------------------*/ -#define MX_I2C2 1 - -/* Filter Settings */ -#define MX_I2C2_DNF 0 -#define MX_I2C2_ANF_ENABLE 1 - -/* Pins */ - -/* I2C2_SCL */ -#define MX_I2C2_SCL_Pin PH4 -#define MX_I2C2_SCL_GPIO_Pin GPIO_PIN_4 -#define MX_I2C2_SCL_GPIOx GPIOH -#define MX_I2C2_SCL_GPIO_Mode GPIO_MODE_AF_OD -#define MX_I2C2_SCL_GPIO_PuPd GPIO_NOPULL -#define MX_I2C2_SCL_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_I2C2_SCL_GPIO_AF GPIO_AF4_I2C2 - -/* I2C2_SDA */ -#define MX_I2C2_SDA_Pin PH5 -#define MX_I2C2_SDA_GPIO_Pin GPIO_PIN_5 -#define MX_I2C2_SDA_GPIOx GPIOH -#define MX_I2C2_SDA_GPIO_Mode GPIO_MODE_AF_OD -#define MX_I2C2_SDA_GPIO_PuPd GPIO_NOPULL -#define MX_I2C2_SDA_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_I2C2_SDA_GPIO_AF GPIO_AF4_I2C2 - -/*------------------------------ SPI2 -----------------------------*/ -#define MX_SPI2 1 - -/* Pins */ - -/* SPI2_MISO */ -#define MX_SPI2_MISO_Pin PD3 -#define MX_SPI2_MISO_GPIO_Pin GPIO_PIN_3 -#define MX_SPI2_MISO_GPIOx GPIOD -#define MX_SPI2_MISO_GPIO_Mode GPIO_MODE_AF_PP -#define MX_SPI2_MISO_GPIO_PuPd GPIO_NOPULL -#define MX_SPI2_MISO_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_SPI2_MISO_GPIO_AF GPIO_AF5_SPI2 - -/* SPI2_MOSI */ -#define MX_SPI2_MOSI_Pin PD4 -#define MX_SPI2_MOSI_GPIO_Pin GPIO_PIN_4 -#define MX_SPI2_MOSI_GPIOx GPIOD -#define MX_SPI2_MOSI_GPIO_Mode GPIO_MODE_AF_PP -#define MX_SPI2_MOSI_GPIO_PuPd GPIO_NOPULL -#define MX_SPI2_MOSI_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_SPI2_MOSI_GPIO_AF GPIO_AF5_SPI2 - -/* SPI2_NSS */ -#define MX_SPI2_NSS_Pin PB12 -#define MX_SPI2_NSS_GPIO_Pin GPIO_PIN_12 -#define MX_SPI2_NSS_GPIOx GPIOB -#define MX_SPI2_NSS_GPIO_Mode GPIO_MODE_AF_PP -#define MX_SPI2_NSS_GPIO_PuPd GPIO_NOPULL -#define MX_SPI2_NSS_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_SPI2_NSS_GPIO_AF GPIO_AF5_SPI2 - -/* SPI2_SCK */ -#define MX_SPI2_SCK_Pin PD1 -#define MX_SPI2_SCK_GPIO_Pin GPIO_PIN_1 -#define MX_SPI2_SCK_GPIOx GPIOD -#define MX_SPI2_SCK_GPIO_Mode GPIO_MODE_AF_PP -#define MX_SPI2_SCK_GPIO_PuPd GPIO_NOPULL -#define MX_SPI2_SCK_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_SPI2_SCK_GPIO_AF GPIO_AF5_SPI2 - -/*------------------------------ UART4 -----------------------------*/ -#define MX_UART4 1 - -/* Pins */ - -/* UART4_RX */ -#define MX_UART4_RX_Pin PC11 -#define MX_UART4_RX_GPIO_Pin GPIO_PIN_11 -#define MX_UART4_RX_GPIOx GPIOC -#define MX_UART4_RX_GPIO_Mode GPIO_MODE_AF_PP -#define MX_UART4_RX_GPIO_PuPd GPIO_NOPULL -#define MX_UART4_RX_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_UART4_RX_GPIO_AF GPIO_AF8_UART4 - -/* UART4_TX */ -#define MX_UART4_TX_Pin PC10 -#define MX_UART4_TX_GPIO_Pin GPIO_PIN_10 -#define MX_UART4_TX_GPIOx GPIOC -#define MX_UART4_TX_GPIO_Mode GPIO_MODE_AF_PP -#define MX_UART4_TX_GPIO_PuPd GPIO_NOPULL -#define MX_UART4_TX_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_UART4_TX_GPIO_AF GPIO_AF8_UART4 - -/*------------------------------ USART1 -----------------------------*/ -#define MX_USART1 1 - -/* Virtual mode */ -#define MX_USART1_VM VM_ASYNC -#define MX_USART1_VM_ASYNC 1 - -/* Pins */ - -/* USART1_RX */ -#define MX_USART1_RX_Pin PA10 -#define MX_USART1_RX_GPIO_Pin GPIO_PIN_10 -#define MX_USART1_RX_GPIOx GPIOA -#define MX_USART1_RX_GPIO_Mode GPIO_MODE_AF_PP -#define MX_USART1_RX_GPIO_PuPd GPIO_NOPULL -#define MX_USART1_RX_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_USART1_RX_GPIO_AF GPIO_AF7_USART1 - -/* USART1_TX */ -#define MX_USART1_TX_Pin PA9 -#define MX_USART1_TX_GPIO_Pin GPIO_PIN_9 -#define MX_USART1_TX_GPIOx GPIOA -#define MX_USART1_TX_GPIO_Mode GPIO_MODE_AF_PP -#define MX_USART1_TX_GPIO_PuPd GPIO_NOPULL -#define MX_USART1_TX_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_USART1_TX_GPIO_AF GPIO_AF7_USART1 - -/*------------------------------ USB_OTG_FS -----------------------------*/ -#define MX_USB_OTG_FS 1 - -/* Handle */ -#define MX_USB_OTG_FS_HANDLE hpcd_USB_OTG_FS - -/* Virtual mode */ -#define MX_USB_OTG_FS_VM Device_Only -#define MX_USB_OTG_FS_Device_Only 1 - -/* Pins */ - -/* USB_OTG_FS_DM */ -#define MX_USB_OTG_FS_DM_Pin PA11 -#define MX_USB_OTG_FS_DM_GPIO_Pin GPIO_PIN_11 -#define MX_USB_OTG_FS_DM_GPIOx GPIOA -#define MX_USB_OTG_FS_DM_GPIO_Mode GPIO_MODE_AF_PP -#define MX_USB_OTG_FS_DM_GPIO_PuPd GPIO_NOPULL -#define MX_USB_OTG_FS_DM_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_USB_OTG_FS_DM_GPIO_AF GPIO_AF10_USB - -/* USB_OTG_FS_DP */ -#define MX_USB_OTG_FS_DP_Pin PA12 -#define MX_USB_OTG_FS_DP_GPIO_Pin GPIO_PIN_12 -#define MX_USB_OTG_FS_DP_GPIOx GPIOA -#define MX_USB_OTG_FS_DP_GPIO_Mode GPIO_MODE_AF_PP -#define MX_USB_OTG_FS_DP_GPIO_PuPd GPIO_NOPULL -#define MX_USB_OTG_FS_DP_GPIO_Speed GPIO_SPEED_FREQ_LOW -#define MX_USB_OTG_FS_DP_GPIO_AF GPIO_AF10_USB - -#endif /* MX_DEVICE_H__ */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/.mxproject b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/.mxproject deleted file mode 100644 index 27bee35f1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/.mxproject +++ /dev/null @@ -1,14 +0,0 @@ -[PreviousLibFiles] -LibFiles=Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_mdf.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_dma.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_dma_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_def.h;Drivers\STM32U5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_i2c.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_i2c_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_rcc.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_rcc_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_cortex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_bus.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_rcc.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_crs.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_system.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_utils.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_flash.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_flash_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_gpio.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_gpio_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_gpio.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_dma.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_dmamux.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_exti.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_exti.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pwr.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pwr_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_pwr.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_cortex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_gtzc.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_icache.h;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_utils.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_exti.c;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_i2c.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_icache.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_ospi.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_dlyb.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_spi.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_spi.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_spi_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_tim.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_tim_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_uart.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_usart.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_lpuart.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_uart_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_ucpd.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_lpgpio.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pcd.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pcd_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_usb.h;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_mdf.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_dma.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_dma_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_i2c.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_i2c_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_rcc.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_rcc_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_cortex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_flash.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_flash_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_gpio.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_exti.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pwr.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pwr_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_gtzc.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_icache.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_ospi.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_dlyb.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_spi.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_spi_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_tim.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_tim_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_uart.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_uart_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_ucpd.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_gpio.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_lpgpio.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_dma.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pcd.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pcd_ex.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_usb.c;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_mdf.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_dma.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_dma_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_def.h;Drivers\STM32U5xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_i2c.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_i2c_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_rcc.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_rcc_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_cortex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_bus.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_rcc.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_crs.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_system.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_utils.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_flash.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_flash_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_gpio.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_gpio_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_gpio.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_dma.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_dmamux.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_exti.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_exti.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pwr.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pwr_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_pwr.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_cortex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_gtzc.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_icache.h;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_utils.c;Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_exti.c;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_i2c.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_icache.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_ospi.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_dlyb.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_spi.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_spi.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_spi_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_tim.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_tim_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_uart.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_usart.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_lpuart.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_uart_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_ucpd.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_lpgpio.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pcd.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_hal_pcd_ex.h;Drivers\STM32U5xx_HAL_Driver\Inc\stm32u5xx_ll_usb.h;Drivers\CMSIS\Device\ST\STM32U5xx\Include\stm32u585xx.h;Drivers\CMSIS\Device\ST\STM32U5xx\Include\stm32u5xx.h;Drivers\CMSIS\Device\ST\STM32U5xx\Include\system_stm32u5xx.h;Drivers\CMSIS\Device\ST\STM32U5xx\Source\Templates\system_stm32u5xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; - -[PreviousUsedKeilFiles] -SourceFiles=..\Src\main.c;..\Src\stm32u5xx_it.c;..\Src\stm32u5xx_hal_msp.c;..\Src\stm32u5xx_hal_timebase_tim.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_utils.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_exti.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_mdf.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_dma.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_dma_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_i2c.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_i2c_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_rcc.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_rcc_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_cortex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_flash.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_flash_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_gpio.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_exti.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pwr.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pwr_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_gtzc.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_icache.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_ospi.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_dlyb.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_spi.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_spi_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_tim.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_tim_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_uart.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_uart_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_ucpd.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_gpio.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_lpgpio.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_dma.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pcd.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pcd_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_usb.c;..\Drivers\CMSIS\Device\ST\STM32U5xx\Source\Templates\system_stm32u5xx.c;..\\Src\system_stm32u5xx.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_utils.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_exti.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_mdf.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_dma.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_dma_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_i2c.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_i2c_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_rcc.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_rcc_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_cortex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_flash.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_flash_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_gpio.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_exti.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pwr.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pwr_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_gtzc.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_icache.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_ospi.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_dlyb.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_spi.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_spi_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_tim.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_tim_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_uart.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_uart_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_ucpd.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_gpio.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_lpgpio.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_dma.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pcd.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_hal_pcd_ex.c;..\Drivers\STM32U5xx_HAL_Driver\Src\stm32u5xx_ll_usb.c;..\Drivers\CMSIS\Device\ST\STM32U5xx\Source\Templates\system_stm32u5xx.c;..\\Src\system_stm32u5xx.c;;; -HeaderPath=..\Drivers\STM32U5xx_HAL_Driver\Inc;..\Drivers\STM32U5xx_HAL_Driver\Inc\Legacy;..\Drivers\CMSIS\Device\ST\STM32U5xx\Include;..\Drivers\CMSIS\Include;..\Inc; -CDefines=USE_FULL_LL_DRIVER;USE_HAL_DRIVER;STM32U585xx;USE_FULL_LL_DRIVER;USE_HAL_DRIVER;USE_HAL_DRIVER; - -[PreviousGenFiles] -HeaderPath=..\Inc -HeaderFiles=stm32u5xx_it.h;stm32_assert.h;stm32u5xx_hal_conf.h;main.h; -SourcePath=..\Src -SourceFiles=stm32u5xx_it.c;stm32u5xx_hal_msp.c;stm32u5xx_hal_timebase_tim.c;main.c; - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h deleted file mode 100644 index d8e9056e9..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u585xx.h +++ /dev/null @@ -1,25115 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u585xx.h - * @author MCD Application Team - * @brief CMSIS STM32U585xx Device Peripheral Access Layer Header File. - * - * This file contains: - * - Data structures and the address mapping for all peripherals - * - Peripheral's registers declarations and bits definition - * - Macros to access peripheral's registers hardware - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -#ifndef STM32U585xx_H -#define STM32U585xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup ST - * @{ - */ - - -/** @addtogroup STM32U585xx - * @{ - */ - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* =========================================================================================================================== */ -/* ================ Interrupt Number Definition ================ */ -/* =========================================================================================================================== */ - -typedef enum -{ -/* ======================================= ARM Cortex-M33 Specific Interrupt Numbers ======================================= */ - Reset_IRQn = -15, /*!< -15 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< -14 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< -13 Hard Fault, all classes of Fault */ - MemoryManagement_IRQn = -12, /*!< -12 Memory Management, MPU mismatch, including Access Violation - and No Match */ - BusFault_IRQn = -11, /*!< -11 Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory - related Fault */ - UsageFault_IRQn = -10, /*!< -10 Usage Fault, i.e. Undef Instruction, Illegal State Transition */ - SecureFault_IRQn = -9, /*!< -9 Secure Fault */ - SVCall_IRQn = -5, /*!< -5 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< -4 Debug Monitor */ - PendSV_IRQn = -2, /*!< -2 Pendable request for system service */ - SysTick_IRQn = -1, /*!< -1 System Tick Timer */ - -/* =========================================== STM32U585xx Specific Interrupt Numbers ================================= */ - WWDG_IRQn = 0, /*!< Window WatchDog interrupt */ - PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */ - RTC_IRQn = 2, /*!< RTC non-secure interrupt */ - RTC_S_IRQn = 3, /*!< RTC secure interrupt */ - TAMP_IRQn = 4, /*!< Tamper global interrupt */ - RAMCFG_IRQn = 5, /*!< RAMCFG global interrupt */ - FLASH_IRQn = 6, /*!< FLASH non-secure global interrupt */ - FLASH_S_IRQn = 7, /*!< FLASH secure global interrupt */ - GTZC_IRQn = 8, /*!< Global TrustZone Controller interrupt */ - RCC_IRQn = 9, /*!< RCC non secure global interrupt */ - RCC_S_IRQn = 10, /*!< RCC secure global interrupt */ - EXTI0_IRQn = 11, /*!< EXTI Line0 interrupt */ - EXTI1_IRQn = 12, /*!< EXTI Line1 interrupt */ - EXTI2_IRQn = 13, /*!< EXTI Line2 interrupt */ - EXTI3_IRQn = 14, /*!< EXTI Line3 interrupt */ - EXTI4_IRQn = 15, /*!< EXTI Line4 interrupt */ - EXTI5_IRQn = 16, /*!< EXTI Line5 interrupt */ - EXTI6_IRQn = 17, /*!< EXTI Line6 interrupt */ - EXTI7_IRQn = 18, /*!< EXTI Line7 interrupt */ - EXTI8_IRQn = 19, /*!< EXTI Line8 interrupt */ - EXTI9_IRQn = 20, /*!< EXTI Line9 interrupt */ - EXTI10_IRQn = 21, /*!< EXTI Line10 interrupt */ - EXTI11_IRQn = 22, /*!< EXTI Line11 interrupt */ - EXTI12_IRQn = 23, /*!< EXTI Line12 interrupt */ - EXTI13_IRQn = 24, /*!< EXTI Line13 interrupt */ - EXTI14_IRQn = 25, /*!< EXTI Line14 interrupt */ - EXTI15_IRQn = 26, /*!< EXTI Line15 interrupt */ - IWDG_IRQn = 27, /*!< IWDG global interrupt */ - SAES_IRQn = 28, /*!< Secure AES global interrupt */ - GPDMA1_Channel0_IRQn = 29, /*!< GPDMA1 Channel 0 global interrupt */ - GPDMA1_Channel1_IRQn = 30, /*!< GPDMA1 Channel 1 global interrupt */ - GPDMA1_Channel2_IRQn = 31, /*!< GPDMA1 Channel 2 global interrupt */ - GPDMA1_Channel3_IRQn = 32, /*!< GPDMA1 Channel 3 global interrupt */ - GPDMA1_Channel4_IRQn = 33, /*!< GPDMA1 Channel 4 global interrupt */ - GPDMA1_Channel5_IRQn = 34, /*!< GPDMA1 Channel 5 global interrupt */ - GPDMA1_Channel6_IRQn = 35, /*!< GPDMA1 Channel 6 global interrupt */ - GPDMA1_Channel7_IRQn = 36, /*!< GPDMA1 Channel 7 global interrupt */ - ADC1_IRQn = 37, /*!< ADC1 global interrupt */ - DAC1_IRQn = 38, /*!< DAC1 global interrupt */ - FDCAN1_IT0_IRQn = 39, /*!< FDCAN1 interrupt 0 */ - FDCAN1_IT1_IRQn = 40, /*!< FDCAN1 interrupt 1 */ - TIM1_BRK_IRQn = 41, /*!< TIM1 Break interrupt */ - TIM1_UP_IRQn = 42, /*!< TIM1 Update interrupt */ - TIM1_TRG_COM_IRQn = 43, /*!< TIM1 Trigger and Commutation interrupt */ - TIM1_CC_IRQn = 44, /*!< TIM1 Capture Compare interrupt */ - TIM2_IRQn = 45, /*!< TIM2 global interrupt */ - TIM3_IRQn = 46, /*!< TIM3 global interrupt */ - TIM4_IRQn = 47, /*!< TIM4 global interrupt */ - TIM5_IRQn = 48, /*!< TIM5 global interrupt */ - TIM6_IRQn = 49, /*!< TIM6 global interrupt */ - TIM7_IRQn = 50, /*!< TIM7 global interrupt */ - TIM8_BRK_IRQn = 51, /*!< TIM8 Break interrupt */ - TIM8_UP_IRQn = 52, /*!< TIM8 Update interrupt */ - TIM8_TRG_COM_IRQn = 53, /*!< TIM8 Trigger and Commutation interrupt */ - TIM8_CC_IRQn = 54, /*!< TIM8 Capture Compare interrupt */ - I2C1_EV_IRQn = 55, /*!< I2C1 Event interrupt */ - I2C1_ER_IRQn = 56, /*!< I2C1 Error interrupt */ - I2C2_EV_IRQn = 57, /*!< I2C2 Event interrupt */ - I2C2_ER_IRQn = 58, /*!< I2C2 Error interrupt */ - SPI1_IRQn = 59, /*!< SPI1 global interrupt */ - SPI2_IRQn = 60, /*!< SPI2 global interrupt */ - USART1_IRQn = 61, /*!< USART1 global interrupt */ - USART2_IRQn = 62, /*!< USART2 global interrupt */ - USART3_IRQn = 63, /*!< USART3 global interrupt */ - UART4_IRQn = 64, /*!< UART4 global interrupt */ - UART5_IRQn = 65, /*!< UART5 global interrupt */ - LPUART1_IRQn = 66, /*!< LPUART1 global interrupt */ - LPTIM1_IRQn = 67, /*!< LPTIM1 global interrupt */ - LPTIM2_IRQn = 68, /*!< LPTIM2 global interrupt */ - TIM15_IRQn = 69, /*!< TIM15 global interrupt */ - TIM16_IRQn = 70, /*!< TIM16 global interrupt */ - TIM17_IRQn = 71, /*!< TIM17 global interrupt */ - COMP_IRQn = 72, /*!< COMP1 and COMP2 through EXTI Lines interrupts */ - OTG_FS_IRQn = 73, /*!< USB OTG FS global interrupt */ - CRS_IRQn = 74, /*!< CRS global interrupt */ - FMC_IRQn = 75, /*!< FSMC global interrupt */ - OCTOSPI1_IRQn = 76, /*!< OctoSPI1 global interrupt */ - PWR_S3WU_IRQn = 77, /*!< PWR wake up from Stop3 interrupt */ - SDMMC1_IRQn = 78, /*!< SDMMC1 global interrupt */ - SDMMC2_IRQn = 79, /*!< SDMMC2 global interrupt */ - GPDMA1_Channel8_IRQn = 80, /*!< GPDMA1 Channel 8 global interrupt */ - GPDMA1_Channel9_IRQn = 81, /*!< GPDMA1 Channel 9 global interrupt */ - GPDMA1_Channel10_IRQn = 82, /*!< GPDMA1 Channel 10 global interrupt */ - GPDMA1_Channel11_IRQn = 83, /*!< GPDMA1 Channel 11 global interrupt */ - GPDMA1_Channel12_IRQn = 84, /*!< GPDMA1 Channel 12 global interrupt */ - GPDMA1_Channel13_IRQn = 85, /*!< GPDMA1 Channel 13 global interrupt */ - GPDMA1_Channel14_IRQn = 86, /*!< GPDMA1 Channel 14 global interrupt */ - GPDMA1_Channel15_IRQn = 87, /*!< GPDMA1 Channel 15 global interrupt */ - I2C3_EV_IRQn = 88, /*!< I2C3 event interrupt */ - I2C3_ER_IRQn = 89, /*!< I2C3 error interrupt */ - SAI1_IRQn = 90, /*!< Serial Audio Interface 1 global interrupt */ - SAI2_IRQn = 91, /*!< Serial Audio Interface 2 global interrupt */ - TSC_IRQn = 92, /*!< Touch Sense Controller global interrupt */ - AES_IRQn = 93, /*!< AES global interrupt */ - RNG_IRQn = 94, /*!< RNG global interrupt */ - FPU_IRQn = 95, /*!< FPU global interrupt */ - HASH_IRQn = 96, /*!< HASH global interrupt */ - PKA_IRQn = 97, /*!< PKA global interrupt */ - LPTIM3_IRQn = 98, /*!< LPTIM3 global interrupt */ - SPI3_IRQn = 99, /*!< SPI3 global interrupt */ - I2C4_ER_IRQn = 100, /*!< I2C4 Error interrupt */ - I2C4_EV_IRQn = 101, /*!< I2C4 Event interrupt */ - MDF1_FLT0_IRQn = 102, /*!< MDF1 Filter 0 global interrupt */ - MDF1_FLT1_IRQn = 103, /*!< MDF1 Filter 1 global interrupt */ - MDF1_FLT2_IRQn = 104, /*!< MDF1 Filter 2 global interrupt */ - MDF1_FLT3_IRQn = 105, /*!< MDF1 Filter 3 global interrupt */ - UCPD1_IRQn = 106, /*!< UCPD1 global interrupt */ - ICACHE_IRQn = 107, /*!< Instruction cache global interrupt */ - OTFDEC1_IRQn = 108, /*!< OTFDEC1 global interrupt */ - OTFDEC2_IRQn = 109, /*!< OTFDEC2 global interrupt */ - LPTIM4_IRQn = 110, /*!< LPTIM4 global interrupt */ - DCACHE1_IRQn = 111, /*!< Data cache global interrupt */ - ADF1_IRQn = 112, /*!< ADF interrupt */ - ADC4_IRQn = 113, /*!< ADC4 (12bits) global interrupt */ - LPDMA1_Channel0_IRQn = 114, /*!< LPDMA1 SmartRun Channel 0 global interrupt */ - LPDMA1_Channel1_IRQn = 115, /*!< LPDMA1 SmartRun Channel 1 global interrupt */ - LPDMA1_Channel2_IRQn = 116, /*!< LPDMA1 SmartRun Channel 2 global interrupt */ - LPDMA1_Channel3_IRQn = 117, /*!< LPDMA1 SmartRun Channel 3 global interrupt */ - DMA2D_IRQn = 118, /*!< DMA2D global interrupt */ - DCMI_PSSI_IRQn = 119, /*!< DCMI/PSSI global interrupt */ - OCTOSPI2_IRQn = 120, /*!< OCTOSPI2 global interrupt */ - MDF1_FLT4_IRQn = 121, /*!< MDF1 Filter 4 global interrupt */ - MDF1_FLT5_IRQn = 122, /*!< MDF1 Filter 5 global interrupt */ - CORDIC_IRQn = 123, /*!< CORDIC global interrupt */ - FMAC_IRQn = 124, /*!< FMAC global interrupt */ - LSECSSD_IRQn = 125, /*!< LSECSSD and MSI_PLL_UNLOCK global interrupts */ -} IRQn_Type; - -/* =========================================================================================================================== */ -/* ================ Processor and Core Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/* ------- Start of section using anonymous unions and disabling warnings ------- */ -#if defined (__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined (__ICCARM__) - #pragma language=extended -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wc11-extensions" - #pragma clang diagnostic ignored "-Wreserved-id-macro" -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning 586 -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - -/* -------- Configuration of the Cortex-M33 Processor and Core Peripherals ------ */ -#define __CM33_REV 0x0000U /* Core revision r0p1 */ -#define __SAUREGION_PRESENT 1U /* SAU regions present */ -#define __MPU_PRESENT 1U /* MPU present */ -#define __VTOR_PRESENT 1U /* VTOR present */ -#define __NVIC_PRIO_BITS 4U /* Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0U /* Set to 1 if different SysTick Config is used */ -#define __FPU_PRESENT 1U /* FPU present */ -#define __DSP_PRESENT 1U /* DSP extension present */ - -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include /*!< ARM Cortex-M33 processor and core peripherals */ -#include "system_stm32u5xx.h" /*!< STM32U5xx System */ - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup STM32U5xx_peripherals - * @{ - */ - -/** - * @brief CRC calculation unit - */ -typedef struct -{ - __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ - __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ - uint32_t RESERVED2; /*!< Reserved, 0x0C */ - __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */ - __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */ - uint32_t RESERVED3[246]; /*!< Reserved, */ - __IO uint32_t HWCFGR; /*!< CRC IP HWCFGR register, Address offset: 0x3F0 */ - __IO uint32_t VERR; /*!< CRC IP version register, Address offset: 0x3F4 */ - __IO uint32_t PIDR; /*!< CRC IP type identification register, Address offset: 0x3F8 */ - __IO uint32_t SIDR; /*!< CRC IP map Size ID register, Address offset: 0x3FC */ -} CRC_TypeDef; - -/** - * @brief Inter-integrated Circuit Interface - */ -typedef struct -{ - __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */ - __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */ - __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */ - __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */ - __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */ - __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */ - __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */ - __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */ - __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */ - __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */ - __IO uint32_t AUTOCR; -} I2C_TypeDef; - -/** - * @brief DAC - */ -typedef struct -{ - __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */ - __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */ - __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */ - __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */ - __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */ - __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */ - __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */ - __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */ - __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */ - __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */ - __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */ - __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */ - __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */ - __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */ - __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */ - __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */ - __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */ - __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */ - __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */ - __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */ - __IO uint32_t RESERVED[1]; - __IO uint32_t AUTOCR; /*!< DAC Autonomous mode register, Address offset: 0x54 */ -} DAC_TypeDef; - -/** - * @brief Clock Recovery System - */ -typedef struct -{ -__IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */ -__IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */ -__IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */ -__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ -} CRS_TypeDef; - -/** - * @brief AES hardware accelerator - */ -typedef struct -{ - __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */ - __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */ - __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */ - __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */ - __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */ - __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */ - __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */ - __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */ - __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */ - __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */ - __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */ - __IO uint32_t KEYR4; /*!< AES key register 4, Address offset: 0x30 */ - __IO uint32_t KEYR5; /*!< AES key register 5, Address offset: 0x34 */ - __IO uint32_t KEYR6; /*!< AES key register 6, Address offset: 0x38 */ - __IO uint32_t KEYR7; /*!< AES key register 7, Address offset: 0x3C */ - __IO uint32_t SUSP0R; /*!< AES Suspend register 0, Address offset: 0x40 */ - __IO uint32_t SUSP1R; /*!< AES Suspend register 1, Address offset: 0x44 */ - __IO uint32_t SUSP2R; /*!< AES Suspend register 2, Address offset: 0x48 */ - __IO uint32_t SUSP3R; /*!< AES Suspend register 3, Address offset: 0x4C */ - __IO uint32_t SUSP4R; /*!< AES Suspend register 4, Address offset: 0x50 */ - __IO uint32_t SUSP5R; /*!< AES Suspend register 5, Address offset: 0x54 */ - __IO uint32_t SUSP6R; /*!< AES Suspend register 6, Address offset: 0x58 */ - __IO uint32_t SUSP7R; /*!< AES Suspend register 7, Address offset: 0x5C */ - uint32_t RESERVED1[168];/*!< Reserved, Address offset: 0x60 -- 0x2FC */ - __IO uint32_t IER; /*!< AES Interrupt Enable Register, Address offset: 0x300 */ - __IO uint32_t ISR; /*!< AES Interrupt Status Register, Address offset: 0x304 */ - __IO uint32_t ICR; /*!< AES Interrupt Clear Register, Address offset: 0x308 */ -} AES_TypeDef; - -/** - * @brief HASH - */ -typedef struct -{ - __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */ - __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */ - __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */ - __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */ - __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */ - __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */ - uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */ - __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */ -} HASH_TypeDef; - -/** - * @brief HASH_DIGEST - */ -typedef struct -{ - __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */ -} HASH_DIGEST_TypeDef; - -/** - * @brief RNG - */ -typedef struct -{ - __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */ - __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ - __IO uint32_t NSCR; /*!< RNG noise source control register , Address offset: 0x0C */ - __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */ -} RNG_TypeDef; - -/** - * @brief Debug MCU - */ -typedef struct -{ - __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ - __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */ - __IO uint32_t APB1FZR1; /*!< Debug MCU APB1 freeze register 1, Address offset: 0x08 */ - __IO uint32_t APB1FZR2; /*!< Debug MCU APB1 freeze register 2, Address offset: 0x0C */ - __IO uint32_t APB2FZR; /*!< Debug MCU APB2 freeze register, Address offset: 0x10 */ - __IO uint32_t APB3FZR; /*!< Debug MCU APB3 freeze register, Address offset: 0x14 */ - uint32_t RESERVED1[2];/*!< Reserved, 0x18 - 0x1C */ - __IO uint32_t AHB1FZR; /*!< Debug MCU AHB1 freeze register, Address offset: 0x20 */ - uint32_t RESERVED2; /*!< Reserved, 0x24 */ - __IO uint32_t AHB3FZR; /*!< Debug MCU AHB3 freeze register, Address offset: 0x28 */ -} DBGMCU_TypeDef; - -/** - * @brief DCMI - */ -typedef struct -{ - __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */ - __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */ - __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */ - __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */ - __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */ - __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */ - __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */ - __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */ - __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */ -} DCMI_TypeDef; - -/** - * @brief DMA Controller - */ -typedef struct -{ - __IO uint32_t SECCFGR; /*!< DMA secure configuration register, Address offset: 0x00 */ - __IO uint32_t PRIVCFGR; /*!< DMA privileged configuration register, Address offset: 0x04 */ - __IO uint32_t RCFGLOCKR; /*!< DMA lock configuration register, Address offset: 0x08 */ - __IO uint32_t MISR; /*!< DMA non secure masked interrupt status register, Address offset: 0x0C */ - __IO uint32_t SMISR; /*!< DMA secure masked interrupt status register, Address offset: 0x10 */ -} DMA_TypeDef; - -typedef struct -{ - __IO uint32_t CLBAR; /*!< DMA channel x linked-list base address register, Address offset: 0x50 + (x * 0x80) */ - uint32_t RESERVED1[2]; /*!< Reserved 1, Address offset: 0x54 -- 0x58 */ - __IO uint32_t CFCR; /*!< DMA channel x flag clear register, Address offset: 0x5C + (x * 0x80) */ - __IO uint32_t CSR; /*!< DMA channel x flag status register, Address offset: 0x60 + (x * 0x80) */ - __IO uint32_t CCR; /*!< DMA channel x control register, Address offset: 0x64 + (x * 0x80) */ - uint32_t RESERVED2[10];/*!< Reserved 2, Address offset: 0x68 -- 0x8C */ - __IO uint32_t CTR1; /*!< DMA channel x transfer register 1, Address offset: 0x90 + (x * 0x80) */ - __IO uint32_t CTR2; /*!< DMA channel x transfer register 2, Address offset: 0x94 + (x * 0x80) */ - __IO uint32_t CBR1; /*!< DMA channel x block register 1, Address offset: 0x98 + (x * 0x80) */ - __IO uint32_t CSAR; /*!< DMA channel x source address register, Address offset: 0x9C + (x * 0x80) */ - __IO uint32_t CDAR; /*!< DMA channel x destination address register, Address offset: 0xA0 + (x * 0x80) */ - __IO uint32_t CTR3; /*!< DMA channel x transfer register 3, Address offset: 0xA4 + (x * 0x80) */ - __IO uint32_t CBR2; /*!< DMA channel x block register 2, Address offset: 0xA8 + (x * 0x80) */ - uint32_t RESERVED3[8]; /*!< Reserved 3, Address offset: 0xAC -- 0xC8 */ - __IO uint32_t CLLR; /*!< DMA channel x linked-list address register, Address offset: 0xCC + (x * 0x80) */ -} DMA_Channel_TypeDef; - -/** - * @brief DMA2D Controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */ - __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */ - __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */ - __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */ - __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */ - __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */ - __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */ - __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */ - __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */ - __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */ - __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */ - __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */ - __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */ - __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */ - __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */ - __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */ - __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */ - __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */ - __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */ - __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */ - uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FC */ - __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FC */ - __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFC */ -} DMA2D_TypeDef; - -/** - * @brief Asynch Interrupt/Event Controller (EXTI) - */ -typedef struct -{ - __IO uint32_t RTSR1; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ - __IO uint32_t FTSR1; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ - __IO uint32_t SWIER1; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ - __IO uint32_t RPR1; /*!< EXTI Rising Pending Register 1, Address offset: 0x0C */ - __IO uint32_t FPR1; /*!< EXTI Falling Pending Register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR1; /*!< EXTI Security Configuration Register 1, Address offset: 0x14 */ - __IO uint32_t PRIVCFGR1; /*!< EXTI Privilege Configuration Register 1, Address offset: 0x18 */ - uint32_t RESERVED1[17]; /*!< Reserved 1, 0x1C -- 0x5C */ - __IO uint32_t EXTICR[4]; /*!< EXIT External Interrupt Configuration Register, 0x60 -- 0x6C */ - __IO uint32_t LOCKR; /*!< EXTI Lock Register, Address offset: 0x70 */ - uint32_t RESERVED2[3]; /*!< Reserved 2, 0x74 -- 0x7C */ - __IO uint32_t IMR1; /*!< EXTI Interrupt Mask Register 1, Address offset: 0x80 */ - __IO uint32_t EMR1; /*!< EXTI Event Mask Register 1, Address offset: 0x84 */ -} EXTI_TypeDef; - -/** - * @brief FLASH Registers - */ -typedef struct -{ - __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */ - uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ - __IO uint32_t NSKEYR; /*!< FLASH non-secure key register, Address offset: 0x08 */ - __IO uint32_t SECKEYR; /*!< FLASH secure key register, Address offset: 0x0C */ - __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x10 */ - __IO uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x14 */ - __IO uint32_t PDKEY1R; /*!< FLASH Bank 1 power-down key register, Address offset: 0x18 */ - __IO uint32_t PDKEY2R; /*!< FLASH Bank 2 power-down key register, Address offset: 0x1C */ - __IO uint32_t NSSR; /*!< FLASH non-secure status register, Address offset: 0x20 */ - __IO uint32_t SECSR; /*!< FLASH secure status register, Address offset: 0x24 */ - __IO uint32_t NSCR; /*!< FLASH non-secure control register, Address offset: 0x28 */ - __IO uint32_t SECCR; /*!< FLASH secure control register, Address offset: 0x2C */ - __IO uint32_t ECCR; /*!< FLASH ECC register, Address offset: 0x30 */ - __IO uint32_t OPSR; /*!< FLASH OPSR register, Address offset: 0x34 */ - uint32_t RESERVED3[2]; /*!< Reserved3, Address offset: 0x38-0x3C */ - __IO uint32_t OPTR; /*!< FLASH option control register, Address offset: 0x40 */ - __IO uint32_t NSBOOTADD0R; /*!< FLASH non-secure boot address 0 register, Address offset: 0x44 */ - __IO uint32_t NSBOOTADD1R; /*!< FLASH non-secure boot address 1 register, Address offset: 0x48 */ - __IO uint32_t SECBOOTADD0R; /*!< FLASH secure boot address 0 register, Address offset: 0x4C */ - __IO uint32_t SECWM1R1; /*!< FLASH secure watermark1 register 1, Address offset: 0x50 */ - __IO uint32_t SECWM1R2; /*!< FLASH secure watermark1 register 2, Address offset: 0x54 */ - __IO uint32_t WRP1AR; /*!< FLASH WRP1 area A address register, Address offset: 0x58 */ - __IO uint32_t WRP1BR; /*!< FLASH WRP1 area B address register, Address offset: 0x5C */ - __IO uint32_t SECWM2R1; /*!< FLASH secure watermark2 register 1, Address offset: 0x60 */ - __IO uint32_t SECWM2R2; /*!< FLASH secure watermark2 register 2, Address offset: 0x64 */ - __IO uint32_t WRP2AR; /*!< FLASH WRP2 area A address register, Address offset: 0x68 */ - __IO uint32_t WRP2BR; /*!< FLASH WRP2 area B address register, Address offset: 0x6C */ - __IO uint32_t OEM1KEYR1; /*!< FLASH OEM1 key register 1, Address offset: 0x70 */ - __IO uint32_t OEM1KEYR2; /*!< FLASH OEM1 key register 2, Address offset: 0x74 */ - __IO uint32_t OEM2KEYR1; /*!< FLASH OEM2 key register 1, Address offset: 0x78 */ - __IO uint32_t OEM2KEYR2; /*!< FLASH OEM2 key register 2, Address offset: 0x7C */ - __IO uint32_t SECBB1R1; /*!< FLASH secure block-based bank 1 register 1, Address offset: 0x80 */ - __IO uint32_t SECBB1R2; /*!< FLASH secure block-based bank 1 register 2, Address offset: 0x84 */ - __IO uint32_t SECBB1R3; /*!< FLASH secure block-based bank 1 register 3, Address offset: 0x88 */ - __IO uint32_t SECBB1R4; /*!< FLASH secure block-based bank 1 register 4, Address offset: 0x8C */ - uint32_t RESERVED4[4]; /*!< Reserved4, Address offset: 0x90-0x9C */ - __IO uint32_t SECBB2R1; /*!< FLASH secure block-based bank 2 register 1, Address offset: 0xA0 */ - __IO uint32_t SECBB2R2; /*!< FLASH secure block-based bank 2 register 2, Address offset: 0xA4 */ - __IO uint32_t SECBB2R3; /*!< FLASH secure block-based bank 2 register 3, Address offset: 0xA8 */ - __IO uint32_t SECBB2R4; /*!< FLASH secure block-based bank 2 register 4, Address offset: 0xAC */ - uint32_t RESERVED5[4]; /*!< Reserved5, Address offset: 0xB0-0xBC */ - __IO uint32_t SECHDPCR; /*!< FLASH secure HDP control register, Address offset: 0xC0 */ - __IO uint32_t PRIVCFGR; /*!< FLASH privilege configuration register, Address offset: 0xC4 */ - uint32_t RESERVED6[2]; /*!< Reserved6, Address offset: 0xC8-0xCC */ - __IO uint32_t PRIVBB1R1; /*!< FLASH privilege block-based bank 1 register 1, Address offset: 0xD0 */ - __IO uint32_t PRIVBB1R2; /*!< FLASH privilege block-based bank 1 register 2, Address offset: 0xD4 */ - __IO uint32_t PRIVBB1R3; /*!< FLASH privilege block-based bank 1 register 3, Address offset: 0xD8 */ - __IO uint32_t PRIVBB1R4; /*!< FLASH privilege block-based bank 1 register 4, Address offset: 0xDC */ - uint32_t RESERVED7[4]; /*!< Reserved7, Address offset: 0xE0-0xEC */ - __IO uint32_t PRIVBB2R1; /*!< FLASH privilege block-based bank 2 register 1, Address offset: 0xF0 */ - __IO uint32_t PRIVBB2R2; /*!< FLASH privilege block-based bank 2 register 2, Address offset: 0xF4 */ - __IO uint32_t PRIVBB2R3; /*!< FLASH privilege block-based bank 2 register 3, Address offset: 0xF8 */ - __IO uint32_t PRIVBB2R4; /*!< FLASH privilege block-based bank 2 register 4, Address offset: 0xFC */ -} FLASH_TypeDef; - -/** - * @brief FMAC - */ -typedef struct -{ - __IO uint32_t X1BUFCFG; /*!< FMAC X1 Buffer Configuration register, Address offset: 0x00 */ - __IO uint32_t X2BUFCFG; /*!< FMAC X2 Buffer Configuration register, Address offset: 0x04 */ - __IO uint32_t YBUFCFG; /*!< FMAC Y Buffer Configuration register, Address offset: 0x08 */ - __IO uint32_t PARAM; /*!< FMAC Parameter register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< FMAC Control register, Address offset: 0x10 */ - __IO uint32_t SR; /*!< FMAC Status register, Address offset: 0x14 */ - __IO uint32_t WDATA; /*!< FMAC Write Data register, Address offset: 0x18 */ - __IO uint32_t RDATA; /*!< FMAC Read Data register, Address offset: 0x1C */ -} FMAC_TypeDef; - -/** - * @brief General Purpose I/O - */ -typedef struct -{ - __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ - __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ - __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ - __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ - __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ - __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ - __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ - __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ - __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ - __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ - __IO uint32_t HSLVR; /*!< GPIO high-speed low voltage register, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< GPIO secure configuration register, Address offset: 0x30 */ -} GPIO_TypeDef; - -/** - * @brief Global TrustZone Controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< TZSC control register, Address offset: 0x00 */ - uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ - __IO uint32_t SECCFGR1; /*!< TZSC secure configuration register 1, Address offset: 0x10 */ - __IO uint32_t SECCFGR2; /*!< TZSC secure configuration register 2, Address offset: 0x14 */ - __IO uint32_t SECCFGR3; /*!< TZSC secure configuration register 3, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved2, Address offset: 0x1C */ - __IO uint32_t PRIVCFGR1; /*!< TZSC privilege configuration register 1, Address offset: 0x20 */ - __IO uint32_t PRIVCFGR2; /*!< TZSC privilege configuration register 2, Address offset: 0x24 */ - __IO uint32_t PRIVCFGR3; /*!< TZSC privilege configuration register 3, Address offset: 0x28 */ - uint32_t RESERVED3[5]; /*!< Reserved3, Address offset: 0x2C-0x3C */ - __IO uint32_t MPCWM1ACFGR; /*!< TZSC memory 1 sub-region A watermark configuration register, Address offset: 0x40 */ - __IO uint32_t MPCWM1AR; /*!< TZSC memory 1 sub-region A watermark register, Address offset: 0x44 */ - __IO uint32_t MPCWM1BCFGR; /*!< TZSC memory 1 sub-region B watermark configuration register, Address offset: 0x48 */ - __IO uint32_t MPCWM1BR; /*!< TZSC memory 1 sub-region B watermark register, Address offset: 0x4C */ - __IO uint32_t MPCWM2ACFGR; /*!< TZSC memory 2 sub-region A watermark configuration register, Address offset: 0x50 */ - __IO uint32_t MPCWM2AR; /*!< TZSC memory 2 sub-region A watermark register, Address offset: 0x54 */ - __IO uint32_t MPCWM2BCFGR; /*!< TZSC memory 2 sub-region B watermark configuration register, Address offset: 0x58 */ - __IO uint32_t MPCWM2BR; /*!< TZSC memory 2 sub-region B watermark register, Address offset: 0x5C */ - __IO uint32_t MPCWM3ACFGR; /*!< TZSC memory 3 sub-region A watermark configuration register, Address offset: 0x60 */ - __IO uint32_t MPCWM3AR; /*!< TZSC memory 3 sub-region A watermark register, Address offset: 0x64 */ - uint32_t RESERVED4[2]; /*!< Reserved4, Address offset: 0x68-0x6C */ - __IO uint32_t MPCWM4ACFGR; /*!< TZSC memory 4 sub-region A watermark configuration register, Address offset: 0x70 */ - __IO uint32_t MPCWM4AR; /*!< TZSC memory 4 sub-region A watermark register, Address offset: 0x74 */ - uint32_t RESERVED5[2]; /*!< Reserved5, Address offset: 0x78-0x7C */ - __IO uint32_t MPCWM5ACFGR; /*!< TZSC memory 5 sub-region A watermark configuration register, Address offset: 0x80 */ - __IO uint32_t MPCWM5AR; /*!< TZSC memory 5 sub-region A watermark register, Address offset: 0x84 */ - __IO uint32_t MPCWM5BCFGR; /*!< TZSC memory 5 sub-region B watermark configuration register, Address offset: 0x88 */ - __IO uint32_t MPCWM5BR; /*!< TZSC memory 5 sub-region B watermark register, Address offset: 0x8C */ -} GTZC_TZSC_TypeDef; - -typedef struct -{ - __IO uint32_t CR; /*!< MPCBBx control register, Address offset: 0x00 */ - uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x04-0x0C */ - __IO uint32_t CFGLOCKR1; /*!< MPCBBx Configuration lock register, Address offset: 0x10 */ - uint32_t RESERVED2[59]; /*!< Reserved2, Address offset: 0x14-0xFC */ - __IO uint32_t SECCFGR[32]; /*!< MPCBBx security configuration registers, Address offset: 0x100-0x180 */ - uint32_t RESERVED3[32]; /*!< Reserved3, Address offset: 0x180-0x200 */ - __IO uint32_t PRIVCFGR[32]; /*!< MPCBBx privilege configuration registers, Address offset: 0x200-0x280 */ -} GTZC_MPCBB_TypeDef; - -typedef struct -{ - __IO uint32_t IER1; /*!< TZIC interrupt enable register 1, Address offset: 0x00 */ - __IO uint32_t IER2; /*!< TZIC interrupt enable register 2, Address offset: 0x04 */ - __IO uint32_t IER3; /*!< TZIC interrupt enable register 3, Address offset: 0x08 */ - __IO uint32_t IER4; /*!< TZIC interrupt enable register 4, Address offset: 0x0C */ - __IO uint32_t SR1; /*!< TZIC status register 1, Address offset: 0x10 */ - __IO uint32_t SR2; /*!< TZIC status register 2, Address offset: 0x14 */ - __IO uint32_t SR3; /*!< TZIC status register 3, Address offset: 0x18 */ - __IO uint32_t SR4; /*!< TZIC status register 4, Address offset: 0x1C */ - __IO uint32_t FCR1; /*!< TZIC flag clear register 1, Address offset: 0x20 */ - __IO uint32_t FCR2; /*!< TZIC flag clear register 2, Address offset: 0x24 */ - __IO uint32_t FCR3; /*!< TZIC flag clear register 3, Address offset: 0x28 */ - __IO uint32_t FCR4; /*!< TZIC flag clear register 3, Address offset: 0x2C */ -} GTZC_TZIC_TypeDef; - -/** - * @brief Instruction Cache - */ -typedef struct -{ - __IO uint32_t CR; /*!< ICACHE control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< ICACHE status register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< ICACHE interrupt enable register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< ICACHE Flag clear register, Address offset: 0x0C */ - __IO uint32_t HMONR; /*!< ICACHE hit monitor register, Address offset: 0x10 */ - __IO uint32_t MMONR; /*!< ICACHE miss monitor register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ - __IO uint32_t CRR0; /*!< ICACHE region 0 configuration register, Address offset: 0x20 */ - __IO uint32_t CRR1; /*!< ICACHE region 1 configuration register, Address offset: 0x24 */ - __IO uint32_t CRR2; /*!< ICACHE region 2 configuration register, Address offset: 0x28 */ - __IO uint32_t CRR3; /*!< ICACHE region 3 configuration register, Address offset: 0x2C */ -} ICACHE_TypeDef; - -/** - * @brief Data Cache - */ -typedef struct -{ - __IO uint32_t CR; /*!< DCACHE control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< DCACHE status register, Address offset: 0x04 */ - __IO uint32_t IER; /*!< DCACHE interrupt enable register, Address offset: 0x08 */ - __IO uint32_t FCR; /*!< DCACHE Flag clear register, Address offset: 0x0C */ - __IO uint32_t RHMONR; /*!< DCACHE Read hit monitor register, Address offset: 0x10 */ - __IO uint32_t RMMONR; /*!< DCACHE Read miss monitor register, Address offset: 0x14 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x18-0x1C */ - __IO uint32_t WHMONR; /*!< DCACHE Write hit monitor register, Address offset: 0x20 */ - __IO uint32_t WMMONR; /*!< DCACHE Write miss monitor register, Address offset: 0x24 */ - __IO uint32_t CMDRSADDRR; /*!< DCACHE Command Start Address register, Address offset: 0x28 */ - __IO uint32_t CMDREADDRR; /*!< DCACHE Command End Address register, Address offset: 0x2C */ -} DCACHE_TypeDef; - -/** - * @brief PSSI - */ -typedef struct -{ - __IO uint32_t CR; /*!< PSSI control register, Address offset: 0x000 */ - __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */ - __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */ - __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */ - __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */ - __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */ - __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */ - __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */ -} PSSI_TypeDef; - -/** - * @brief TIM - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ - __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ - __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ - __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ - __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ - __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ - __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ - __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ - __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ - __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */ - __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ - __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ - __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ - __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ - __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ - __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ - __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ - __IO uint32_t CCR5; /*!< TIM capture/compare register 5, Address offset: 0x48 */ - __IO uint32_t CCR6; /*!< TIM capture/compare register 6, Address offset: 0x4C */ - __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x50 */ - __IO uint32_t DTR2; /*!< TIM deadtime register 2, Address offset: 0x54 */ - __IO uint32_t ECR; /*!< TIM encoder control register, Address offset: 0x58 */ - __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x5C */ - __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */ - __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */ - __IO uint32_t OR1 ; /*!< TIM option register, Address offset: 0x68 */ - uint32_t RESERVED0[220];/*!< Reserved, Address offset: 0x6C */ - __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x3DC */ - __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x3E0 */ -} TIM_TypeDef; - -/** - * @brief LPTIMER - */ -typedef struct -{ - __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ - __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ - __IO uint32_t DIER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ - __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ - __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ - __IO uint32_t CCR1; /*!< LPTIM Capture/Compare register 1, Address offset: 0x14 */ - __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ - __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ - __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t CFGR2; /*!< LPTIM Configuration register 2, Address offset: 0x24 */ - __IO uint32_t RCR; /*!< LPTIM Repetition register, Address offset: 0x28 */ - __IO uint32_t CCMR1; /*!< LPTIM Capture/Compare mode register, Address offset: 0x2C */ - __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x30 */ - __IO uint32_t CCR2; /*!< LPTIM Capture/Compare register 2, Address offset: 0x34 */ -} LPTIM_TypeDef; - -/** - * @brief Comparator - */ -typedef struct -{ - __IO uint32_t CSR; /*!< Comparator control and status register, Address offset: 0x00 */ -} COMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ - __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ -} COMP_Common_TypeDef; - -/** - * @brief Operational Amplifier (OPAMP) - */ -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */ - __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */ - __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */ -} OPAMP_TypeDef; - -typedef struct -{ - __IO uint32_t CSR; /*!< OPAMP control/status register, used for bits common to - several OPAMP instances, Address offset: 0x00 */ -} OPAMP_Common_TypeDef; - - -/** - * @brief MDF/ADF - */ -typedef struct -{ - __IO uint32_t GCR; /*!< MDF Global Control register, Address offset: 0x00 */ - __IO uint32_t CKGCR; /*!< MDF Clock Generator Control Register, Address offset: 0x04 */ - uint32_t RESERVED1[6]; /*!< Reserved, 0x08-0x1C */ - __IO uint32_t OR; /*!< MDF Option Register, Address offset: 0x20 */ -}MDF_TypeDef; - -/** - * @brief MDF/ADF filter - */ -typedef struct -{ - __IO uint32_t SITFCR; /*!< MDF Serial Interface Control Register, Address offset: 0x80 */ - __IO uint32_t BSMXCR; /*!< MDF Bitstream Matrix Control Register, Address offset: 0x84 */ - __IO uint32_t DFLTCR; /*!< MDF Digital Filter Control Register, Address offset: 0x88 */ - __IO uint32_t DFLTCICR; /*!< MDF MCIC Configuration Register, Address offset: 0x8C */ - __IO uint32_t DFLTRSFR; /*!< MDF Reshape Filter Configuration Register, Address offset: 0x90 */ - __IO uint32_t DFLTINTR; /*!< MDF Integrator Configuration Register, Address offset: 0x94 */ - __IO uint32_t OLDCR; /*!< MDF Out-Of Limit Detector Control Register, Address offset: 0x98 */ - __IO uint32_t OLDTHLR; /*!< MDF OLD Threshold Low Register, Address offset: 0x9C */ - __IO uint32_t OLDTHHR; /*!< MDF OLD Threshold High Register, Address offset: 0xA0 */ - __IO uint32_t DLYCR; /*!< MDF Delay control Register, Address offset: 0xA4 */ - __IO uint32_t SCDCR; /*!< MDF short circuit detector control Register, Address offset: 0xA8 */ - __IO uint32_t DFLTIER; /*!< MDF DFLT Interrupt enable Register, Address offset: 0xAC */ - __IO uint32_t DFLTISR; /*!< MDF DFLT Interrupt status Register, Address offset: 0xB0 */ - __IO uint32_t OECCR; /*!< MDF Offset Error Compensation Control Register, Address offset: 0xB4 */ - __IO uint32_t SADCR; /*!< MDF SAD Control Register, Address offset: 0xB8 */ - __IO uint32_t SADCFGR; /*!< MDF SAD configuration register, Address offset: 0xBC */ - __IO uint32_t SADSDLVR; /*!< MDF SAD Sound level Register, Address offset: 0xC0 */ - __IO uint32_t SADANLVR; /*!< MDF SAD Ambient Noise level Register, Address offset: 0xC4 */ - uint32_t RESERVED1[9]; /*!< Reserved, 0xC8-0xE8 */ - __IO uint32_t SNPSDR; /*!< MDF Snapshot Data Register, Address offset: 0xEC */ - __IO uint32_t DFLTDR; /*!< MDF Digital Filter Data Register, Address offset: 0xF0 */ -} MDF_Filter_TypeDef; - -/** - * @brief OCTO Serial Peripheral Interface - */ - -typedef struct -{ - __IO uint32_t CR; /*!< XSPI Control register, Address offset: 0x000 */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */ - __IO uint32_t DCR1; /*!< XSPI Device Configuration register 1, Address offset: 0x008 */ - __IO uint32_t DCR2; /*!< XSPI Device Configuration register 2, Address offset: 0x00C */ - __IO uint32_t DCR3; /*!< XSPI Device Configuration register 3, Address offset: 0x010 */ - __IO uint32_t DCR4; /*!< XSPI Device Configuration register 4, Address offset: 0x014 */ - uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */ - __IO uint32_t SR; /*!< XSPI Status register, Address offset: 0x020 */ - __IO uint32_t FCR; /*!< XSPI Flag Clear register, Address offset: 0x024 */ - uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */ - __IO uint32_t DLR; /*!< XSPI Data Length register, Address offset: 0x040 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */ - __IO uint32_t AR; /*!< XSPI Address register, Address offset: 0x048 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */ - __IO uint32_t DR; /*!< XSPI Data register, Address offset: 0x050 */ - uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */ - __IO uint32_t PSMKR; /*!< XSPI Polling Status Mask register, Address offset: 0x080 */ - uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */ - __IO uint32_t PSMAR; /*!< XSPI Polling Status Match register, Address offset: 0x088 */ - uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */ - __IO uint32_t PIR; /*!< XSPI Polling Interval register, Address offset: 0x090 */ - uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */ - __IO uint32_t CCR; /*!< XSPI Communication Configuration register, Address offset: 0x100 */ - uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */ - __IO uint32_t TCR; /*!< XSPI Timing Configuration register, Address offset: 0x108 */ - uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */ - __IO uint32_t IR; /*!< XSPI Instruction register, Address offset: 0x110 */ - uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */ - __IO uint32_t ABR; /*!< XSPI Alternate Bytes register, Address offset: 0x120 */ - uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */ - __IO uint32_t LPTR; /*!< XSPI Low Power Timeout register, Address offset: 0x130 */ - uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */ - __IO uint32_t WPCCR; /*!< XSPI Wrap Communication Configuration register, Address offset: 0x140 */ - uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */ - __IO uint32_t WPTCR; /*!< XSPI Wrap Timing Configuration register, Address offset: 0x148 */ - uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */ - __IO uint32_t WPIR; /*!< XSPI Wrap Instruction register, Address offset: 0x150 */ - uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */ - __IO uint32_t WPABR; /*!< XSPI Wrap Alternate Bytes register, Address offset: 0x160 */ - uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */ - __IO uint32_t WCCR; /*!< XSPI Write Communication Configuration register, Address offset: 0x180 */ - uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */ - __IO uint32_t WTCR; /*!< XSPI Write Timing Configuration register, Address offset: 0x188 */ - uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */ - __IO uint32_t WIR; /*!< XSPI Write Instruction register, Address offset: 0x190 */ - uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */ - __IO uint32_t WABR; /*!< XSPI Write Alternate Bytes register, Address offset: 0x1A0 */ - uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */ - __IO uint32_t HLCR; /*!< XSPI Hyperbus Latency Configuration register, Address offset: 0x200 */ -} XSPI_TypeDef; - -typedef XSPI_TypeDef OCTOSPI_TypeDef; - - -/** - * @brief OTFDEC register - */ -typedef struct -{ - __IO uint32_t REG_CONFIGR; /*!< OTFDEC Region Configuration register, Address offset: 0x20 + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_START_ADDR; /*!< OTFDEC Region Start Address register, Address offset: 0x24 + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_END_ADDR; /*!< OTFDEC Region End Address register, Address offset: 0x28 + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_NONCER0; /*!< OTFDEC Region Nonce register 0, Address offset: 0x2C + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_NONCER1; /*!< OTFDEC Region Nonce register 1, Address offset: 0x30 + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_KEYR0; /*!< OTFDEC Region Key register 0, Address offset: 0x34 + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_KEYR1; /*!< OTFDEC Region Key register 1, Address offset: 0x38 + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_KEYR2; /*!< OTFDEC Region Key register 2, Address offset: 0x3C + 0x30 * (x -1) (x = 1 to 4) */ - __IO uint32_t REG_KEYR3; /*!< OTFDEC Region Key register 3, Address offset: 0x40 + 0x30 * (x -1) (x = 1 to 4) */ -} OTFDEC_Region_TypeDef; - -typedef struct -{ - __IO uint32_t CR; /*!< OTFDEC Control register, Address offset: 0x000 */ - uint32_t RESERVED1[3]; /*!< Reserved, Address offset: 0x004-0x00C */ - __IO uint32_t PRIVCFGR; /*!< OTFDEC Privileged access control Configuration register, Address offset: 0x010 */ - uint32_t RESERVED2[187]; /*!< Reserved, Address offset: 0x014-0x2FC */ - __IO uint32_t ISR; /*!< OTFDEC Interrupt Status register, Address offset: 0x300 */ - __IO uint32_t ICR; /*!< OTFDEC Interrupt Clear register, Address offset: 0x304 */ - __IO uint32_t IER; /*!< OTFDEC Interrupt Enable register, Address offset: 0x308 */ -} OTFDEC_TypeDef; - - -/** - * @brief Serial Peripheral Interface IO Manager - */ -typedef struct -{ - __IO uint32_t CR; /*!< OCTOSPIM IO Manager Control register, Address offset: 0x00 */ - __IO uint32_t PCR[8]; /*!< OCTOSPIM IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */ -} XSPIM_TypeDef; - -typedef XSPIM_TypeDef OCTOSPIM_TypeDef; - -/** - * @brief Power Control - */ -typedef struct -{ - __IO uint32_t CR1; /*!< Power control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< Power control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< Power control register 3, Address offset: 0x08 */ - __IO uint32_t VOSR; /*!< Power voltage scaling register, Address offset: 0x0C */ - __IO uint32_t SVMCR; /*!< Power supply voltage monitoring control register, Address offset: 0x10 */ - __IO uint32_t WUCR1; /*!< Power wakeup control register 1, Address offset: 0x14 */ - __IO uint32_t WUCR2; /*!< Power wakeup control register 2, Address offset: 0x18 */ - __IO uint32_t WUCR3; /*!< Power wakeup control register 3, Address offset: 0x1C */ - __IO uint32_t BDCR1; /*!< Power backup domain control register 1, Address offset: 0x20 */ - __IO uint32_t BDCR2; /*!< Power backup domain control register 2, Address offset: 0x24 */ - __IO uint32_t DBPR; /*!< Power disable backup domain register, Address offset: 0x28 */ - __IO uint32_t UCPDR; /*!< Power USB Type-C and Power Delivery register, Address offset: 0x2C */ - __IO uint32_t SECCFGR; /*!< Power Security configuration register, Address offset: 0x30 */ - __IO uint32_t PRIVCFGR; /*!< Power privilege control register, Address offset: 0x34 */ - __IO uint32_t SR; /*!< Power status register, Address offset: 0x38 */ - __IO uint32_t SVMSR; /*!< Power supply voltage monitoring status register, Address offset: 0x3C */ - __IO uint32_t BDSR; /*!< Power backup domain status register, Address offset: 0x40 */ - __IO uint32_t WUSR; /*!< Power wakeup status register, Address offset: 0x44 */ - __IO uint32_t WUSCR; /*!< Power wakeup status clear register, Address offset: 0x48 */ - __IO uint32_t APCR; /*!< Power apply pull configuration register, Address offset: 0x4C */ - __IO uint32_t PUCRA; /*!< Power Port A pull-up control register, Address offset: 0x50 */ - __IO uint32_t PDCRA; /*!< Power Port A pull-down control register, Address offset: 0x54 */ - __IO uint32_t PUCRB; /*!< Power Port B pull-up control register, Address offset: 0x58 */ - __IO uint32_t PDCRB; /*!< Power Port B pull-down control register, Address offset: 0x5C */ - __IO uint32_t PUCRC; /*!< Power Port C pull-up control register, Address offset: 0x60 */ - __IO uint32_t PDCRC; /*!< Power Port C pull-down control register, Address offset: 0x64 */ - __IO uint32_t PUCRD; /*!< Power Port D pull-up control register, Address offset: 0x68 */ - __IO uint32_t PDCRD; /*!< Power Port D pull-down control register, Address offset: 0x6C */ - __IO uint32_t PUCRE; /*!< Power Port E pull-up control register, Address offset: 0x70 */ - __IO uint32_t PDCRE; /*!< Power Port E pull-down control register, Address offset: 0x74 */ - __IO uint32_t PUCRF; /*!< Power Port F pull-up control register, Address offset: 0x78 */ - __IO uint32_t PDCRF; /*!< Power Port F pull-down control register, Address offset: 0x7C */ - __IO uint32_t PUCRG; /*!< Power Port G pull-up control register, Address offset: 0x80 */ - __IO uint32_t PDCRG; /*!< Power Port G pull-down control register, Address offset: 0x84 */ - __IO uint32_t PUCRH; /*!< Power Port H pull-up control register, Address offset: 0x88 */ - __IO uint32_t PDCRH; /*!< Power Port H pull-down control register, Address offset: 0x8C */ - __IO uint32_t PUCRI; /*!< Power Port I pull-up control register, Address offset: 0x90 */ - __IO uint32_t PDCRI; /*!< Power Port I pull-down control register, Address offset: 0x94 */ -} PWR_TypeDef; - -/** - * @brief SRAMs configuration controller - */ -typedef struct -{ - __IO uint32_t CR; /*!< Control Register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< Interrupt Enable Register, Address offset: 0x04 */ - __IO uint32_t ISR; /*!< Interrupt Status Register, Address offset: 0x08 */ - __IO uint32_t SEAR; /*!< ECC Single Error Address Register, Address offset: 0x0C */ - __IO uint32_t DEAR; /*!< ECC Double Error Address Register, Address offset: 0x10 */ - __IO uint32_t ICR; /*!< Interrupt Clear Register, Address offset: 0x14 */ - __IO uint32_t WPR1; /*!< SRAM Write Protection Register 1, Address offset: 0x18 */ - __IO uint32_t WPR2; /*!< SRAM Write Protection Register 2, Address offset: 0x1C */ - uint32_t RESERVED; /*!< Reserved, Address offset: 0x20 */ - __IO uint32_t ECCKEY; /*!< SRAM ECC Key Register, Address offset: 0x24 */ - __IO uint32_t ERKEYR; /*!< SRAM Erase Key Register, Address offset: 0x28 */ -}RAMCFG_TypeDef; - -/** - * @brief Reset and Clock Control - */ -typedef struct -{ - __IO uint32_t CR; /*!< RCC clock control register Address offset: 0x00 */ - uint32_t RESERVED0; /*!< Reserved Address offset: 0x04 */ - __IO uint32_t ICSCR1; /*!< RCC internal clock sources calibration register 1 Address offset: 0x08 */ - __IO uint32_t ICSCR2; /*!< RCC internal clock sources calibration register 2 Address offset: 0x0C */ - __IO uint32_t ICSCR3; /*!< RCC internal clock sources calibration register 3 Address offset: 0x10 */ - __IO uint32_t CRRCR; /*!< RCC Clock Recovery RC Register Address offset: 0x14 */ - uint32_t RESERVED1; /*!< Reserved Address offset: 0x18 */ - __IO uint32_t CFGR1; /*!< RCC clock configuration register 1 Address offset: 0x1C */ - __IO uint32_t CFGR2; /*!< RCC clock configuration register 2 Address offset: 0x20 */ - __IO uint32_t CFGR3; /*!< RCC clock configuration register 3 Address offset: 0x24 */ - __IO uint32_t PLL1CFGR; /*!< PLL1 Configuration Register Address offset: 0x28 */ - __IO uint32_t PLL2CFGR; /*!< PLL2 Configuration Register Address offset: 0x2C */ - __IO uint32_t PLL3CFGR; /*!< PLL3 Configuration Register Address offset: 0x30 */ - __IO uint32_t PLL1DIVR; /*!< PLL1 Dividers Configuration Register Address offset: 0x34 */ - __IO uint32_t PLL1FRACR; /*!< PLL1 Fractional Divider Configuration Register Address offset: 0x38 */ - __IO uint32_t PLL2DIVR; /*!< PLL2 Dividers Configuration Register Address offset: 0x3C */ - __IO uint32_t PLL2FRACR; /*!< PLL2 Fractional Divider Configuration Register Address offset: 0x40 */ - __IO uint32_t PLL3DIVR; /*!< PLL3 Dividers Configuration Register Address offset: 0x44 */ - __IO uint32_t PLL3FRACR; /*!< PLL3 Fractional Divider Configuration Register Address offset: 0x48 */ - uint32_t RESERVED2; /*!< Reserved Address offset: 0x4C */ - __IO uint32_t CIER; /*!< Clock Interrupt Enable Register Address offset: 0x50 */ - __IO uint32_t CIFR; /*!< Clock Interrupt Flag Register Address offset: 0x54 */ - __IO uint32_t CICR; /*!< Clock Interrupt Clear Register Address offset: 0x58 */ - uint32_t RESERVED3; /*!< Reserved Address offset: 0x5C */ - __IO uint32_t AHB1RSTR; /*!< AHB1 Peripherals Reset Register Address offset: 0x60 */ - __IO uint32_t AHB2RSTR1; /*!< AHB2 Peripherals Reset Register 1 Address offset: 0x64 */ - __IO uint32_t AHB2RSTR2; /*!< AHB2 Peripherals Reset Register 2 Address offset: 0x68 */ - __IO uint32_t AHB3RSTR; /*!< AHB3 Peripherals Reset Register Address offset: 0x6C */ - uint32_t RESERVED4; /*!< Reserved Address offset: 0x70 */ - __IO uint32_t APB1RSTR1; /*!< APB1 Peripherals Reset Register 1 Address offset: 0x74 */ - __IO uint32_t APB1RSTR2; /*!< APB1 Peripherals Reset Register 2 Address offset: 0x78 */ - __IO uint32_t APB2RSTR; /*!< APB2 Peripherals Reset Register Address offset: 0x7C */ - __IO uint32_t APB3RSTR; /*!< APB3 Peripherals Reset Register Address offset: 0x80 */ - uint32_t RESERVED5; /*!< Reserved Address offset: 0x84 */ - __IO uint32_t AHB1ENR; /*!< AHB1 Peripherals Clock Enable Register Address offset: 0x88 */ - __IO uint32_t AHB2ENR1; /*!< AHB2 Peripherals Clock Enable Register 1 Address offset: 0x8C */ - __IO uint32_t AHB2ENR2; /*!< AHB2 Peripherals Clock Enable Register 2 Address offset: 0x90 */ - __IO uint32_t AHB3ENR; /*!< AHB3 Peripherals Clock Enable Register Address offset: 0x94 */ - uint32_t RESERVED6; /*!< Reserved Address offset: 0x98 */ - __IO uint32_t APB1ENR1; /*!< APB1 Peripherals Clock Enable Register 1 Address offset: 0x9C */ - __IO uint32_t APB1ENR2; /*!< APB1 Peripherals Clock Enable Register 2 Address offset: 0xA0 */ - __IO uint32_t APB2ENR; /*!< APB2 Peripherals Clock Enable Register Address offset: 0xA4 */ - __IO uint32_t APB3ENR; /*!< APB3 Peripherals Clock Enable Register Address offset: 0xA8 */ - uint32_t RESERVED7; /*!< Reserved Address offset: 0xAC */ - __IO uint32_t AHB1SMENR; /*!< AHB1 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xB0 */ - __IO uint32_t AHB2SMENR1; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xB4 */ - __IO uint32_t AHB2SMENR2; /*!< AHB2 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xB8 */ - __IO uint32_t AHB3SMENR; /*!< AHB3 Peripherals Clock Enable in Sleep and Stop Modes Register Address offset: 0xBC */ - uint32_t RESERVED8; /*!< Reserved Address offset: 0xC0 */ - __IO uint32_t APB1SMENR1; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xC4 */ - __IO uint32_t APB1SMENR2; /*!< APB1 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xC8 */ - __IO uint32_t APB2SMENR; /*!< APB2 Peripherals Clock Enable in Sleep and Stop Modes Register 1 Address offset: 0xCC */ - __IO uint32_t APB3SMENR; /*!< APB3 Peripherals Clock Enable in Sleep and Stop Modes Register 2 Address offset: 0xD0 */ - uint32_t RESERVED9; /*!< Reserved Address offset: 0xD4 */ - __IO uint32_t SRDAMR; /*!< SRD Autonomous Mode Register Address offset: 0xD8 */ - uint32_t RESERVED10; /*!< Reserved, Address offset: 0xDC */ - __IO uint32_t CCIPR1; /*!< IPs Clocks Configuration Register 1 Address offset: 0xE0 */ - __IO uint32_t CCIPR2; /*!< IPs Clocks Configuration Register 2 Address offset: 0xE4 */ - __IO uint32_t CCIPR3; /*!< IPs Clocks Configuration Register 3 Address offset: 0xE8 */ - uint32_t RESERVED11; /*!< Reserved, Address offset: 0xEC */ - __IO uint32_t BDCR; /*!< Backup Domain Control Register Address offset: 0xF0 */ - __IO uint32_t CSR; /*!< V33 Clock Control & Status Register Address offset: 0xF4 */ - uint32_t RESERVED[6]; /*!< Reserved Address offset: 0xF8 */ - __IO uint32_t SECCFGR; /*!< RCC secure configuration register Address offset: 0x110 */ - __IO uint32_t PRIVCFGR; /*!< RCC privilege configuration register Address offset: 0x114 */ -} RCC_TypeDef; - -/** - * @brief PKA - */ -typedef struct -{ - __IO uint32_t CR; /*!< PKA control register, Address offset: 0x00 */ - __IO uint32_t SR; /*!< PKA status register, Address offset: 0x04 */ - __IO uint32_t CLRFR; /*!< PKA clear flag register, Address offset: 0x08 */ - uint32_t Reserved[253]; /*!< Reserved memory area Address offset: 0x0C -> 0x03FC */ - __IO uint32_t RAM[1334]; /*!< PKA RAM Address offset: 0x400 -> 0x18D4 */ -} PKA_TypeDef; - -/* -* @brief RTC Specific device feature definitions -*/ -#define RTC_BKP_NB 32U -#define RTC_TAMP_NB 8U - -/** - * @brief Real-Time Clock - */ -typedef struct -{ - __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */ - __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */ - __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */ - __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */ - __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */ - __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */ - __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */ - __IO uint32_t PRIVCFGR; /*!< RTC privilege mode control register, Address offset: 0x1C */ - __IO uint32_t SECCFGR; /*!< RTC secure mode control register, Address offset: 0x20 */ - __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */ - __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */ - __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */ - __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */ - __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */ - __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x3C */ - __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */ - __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */ - __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */ - __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */ - __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */ - __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */ - __IO uint32_t SMISR; /*!< RTC secure masked interrupt status register, Address offset: 0x58 */ - __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */ - uint32_t RESERVED4[4];/*!< Reserved, Address offset: 0x58 */ - __IO uint32_t ALRABINR; /*!< RTC alarm A binary mode register, Address offset: 0x70 */ - __IO uint32_t ALRBBINR; /*!< RTC alarm B binary mode register, Address offset: 0x74 */ -} RTC_TypeDef; - -/** - * @brief Tamper and backup registers - */ -typedef struct -{ - __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< TAMP configuration register 3, Address offset: 0x08 */ - __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */ - __IO uint32_t ATCR1; /*!< TAMP filter control register 1 Address offset: 0x10 */ - __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */ - __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */ - __IO uint32_t ATCR2; /*!< TAMP filter control register 2, Address offset: 0x1C */ - __IO uint32_t SECCFGR; /*!< TAMP secure mode control register, Address offset: 0x20 */ - __IO uint32_t PRIVCFGR; /*!< TAMP privilege mode control register, Address offset: 0x24 */ - uint32_t RESERVED0; /*!< Reserved, Address offset: 0x28 */ - __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */ - __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */ - __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */ - __IO uint32_t SMISR; /*!< TAMP secure masked interrupt status register,Address offset: 0x38 */ - __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */ - __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */ - uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x43 -- 0x50 */ - __IO uint32_t ERCFGR; /*!< TAMP erase configuration register, Address offset: 0x54 */ - uint32_t RESERVED2[42]; /*!< Reserved, Address offset: 0x58 -- 0xFC */ - __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */ - __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */ - __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */ - __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */ - __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */ - __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */ - __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */ - __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */ - __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */ - __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */ - __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */ - __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */ - __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */ - __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */ - __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */ - __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */ - __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */ - __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */ - __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */ - __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */ - __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */ - __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */ - __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */ - __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */ - __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */ - __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */ - __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */ - __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */ - __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */ - __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */ - __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */ - __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */ -} TAMP_TypeDef; - -/** - * @brief Universal Synchronous Asynchronous Receiver Transmitter - */ -typedef struct -{ - __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */ - __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */ - __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */ - __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */ - __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */ - __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */ - __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */ - __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */ - __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */ - __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */ - __IO uint32_t PRESC; /*!< USART Prescaler register, Address offset: 0x2C */ - __IO uint32_t AUTOCR; /*!< USART Autonomous mode control register Address offset: 0x30 */ -} USART_TypeDef; - -/** - * @brief Serial Audio Interface - */ -typedef struct -{ - __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */ - uint32_t RESERVED[16]; /*!< Reserved, Address offset: 0x04 to 0x40 */ - __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */ - __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */ -} SAI_TypeDef; - -typedef struct -{ - __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */ - __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */ - __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */ - __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */ - __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */ - __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */ - __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */ - __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */ -} SAI_Block_TypeDef; - -/** - * @brief System configuration controller - */ -typedef struct -{ - __IO uint32_t SECCFGR; /*!< SYSCFG secure configuration register, Address offset: 0x00 */ - __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x04 */ - __IO uint32_t FPUIMR; /*!< SYSCFG FPU interrupt mask register, Address offset: 0x08 */ - __IO uint32_t CNSLCKR; /*!< SYSCFG CPU non-secure lock register, Address offset: 0x0C */ - __IO uint32_t CSLCKR; /*!< SYSCFG CPU secure lock register, Address offset: 0x10 */ - __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x14 */ - __IO uint32_t MESR; /*!< SYSCFG Memory Erase Status register, Address offset: 0x18 */ - __IO uint32_t CCCSR; /*!< SYSCFG Conpensaion Cell Control&Status register, Address offset: 0x1C */ - __IO uint32_t CCVR; /*!< SYSCFG Conpensaion Cell value register, Address offset: 0x20 */ - __IO uint32_t CCCR; /*!< SYSCFG Conpensaion Cell Code register, Address offset: 0x24 */ - uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x28 */ - __IO uint32_t RSSCMDR; /*!< SYSCFG RSS command mode register, Address offset: 0x2C */ -} SYSCFG_TypeDef; - -/** - * @brief Secure digital input/output Interface - */ -typedef struct -{ - __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */ - __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */ - __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */ - __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */ - __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */ - __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */ - __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */ - __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */ - __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */ - __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */ - __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */ - __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */ - __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */ - __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */ - __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */ - __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */ - __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */ - uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */ - __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */ - __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */ - __IO uint32_t IDMABASER; /*!< SDMMC DMA buffer base address register, Address offset: 0x58 */ - uint32_t RESERVED1[2]; /*!< Reserved, 0x60 */ - __IO uint32_t IDMALAR; /*!< SDMMC DMA linked list address register, Address offset: 0x64 */ - __IO uint32_t IDMABAR; /*!< SDMMC DMA linked list memory base register,Address offset: 0x68 */ - uint32_t RESERVED2[5]; /*!< Reserved, 0x6C-0x7C */ - __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */ -} SDMMC_TypeDef; - - - -/** - * @brief Delay Block DLYB - */ -typedef struct -{ - __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */ - __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */ -} DLYB_TypeDef; - -/** - * @brief UCPD - */ -typedef struct -{ - __IO uint32_t CFG1; /*!< UCPD configuration register 1, Address offset: 0x00 */ - __IO uint32_t CFG2; /*!< UCPD configuration register 2, Address offset: 0x04 */ - __IO uint32_t CFG3; /*!< UCPD configuration register 3, Address offset: 0x08 */ - __IO uint32_t CR; /*!< UCPD control register, Address offset: 0x0C */ - __IO uint32_t IMR; /*!< UCPD interrupt mask register, Address offset: 0x10 */ - __IO uint32_t SR; /*!< UCPD status register, Address offset: 0x14 */ - __IO uint32_t ICR; /*!< UCPD interrupt flag clear register Address offset: 0x18 */ - __IO uint32_t TX_ORDSET; /*!< UCPD Tx ordered set type register, Address offset: 0x1C */ - __IO uint32_t TX_PAYSZ; /*!< UCPD Tx payload size register, Address offset: 0x20 */ - __IO uint32_t TXDR; /*!< UCPD Tx data register, Address offset: 0x24 */ - __IO uint32_t RX_ORDSET; /*!< UCPD Rx ordered set type register, Address offset: 0x28 */ - __IO uint32_t RX_PAYSZ; /*!< UCPD Rx payload size register, Address offset: 0x2C */ - __IO uint32_t RXDR; /*!< UCPD Rx data register, Address offset: 0x30 */ - __IO uint32_t RX_ORDEXT1; /*!< UCPD Rx ordered set extension 1 register, Address offset: 0x34 */ - __IO uint32_t RX_ORDEXT2; /*!< UCPD Rx ordered set extension 2 register, Address offset: 0x38 */ -} UCPD_TypeDef; - -/** - * @brief USB_OTG_Core_register - */ -typedef struct -{ - __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register, Address offset: 000h */ - __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register, Address offset: 004h */ - __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register, Address offset: 008h */ - __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register, Address offset: 00Ch */ - __IO uint32_t GRSTCTL; /*!< Core Reset Register, Address offset: 010h */ - __IO uint32_t GINTSTS; /*!< Core Interrupt Register, Address offset: 014h */ - __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register, Address offset: 018h */ - __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register, Address offset: 01Ch */ - __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register, Address offset: 020h */ - __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register, Address offset: 024h */ - __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register, Address offset: 028h */ - __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg, Address offset: 02Ch */ - __IO uint32_t Reserved30[2]; /*!< Reserved, Address offset: 030h */ - __IO uint32_t GCCFG; /*!< General Purpose IO Register, Address offset: 038h */ - __IO uint32_t CID; /*!< User ID Register, Address offset: 03Ch */ - __IO uint32_t GSNPSID; /*!< USB_OTG core ID, Address offset: 040h */ - __IO uint32_t GHWCFG1; /*!< User HW config1, Address offset: 044h */ - __IO uint32_t GHWCFG2; /*!< User HW config2, Address offset: 048h */ - __IO uint32_t GHWCFG3; /*!< User HW config3, Address offset: 04Ch */ - __IO uint32_t Reserved6; /*!< Reserved, Address offset: 050h */ - __IO uint32_t GLPMCFG; /*!< LPM Register, Address offset: 054h */ - __IO uint32_t GPWRDN; /*!< Power Down Register, Address offset: 058h */ - __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register, Address offset: 05Ch */ - __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register, Address offset: 60Ch */ - __IO uint32_t Reserved43[39]; /*!< Reserved, Address offset: 058h */ - __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg, Address offset: 100h */ - __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO Address offset: 104h */ -} USB_OTG_GlobalTypeDef; - -/** - * @brief USB_OTG_device_Registers - */ -typedef struct -{ - __IO uint32_t DCFG; /*!< dev Configuration Register, Address offset: 800h */ - __IO uint32_t DCTL; /*!< dev Control Register, Address offset: 804h */ - __IO uint32_t DSTS; /*!< dev Status Register (RO), Address offset: 808h */ - uint32_t Reserved0C; /*!< Reserved, Address offset: 80Ch */ - __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask, Address offset: 810h */ - __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask, Address offset: 814h */ - __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg, Address offset: 818h */ - __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask, Address offset: 81Ch */ - uint32_t Reserved20; /*!< Reserved, Address offset: 820h */ - uint32_t Reserved9; /*!< Reserved, Address offset: 824h */ - __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register, Address offset: 828h */ - __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register, Address offset: 82Ch */ - __IO uint32_t DTHRCTL; /*!< dev threshold, Address offset: 830h */ - __IO uint32_t DIEPEMPMSK; /*!< dev empty msk, Address offset: 834h */ - __IO uint32_t DEACHINT; /*!< dedicated EP interrupt, Address offset: 838h */ - __IO uint32_t DEACHMSK; /*!< dedicated EP msk, Address offset: 83Ch */ - uint32_t Reserved40; /*!< dedicated EP mask, Address offset: 840h */ - __IO uint32_t DINEP1MSK; /*!< dedicated EP mask, Address offset: 844h */ - uint32_t Reserved44[15]; /*!< Reserved, Address offset: 844-87Ch */ - __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk, Address offset: 884h */ -} USB_OTG_DeviceTypeDef; - - -/** - * @brief USB_OTG_IN_Endpoint-Specific_Register - */ -typedef struct -{ - __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Register, Address offset: 900h + (ep_num * 20h) + 00h */ - __IO uint32_t Reserved04; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 04h */ - __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Register, Address offset: 900h + (ep_num * 20h) + 08h */ - __IO uint32_t Reserved0C; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size Register, Address offset: 900h + (ep_num * 20h) + 10h */ - __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Register, Address offset: 900h + (ep_num * 20h) + 14h */ - __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Register, Address offset: 900h + (ep_num * 20h) + 18h */ - __IO uint32_t Reserved18; /*!< Reserved, Address offset: 900h + (ep_num * 20h) + 1Ch */ -} USB_OTG_INEndpointTypeDef; - -/** - * @brief USB_OTG_OUT_Endpoint-Specific_Registers - */ -typedef struct -{ - __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Register, Address offset: B00h + (ep_num * 20h) + 00h */ - __IO uint32_t Reserved04; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 04h */ - __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Register, Address offset: B00h + (ep_num * 20h) + 08h */ - __IO uint32_t Reserved0C; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 0Ch */ - __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size Register, Address offset: B00h + (ep_num * 20h) + 10h */ - __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address Register, Address offset: B00h + (ep_num * 20h) + 14h */ - __IO uint32_t Reserved18[2]; /*!< Reserved, Address offset: B00h + (ep_num * 20h) + 18h */ -} USB_OTG_OUTEndpointTypeDef; - -/** - * @brief USB_OTG_Host_Mode_Register_Structures - */ -typedef struct -{ - __IO uint32_t HCFG; /*!< Host Configuration Register, Address offset: 400h */ - __IO uint32_t HFIR; /*!< Host Frame Interval Register, Address offset: 404h */ - __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining, Address offset: 408h */ - uint32_t Reserved40C; /*!< Reserved, Address offset: 40Ch */ - __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status, Address offset: 410h */ - __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register, Address offset: 414h */ - __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask, Address offset: 418h */ -} USB_OTG_HostTypeDef; - -/** - * @brief USB_OTG_Host_Channel_Specific_Registers - */ -typedef struct -{ - __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register, Address offset: 500h */ - __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register, Address offset: 504h */ - __IO uint32_t HCINT; /*!< Host Channel Interrupt Register, Address offset: 508h */ - __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register, Address offset: 50Ch */ - __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register, Address offset: 510h */ - __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register, Address offset: 514h */ - uint32_t Reserved[2]; /*!< Reserved, Address offset: 518h */ -} USB_OTG_HostChannelTypeDef; - -/** - * @brief FD Controller Area Network - */ -typedef struct -{ - __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */ - __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */ - uint32_t RESERVED1; /*!< Reserved, 0x008 */ - __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */ - __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */ - __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */ - __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */ - __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */ - __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */ - __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */ - __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */ - __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */ - uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */ - __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */ - __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */ - __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */ - uint32_t RESERVED3; /*!< Reserved, 0x04C */ - __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */ - __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */ - __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */ - __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */ - uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */ - __IO uint32_t RXGFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */ - __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x084 */ - __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x088 */ - uint32_t RESERVED5; /*!< Reserved, 0x08C */ - __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x090 */ - __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x094 */ - __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x098 */ - __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x09C */ - uint32_t RESERVED6[8]; /*!< Reserved, 0x0A0 - 0x0BC */ - __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */ - __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */ - __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0C8 */ - __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0CC */ - __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D0 */ - __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D4 */ - __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0D8 */ - __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0DC */ - __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E0 */ - __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0E4 */ - __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0E8 */ -} FDCAN_GlobalTypeDef; - -/** - * @brief FD Controller Area Network Configuration - */ -typedef struct -{ - __IO uint32_t CKDIV; /*!< FDCAN clock divider register, Address offset: 0x100 + 0x000 */ - uint32_t RESERVED1[128];/*!< Reserved, 0x100 + 0x004 - 0x100 + 0x200 */ - __IO uint32_t OPTR; /*!< FDCAN option register, Address offset: 0x100 + 0x204 */ - uint32_t RESERVED2[58];/*!< Reserved, 0x100 + 0x208 - 0x100 + 0x2EC */ - __IO uint32_t HWCFG; /*!< FDCAN hardware configuration register, Address offset: 0x100 + 0x2F0 */ - __IO uint32_t VERR; /*!< FDCAN IP version register, Address offset: 0x100 + 0x2F4 */ - __IO uint32_t IPIDR; /*!< FDCAN IP ID register, Address offset: 0x100 + 0x2F8 */ - __IO uint32_t SIDR; /*!< FDCAN size ID register, Address offset: 0x100 + 0x2FC */ -} FDCAN_Config_TypeDef; - -/** - * @brief Flexible Memory Controller - */ -typedef struct -{ - __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */ - __IO uint32_t PCSCNTR; /*!< PSRAM chip-select counter register, Address offset: 0x20 */ -} FMC_Bank1_TypeDef; - -/** - * @brief Flexible Memory Controller Bank1E - */ -typedef struct -{ - __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */ -} FMC_Bank1E_TypeDef; - -/** - * @brief Flexible Memory Controller Bank3 - */ -typedef struct -{ - __IO uint32_t PCR; /*!< NAND Flash control register, Address offset: 0x80 */ - __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 */ - __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register, Address offset: 0x88 */ - __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register, Address offset: 0x8C */ - uint32_t RESERVED0; /*!< Reserved, 0x90 */ - __IO uint32_t ECCR; /*!< NAND Flash ECC result registers, Address offset: 0x94 */ -} FMC_Bank3_TypeDef; - -/** - * @brief VREFBUF - */ -typedef struct -{ - __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */ - __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */ -} VREFBUF_TypeDef; - -/** - * @brief ADC - */ -typedef struct -{ - __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */ - __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ - __IO uint32_t CFGR1; /*!< ADC Configuration register, Address offset: 0x0C */ - __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */ - __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */ - __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */ /* Specific to ADC 14Bits*/ - __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */ - __IO uint32_t AWD1TR; /*!< ADC watchdog threshold register, Address offset: 0x20 */ /* Specific to ADC 12Bits*/ - __IO uint32_t AWD2TR; /*!< ADC watchdog threshold register, Address offset: 0x24 */ /* Specific to ADC 12Bits*/ - __IO uint32_t CHSELR; /*!< ADC channel select register, Address offset: 0x28 */ /* Specific to ADC 12Bits*/ - __IO uint32_t AWD3TR; /*!< ADC watchdog threshold register, Address offset: 0x2C */ /* Specific to ADC 12Bits*/ - __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */ /* Specific to ADC 14Bits*/ - __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */ /* Specific to ADC 14Bits*/ - __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */ /* Specific to ADC 14Bits*/ - __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */ /* Specific to ADC 14Bits*/ - __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */ - __IO uint32_t PWRR; /*!< ADC power register, Address offset: 0x44 */ - uint32_t RESERVED1; /*!< Reserved, 0x048 */ - __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */ /* Specific to ADC 14Bits*/ - uint32_t RESERVED2[4]; /*!< Reserved, 0x050 - 0x05C */ - __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */ /* Specific to ADC 14Bits*/ - __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */ /* Specific to ADC 14Bits*/ - __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */ /* Specific to ADC 14Bits*/ - __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */ /* Specific to ADC 14Bits*/ - __IO uint32_t GCOMP; /*!< ADC gain compensation register, Address offset: 0x70 */ /* Specific to ADC 14Bits*/ - uint32_t RESERVED3[3]; /*!< Reserved, 0x074 - 0x07C */ - __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */ /* Specific to ADC 14Bits*/ - __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */ /* Specific to ADC 14Bits*/ - __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */ /* Specific to ADC 14Bits*/ - __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */ /* Specific to ADC 14Bits*/ - uint32_t RESERVED4[4]; /*!< Reserved, 0x090 - 0x09C */ - __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */ - __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */ - __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0xA8 */ /* Specific to ADC 14Bits*/ - __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0xAC */ /* Specific to ADC 14Bits*/ - __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */ /* Specific to ADC 14Bits*/ - __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */ /* Specific to ADC 14Bits*/ - __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */ /* Specific to ADC 14Bits*/ - __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */ /* Specific to ADC 14Bits*/ - __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */ /* Specific to ADC 14Bits*/ - __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */ - __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */ /* Specific to ADC 14Bits*/ - uint32_t RESERVED5; /*!< Reserved, 0x0CC */ - __IO uint32_t OR; /*!< ADC Option Register, Address offset: 0xD0 */ /* Specific to ADC 12Bits*/ -} ADC_TypeDef; - -typedef struct -{ - __IO uint32_t CCR; /*!< ADC common control register, Address offset: 0x308 */ -} ADC_Common_TypeDef; - - -/* Legacy registers naming */ -#define PW PWRR - -/** - * @brief CORDIC - */ -typedef struct -{ - __IO uint32_t CSR; /*!< CORDIC control and status register, Address offset: 0x00 */ - __IO uint32_t WDATA; /*!< CORDIC argument register, Address offset: 0x04 */ - __IO uint32_t RDATA; /*!< CORDIC result register, Address offset: 0x08 */ -} CORDIC_TypeDef; - -/** - * @brief IWDG - */ -typedef struct -{ - __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ - __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ - __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ - __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ - __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ - __IO uint32_t EWCR; /*!< IWDG Early Wakeup register, Address offset: 0x14 */ -} IWDG_TypeDef; - -/** - * @brief SPI - */ -typedef struct -{ - __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */ - __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ - __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */ - __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */ - __IO uint32_t IER; /*!< SPI Interrupt Enable register, Address offset: 0x10 */ - __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x14 */ - __IO uint32_t IFCR; /*!< SPI Interrupt/Status Flags Clear register, Address offset: 0x18 */ - __IO uint32_t AUTOCR; /*!< SPI Autonomous Mode Control register, Address offset: 0x1C */ - __IO uint32_t TXDR; /*!< SPI Transmit data register, Address offset: 0x20 */ - uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */ - __IO uint32_t RXDR; /*!< SPI/I2S data register, Address offset: 0x30 */ - uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */ - __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */ - __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */ - __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */ - __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */ -} SPI_TypeDef; - -/** - * @brief Touch Sensing Controller (TSC) - */ - -typedef struct -{ - __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */ - __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */ - __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */ - __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */ - __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */ - uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ - __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */ - uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */ - __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */ - uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */ - __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */ - uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */ - __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */ - __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */ -} TSC_TypeDef; - -/** - * @brief WWDG - */ -typedef struct -{ - __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ - __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ - __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ -} WWDG_TypeDef; - -/*@}*/ /* end of group STM32U5xx_peripherals */ - - -/* -------- End of section using anonymous unions and disabling warnings -------- */ -#if defined (__CC_ARM) - #pragma pop -#elif defined (__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #pragma clang diagnostic pop -#elif defined (__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined (__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined (__TASKING__) - #pragma warning restore -#elif defined (__CSMC__) - /* anonymous unions are enabled by default */ -#else - #warning Not supported compiler type -#endif - - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Address Map ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup STM32U5xx_Peripheral_peripheralAddr - * @{ - */ - -/* Internal SRAMs size */ -#define SRAM1_SIZE (0x30000UL) /*!< SRAM1=192k */ -#define SRAM2_SIZE (0x10000UL) /*!< SRAM2=64k */ -#define SRAM3_SIZE (0x80000UL) /*!< SRAM3=512k */ -#define SRAM4_SIZE (0x04000UL) /*!< SRAM4=16k */ - -/* External memories base addresses - Not aliased */ -#define FMC_BASE (0x60000000UL) /*!< FMC base address */ -#define OCTOSPI2_BASE (0x70000000UL) /*!< OCTOSPI2 memories accessible over AHB base address */ -#define OCTOSPI1_BASE (0x90000000UL) /*!< OCTOSPI1 memories accessible over AHB base address */ - -#define FMC_BANK1 FMC_BASE -#define FMC_BANK1_1 FMC_BANK1 -#define FMC_BANK1_2 (FMC_BANK1 + 0x04000000UL) -#define FMC_BANK1_3 (FMC_BANK1 + 0x08000000UL) -#define FMC_BANK1_4 (FMC_BANK1 + 0x0C000000UL) -#define FMC_BANK3 (FMC_BASE + 0x20000000UL) - -/* Flash, Peripheral and internal SRAMs base addresses - Non secure */ -#define FLASH_BASE_NS (0x08000000UL) /*!< FLASH (up to 2 MB) non-secure base address */ -#define SRAM1_BASE_NS (0x20000000UL) /*!< SRAM1 (192 KB) non-secure base address */ -#define SRAM2_BASE_NS (0x20030000UL) /*!< SRAM2 (64 KB) non-secure base address */ -#define SRAM3_BASE_NS (0x20040000UL) /*!< SRAM3 (512 KB) non-secure base address */ -#define SRAM4_BASE_NS (0x28000000UL) /*!< SRAM4 (16 KB) non-secure base address */ -#define PERIPH_BASE_NS (0x40000000UL) /*!< Peripheral non-secure base address */ - -/* Peripheral memory map - Non secure */ -#define APB1PERIPH_BASE_NS PERIPH_BASE_NS -#define APB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00010000UL) -#define AHB1PERIPH_BASE_NS (PERIPH_BASE_NS + 0x00020000UL) -#define AHB2PERIPH_BASE_NS (PERIPH_BASE_NS + 0x02020000UL) -#define APB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06000000UL) -#define AHB3PERIPH_BASE_NS (PERIPH_BASE_NS + 0x06020000UL) - -/*!< APB1 Non secure peripherals */ -#define TIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x0000UL) -#define TIM3_BASE_NS (APB1PERIPH_BASE_NS + 0x0400UL) -#define TIM4_BASE_NS (APB1PERIPH_BASE_NS + 0x0800UL) -#define TIM5_BASE_NS (APB1PERIPH_BASE_NS + 0x0C00UL) -#define TIM6_BASE_NS (APB1PERIPH_BASE_NS + 0x1000UL) -#define TIM7_BASE_NS (APB1PERIPH_BASE_NS + 0x1400UL) -#define WWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x2C00UL) -#define IWDG_BASE_NS (APB1PERIPH_BASE_NS + 0x3000UL) -#define SPI2_BASE_NS (APB1PERIPH_BASE_NS + 0x3800UL) -#define USART2_BASE_NS (APB1PERIPH_BASE_NS + 0x4400UL) -#define USART3_BASE_NS (APB1PERIPH_BASE_NS + 0x4800UL) -#define UART4_BASE_NS (APB1PERIPH_BASE_NS + 0x4C00UL) -#define UART5_BASE_NS (APB1PERIPH_BASE_NS + 0x5000UL) -#define I2C1_BASE_NS (APB1PERIPH_BASE_NS + 0x5400UL) -#define I2C2_BASE_NS (APB1PERIPH_BASE_NS + 0x5800UL) -#define CRS_BASE_NS (APB1PERIPH_BASE_NS + 0x6000UL) -#define I2C4_BASE_NS (APB1PERIPH_BASE_NS + 0x8400UL) -#define LPTIM2_BASE_NS (APB1PERIPH_BASE_NS + 0x9400UL) -#define FDCAN1_BASE_NS (APB1PERIPH_BASE_NS + 0xA400UL) -#define FDCAN_CONFIG_BASE_NS (APB1PERIPH_BASE_NS + 0xA500UL) -#define SRAMCAN_BASE_NS (APB1PERIPH_BASE_NS + 0xAC00UL) -#define UCPD1_BASE_NS (APB1PERIPH_BASE_NS + 0xDC00UL) - -/*!< APB2 Non secure peripherals */ -#define TIM1_BASE_NS (APB2PERIPH_BASE_NS + 0x2C00UL) -#define SPI1_BASE_NS (APB2PERIPH_BASE_NS + 0x3000UL) -#define TIM8_BASE_NS (APB2PERIPH_BASE_NS + 0x3400UL) -#define USART1_BASE_NS (APB2PERIPH_BASE_NS + 0x3800UL) -#define TIM15_BASE_NS (APB2PERIPH_BASE_NS + 0x4000UL) -#define TIM16_BASE_NS (APB2PERIPH_BASE_NS + 0x4400UL) -#define TIM17_BASE_NS (APB2PERIPH_BASE_NS + 0x4800UL) -#define SAI1_BASE_NS (APB2PERIPH_BASE_NS + 0x5400UL) -#define SAI1_Block_A_BASE_NS (SAI1_BASE_NS + 0x004UL) -#define SAI1_Block_B_BASE_NS (SAI1_BASE_NS + 0x024UL) -#define SAI2_BASE_NS (APB2PERIPH_BASE_NS + 0x5800UL) -#define SAI2_Block_A_BASE_NS (SAI2_BASE_NS + 0x004UL) -#define SAI2_Block_B_BASE_NS (SAI2_BASE_NS + 0x024UL) - -/*!< APB3 Non secure peripherals */ -#define SYSCFG_BASE_NS (APB3PERIPH_BASE_NS + 0x0400UL) -#define SPI3_BASE_NS (APB3PERIPH_BASE_NS + 0x2000UL) -#define LPUART1_BASE_NS (APB3PERIPH_BASE_NS + 0x2400UL) -#define I2C3_BASE_NS (APB3PERIPH_BASE_NS + 0x2800UL) -#define LPTIM1_BASE_NS (APB3PERIPH_BASE_NS + 0x4400UL) -#define LPTIM3_BASE_NS (APB3PERIPH_BASE_NS + 0x4800UL) -#define LPTIM4_BASE_NS (APB3PERIPH_BASE_NS + 0x4C00UL) -#define OPAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) -#define OPAMP1_BASE_NS (APB3PERIPH_BASE_NS + 0x5000UL) -#define OPAMP2_BASE_NS (APB3PERIPH_BASE_NS + 0x5010UL) -#define COMP12_BASE_NS (APB3PERIPH_BASE_NS + 0x5400UL) -#define COMP1_BASE_NS (COMP12_BASE_NS) -#define COMP2_BASE_NS (COMP12_BASE_NS + 0x04UL) -#define VREFBUF_BASE_NS (APB3PERIPH_BASE_NS + 0x7400UL) -#define RTC_BASE_NS (APB3PERIPH_BASE_NS + 0x7800UL) -#define TAMP_BASE_NS (APB3PERIPH_BASE_NS + 0x7C00UL) - -/*!< AHB1 Non secure peripherals */ -#define GPDMA1_BASE_NS (AHB1PERIPH_BASE_NS) -#define GPDMA1_Channel0_BASE_NS (GPDMA1_BASE_NS + 0x0050UL) -#define GPDMA1_Channel1_BASE_NS (GPDMA1_BASE_NS + 0x00D0UL) -#define GPDMA1_Channel2_BASE_NS (GPDMA1_BASE_NS + 0x0150UL) -#define GPDMA1_Channel3_BASE_NS (GPDMA1_BASE_NS + 0x01D0UL) -#define GPDMA1_Channel4_BASE_NS (GPDMA1_BASE_NS + 0x0250UL) -#define GPDMA1_Channel5_BASE_NS (GPDMA1_BASE_NS + 0x02D0UL) -#define GPDMA1_Channel6_BASE_NS (GPDMA1_BASE_NS + 0x0350UL) -#define GPDMA1_Channel7_BASE_NS (GPDMA1_BASE_NS + 0x03D0UL) -#define GPDMA1_Channel8_BASE_NS (GPDMA1_BASE_NS + 0x0450UL) -#define GPDMA1_Channel9_BASE_NS (GPDMA1_BASE_NS + 0x04D0UL) -#define GPDMA1_Channel10_BASE_NS (GPDMA1_BASE_NS + 0x0550UL) -#define GPDMA1_Channel11_BASE_NS (GPDMA1_BASE_NS + 0x05D0UL) -#define GPDMA1_Channel12_BASE_NS (GPDMA1_BASE_NS + 0x0650UL) -#define GPDMA1_Channel13_BASE_NS (GPDMA1_BASE_NS + 0x06D0UL) -#define GPDMA1_Channel14_BASE_NS (GPDMA1_BASE_NS + 0x0750UL) -#define GPDMA1_Channel15_BASE_NS (GPDMA1_BASE_NS + 0x07D0UL) -#define CORDIC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01000UL) -#define FMAC_BASE_NS (AHB1PERIPH_BASE_NS + 0x01400UL) -#define FLASH_R_BASE_NS (AHB1PERIPH_BASE_NS + 0x02000UL) -#define CRC_BASE_NS (AHB1PERIPH_BASE_NS + 0x03000UL) -#define TSC_BASE_NS (AHB1PERIPH_BASE_NS + 0x04000UL) -#define MDF1_BASE_NS (AHB1PERIPH_BASE_NS + 0x05000UL) -#define MDF1_Filter0_BASE_NS (MDF1_BASE_NS + 0x80UL) -#define MDF1_Filter1_BASE_NS (MDF1_BASE_NS + 0x100UL) -#define MDF1_Filter2_BASE_NS (MDF1_BASE_NS + 0x180UL) -#define MDF1_Filter3_BASE_NS (MDF1_BASE_NS + 0x200UL) -#define MDF1_Filter4_BASE_NS (MDF1_BASE_NS + 0x280UL) -#define MDF1_Filter5_BASE_NS (MDF1_BASE_NS + 0x300UL) -#define RAMCFG_BASE_NS (AHB1PERIPH_BASE_NS + 0x06000UL) -#define RAMCFG_SRAM1_BASE_NS (RAMCFG_BASE_NS) -#define RAMCFG_SRAM2_BASE_NS (RAMCFG_BASE_NS + 0x0040UL) -#define RAMCFG_SRAM3_BASE_NS (RAMCFG_BASE_NS + 0x0080UL) -#define RAMCFG_SRAM4_BASE_NS (RAMCFG_BASE_NS + 0x00C0UL) -#define RAMCFG_BKPRAM_BASE_NS (RAMCFG_BASE_NS + 0x0100UL) -#define DMA2D_BASE_NS (AHB1PERIPH_BASE_NS + 0x0B000UL) -#define ICACHE_BASE_NS (AHB1PERIPH_BASE_NS + 0x10400UL) -#define DCACHE1_BASE_NS (AHB1PERIPH_BASE_NS + 0x11400UL) -#define GTZC_TZSC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12400UL) -#define GTZC_TZIC1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12800UL) -#define GTZC_MPCBB1_BASE_NS (AHB1PERIPH_BASE_NS + 0x12C00UL) -#define GTZC_MPCBB2_BASE_NS (AHB1PERIPH_BASE_NS + 0x13000UL) -#define GTZC_MPCBB3_BASE_NS (AHB1PERIPH_BASE_NS + 0x13400UL) -#define BKPSRAM_BASE_NS (AHB1PERIPH_BASE_NS + 0x16400UL) - -/*!< AHB2 Non secure peripherals */ -#define GPIOA_BASE_NS (AHB2PERIPH_BASE_NS + 0x00000UL) -#define GPIOB_BASE_NS (AHB2PERIPH_BASE_NS + 0x00400UL) -#define GPIOC_BASE_NS (AHB2PERIPH_BASE_NS + 0x00800UL) -#define GPIOD_BASE_NS (AHB2PERIPH_BASE_NS + 0x00C00UL) -#define GPIOE_BASE_NS (AHB2PERIPH_BASE_NS + 0x01000UL) -#define GPIOF_BASE_NS (AHB2PERIPH_BASE_NS + 0x01400UL) -#define GPIOG_BASE_NS (AHB2PERIPH_BASE_NS + 0x01800UL) -#define GPIOH_BASE_NS (AHB2PERIPH_BASE_NS + 0x01C00UL) -#define GPIOI_BASE_NS (AHB2PERIPH_BASE_NS + 0x02000UL) -#define ADC1_BASE_NS (AHB2PERIPH_BASE_NS + 0x08000UL) -#define ADC12_COMMON_BASE_NS (AHB2PERIPH_BASE_NS + 0x08308UL) -#define DCMI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C000UL) -#define PSSI_BASE_NS (AHB2PERIPH_BASE_NS + 0x0C400UL) -#define USB_OTG_FS_BASE_NS (AHB2PERIPH_BASE_NS + 0x20000UL) -#define AES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0000UL) -#define HASH_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0400UL) -#define HASH_DIGEST_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0710UL) -#define RNG_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0800UL) -#define SAES_BASE_NS (AHB2PERIPH_BASE_NS + 0xA0C00UL) -#define PKA_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2000UL) -#define PKA_RAM_BASE_NS (AHB2PERIPH_BASE_NS + 0xA2400UL) -#define OCTOSPIM_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xA4000UL) /*!< OCTOSPIO Manager control registers base address */ -#define OTFDEC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5000UL) -#define OTFDEC1_REGION1_BASE_NS (OTFDEC1_BASE_NS + 0x20UL) -#define OTFDEC1_REGION2_BASE_NS (OTFDEC1_BASE_NS + 0x50UL) -#define OTFDEC1_REGION3_BASE_NS (OTFDEC1_BASE_NS + 0x80UL) -#define OTFDEC1_REGION4_BASE_NS (OTFDEC1_BASE_NS + 0xB0UL) -#define OTFDEC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA5400UL) -#define OTFDEC2_REGION1_BASE_NS (OTFDEC2_BASE_NS + 0x20UL) -#define OTFDEC2_REGION2_BASE_NS (OTFDEC2_BASE_NS + 0x50UL) -#define OTFDEC2_REGION3_BASE_NS (OTFDEC2_BASE_NS + 0x80UL) -#define OTFDEC2_REGION4_BASE_NS (OTFDEC2_BASE_NS + 0xB0UL) -#define SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8000UL) -#define SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8C00UL) -#define DLYB_SDMMC1_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8400UL) -#define DLYB_SDMMC2_BASE_NS (AHB2PERIPH_BASE_NS + 0xA8800UL) -#define DLYB_OCTOSPI1_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF000UL) -#define DLYB_OCTOSPI2_BASE_NS (AHB2PERIPH_BASE_NS + 0xAF400UL) -#define FMC_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB0400UL) /*!< FMC control registers base address */ -/*!< FMC Banks Non secure registers base address */ -#define FMC_Bank1_R_BASE_NS (FMC_R_BASE_NS + 0x0000UL) -#define FMC_Bank1E_R_BASE_NS (FMC_R_BASE_NS + 0x0104UL) -#define FMC_Bank3_R_BASE_NS (FMC_R_BASE_NS + 0x0080UL) -#define OCTOSPI1_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ -#define OCTOSPI2_R_BASE_NS (AHB2PERIPH_BASE_NS + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ - -/*!< AHB3 Non secure peripherals */ -#define LPGPIO1_BASE_NS (AHB3PERIPH_BASE_NS) -#define PWR_BASE_NS (AHB3PERIPH_BASE_NS + 0x0800UL) -#define RCC_BASE_NS (AHB3PERIPH_BASE_NS + 0x0C00UL) -#define ADC4_BASE_NS (AHB3PERIPH_BASE_NS + 0x1000UL) -#define ADC4_COMMON_BASE_NS (AHB3PERIPH_BASE_NS + 0x1308UL) -#define DAC1_BASE_NS (AHB3PERIPH_BASE_NS + 0x1800UL) -#define EXTI_BASE_NS (AHB3PERIPH_BASE_NS + 0x2000UL) -#define GTZC_TZSC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3000UL) -#define GTZC_TZIC2_BASE_NS (AHB3PERIPH_BASE_NS + 0x3400UL) -#define GTZC_MPCBB4_BASE_NS (AHB3PERIPH_BASE_NS + 0x3800UL) -#define ADF1_BASE_NS (AHB3PERIPH_BASE_NS + 0x4000UL) -#define ADF1_Filter0_BASE_NS (ADF1_BASE_NS + 0x80UL) -#define LPDMA1_BASE_NS (AHB3PERIPH_BASE_NS + 0x5000UL) -#define LPDMA1_Channel0_BASE_NS (LPDMA1_BASE_NS + 0x0050UL) -#define LPDMA1_Channel1_BASE_NS (LPDMA1_BASE_NS + 0x00D0UL) -#define LPDMA1_Channel2_BASE_NS (LPDMA1_BASE_NS + 0x0150UL) -#define LPDMA1_Channel3_BASE_NS (LPDMA1_BASE_NS + 0x01D0UL) - -/* Flash, Peripheral and internal SRAMs base addresses - Secure */ -#define FLASH_BASE_S (0x0C000000UL) /*!< FLASH (up to 2 MB) secure base address */ -#define SRAM1_BASE_S (0x30000000UL) /*!< SRAM1 (192 KB) secure base address */ -#define SRAM2_BASE_S (0x30030000UL) /*!< SRAM2 (64 KB) secure base address */ -#define SRAM3_BASE_S (0x30040000UL) /*!< SRAM3 (512 KB) secure base address */ -#define SRAM4_BASE_S (0x38000000UL) /*!< SRAM4 (16 KB) secure base address */ -#define PERIPH_BASE_S (0x50000000UL) /*!< Peripheral secure base address */ - -/* Peripheral memory map - Secure */ -#define APB1PERIPH_BASE_S PERIPH_BASE_S -#define APB2PERIPH_BASE_S (PERIPH_BASE_S + 0x00010000UL) -#define AHB1PERIPH_BASE_S (PERIPH_BASE_S + 0x00020000UL) -#define AHB2PERIPH_BASE_S (PERIPH_BASE_S + 0x02020000UL) -#define APB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06000000UL) -#define AHB3PERIPH_BASE_S (PERIPH_BASE_S + 0x06020000UL) - -/*!< APB1 Secure peripherals */ -#define TIM2_BASE_S (APB1PERIPH_BASE_S + 0x0000UL) -#define TIM3_BASE_S (APB1PERIPH_BASE_S + 0x0400UL) -#define TIM4_BASE_S (APB1PERIPH_BASE_S + 0x0800UL) -#define TIM5_BASE_S (APB1PERIPH_BASE_S + 0x0C00UL) -#define TIM6_BASE_S (APB1PERIPH_BASE_S + 0x1000UL) -#define TIM7_BASE_S (APB1PERIPH_BASE_S + 0x1400UL) -#define WWDG_BASE_S (APB1PERIPH_BASE_S + 0x2C00UL) -#define IWDG_BASE_S (APB1PERIPH_BASE_S + 0x3000UL) -#define SPI2_BASE_S (APB1PERIPH_BASE_S + 0x3800UL) -#define USART2_BASE_S (APB1PERIPH_BASE_S + 0x4400UL) -#define USART3_BASE_S (APB1PERIPH_BASE_S + 0x4800UL) -#define UART4_BASE_S (APB1PERIPH_BASE_S + 0x4C00UL) -#define UART5_BASE_S (APB1PERIPH_BASE_S + 0x5000UL) -#define I2C1_BASE_S (APB1PERIPH_BASE_S + 0x5400UL) -#define I2C2_BASE_S (APB1PERIPH_BASE_S + 0x5800UL) -#define I2C4_BASE_S (APB1PERIPH_BASE_S + 0x8400UL) -#define CRS_BASE_S (APB1PERIPH_BASE_S + 0x6000UL) -#define LPTIM2_BASE_S (APB1PERIPH_BASE_S + 0x9400UL) -#define FDCAN1_BASE_S (APB1PERIPH_BASE_S + 0xA400UL) -#define FDCAN_CONFIG_BASE_S (APB1PERIPH_BASE_S + 0xA500UL) -#define SRAMCAN_BASE_S (APB1PERIPH_BASE_S + 0xAC00UL) -#define UCPD1_BASE_S (APB1PERIPH_BASE_S + 0xDC00UL) - -/*!< APB2 Secure peripherals */ -#define TIM1_BASE_S (APB2PERIPH_BASE_S + 0x2C00UL) -#define SPI1_BASE_S (APB2PERIPH_BASE_S + 0x3000UL) -#define TIM8_BASE_S (APB2PERIPH_BASE_S + 0x3400UL) -#define USART1_BASE_S (APB2PERIPH_BASE_S + 0x3800UL) -#define TIM15_BASE_S (APB2PERIPH_BASE_S + 0x4000UL) -#define TIM16_BASE_S (APB2PERIPH_BASE_S + 0x4400UL) -#define TIM17_BASE_S (APB2PERIPH_BASE_S + 0x4800UL) -#define SAI1_BASE_S (APB2PERIPH_BASE_S + 0x5400UL) -#define SAI1_Block_A_BASE_S (SAI1_BASE_S + 0x004UL) -#define SAI1_Block_B_BASE_S (SAI1_BASE_S + 0x024UL) -#define SAI2_BASE_S (APB2PERIPH_BASE_S + 0x5800UL) -#define SAI2_Block_A_BASE_S (SAI2_BASE_S + 0x004UL) -#define SAI2_Block_B_BASE_S (SAI2_BASE_S + 0x024UL) - -/*!< APB3 Secure peripherals */ -#define SYSCFG_BASE_S (APB3PERIPH_BASE_S + 0x0400UL) -#define SPI3_BASE_S (APB3PERIPH_BASE_S + 0x2000UL) -#define LPUART1_BASE_S (APB3PERIPH_BASE_S + 0x2400UL) -#define I2C3_BASE_S (APB3PERIPH_BASE_S + 0x2800UL) -#define LPTIM1_BASE_S (APB3PERIPH_BASE_S + 0x4400UL) -#define LPTIM3_BASE_S (APB3PERIPH_BASE_S + 0x4800UL) -#define LPTIM4_BASE_S (APB3PERIPH_BASE_S + 0x4C00UL) -#define OPAMP_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) -#define OPAMP1_BASE_S (APB3PERIPH_BASE_S + 0x5000UL) -#define OPAMP2_BASE_S (APB3PERIPH_BASE_S + 0x5010UL) -#define COMP12_BASE_S (APB3PERIPH_BASE_S + 0x5400UL) -#define COMP1_BASE_S (COMP12_BASE_S) -#define COMP2_BASE_S (COMP12_BASE_S + 0x04UL) -#define VREFBUF_BASE_S (APB3PERIPH_BASE_S + 0x7400UL) -#define RTC_BASE_S (APB3PERIPH_BASE_S + 0x7800UL) -#define TAMP_BASE_S (APB3PERIPH_BASE_S + 0x7C00UL) - -/*!< AHB1 Secure peripherals */ -#define GPDMA1_BASE_S (AHB1PERIPH_BASE_S) -#define GPDMA1_Channel0_BASE_S (GPDMA1_BASE_S + 0x0050UL) -#define GPDMA1_Channel1_BASE_S (GPDMA1_BASE_S + 0x00D0UL) -#define GPDMA1_Channel2_BASE_S (GPDMA1_BASE_S + 0x0150UL) -#define GPDMA1_Channel3_BASE_S (GPDMA1_BASE_S + 0x01D0UL) -#define GPDMA1_Channel4_BASE_S (GPDMA1_BASE_S + 0x0250UL) -#define GPDMA1_Channel5_BASE_S (GPDMA1_BASE_S + 0x02D0UL) -#define GPDMA1_Channel6_BASE_S (GPDMA1_BASE_S + 0x0350UL) -#define GPDMA1_Channel7_BASE_S (GPDMA1_BASE_S + 0x03D0UL) -#define GPDMA1_Channel8_BASE_S (GPDMA1_BASE_S + 0x0450UL) -#define GPDMA1_Channel9_BASE_S (GPDMA1_BASE_S + 0x04D0UL) -#define GPDMA1_Channel10_BASE_S (GPDMA1_BASE_S + 0x0550UL) -#define GPDMA1_Channel11_BASE_S (GPDMA1_BASE_S + 0x05D0UL) -#define GPDMA1_Channel12_BASE_S (GPDMA1_BASE_S + 0x0650UL) -#define GPDMA1_Channel13_BASE_S (GPDMA1_BASE_S + 0x06D0UL) -#define GPDMA1_Channel14_BASE_S (GPDMA1_BASE_S + 0x0750UL) -#define GPDMA1_Channel15_BASE_S (GPDMA1_BASE_S + 0x07D0UL) -#define CORDIC_BASE_S (AHB1PERIPH_BASE_S + 0x01000UL) -#define FMAC_BASE_S (AHB1PERIPH_BASE_S + 0x01400UL) -#define FLASH_R_BASE_S (AHB1PERIPH_BASE_S + 0x02000UL) -#define CRC_BASE_S (AHB1PERIPH_BASE_S + 0x03000UL) -#define TSC_BASE_S (AHB1PERIPH_BASE_S + 0x04000UL) -#define MDF1_BASE_S (AHB1PERIPH_BASE_S + 0x05000UL) -#define MDF1_Filter0_BASE_S (MDF1_BASE_S + 0x80UL) -#define MDF1_Filter1_BASE_S (MDF1_BASE_S + 0x100UL) -#define MDF1_Filter2_BASE_S (MDF1_BASE_S + 0x180UL) -#define MDF1_Filter3_BASE_S (MDF1_BASE_S + 0x200UL) -#define MDF1_Filter4_BASE_S (MDF1_BASE_S + 0x280UL) -#define MDF1_Filter5_BASE_S (MDF1_BASE_S + 0x300UL) -#define RAMCFG_BASE_S (AHB1PERIPH_BASE_S + 0x06000UL) -#define RAMCFG_SRAM1_BASE_S (RAMCFG_BASE_S) -#define RAMCFG_SRAM2_BASE_S (RAMCFG_BASE_S + 0x0040UL) -#define RAMCFG_SRAM3_BASE_S (RAMCFG_BASE_S + 0x0080UL) -#define RAMCFG_SRAM4_BASE_S (RAMCFG_BASE_S + 0x00C0UL) -#define RAMCFG_BKPRAM_BASE_S (RAMCFG_BASE_S + 0x0100UL) -#define DMA2D_BASE_S (AHB1PERIPH_BASE_S + 0x0B000UL) -#define ICACHE_BASE_S (AHB1PERIPH_BASE_S + 0x10400UL) -#define DCACHE1_BASE_S (AHB1PERIPH_BASE_S + 0x11400UL) -#define GTZC_TZSC1_BASE_S (AHB1PERIPH_BASE_S + 0x12400UL) -#define GTZC_TZIC1_BASE_S (AHB1PERIPH_BASE_S + 0x12800UL) -#define GTZC_MPCBB1_BASE_S (AHB1PERIPH_BASE_S + 0x12C00UL) -#define GTZC_MPCBB2_BASE_S (AHB1PERIPH_BASE_S + 0x13000UL) -#define GTZC_MPCBB3_BASE_S (AHB1PERIPH_BASE_S + 0x13400UL) -#define BKPSRAM_BASE_S (AHB1PERIPH_BASE_S + 0x16400UL) - -/*!< AHB2 Secure peripherals */ -#define GPIOA_BASE_S (AHB2PERIPH_BASE_S + 0x00000UL) -#define GPIOB_BASE_S (AHB2PERIPH_BASE_S + 0x00400UL) -#define GPIOC_BASE_S (AHB2PERIPH_BASE_S + 0x00800UL) -#define GPIOD_BASE_S (AHB2PERIPH_BASE_S + 0x00C00UL) -#define GPIOE_BASE_S (AHB2PERIPH_BASE_S + 0x01000UL) -#define GPIOF_BASE_S (AHB2PERIPH_BASE_S + 0x01400UL) -#define GPIOG_BASE_S (AHB2PERIPH_BASE_S + 0x01800UL) -#define GPIOH_BASE_S (AHB2PERIPH_BASE_S + 0x01C00UL) -#define GPIOI_BASE_S (AHB2PERIPH_BASE_S + 0x02000UL) -#define ADC1_BASE_S (AHB2PERIPH_BASE_S + 0x08000UL) -#define ADC12_COMMON_BASE_S (AHB2PERIPH_BASE_S + 0x08308UL) -#define DCMI_BASE_S (AHB2PERIPH_BASE_S + 0x0C000UL) -#define PSSI_BASE_S (AHB2PERIPH_BASE_S + 0x0C400UL) -#define USB_OTG_FS_BASE_S (AHB2PERIPH_BASE_S + 0x20000UL) -#define AES_BASE_S (AHB2PERIPH_BASE_S + 0xA0000UL) -#define HASH_BASE_S (AHB2PERIPH_BASE_S + 0xA0400UL) -#define HASH_DIGEST_BASE_S (AHB2PERIPH_BASE_S + 0xA0710UL) -#define RNG_BASE_S (AHB2PERIPH_BASE_S + 0xA0800UL) -#define SAES_BASE_S (AHB2PERIPH_BASE_S + 0xA0C00UL) -#define PKA_BASE_S (AHB2PERIPH_BASE_S + 0xA2000UL) -#define PKA_RAM_BASE_S (AHB2PERIPH_BASE_S + 0xA2400UL) -#define OTFDEC1_BASE_S (AHB2PERIPH_BASE_S + 0xA5000UL) -#define OTFDEC1_REGION1_BASE_S (OTFDEC1_BASE_S + 0x20UL) -#define OTFDEC1_REGION2_BASE_S (OTFDEC1_BASE_S + 0x50UL) -#define OTFDEC1_REGION3_BASE_S (OTFDEC1_BASE_S + 0x80UL) -#define OTFDEC1_REGION4_BASE_S (OTFDEC1_BASE_S + 0xB0UL) -#define OTFDEC2_BASE_S (AHB2PERIPH_BASE_S + 0xA5400UL) -#define OTFDEC2_REGION1_BASE_S (OTFDEC2_BASE_S + 0x20UL) -#define OTFDEC2_REGION2_BASE_S (OTFDEC2_BASE_S + 0x50UL) -#define OTFDEC2_REGION3_BASE_S (OTFDEC2_BASE_S + 0x80UL) -#define OTFDEC2_REGION4_BASE_S (OTFDEC2_BASE_S + 0xB0UL) -#define OCTOSPIM_R_BASE_S (AHB2PERIPH_BASE_S + 0xA4000UL) /*!< OCTOSPIM control registers base address */ -#define SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8000UL) -#define SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8C00UL) -#define DLYB_SDMMC1_BASE_S (AHB2PERIPH_BASE_S + 0xA8400UL) -#define DLYB_SDMMC2_BASE_S (AHB2PERIPH_BASE_S + 0xA8800UL) -#define DLYB_OCTOSPI1_BASE_S (AHB2PERIPH_BASE_S + 0xAF000UL) -#define DLYB_OCTOSPI2_BASE_S (AHB2PERIPH_BASE_S + 0xAF400UL) -#define FMC_R_BASE_S (AHB2PERIPH_BASE_S + 0xB0400UL) /*!< FMC control registers base address */ -#define FMC_Bank1_R_BASE_S (FMC_R_BASE_S + 0x0000UL) -#define FMC_Bank1E_R_BASE_S (FMC_R_BASE_S + 0x0104UL) -#define FMC_Bank3_R_BASE_S (FMC_R_BASE_S + 0x0080UL) -#define OCTOSPI1_R_BASE_S (AHB2PERIPH_BASE_S + 0xB1400UL) /*!< OCTOSPI1 control registers base address */ -#define OCTOSPI2_R_BASE_S (AHB2PERIPH_BASE_S + 0xB2400UL) /*!< OCTOSPI2 control registers base address */ - -/*!< AHB3 Secure peripherals */ -#define LPGPIO1_BASE_S (AHB3PERIPH_BASE_S) -#define PWR_BASE_S (AHB3PERIPH_BASE_S + 0x0800UL) -#define RCC_BASE_S (AHB3PERIPH_BASE_S + 0x0C00UL) -#define ADC4_BASE_S (AHB3PERIPH_BASE_S + 0x1000UL) -#define ADC4_COMMON_BASE_S (AHB3PERIPH_BASE_S + 0x1308UL) -#define DAC1_BASE_S (AHB3PERIPH_BASE_S + 0x1800UL) -#define EXTI_BASE_S (AHB3PERIPH_BASE_S + 0x2000UL) -#define GTZC_TZSC2_BASE_S (AHB3PERIPH_BASE_S + 0x3000UL) -#define GTZC_TZIC2_BASE_S (AHB3PERIPH_BASE_S + 0x3400UL) -#define GTZC_MPCBB4_BASE_S (AHB3PERIPH_BASE_S + 0x3800UL) -#define ADF1_BASE_S (AHB3PERIPH_BASE_S + 0x4000UL) -#define ADF1_Filter0_BASE_S (ADF1_BASE_S + 0x80UL) -#define LPDMA1_BASE_S (AHB3PERIPH_BASE_S + 0x5000UL) -#define LPDMA1_Channel0_BASE_S (LPDMA1_BASE_S + 0x0050UL) -#define LPDMA1_Channel1_BASE_S (LPDMA1_BASE_S + 0x00D0UL) -#define LPDMA1_Channel2_BASE_S (LPDMA1_BASE_S + 0x0150UL) -#define LPDMA1_Channel3_BASE_S (LPDMA1_BASE_S + 0x01D0UL) - - -/* Debug MCU registers base address */ -#define DBGMCU_BASE (0xE0044000UL) -#define PACKAGE_BASE (0x0BFA0500UL) /*!< Package data register base address */ -#define UID_BASE (0x0BFA0700UL) /*!< Unique device ID register base address */ -#define FLASHSIZE_BASE (0x0BFA07A0UL) /*!< Flash size data register base address */ - -/* Internal Flash OTP Area */ -#define FLASH_OTP_BASE (0x0BFA0000UL) /*!< FLASH OTP (one-time programmable) base address */ -#define FLASH_OTP_SIZE (0x200U) /*!< 512 bytes OTP (one-time programmable) */ - -/* USB OTG registers Base address */ -#define USB_OTG_GLOBAL_BASE (0x0000UL) -#define USB_OTG_DEVICE_BASE (0x0800UL) -#define USB_OTG_IN_ENDPOINT_BASE (0x0900UL) -#define USB_OTG_OUT_ENDPOINT_BASE (0x0B00UL) -#define USB_OTG_EP_REG_SIZE (0x0020UL) -#define USB_OTG_HOST_BASE (0x0400UL) -#define USB_OTG_HOST_PORT_BASE (0x0440UL) -#define USB_OTG_HOST_CHANNEL_BASE (0x0500UL) -#define USB_OTG_HOST_CHANNEL_SIZE (0x0020UL) -#define USB_OTG_PCGCCTL_BASE (0x0E00UL) -#define USB_OTG_FIFO_BASE (0x1000UL) -#define USB_OTG_FIFO_SIZE (0x1000UL) - -/*!< Root Secure Service Library */ -/************ RSSLIB SAU system Flash region definition constants *************/ -#define RSSLIB_SYS_FLASH_NS_PFUNC_START (0x0BF99E40UL) -#define RSSLIB_SYS_FLASH_NS_PFUNC_END (0x0BF99EFFUL) - -/************ RSSLIB function return constants ********************************/ -#define RSSLIB_ERROR (0xF5F5F5F5UL) -#define RSSLIB_SUCCESS (0xEAEAEAEAUL) - -/*!< RSSLIB pointer function structure address definition */ -#define RSSLIB_PFUNC_BASE RSSLIB_SYS_FLASH_NS_PFUNC_START -#define RSSLIB_PFUNC ((RSSLIB_pFunc_TypeDef *)RSSLIB_PFUNC_BASE) - -/*!< HDP Area constant definition */ -#define RSSLIB_HDP_AREA_Pos (0U) -#define RSSLIB_HDP_AREA_Msk (0x3UL << RSSLIB_HDP_AREA_Pos ) -#define RSSLIB_HDP_AREA1_Pos (0U) -#define RSSLIB_HDP_AREA1_Msk (0x1UL << RSSLIB_HDP_AREA1_Pos ) -#define RSSLIB_HDP_AREA2_Pos (1U) -#define RSSLIB_HDP_AREA2_Msk (0x1UL << RSSLIB_HDP_AREA2_Pos ) - -/** - * @brief Prototype of RSSLIB Close and exit HDP Function - * @detail This function close the requested hdp area passed in input - * parameter and jump to the reset handler present within the - * Vector table. The function does not return on successful execution. - * @param HdpArea notifies which hdp area to close, can be a combination of - * hdpa area 1 and hdp area 2 - * @param pointer on the vector table containing the reset handler the function - * jumps to. - * @retval RSSLIB_RSS_ERROR on error on input parameter, otherwise does not return. - */ -typedef uint32_t ( *RSSLIB_S_CloseExitHDP_TypeDef)( uint32_t HdpArea, uint32_t VectorTableAddr ); - - -/** - * @brief RSSLib non-secure callable function pointer structure - */ -typedef struct -{ - __IM uint32_t Reserved[8]; -}NSC_pFuncTypeDef; - -/** - * @brief RSSLib secure callable function pointer structure - */ -typedef struct -{ - __IM uint32_t Reserved2[2]; - __IM RSSLIB_S_CloseExitHDP_TypeDef CloseExitHDP; /*!< RSSLIB Bootloader Close and exit HDP Address offset: 0x28 */ -}S_pFuncTypeDef; - -/** - * @brief RSSLib function pointer structure - */ -typedef struct -{ - NSC_pFuncTypeDef NSC; - S_pFuncTypeDef S; -}RSSLIB_pFunc_TypeDef; - -/** @} */ /* End of group STM32U5xx_Peripheral_peripheralAddr */ - - -/* =========================================================================================================================== */ -/* ================ Peripheral declaration ================ */ -/* =========================================================================================================================== */ - - -/** @addtogroup STM32U5xx_Peripheral_declaration - * @{ - */ - -/*!< APB1 Non secure peripherals */ -#define TIM2_NS ((TIM_TypeDef *) TIM2_BASE_NS) -#define TIM3_NS ((TIM_TypeDef *) TIM3_BASE_NS) -#define TIM4_NS ((TIM_TypeDef *) TIM4_BASE_NS) -#define TIM5_NS ((TIM_TypeDef *) TIM5_BASE_NS) -#define TIM6_NS ((TIM_TypeDef *) TIM6_BASE_NS) -#define TIM7_NS ((TIM_TypeDef *) TIM7_BASE_NS) -#define WWDG_NS ((WWDG_TypeDef *) WWDG_BASE_NS) -#define IWDG_NS ((IWDG_TypeDef *) IWDG_BASE_NS) -#define SPI2_NS ((SPI_TypeDef *) SPI2_BASE_NS) -#define USART2_NS ((USART_TypeDef *) USART2_BASE_NS) -#define USART3_NS ((USART_TypeDef *) USART3_BASE_NS) -#define UART4_NS ((USART_TypeDef *) UART4_BASE_NS) -#define UART5_NS ((USART_TypeDef *) UART5_BASE_NS) -#define I2C1_NS ((I2C_TypeDef *) I2C1_BASE_NS) -#define I2C2_NS ((I2C_TypeDef *) I2C2_BASE_NS) -#define CRS_NS ((CRS_TypeDef *) CRS_BASE_NS) -#define I2C4_NS ((I2C_TypeDef *) I2C4_BASE_NS) -#define LPTIM2_NS ((LPTIM_TypeDef *) LPTIM2_BASE_NS) -#define FDCAN1_NS ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_NS) -#define FDCAN_CONFIG_NS ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_NS) -#define UCPD1_NS ((UCPD_TypeDef *) UCPD1_BASE_NS) - -/*!< APB2 Non secure peripherals */ -#define TIM1_NS ((TIM_TypeDef *) TIM1_BASE_NS) -#define SPI1_NS ((SPI_TypeDef *) SPI1_BASE_NS) -#define TIM8_NS ((TIM_TypeDef *) TIM8_BASE_NS) -#define USART1_NS ((USART_TypeDef *) USART1_BASE_NS) -#define TIM15_NS ((TIM_TypeDef *) TIM15_BASE_NS) -#define TIM16_NS ((TIM_TypeDef *) TIM16_BASE_NS) -#define TIM17_NS ((TIM_TypeDef *) TIM17_BASE_NS) -#define SAI1_NS ((SAI_TypeDef *) SAI1_BASE_NS) -#define SAI1_Block_A_NS ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_NS) -#define SAI1_Block_B_NS ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_NS) -#define SAI2_NS ((SAI_TypeDef *) SAI2_BASE_NS) -#define SAI2_Block_A_NS ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_NS) -#define SAI2_Block_B_NS ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_NS) - -/*!< APB3 Non secure peripherals */ -#define SYSCFG_NS ((SYSCFG_TypeDef *) SYSCFG_BASE_NS) -#define SPI3_NS ((SPI_TypeDef *) SPI3_BASE_NS) -#define LPUART1_NS ((USART_TypeDef *) LPUART1_BASE_NS) -#define I2C3_NS ((I2C_TypeDef *) I2C3_BASE_NS) -#define LPTIM1_NS ((LPTIM_TypeDef *) LPTIM1_BASE_NS) -#define LPTIM3_NS ((LPTIM_TypeDef *) LPTIM3_BASE_NS) -#define LPTIM4_NS ((LPTIM_TypeDef *) LPTIM4_BASE_NS) -#define OPAMP_NS ((OPAMP_TypeDef *) OPAMP_BASE_NS) -#define OPAMP1_NS ((OPAMP_TypeDef *) OPAMP1_BASE_NS) -#define OPAMP2_NS ((OPAMP_TypeDef *) OPAMP2_BASE_NS) -#define OPAMP12_COMMON_NS ((OPAMP_Common_TypeDef *) OPAMP1_BASE_NS) -#define COMP12_NS ((COMP_TypeDef *) COMP12_BASE_NS) -#define COMP1_NS ((COMP_TypeDef *) COMP1_BASE_NS) -#define COMP2_NS ((COMP_TypeDef *) COMP2_BASE_NS) -#define COMP12_COMMON_NS ((COMP_Common_TypeDef *) COMP1_BASE_NS) -#define VREFBUF_NS ((VREFBUF_TypeDef *) VREFBUF_BASE_NS) -#define RTC_NS ((RTC_TypeDef *) RTC_BASE_NS) -#define TAMP_NS ((TAMP_TypeDef *) TAMP_BASE_NS) - -/*!< AHB1 Non secure peripherals */ -#define GPDMA1_NS ((DMA_TypeDef *) GPDMA1_BASE_NS) -#define GPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_NS) -#define GPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_NS) -#define GPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_NS) -#define GPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_NS) -#define GPDMA1_Channel4_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_NS) -#define GPDMA1_Channel5_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_NS) -#define GPDMA1_Channel6_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_NS) -#define GPDMA1_Channel7_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_NS) -#define GPDMA1_Channel8_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_NS) -#define GPDMA1_Channel9_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_NS) -#define GPDMA1_Channel10_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_NS) -#define GPDMA1_Channel11_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_NS) -#define GPDMA1_Channel12_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_NS) -#define GPDMA1_Channel13_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_NS) -#define GPDMA1_Channel14_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_NS) -#define GPDMA1_Channel15_NS ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_NS) -#define CORDIC_NS ((CORDIC_TypeDef *) CORDIC_BASE_NS) -#define FMAC_NS ((FMAC_TypeDef *) FMAC_BASE_NS) -#define FLASH_NS ((FLASH_TypeDef *) FLASH_R_BASE_NS) -#define CRC_NS ((CRC_TypeDef *) CRC_BASE_NS) -#define TSC_NS ((TSC_TypeDef *) TSC_BASE_NS) -#define MDF1_NS ((MDF_TypeDef *) MDF1_BASE_NS) -#define MDF1_Filter0_NS ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_NS) -#define MDF1_Filter1_NS ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_NS) -#define MDF1_Filter2_NS ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_NS) -#define MDF1_Filter3_NS ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_NS) -#define MDF1_Filter4_NS ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_NS) -#define MDF1_Filter5_NS ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_NS) -#define RAMCFG_SRAM1_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_NS) -#define RAMCFG_SRAM2_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_NS) -#define RAMCFG_SRAM3_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_NS) -#define RAMCFG_SRAM4_NS ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_NS) -#define RAMCFG_BKPRAM_NS ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_NS) -#define DMA2D_NS ((DMA2D_TypeDef *) DMA2D_BASE_NS) -#define ICACHE_NS ((ICACHE_TypeDef *) ICACHE_BASE_NS) -#define DCACHE1_NS ((DCACHE_TypeDef *) DCACHE1_BASE_NS) -#define GTZC_TZSC1_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_NS) -#define GTZC_TZIC1_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_NS) -#define GTZC_MPCBB1_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_NS) -#define GTZC_MPCBB2_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_NS) -#define GTZC_MPCBB3_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_NS) - -/*!< AHB2 Non secure peripherals */ -#define GPIOA_NS ((GPIO_TypeDef *) GPIOA_BASE_NS) -#define GPIOB_NS ((GPIO_TypeDef *) GPIOB_BASE_NS) -#define GPIOC_NS ((GPIO_TypeDef *) GPIOC_BASE_NS) -#define GPIOD_NS ((GPIO_TypeDef *) GPIOD_BASE_NS) -#define GPIOE_NS ((GPIO_TypeDef *) GPIOE_BASE_NS) -#define GPIOF_NS ((GPIO_TypeDef *) GPIOF_BASE_NS) -#define GPIOG_NS ((GPIO_TypeDef *) GPIOG_BASE_NS) -#define GPIOH_NS ((GPIO_TypeDef *) GPIOH_BASE_NS) -#define GPIOI_NS ((GPIO_TypeDef *) GPIOI_BASE_NS) -#define ADC1_NS ((ADC_TypeDef *) ADC1_BASE_NS) -#define ADC12_COMMON_NS ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_NS) -#define DCMI_NS ((DCMI_TypeDef *) DCMI_BASE_NS) -#define PSSI_NS ((PSSI_TypeDef *) PSSI_BASE_NS) -#define USB_OTG_FS_NS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_NS) -#define AES_NS ((AES_TypeDef *) AES_BASE_NS) -#define HASH_NS ((HASH_TypeDef *) HASH_BASE_NS) -#define HASH_DIGEST_NS ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_NS) -#define RNG_NS ((RNG_TypeDef *) RNG_BASE_NS) -#define SAES_NS ((AES_TypeDef *) SAES_BASE_NS) -#define PKA_NS ((PKA_TypeDef *) PKA_BASE_NS) -#define OTFDEC1_NS ((OTFDEC_TypeDef *) OTFDEC1_BASE_NS) -#define OTFDEC1_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_NS) -#define OTFDEC1_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_NS) -#define OTFDEC1_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_NS) -#define OTFDEC1_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_NS) -#define OTFDEC2_NS ((OTFDEC_TypeDef *) OTFDEC2_BASE_NS) -#define OTFDEC2_REGION1_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_NS) -#define OTFDEC2_REGION2_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_NS) -#define OTFDEC2_REGION3_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_NS) -#define OTFDEC2_REGION4_NS ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_NS) -#define SDMMC1_NS ((SDMMC_TypeDef *) SDMMC1_BASE_NS) -#define SDMMC2_NS ((SDMMC_TypeDef *) SDMMC2_BASE_NS) -#define DLYB_SDMMC1_NS ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_NS) -#define DLYB_SDMMC2_NS ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_NS) -#define DLYB_OCTOSPI1_NS ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_NS) -#define DLYB_OCTOSPI2_NS ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_NS) -#define FMC_Bank1_R_NS ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_NS) -#define FMC_Bank1E_R_NS ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_NS) -#define FMC_Bank3_R_NS ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_NS) -#define OCTOSPIM_NS ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_NS) -#define OCTOSPI1_NS ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_NS) -#define OCTOSPI2_NS ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_NS) - -/*!< AHB3 Non secure peripherals */ -#define LPGPIO1_NS ((GPIO_TypeDef *) LPGPIO1_BASE_NS) -#define PWR_NS ((PWR_TypeDef *) PWR_BASE_NS) -#define RCC_NS ((RCC_TypeDef *) RCC_BASE_NS) -#define ADC4_NS ((ADC_TypeDef *) ADC4_BASE_NS) -#define ADC4_COMMON_NS ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_NS) -#define DAC1_NS ((DAC_TypeDef *) DAC1_BASE_NS) -#define EXTI_NS ((EXTI_TypeDef *) EXTI_BASE_NS) -#define GTZC_TZSC2_NS ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_NS) -#define GTZC_TZIC2_NS ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_NS) -#define GTZC_MPCBB4_NS ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_NS) -#define ADF1_NS ((MDF_TypeDef *) ADF1_BASE_NS) -#define ADF1_Filter0_NS ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_NS) -#define LPDMA1_NS ((DMA_TypeDef *) LPDMA1_BASE_NS) -#define LPDMA1_Channel0_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_NS) -#define LPDMA1_Channel1_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_NS) -#define LPDMA1_Channel2_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_NS) -#define LPDMA1_Channel3_NS ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_NS) - -/*!< APB1 Secure peripherals */ -#define TIM2_S ((TIM_TypeDef *) TIM2_BASE_S) -#define TIM3_S ((TIM_TypeDef *) TIM3_BASE_S) -#define TIM4_S ((TIM_TypeDef *) TIM4_BASE_S) -#define TIM5_S ((TIM_TypeDef *) TIM5_BASE_S) -#define TIM6_S ((TIM_TypeDef *) TIM6_BASE_S) -#define TIM7_S ((TIM_TypeDef *) TIM7_BASE_S) -#define WWDG_S ((WWDG_TypeDef *) WWDG_BASE_S) -#define IWDG_S ((IWDG_TypeDef *) IWDG_BASE_S) -#define SPI2_S ((SPI_TypeDef *) SPI2_BASE_S) -#define USART2_S ((USART_TypeDef *) USART2_BASE_S) -#define USART3_S ((USART_TypeDef *) USART3_BASE_S) -#define UART4_S ((USART_TypeDef *) UART4_BASE_S) -#define UART5_S ((USART_TypeDef *) UART5_BASE_S) -#define I2C1_S ((I2C_TypeDef *) I2C1_BASE_S) -#define I2C2_S ((I2C_TypeDef *) I2C2_BASE_S) -#define CRS_S ((CRS_TypeDef *) CRS_BASE_S) -#define I2C4_S ((I2C_TypeDef *) I2C4_BASE_S) -#define LPTIM2_S ((LPTIM_TypeDef *) LPTIM2_BASE_S) -#define FDCAN1_S ((FDCAN_GlobalTypeDef *) FDCAN1_BASE_S) -#define FDCAN_CONFIG_S ((FDCAN_Config_TypeDef *) FDCAN_CONFIG_BASE_S) -#define UCPD1_S ((UCPD_TypeDef *) UCPD1_BASE_S) - -/*!< APB2 Secure peripherals */ -#define TIM1_S ((TIM_TypeDef *) TIM1_BASE_S) -#define SPI1_S ((SPI_TypeDef *) SPI1_BASE_S) -#define TIM8_S ((TIM_TypeDef *) TIM8_BASE_S) -#define USART1_S ((USART_TypeDef *) USART1_BASE_S) -#define TIM15_S ((TIM_TypeDef *) TIM15_BASE_S) -#define TIM16_S ((TIM_TypeDef *) TIM16_BASE_S) -#define TIM17_S ((TIM_TypeDef *) TIM17_BASE_S) -#define SAI1_S ((SAI_TypeDef *) SAI1_BASE_S) -#define SAI1_Block_A_S ((SAI_Block_TypeDef *)SAI1_Block_A_BASE_S) -#define SAI1_Block_B_S ((SAI_Block_TypeDef *)SAI1_Block_B_BASE_S) -#define SAI2_S ((SAI_TypeDef *) SAI2_BASE_S) -#define SAI2_Block_A_S ((SAI_Block_TypeDef *)SAI2_Block_A_BASE_S) -#define SAI2_Block_B_S ((SAI_Block_TypeDef *)SAI2_Block_B_BASE_S) - -/*!< APB3 secure peripherals */ -#define SYSCFG_S ((SYSCFG_TypeDef *) SYSCFG_BASE_S) -#define SPI3_S ((SPI_TypeDef *) SPI3_BASE_S) -#define LPUART1_S ((USART_TypeDef *) LPUART1_BASE_S) -#define I2C3_S ((I2C_TypeDef *) I2C3_BASE_S) -#define LPTIM1_S ((LPTIM_TypeDef *) LPTIM1_BASE_S) -#define LPTIM3_S ((LPTIM_TypeDef *) LPTIM3_BASE_S) -#define LPTIM4_S ((LPTIM_TypeDef *) LPTIM4_BASE_S) -#define OPAMP_S ((OPAMP_TypeDef *) OPAMP_BASE_S) -#define OPAMP1_S ((OPAMP_TypeDef *) OPAMP1_BASE_S) -#define OPAMP2_S ((OPAMP_TypeDef *) OPAMP2_BASE_S) -#define OPAMP12_COMMON_S ((OPAMP_Common_TypeDef *) OPAMP1_BASE_S) -#define COMP12_S ((COMP_TypeDef *) COMP12_BASE_S) -#define COMP1_S ((COMP_TypeDef *) COMP1_BASE_S) -#define COMP2_S ((COMP_TypeDef *) COMP2_BASE_S) -#define COMP12_COMMON_S ((COMP_Common_TypeDef *) COMP1_BASE_S) -#define VREFBUF_S ((VREFBUF_TypeDef *) VREFBUF_BASE_S) -#define RTC_S ((RTC_TypeDef *) RTC_BASE_S) -#define TAMP_S ((TAMP_TypeDef *) TAMP_BASE_S) - -/*!< AHB1 Secure peripherals */ -#define GPDMA1_S ((DMA_TypeDef *) GPDMA1_BASE_S) -#define GPDMA1_Channel0_S ((DMA_Channel_TypeDef *) GPDMA1_Channel0_BASE_S) -#define GPDMA1_Channel1_S ((DMA_Channel_TypeDef *) GPDMA1_Channel1_BASE_S) -#define GPDMA1_Channel2_S ((DMA_Channel_TypeDef *) GPDMA1_Channel2_BASE_S) -#define GPDMA1_Channel3_S ((DMA_Channel_TypeDef *) GPDMA1_Channel3_BASE_S) -#define GPDMA1_Channel4_S ((DMA_Channel_TypeDef *) GPDMA1_Channel4_BASE_S) -#define GPDMA1_Channel5_S ((DMA_Channel_TypeDef *) GPDMA1_Channel5_BASE_S) -#define GPDMA1_Channel6_S ((DMA_Channel_TypeDef *) GPDMA1_Channel6_BASE_S) -#define GPDMA1_Channel7_S ((DMA_Channel_TypeDef *) GPDMA1_Channel7_BASE_S) -#define GPDMA1_Channel8_S ((DMA_Channel_TypeDef *) GPDMA1_Channel8_BASE_S) -#define GPDMA1_Channel9_S ((DMA_Channel_TypeDef *) GPDMA1_Channel9_BASE_S) -#define GPDMA1_Channel10_S ((DMA_Channel_TypeDef *) GPDMA1_Channel10_BASE_S) -#define GPDMA1_Channel11_S ((DMA_Channel_TypeDef *) GPDMA1_Channel11_BASE_S) -#define GPDMA1_Channel12_S ((DMA_Channel_TypeDef *) GPDMA1_Channel12_BASE_S) -#define GPDMA1_Channel13_S ((DMA_Channel_TypeDef *) GPDMA1_Channel13_BASE_S) -#define GPDMA1_Channel14_S ((DMA_Channel_TypeDef *) GPDMA1_Channel14_BASE_S) -#define GPDMA1_Channel15_S ((DMA_Channel_TypeDef *) GPDMA1_Channel15_BASE_S) -#define CORDIC_S ((CORDIC_TypeDef *) CORDIC_BASE_S) -#define FMAC_S ((FMAC_TypeDef *) FMAC_BASE_S) -#define FLASH_S ((FLASH_TypeDef *) FLASH_R_BASE_S) -#define CRC_S ((CRC_TypeDef *) CRC_BASE_S) -#define TSC_S ((TSC_TypeDef *) TSC_BASE_S) -#define MDF1_S ((MDF_TypeDef *) MDF1_BASE_S) -#define MDF1_Filter0_S ((MDF_Filter_TypeDef*) MDF1_Filter0_BASE_S) -#define MDF1_Filter1_S ((MDF_Filter_TypeDef*) MDF1_Filter1_BASE_S) -#define MDF1_Filter2_S ((MDF_Filter_TypeDef*) MDF1_Filter2_BASE_S) -#define MDF1_Filter3_S ((MDF_Filter_TypeDef*) MDF1_Filter3_BASE_S) -#define MDF1_Filter4_S ((MDF_Filter_TypeDef*) MDF1_Filter4_BASE_S) -#define MDF1_Filter5_S ((MDF_Filter_TypeDef*) MDF1_Filter5_BASE_S) -#define RAMCFG_SRAM1_S ((RAMCFG_TypeDef *) RAMCFG_SRAM1_BASE_S) -#define RAMCFG_SRAM2_S ((RAMCFG_TypeDef *) RAMCFG_SRAM2_BASE_S) -#define RAMCFG_SRAM3_S ((RAMCFG_TypeDef *) RAMCFG_SRAM3_BASE_S) -#define RAMCFG_SRAM4_S ((RAMCFG_TypeDef *) RAMCFG_SRAM4_BASE_S) -#define RAMCFG_BKPRAM_S ((RAMCFG_TypeDef *) RAMCFG_BKPRAM_BASE_S) -#define DMA2D_S ((DMA2D_TypeDef *) DMA2D_BASE_S) -#define ICACHE_S ((ICACHE_TypeDef *) ICACHE_BASE_S) -#define DCACHE1_S ((DCACHE_TypeDef *) DCACHE1_BASE_S) -#define GTZC_TZSC1_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC1_BASE_S) -#define GTZC_TZIC1_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC1_BASE_S) -#define GTZC_MPCBB1_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB1_BASE_S) -#define GTZC_MPCBB2_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB2_BASE_S) -#define GTZC_MPCBB3_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB3_BASE_S) - -/*!< AHB2 Secure peripherals */ -#define GPIOA_S ((GPIO_TypeDef *) GPIOA_BASE_S) -#define GPIOB_S ((GPIO_TypeDef *) GPIOB_BASE_S) -#define GPIOC_S ((GPIO_TypeDef *) GPIOC_BASE_S) -#define GPIOD_S ((GPIO_TypeDef *) GPIOD_BASE_S) -#define GPIOE_S ((GPIO_TypeDef *) GPIOE_BASE_S) -#define GPIOF_S ((GPIO_TypeDef *) GPIOF_BASE_S) -#define GPIOG_S ((GPIO_TypeDef *) GPIOG_BASE_S) -#define GPIOH_S ((GPIO_TypeDef *) GPIOH_BASE_S) -#define GPIOI_S ((GPIO_TypeDef *) GPIOI_BASE_S) -#define ADC1_S ((ADC_TypeDef *) ADC1_BASE_S) -#define ADC12_COMMON_S ((ADC_Common_TypeDef *) ADC12_COMMON_BASE_S) -#define DCMI_S ((DCMI_TypeDef *) DCMI_BASE_S) -#define PSSI_S ((PSSI_TypeDef *) PSSI_BASE_S) -#define USB_OTG_FS_S ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_BASE_S) -#define AES_S ((AES_TypeDef *) AES_BASE_S) -#define HASH_S ((HASH_TypeDef *) HASH_BASE_S) -#define HASH_DIGEST_S ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE_S) -#define RNG_S ((RNG_TypeDef *) RNG_BASE_S) -#define SAES_S ((AES_TypeDef *) SAES_BASE_S) -#define PKA_S ((PKA_TypeDef *) PKA_BASE_S) -#define OTFDEC1_S ((OTFDEC_TypeDef *) OTFDEC1_BASE_S) -#define OTFDEC1_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE_S) -#define OTFDEC1_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE_S) -#define OTFDEC1_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE_S) -#define OTFDEC1_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE_S) -#define OTFDEC2_S ((OTFDEC_TypeDef *) OTFDEC2_BASE_S) -#define OTFDEC2_REGION1_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE_S) -#define OTFDEC2_REGION2_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE_S) -#define OTFDEC2_REGION3_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE_S) -#define OTFDEC2_REGION4_S ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE_S) -#define SDMMC1_S ((SDMMC_TypeDef *) SDMMC1_BASE_S) -#define SDMMC2_S ((SDMMC_TypeDef *) SDMMC2_BASE_S) -#define DLYB_SDMMC1_S ((DLYB_TypeDef *) DLYB_SDMMC1_BASE_S) -#define DLYB_SDMMC2_S ((DLYB_TypeDef *) DLYB_SDMMC2_BASE_S) -#define DLYB_OCTOSPI1_S ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE_S) -#define DLYB_OCTOSPI2_S ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE_S) -#define FMC_Bank1_R_S ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE_S) -#define FMC_Bank1E_R_S ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE_S) -#define FMC_Bank3_R_S ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE_S) -#define OCTOSPIM_S ((OCTOSPIM_TypeDef *) OCTOSPIM_R_BASE_S) -#define OCTOSPI1_S ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE_S) -#define OCTOSPI2_S ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE_S) - -/*!< AHB3 Secure peripherals */ -#define LPGPIO1_S ((GPIO_TypeDef *) LPGPIO1_BASE_S) -#define PWR_S ((PWR_TypeDef *) PWR_BASE_S) -#define RCC_S ((RCC_TypeDef *) RCC_BASE_S) -#define ADC4_S ((ADC_TypeDef *) ADC4_BASE_S) -#define ADC4_COMMON_S ((ADC_Common_TypeDef *) ADC4_COMMON_BASE_S) -#define DAC1_S ((DAC_TypeDef *) DAC1_BASE_S) -#define EXTI_S ((EXTI_TypeDef *) EXTI_BASE_S) -#define GTZC_TZSC2_S ((GTZC_TZSC_TypeDef *) GTZC_TZSC2_BASE_S) -#define GTZC_TZIC2_S ((GTZC_TZIC_TypeDef *) GTZC_TZIC2_BASE_S) -#define GTZC_MPCBB4_S ((GTZC_MPCBB_TypeDef *) GTZC_MPCBB4_BASE_S) -#define ADF1_S ((MDF_TypeDef *) ADF1_BASE_S) -#define ADF1_Filter0_S ((MDF_Filter_TypeDef*) ADF1_Filter0_BASE_S) -#define LPDMA1_S ((DMA_TypeDef *) LPDMA1_BASE_S) -#define LPDMA1_Channel0_S ((DMA_Channel_TypeDef *) LPDMA1_Channel0_BASE_S) -#define LPDMA1_Channel1_S ((DMA_Channel_TypeDef *) LPDMA1_Channel1_BASE_S) -#define LPDMA1_Channel2_S ((DMA_Channel_TypeDef *) LPDMA1_Channel2_BASE_S) -#define LPDMA1_Channel3_S ((DMA_Channel_TypeDef *) LPDMA1_Channel3_BASE_S) - -/*!< DBGMCU peripheral */ -#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) - -/*!< Memory & Instance aliases and base addresses for Non-Secure/Secure peripherals */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/*!< Memory base addresses for Secure peripherals */ -#define FLASH_BASE FLASH_BASE_S -#define SRAM1_BASE SRAM1_BASE_S -#define SRAM2_BASE SRAM2_BASE_S -#define SRAM3_BASE SRAM3_BASE_S -#define SRAM4_BASE SRAM4_BASE_S -#define BKPSRAM_BASE BKPSRAM_BASE_S -#define PERIPH_BASE PERIPH_BASE_S -#define APB1PERIPH_BASE APB1PERIPH_BASE_S -#define APB2PERIPH_BASE APB2PERIPH_BASE_S -#define AHB1PERIPH_BASE AHB1PERIPH_BASE_S -#define AHB2PERIPH_BASE AHB2PERIPH_BASE_S - -/*!< Instance aliases and base addresses for Secure peripherals */ -#define CORDIC CORDIC_S -#define CORDIC_BASE CORDIC_BASE_S - -#define RCC RCC_S -#define RCC_BASE RCC_BASE_S - -#define DCMI DCMI_S -#define DCMI_BASE DCMI_BASE_S - -#define PSSI PSSI_S -#define PSSI_BASE PSSI_BASE_S - -#define FLASH FLASH_S -#define FLASH_R_BASE FLASH_R_BASE_S - -#define FMAC FMAC_S -#define FMAC_BASE FMAC_BASE_S - -#define GPDMA1 GPDMA1_S -#define GPDMA1_BASE GPDMA1_BASE_S - -#define GPDMA1_Channel0 GPDMA1_Channel0_S -#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_S - -#define GPDMA1_Channel1 GPDMA1_Channel1_S -#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_S - -#define GPDMA1_Channel2 GPDMA1_Channel2_S -#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_S - -#define GPDMA1_Channel3 GPDMA1_Channel3_S -#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_S - -#define GPDMA1_Channel4 GPDMA1_Channel4_S -#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_S - -#define GPDMA1_Channel5 GPDMA1_Channel5_S -#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_S - -#define GPDMA1_Channel6 GPDMA1_Channel6_S -#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_S - -#define GPDMA1_Channel7 GPDMA1_Channel7_S -#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_S - -#define GPDMA1_Channel8 GPDMA1_Channel8_S -#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_S - -#define GPDMA1_Channel9 GPDMA1_Channel9_S -#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_S - -#define GPDMA1_Channel10 GPDMA1_Channel10_S -#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_S - -#define GPDMA1_Channel11 GPDMA1_Channel11_S -#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_S - -#define GPDMA1_Channel12 GPDMA1_Channel12_S -#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_S - -#define GPDMA1_Channel13 GPDMA1_Channel13_S -#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_S - -#define GPDMA1_Channel14 GPDMA1_Channel14_S -#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_S - -#define GPDMA1_Channel15 GPDMA1_Channel15_S -#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_S - -#define LPDMA1 LPDMA1_S -#define LPDMA1_BASE LPDMA1_BASE_S - -#define LPDMA1_Channel0 LPDMA1_Channel0_S -#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_S - -#define LPDMA1_Channel1 LPDMA1_Channel1_S -#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_S - -#define LPDMA1_Channel2 LPDMA1_Channel2_S -#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_S - -#define LPDMA1_Channel3 LPDMA1_Channel3_S -#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_S - -#define GPIOA GPIOA_S -#define GPIOA_BASE GPIOA_BASE_S - -#define GPIOB GPIOB_S -#define GPIOB_BASE GPIOB_BASE_S - -#define GPIOC GPIOC_S -#define GPIOC_BASE GPIOC_BASE_S - -#define GPIOD GPIOD_S -#define GPIOD_BASE GPIOD_BASE_S - -#define GPIOE GPIOE_S -#define GPIOE_BASE GPIOE_BASE_S - -#define GPIOF GPIOF_S -#define GPIOF_BASE GPIOF_BASE_S - -#define GPIOG GPIOG_S -#define GPIOG_BASE GPIOG_BASE_S - -#define GPIOH GPIOH_S -#define GPIOH_BASE GPIOH_BASE_S - -#define GPIOI GPIOI_S -#define GPIOI_BASE GPIOI_BASE_S - -#define LPGPIO1 LPGPIO1_S -#define LPGPIO1_BASE LPGPIO1_BASE_S - -#define PWR PWR_S -#define PWR_BASE PWR_BASE_S - -#define RAMCFG_SRAM1 RAMCFG_SRAM1_S -#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_S - -#define RAMCFG_SRAM2 RAMCFG_SRAM2_S -#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_S - -#define RAMCFG_SRAM3 RAMCFG_SRAM3_S -#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_S - -#define RAMCFG_SRAM4 RAMCFG_SRAM4_S -#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_S - -#define RAMCFG_BKPRAM RAMCFG_BKPRAM_S -#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_S - -#define EXTI EXTI_S -#define EXTI_BASE EXTI_BASE_S - -#define ICACHE ICACHE_S -#define ICACHE_BASE ICACHE_BASE_S - -#define DCACHE1 DCACHE1_S -#define DCACHE1_BASE DCACHE1_BASE_S - -#define GTZC_TZSC1 GTZC_TZSC1_S -#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_S - -#define GTZC_TZSC2 GTZC_TZSC2_S -#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_S - -#define GTZC_TZIC1 GTZC_TZIC1_S -#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_S - -#define GTZC_TZIC2 GTZC_TZIC2_S -#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_S - -#define GTZC_MPCBB1 GTZC_MPCBB1_S -#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_S - -#define GTZC_MPCBB2 GTZC_MPCBB2_S -#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_S - -#define GTZC_MPCBB3 GTZC_MPCBB3_S -#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_S - -#define GTZC_MPCBB4 GTZC_MPCBB4_S -#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_S - -#define RTC RTC_S -#define RTC_BASE RTC_BASE_S - -#define TAMP TAMP_S -#define TAMP_BASE TAMP_BASE_S - -#define TIM1 TIM1_S -#define TIM1_BASE TIM1_BASE_S - -#define TIM2 TIM2_S -#define TIM2_BASE TIM2_BASE_S - -#define TIM3 TIM3_S -#define TIM3_BASE TIM3_BASE_S - -#define TIM4 TIM4_S -#define TIM4_BASE TIM4_BASE_S - -#define TIM5 TIM5_S -#define TIM5_BASE TIM5_BASE_S - -#define TIM6 TIM6_S -#define TIM6_BASE TIM6_BASE_S - -#define TIM7 TIM7_S -#define TIM7_BASE TIM7_BASE_S - -#define TIM8 TIM8_S -#define TIM8_BASE TIM8_BASE_S - -#define TIM15 TIM15_S -#define TIM15_BASE TIM15_BASE_S - -#define TIM16 TIM16_S -#define TIM16_BASE TIM16_BASE_S - -#define TIM17 TIM17_S -#define TIM17_BASE TIM17_BASE_S - -#define WWDG WWDG_S -#define WWDG_BASE WWDG_BASE_S - -#define IWDG IWDG_S -#define IWDG_BASE IWDG_BASE_S - -#define SPI1 SPI1_S -#define SPI1_BASE SPI1_BASE_S - -#define SPI2 SPI2_S -#define SPI2_BASE SPI2_BASE_S - -#define SPI3 SPI3_S -#define SPI3_BASE SPI3_BASE_S - -#define USART1 USART1_S -#define USART1_BASE USART1_BASE_S - -#define USART2 USART2_S -#define USART2_BASE USART2_BASE_S - -#define USART3 USART3_S -#define USART3_BASE USART3_BASE_S - -#define UART4 UART4_S -#define UART4_BASE UART4_BASE_S - -#define UART5 UART5_S -#define UART5_BASE UART5_BASE_S - -#define I2C1 I2C1_S -#define I2C1_BASE I2C1_BASE_S - -#define I2C2 I2C2_S -#define I2C2_BASE I2C2_BASE_S - -#define I2C3 I2C3_S -#define I2C3_BASE I2C3_BASE_S - -#define I2C4 I2C4_S -#define I2C4_BASE I2C4_BASE_S - -#define CRS CRS_S -#define CRS_BASE CRS_BASE_S - -#define FDCAN1 FDCAN1_S -#define FDCAN1_BASE FDCAN1_BASE_S - -#define FDCAN_CONFIG FDCAN_CONFIG_S -#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_S -#define SRAMCAN_BASE SRAMCAN_BASE_S - -#define DAC DAC_S -#define DAC_BASE DAC_BASE_S - -#define DAC1 DAC1_S -#define DAC1_BASE DAC1_BASE_S - -#define OPAMP OPAMP_S -#define OPAMP_BASE OPAMP_BASE_S - -#define OPAMP1 OPAMP1_S -#define OPAMP1_BASE OPAMP1_BASE_S - -#define OPAMP2 OPAMP2_S -#define OPAMP2_BASE OPAMP2_BASE_S - -#define OPAMP12_COMMON OPAMP12_COMMON_S -#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_S - -#define LPTIM1 LPTIM1_S -#define LPTIM1_BASE LPTIM1_BASE_S - -#define LPTIM2 LPTIM2_S -#define LPTIM2_BASE LPTIM2_BASE_S - -#define LPTIM3 LPTIM3_S -#define LPTIM3_BASE LPTIM3_BASE_S - -#define LPTIM4 LPTIM4_S -#define LPTIM4_BASE LPTIM4_BASE_S - -#define LPUART1 LPUART1_S -#define LPUART1_BASE LPUART1_BASE_S - -#define UCPD1 UCPD1_S -#define UCPD1_BASE UCPD1_BASE_S - -#define SYSCFG SYSCFG_S -#define SYSCFG_BASE SYSCFG_BASE_S - -#define VREFBUF VREFBUF_S -#define VREFBUF_BASE VREFBUF_BASE_S - -#define COMP12 COMP12_S -#define COMP12_BASE COMP12_BASE_S - -#define COMP1 COMP1_S -#define COMP1_BASE COMP1_BASE_S - -#define COMP2 COMP2_S -#define COMP2_BASE COMP2_BASE_S - -#define COMP12_COMMON COMP12_COMMON_S -#define COMP12_COMMON_BASE COMP1_BASE_S - -#define SAI1 SAI1_S -#define SAI1_BASE SAI1_BASE_S - -#define SAI1_Block_A SAI1_Block_A_S -#define SAI1_Block_A_BASE SAI1_Block_A_BASE_S - -#define SAI1_Block_B SAI1_Block_B_S -#define SAI1_Block_B_BASE SAI1_Block_B_BASE_S - -#define SAI2 SAI2_S -#define SAI2_BASE SAI2_BASE_S - -#define SAI2_Block_A SAI2_Block_A_S -#define SAI2_Block_A_BASE SAI2_Block_A_BASE_S - -#define SAI2_Block_B SAI2_Block_B_S -#define SAI2_Block_B_BASE SAI2_Block_B_BASE_S - -#define CRC CRC_S -#define CRC_BASE CRC_BASE_S - -#define TSC TSC_S -#define TSC_BASE TSC_BASE_S - -#define ADC1 ADC1_S -#define ADC1_BASE ADC1_BASE_S - -#define ADC12_COMMON ADC12_COMMON_S -#define ADC12_COMMON_BASE ADC12_COMMON_BASE_S - - -#define ADC4 ADC4_S -#define ADC4_BASE ADC4_BASE_S - -#define ADC4_COMMON ADC4_COMMON_S -#define ADC4_COMMON_BASE ADC4_COMMON_BASE_S - -#define HASH HASH_S -#define HASH_BASE HASH_BASE_S - -#define HASH_DIGEST HASH_DIGEST_S -#define HASH_DIGEST_BASE HASH_DIGEST_BASE_S - -#define AES AES_S -#define AES_BASE AES_BASE_S - -#define RNG RNG_S -#define RNG_BASE RNG_BASE_S - -#define SAES SAES_S -#define SAES_BASE SAES_BASE_S - -#define PKA PKA_S -#define PKA_BASE PKA_BASE_S -#define PKA_RAM_BASE PKA_RAM_BASE_S - -#define OTFDEC1 OTFDEC1_S -#define OTFDEC1_BASE OTFDEC1_BASE_S - -#define OTFDEC1_REGION1 OTFDEC1_REGION1_S -#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_S - -#define OTFDEC1_REGION2 OTFDEC1_REGION2_S -#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_S - -#define OTFDEC1_REGION3 OTFDEC1_REGION3_S -#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_S - -#define OTFDEC1_REGION4 OTFDEC1_REGION4_S -#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_S - -#define OTFDEC2 OTFDEC2_S -#define OTFDEC2_BASE OTFDEC2_BASE_S - -#define OTFDEC2_REGION1 OTFDEC2_REGION1_S -#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_S - -#define OTFDEC2_REGION2 OTFDEC2_REGION2_S -#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_S - -#define OTFDEC2_REGION3 OTFDEC2_REGION3_S -#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_S - -#define OTFDEC2_REGION4 OTFDEC2_REGION4_S -#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_S - -#define SDMMC1 SDMMC1_S -#define SDMMC1_BASE SDMMC1_BASE_S - -#define SDMMC2 SDMMC2_S -#define SDMMC2_BASE SDMMC2_BASE_S - -#define FMC_Bank1_R FMC_Bank1_R_S -#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_S - -#define FMC_Bank1E_R FMC_Bank1E_R_S -#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_S - -#define FMC_Bank3_R FMC_Bank3_R_S -#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_S - -#define OCTOSPI1 OCTOSPI1_S -#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_S - -#define OCTOSPI2 OCTOSPI2_S -#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_S - -#define OCTOSPIM OCTOSPIM_S -#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_S - -#define DLYB_SDMMC1 DLYB_SDMMC1_S -#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_S - -#define DLYB_SDMMC2 DLYB_SDMMC2_S -#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_S - -#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_S -#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_S - -#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_S -#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_S - -#define DMA2D DMA2D_S -#define DMA2D_BASE DMA2D_BASE_S - -#define USB_OTG_FS USB_OTG_FS_S -#define USB_OTG_FS_BASE USB_OTG_FS_BASE_S - -#define MDF1 MDF1_S -#define MDF1_BASE MDF1_BASE_S - -#define MDF1_Filter0 MDF1_Filter0_S -#define MDF1_Filter0_BASE MDF1_Filter0_BASE_S - -#define MDF1_Filter1 MDF1_Filter1_S -#define MDF1_Filter1_BASE MDF1_Filter1_BASE_S - -#define MDF1_Filter2 MDF1_Filter2_S -#define MDF1_Filter2_BASE MDF1_Filter2_BASE_S - -#define MDF1_Filter3 MDF1_Filter3_S -#define MDF1_Filter3_BASE MDF1_Filter3_BASE_S - -#define MDF1_Filter4 MDF1_Filter4_S -#define MDF1_Filter4_BASE MDF1_Filter4_BASE_S - -#define MDF1_Filter5 MDF1_Filter5_S -#define MDF1_Filter5_BASE MDF1_Filter5_BASE_S - -#define ADF1 ADF1_S -#define ADF1_BASE ADF1_BASE_S - -#define ADF1_Filter0 ADF1_Filter0_S -#define ADF1_Filter0_BASE ADF1_Filter0_BASE_S - -#else -/*!< Memory base addresses for Non secure peripherals */ -#define FLASH_BASE FLASH_BASE_NS -#define SRAM1_BASE SRAM1_BASE_NS -#define SRAM2_BASE SRAM2_BASE_NS -#define SRAM3_BASE SRAM3_BASE_NS -#define SRAM4_BASE SRAM4_BASE_NS -#define BKPSRAM_BASE BKPSRAM_BASE_NS -#define PERIPH_BASE PERIPH_BASE_NS -#define APB1PERIPH_BASE APB1PERIPH_BASE_NS -#define APB2PERIPH_BASE APB2PERIPH_BASE_NS -#define AHB1PERIPH_BASE AHB1PERIPH_BASE_NS -#define AHB2PERIPH_BASE AHB2PERIPH_BASE_NS - -/*!< Instance aliases and base addresses for Non secure peripherals */ -#define CORDIC CORDIC_NS -#define CORDIC_BASE CORDIC_BASE_NS - -#define RCC RCC_NS -#define RCC_BASE RCC_BASE_NS - -#define DMA2D DMA2D_NS -#define DMA2D_BASE DMA2D_BASE_NS - -#define DCMI DCMI_NS -#define DCMI_BASE DCMI_BASE_NS - -#define PSSI PSSI_NS -#define PSSI_BASE PSSI_BASE_NS - -#define FLASH FLASH_NS -#define FLASH_R_BASE FLASH_R_BASE_NS - -#define FMAC FMAC_NS -#define FMAC_BASE FMAC_BASE_NS - -#define GPDMA1 GPDMA1_NS -#define GPDMA1_BASE GPDMA1_BASE_NS - -#define GPDMA1_Channel0 GPDMA1_Channel0_NS -#define GPDMA1_Channel0_BASE GPDMA1_Channel0_BASE_NS - -#define GPDMA1_Channel1 GPDMA1_Channel1_NS -#define GPDMA1_Channel1_BASE GPDMA1_Channel1_BASE_NS - -#define GPDMA1_Channel2 GPDMA1_Channel2_NS -#define GPDMA1_Channel2_BASE GPDMA1_Channel2_BASE_NS - -#define GPDMA1_Channel3 GPDMA1_Channel3_NS -#define GPDMA1_Channel3_BASE GPDMA1_Channel3_BASE_NS - -#define GPDMA1_Channel4 GPDMA1_Channel4_NS -#define GPDMA1_Channel4_BASE GPDMA1_Channel4_BASE_NS - -#define GPDMA1_Channel5 GPDMA1_Channel5_NS -#define GPDMA1_Channel5_BASE GPDMA1_Channel5_BASE_NS - -#define GPDMA1_Channel6 GPDMA1_Channel6_NS -#define GPDMA1_Channel6_BASE GPDMA1_Channel6_BASE_NS - -#define GPDMA1_Channel7 GPDMA1_Channel7_NS -#define GPDMA1_Channel7_BASE GPDMA1_Channel7_BASE_NS - -#define GPDMA1_Channel8 GPDMA1_Channel8_NS -#define GPDMA1_Channel8_BASE GPDMA1_Channel8_BASE_NS - -#define GPDMA1_Channel9 GPDMA1_Channel9_NS -#define GPDMA1_Channel9_BASE GPDMA1_Channel9_BASE_NS - -#define GPDMA1_Channel10 GPDMA1_Channel10_NS -#define GPDMA1_Channel10_BASE GPDMA1_Channel10_BASE_NS - -#define GPDMA1_Channel11 GPDMA1_Channel11_NS -#define GPDMA1_Channel11_BASE GPDMA1_Channel11_BASE_NS - -#define GPDMA1_Channel12 GPDMA1_Channel12_NS -#define GPDMA1_Channel12_BASE GPDMA1_Channel12_BASE_NS - -#define GPDMA1_Channel13 GPDMA1_Channel13_NS -#define GPDMA1_Channel13_BASE GPDMA1_Channel13_BASE_NS - -#define GPDMA1_Channel14 GPDMA1_Channel14_NS -#define GPDMA1_Channel14_BASE GPDMA1_Channel14_BASE_NS - -#define GPDMA1_Channel15 GPDMA1_Channel15_NS -#define GPDMA1_Channel15_BASE GPDMA1_Channel15_BASE_NS - -#define LPDMA1 LPDMA1_NS -#define LPDMA1_BASE LPDMA1_BASE_NS - -#define LPDMA1_Channel0 LPDMA1_Channel0_NS -#define LPDMA1_Channel0_BASE LPDMA1_Channel0_BASE_NS - -#define LPDMA1_Channel1 LPDMA1_Channel1_NS -#define LPDMA1_Channel1_BASE LPDMA1_Channel1_BASE_NS - -#define LPDMA1_Channel2 LPDMA1_Channel2_NS -#define LPDMA1_Channel2_BASE LPDMA1_Channel2_BASE_NS - -#define LPDMA1_Channel3 LPDMA1_Channel3_NS -#define LPDMA1_Channel3_BASE LPDMA1_Channel3_BASE_NS - -#define GPIOA GPIOA_NS -#define GPIOA_BASE GPIOA_BASE_NS - -#define GPIOB GPIOB_NS -#define GPIOB_BASE GPIOB_BASE_NS - -#define GPIOC GPIOC_NS -#define GPIOC_BASE GPIOC_BASE_NS - -#define GPIOD GPIOD_NS -#define GPIOD_BASE GPIOD_BASE_NS - -#define GPIOE GPIOE_NS -#define GPIOE_BASE GPIOE_BASE_NS - -#define GPIOF GPIOF_NS -#define GPIOF_BASE GPIOF_BASE_NS - -#define GPIOG GPIOG_NS -#define GPIOG_BASE GPIOG_BASE_NS - -#define GPIOH GPIOH_NS -#define GPIOH_BASE GPIOH_BASE_NS - -#define GPIOI GPIOI_NS -#define GPIOI_BASE GPIOI_BASE_NS -#define LPGPIO1 LPGPIO1_NS -#define LPGPIO1_BASE LPGPIO1_BASE_NS - -#define PWR PWR_NS -#define PWR_BASE PWR_BASE_NS - -#define RAMCFG_SRAM1 RAMCFG_SRAM1_NS -#define RAMCFG_SRAM1_BASE RAMCFG_SRAM1_BASE_NS - -#define RAMCFG_SRAM2 RAMCFG_SRAM2_NS -#define RAMCFG_SRAM2_BASE RAMCFG_SRAM2_BASE_NS - -#define RAMCFG_SRAM3 RAMCFG_SRAM3_NS -#define RAMCFG_SRAM3_BASE RAMCFG_SRAM3_BASE_NS - -#define RAMCFG_SRAM4 RAMCFG_SRAM4_NS -#define RAMCFG_SRAM4_BASE RAMCFG_SRAM4_BASE_NS - -#define RAMCFG_BKPRAM RAMCFG_BKPRAM_NS -#define RAMCFG_BKPRAM_BASE RAMCFG_BKPRAM_BASE_NS - -#define EXTI EXTI_NS -#define EXTI_BASE EXTI_BASE_NS - -#define ICACHE ICACHE_NS -#define ICACHE_BASE ICACHE_BASE_NS - -#define DCACHE1 DCACHE1_NS -#define DCACHE1_BASE DCACHE1_BASE_NS - -#define GTZC_TZSC1 GTZC_TZSC1_NS -#define GTZC_TZSC1_BASE GTZC_TZSC1_BASE_NS - -#define GTZC_TZSC2 GTZC_TZSC2_NS -#define GTZC_TZSC2_BASE GTZC_TZSC2_BASE_NS - -#define GTZC_TZIC1 GTZC_TZIC1_NS -#define GTZC_TZIC1_BASE GTZC_TZIC1_BASE_NS - -#define GTZC_TZIC2 GTZC_TZIC2_NS -#define GTZC_TZIC2_BASE GTZC_TZIC2_BASE_NS - -#define GTZC_MPCBB1 GTZC_MPCBB1_NS -#define GTZC_MPCBB1_BASE GTZC_MPCBB1_BASE_NS - -#define GTZC_MPCBB2 GTZC_MPCBB2_NS -#define GTZC_MPCBB2_BASE GTZC_MPCBB2_BASE_NS - -#define GTZC_MPCBB3 GTZC_MPCBB3_NS -#define GTZC_MPCBB3_BASE GTZC_MPCBB3_BASE_NS - -#define GTZC_MPCBB4 GTZC_MPCBB4_NS -#define GTZC_MPCBB4_BASE GTZC_MPCBB4_BASE_NS - -#define RTC RTC_NS -#define RTC_BASE RTC_BASE_NS - -#define TAMP TAMP_NS -#define TAMP_BASE TAMP_BASE_NS - -#define TIM1 TIM1_NS -#define TIM1_BASE TIM1_BASE_NS - -#define TIM2 TIM2_NS -#define TIM2_BASE TIM2_BASE_NS - -#define TIM3 TIM3_NS -#define TIM3_BASE TIM3_BASE_NS - -#define TIM4 TIM4_NS -#define TIM4_BASE TIM4_BASE_NS - -#define TIM5 TIM5_NS -#define TIM5_BASE TIM5_BASE_NS - -#define TIM6 TIM6_NS -#define TIM6_BASE TIM6_BASE_NS - -#define TIM7 TIM7_NS -#define TIM7_BASE TIM7_BASE_NS - -#define TIM8 TIM8_NS -#define TIM8_BASE TIM8_BASE_NS - -#define TIM15 TIM15_NS -#define TIM15_BASE TIM15_BASE_NS - -#define TIM16 TIM16_NS -#define TIM16_BASE TIM16_BASE_NS - -#define TIM17 TIM17_NS -#define TIM17_BASE TIM17_BASE_NS - -#define WWDG WWDG_NS -#define WWDG_BASE WWDG_BASE_NS - -#define IWDG IWDG_NS -#define IWDG_BASE IWDG_BASE_NS - -#define SPI1 SPI1_NS -#define SPI1_BASE SPI1_BASE_NS - -#define SPI2 SPI2_NS -#define SPI2_BASE SPI2_BASE_NS - -#define SPI3 SPI3_NS -#define SPI3_BASE SPI3_BASE_NS - -#define USART1 USART1_NS -#define USART1_BASE USART1_BASE_NS - -#define USART2 USART2_NS -#define USART2_BASE USART2_BASE_NS - -#define USART3 USART3_NS -#define USART3_BASE USART3_BASE_NS - -#define UART4 UART4_NS -#define UART4_BASE UART4_BASE_NS - -#define UART5 UART5_NS -#define UART5_BASE UART5_BASE_NS - -#define I2C1 I2C1_NS -#define I2C1_BASE I2C1_BASE_NS - -#define I2C2 I2C2_NS -#define I2C2_BASE I2C2_BASE_NS - -#define I2C3 I2C3_NS -#define I2C3_BASE I2C3_BASE_NS - -#define I2C4 I2C4_NS -#define I2C4_BASE I2C4_BASE_NS - -#define CRS CRS_NS -#define CRS_BASE CRS_BASE_NS - -#define FDCAN1 FDCAN1_NS -#define FDCAN1_BASE FDCAN1_BASE_NS - -#define FDCAN_CONFIG FDCAN_CONFIG_NS -#define FDCAN_CONFIG_BASE FDCAN_CONFIG_BASE_NS -#define SRAMCAN_BASE SRAMCAN_BASE_NS - -#define DAC1 DAC1_NS -#define DAC1_BASE DAC1_BASE_NS - -#define OPAMP OPAMP_NS -#define OPAMP_BASE OPAMP_BASE_NS - -#define OPAMP1 OPAMP1_NS -#define OPAMP1_BASE OPAMP1_BASE_NS - -#define OPAMP2 OPAMP2_NS -#define OPAMP2_BASE OPAMP2_BASE_NS - -#define OPAMP12_COMMON OPAMP12_COMMON_NS -#define OPAMP12_COMMON_BASE OPAMP12_COMMON_BASE_NS - -#define LPTIM1 LPTIM1_NS -#define LPTIM1_BASE LPTIM1_BASE_NS - -#define LPTIM2 LPTIM2_NS -#define LPTIM2_BASE LPTIM2_BASE_NS - -#define LPTIM3 LPTIM3_NS -#define LPTIM3_BASE LPTIM3_BASE_NS - -#define LPTIM4 LPTIM4_NS -#define LPTIM4_BASE LPTIM4_BASE_NS - -#define LPUART1 LPUART1_NS -#define LPUART1_BASE LPUART1_BASE_NS - -#define UCPD1 UCPD1_NS -#define UCPD1_BASE UCPD1_BASE_NS - -#define SYSCFG SYSCFG_NS -#define SYSCFG_BASE SYSCFG_BASE_NS - -#define VREFBUF VREFBUF_NS -#define VREFBUF_BASE VREFBUF_BASE_NS - -#define COMP12 COMP12_NS -#define COMP12_BASE COMP12_BASE_NS - -#define COMP1 COMP1_NS -#define COMP1_BASE COMP1_BASE_NS - -#define COMP2 COMP2_NS -#define COMP2_BASE COMP2_BASE_NS - -#define COMP12_COMMON COMP12_COMMON_NS -#define COMP12_COMMON_BASE COMP1_BASE_NS - -#define SAI1 SAI1_NS -#define SAI1_BASE SAI1_BASE_NS - -#define SAI1_Block_A SAI1_Block_A_NS -#define SAI1_Block_A_BASE SAI1_Block_A_BASE_NS - -#define SAI1_Block_B SAI1_Block_B_NS -#define SAI1_Block_B_BASE SAI1_Block_B_BASE_NS - -#define SAI2 SAI2_NS -#define SAI2_BASE SAI2_BASE_NS - -#define SAI2_Block_A SAI2_Block_A_NS -#define SAI2_Block_A_BASE SAI2_Block_A_BASE_NS - -#define SAI2_Block_B SAI2_Block_B_NS -#define SAI2_Block_B_BASE SAI2_Block_B_BASE_NS - -#define CRC CRC_NS -#define CRC_BASE CRC_BASE_NS - -#define TSC TSC_NS -#define TSC_BASE TSC_BASE_NS - -#define ADC1 ADC1_NS -#define ADC1_BASE ADC1_BASE_NS - -#define ADC12_COMMON ADC12_COMMON_NS -#define ADC12_COMMON_BASE ADC12_COMMON_BASE_NS - -#define ADC4 ADC4_NS -#define ADC4_BASE ADC4_BASE_NS - -#define ADC4_COMMON ADC4_COMMON_NS -#define ADC4_COMMON_BASE ADC4_COMMON_BASE_NS - -#define HASH HASH_NS -#define HASH_BASE HASH_BASE_NS - -#define HASH_DIGEST HASH_DIGEST_NS -#define HASH_DIGEST_BASE HASH_DIGEST_BASE_NS - -#define AES AES_NS -#define AES_BASE AES_BASE_NS - -#define RNG RNG_NS -#define RNG_BASE RNG_BASE_NS - -#define SAES SAES_NS -#define SAES_BASE SAES_BASE_NS - -#define PKA PKA_NS -#define PKA_BASE PKA_BASE_NS -#define PKA_RAM_BASE PKA_RAM_BASE_NS - -#define OTFDEC1 OTFDEC1_NS -#define OTFDEC1_BASE OTFDEC1_BASE_NS - -#define OTFDEC1_REGION1 OTFDEC1_REGION1_NS -#define OTFDEC1_REGION1_BASE OTFDEC1_REGION1_BASE_NS - -#define OTFDEC1_REGION2 OTFDEC1_REGION2_NS -#define OTFDEC1_REGION2_BASE OTFDEC1_REGION2_BASE_NS - -#define OTFDEC1_REGION3 OTFDEC1_REGION3_NS -#define OTFDEC1_REGION3_BASE OTFDEC1_REGION3_BASE_NS - -#define OTFDEC1_REGION4 OTFDEC1_REGION4_NS -#define OTFDEC1_REGION4_BASE OTFDEC1_REGION4_BASE_NS - -#define OTFDEC2 OTFDEC2_NS -#define OTFDEC2_BASE OTFDEC2_BASE_NS - -#define OTFDEC2_REGION1 OTFDEC2_REGION1_NS -#define OTFDEC2_REGION1_BASE OTFDEC2_REGION1_BASE_NS - -#define OTFDEC2_REGION2 OTFDEC2_REGION2_NS -#define OTFDEC2_REGION2_BASE OTFDEC2_REGION2_BASE_NS - -#define OTFDEC2_REGION3 OTFDEC2_REGION3_NS -#define OTFDEC2_REGION3_BASE OTFDEC2_REGION3_BASE_NS - -#define OTFDEC2_REGION4 OTFDEC2_REGION4_NS -#define OTFDEC2_REGION4_BASE OTFDEC2_REGION4_BASE_NS - -#define SDMMC1 SDMMC1_NS -#define SDMMC1_BASE SDMMC1_BASE_NS - -#define SDMMC2 SDMMC2_NS -#define SDMMC2_BASE SDMMC2_BASE_NS - -#define FMC_Bank1_R FMC_Bank1_R_NS -#define FMC_Bank1_R_BASE FMC_Bank1_R_BASE_NS - -#define FMC_Bank1E_R FMC_Bank1E_R_NS -#define FMC_Bank1E_R_BASE FMC_Bank1E_R_BASE_NS - -#define FMC_Bank3_R FMC_Bank3_R_NS -#define FMC_Bank3_R_BASE FMC_Bank3_R_BASE_NS - -#define OCTOSPI1 OCTOSPI1_NS -#define OCTOSPI1_R_BASE OCTOSPI1_R_BASE_NS - -#define OCTOSPI2 OCTOSPI2_NS -#define OCTOSPI2_R_BASE OCTOSPI2_R_BASE_NS - -#define OCTOSPIM OCTOSPIM_NS -#define OCTOSPIM_R_BASE OCTOSPIM_R_BASE_NS - -#define DLYB_SDMMC1 DLYB_SDMMC1_NS -#define DLYB_SDMMC1_BASE DLYB_SDMMC1_BASE_NS - -#define DLYB_SDMMC2 DLYB_SDMMC2_NS -#define DLYB_SDMMC2_BASE DLYB_SDMMC2_BASE_NS - -#define DLYB_OCTOSPI1 DLYB_OCTOSPI1_NS -#define DLYB_OCTOSPI1_BASE DLYB_OCTOSPI1_BASE_NS - -#define DLYB_OCTOSPI2 DLYB_OCTOSPI2_NS -#define DLYB_OCTOSPI2_BASE DLYB_OCTOSPI2_BASE_NS - -#define USB_OTG_FS USB_OTG_FS_NS -#define USB_OTG_FS_BASE USB_OTG_FS_BASE_NS - -#define MDF1 MDF1_NS -#define MDF1_BASE MDF1_BASE_NS - -#define MDF1_Filter0 MDF1_Filter0_NS -#define MDF1_Filter0_BASE MDF1_Filter0_BASE_NS - -#define MDF1_Filter1 MDF1_Filter1_NS -#define MDF1_Filter1_BASE MDF1_Filter1_BASE_NS - -#define MDF1_Filter2 MDF1_Filter2_NS -#define MDF1_Filter2_BASE MDF1_Filter2_BASE_NS - -#define MDF1_Filter3 MDF1_Filter3_NS -#define MDF1_Filter3_BASE MDF1_Filter3_BASE_NS - -#define MDF1_Filter4 MDF1_Filter4_NS -#define MDF1_Filter4_BASE MDF1_Filter4_BASE_NS - -#define MDF1_Filter5 MDF1_Filter5_NS -#define MDF1_Filter5_BASE MDF1_Filter5_BASE_NS - -#define ADF1 ADF1_NS -#define ADF1_BASE ADF1_BASE_NS - -#define ADF1_Filter0 ADF1_Filter0_NS -#define ADF1_Filter0_BASE ADF1_Filter0_BASE_NS -#endif - -/** @addtogroup Hardware_Constant_Definition - * @{ - */ -#define LSI_STARTUP_TIME 260U /*!< LSI Maximum startup time in us */ - -/** - * @} - */ - -/******************************************************************************/ -/* */ -/* Analog to Digital Converter */ -/* */ -/******************************************************************************/ -/******************************* ADC VERSION ********************************/ -#define ADC_VER_V5_X -/******************** Bit definition for ADC_ISR register ********************/ -#define ADC_ISR_ADRDY_Pos (0U) -#define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */ -#define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */ -#define ADC_ISR_EOSMP_Pos (1U) -#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ -#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */ -#define ADC_ISR_EOC_Pos (2U) -#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ -#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */ -#define ADC_ISR_EOS_Pos (3U) -#define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */ -#define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_ISR_OVR_Pos (4U) -#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ -#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */ -#define ADC_ISR_JEOC_Pos (5U) -#define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */ -#define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */ -#define ADC_ISR_JEOS_Pos (6U) -#define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */ -#define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */ -#define ADC_ISR_AWD1_Pos (7U) -#define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */ -#define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */ -#define ADC_ISR_AWD2_Pos (8U) -#define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */ -#define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */ -#define ADC_ISR_AWD3_Pos (9U) -#define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */ -#define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */ -#define ADC_ISR_JQOVF_Pos (10U) -#define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */ -#define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */ -#define ADC_ISR_EOCAL_Pos (11U) -#define ADC_ISR_EOCAL_Msk (0x1UL << ADC_ISR_EOCAL_Pos) /*!< 0x00000800 */ -#define ADC_ISR_EOCAL ADC_ISR_EOCAL_Msk /*!< ADC End of Calibration flag */ -#define ADC_ISR_LDORDY_Pos (12U) -#define ADC_ISR_LDORDY_Msk (0x1UL << ADC_ISR_LDORDY_Pos) /*!< 0x00001000 */ -#define ADC_ISR_LDORDY ADC_ISR_LDORDY_Msk /*!< ADC Voltage Regulator Ready flag */ - -/******************** Bit definition for ADC_IER register ********************/ -#define ADC_IER_ADRDYIE_Pos (0U) -#define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */ -#define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */ -#define ADC_IER_EOSMPIE_Pos (1U) -#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ -#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */ -#define ADC_IER_EOCIE_Pos (2U) -#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ -#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */ -#define ADC_IER_EOSIE_Pos (3U) -#define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */ -#define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */ -#define ADC_IER_OVRIE_Pos (4U) -#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ -#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */ -#define ADC_IER_JEOCIE_Pos (5U) -#define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */ -#define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */ -#define ADC_IER_JEOSIE_Pos (6U) -#define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */ -#define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */ -#define ADC_IER_AWD1IE_Pos (7U) -#define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */ -#define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */ -#define ADC_IER_AWD2IE_Pos (8U) -#define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */ -#define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */ -#define ADC_IER_AWD3IE_Pos (9U) -#define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */ -#define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */ -#define ADC_IER_JQOVFIE_Pos (10U) -#define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */ -#define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */ -#define ADC_IER_EOCALIE_Pos (11U) -#define ADC_IER_EOCALIE_Msk (0x1UL << ADC_IER_EOCALIE_Pos) /*!< 0x00000800 */ -#define ADC_IER_EOCALIE ADC_IER_EOCALIE_Msk /*!< ADC End of Calibration Enable */ -#define ADC_IER_LDORDYIE_Pos (12U) -#define ADC_IER_LDORDYIE_Msk (0x1UL << ADC_IER_LDORDYIE_Pos) /*!< 0x00001000 */ -#define ADC_IER_LDORDYIE ADC_IER_LDORDYIE_Msk /*!< ADC Voltage Regulator Ready flag */ - -/******************** Bit definition for ADC_CR register ********************/ -#define ADC_CR_ADEN_Pos (0U) -#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ -#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */ -#define ADC_CR_ADDIS_Pos (1U) -#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ -#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */ -#define ADC_CR_ADSTART_Pos (2U) -#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ -#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */ -#define ADC_CR_JADSTART_Pos (3U) -#define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */ -#define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */ -#define ADC_CR_ADSTP_Pos (4U) -#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ -#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */ -#define ADC_CR_JADSTP_Pos (5U) -#define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */ -#define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */ -#define ADC_CR_ADCALLIN_Pos (16U) -#define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */ -#define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */ - -#define ADC_CR_CALINDEX_Pos (24U) -#define ADC_CR_CALINDEX_Msk (0xFUL << ADC_CR_CALINDEX_Pos) /*!< 0x0F000000 */ -#define ADC_CR_CALINDEX ADC_CR_CALINDEX_Msk /*!< ADC calibration factor selection */ -#define ADC_CR_CALINDEX0_Pos (24U) -#define ADC_CR_CALINDEX0_Msk (0x1UL << ADC_CR_CALINDEX0_Pos) /*!< 0x01000000 */ -#define ADC_CR_CALINDEX0 ADC_CR_CALINDEX0_Msk /*!< ADC calibration factor selection (bit 0) */ -#define ADC_CR_CALINDEX1_Pos (25U) -#define ADC_CR_CALINDEX1_Msk (0x1UL << ADC_CR_CALINDEX1_Pos) /*!< 0x02000000 */ -#define ADC_CR_CALINDEX1 ADC_CR_CALINDEX1_Msk /*!< ADC calibration factor selection (bit 1) */ -#define ADC_CR_CALINDEX2_Pos (26U) -#define ADC_CR_CALINDEX2_Msk (0x1UL << ADC_CR_CALINDEX2_Pos) /*!< 0x04000000 */ -#define ADC_CR_CALINDEX2 ADC_CR_CALINDEX2_Msk /*!< ADC calibration factor selection (bit 2) */ -#define ADC_CR_CALINDEX3_Pos (27U) -#define ADC_CR_CALINDEX3_Msk (0x1UL << ADC_CR_CALINDEX3_Pos) /*!< 0x08000000 */ -#define ADC_CR_CALINDEX3 ADC_CR_CALINDEX3_Msk /*!< ADC calibration factor selection (bit 3) */ -#define ADC_CR_ADVREGEN_Pos (28U) -#define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */ -#define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */ -#define ADC_CR_DEEPPWD_Pos (29U) -#define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */ -#define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */ -#define ADC_CR_ADCAL_Pos (31U) -#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ -#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */ - -/******************** Bit definition for ADC_CFGR register ********************/ -#define ADC_CFGR1_DMNGT_Pos (0U) -#define ADC_CFGR1_DMNGT_Msk (0x3UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000003 */ -#define ADC_CFGR1_DMNGT ADC_CFGR1_DMNGT_Msk /*!< ADC Data Management configuration */ -#define ADC_CFGR1_DMNGT_0 (0x1UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000001 */ -#define ADC_CFGR1_DMNGT_1 (0x2UL << ADC_CFGR1_DMNGT_Pos) /*!< 0x00000002 */ - -#define ADC_CFGR1_RES_Pos (2U) -#define ADC_CFGR1_RES_Msk (0x3UL << ADC_CFGR1_RES_Pos) /*!< 0x0000000C */ -#define ADC_CFGR1_RES ADC_CFGR1_RES_Msk /*!< ADC Data resolution */ -#define ADC_CFGR1_RES_0 (0x1UL << ADC_CFGR1_RES_Pos) /*!< 0x00000004 */ -#define ADC_CFGR1_RES_1 (0x2UL << ADC_CFGR1_RES_Pos) /*!< 0x00000008 */ - -#define ADC4_CFGR1_DMAEN_Pos (0U) -#define ADC4_CFGR1_DMAEN_Msk (0x1UL << ADC4_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ -#define ADC4_CFGR1_DMAEN ADC4_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ -#define ADC4_CFGR1_DMACFG_Pos (1U) -#define ADC4_CFGR1_DMACFG_Msk (0x1UL << ADC4_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ -#define ADC4_CFGR1_DMACFG ADC4_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ - -#define ADC4_CFGR1_SCANDIR_Pos (4U) -#define ADC4_CFGR1_SCANDIR_Msk (0x1UL << ADC4_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ -#define ADC4_CFGR1_SCANDIR ADC4_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ - -#define ADC4_CFGR1_ALIGN_Pos (5U) -#define ADC4_CFGR1_ALIGN_Msk (0x1UL << ADC4_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_ALIGN ADC4_CFGR1_ALIGN_Msk /*!< ADC data alignment */ - -#define ADC_CFGR1_EXTSEL_Pos (5U) -#define ADC_CFGR1_EXTSEL_Msk (0x1FUL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ -#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC_CFGR1_EXTSEL_0 (0x01UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_CFGR1_EXTSEL_1 (0x02UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC_CFGR1_EXTSEL_2 (0x04UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ -#define ADC_CFGR1_EXTSEL_3 (0x08UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ -#define ADC_CFGR1_EXTSEL_4 (0x10UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000200 */ - -#define ADC_CFGR1_EXTEN_Pos (10U) -#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ -#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */ -#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ -#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ - -#define ADC_CFGR1_OVRMOD_Pos (12U) -#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ -#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC overrun mode */ -#define ADC_CFGR1_CONT_Pos (13U) -#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ -#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */ - -#define ADC_CFGR1_AUTDLY_Pos (14U) -#define ADC_CFGR1_AUTDLY_Msk (0x1UL << ADC_CFGR1_AUTDLY_Pos) /*!< 0x00004000 */ -#define ADC_CFGR1_AUTDLY ADC_CFGR1_AUTDLY_Msk /*!< ADC Delayed conversion mode */ - -#define ADC4_CFGR1_WAIT_Pos (14U) -#define ADC4_CFGR1_WAIT_Msk (0x1UL << ADC4_CFGR1_WAIT_Pos) /*!< 0x00004000 */ -#define ADC4_CFGR1_WAIT ADC4_CFGR1_WAIT_Msk /*!< ADC Delayed conversion mode */ - -#define ADC_CFGR1_DISCEN_Pos (16U) -#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ -#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */ - -#define ADC_CFGR1_DISCNUM_Pos (17U) -#define ADC_CFGR1_DISCNUM_Msk (0x7UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x000E0000 */ -#define ADC_CFGR1_DISCNUM ADC_CFGR1_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */ -#define ADC_CFGR1_DISCNUM_0 (0x1UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00020000 */ -#define ADC_CFGR1_DISCNUM_1 (0x2UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00040000 */ -#define ADC_CFGR1_DISCNUM_2 (0x4UL << ADC_CFGR1_DISCNUM_Pos) /*!< 0x00080000 */ - -#define ADC_CFGR1_JDISCEN_Pos (20U) -#define ADC_CFGR1_JDISCEN_Msk (0x1UL << ADC_CFGR1_JDISCEN_Pos) /*!< 0x00100000 */ -#define ADC_CFGR1_JDISCEN ADC_CFGR1_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */ - -#define ADC_CFGR1_AWD1SGL_Pos (22U) -#define ADC_CFGR1_AWD1SGL_Msk (0x1UL << ADC_CFGR1_AWD1SGL_Pos) /*!< 0x00400000 */ -#define ADC_CFGR1_AWD1SGL ADC_CFGR1_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */ -#define ADC_CFGR1_AWD1EN_Pos (23U) -#define ADC_CFGR1_AWD1EN_Msk (0x1UL << ADC_CFGR1_AWD1EN_Pos) /*!< 0x00800000 */ -#define ADC_CFGR1_AWD1EN ADC_CFGR1_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */ -#define ADC_CFGR1_JAWD1EN_Pos (24U) -#define ADC_CFGR1_JAWD1EN_Msk (0x1UL << ADC_CFGR1_JAWD1EN_Pos) /*!< 0x01000000 */ -#define ADC_CFGR1_JAWD1EN ADC_CFGR1_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */ -#define ADC_CFGR1_JAUTO_Pos (25U) -#define ADC_CFGR1_JAUTO_Msk (0x1UL << ADC_CFGR1_JAUTO_Pos) /*!< 0x02000000 */ -#define ADC_CFGR1_JAUTO ADC_CFGR1_JAUTO_Msk /*!< ADC Automatic injected group conversion */ - -/* Specific ADC4 */ -#define ADC4_CFGR1_EXTSEL_Pos (6U) -#define ADC4_CFGR1_EXTSEL_Msk (0x7UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x000003E0 */ -#define ADC4_CFGR1_EXTSEL ADC4_CFGR1_EXTSEL_Msk /*!< ADC External trigger selection for regular group */ -#define ADC4_CFGR1_EXTSEL_0 (0x01UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000020 */ -#define ADC4_CFGR1_EXTSEL_1 (0x02UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ -#define ADC4_CFGR1_EXTSEL_2 (0x04UL << ADC4_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ - -#define ADC4_CFGR1_CHSELRMOD_Pos (21U) -#define ADC4_CFGR1_CHSELRMOD_Msk (0x1UL << ADC4_CFGR1_CHSELRMOD_Pos) /*!< 0x00200000 */ -#define ADC4_CFGR1_CHSELRMOD ADC4_CFGR1_CHSELRMOD_Msk /*!< ADC JSQR Queue mode */ - -#define ADC_CFGR1_AWD1CH_Pos (26U) -#define ADC_CFGR1_AWD1CH_Msk (0x1FUL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x7C000000 */ -#define ADC_CFGR1_AWD1CH ADC_CFGR1_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */ -#define ADC_CFGR1_AWD1CH_0 (0x01UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x04000000 */ -#define ADC_CFGR1_AWD1CH_1 (0x02UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x08000000 */ -#define ADC_CFGR1_AWD1CH_2 (0x04UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x10000000 */ -#define ADC_CFGR1_AWD1CH_3 (0x08UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x20000000 */ -#define ADC_CFGR1_AWD1CH_4 (0x10UL << ADC_CFGR1_AWD1CH_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_CFGR2 register ********************/ -#define ADC_CFGR2_ROVSE_Pos (0U) -#define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */ -#define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */ -#define ADC_CFGR2_JOVSE_Pos (1U) -#define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */ -#define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */ - -#define ADC_CFGR2_OVSS_Pos (5U) -#define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */ -#define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */ -#define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */ -#define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */ -#define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */ -#define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */ - -#define ADC_CFGR2_TROVS_Pos (9U) -#define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */ -#define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */ -#define ADC_CFGR2_ROVSM_Pos (10U) -#define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */ -#define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */ - -#define ADC_CFGR2_OVSR_Pos (16U) -#define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */ -#define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */ -#define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */ -#define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */ -#define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */ -#define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */ -#define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */ -#define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */ -#define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */ -#define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */ -#define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */ -#define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */ - -#define ADC_CFGR2_BULB_Pos (13U) -#define ADC_CFGR2_BULB_Msk (0x1UL << ADC_CFGR2_BULB_Pos) /*!< 0x00002000 */ -#define ADC_CFGR2_BULB ADC_CFGR2_BULB_Msk /*!< ADC Bulb sampling mode */ - -#define ADC_CFGR2_SWTRIG_Pos (14U) -#define ADC_CFGR2_SWTRIG_Msk (0x1UL << ADC_CFGR2_SWTRIG_Pos) /*!< 0x00004000 */ -#define ADC_CFGR2_SWTRIG ADC_CFGR2_SWTRIG_Msk /*!< ADC Software trigger bit for sampling time control trigger mode */ - -#define ADC_CFGR2_SMPTRIG_Pos (15U) -#define ADC_CFGR2_SMPTRIG_Msk (0x1UL << ADC_CFGR2_SMPTRIG_Pos) /*!< 0x00008000 */ -#define ADC_CFGR2_SMPTRIG ADC_CFGR2_SMPTRIG_Msk /*!< ADC Sampling time control trigger mode */ - -#define ADC_CFGR2_LFTRIG_Pos (27U) -#define ADC_CFGR2_LFTRIG_Msk (0x1UL << ADC_CFGR2_LFTRIG_Pos) /*!< 0x08000000 */ -#define ADC_CFGR2_LFTRIG ADC_CFGR2_LFTRIG_Msk /*!< ADC low frequency trigger mode */ - -#define ADC_CFGR2_LSHIFT_Pos (28U) -#define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */ -#define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */ -#define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */ -#define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */ -#define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */ -#define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */ - -/* Specific ADC4 */ -#define ADC4_CFGR2_OVSR_Pos (2U) -#define ADC4_CFGR2_OVSR_Msk (0x7UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x0000001C */ -#define ADC4_CFGR2_OVSR ADC4_CFGR2_OVSR_Msk /*!< ADC oversampling ratio */ -#define ADC4_CFGR2_OVSR_0 (0x1UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000004 */ -#define ADC4_CFGR2_OVSR_1 (0x2UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000008 */ -#define ADC4_CFGR2_OVSR_2 (0x4UL << ADC4_CFGR2_OVSR_Pos) /*!< 0x00000010 */ - -#define ADC4_CFGR2_LFTRIG_Pos (29U) -#define ADC4_CFGR2_LFTRIG_Msk (0x1UL << ADC4_CFGR2_LFTRIG_Pos) /*!< 0x20000000 */ -#define ADC4_CFGR2_LFTRIG ADC4_CFGR2_LFTRIG_Msk /*!< ADC4 low frequency trigger mode */ - -/******************** Bit definition for ADC_SMPR1 register ********************/ -#define ADC_SMPR1_SMP0_Pos (0U) -#define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */ -#define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */ -#define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */ -#define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */ -#define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR1_SMP1_Pos (3U) -#define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */ -#define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */ -#define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */ -#define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */ -#define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR1_SMP2_Pos (6U) -#define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */ -#define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */ -#define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */ -#define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR1_SMP3_Pos (9U) -#define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */ -#define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */ -#define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */ -#define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR1_SMP4_Pos (12U) -#define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */ -#define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */ -#define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */ -#define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */ -#define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR1_SMP5_Pos (15U) -#define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */ -#define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */ -#define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */ -#define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */ -#define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR1_SMP6_Pos (18U) -#define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */ -#define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */ -#define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */ -#define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR1_SMP7_Pos (21U) -#define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */ -#define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */ -#define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */ -#define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR1_SMP8_Pos (24U) -#define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */ -#define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */ -#define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */ -#define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */ -#define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR1_SMP9_Pos (27U) -#define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */ -#define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */ -#define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */ -#define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */ -#define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */ - -#define ADC4_SMPR_SMP1_Pos (0U) -#define ADC4_SMPR_SMP1_Msk (0x7UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000007 */ -#define ADC4_SMPR_SMP1 ADC4_SMPR_SMP1_Msk /*!< ADC Channel 0 Sampling time selection */ -#define ADC4_SMPR_SMP1_0 (0x1UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000001 */ -#define ADC4_SMPR_SMP1_1 (0x2UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000002 */ -#define ADC4_SMPR_SMP1_2 (0x4UL << ADC4_SMPR_SMP1_Pos) /*!< 0x00000004 */ - -#define ADC4_SMPR_SMP2_Pos (4U) -#define ADC4_SMPR_SMP2_Msk (0x7UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000070 */ -#define ADC4_SMPR_SMP2 ADC4_SMPR_SMP2_Msk /*!< ADC group of channels sampling time 2 */ -#define ADC4_SMPR_SMP2_0 (0x1UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000010 */ -#define ADC4_SMPR_SMP2_1 (0x2UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000020 */ -#define ADC4_SMPR_SMP2_2 (0x4UL << ADC4_SMPR_SMP2_Pos) /*!< 0x00000040 */ - -#define ADC4_SMPR_SMPSEL_Pos (8U) -#define ADC4_SMPR_SMPSEL_Msk (0xFFFFFFUL << ADC4_SMPR_SMPSEL_Pos) /*!< 0xFFFFFF00 */ -#define ADC4_SMPR_SMPSEL ADC4_SMPR_SMPSEL_Msk /*!< ADC4 all channels sampling time selection */ -#define ADC4_SMPR_SMPSEL0_Pos (8U) -#define ADC4_SMPR_SMPSEL0_Msk (0x1UL << ADC4_SMPR_SMPSEL0_Pos) /*!< 0x00000100 */ -#define ADC4_SMPR_SMPSEL0 ADC4_SMPR_SMPSEL0_Msk /*!< ADC4 channel 0 sampling time selection */ -#define ADC4_SMPR_SMPSEL1_Pos (9U) -#define ADC4_SMPR_SMPSEL1_Msk (0x1UL << ADC4_SMPR_SMPSEL1_Pos) /*!< 0x00000200 */ -#define ADC4_SMPR_SMPSEL1 ADC4_SMPR_SMPSEL1_Msk /*!< ADC4 channel 1 sampling time selection */ -#define ADC4_SMPR_SMPSEL2_Pos (10U) -#define ADC4_SMPR_SMPSEL2_Msk (0x1UL << ADC4_SMPR_SMPSEL2_Pos) /*!< 0x00000400 */ -#define ADC4_SMPR_SMPSEL2 ADC4_SMPR_SMPSEL2_Msk /*!< ADC4 channel 2 sampling time selection */ -#define ADC4_SMPR_SMPSEL3_Pos (11U) -#define ADC4_SMPR_SMPSEL3_Msk (0x1UL << ADC4_SMPR_SMPSEL3_Pos) /*!< 0x00000800 */ -#define ADC4_SMPR_SMPSEL3 ADC4_SMPR_SMPSEL3_Msk /*!< ADC4 channel 3 sampling time selection */ -#define ADC4_SMPR_SMPSEL4_Pos (12U) -#define ADC4_SMPR_SMPSEL4_Msk (0x1UL << ADC4_SMPR_SMPSEL4_Pos) /*!< 0x00001000 */ -#define ADC4_SMPR_SMPSEL4 ADC4_SMPR_SMPSEL4_Msk /*!< ADC4 channel 4 sampling time selection */ -#define ADC4_SMPR_SMPSEL5_Pos (13U) -#define ADC4_SMPR_SMPSEL5_Msk (0x1UL << ADC4_SMPR_SMPSEL5_Pos) /*!< 0x00002000 */ -#define ADC4_SMPR_SMPSEL5 ADC4_SMPR_SMPSEL5_Msk /*!< ADC4 channel 5 sampling time selection */ -#define ADC4_SMPR_SMPSEL6_Pos (14U) -#define ADC4_SMPR_SMPSEL6_Msk (0x1UL << ADC4_SMPR_SMPSEL6_Pos) /*!< 0x00004000 */ -#define ADC4_SMPR_SMPSEL6 ADC4_SMPR_SMPSEL6_Msk /*!< ADC4 channel 6 sampling time selection */ -#define ADC4_SMPR_SMPSEL7_Pos (15U) -#define ADC4_SMPR_SMPSEL7_Msk (0x1UL << ADC4_SMPR_SMPSEL7_Pos) /*!< 0x00008000 */ -#define ADC4_SMPR_SMPSEL7 ADC4_SMPR_SMPSEL7_Msk /*!< ADC4 channel 7 sampling time selection */ -#define ADC4_SMPR_SMPSEL8_Pos (16U) -#define ADC4_SMPR_SMPSEL8_Msk (0x1UL << ADC4_SMPR_SMPSEL8_Pos) /*!< 0x00010000 */ -#define ADC4_SMPR_SMPSEL8 ADC4_SMPR_SMPSEL8_Msk /*!< ADC4 channel 8 sampling time selection */ -#define ADC4_SMPR_SMPSEL9_Pos (17U) -#define ADC4_SMPR_SMPSEL9_Msk (0x1UL << ADC4_SMPR_SMPSEL9_Pos) /*!< 0x00020000 */ -#define ADC4_SMPR_SMPSEL9 ADC4_SMPR_SMPSEL9_Msk /*!< ADC4 channel 9 sampling time selection */ -#define ADC4_SMPR_SMPSEL10_Pos (18U) -#define ADC4_SMPR_SMPSEL10_Msk (0x1UL << ADC4_SMPR_SMPSEL10_Pos) /*!< 0x00040000 */ -#define ADC4_SMPR_SMPSEL10 ADC4_SMPR_SMPSEL10_Msk /*!< ADC4 channel 10 sampling time selection */ -#define ADC4_SMPR_SMPSEL11_Pos (19U) -#define ADC4_SMPR_SMPSEL11_Msk (0x1UL << ADC4_SMPR_SMPSEL11_Pos) /*!< 0x00080000 */ -#define ADC4_SMPR_SMPSEL11 ADC4_SMPR_SMPSEL11_Msk /*!< ADC4 channel 11 sampling time selection */ -#define ADC4_SMPR_SMPSEL12_Pos (20U) -#define ADC4_SMPR_SMPSEL12_Msk (0x1UL << ADC4_SMPR_SMPSEL12_Pos) /*!< 0x00100000 */ -#define ADC4_SMPR_SMPSEL12 ADC4_SMPR_SMPSEL12_Msk /*!< ADC4 channel 12 sampling time selection */ -#define ADC4_SMPR_SMPSEL13_Pos (21U) -#define ADC4_SMPR_SMPSEL13_Msk (0x1UL << ADC4_SMPR_SMPSEL13_Pos) /*!< 0x00200000 */ -#define ADC4_SMPR_SMPSEL13 ADC4_SMPR_SMPSEL13_Msk /*!< ADC4 channel 13 sampling time selection */ -#define ADC4_SMPR_SMPSEL14_Pos (22U) -#define ADC4_SMPR_SMPSEL14_Msk (0x1UL << ADC4_SMPR_SMPSEL14_Pos) /*!< 0x00400000 */ -#define ADC4_SMPR_SMPSEL14 ADC4_SMPR_SMPSEL14_Msk /*!< ADC4 channel 14 sampling time selection */ -#define ADC4_SMPR_SMPSEL15_Pos (23U) -#define ADC4_SMPR_SMPSEL15_Msk (0x1UL << ADC4_SMPR_SMPSEL15_Pos) /*!< 0x00800000 */ -#define ADC4_SMPR_SMPSEL15 ADC4_SMPR_SMPSEL15_Msk /*!< ADC4 channel 15 sampling time selection */ -#define ADC4_SMPR_SMPSEL16_Pos (24U) -#define ADC4_SMPR_SMPSEL16_Msk (0x1UL << ADC4_SMPR_SMPSEL16_Pos) /*!< 0x01000000 */ -#define ADC4_SMPR_SMPSEL16 ADC4_SMPR_SMPSEL16_Msk /*!< ADC4 channel 16 sampling time selection */ -#define ADC4_SMPR_SMPSEL17_Pos (25U) -#define ADC4_SMPR_SMPSEL17_Msk (0x1UL << ADC4_SMPR_SMPSEL17_Pos) /*!< 0x02000000 */ -#define ADC4_SMPR_SMPSEL17 ADC4_SMPR_SMPSEL17_Msk /*!< ADC4 channel 17 sampling time selection */ -#define ADC4_SMPR_SMPSEL18_Pos (26U) -#define ADC4_SMPR_SMPSEL18_Msk (0x1UL << ADC4_SMPR_SMPSEL18_Pos) /*!< 0x04000000 */ -#define ADC4_SMPR_SMPSEL18 ADC4_SMPR_SMPSEL18_Msk /*!< ADC4 channel 18 sampling time selection */ -#define ADC4_SMPR_SMPSEL19_Pos (27U) -#define ADC4_SMPR_SMPSEL19_Msk (0x1UL << ADC4_SMPR_SMPSEL19_Pos) /*!< 0x08000000 */ -#define ADC4_SMPR_SMPSEL19 ADC4_SMPR_SMPSEL19_Msk /*!< ADC4 channel 19 sampling time selection */ -#define ADC4_SMPR_SMPSEL20_Pos (26U) -#define ADC4_SMPR_SMPSEL20_Msk (0x1UL << ADC4_SMPR_SMPSEL20_Pos) /*!< 0x10000000 */ -#define ADC4_SMPR_SMPSEL20 ADC4_SMPR_SMPSEL20_Msk /*!< ADC4 channel 20 sampling time selection */ -#define ADC4_SMPR_SMPSEL21_Pos (26U) -#define ADC4_SMPR_SMPSEL21_Msk (0x1UL << ADC4_SMPR_SMPSEL21_Pos) /*!< 0x20000000 */ -#define ADC4_SMPR_SMPSEL21 ADC4_SMPR_SMPSEL21_Msk /*!< ADC4 channel 20 sampling time selection */ -#define ADC4_SMPR_SMPSEL22_Pos (30U) -#define ADC4_SMPR_SMPSEL22_Msk (0x1UL << ADC4_SMPR_SMPSEL22_Pos) /*!< 0x40000000 */ -#define ADC4_SMPR_SMPSEL22 ADC4_SMPR_SMPSEL22_Msk /*!< ADC4 channel 21 sampling time selection */ -#define ADC4_SMPR_SMPSEL23_Pos (31U) -#define ADC4_SMPR_SMPSEL23_Msk (0x1UL << ADC4_SMPR_SMPSEL23_Pos) /*!< 0x80000000 */ -#define ADC4_SMPR_SMPSEL23 ADC4_SMPR_SMPSEL23_Msk /*!< ADC4 channel 23 sampling time selection */ - -/******************** Bit definition for ADC_SMPR2 register ********************/ -#define ADC_SMPR2_SMP10_Pos (0U) -#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ -#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */ -#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ -#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ -#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */ - -#define ADC_SMPR2_SMP11_Pos (3U) -#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */ -#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */ -#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */ -#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */ -#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */ - -#define ADC_SMPR2_SMP12_Pos (6U) -#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */ -#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */ -#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */ -#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */ -#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */ - -#define ADC_SMPR2_SMP13_Pos (9U) -#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */ -#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */ -#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */ -#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */ -#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */ - -#define ADC_SMPR2_SMP14_Pos (12U) -#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */ -#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */ -#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */ -#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */ -#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */ - -#define ADC_SMPR2_SMP15_Pos (15U) -#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ -#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */ -#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ -#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ -#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ - -#define ADC_SMPR2_SMP16_Pos (18U) -#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */ -#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */ -#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */ -#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */ -#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */ - -#define ADC_SMPR2_SMP17_Pos (21U) -#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */ -#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */ -#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */ -#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */ -#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */ - -#define ADC_SMPR2_SMP18_Pos (24U) -#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */ -#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */ -#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */ -#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */ -#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */ - -#define ADC_SMPR2_SMP19_Pos (27U) -#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */ -#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */ -#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */ -#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */ -#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */ - -/******************** Bit definition for ADC_PCSEL register ********************/ -#define ADC_PCSEL_PCSEL_Pos (0U) -#define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */ -#define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */ -#define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */ -#define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */ -#define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */ -#define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */ -#define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */ -#define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */ -#define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */ -#define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */ -#define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */ -#define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */ -#define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */ -#define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */ -#define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */ -#define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */ -#define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */ -#define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */ -#define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */ -#define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */ -#define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */ - -/***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/ -#define ADC_LTR_LT_Pos (0U) -#define ADC_LTR_LT_Msk (0x01FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x01FFFFFF */ -#define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */ - -/***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/ -#define ADC_HTR_HT_Pos (0U) -#define ADC_HTR_HT_Msk (0x01FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x01FFFFFF */ -#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */ - -#define ADC_HTR_AWDFILT_Pos (29U) -#define ADC_HTR_AWDFILT_Msk (0x7UL << ADC_HTR_AWDFILT_Pos) /*!< 0xE0000000 */ -#define ADC_HTR_AWDFILT ADC_HTR_AWDFILT_Msk /*!< Analog watchdog filtering parameter, HTR1 only */ -#define ADC_HTR_AWDFILT_0 (0x1UL << ADC_HTR_AWDFILT_Pos) /*!< 0x20000000 */ -#define ADC_HTR_AWDFILT_1 (0x2UL << ADC_HTR_AWDFILT_Pos) /*!< 0x40000000 */ -#define ADC_HTR_AWDFILT_2 (0x4UL << ADC_HTR_AWDFILT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_SQR1 register ********************/ -#define ADC_SQR1_L_Pos (0U) -#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */ -#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence length */ -#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */ -#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */ -#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */ -#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */ - -#define ADC_SQR1_SQ1_Pos (6U) -#define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */ -#define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */ -#define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */ -#define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */ -#define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */ -#define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */ -#define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */ - -#define ADC_SQR1_SQ2_Pos (12U) -#define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */ -#define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */ -#define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */ -#define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */ -#define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */ -#define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */ -#define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */ - -#define ADC_SQR1_SQ3_Pos (18U) -#define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */ -#define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */ -#define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */ -#define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */ -#define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */ -#define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */ -#define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */ - -#define ADC_SQR1_SQ4_Pos (24U) -#define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */ -#define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */ -#define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */ -#define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */ -#define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */ -#define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */ -#define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR2 register ********************/ -#define ADC_SQR2_SQ5_Pos (0U) -#define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */ -#define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */ -#define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */ -#define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */ -#define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */ -#define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */ -#define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */ - -#define ADC_SQR2_SQ6_Pos (6U) -#define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */ -#define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */ -#define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */ -#define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */ -#define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */ -#define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */ -#define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */ - -#define ADC_SQR2_SQ7_Pos (12U) -#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */ -#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */ -#define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */ -#define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */ -#define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */ -#define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */ -#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */ - -#define ADC_SQR2_SQ8_Pos (18U) -#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */ -#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */ -#define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */ -#define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */ -#define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */ -#define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */ -#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */ - -#define ADC_SQR2_SQ9_Pos (24U) -#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */ -#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */ -#define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */ -#define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */ -#define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */ -#define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */ -#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR3 register ********************/ -#define ADC_SQR3_SQ10_Pos (0U) -#define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */ -#define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */ -#define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */ -#define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */ -#define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */ -#define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */ -#define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */ - -#define ADC_SQR3_SQ11_Pos (6U) -#define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */ -#define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */ -#define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */ -#define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */ -#define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */ -#define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */ -#define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */ - -#define ADC_SQR3_SQ12_Pos (12U) -#define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */ -#define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */ -#define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */ -#define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */ -#define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */ -#define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */ -#define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */ - -#define ADC_SQR3_SQ13_Pos (18U) -#define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */ -#define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */ -#define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */ -#define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */ -#define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */ -#define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */ -#define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */ - -#define ADC_SQR3_SQ14_Pos (24U) -#define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */ -#define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */ -#define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */ -#define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */ -#define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */ -#define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */ -#define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */ - -/******************** Bit definition for ADC_SQR4 register ********************/ -#define ADC_SQR4_SQ15_Pos (0U) -#define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */ -#define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */ -#define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */ -#define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */ -#define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */ -#define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */ -#define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */ - -#define ADC_SQR4_SQ16_Pos (6U) -#define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */ -#define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */ -#define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */ -#define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */ -#define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */ -#define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */ -#define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */ -/******************** Bit definition for ADC_DR register ********************/ -#define ADC_DR_RDATA_Pos (0U) -#define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */ - -/******************** Bit definition for ADC_PW register ********************/ -#define ADC4_PWRR_AUTOFF_Pos (0U) -#define ADC4_PWRR_AUTOFF_Msk (0x1UL << ADC4_PWRR_AUTOFF_Pos) /*!< 0x00000001 */ -#define ADC4_PWRR_AUTOFF ADC4_PWRR_AUTOFF_Msk /*!< ADC Auto-Off mode */ -#define ADC4_PWRR_DPD_Pos (1U) -#define ADC4_PWRR_DPD_Msk (0x1UL << ADC4_PWRR_DPD_Pos) /*!< 0x00000002 */ -#define ADC4_PWRR_DPD ADC4_PWRR_DPD_Msk /*!< ADC Deep Power mode */ -#define ADC4_PWRR_VREFPROT_Pos (2U) -#define ADC4_PWRR_VREFPROT_Msk (0x1UL << ADC4_PWRR_VREFPROT_Pos) /*!< 0x00000004 */ -#define ADC4_PWRR_VREFPROT ADC4_PWRR_VREFPROT_Msk /*!< ADC Vref protection */ -#define ADC4_PWRR_VREFSECSMP_Pos (3U) -#define ADC4_PWRR_VREFSECSMP_Msk (0x1UL << ADC4_PWRR_VREFSECSMP_Pos) /*!< 0x00000008 */ -#define ADC4_PWRR_VREFSECSMP ADC4_PWRR_VREFSECSMP_Msk /*!< ADC Vref Second Sample */ - -/* Legacy definitions */ -#define ADC4_PW_AUTOFF_Pos ADC4_PWRR_AUTOFF_Pos -#define ADC4_PW_AUTOFF_Msk ADC4_PWRR_AUTOFF_Msk -#define ADC4_PW_AUTOFF ADC4_PWRR_AUTOFF -#define ADC4_PW_DPD_Pos ADC4_PWRR_DPD_Pos -#define ADC4_PW_DPD_Msk ADC4_PWRR_DPD_Msk -#define ADC4_PW_DPD ADC4_PWRR_DPD -#define ADC4_PW_VREFPROT_Pos ADC4_PWRR_VREFPROT_Pos -#define ADC4_PW_VREFPROT_Msk ADC4_PWRR_VREFPROT_Msk -#define ADC4_PW_VREFPROT ADC4_PWRR_VREFPROT -#define ADC4_PW_VREFSECSMP_Pos ADC4_PWRR_VREFSECSMP_Pos -#define ADC4_PW_VREFSECSMP_Msk ADC4_PWRR_VREFSECSMP_Msk -#define ADC4_PW_VREFSECSMP ADC4_PWRR_VREFSECSMP - -/******************** Bit definition for ADC_JSQR register ********************/ -#define ADC_JSQR_JL_Pos (0U) -#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */ -#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */ -#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */ -#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */ - -#define ADC_JSQR_JEXTSEL_Pos (2U) -#define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */ -#define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */ -#define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */ -#define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */ -#define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */ -#define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */ -#define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */ - -#define ADC_JSQR_JEXTEN_Pos (7U) -#define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */ -#define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */ -#define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */ -#define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */ - -#define ADC_JSQR_JSQ1_Pos (9U) -#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */ -#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */ -#define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */ -#define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */ -#define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */ -#define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */ -#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */ - -#define ADC_JSQR_JSQ2_Pos (15U) -#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */ -#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */ -#define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */ -#define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */ -#define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */ -#define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */ -#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */ - -#define ADC_JSQR_JSQ3_Pos (21U) -#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */ -#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */ -#define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */ -#define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */ -#define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */ -#define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */ -#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */ - -#define ADC_JSQR_JSQ4_Pos (27U) -#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */ -#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */ -#define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */ -#define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */ -#define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */ -#define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */ -#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OFR1 register ********************/ -#define ADC_OFR1_OFFSET1_Pos (0U) -#define ADC_OFR1_OFFSET1_Msk (0x00FFFFFFUL << ADC_OFR1_OFFSET1_Pos)/*!< 0x00FFFFFF */ -#define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */ -#define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */ -#define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */ -#define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */ -#define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */ -#define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */ -#define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */ -#define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */ -#define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */ -#define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */ -#define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */ -#define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */ -#define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */ -#define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */ -#define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */ -#define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */ -#define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */ -#define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */ -#define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */ -#define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */ -#define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */ -#define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */ -#define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */ -#define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */ -#define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */ - -#define ADC_OFR1_OFFSETPOS_Pos (24U) -#define ADC_OFR1_OFFSETPOS_Msk (0x1UL << ADC_OFR1_OFFSETPOS_Pos) /*!< 0x01000000 */ -#define ADC_OFR1_OFFSETPOS ADC_OFR1_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR1_USAT_Pos (25U) -#define ADC_OFR1_USAT_Msk (0x1UL << ADC_OFR1_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFR1_USAT ADC_OFR1_USAT_Msk /*!< ADC offset number 1 saturation enable */ - -#define ADC_OFR1_SSAT_Pos (26U) -#define ADC_OFR1_SSAT_Msk (0x1UL << ADC_OFR1_SSAT_Pos) /*!< 0x80000000 */ -#define ADC_OFR1_SSAT ADC_OFR1_SSAT_Msk /*!< ADC Signed saturation Enable */ - -#define ADC_OFR1_OFFSET1_CH_Pos (27U) -#define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */ -#define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_OFR2 register ********************/ -#define ADC_OFR2_OFFSET2_Pos (0U) -#define ADC_OFR2_OFFSET2_Msk (0x00FFFFFFUL << ADC_OFR2_OFFSET2_Pos)/*!< 0x00FFFFFF */ -#define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */ -#define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */ -#define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */ -#define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */ -#define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */ -#define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */ -#define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */ -#define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */ -#define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */ -#define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */ -#define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */ -#define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */ -#define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */ -#define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */ -#define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */ -#define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */ -#define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */ -#define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */ -#define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */ -#define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */ -#define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */ -#define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */ -#define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */ -#define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */ -#define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */ - -#define ADC_OFR2_OFFSETPOS_Pos (24U) -#define ADC_OFR2_OFFSETPOS_Msk (0x1UL << ADC_OFR2_OFFSETPOS_Pos) /*!< 0x01000000 */ -#define ADC_OFR2_OFFSETPOS ADC_OFR2_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR2_USAT_Pos (25U) -#define ADC_OFR2_USAT_Msk (0x1UL << ADC_OFR2_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFR2_USAT ADC_OFR2_USAT_Msk /*!< ADC offset number 1 saturation enable */ - -#define ADC_OFR2_SSAT_Pos (26U) -#define ADC_OFR2_SSAT_Msk (0x1UL << ADC_OFR2_SSAT_Pos) /*!< 0x80000000 */ -#define ADC_OFR2_SSAT ADC_OFR2_SSAT_Msk /*!< ADC Signed saturation Enable */ - -#define ADC_OFR2_OFFSET2_CH_Pos (27U) -#define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */ -#define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_OFR3 register ********************/ -#define ADC_OFR3_OFFSET3_Pos (0U) -#define ADC_OFR3_OFFSET3_Msk (0x00FFFFFFUL << ADC_OFR3_OFFSET3_Pos)/*!< 0x00FFFFFF */ -#define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */ -#define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */ -#define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */ -#define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */ -#define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */ -#define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */ -#define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */ -#define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */ -#define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */ -#define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */ -#define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */ -#define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */ -#define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */ -#define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */ -#define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */ -#define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */ -#define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */ -#define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */ -#define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */ -#define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */ -#define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */ -#define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */ -#define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */ -#define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */ -#define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */ - -#define ADC_OFR3_OFFSETPOS_Pos (24U) -#define ADC_OFR3_OFFSETPOS_Msk (0x1UL << ADC_OFR3_OFFSETPOS_Pos) /*!< 0x01000000 */ -#define ADC_OFR3_OFFSETPOS ADC_OFR3_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR3_USAT_Pos (25U) -#define ADC_OFR3_USAT_Msk (0x1UL << ADC_OFR3_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFR3_USAT ADC_OFR3_USAT_Msk /*!< ADC offset number 1 saturation enable */ - -#define ADC_OFR3_SSAT_Pos (26U) -#define ADC_OFR3_SSAT_Msk (0x1UL << ADC_OFR3_SSAT_Pos) /*!< 0x80000000 */ -#define ADC_OFR3_SSAT ADC_OFR3_SSAT_Msk /*!< ADC Signed saturation Enable */ - -#define ADC_OFR3_OFFSET3_CH_Pos (27U) -#define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */ -#define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_OFR4 register ********************/ -#define ADC_OFR4_OFFSET4_Pos (0U) -#define ADC_OFR4_OFFSET4_Msk (0x00FFFFFFUL << ADC_OFR4_OFFSET4_Pos)/*!< 0x00FFFFFF */ -#define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */ -#define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */ -#define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */ -#define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */ -#define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */ -#define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */ -#define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */ -#define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */ -#define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */ -#define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */ -#define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */ -#define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */ -#define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */ -#define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */ -#define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */ -#define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */ -#define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */ -#define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */ -#define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */ -#define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */ -#define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */ -#define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */ -#define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */ -#define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */ -#define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */ - -#define ADC_OFR4_OFFSETPOS_Pos (24U) -#define ADC_OFR4_OFFSETPOS_Msk (0x1UL << ADC_OFR4_OFFSETPOS_Pos) /*!< 0x01000000 */ -#define ADC_OFR4_OFFSETPOS ADC_OFR4_OFFSETPOS_Msk /*!< ADC offset number 1 positive */ -#define ADC_OFR4_USAT_Pos (25U) -#define ADC_OFR4_USAT_Msk (0x1UL << ADC_OFR4_USAT_Pos) /*!< 0x02000000 */ -#define ADC_OFR4_USAT ADC_OFR4_USAT_Msk /*!< ADC offset number 1 saturation enable */ - -#define ADC_OFR4_SSAT_Pos (26U) -#define ADC_OFR4_SSAT_Msk (0x1UL << ADC_OFR4_SSAT_Pos) /*!< 0x80000000 */ -#define ADC_OFR4_SSAT ADC_OFR4_SSAT_Msk /*!< ADC Signed saturation Enable */ - -#define ADC_OFR4_OFFSET4_CH_Pos (27U) -#define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */ -#define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */ -#define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */ -#define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */ -#define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */ -#define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */ -#define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */ - -/******************** Bit definition for ADC_GCOMP register ********************/ -#define ADC_GCOMP_GCOMPCOEFF_Pos (0U) -#define ADC_GCOMP_GCOMPCOEFF_Msk (0x3FFFUL << ADC_GCOMP_GCOMPCOEFF_Pos)/*!< 0x00003FFF */ -#define ADC_GCOMP_GCOMPCOEFF ADC_GCOMP_GCOMPCOEFF_Msk /*!< ADC Injected DATA */ -#define ADC_GCOMP_GCOMP_Pos (31U) -#define ADC_GCOMP_GCOMP_Msk (0x1UL << ADC_GCOMP_GCOMP_Pos) /*!< 0x00003FFF */ -#define ADC_GCOMP_GCOMP ADC_GCOMP_GCOMP_Msk /*!< ADC Injected DATA */ - -/******************** Bit definition for ADC_JDR1 register ********************/ -#define ADC_JDR1_JDATA_Pos (0U) -#define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */ -#define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR2 register ********************/ -#define ADC_JDR2_JDATA_Pos (0U) -#define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */ -#define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR3 register ********************/ -#define ADC_JDR3_JDATA_Pos (0U) -#define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */ -#define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_JDR4 register ********************/ -#define ADC_JDR4_JDATA_Pos (0U) -#define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */ -#define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */ -#define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */ -#define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */ -#define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */ -#define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */ -#define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */ -#define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */ -#define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */ -#define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */ -#define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */ -#define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */ -#define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */ -#define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */ -#define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */ -#define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */ -#define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */ -#define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */ -#define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */ -#define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */ -#define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */ -#define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */ -#define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */ -#define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */ -#define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */ -#define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */ -#define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */ -#define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */ -#define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */ -#define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */ -#define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */ -#define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */ -#define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */ -#define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_AWD2CR register ********************/ -#define ADC_AWD2CR_AWD2CH_Pos (0U) -#define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00FFFFFF */ -#define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */ -#define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */ -#define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */ -#define ADC_AWD2CR_AWD2CH_20 (0x100000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00100000 */ -#define ADC_AWD2CR_AWD2CH_21 (0x200000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00200000 */ -#define ADC_AWD2CR_AWD2CH_22 (0x400000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00400000 */ -#define ADC_AWD2CR_AWD2CH_23 (0x800000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_AWD1TR register *******************/ -#define ADC_AWD1TR_LT1_Pos (0U) -#define ADC_AWD1TR_LT1_Msk (0xFFFUL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000FFF */ -#define ADC_AWD1TR_LT1 ADC_AWD1TR_LT1_Msk /*!< ADC analog watchdog 1 threshold low */ -#define ADC_AWD1TR_LT1_0 (0x001UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000001 */ -#define ADC_AWD1TR_LT1_1 (0x002UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000002 */ -#define ADC_AWD1TR_LT1_2 (0x004UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000004 */ -#define ADC_AWD1TR_LT1_3 (0x008UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000008 */ -#define ADC_AWD1TR_LT1_4 (0x010UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000010 */ -#define ADC_AWD1TR_LT1_5 (0x020UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000020 */ -#define ADC_AWD1TR_LT1_6 (0x040UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000040 */ -#define ADC_AWD1TR_LT1_7 (0x080UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000080 */ -#define ADC_AWD1TR_LT1_8 (0x100UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000100 */ -#define ADC_AWD1TR_LT1_9 (0x200UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000200 */ -#define ADC_AWD1TR_LT1_10 (0x400UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000400 */ -#define ADC_AWD1TR_LT1_11 (0x800UL << ADC_AWD1TR_LT1_Pos) /*!< 0x00000800 */ - -#define ADC_AWD1TR_HT1_Pos (16U) -#define ADC_AWD1TR_HT1_Msk (0xFFFUL << ADC_AWD1TR_HT1_Pos) /*!< 0x0FFF0000 */ -#define ADC_AWD1TR_HT1 ADC_AWD1TR_HT1_Msk /*!< ADC Analog watchdog 1 threshold high */ -#define ADC_AWD1TR_HT1_0 (0x001UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00010000 */ -#define ADC_AWD1TR_HT1_1 (0x002UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00020000 */ -#define ADC_AWD1TR_HT1_2 (0x004UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00040000 */ -#define ADC_AWD1TR_HT1_3 (0x008UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00080000 */ -#define ADC_AWD1TR_HT1_4 (0x010UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00100000 */ -#define ADC_AWD1TR_HT1_5 (0x020UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00200000 */ -#define ADC_AWD1TR_HT1_6 (0x040UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00400000 */ -#define ADC_AWD1TR_HT1_7 (0x080UL << ADC_AWD1TR_HT1_Pos) /*!< 0x00800000 */ -#define ADC_AWD1TR_HT1_8 (0x100UL << ADC_AWD1TR_HT1_Pos) /*!< 0x01000000 */ -#define ADC_AWD1TR_HT1_9 (0x200UL << ADC_AWD1TR_HT1_Pos) /*!< 0x02000000 */ -#define ADC_AWD1TR_HT1_10 (0x400UL << ADC_AWD1TR_HT1_Pos) /*!< 0x04000000 */ -#define ADC_AWD1TR_HT1_11 (0x800UL << ADC_AWD1TR_HT1_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_AWDTR2 register *******************/ -#define ADC_AWD2TR_LT2_Pos (0U) -#define ADC_AWD2TR_LT2_Msk (0xFFFUL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000FFF */ -#define ADC_AWD2TR_LT2 ADC_AWD2TR_LT2_Msk /*!< ADC analog watchdog 2 threshold low */ -#define ADC_AWD2TR_LT2_0 (0x001UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000001 */ -#define ADC_AWD2TR_LT2_1 (0x002UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000002 */ -#define ADC_AWD2TR_LT2_2 (0x004UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000004 */ -#define ADC_AWD2TR_LT2_3 (0x008UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000008 */ -#define ADC_AWD2TR_LT2_4 (0x010UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000010 */ -#define ADC_AWD2TR_LT2_5 (0x020UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000020 */ -#define ADC_AWD2TR_LT2_6 (0x040UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000040 */ -#define ADC_AWD2TR_LT2_7 (0x080UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000080 */ -#define ADC_AWD2TR_LT2_8 (0x100UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000100 */ -#define ADC_AWD2TR_LT2_9 (0x200UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000200 */ -#define ADC_AWD2TR_LT2_10 (0x400UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000400 */ -#define ADC_AWD2TR_LT2_11 (0x800UL << ADC_AWD2TR_LT2_Pos) /*!< 0x00000800 */ - -#define ADC_AWD2TR_HT2_Pos (16U) -#define ADC_AWD2TR_HT2_Msk (0xFFFUL << ADC_AWD2TR_HT2_Pos) /*!< 0x0FFF0000 */ -#define ADC_AWD2TR_HT2 ADC_AWD2TR_HT2_Msk /*!< ADC analog watchdog 2 threshold high */ -#define ADC_AWD2TR_HT2_0 (0x001UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00010000 */ -#define ADC_AWD2TR_HT2_1 (0x002UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00020000 */ -#define ADC_AWD2TR_HT2_2 (0x004UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00040000 */ -#define ADC_AWD2TR_HT2_3 (0x008UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00080000 */ -#define ADC_AWD2TR_HT2_4 (0x010UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00100000 */ -#define ADC_AWD2TR_HT2_5 (0x020UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00200000 */ -#define ADC_AWD2TR_HT2_6 (0x040UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00400000 */ -#define ADC_AWD2TR_HT2_7 (0x080UL << ADC_AWD2TR_HT2_Pos) /*!< 0x00800000 */ -#define ADC_AWD2TR_HT2_8 (0x100UL << ADC_AWD2TR_HT2_Pos) /*!< 0x01000000 */ -#define ADC_AWD2TR_HT2_9 (0x200UL << ADC_AWD2TR_HT2_Pos) /*!< 0x02000000 */ -#define ADC_AWD2TR_HT2_10 (0x400UL << ADC_AWD2TR_HT2_Pos) /*!< 0x04000000 */ -#define ADC_AWD2TR_HT2_11 (0x800UL << ADC_AWD2TR_HT2_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_CHSELR register ****************/ -#define ADC_CHSELR_CHSEL_Pos (0U) -#define ADC_CHSELR_CHSEL_Msk (0xFFFFFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x0007FFFF */ -#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ - -#define ADC_CHSELR_CHSEL0_Pos (0U) -#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ -#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL1_Pos (1U) -#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ -#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL2_Pos (2U) -#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ -#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL3_Pos (3U) -#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ -#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL4_Pos (4U) -#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ -#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL5_Pos (5U) -#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ -#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL6_Pos (6U) -#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ -#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL7_Pos (7U) -#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ -#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL8_Pos (8U) -#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ -#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL9_Pos (9U) -#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ -#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL10_Pos (10U) -#define ADC_CHSELR_CHSEL10_Msk (0x1UL << ADC_CHSELR_CHSEL10_Pos) /*!< 0x00000400 */ -#define ADC_CHSELR_CHSEL10 ADC_CHSELR_CHSEL10_Msk /*!< ADC group regular sequencer channel 10, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL11_Pos (11U) -#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ -#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL12_Pos (12U) -#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ -#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL13_Pos (13U) -#define ADC_CHSELR_CHSEL13_Msk (0x1UL << ADC_CHSELR_CHSEL13_Pos) /*!< 0x00002000 */ -#define ADC_CHSELR_CHSEL13 ADC_CHSELR_CHSEL13_Msk /*!< ADC group regular sequencer channel 13, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL14_Pos (14U) -#define ADC_CHSELR_CHSEL14_Msk (0x1UL << ADC_CHSELR_CHSEL14_Pos) /*!< 0x00004000 */ -#define ADC_CHSELR_CHSEL14 ADC_CHSELR_CHSEL14_Msk /*!< ADC group regular sequencer channel 14, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL15_Pos (15U) -#define ADC_CHSELR_CHSEL15_Msk (0x1UL << ADC_CHSELR_CHSEL15_Pos) /*!< 0x00008000 */ -#define ADC_CHSELR_CHSEL15 ADC_CHSELR_CHSEL15_Msk /*!< ADC group regular sequencer channel 15, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL16_Pos (16U) -#define ADC_CHSELR_CHSEL16_Msk (0x1UL << ADC_CHSELR_CHSEL16_Pos) /*!< 0x00010000 */ -#define ADC_CHSELR_CHSEL16 ADC_CHSELR_CHSEL16_Msk /*!< ADC group regular sequencer channel 16, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL17_Pos (17U) -#define ADC_CHSELR_CHSEL17_Msk (0x1UL << ADC_CHSELR_CHSEL17_Pos) /*!< 0x00020000 */ -#define ADC_CHSELR_CHSEL17 ADC_CHSELR_CHSEL17_Msk /*!< ADC group regular sequencer channel 17, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL18_Pos (18U) -#define ADC_CHSELR_CHSEL18_Msk (0x1UL << ADC_CHSELR_CHSEL18_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_CHSEL18 ADC_CHSELR_CHSEL18_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL19_Pos (19U) -#define ADC_CHSELR_CHSEL19_Msk (0x1UL << ADC_CHSELR_CHSEL19_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_CHSEL19 ADC_CHSELR_CHSEL19_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL20_Pos (20U) -#define ADC_CHSELR_CHSEL20_Msk (0x1UL << ADC_CHSELR_CHSEL20_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_CHSEL20 ADC_CHSELR_CHSEL20_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL21_Pos (21U) -#define ADC_CHSELR_CHSEL21_Msk (0x1UL << ADC_CHSELR_CHSEL21_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_CHSEL21 ADC_CHSELR_CHSEL21_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL22_Pos (22U) -#define ADC_CHSELR_CHSEL22_Msk (0x1UL << ADC_CHSELR_CHSEL22_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_CHSEL22 ADC_CHSELR_CHSEL22_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ -#define ADC_CHSELR_CHSEL23_Pos (23U) -#define ADC_CHSELR_CHSEL23_Msk (0x1UL << ADC_CHSELR_CHSEL23_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_CHSEL23 ADC_CHSELR_CHSEL23_Msk /*!< ADC group regular sequencer channel 18, available when ADC_CFGR1_CHSELRMOD is reset */ - -#define ADC_CHSELR_SQ_ALL_Pos (0U) -#define ADC_CHSELR_SQ_ALL_Msk (0xFFFFFFFFUL << ADC_CHSELR_SQ_ALL_Pos) /*!< 0xFFFFFFFF */ -#define ADC_CHSELR_SQ_ALL ADC_CHSELR_SQ_ALL_Msk /*!< ADC group regular sequencer all ranks, available when ADC_CFGR1_CHSELRMOD is set */ - -#define ADC_CHSELR_SQ1_Pos (0U) -#define ADC_CHSELR_SQ1_Msk (0xFUL << ADC_CHSELR_SQ1_Pos) /*!< 0x0000000F */ -#define ADC_CHSELR_SQ1 ADC_CHSELR_SQ1_Msk /*!< ADC group regular sequencer rank 1, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ1_0 (0x1UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000001 */ -#define ADC_CHSELR_SQ1_1 (0x2UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000002 */ -#define ADC_CHSELR_SQ1_2 (0x4UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000004 */ -#define ADC_CHSELR_SQ1_3 (0x8UL << ADC_CHSELR_SQ1_Pos) /*!< 0x00000008 */ - -#define ADC_CHSELR_SQ2_Pos (4U) -#define ADC_CHSELR_SQ2_Msk (0xFUL << ADC_CHSELR_SQ2_Pos) /*!< 0x000000F0 */ -#define ADC_CHSELR_SQ2 ADC_CHSELR_SQ2_Msk /*!< ADC group regular sequencer rank 2, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ2_0 (0x1UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000010 */ -#define ADC_CHSELR_SQ2_1 (0x2UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000020 */ -#define ADC_CHSELR_SQ2_2 (0x4UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000040 */ -#define ADC_CHSELR_SQ2_3 (0x8UL << ADC_CHSELR_SQ2_Pos) /*!< 0x00000080 */ - -#define ADC_CHSELR_SQ3_Pos (8U) -#define ADC_CHSELR_SQ3_Msk (0xFUL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000F00 */ -#define ADC_CHSELR_SQ3 ADC_CHSELR_SQ3_Msk /*!< ADC group regular sequencer rank 3, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ3_0 (0x1UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000100 */ -#define ADC_CHSELR_SQ3_1 (0x2UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000200 */ -#define ADC_CHSELR_SQ3_2 (0x4UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000400 */ -#define ADC_CHSELR_SQ3_3 (0x8UL << ADC_CHSELR_SQ3_Pos) /*!< 0x00000800 */ - -#define ADC_CHSELR_SQ4_Pos (12U) -#define ADC_CHSELR_SQ4_Msk (0xFUL << ADC_CHSELR_SQ4_Pos) /*!< 0x0000F000 */ -#define ADC_CHSELR_SQ4 ADC_CHSELR_SQ4_Msk /*!< ADC group regular sequencer rank 4, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ4_0 (0x1UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00001000 */ -#define ADC_CHSELR_SQ4_1 (0x2UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00002000 */ -#define ADC_CHSELR_SQ4_2 (0x4UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00004000 */ -#define ADC_CHSELR_SQ4_3 (0x8UL << ADC_CHSELR_SQ4_Pos) /*!< 0x00008000 */ - -#define ADC_CHSELR_SQ5_Pos (16U) -#define ADC_CHSELR_SQ5_Msk (0xFUL << ADC_CHSELR_SQ5_Pos) /*!< 0x000F0000 */ -#define ADC_CHSELR_SQ5 ADC_CHSELR_SQ5_Msk /*!< ADC group regular sequencer rank 5, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ5_0 (0x1UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00010000 */ -#define ADC_CHSELR_SQ5_1 (0x2UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00020000 */ -#define ADC_CHSELR_SQ5_2 (0x4UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00040000 */ -#define ADC_CHSELR_SQ5_3 (0x8UL << ADC_CHSELR_SQ5_Pos) /*!< 0x00080000 */ - -#define ADC_CHSELR_SQ6_Pos (20U) -#define ADC_CHSELR_SQ6_Msk (0xFUL << ADC_CHSELR_SQ6_Pos) /*!< 0x00F00000 */ -#define ADC_CHSELR_SQ6 ADC_CHSELR_SQ6_Msk /*!< ADC group regular sequencer rank 6, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ6_0 (0x1UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00100000 */ -#define ADC_CHSELR_SQ6_1 (0x2UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00200000 */ -#define ADC_CHSELR_SQ6_2 (0x4UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00400000 */ -#define ADC_CHSELR_SQ6_3 (0x8UL << ADC_CHSELR_SQ6_Pos) /*!< 0x00800000 */ - -#define ADC_CHSELR_SQ7_Pos (24U) -#define ADC_CHSELR_SQ7_Msk (0xFUL << ADC_CHSELR_SQ7_Pos) /*!< 0x0F000000 */ -#define ADC_CHSELR_SQ7 ADC_CHSELR_SQ7_Msk /*!< ADC group regular sequencer rank 7, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ7_0 (0x1UL << ADC_CHSELR_SQ7_Pos) /*!< 0x01000000 */ -#define ADC_CHSELR_SQ7_1 (0x2UL << ADC_CHSELR_SQ7_Pos) /*!< 0x02000000 */ -#define ADC_CHSELR_SQ7_2 (0x4UL << ADC_CHSELR_SQ7_Pos) /*!< 0x04000000 */ -#define ADC_CHSELR_SQ7_3 (0x8UL << ADC_CHSELR_SQ7_Pos) /*!< 0x08000000 */ - -#define ADC_CHSELR_SQ8_Pos (28U) -#define ADC_CHSELR_SQ8_Msk (0xFUL << ADC_CHSELR_SQ8_Pos) /*!< 0xF0000000 */ -#define ADC_CHSELR_SQ8 ADC_CHSELR_SQ8_Msk /*!< ADC group regular sequencer rank 8, available when ADC_CFGR1_CHSELRMOD is set */ -#define ADC_CHSELR_SQ8_0 (0x1UL << ADC_CHSELR_SQ8_Pos) /*!< 0x10000000 */ -#define ADC_CHSELR_SQ8_1 (0x2UL << ADC_CHSELR_SQ8_Pos) /*!< 0x20000000 */ -#define ADC_CHSELR_SQ8_2 (0x4UL << ADC_CHSELR_SQ8_Pos) /*!< 0x40000000 */ -#define ADC_CHSELR_SQ8_3 (0x8UL << ADC_CHSELR_SQ8_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_AWD3TR register *******************/ -#define ADC_AWD3TR_LT3_Pos (0U) -#define ADC_AWD3TR_LT3_Msk (0xFFFUL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000FFF */ -#define ADC_AWD3TR_LT3 ADC_AWD3TR_LT3_Msk /*!< ADC analog watchdog 3 threshold low */ -#define ADC_AWD3TR_LT3_0 (0x001UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000001 */ -#define ADC_AWD3TR_LT3_1 (0x002UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000002 */ -#define ADC_AWD3TR_LT3_2 (0x004UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000004 */ -#define ADC_AWD3TR_LT3_3 (0x008UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000008 */ -#define ADC_AWD3TR_LT3_4 (0x010UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000010 */ -#define ADC_AWD3TR_LT3_5 (0x020UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000020 */ -#define ADC_AWD3TR_LT3_6 (0x040UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000040 */ -#define ADC_AWD3TR_LT3_7 (0x080UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000080 */ -#define ADC_AWD3TR_LT3_8 (0x100UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000100 */ -#define ADC_AWD3TR_LT3_9 (0x200UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000200 */ -#define ADC_AWD3TR_LT3_10 (0x400UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000400 */ -#define ADC_AWD3TR_LT3_11 (0x800UL << ADC_AWD3TR_LT3_Pos) /*!< 0x00000800 */ - -#define ADC_AWD3TR_HT3_Pos (16U) -#define ADC_AWD3TR_HT3_Msk (0xFFFUL << ADC_AWD3TR_HT3_Pos) /*!< 0x0FFF0000 */ -#define ADC_AWD3TR_HT3 ADC_AWD3TR_HT3_Msk /*!< ADC analog watchdog 3 threshold high */ -#define ADC_AWD3TR_HT3_0 (0x001UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00010000 */ -#define ADC_AWD3TR_HT3_1 (0x002UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00020000 */ -#define ADC_AWD3TR_HT3_2 (0x004UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00040000 */ -#define ADC_AWD3TR_HT3_3 (0x008UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00080000 */ -#define ADC_AWD3TR_HT3_4 (0x010UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00100000 */ -#define ADC_AWD3TR_HT3_5 (0x020UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00200000 */ -#define ADC_AWD3TR_HT3_6 (0x040UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00400000 */ -#define ADC_AWD3TR_HT3_7 (0x080UL << ADC_AWD3TR_HT3_Pos) /*!< 0x00800000 */ -#define ADC_AWD3TR_HT3_8 (0x100UL << ADC_AWD3TR_HT3_Pos) /*!< 0x01000000 */ -#define ADC_AWD3TR_HT3_9 (0x200UL << ADC_AWD3TR_HT3_Pos) /*!< 0x02000000 */ -#define ADC_AWD3TR_HT3_10 (0x400UL << ADC_AWD3TR_HT3_Pos) /*!< 0x04000000 */ -#define ADC_AWD3TR_HT3_11 (0x800UL << ADC_AWD3TR_HT3_Pos) /*!< 0x08000000 */ - -/******************** Bit definition for ADC_AWD3CR register ********************/ -#define ADC_AWD3CR_AWD3CH_Pos (0U) -#define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00FFFFFF */ -#define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */ -#define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */ -#define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */ -#define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */ -#define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */ -#define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */ -#define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */ -#define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */ -#define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */ -#define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */ -#define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */ -#define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */ -#define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */ -#define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */ -#define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */ -#define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */ -#define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */ -#define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */ -#define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */ -#define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */ -#define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */ -#define ADC_AWD3CR_AWD2CH_20 (0x100000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00100000 */ -#define ADC_AWD3CR_AWD2CH_21 (0x200000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00200000 */ -#define ADC_AWD3CR_AWD2CH_22 (0x400000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00400000 */ -#define ADC_AWD3CR_AWD2CH_23 (0x800000UL << ADC_AWD3CR_AWD2CH_Pos) /*!< 0x00800000 */ - -/******************** Bit definition for ADC_DIFSEL register ********************/ -#define ADC_DIFSEL_DIFSEL_Pos (0U) -#define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */ -#define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */ -#define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */ -#define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */ -#define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */ -#define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */ -#define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */ -#define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */ -#define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */ -#define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */ -#define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */ -#define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */ -#define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */ -#define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */ -#define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */ -#define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */ -#define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */ -#define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */ -#define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */ -#define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */ -#define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */ -#define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */ - -/******************** Bit definition for ADC_CALFACT register ********************/ -#define ADC_CALFACT_I_APB_ADDR_Pos (0U) -#define ADC_CALFACT_I_APB_ADDR_Msk (0xFFUL << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x000000FF */ -#define ADC_CALFACT_I_APB_ADDR ADC_CALFACT_I_APB_ADDR_Msk /*!< ADC calibration factors in single-ended mode */ -#define ADC_CALFACT_I_APB_ADDR_0 (0x001U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT_I_APB_ADDR_1 (0x002U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT_I_APB_ADDR_2 (0x004U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT_I_APB_ADDR_3 (0x008U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT_I_APB_ADDR_4 (0x010U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT_I_APB_ADDR_5 (0x020U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT_I_APB_ADDR_6 (0x040U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT_I_APB_ADDR_7 (0x080U << ADC_CALFACT_I_APB_ADDR_Pos) /*!< 0x00000080 */ - -#define ADC_CALFACT_I_APB_DATA_Pos (08U) -#define ADC_CALFACT_I_APB_DATA_Msk (0xFFUL << ADC_CALFACT_I_APB_DATA_Pos) /*!< 0x0000FF00 */ -#define ADC_CALFACT_I_APB_DATA ADC_CALFACT_I_APB_DATA_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_APB_DATA_0 (0x001U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000100 */ -#define ADC_CALFACT_APB_DATA_1 (0x002U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000200 */ -#define ADC_CALFACT_APB_DATA_2 (0x004U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000400 */ -#define ADC_CALFACT_APB_DATA_3 (0x008U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00000800 */ -#define ADC_CALFACT_APB_DATA_4 (0x010U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00001000 */ -#define ADC_CALFACT_APB_DATA_5 (0x020U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00002000 */ -#define ADC_CALFACT_APB_DATA_6 (0x040U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00004000 */ -#define ADC_CALFACT_APB_DATA_7 (0x080U << ADC_CALFACT_APB_DATA_Pos) /*!< 0x00008000 */ - -#define ADC_CALFACT_VALIDITY_Pos (16U) -#define ADC_CALFACT_VALIDITY_Msk (0x1UL << ADC_CALFACT_VALIDITY_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT_VALIDITY ADC_CALFACT_VALIDITY_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_LATCH_COEF_Pos (24U) -#define ADC_CALFACT_LATCH_COEF_Msk (0x1UL << ADC_CALFACT_LATCH_COEF_Pos) /*!< 0x01000000 */ -#define ADC_CALFACT_LATCH_COEF ADC_CALFACT_LATCH_COEF_Msk /*!< ADC calibration factors in differential mode */ -#define ADC_CALFACT_CAPTURE_COEF_Pos (25U) -#define ADC_CALFACT_CAPTURE_COEF_Msk (0x1UL << ADC_CALFACT_CAPTURE_COEF_Pos) /*!< 0x01000000 */ -#define ADC_CALFACT_CAPTURE_COEF ADC_CALFACT_CAPTURE_COEF_Msk /*!< ADC calibration factors in differential mode */ - -#define ADC4_CALFACT_CALFACT_Pos (0U) -#define ADC4_CALFACT_CALFACT_Msk (0x7FUL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x0000007F */ -#define ADC4_CALFACT_CALFACT ADC4_CALFACT_CALFACT_Msk /*!< ADC calibration factor in single-ended mode */ -#define ADC4_CALFACT_CALFACT_0 (0x01UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000001 */ -#define ADC4_CALFACT_CALFACT_1 (0x02UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000002 */ -#define ADC4_CALFACT_CALFACT_2 (0x04UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000004 */ -#define ADC4_CALFACT_CALFACT_3 (0x08UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000008 */ -#define ADC4_CALFACT_CALFACT_4 (0x10UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000010 */ -#define ADC4_CALFACT_CALFACT_5 (0x20UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000020 */ -#define ADC4_CALFACT_CALFACT_6 (0x40UL << ADC4_CALFACT_CALFACT_Pos) /*!< 0x00000040 */ - -/******************** Bit definition for ADC_CALFACT2 register ********************/ -#define ADC_CALFACT2_CALFACT_Pos (0U) -#define ADC_CALFACT2_CALFACT_Msk (0xFFFFFFFFUL << ADC_CALFACT2_CALFACT_Pos) /*!< 0xFFFFFFFF */ -#define ADC_CALFACT2_CALFACT ADC_CALFACT2_CALFACT_Msk /*!< ADC Linearity calibration factors */ -#define ADC_CALFACT2_CALFACT_0 (0x00000001UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000001 */ -#define ADC_CALFACT2_CALFACT_1 (0x00000002UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000002 */ -#define ADC_CALFACT2_CALFACT_2 (0x00000004UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000004 */ -#define ADC_CALFACT2_CALFACT_3 (0x00000008UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000008 */ -#define ADC_CALFACT2_CALFACT_4 (0x00000010UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000010 */ -#define ADC_CALFACT2_CALFACT_5 (0x00000020UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000020 */ -#define ADC_CALFACT2_CALFACT_6 (0x00000040UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000040 */ -#define ADC_CALFACT2_CALFACT_7 (0x00000080UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000080 */ -#define ADC_CALFACT2_CALFACT_8 (0x00000100UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000100 */ -#define ADC_CALFACT2_CALFACT_9 (0x00000200UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000200 */ -#define ADC_CALFACT2_CALFACT_10 (0x00000400UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000400 */ -#define ADC_CALFACT2_CALFACT_11 (0x00000800UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00000800 */ -#define ADC_CALFACT2_CALFACT_12 (0x00001000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00001000 */ -#define ADC_CALFACT2_CALFACT_13 (0x00002000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00002000 */ -#define ADC_CALFACT2_CALFACT_14 (0x00004000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00004000 */ -#define ADC_CALFACT2_CALFACT_15 (0x00008000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00008000 */ -#define ADC_CALFACT2_CALFACT_16 (0x00010000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00010000 */ -#define ADC_CALFACT2_CALFACT_17 (0x00020000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00020000 */ -#define ADC_CALFACT2_CALFACT_18 (0x00040000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00040000 */ -#define ADC_CALFACT2_CALFACT_19 (0x00080000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00080000 */ -#define ADC_CALFACT2_CALFACT_20 (0x00100000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00100000 */ -#define ADC_CALFACT2_CALFACT_21 (0x00200000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00200000 */ -#define ADC_CALFACT2_CALFACT_22 (0x00400000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00400000 */ -#define ADC_CALFACT2_CALFACT_23 (0x00800000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x00800000 */ -#define ADC_CALFACT2_CALFACT_24 (0x01000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x01000000 */ -#define ADC_CALFACT2_CALFACT_25 (0x02000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x02000000 */ -#define ADC_CALFACT2_CALFACT_26 (0x04000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x04000000 */ -#define ADC_CALFACT2_CALFACT_27 (0x08000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x08000000 */ -#define ADC_CALFACT2_CALFACT_28 (0x10000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x10000000 */ -#define ADC_CALFACT2_CALFACT_29 (0x20000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x20000000 */ -#define ADC_CALFACT2_CALFACT_30 (0x40000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x40000000 */ -#define ADC_CALFACT2_CALFACT_31 (0x80000000UL << ADC_CALFACT2_CALFACT_Pos) /*!< 0x80000000 */ - -/******************** Bit definition for ADC_OR register ********************/ -#define ADC_OR_CHN0SEL_Pos (0U) -#define ADC_OR_CHN0SEL_Msk (0x1UL << ADC_OR_CHN0SEL_Pos) /*!< 0x00000001 */ -#define ADC_OR_CHN0SEL ADC_OR_CHN0SEL_Msk /*!< ADC Channel 0 selection */ - -/************************* ADC Common registers *****************************/ - -#define ADC_CCR_PRESC_Pos (18U) -#define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */ -#define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */ -#define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */ -#define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */ -#define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */ -#define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */ - -#define ADC_CCR_VREFEN_Pos (22U) -#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ -#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */ -#define ADC_CCR_VSENSEEN_Pos (23U) -#define ADC_CCR_VSENSEEN_Msk (0x1UL << ADC_CCR_VSENSEEN_Pos) /*!< 0x00800000 */ -#define ADC_CCR_VSENSEEN ADC_CCR_VSENSEEN_Msk /*!< Temperature sensor enable */ -#define ADC_CCR_VBATEN_Pos (24U) -#define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */ -#define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */ -#define ADC_CCR_LFMEN_Pos (25U) -#define ADC_CCR_LFMEN_Msk (0x1UL << ADC_CCR_LFMEN_Pos) /*!< 0x02000000 */ -#define ADC_CCR_LFMEN ADC_CCR_LFMEN_Msk /*!< Low Frequency Mode Enable, specific ADC4*/ -#define ADC_CCR_VDDCOREN_Pos (26U) -#define ADC_CCR_VDDCOREN_Msk (0x1UL << ADC_CCR_VDDCOREN_Pos) /*!< 0x04000000 */ -#define ADC_CCR_VDDCOREN ADC_CCR_VDDCOREN_Msk /*!< VDDCode enable */ - - -/******************************************************************************/ -/* */ -/* CORDIC calculation unit */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CORDIC_CSR register *****************/ -#define CORDIC_CSR_FUNC_Pos (0U) -#define CORDIC_CSR_FUNC_Msk (0xFUL << CORDIC_CSR_FUNC_Pos) /*!< 0x0000000F */ -#define CORDIC_CSR_FUNC CORDIC_CSR_FUNC_Msk /*!< Function */ -#define CORDIC_CSR_FUNC_0 (0x1UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000001 */ -#define CORDIC_CSR_FUNC_1 (0x2UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000002 */ -#define CORDIC_CSR_FUNC_2 (0x4UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000004 */ -#define CORDIC_CSR_FUNC_3 (0x8UL << CORDIC_CSR_FUNC_Pos) /*!< 0x00000008 */ -#define CORDIC_CSR_PRECISION_Pos (4U) -#define CORDIC_CSR_PRECISION_Msk (0xFUL << CORDIC_CSR_PRECISION_Pos) /*!< 0x000000F0 */ -#define CORDIC_CSR_PRECISION CORDIC_CSR_PRECISION_Msk /*!< Precision */ -#define CORDIC_CSR_PRECISION_0 (0x1UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000010 */ -#define CORDIC_CSR_PRECISION_1 (0x2UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000020 */ -#define CORDIC_CSR_PRECISION_2 (0x4UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000040 */ -#define CORDIC_CSR_PRECISION_3 (0x8UL << CORDIC_CSR_PRECISION_Pos) /*!< 0x00000080 */ -#define CORDIC_CSR_SCALE_Pos (8U) -#define CORDIC_CSR_SCALE_Msk (0x7UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000700 */ -#define CORDIC_CSR_SCALE CORDIC_CSR_SCALE_Msk /*!< Scaling factor */ -#define CORDIC_CSR_SCALE_0 (0x1UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000100 */ -#define CORDIC_CSR_SCALE_1 (0x2UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000200 */ -#define CORDIC_CSR_SCALE_2 (0x4UL << CORDIC_CSR_SCALE_Pos) /*!< 0x00000400 */ -#define CORDIC_CSR_IEN_Pos (16U) -#define CORDIC_CSR_IEN_Msk (0x1UL << CORDIC_CSR_IEN_Pos) /*!< 0x00010000 */ -#define CORDIC_CSR_IEN CORDIC_CSR_IEN_Msk /*!< Interrupt Enable */ -#define CORDIC_CSR_DMAREN_Pos (17U) -#define CORDIC_CSR_DMAREN_Msk (0x1UL << CORDIC_CSR_DMAREN_Pos) /*!< 0x00020000 */ -#define CORDIC_CSR_DMAREN CORDIC_CSR_DMAREN_Msk /*!< DMA Read channel Enable */ -#define CORDIC_CSR_DMAWEN_Pos (18U) -#define CORDIC_CSR_DMAWEN_Msk (0x1UL << CORDIC_CSR_DMAWEN_Pos) /*!< 0x00040000 */ -#define CORDIC_CSR_DMAWEN CORDIC_CSR_DMAWEN_Msk /*!< DMA Write channel Enable */ -#define CORDIC_CSR_NRES_Pos (19U) -#define CORDIC_CSR_NRES_Msk (0x1UL << CORDIC_CSR_NRES_Pos) /*!< 0x00080000 */ -#define CORDIC_CSR_NRES CORDIC_CSR_NRES_Msk /*!< Number of results in WDATA register */ -#define CORDIC_CSR_NARGS_Pos (20U) -#define CORDIC_CSR_NARGS_Msk (0x1UL << CORDIC_CSR_NARGS_Pos) /*!< 0x00100000 */ -#define CORDIC_CSR_NARGS CORDIC_CSR_NARGS_Msk /*!< Number of arguments in RDATA register */ -#define CORDIC_CSR_RESSIZE_Pos (21U) -#define CORDIC_CSR_RESSIZE_Msk (0x1UL << CORDIC_CSR_RESSIZE_Pos) /*!< 0x00200000 */ -#define CORDIC_CSR_RESSIZE CORDIC_CSR_RESSIZE_Msk /*!< Width of output data */ -#define CORDIC_CSR_ARGSIZE_Pos (22U) -#define CORDIC_CSR_ARGSIZE_Msk (0x1UL << CORDIC_CSR_ARGSIZE_Pos) /*!< 0x00400000 */ -#define CORDIC_CSR_ARGSIZE CORDIC_CSR_ARGSIZE_Msk /*!< Width of input data */ -#define CORDIC_CSR_RRDY_Pos (31U) -#define CORDIC_CSR_RRDY_Msk (0x1UL << CORDIC_CSR_RRDY_Pos) /*!< 0x80000000 */ -#define CORDIC_CSR_RRDY CORDIC_CSR_RRDY_Msk /*!< Result Ready Flag */ - -/******************* Bit definition for CORDIC_WDATA register ***************/ -#define CORDIC_WDATA_ARG_Pos (0U) -#define CORDIC_WDATA_ARG_Msk (0xFFFFFFFFUL << CORDIC_WDATA_ARG_Pos) /*!< 0xFFFFFFFF */ -#define CORDIC_WDATA_ARG CORDIC_WDATA_ARG_Msk /*!< Input Argument */ - -/******************* Bit definition for CORDIC_RDATA register ***************/ -#define CORDIC_RDATA_RES_Pos (0U) -#define CORDIC_RDATA_RES_Msk (0xFFFFFFFFUL << CORDIC_RDATA_RES_Pos) /*!< 0xFFFFFFFF */ -#define CORDIC_RDATA_RES CORDIC_RDATA_RES_Msk /*!< Output Result */ - -/******************************************************************************/ -/* */ -/* CRC calculation unit */ -/* */ -/******************************************************************************/ -/******************* Bit definition for CRC_DR register *********************/ -#define CRC_DR_DR_Pos (0U) -#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ - -/******************* Bit definition for CRC_IDR register ********************/ -#define CRC_IDR_IDR_Pos (0U) -#define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ -#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bits data register bits */ - -/******************** Bit definition for CRC_CR register ********************/ -#define CRC_CR_RESET_Pos (0U) -#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ -#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ -#define CRC_CR_POLYSIZE_Pos (3U) -#define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */ -#define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */ -#define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */ -#define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */ -#define CRC_CR_REV_IN_Pos (5U) -#define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */ -#define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */ -#define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */ -#define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */ -#define CRC_CR_REV_OUT_Pos (7U) -#define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */ -#define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */ - -/******************* Bit definition for CRC_INIT register *******************/ -#define CRC_INIT_INIT_Pos (0U) -#define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */ -#define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */ - -/******************* Bit definition for CRC_POL register ********************/ -#define CRC_POL_POL_Pos (0U) -#define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */ -#define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */ - -/******************************************************************************/ -/* */ -/* CRS Clock Recovery System */ -/******************************************************************************/ -/******************* Bit definition for CRS_CR register *********************/ -#define CRS_CR_SYNCOKIE_Pos (0U) -#define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */ -#define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */ -#define CRS_CR_SYNCWARNIE_Pos (1U) -#define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */ -#define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */ -#define CRS_CR_ERRIE_Pos (2U) -#define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */ -#define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */ -#define CRS_CR_ESYNCIE_Pos (3U) -#define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */ -#define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */ -#define CRS_CR_CEN_Pos (5U) -#define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */ -#define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */ -#define CRS_CR_AUTOTRIMEN_Pos (6U) -#define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */ -#define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */ -#define CRS_CR_SWSYNC_Pos (7U) -#define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */ -#define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */ -#define CRS_CR_TRIM_Pos (8U) -#define CRS_CR_TRIM_Msk (0x7FUL << CRS_CR_TRIM_Pos) /*!< 0x00007F00 */ -#define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */ - -/******************* Bit definition for CRS_CFGR register *********************/ -#define CRS_CFGR_RELOAD_Pos (0U) -#define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */ -#define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */ -#define CRS_CFGR_FELIM_Pos (16U) -#define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */ -#define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */ -#define CRS_CFGR_SYNCDIV_Pos (24U) -#define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */ -#define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */ -#define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */ -#define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */ -#define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */ -#define CRS_CFGR_SYNCSRC_Pos (28U) -#define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */ -#define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */ -#define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */ -#define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */ -#define CRS_CFGR_SYNCPOL_Pos (31U) -#define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */ -#define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */ - -/******************* Bit definition for CRS_ISR register *********************/ -#define CRS_ISR_SYNCOKF_Pos (0U) -#define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */ -#define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */ -#define CRS_ISR_SYNCWARNF_Pos (1U) -#define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */ -#define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */ -#define CRS_ISR_ERRF_Pos (2U) -#define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */ -#define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */ -#define CRS_ISR_ESYNCF_Pos (3U) -#define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */ -#define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */ -#define CRS_ISR_SYNCERR_Pos (8U) -#define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */ -#define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */ -#define CRS_ISR_SYNCMISS_Pos (9U) -#define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */ -#define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */ -#define CRS_ISR_TRIMOVF_Pos (10U) -#define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */ -#define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */ -#define CRS_ISR_FEDIR_Pos (15U) -#define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */ -#define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */ -#define CRS_ISR_FECAP_Pos (16U) -#define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */ -#define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */ - -/******************* Bit definition for CRS_ICR register *********************/ -#define CRS_ICR_SYNCOKC_Pos (0U) -#define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */ -#define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */ -#define CRS_ICR_SYNCWARNC_Pos (1U) -#define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */ -#define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */ -#define CRS_ICR_ERRC_Pos (2U) -#define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */ -#define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */ -#define CRS_ICR_ESYNCC_Pos (3U) -#define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */ -#define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */ - -/******************************************************************************/ -/* */ -/* RNG */ -/* */ -/******************************************************************************/ -/******************** Bits definition for RNG_CR register *******************/ -#define RNG_CR_RNGEN_Pos (2U) -#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */ -#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk -#define RNG_CR_IE_Pos (3U) -#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */ -#define RNG_CR_IE RNG_CR_IE_Msk -#define RNG_CR_CED_Pos (5U) -#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */ -#define RNG_CR_CED RNG_CR_CED_Msk -#define RNG_CR_ARDIS_Pos (7U) -#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) -#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk -#define RNG_CR_RNG_CONFIG3_Pos (8U) -#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) -#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk -#define RNG_CR_NISTC_Pos (12U) -#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) -#define RNG_CR_NISTC RNG_CR_NISTC_Msk -#define RNG_CR_RNG_CONFIG2_Pos (13U) -#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) -#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk -#define RNG_CR_CLKDIV_Pos (16U) -#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) -#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk -#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */ -#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */ -#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */ -#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */ -#define RNG_CR_RNG_CONFIG1_Pos (20U) -#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) -#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk -#define RNG_CR_CONDRST_Pos (30U) -#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) -#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk -#define RNG_CR_CONFIGLOCK_Pos (31U) -#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) -#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk - -/******************** Bits definition for RNG_SR register *******************/ -#define RNG_SR_DRDY_Pos (0U) -#define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */ -#define RNG_SR_DRDY RNG_SR_DRDY_Msk -#define RNG_SR_CECS_Pos (1U) -#define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */ -#define RNG_SR_CECS RNG_SR_CECS_Msk -#define RNG_SR_SECS_Pos (2U) -#define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */ -#define RNG_SR_SECS RNG_SR_SECS_Msk -#define RNG_SR_CEIS_Pos (5U) -#define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */ -#define RNG_SR_CEIS RNG_SR_CEIS_Msk -#define RNG_SR_SEIS_Pos (6U) -#define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */ -#define RNG_SR_SEIS RNG_SR_SEIS_Msk - -/******************** Bits definition for RNG_NSCR register *******************/ -#define RNG_NSCR_EN_OSC1_Pos (0U) -#define RNG_NSCR_EN_OSC1_Msk (0x7UL << RNG_NSCR_EN_OSC1_Pos) /*!< 0x00000007 */ -#define RNG_NSCR_EN_OSC1 RNG_NSCR_EN_OSC1_Msk -#define RNG_NSCR_EN_OSC2_Pos (3U) -#define RNG_NSCR_EN_OSC2_Msk (0x7UL << RNG_NSCR_EN_OSC2_Pos) /*!< 0x00000038 */ -#define RNG_NSCR_EN_OSC2 RNG_NSCR_EN_OSC2_Msk -#define RNG_NSCR_EN_OSC3_Pos (6U) -#define RNG_NSCR_EN_OSC3_Msk (0x7UL << RNG_NSCR_EN_OSC3_Pos) /*!< 0x000001C0 */ -#define RNG_NSCR_EN_OSC3 RNG_NSCR_EN_OSC3_Msk -#define RNG_NSCR_EN_OSC4_Pos (9U) -#define RNG_NSCR_EN_OSC4_Msk (0x7UL << RNG_NSCR_EN_OSC4_Pos) /*!< 0x00000E00 */ -#define RNG_NSCR_EN_OSC4 RNG_NSCR_EN_OSC4_Msk -#define RNG_NSCR_EN_OSC5_Pos (12U) -#define RNG_NSCR_EN_OSC5_Msk (0x7UL << RNG_NSCR_EN_OSC5_Pos) /*!< 0x00007000 */ -#define RNG_NSCR_EN_OSC5 RNG_NSCR_EN_OSC5_Msk -#define RNG_NSCR_EN_OSC6_Pos (15U) -#define RNG_NSCR_EN_OSC6_Msk (0x7UL << RNG_NSCR_EN_OSC6_Pos) /*!< 0x00038000 */ -#define RNG_NSCR_EN_OSC6 RNG_NSCR_EN_OSC6_Msk - -/******************** Bits definition for RNG_HTCR register *******************/ -#define RNG_HTCR_HTCFG_Pos (0U) -#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */ -#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk - -/******************************************************************************/ -/* */ -/* Digital to Analog Converter */ -/* */ -/******************************************************************************/ -#define DAC_CHANNEL2_SUPPORT /*!< DAC feature available only on specific devices: DAC channel 2 available */ - -/******************** Bit definition for DAC_CR register ********************/ -#define DAC_CR_EN1_Pos (0U) -#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ -#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!*/ -#define DAC_CR_CEN1_Pos (14U) -#define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */ -#define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!*/ -#define DAC_CR_EN2_Pos (16U) -#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ -#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!*/ -#define DAC_CR_CEN2_Pos (30U) -#define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */ -#define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!*/ - -/***************** Bit definition for DAC_SWTRIGR register ******************/ -#define DAC_SWTRIGR_SWTRIG1_Pos (0U) -#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ -#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!> 1U) - -#define FLASH_PAGE_SIZE 0x2000U /* 8 KB */ - -#define FLASH_PAGE_NB (FLASH_BANK_SIZE / FLASH_PAGE_SIZE) - -/******************* Bits definition for FLASH_ACR register *****************/ -#define FLASH_ACR_LATENCY_Pos (0U) -#define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */ -#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ -#define FLASH_ACR_LATENCY_0WS (0x00000000U) -#define FLASH_ACR_LATENCY_1WS (0x00000001U) -#define FLASH_ACR_LATENCY_2WS (0x00000002U) -#define FLASH_ACR_LATENCY_3WS (0x00000003U) -#define FLASH_ACR_LATENCY_4WS (0x00000004U) -#define FLASH_ACR_LATENCY_5WS (0x00000005U) -#define FLASH_ACR_LATENCY_6WS (0x00000006U) -#define FLASH_ACR_LATENCY_7WS (0x00000007U) -#define FLASH_ACR_LATENCY_8WS (0x00000008U) -#define FLASH_ACR_LATENCY_9WS (0x00000009U) -#define FLASH_ACR_LATENCY_10WS (0x0000000AU) -#define FLASH_ACR_LATENCY_11WS (0x0000000BU) -#define FLASH_ACR_LATENCY_12WS (0x0000000CU) -#define FLASH_ACR_LATENCY_13WS (0x0000000DU) -#define FLASH_ACR_LATENCY_14WS (0x0000000EU) -#define FLASH_ACR_LATENCY_15WS (0x0000000FU) -#define FLASH_ACR_PRFTEN_Pos (8U) -#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ -#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ -#define FLASH_ACR_LPM_Pos (11U) -#define FLASH_ACR_LPM_Msk (0x1UL << FLASH_ACR_LPM_Pos) /*!< 0x00000800 */ -#define FLASH_ACR_LPM FLASH_ACR_LPM_Msk /*!< Low-Power read mode */ -#define FLASH_ACR_PDREQ1_Pos (12U) -#define FLASH_ACR_PDREQ1_Msk (0x1UL << FLASH_ACR_PDREQ1_Pos) /*!< 0x00001000 */ -#define FLASH_ACR_PDREQ1 FLASH_ACR_PDREQ1_Msk /*!< Bank 1 power-down mode request */ -#define FLASH_ACR_PDREQ2_Pos (13U) -#define FLASH_ACR_PDREQ2_Msk (0x1UL << FLASH_ACR_PDREQ2_Pos) /*!< 0x00002000 */ -#define FLASH_ACR_PDREQ2 FLASH_ACR_PDREQ2_Msk /*!< Bank 2 power-down mode request */ -#define FLASH_ACR_SLEEP_PD_Pos (14U) -#define FLASH_ACR_SLEEP_PD_Msk (0x1UL << FLASH_ACR_SLEEP_PD_Pos) /*!< 0x00004000 */ -#define FLASH_ACR_SLEEP_PD FLASH_ACR_SLEEP_PD_Msk /*!< Flash power-down mode during sleep */ - -/****************** Bits definition for FLASH_NSSR register *****************/ -#define FLASH_NSSR_EOP_Pos (0U) -#define FLASH_NSSR_EOP_Msk (0x1UL << FLASH_NSSR_EOP_Pos) /*!< 0x00000001 */ -#define FLASH_NSSR_EOP FLASH_NSSR_EOP_Msk /*!< Non-secure end of operation */ -#define FLASH_NSSR_OPERR_Pos (1U) -#define FLASH_NSSR_OPERR_Msk (0x1UL << FLASH_NSSR_OPERR_Pos) /*!< 0x00000002 */ -#define FLASH_NSSR_OPERR FLASH_NSSR_OPERR_Msk /*!< Non-secure operation error */ -#define FLASH_NSSR_PROGERR_Pos (3U) -#define FLASH_NSSR_PROGERR_Msk (0x1UL << FLASH_NSSR_PROGERR_Pos) /*!< 0x00000008 */ -#define FLASH_NSSR_PROGERR FLASH_NSSR_PROGERR_Msk /*!< Non-secure programming error */ -#define FLASH_NSSR_WRPERR_Pos (4U) -#define FLASH_NSSR_WRPERR_Msk (0x1UL << FLASH_NSSR_WRPERR_Pos) /*!< 0x00000010 */ -#define FLASH_NSSR_WRPERR FLASH_NSSR_WRPERR_Msk /*!< Non-secure write protection error */ -#define FLASH_NSSR_PGAERR_Pos (5U) -#define FLASH_NSSR_PGAERR_Msk (0x1UL << FLASH_NSSR_PGAERR_Pos) /*!< 0x00000020 */ -#define FLASH_NSSR_PGAERR FLASH_NSSR_PGAERR_Msk /*!< Non-secure programming alignment error */ -#define FLASH_NSSR_SIZERR_Pos (6U) -#define FLASH_NSSR_SIZERR_Msk (0x1UL << FLASH_NSSR_SIZERR_Pos) /*!< 0x00000040 */ -#define FLASH_NSSR_SIZERR FLASH_NSSR_SIZERR_Msk /*!< Non-secure size error */ -#define FLASH_NSSR_PGSERR_Pos (7U) -#define FLASH_NSSR_PGSERR_Msk (0x1UL << FLASH_NSSR_PGSERR_Pos) /*!< 0x00000080 */ -#define FLASH_NSSR_PGSERR FLASH_NSSR_PGSERR_Msk /*!< Non-secure programming sequence error */ -#define FLASH_NSSR_OPTWERR_Pos (13U) -#define FLASH_NSSR_OPTWERR_Msk (0x1UL << FLASH_NSSR_OPTWERR_Pos) /*!< 0x00002000 */ -#define FLASH_NSSR_OPTWERR FLASH_NSSR_OPTWERR_Msk /*!< Option write error */ -#define FLASH_NSSR_BSY_Pos (16U) -#define FLASH_NSSR_BSY_Msk (0x1UL << FLASH_NSSR_BSY_Pos) /*!< 0x00010000 */ -#define FLASH_NSSR_BSY FLASH_NSSR_BSY_Msk /*!< Non-secure busy */ -#define FLASH_NSSR_WDW_Pos (17U) -#define FLASH_NSSR_WDW_Msk (0x1UL << FLASH_NSSR_WDW_Pos) /*!< 0x00020000 */ -#define FLASH_NSSR_WDW FLASH_NSSR_WDW_Msk /*!< Non-secure wait data to write */ -#define FLASH_NSSR_OEM1LOCK_Pos (18U) -#define FLASH_NSSR_OEM1LOCK_Msk (0x1UL << FLASH_NSSR_OEM1LOCK_Pos) /*!< 0x00040000 */ -#define FLASH_NSSR_OEM1LOCK FLASH_NSSR_OEM1LOCK_Msk /*!< OEM1 lock */ -#define FLASH_NSSR_OEM2LOCK_Pos (19U) -#define FLASH_NSSR_OEM2LOCK_Msk (0x1UL << FLASH_NSSR_OEM2LOCK_Pos) /*!< 0x00080000 */ -#define FLASH_NSSR_OEM2LOCK FLASH_NSSR_OEM2LOCK_Msk /*!< OEM2 lock */ -#define FLASH_NSSR_PD1_Pos (20U) -#define FLASH_NSSR_PD1_Msk (0x1UL << FLASH_NSSR_PD1_Pos) /*!< 0x00100000 */ -#define FLASH_NSSR_PD1 FLASH_NSSR_PD1_Msk /*!< Bank 1 in power-down mode */ -#define FLASH_NSSR_PD2_Pos (21U) -#define FLASH_NSSR_PD2_Msk (0x1UL << FLASH_NSSR_PD2_Pos) /*!< 0x00200000 */ -#define FLASH_NSSR_PD2 FLASH_NSSR_PD2_Msk /*!< Bank 2 in power-down mode */ - -/****************** Bits definition for FLASH_SECSR register ****************/ -#define FLASH_SECSR_EOP_Pos (0U) -#define FLASH_SECSR_EOP_Msk (0x1UL << FLASH_SECSR_EOP_Pos) /*!< 0x00000001 */ -#define FLASH_SECSR_EOP FLASH_SECSR_EOP_Msk /*!< Secure end of operation */ -#define FLASH_SECSR_OPERR_Pos (1U) -#define FLASH_SECSR_OPERR_Msk (0x1UL << FLASH_SECSR_OPERR_Pos) /*!< 0x00000002 */ -#define FLASH_SECSR_OPERR FLASH_SECSR_OPERR_Msk /*!< Secure operation error */ -#define FLASH_SECSR_PROGERR_Pos (3U) -#define FLASH_SECSR_PROGERR_Msk (0x1UL << FLASH_SECSR_PROGERR_Pos) /*!< 0x00000008 */ -#define FLASH_SECSR_PROGERR FLASH_SECSR_PROGERR_Msk /*!< Secure programming error */ -#define FLASH_SECSR_WRPERR_Pos (4U) -#define FLASH_SECSR_WRPERR_Msk (0x1UL << FLASH_SECSR_WRPERR_Pos) /*!< 0x00000010 */ -#define FLASH_SECSR_WRPERR FLASH_SECSR_WRPERR_Msk /*!< Secure write protection error */ -#define FLASH_SECSR_PGAERR_Pos (5U) -#define FLASH_SECSR_PGAERR_Msk (0x1UL << FLASH_SECSR_PGAERR_Pos) /*!< 0x00000020 */ -#define FLASH_SECSR_PGAERR FLASH_SECSR_PGAERR_Msk /*!< Secure programming alignment error */ -#define FLASH_SECSR_SIZERR_Pos (6U) -#define FLASH_SECSR_SIZERR_Msk (0x1UL << FLASH_SECSR_SIZERR_Pos) /*!< 0x00000040 */ -#define FLASH_SECSR_SIZERR FLASH_SECSR_SIZERR_Msk /*!< Secure size error */ -#define FLASH_SECSR_PGSERR_Pos (7U) -#define FLASH_SECSR_PGSERR_Msk (0x1UL << FLASH_SECSR_PGSERR_Pos) /*!< 0x00000080 */ -#define FLASH_SECSR_PGSERR FLASH_SECSR_PGSERR_Msk /*!< Secure programming sequence error */ -#define FLASH_SECSR_BSY_Pos (16U) -#define FLASH_SECSR_BSY_Msk (0x1UL << FLASH_SECSR_BSY_Pos) /*!< 0x00010000 */ -#define FLASH_SECSR_BSY FLASH_SECSR_BSY_Msk /*!< Secure busy */ -#define FLASH_SECSR_WDW_Pos (17U) -#define FLASH_SECSR_WDW_Msk (0x1UL << FLASH_SECSR_WDW_Pos) /*!< 0x00020000 */ -#define FLASH_SECSR_WDW FLASH_SECSR_WDW_Msk /*!< Secure wait data to write */ - -/****************** Bits definition for FLASH_NSCR register *****************/ -#define FLASH_NSCR_PG_Pos (0U) -#define FLASH_NSCR_PG_Msk (0x1UL << FLASH_NSCR_PG_Pos) /*!< 0x00000001 */ -#define FLASH_NSCR_PG FLASH_NSCR_PG_Msk /*!< Non-secure Programming */ -#define FLASH_NSCR_PER_Pos (1U) -#define FLASH_NSCR_PER_Msk (0x1UL << FLASH_NSCR_PER_Pos) /*!< 0x00000002 */ -#define FLASH_NSCR_PER FLASH_NSCR_PER_Msk /*!< Non-secure Page Erase */ -#define FLASH_NSCR_MER1_Pos (2U) -#define FLASH_NSCR_MER1_Msk (0x1UL << FLASH_NSCR_MER1_Pos) /*!< 0x00000004 */ -#define FLASH_NSCR_MER1 FLASH_NSCR_MER1_Msk /*!< Non-secure Bank 1 Mass Erase */ -#define FLASH_NSCR_PNB_Pos (3U) -#define FLASH_NSCR_PNB_Msk (0x7FUL << FLASH_NSCR_PNB_Pos) /*!< 0x000003F8 */ -#define FLASH_NSCR_PNB FLASH_NSCR_PNB_Msk /*!< Non-secure Page Number selection */ -#define FLASH_NSCR_BKER_Pos (11U) -#define FLASH_NSCR_BKER_Msk (0x1UL << FLASH_NSCR_BKER_Pos) /*!< 0x00000800 */ -#define FLASH_NSCR_BKER FLASH_NSCR_BKER_Msk /*!< Non-secure Bank Selection for Page Erase */ -#define FLASH_NSCR_BWR_Pos (14U) -#define FLASH_NSCR_BWR_Msk (0x1UL << FLASH_NSCR_BWR_Pos) /*!< 0x00004000 */ -#define FLASH_NSCR_BWR FLASH_NSCR_BWR_Msk /*!< Non-secure Burst Write Programming mode */ -#define FLASH_NSCR_MER2_Pos (15U) -#define FLASH_NSCR_MER2_Msk (0x1UL << FLASH_NSCR_MER2_Pos) /*!< 0x00008000 */ -#define FLASH_NSCR_MER2 FLASH_NSCR_MER2_Msk /*!< Non-secure Bank 2 Mass Erase */ -#define FLASH_NSCR_STRT_Pos (16U) -#define FLASH_NSCR_STRT_Msk (0x1UL << FLASH_NSCR_STRT_Pos) /*!< 0x00010000 */ -#define FLASH_NSCR_STRT FLASH_NSCR_STRT_Msk /*!< Non-secure Start */ -#define FLASH_NSCR_OPTSTRT_Pos (17U) -#define FLASH_NSCR_OPTSTRT_Msk (0x1UL << FLASH_NSCR_OPTSTRT_Pos) /*!< 0x00020000 */ -#define FLASH_NSCR_OPTSTRT FLASH_NSCR_OPTSTRT_Msk /*!< Option Modification Start */ -#define FLASH_NSCR_EOPIE_Pos (24U) -#define FLASH_NSCR_EOPIE_Msk (0x1UL << FLASH_NSCR_EOPIE_Pos) /*!< 0x01000000 */ -#define FLASH_NSCR_EOPIE FLASH_NSCR_EOPIE_Msk /*!< Non-secure End of operation interrupt enable */ -#define FLASH_NSCR_ERRIE_Pos (25U) -#define FLASH_NSCR_ERRIE_Msk (0x1UL << FLASH_NSCR_ERRIE_Pos) /*!< 0x02000000 */ -#define FLASH_NSCR_ERRIE FLASH_NSCR_ERRIE_Msk /*!< Non-secure error interrupt enable */ -#define FLASH_NSCR_OBL_LAUNCH_Pos (27U) -#define FLASH_NSCR_OBL_LAUNCH_Msk (0x1UL << FLASH_NSCR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ -#define FLASH_NSCR_OBL_LAUNCH FLASH_NSCR_OBL_LAUNCH_Msk /*!< Force the option byte loading */ -#define FLASH_NSCR_OPTLOCK_Pos (30U) -#define FLASH_NSCR_OPTLOCK_Msk (0x1UL << FLASH_NSCR_OPTLOCK_Pos) /*!< 0x40000000 */ -#define FLASH_NSCR_OPTLOCK FLASH_NSCR_OPTLOCK_Msk /*!< Option Lock */ -#define FLASH_NSCR_LOCK_Pos (31U) -#define FLASH_NSCR_LOCK_Msk (0x1UL << FLASH_NSCR_LOCK_Pos) /*!< 0x80000000 */ -#define FLASH_NSCR_LOCK FLASH_NSCR_LOCK_Msk /*!< Non-secure Lock */ - -/****************** Bits definition for FLASH_SECCR register ****************/ -#define FLASH_SECCR_PG_Pos (0U) -#define FLASH_SECCR_PG_Msk (0x1UL << FLASH_SECCR_PG_Pos) /*!< 0x00000001 */ -#define FLASH_SECCR_PG FLASH_SECCR_PG_Msk /*!< Secure Programming */ -#define FLASH_SECCR_PER_Pos (1U) -#define FLASH_SECCR_PER_Msk (0x1UL << FLASH_SECCR_PER_Pos) /*!< 0x00000002 */ -#define FLASH_SECCR_PER FLASH_SECCR_PER_Msk /*!< Secure Page Erase */ -#define FLASH_SECCR_MER1_Pos (2U) -#define FLASH_SECCR_MER1_Msk (0x1UL << FLASH_SECCR_MER1_Pos) /*!< 0x00000004 */ -#define FLASH_SECCR_MER1 FLASH_SECCR_MER1_Msk /*!< Secure Bank 1 Mass Erase */ -#define FLASH_SECCR_PNB_Pos (3U) -#define FLASH_SECCR_PNB_Msk (0x7FUL << FLASH_SECCR_PNB_Pos) /*!< 0x000003F8 */ -#define FLASH_SECCR_PNB FLASH_SECCR_PNB_Msk /*!< Secure Page Number selection */ -#define FLASH_SECCR_BKER_Pos (11U) -#define FLASH_SECCR_BKER_Msk (0x1UL << FLASH_SECCR_BKER_Pos) /*!< 0x00000800 */ -#define FLASH_SECCR_BKER FLASH_SECCR_BKER_Msk /*!< Secure Bank Selection for Page Erase */ -#define FLASH_SECCR_BWR_Pos (14U) -#define FLASH_SECCR_BWR_Msk (0x1UL << FLASH_SECCR_BWR_Pos) /*!< 0x00004000 */ -#define FLASH_SECCR_BWR FLASH_SECCR_BWR_Msk /*!< Secure Burst Write programming mode */ -#define FLASH_SECCR_MER2_Pos (15U) -#define FLASH_SECCR_MER2_Msk (0x1UL << FLASH_SECCR_MER2_Pos) /*!< 0x00008000 */ -#define FLASH_SECCR_MER2 FLASH_SECCR_MER2_Msk /*!< Secure Bank 2 Mass Erase */ -#define FLASH_SECCR_STRT_Pos (16U) -#define FLASH_SECCR_STRT_Msk (0x1UL << FLASH_SECCR_STRT_Pos) /*!< 0x00010000 */ -#define FLASH_SECCR_STRT FLASH_SECCR_STRT_Msk /*!< Secure Start */ -#define FLASH_SECCR_EOPIE_Pos (24U) -#define FLASH_SECCR_EOPIE_Msk (0x1UL << FLASH_SECCR_EOPIE_Pos) /*!< 0x01000000 */ -#define FLASH_SECCR_EOPIE FLASH_SECCR_EOPIE_Msk /*!< Secure end of operation interrupt enable */ -#define FLASH_SECCR_ERRIE_Pos (25U) -#define FLASH_SECCR_ERRIE_Msk (0x1UL << FLASH_SECCR_ERRIE_Pos) /*!< 0x02000000 */ -#define FLASH_SECCR_ERRIE FLASH_SECCR_ERRIE_Msk /*!< Secure error interrupt enable */ -#define FLASH_SECCR_INV_Pos (29U) -#define FLASH_SECCR_INV_Msk (0x1UL << FLASH_SECCR_INV_Pos) /*!< 0x20000000 */ -#define FLASH_SECCR_INV FLASH_SECCR_INV_Msk /*!< Flash Security State Invert */ -#define FLASH_SECCR_LOCK_Pos (31U) -#define FLASH_SECCR_LOCK_Msk (0x1UL << FLASH_SECCR_LOCK_Pos) /*!< 0x80000000 */ -#define FLASH_SECCR_LOCK FLASH_SECCR_LOCK_Msk /*!< Secure Lock */ - -/******************* Bits definition for FLASH_ECCR register ***************/ -#define FLASH_ECCR_ADDR_ECC_Pos (0U) -#define FLASH_ECCR_ADDR_ECC_Msk (0xFFFFFUL << FLASH_ECCR_ADDR_ECC_Pos) /*!< 0x000FFFFF */ -#define FLASH_ECCR_ADDR_ECC FLASH_ECCR_ADDR_ECC_Msk /*!< ECC fail address */ -#define FLASH_ECCR_BK_ECC_Pos (21U) -#define FLASH_ECCR_BK_ECC_Msk (0x1UL << FLASH_ECCR_BK_ECC_Pos) /*!< 0x00200000 */ -#define FLASH_ECCR_BK_ECC FLASH_ECCR_BK_ECC_Msk /*!< ECC fail bank */ -#define FLASH_ECCR_SYSF_ECC_Pos (22U) -#define FLASH_ECCR_SYSF_ECC_Msk (0x1UL << FLASH_ECCR_SYSF_ECC_Pos) /*!< 0x00400000 */ -#define FLASH_ECCR_SYSF_ECC FLASH_ECCR_SYSF_ECC_Msk /*!< System Flash ECC fail */ -#define FLASH_ECCR_ECCIE_Pos (24U) -#define FLASH_ECCR_ECCIE_Msk (0x1UL << FLASH_ECCR_ECCIE_Pos) /*!< 0x01000000 */ -#define FLASH_ECCR_ECCIE FLASH_ECCR_ECCIE_Msk /*!< ECC correction interrupt enable */ -#define FLASH_ECCR_ECCC_Pos (30U) -#define FLASH_ECCR_ECCC_Msk (0x1UL << FLASH_ECCR_ECCC_Pos) /*!< 0x40000000 */ -#define FLASH_ECCR_ECCC FLASH_ECCR_ECCC_Msk /*!< ECC correction */ -#define FLASH_ECCR_ECCD_Pos (31U) -#define FLASH_ECCR_ECCD_Msk (0x1UL << FLASH_ECCR_ECCD_Pos) /*!< 0x80000000 */ -#define FLASH_ECCR_ECCD FLASH_ECCR_ECCD_Msk /*!< ECC detection */ - -/******************* Bits definition for FLASH_OPSR register ***************/ -#define FLASH_OPSR_ADDR_OP_Pos (0U) -#define FLASH_OPSR_ADDR_OP_Msk (0xFFFFFUL << FLASH_OPSR_ADDR_OP_Pos) /*!< 0x000FFFFF */ -#define FLASH_OPSR_ADDR_OP FLASH_OPSR_ADDR_OP_Msk /*!< Flash operation address */ -#define FLASH_OPSR_BK_OP_Pos (21U) -#define FLASH_OPSR_BK_OP_Msk (0x1UL << FLASH_OPSR_BK_OP_Pos) /*!< 0x00200000 */ -#define FLASH_OPSR_BK_OP FLASH_OPSR_BK_OP_Msk /*!< Interrupted operation bank */ -#define FLASH_OPSR_SYSF_OP_Pos (22U) -#define FLASH_OPSR_SYSF_OP_Msk (0x1UL << FLASH_OPSR_SYSF_OP_Pos) /*!< 0x00400000 */ -#define FLASH_OPSR_SYSF_OP FLASH_OPSR_SYSF_OP_Msk /*!< Operation in System Flash interrupted */ -#define FLASH_OPSR_CODE_OP_Pos (29U) -#define FLASH_OPSR_CODE_OP_Msk (0x7UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0xE0000000 */ -#define FLASH_OPSR_CODE_OP FLASH_OPSR_CODE_OP_Msk /*!< Flash operation code */ -#define FLASH_OPSR_CODE_OP_0 (0x1UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x20000000 */ -#define FLASH_OPSR_CODE_OP_1 (0x2UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x40000000 */ -#define FLASH_OPSR_CODE_OP_2 (0x4UL << FLASH_OPSR_CODE_OP_Pos) /*!< 0x80000000 */ - -/******************* Bits definition for FLASH_OPTR register ***************/ -#define FLASH_OPTR_RDP_Pos (0U) -#define FLASH_OPTR_RDP_Msk (0xFFUL << FLASH_OPTR_RDP_Pos) /*!< 0x000000FF */ -#define FLASH_OPTR_RDP FLASH_OPTR_RDP_Msk /*!< Readout protection level */ -#define FLASH_OPTR_BOR_LEV_Pos (8U) -#define FLASH_OPTR_BOR_LEV_Msk (0x7UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000700 */ -#define FLASH_OPTR_BOR_LEV FLASH_OPTR_BOR_LEV_Msk /*!< BOR reset Level */ -#define FLASH_OPTR_BOR_LEV_0 (0x1UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000100 */ -#define FLASH_OPTR_BOR_LEV_1 (0x2UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000200 */ -#define FLASH_OPTR_BOR_LEV_2 (0x4UL << FLASH_OPTR_BOR_LEV_Pos) /*!< 0x00000400 */ -#define FLASH_OPTR_nRST_STOP_Pos (12U) -#define FLASH_OPTR_nRST_STOP_Msk (0x1UL << FLASH_OPTR_nRST_STOP_Pos) /*!< 0x00001000 */ -#define FLASH_OPTR_nRST_STOP FLASH_OPTR_nRST_STOP_Msk /*!< nRST_STOP */ -#define FLASH_OPTR_nRST_STDBY_Pos (13U) -#define FLASH_OPTR_nRST_STDBY_Msk (0x1UL << FLASH_OPTR_nRST_STDBY_Pos) /*!< 0x00002000 */ -#define FLASH_OPTR_nRST_STDBY FLASH_OPTR_nRST_STDBY_Msk /*!< nRST_STDBY */ -#define FLASH_OPTR_nRST_SHDW_Pos (14U) -#define FLASH_OPTR_nRST_SHDW_Msk (0x1UL << FLASH_OPTR_nRST_SHDW_Pos) /*!< 0x00004000 */ -#define FLASH_OPTR_nRST_SHDW FLASH_OPTR_nRST_SHDW_Msk /*!< nRST_SHDW */ -#define FLASH_OPTR_SRAM_RST_Pos (15U) -#define FLASH_OPTR_SRAM_RST_Msk (0x1UL << FLASH_OPTR_SRAM_RST_Pos) /*!< 0x00008000 */ -#define FLASH_OPTR_SRAM_RST FLASH_OPTR_SRAM_RST_Msk /*!< All SRAMs (except SRAM2 and BKPSRAM) erase upon system reset */ -#define FLASH_OPTR_IWDG_SW_Pos (16U) -#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ -#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk /*!< Independent watchdog selection */ -#define FLASH_OPTR_IWDG_STOP_Pos (17U) -#define FLASH_OPTR_IWDG_STOP_Msk (0x1UL << FLASH_OPTR_IWDG_STOP_Pos) /*!< 0x00020000 */ -#define FLASH_OPTR_IWDG_STOP FLASH_OPTR_IWDG_STOP_Msk /*!< Independent watchdog counter freeze in Stop mode */ -#define FLASH_OPTR_IWDG_STDBY_Pos (18U) -#define FLASH_OPTR_IWDG_STDBY_Msk (0x1UL << FLASH_OPTR_IWDG_STDBY_Pos) /*!< 0x00040000 */ -#define FLASH_OPTR_IWDG_STDBY FLASH_OPTR_IWDG_STDBY_Msk /*!< Independent watchdog counter freeze in Standby mode */ -#define FLASH_OPTR_WWDG_SW_Pos (19U) -#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ -#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk /*!< Window watchdog selection */ -#define FLASH_OPTR_SWAP_BANK_Pos (20U) -#define FLASH_OPTR_SWAP_BANK_Msk (0x1UL << FLASH_OPTR_SWAP_BANK_Pos) /*!< 0x00100000 */ -#define FLASH_OPTR_SWAP_BANK FLASH_OPTR_SWAP_BANK_Msk /*!< Swap banks */ -#define FLASH_OPTR_DUALBANK_Pos (21U) -#define FLASH_OPTR_DUALBANK_Msk (0x1UL << FLASH_OPTR_DUALBANK_Pos) /*!< 0x00200000 */ -#define FLASH_OPTR_DUALBANK FLASH_OPTR_DUALBANK_Msk /*!< Dual-bank on 1M and 512 Kbytes Flash memory devices */ -#define FLASH_OPTR_BKPRAM_ECC_Pos (22U) -#define FLASH_OPTR_BKPRAM_ECC_Msk (0x1UL << FLASH_OPTR_BKPRAM_ECC_Pos) /*!< 0x00400000 */ -#define FLASH_OPTR_BKPRAM_ECC FLASH_OPTR_BKPRAM_ECC_Msk /*!< Backup RAM ECC detection and correction enable */ -#define FLASH_OPTR_SRAM3_ECC_Pos (23U) -#define FLASH_OPTR_SRAM3_ECC_Msk (0x1UL << FLASH_OPTR_SRAM3_ECC_Pos) /*!< 0x00800000 */ -#define FLASH_OPTR_SRAM3_ECC FLASH_OPTR_SRAM3_ECC_Msk /*!< SRAM3 ECC detection and correction enable */ -#define FLASH_OPTR_SRAM2_ECC_Pos (24U) -#define FLASH_OPTR_SRAM2_ECC_Msk (0x1UL << FLASH_OPTR_SRAM2_ECC_Pos) /*!< 0x01000000 */ -#define FLASH_OPTR_SRAM2_ECC FLASH_OPTR_SRAM2_ECC_Msk /*!< SRAM2 ECC detection and correction enable*/ -#define FLASH_OPTR_SRAM2_RST_Pos (25U) -#define FLASH_OPTR_SRAM2_RST_Msk (0x1UL << FLASH_OPTR_SRAM2_RST_Pos) /*!< 0x02000000 */ -#define FLASH_OPTR_SRAM2_RST FLASH_OPTR_SRAM2_RST_Msk /*!< SRAM2 erase when system reset */ -#define FLASH_OPTR_nSWBOOT0_Pos (26U) -#define FLASH_OPTR_nSWBOOT0_Msk (0x1UL << FLASH_OPTR_nSWBOOT0_Pos) /*!< 0x04000000 */ -#define FLASH_OPTR_nSWBOOT0 FLASH_OPTR_nSWBOOT0_Msk /*!< Software BOOT0 */ -#define FLASH_OPTR_nBOOT0_Pos (27U) -#define FLASH_OPTR_nBOOT0_Msk (0x1UL << FLASH_OPTR_nBOOT0_Pos) /*!< 0x08000000 */ -#define FLASH_OPTR_nBOOT0 FLASH_OPTR_nBOOT0_Msk /*!< nBOOT0 option bit */ -#define FLASH_OPTR_PA15_PUPEN_Pos (28U) -#define FLASH_OPTR_PA15_PUPEN_Msk (0x1UL << FLASH_OPTR_PA15_PUPEN_Pos) /*!< 0x10000000 */ -#define FLASH_OPTR_PA15_PUPEN FLASH_OPTR_PA15_PUPEN_Msk /*!< PA15 pull-up enable */ -#define FLASH_OPTR_IO_VDD_HSLV_Pos (29U) -#define FLASH_OPTR_IO_VDD_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDD_HSLV_Pos) /*!< 0x20000000 */ -#define FLASH_OPTR_IO_VDD_HSLV FLASH_OPTR_IO_VDD_HSLV_Msk /*!< High speed IO at low voltage configuration bit */ -#define FLASH_OPTR_IO_VDDIO2_HSLV_Pos (30U) -#define FLASH_OPTR_IO_VDDIO2_HSLV_Msk (0x1UL << FLASH_OPTR_IO_VDDIO2_HSLV_Pos) /*!< 0x40000000 */ -#define FLASH_OPTR_IO_VDDIO2_HSLV FLASH_OPTR_IO_VDDIO2_HSLV_Msk /*!< High speed IO at low VDDIO2 voltage configuration bit */ -#define FLASH_OPTR_TZEN_Pos (31U) -#define FLASH_OPTR_TZEN_Msk (0x1UL << FLASH_OPTR_TZEN_Pos) /*!< 0x80000000 */ -#define FLASH_OPTR_TZEN FLASH_OPTR_TZEN_Msk /*!< Global TrustZone security enable */ - -/**************** Bits definition for FLASH_NSBOOTADD0R register ************/ -#define FLASH_NSBOOTADD0R_NSBOOTADD0_Pos (7U) -#define FLASH_NSBOOTADD0R_NSBOOTADD0_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD0R_NSBOOTADD0_Pos) /*!< 0xFFFFFF80 */ -#define FLASH_NSBOOTADD0R_NSBOOTADD0 FLASH_NSBOOTADD0R_NSBOOTADD0_Msk /*!< Non-secure boot address 0 */ - -/**************** Bits definition for FLASH_NSBOOTADD1R register ************/ -#define FLASH_NSBOOTADD1R_NSBOOTADD1_Pos (7U) -#define FLASH_NSBOOTADD1R_NSBOOTADD1_Msk (0x1FFFFFFUL << FLASH_NSBOOTADD1R_NSBOOTADD1_Pos) /*!< 0xFFFFFF80 */ -#define FLASH_NSBOOTADD1R_NSBOOTADD1 FLASH_NSBOOTADD1R_NSBOOTADD1_Msk /*!< Non-secure boot address 1 */ - -/**************** Bits definition for FLASH_SECBOOTADD0R register ***********/ -#define FLASH_SECBOOTADD0R_BOOT_LOCK_Pos (0U) -#define FLASH_SECBOOTADD0R_BOOT_LOCK_Msk (0x1UL << FLASH_SECBOOTADD0R_BOOT_LOCK_Pos) /*!< 0x00000001 */ -#define FLASH_SECBOOTADD0R_BOOT_LOCK FLASH_SECBOOTADD0R_BOOT_LOCK_Msk /*!< Boot Lock */ -#define FLASH_SECBOOTADD0R_SECBOOTADD0_Pos (7U) -#define FLASH_SECBOOTADD0R_SECBOOTADD0_Msk (0x1FFFFFFUL << FLASH_SECBOOTADD0R_SECBOOTADD0_Pos) /*!< 0xFFFFFF80 */ -#define FLASH_SECBOOTADD0R_SECBOOTADD0 FLASH_SECBOOTADD0R_SECBOOTADD0_Msk /*!< Secure boot address 0 */ - -/***************** Bits definition for FLASH_SECWM1R1 register **************/ -#define FLASH_SECWM1R1_SECWM1_PSTRT_Pos (0U) -#define FLASH_SECWM1R1_SECWM1_PSTRT_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PSTRT_Pos) /*!< 0x0000007F */ -#define FLASH_SECWM1R1_SECWM1_PSTRT FLASH_SECWM1R1_SECWM1_PSTRT_Msk /*!< Start page of first secure area */ -#define FLASH_SECWM1R1_SECWM1_PEND_Pos (16U) -#define FLASH_SECWM1R1_SECWM1_PEND_Msk (0x7FUL << FLASH_SECWM1R1_SECWM1_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_SECWM1R1_SECWM1_PEND FLASH_SECWM1R1_SECWM1_PEND_Msk /*!< End page of first secure area */ - -/***************** Bits definition for FLASH_SECWM1R2 register **************/ -#define FLASH_SECWM1R2_HDP1_PEND_Pos (16U) -#define FLASH_SECWM1R2_HDP1_PEND_Msk (0x7FUL << FLASH_SECWM1R2_HDP1_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_SECWM1R2_HDP1_PEND FLASH_SECWM1R2_HDP1_PEND_Msk /*!< End page of first hide protection area */ -#define FLASH_SECWM1R2_HDP1EN_Pos (31U) -#define FLASH_SECWM1R2_HDP1EN_Msk (0x1UL << FLASH_SECWM1R2_HDP1EN_Pos) /*!< 0x80000000 */ -#define FLASH_SECWM1R2_HDP1EN FLASH_SECWM1R2_HDP1EN_Msk /*!< Hide protection first area enable */ - -/****************** Bits definition for FLASH_WRP1AR register ***************/ -#define FLASH_WRP1AR_WRP1A_PSTRT_Pos (0U) -#define FLASH_WRP1AR_WRP1A_PSTRT_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PSTRT_Pos) /*!< 0x0000007F */ -#define FLASH_WRP1AR_WRP1A_PSTRT FLASH_WRP1AR_WRP1A_PSTRT_Msk /*!< Bank 1 WPR first area A start page */ -#define FLASH_WRP1AR_WRP1A_PEND_Pos (16U) -#define FLASH_WRP1AR_WRP1A_PEND_Msk (0x7FUL << FLASH_WRP1AR_WRP1A_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_WRP1AR_WRP1A_PEND FLASH_WRP1AR_WRP1A_PEND_Msk /*!< Bank 1 WPR first area A end page */ -#define FLASH_WRP1AR_UNLOCK_Pos (31U) -#define FLASH_WRP1AR_UNLOCK_Msk (0x1UL << FLASH_WRP1AR_UNLOCK_Pos) /*!< 0x80000000 */ -#define FLASH_WRP1AR_UNLOCK FLASH_WRP1AR_UNLOCK_Msk /*!< Bank 1 WPR first area A unlock */ - -/****************** Bits definition for FLASH_WRP1BR register ***************/ -#define FLASH_WRP1BR_WRP1B_PSTRT_Pos (0U) -#define FLASH_WRP1BR_WRP1B_PSTRT_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PSTRT_Pos) /*!< 0x0000007F */ -#define FLASH_WRP1BR_WRP1B_PSTRT FLASH_WRP1BR_WRP1B_PSTRT_Msk /*!< Bank 1 WPR second area B start page */ -#define FLASH_WRP1BR_WRP1B_PEND_Pos (16U) -#define FLASH_WRP1BR_WRP1B_PEND_Msk (0x7FUL << FLASH_WRP1BR_WRP1B_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_WRP1BR_WRP1B_PEND FLASH_WRP1BR_WRP1B_PEND_Msk /*!< Bank 1 WPR second area B end page */ -#define FLASH_WRP1BR_UNLOCK_Pos (31U) -#define FLASH_WRP1BR_UNLOCK_Msk (0x1UL << FLASH_WRP1BR_UNLOCK_Pos) /*!< 0x80000000 */ -#define FLASH_WRP1BR_UNLOCK FLASH_WRP1BR_UNLOCK_Msk /*!< Bank 1 WPR first area B unlock */ - -/***************** Bits definition for FLASH_SECWM2R1 register **************/ -#define FLASH_SECWM2R1_SECWM2_PSTRT_Pos (0U) -#define FLASH_SECWM2R1_SECWM2_PSTRT_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PSTRT_Pos) /*!< 0x0000007F */ -#define FLASH_SECWM2R1_SECWM2_PSTRT FLASH_SECWM2R1_SECWM2_PSTRT_Msk /*!< Start page of second secure area */ -#define FLASH_SECWM2R1_SECWM2_PEND_Pos (16U) -#define FLASH_SECWM2R1_SECWM2_PEND_Msk (0x7FUL << FLASH_SECWM2R1_SECWM2_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_SECWM2R1_SECWM2_PEND FLASH_SECWM2R1_SECWM2_PEND_Msk /*!< End page of second secure area */ - -/***************** Bits definition for FLASH_SECWM2R2 register **************/ -#define FLASH_SECWM2R2_HDP2_PEND_Pos (16U) -#define FLASH_SECWM2R2_HDP2_PEND_Msk (0x7FUL << FLASH_SECWM2R2_HDP2_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_SECWM2R2_HDP2_PEND FLASH_SECWM2R2_HDP2_PEND_Msk /*!< End page of hide protection second area */ -#define FLASH_SECWM2R2_HDP2EN_Pos (31U) -#define FLASH_SECWM2R2_HDP2EN_Msk (0x1UL << FLASH_SECWM2R2_HDP2EN_Pos) /*!< 0x80000000 */ -#define FLASH_SECWM2R2_HDP2EN FLASH_SECWM2R2_HDP2EN_Msk /*!< Hide protection second area enable */ - -/****************** Bits definition for FLASH_WRP2AR register ***************/ -#define FLASH_WRP2AR_WRP2A_PSTRT_Pos (0U) -#define FLASH_WRP2AR_WRP2A_PSTRT_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PSTRT_Pos) /*!< 0x0000007F */ -#define FLASH_WRP2AR_WRP2A_PSTRT FLASH_WRP2AR_WRP2A_PSTRT_Msk /*!< Bank 2 WPR first area A start page */ -#define FLASH_WRP2AR_WRP2A_PEND_Pos (16U) -#define FLASH_WRP2AR_WRP2A_PEND_Msk (0x7FUL << FLASH_WRP2AR_WRP2A_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_WRP2AR_WRP2A_PEND FLASH_WRP2AR_WRP2A_PEND_Msk /*!< Bank 2 WPR first area A end page */ -#define FLASH_WRP2AR_UNLOCK_Pos (31U) -#define FLASH_WRP2AR_UNLOCK_Msk (0x1UL << FLASH_WRP2AR_UNLOCK_Pos) /*!< 0x80000000 */ -#define FLASH_WRP2AR_UNLOCK FLASH_WRP2AR_UNLOCK_Msk /*!< Bank 2 WPR first area A unlock */ - -/****************** Bits definition for FLASH_WRP2BR register ***************/ -#define FLASH_WRP2BR_WRP2B_PSTRT_Pos (0U) -#define FLASH_WRP2BR_WRP2B_PSTRT_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PSTRT_Pos) /*!< 0x0000007F */ -#define FLASH_WRP2BR_WRP2B_PSTRT FLASH_WRP2BR_WRP2B_PSTRT_Msk /*!< Bank 2 WPR first area B start page */ -#define FLASH_WRP2BR_WRP2B_PEND_Pos (16U) -#define FLASH_WRP2BR_WRP2B_PEND_Msk (0x7FUL << FLASH_WRP2BR_WRP2B_PEND_Pos) /*!< 0x007F0000 */ -#define FLASH_WRP2BR_WRP2B_PEND FLASH_WRP2BR_WRP2B_PEND_Msk /*!< Bank 2 WPR first area B end page */ -#define FLASH_WRP2BR_UNLOCK_Pos (31U) -#define FLASH_WRP2BR_UNLOCK_Msk (0x1UL << FLASH_WRP2BR_UNLOCK_Pos) /*!< 0x80000000 */ -#define FLASH_WRP2BR_UNLOCK FLASH_WRP2BR_UNLOCK_Msk /*!< Bank 2 WPR first area B unlock */ - -/****************** Bits definition for FLASH_SECHDPCR register ***********/ -#define FLASH_SECHDPCR_HDP1_ACCDIS_Pos (0U) -#define FLASH_SECHDPCR_HDP1_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP1_ACCDIS_Pos) /*!< 0x00000001 */ -#define FLASH_SECHDPCR_HDP1_ACCDIS FLASH_SECHDPCR_HDP1_ACCDIS_Msk /*!< HDP1 area access disable */ -#define FLASH_SECHDPCR_HDP2_ACCDIS_Pos (1U) -#define FLASH_SECHDPCR_HDP2_ACCDIS_Msk (0x1UL << FLASH_SECHDPCR_HDP2_ACCDIS_Pos) /*!< 0x00000002 */ -#define FLASH_SECHDPCR_HDP2_ACCDIS FLASH_SECHDPCR_HDP2_ACCDIS_Msk /*!< HDP2 area access disable */ - -/****************** Bits definition for FLASH_PRIVCFGR register ***********/ -#define FLASH_PRIVCFGR_SPRIV_Pos (0U) -#define FLASH_PRIVCFGR_SPRIV_Msk (0x1UL << FLASH_PRIVCFGR_SPRIV_Pos) /*!< 0x00000001 */ -#define FLASH_PRIVCFGR_SPRIV FLASH_PRIVCFGR_SPRIV_Msk /*!< Privilege protection for secure registers */ -#define FLASH_PRIVCFGR_NSPRIV_Pos (1U) -#define FLASH_PRIVCFGR_NSPRIV_Msk (0x1UL << FLASH_PRIVCFGR_NSPRIV_Pos) /*!< 0x00000002 */ -#define FLASH_PRIVCFGR_NSPRIV FLASH_PRIVCFGR_NSPRIV_Msk /*!< Privilege protection for non-secure registers */ - -/******************************************************************************/ -/* */ -/* Filter Mathematical ACcelerator unit (FMAC) */ -/* */ -/******************************************************************************/ -/***************** Bit definition for FMAC_X1BUFCFG register ****************/ -#define FMAC_X1BUFCFG_X1_BASE_Pos (0U) -#define FMAC_X1BUFCFG_X1_BASE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BASE_Pos) /*!< 0x000000FF */ -#define FMAC_X1BUFCFG_X1_BASE FMAC_X1BUFCFG_X1_BASE_Msk /*!< Base address of X1 buffer */ -#define FMAC_X1BUFCFG_X1_BUF_SIZE_Pos (8U) -#define FMAC_X1BUFCFG_X1_BUF_SIZE_Msk (0xFFUL << FMAC_X1BUFCFG_X1_BUF_SIZE_Pos) /*!< 0x0000FF00 */ -#define FMAC_X1BUFCFG_X1_BUF_SIZE FMAC_X1BUFCFG_X1_BUF_SIZE_Msk /*!< Allocated size of X1 buffer in 16-bit words */ -#define FMAC_X1BUFCFG_FULL_WM_Pos (24U) -#define FMAC_X1BUFCFG_FULL_WM_Msk (0x3UL << FMAC_X1BUFCFG_FULL_WM_Pos) /*!< 0x03000000 */ -#define FMAC_X1BUFCFG_FULL_WM FMAC_X1BUFCFG_FULL_WM_Msk /*!< Watermark for buffer full flag */ - -/***************** Bit definition for FMAC_X2BUFCFG register ****************/ -#define FMAC_X2BUFCFG_X2_BASE_Pos (0U) -#define FMAC_X2BUFCFG_X2_BASE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BASE_Pos) /*!< 0x000000FF */ -#define FMAC_X2BUFCFG_X2_BASE FMAC_X2BUFCFG_X2_BASE_Msk /*!< Base address of X2 buffer */ -#define FMAC_X2BUFCFG_X2_BUF_SIZE_Pos (8U) -#define FMAC_X2BUFCFG_X2_BUF_SIZE_Msk (0xFFUL << FMAC_X2BUFCFG_X2_BUF_SIZE_Pos) /*!< 0x0000FF00 */ -#define FMAC_X2BUFCFG_X2_BUF_SIZE FMAC_X2BUFCFG_X2_BUF_SIZE_Msk /*!< Size of X2 buffer in 16-bit words */ - -/***************** Bit definition for FMAC_YBUFCFG register *****************/ -#define FMAC_YBUFCFG_Y_BASE_Pos (0U) -#define FMAC_YBUFCFG_Y_BASE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BASE_Pos) /*!< 0x000000FF */ -#define FMAC_YBUFCFG_Y_BASE FMAC_YBUFCFG_Y_BASE_Msk /*!< Base address of Y buffer */ -#define FMAC_YBUFCFG_Y_BUF_SIZE_Pos (8U) -#define FMAC_YBUFCFG_Y_BUF_SIZE_Msk (0xFFUL << FMAC_YBUFCFG_Y_BUF_SIZE_Pos) /*!< 0x0000FF00 */ -#define FMAC_YBUFCFG_Y_BUF_SIZE FMAC_YBUFCFG_Y_BUF_SIZE_Msk /*!< Size of Y buffer in 16-bit words */ -#define FMAC_YBUFCFG_EMPTY_WM_Pos (24U) -#define FMAC_YBUFCFG_EMPTY_WM_Msk (0x3UL << FMAC_YBUFCFG_EMPTY_WM_Pos) /*!< 0x03000000 */ -#define FMAC_YBUFCFG_EMPTY_WM FMAC_YBUFCFG_EMPTY_WM_Msk /*!< Watermark for buffer empty flag */ - -/****************** Bit definition for FMAC_PARAM register ******************/ -#define FMAC_PARAM_P_Pos (0U) -#define FMAC_PARAM_P_Msk (0xFFUL << FMAC_PARAM_P_Pos) /*!< 0x000000FF */ -#define FMAC_PARAM_P FMAC_PARAM_P_Msk /*!< Input parameter P */ -#define FMAC_PARAM_Q_Pos (8U) -#define FMAC_PARAM_Q_Msk (0xFFUL << FMAC_PARAM_Q_Pos) /*!< 0x0000FF00 */ -#define FMAC_PARAM_Q FMAC_PARAM_Q_Msk /*!< Input parameter Q */ -#define FMAC_PARAM_R_Pos (16U) -#define FMAC_PARAM_R_Msk (0xFFUL << FMAC_PARAM_R_Pos) /*!< 0x00FF0000 */ -#define FMAC_PARAM_R FMAC_PARAM_R_Msk /*!< Input parameter R */ -#define FMAC_PARAM_FUNC_Pos (24U) -#define FMAC_PARAM_FUNC_Msk (0x7FUL << FMAC_PARAM_FUNC_Pos) /*!< 0x7F000000 */ -#define FMAC_PARAM_FUNC FMAC_PARAM_FUNC_Msk /*!< Function */ -#define FMAC_PARAM_FUNC_0 (0x1UL << FMAC_PARAM_FUNC_Pos) /*!< 0x01000000 */ -#define FMAC_PARAM_FUNC_1 (0x2UL << FMAC_PARAM_FUNC_Pos) /*!< 0x02000000 */ -#define FMAC_PARAM_FUNC_2 (0x4UL << FMAC_PARAM_FUNC_Pos) /*!< 0x04000000 */ -#define FMAC_PARAM_FUNC_3 (0x8UL << FMAC_PARAM_FUNC_Pos) /*!< 0x08000000 */ -#define FMAC_PARAM_FUNC_4 (0x10UL << FMAC_PARAM_FUNC_Pos) /*!< 0x10000000 */ -#define FMAC_PARAM_FUNC_5 (0x20UL << FMAC_PARAM_FUNC_Pos) /*!< 0x20000000 */ -#define FMAC_PARAM_FUNC_6 (0x40UL << FMAC_PARAM_FUNC_Pos) /*!< 0x40000000 */ -#define FMAC_PARAM_START_Pos (31U) -#define FMAC_PARAM_START_Msk (0x1UL << FMAC_PARAM_START_Pos) /*!< 0x80000000 */ -#define FMAC_PARAM_START FMAC_PARAM_START_Msk /*!< Enable execution */ - -/******************** Bit definition for FMAC_CR register *******************/ -#define FMAC_CR_RIEN_Pos (0U) -#define FMAC_CR_RIEN_Msk (0x1UL << FMAC_CR_RIEN_Pos) /*!< 0x00000001 */ -#define FMAC_CR_RIEN FMAC_CR_RIEN_Msk /*!< Enable read interrupt */ -#define FMAC_CR_WIEN_Pos (1U) -#define FMAC_CR_WIEN_Msk (0x1UL << FMAC_CR_WIEN_Pos) /*!< 0x00000002 */ -#define FMAC_CR_WIEN FMAC_CR_WIEN_Msk /*!< Enable write interrupt */ -#define FMAC_CR_OVFLIEN_Pos (2U) -#define FMAC_CR_OVFLIEN_Msk (0x1UL << FMAC_CR_OVFLIEN_Pos) /*!< 0x00000004 */ -#define FMAC_CR_OVFLIEN FMAC_CR_OVFLIEN_Msk /*!< Enable overflow error interrupts */ -#define FMAC_CR_UNFLIEN_Pos (3U) -#define FMAC_CR_UNFLIEN_Msk (0x1UL << FMAC_CR_UNFLIEN_Pos) /*!< 0x00000008 */ -#define FMAC_CR_UNFLIEN FMAC_CR_UNFLIEN_Msk /*!< Enable underflow error interrupts */ -#define FMAC_CR_SATIEN_Pos (4U) -#define FMAC_CR_SATIEN_Msk (0x1UL << FMAC_CR_SATIEN_Pos) /*!< 0x00000010 */ -#define FMAC_CR_SATIEN FMAC_CR_SATIEN_Msk /*!< Enable saturation error interrupts */ -#define FMAC_CR_DMAREN_Pos (8U) -#define FMAC_CR_DMAREN_Msk (0x1UL << FMAC_CR_DMAREN_Pos) /*!< 0x00000100 */ -#define FMAC_CR_DMAREN FMAC_CR_DMAREN_Msk /*!< Enable DMA read channel requests */ -#define FMAC_CR_DMAWEN_Pos (9U) -#define FMAC_CR_DMAWEN_Msk (0x1UL << FMAC_CR_DMAWEN_Pos) /*!< 0x00000200 */ -#define FMAC_CR_DMAWEN FMAC_CR_DMAWEN_Msk /*!< Enable DMA write channel requests */ -#define FMAC_CR_CLIPEN_Pos (15U) -#define FMAC_CR_CLIPEN_Msk (0x1UL << FMAC_CR_CLIPEN_Pos) /*!< 0x00008000 */ -#define FMAC_CR_CLIPEN FMAC_CR_CLIPEN_Msk /*!< Enable clipping */ -#define FMAC_CR_RESET_Pos (16U) -#define FMAC_CR_RESET_Msk (0x1UL << FMAC_CR_RESET_Pos) /*!< 0x00010000 */ -#define FMAC_CR_RESET FMAC_CR_RESET_Msk /*!< Reset filter mathematical accelerator unit */ - -/******************* Bit definition for FMAC_SR register ********************/ -#define FMAC_SR_YEMPTY_Pos (0U) -#define FMAC_SR_YEMPTY_Msk (0x1UL << FMAC_SR_YEMPTY_Pos) /*!< 0x00000001 */ -#define FMAC_SR_YEMPTY FMAC_SR_YEMPTY_Msk /*!< Y buffer empty flag */ -#define FMAC_SR_X1FULL_Pos (1U) -#define FMAC_SR_X1FULL_Msk (0x1UL << FMAC_SR_X1FULL_Pos) /*!< 0x00000002 */ -#define FMAC_SR_X1FULL FMAC_SR_X1FULL_Msk /*!< X1 buffer full flag */ -#define FMAC_SR_OVFL_Pos (8U) -#define FMAC_SR_OVFL_Msk (0x1UL << FMAC_SR_OVFL_Pos) /*!< 0x00000100 */ -#define FMAC_SR_OVFL FMAC_SR_OVFL_Msk /*!< Overflow error flag */ -#define FMAC_SR_UNFL_Pos (9U) -#define FMAC_SR_UNFL_Msk (0x1UL << FMAC_SR_UNFL_Pos) /*!< 0x00000200 */ -#define FMAC_SR_UNFL FMAC_SR_UNFL_Msk /*!< Underflow error flag */ -#define FMAC_SR_SAT_Pos (10U) -#define FMAC_SR_SAT_Msk (0x1UL << FMAC_SR_SAT_Pos) /*!< 0x00000400 */ -#define FMAC_SR_SAT FMAC_SR_SAT_Msk /*!< Saturation error flag */ - -/****************** Bit definition for FMAC_WDATA register ******************/ -#define FMAC_WDATA_WDATA_Pos (0U) -#define FMAC_WDATA_WDATA_Msk (0xFFFFUL << FMAC_WDATA_WDATA_Pos) /*!< 0x0000FFFF */ -#define FMAC_WDATA_WDATA FMAC_WDATA_WDATA_Msk /*!< Write data */ - -/****************** Bit definition for FMACX_RDATA register *****************/ -#define FMAC_RDATA_RDATA_Pos (0U) -#define FMAC_RDATA_RDATA_Msk (0xFFFFUL << FMAC_RDATA_RDATA_Pos) /*!< 0x0000FFFF */ -#define FMAC_RDATA_RDATA FMAC_RDATA_RDATA_Msk /*!< Read data */ - -/******************************************************************************/ -/* */ -/* Flexible Memory Controller */ -/* */ -/******************************************************************************/ -/****************** Bit definition for FMC_BCR1 register *******************/ -#define FMC_BCR1_CCLKEN_Pos (20U) -#define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */ -#define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*! */ - -/******************** Bits definition for RTC_ALRMAR register ***************/ -#define RTC_ALRMAR_SU_Pos (0U) -#define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */ -#define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk -#define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */ -#define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */ -#define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */ -#define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMAR_ST_Pos (4U) -#define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */ -#define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk -#define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */ -#define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */ -#define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMAR_MSK1_Pos (7U) -#define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */ -#define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk -#define RTC_ALRMAR_MNU_Pos (8U) -#define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */ -#define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk -#define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */ -#define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */ -#define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */ -#define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMAR_MNT_Pos (12U) -#define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */ -#define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk -#define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */ -#define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */ -#define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMAR_MSK2_Pos (15U) -#define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */ -#define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk -#define RTC_ALRMAR_HU_Pos (16U) -#define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */ -#define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk -#define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */ -#define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */ -#define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */ -#define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMAR_HT_Pos (20U) -#define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */ -#define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk -#define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */ -#define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMAR_PM_Pos (22U) -#define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */ -#define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk -#define RTC_ALRMAR_MSK3_Pos (23U) -#define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */ -#define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk -#define RTC_ALRMAR_DU_Pos (24U) -#define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk -#define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */ -#define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */ -#define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */ -#define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMAR_DT_Pos (28U) -#define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */ -#define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk -#define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */ -#define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMAR_WDSEL_Pos (30U) -#define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */ -#define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk -#define RTC_ALRMAR_MSK4_Pos (31U) -#define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */ -#define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk - -/******************** Bits definition for RTC_ALRMASSR register *************/ -#define RTC_ALRMASSR_SS_Pos (0U) -#define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */ -#define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk -#define RTC_ALRMASSR_MASKSS_Pos (24U) -#define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk -#define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */ -#define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */ -#define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */ -#define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMASSR_SSCLR_Pos (31U) -#define RTC_ALRMASSR_SSCLR_Msk (0x1UL << RTC_ALRMASSR_SSCLR_Pos) /*!< 0x80000000 */ -#define RTC_ALRMASSR_SSCLR RTC_ALRMASSR_SSCLR_Msk - -/******************** Bits definition for RTC_ALRMBR register ***************/ -#define RTC_ALRMBR_SU_Pos (0U) -#define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */ -#define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk -#define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */ -#define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */ -#define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */ -#define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */ -#define RTC_ALRMBR_ST_Pos (4U) -#define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */ -#define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk -#define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */ -#define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */ -#define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */ -#define RTC_ALRMBR_MSK1_Pos (7U) -#define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */ -#define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk -#define RTC_ALRMBR_MNU_Pos (8U) -#define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */ -#define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk -#define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */ -#define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */ -#define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */ -#define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */ -#define RTC_ALRMBR_MNT_Pos (12U) -#define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */ -#define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk -#define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */ -#define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */ -#define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */ -#define RTC_ALRMBR_MSK2_Pos (15U) -#define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */ -#define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk -#define RTC_ALRMBR_HU_Pos (16U) -#define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */ -#define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk -#define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */ -#define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */ -#define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */ -#define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */ -#define RTC_ALRMBR_HT_Pos (20U) -#define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */ -#define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk -#define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */ -#define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */ -#define RTC_ALRMBR_PM_Pos (22U) -#define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */ -#define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk -#define RTC_ALRMBR_MSK3_Pos (23U) -#define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */ -#define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk -#define RTC_ALRMBR_DU_Pos (24U) -#define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk -#define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */ -#define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */ -#define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */ -#define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBR_DT_Pos (28U) -#define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */ -#define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk -#define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */ -#define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */ -#define RTC_ALRMBR_WDSEL_Pos (30U) -#define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */ -#define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk -#define RTC_ALRMBR_MSK4_Pos (31U) -#define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */ -#define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk - -/******************** Bits definition for RTC_ALRMBSSR register *************/ -#define RTC_ALRMBSSR_SS_Pos (0U) -#define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */ -#define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk -#define RTC_ALRMBSSR_MASKSS_Pos (24U) -#define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */ -#define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk -#define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */ -#define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */ -#define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */ -#define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */ -#define RTC_ALRMBSSR_SSCLR_Pos (31U) -#define RTC_ALRMBSSR_SSCLR_Msk (0x1UL << RTC_ALRMBSSR_SSCLR_Pos) /*!< 0x80000000 */ -#define RTC_ALRMBSSR_SSCLR RTC_ALRMBSSR_SSCLR_Msk - -/******************** Bits definition for RTC_SR register *******************/ -#define RTC_SR_ALRAF_Pos (0U) -#define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */ -#define RTC_SR_ALRAF RTC_SR_ALRAF_Msk -#define RTC_SR_ALRBF_Pos (1U) -#define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */ -#define RTC_SR_ALRBF RTC_SR_ALRBF_Msk -#define RTC_SR_WUTF_Pos (2U) -#define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */ -#define RTC_SR_WUTF RTC_SR_WUTF_Msk -#define RTC_SR_TSF_Pos (3U) -#define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */ -#define RTC_SR_TSF RTC_SR_TSF_Msk -#define RTC_SR_TSOVF_Pos (4U) -#define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */ -#define RTC_SR_TSOVF RTC_SR_TSOVF_Msk -#define RTC_SR_ITSF_Pos (5U) -#define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */ -#define RTC_SR_ITSF RTC_SR_ITSF_Msk -#define RTC_SR_SSRUF_Pos (6U) -#define RTC_SR_SSRUF_Msk (0x1UL << RTC_SR_SSRUF_Pos) /*!< 0x00000040 */ -#define RTC_SR_SSRUF RTC_SR_SSRUF_Msk - -/******************** Bits definition for RTC_MISR register *****************/ -#define RTC_MISR_ALRAMF_Pos (0U) -#define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */ -#define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk -#define RTC_MISR_ALRBMF_Pos (1U) -#define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */ -#define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk -#define RTC_MISR_WUTMF_Pos (2U) -#define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */ -#define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk -#define RTC_MISR_TSMF_Pos (3U) -#define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */ -#define RTC_MISR_TSMF RTC_MISR_TSMF_Msk -#define RTC_MISR_TSOVMF_Pos (4U) -#define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */ -#define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk -#define RTC_MISR_ITSMF_Pos (5U) -#define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */ -#define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk -#define RTC_MISR_SSRUMF_Pos (6U) -#define RTC_MISR_SSRUMF_Msk (0x1UL << RTC_MISR_SSRUMF_Pos) /*!< 0x00000040 */ -#define RTC_MISR_SSRUMF RTC_MISR_SSRUMF_Msk - -/******************** Bits definition for RTC_SMISR register *****************/ -#define RTC_SMISR_ALRAMF_Pos (0U) -#define RTC_SMISR_ALRAMF_Msk (0x1UL << RTC_SMISR_ALRAMF_Pos) /*!< 0x00000001 */ -#define RTC_SMISR_ALRAMF RTC_SMISR_ALRAMF_Msk -#define RTC_SMISR_ALRBMF_Pos (1U) -#define RTC_SMISR_ALRBMF_Msk (0x1UL << RTC_SMISR_ALRBMF_Pos) /*!< 0x00000002 */ -#define RTC_SMISR_ALRBMF RTC_SMISR_ALRBMF_Msk -#define RTC_SMISR_WUTMF_Pos (2U) -#define RTC_SMISR_WUTMF_Msk (0x1UL << RTC_SMISR_WUTMF_Pos) /*!< 0x00000004 */ -#define RTC_SMISR_WUTMF RTC_SMISR_WUTMF_Msk -#define RTC_SMISR_TSMF_Pos (3U) -#define RTC_SMISR_TSMF_Msk (0x1UL << RTC_SMISR_TSMF_Pos) /*!< 0x00000008 */ -#define RTC_SMISR_TSMF RTC_SMISR_TSMF_Msk -#define RTC_SMISR_TSOVMF_Pos (4U) -#define RTC_SMISR_TSOVMF_Msk (0x1UL << RTC_SMISR_TSOVMF_Pos) /*!< 0x00000010 */ -#define RTC_SMISR_TSOVMF RTC_SMISR_TSOVMF_Msk -#define RTC_SMISR_ITSMF_Pos (5U) -#define RTC_SMISR_ITSMF_Msk (0x1UL << RTC_SMISR_ITSMF_Pos) /*!< 0x00000020 */ -#define RTC_SMISR_ITSMF RTC_SMISR_ITSMF_Msk -#define RTC_SMISR_SSRUMF_Pos (6U) -#define RTC_SMISR_SSRUMF_Msk (0x1UL << RTC_SMISR_SSRUMF_Pos) /*!< 0x00000040 */ -#define RTC_SMISR_SSRUMF RTC_SMISR_SSRUMF_Msk - -/******************** Bits definition for RTC_SCR register ******************/ -#define RTC_SCR_CALRAF_Pos (0U) -#define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */ -#define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk -#define RTC_SCR_CALRBF_Pos (1U) -#define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */ -#define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk -#define RTC_SCR_CWUTF_Pos (2U) -#define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */ -#define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk -#define RTC_SCR_CTSF_Pos (3U) -#define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */ -#define RTC_SCR_CTSF RTC_SCR_CTSF_Msk -#define RTC_SCR_CTSOVF_Pos (4U) -#define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */ -#define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk -#define RTC_SCR_CITSF_Pos (5U) -#define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */ -#define RTC_SCR_CITSF RTC_SCR_CITSF_Msk -#define RTC_SCR_CSSRUF_Pos (6U) -#define RTC_SCR_CSSRUF_Msk (0x1UL << RTC_SCR_CSSRUF_Pos) /*!< 0x00000040 */ -#define RTC_SCR_CSSRUF RTC_SCR_CSSRUF_Msk - -/******************** Bits definition for RTC_ALRABINR register ******************/ -#define RTC_ALRABINR_SS_Pos (0U) -#define RTC_ALRABINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRABINR_SS_Pos) /*!< 0xFFFFFFFF */ -#define RTC_ALRABINR_SS RTC_ALRABINR_SS_Msk - -/******************** Bits definition for RTC_ALRBBINR register ******************/ -#define RTC_ALRBBINR_SS_Pos (0U) -#define RTC_ALRBBINR_SS_Msk (0xFFFFFFFFUL << RTC_ALRBBINR_SS_Pos) /*!< 0xFFFFFFFF */ -#define RTC_ALRBBINR_SS RTC_ALRBBINR_SS_Msk - -/******************************************************************************/ -/* */ -/* Tamper and backup register (TAMP) */ -/* */ -/******************************************************************************/ -/******************** Bits definition for TAMP_CR1 register *****************/ -#define TAMP_CR1_TAMP1E_Pos (0U) -#define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */ -#define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk -#define TAMP_CR1_TAMP2E_Pos (1U) -#define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */ -#define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk -#define TAMP_CR1_TAMP3E_Pos (2U) -#define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */ -#define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk -#define TAMP_CR1_TAMP4E_Pos (3U) -#define TAMP_CR1_TAMP4E_Msk (0x1UL << TAMP_CR1_TAMP4E_Pos) /*!< 0x00000008 */ -#define TAMP_CR1_TAMP4E TAMP_CR1_TAMP4E_Msk -#define TAMP_CR1_TAMP5E_Pos (4U) -#define TAMP_CR1_TAMP5E_Msk (0x1UL << TAMP_CR1_TAMP5E_Pos) /*!< 0x00000010 */ -#define TAMP_CR1_TAMP5E TAMP_CR1_TAMP5E_Msk -#define TAMP_CR1_TAMP6E_Pos (5U) -#define TAMP_CR1_TAMP6E_Msk (0x1UL << TAMP_CR1_TAMP6E_Pos) /*!< 0x00000020 */ -#define TAMP_CR1_TAMP6E TAMP_CR1_TAMP6E_Msk -#define TAMP_CR1_TAMP7E_Pos (6U) -#define TAMP_CR1_TAMP7E_Msk (0x1UL << TAMP_CR1_TAMP7E_Pos) /*!< 0x00000040 */ -#define TAMP_CR1_TAMP7E TAMP_CR1_TAMP7E_Msk -#define TAMP_CR1_TAMP8E_Pos (7U) -#define TAMP_CR1_TAMP8E_Msk (0x1UL << TAMP_CR1_TAMP8E_Pos) /*!< 0x00000080 */ -#define TAMP_CR1_TAMP8E TAMP_CR1_TAMP8E_Msk -#define TAMP_CR1_ITAMP1E_Pos (16U) -#define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */ -#define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk -#define TAMP_CR1_ITAMP2E_Pos (17U) -#define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00040000 */ -#define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk -#define TAMP_CR1_ITAMP3E_Pos (18U) -#define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */ -#define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk -#define TAMP_CR1_ITAMP5E_Pos (20U) -#define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */ -#define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk -#define TAMP_CR1_ITAMP6E_Pos (21U) -#define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */ -#define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk -#define TAMP_CR1_ITAMP7E_Pos (22U) -#define TAMP_CR1_ITAMP7E_Msk (0x1UL << TAMP_CR1_ITAMP7E_Pos) /*!< 0x00400000 */ -#define TAMP_CR1_ITAMP7E TAMP_CR1_ITAMP7E_Msk -#define TAMP_CR1_ITAMP8E_Pos (23U) -#define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */ -#define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk -#define TAMP_CR1_ITAMP9E_Pos (24U) -#define TAMP_CR1_ITAMP9E_Msk (0x1UL << TAMP_CR1_ITAMP9E_Pos) /*!< 0x01000000 */ -#define TAMP_CR1_ITAMP9E TAMP_CR1_ITAMP9E_Msk -#define TAMP_CR1_ITAMP11E_Pos (26U) -#define TAMP_CR1_ITAMP11E_Msk (0x1UL << TAMP_CR1_ITAMP11E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP11E TAMP_CR1_ITAMP11E_Msk -#define TAMP_CR1_ITAMP12E_Pos (27U) -#define TAMP_CR1_ITAMP12E_Msk (0x1UL << TAMP_CR1_ITAMP12E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP12E TAMP_CR1_ITAMP12E_Msk -#define TAMP_CR1_ITAMP13E_Pos (28U) -#define TAMP_CR1_ITAMP13E_Msk (0x1UL << TAMP_CR1_ITAMP13E_Pos) /*!< 0x04000000 */ -#define TAMP_CR1_ITAMP13E TAMP_CR1_ITAMP13E_Msk - -/******************** Bits definition for TAMP_CR2 register *****************/ -#define TAMP_CR2_TAMP1NOERASE_Pos (0U) -#define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */ -#define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk -#define TAMP_CR2_TAMP2NOERASE_Pos (1U) -#define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */ -#define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk -#define TAMP_CR2_TAMP3NOERASE_Pos (2U) -#define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */ -#define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk -#define TAMP_CR2_TAMP4NOERASE_Pos (3U) -#define TAMP_CR2_TAMP4NOERASE_Msk (0x1UL << TAMP_CR2_TAMP4NOERASE_Pos) /*!< 0x00000008 */ -#define TAMP_CR2_TAMP4NOERASE TAMP_CR2_TAMP4NOERASE_Msk -#define TAMP_CR2_TAMP5NOERASE_Pos (4U) -#define TAMP_CR2_TAMP5NOERASE_Msk (0x1UL << TAMP_CR2_TAMP5NOERASE_Pos) /*!< 0x00000010 */ -#define TAMP_CR2_TAMP5NOERASE TAMP_CR2_TAMP5NOERASE_Msk -#define TAMP_CR2_TAMP6NOERASE_Pos (5U) -#define TAMP_CR2_TAMP6NOERASE_Msk (0x1UL << TAMP_CR2_TAMP6NOERASE_Pos) /*!< 0x00000020 */ -#define TAMP_CR2_TAMP6NOERASE TAMP_CR2_TAMP6NOERASE_Msk -#define TAMP_CR2_TAMP7NOERASE_Pos (6U) -#define TAMP_CR2_TAMP7NOERASE_Msk (0x1UL << TAMP_CR2_TAMP7NOERASE_Pos) /*!< 0x00000040 */ -#define TAMP_CR2_TAMP7NOERASE TAMP_CR2_TAMP7NOERASE_Msk -#define TAMP_CR2_TAMP8NOERASE_Pos (7U) -#define TAMP_CR2_TAMP8NOERASE_Msk (0x1UL << TAMP_CR2_TAMP8NOERASE_Pos) /*!< 0x00000080 */ -#define TAMP_CR2_TAMP8NOERASE TAMP_CR2_TAMP8NOERASE_Msk -#define TAMP_CR2_TAMP1MSK_Pos (16U) -#define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */ -#define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk -#define TAMP_CR2_TAMP2MSK_Pos (17U) -#define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */ -#define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk -#define TAMP_CR2_TAMP3MSK_Pos (18U) -#define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */ -#define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk -#define TAMP_CR2_BKBLOCK_Pos (22U) -#define TAMP_CR2_BKBLOCK_Msk (0x1UL << TAMP_CR2_BKBLOCK_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_BKBLOCK TAMP_CR2_BKBLOCK_Msk -#define TAMP_CR2_BKERASE_Pos (23U) -#define TAMP_CR2_BKERASE_Msk (0x1UL << TAMP_CR2_BKERASE_Pos) /*!< 0x00800000 */ -#define TAMP_CR2_BKERASE TAMP_CR2_BKERASE_Msk -#define TAMP_CR2_TAMP1TRG_Pos (24U) -#define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */ -#define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk -#define TAMP_CR2_TAMP2TRG_Pos (25U) -#define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk -#define TAMP_CR2_TAMP3TRG_Pos (26U) -#define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk -#define TAMP_CR2_TAMP4TRG_Pos (27U) -#define TAMP_CR2_TAMP4TRG_Msk (0x1UL << TAMP_CR2_TAMP4TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP4TRG TAMP_CR2_TAMP4TRG_Msk -#define TAMP_CR2_TAMP5TRG_Pos (28U) -#define TAMP_CR2_TAMP5TRG_Msk (0x1UL << TAMP_CR2_TAMP5TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP5TRG TAMP_CR2_TAMP5TRG_Msk -#define TAMP_CR2_TAMP6TRG_Pos (29U) -#define TAMP_CR2_TAMP6TRG_Msk (0x1UL << TAMP_CR2_TAMP6TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP6TRG TAMP_CR2_TAMP6TRG_Msk -#define TAMP_CR2_TAMP7TRG_Pos (30U) -#define TAMP_CR2_TAMP7TRG_Msk (0x1UL << TAMP_CR2_TAMP7TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP7TRG TAMP_CR2_TAMP7TRG_Msk -#define TAMP_CR2_TAMP8TRG_Pos (31U) -#define TAMP_CR2_TAMP8TRG_Msk (0x1UL << TAMP_CR2_TAMP8TRG_Pos) /*!< 0x02000000 */ -#define TAMP_CR2_TAMP8TRG TAMP_CR2_TAMP8TRG_Msk - -/******************** Bits definition for TAMP_CR3 register *****************/ -#define TAMP_CR3_ITAMP1NOER_Pos (0U) -#define TAMP_CR3_ITAMP1NOER_Msk (0x1UL << TAMP_CR3_ITAMP1NOER_Pos) /*!< 0x00000001 */ -#define TAMP_CR3_ITAMP1NOER TAMP_CR3_ITAMP1NOER_Msk -#define TAMP_CR3_ITAMP2NOER_Pos (1U) -#define TAMP_CR3_ITAMP2NOER_Msk (0x1UL << TAMP_CR3_ITAMP2NOER_Pos) /*!< 0x00000002 */ -#define TAMP_CR3_ITAMP2NOER TAMP_CR3_ITAMP2NOER_Msk -#define TAMP_CR3_ITAMP3NOER_Pos (2U) -#define TAMP_CR3_ITAMP3NOER_Msk (0x1UL << TAMP_CR3_ITAMP3NOER_Pos) /*!< 0x00000004 */ -#define TAMP_CR3_ITAMP3NOER TAMP_CR3_ITAMP3NOER_Msk -#define TAMP_CR3_ITAMP5NOER_Pos (4U) -#define TAMP_CR3_ITAMP5NOER_Msk (0x1UL << TAMP_CR3_ITAMP5NOER_Pos) /*!< 0x00000010 */ -#define TAMP_CR3_ITAMP5NOER TAMP_CR3_ITAMP5NOER_Msk -#define TAMP_CR3_ITAMP6NOER_Pos (5U) -#define TAMP_CR3_ITAMP6NOER_Msk (0x1UL << TAMP_CR3_ITAMP6NOER_Pos) /*!< 0x00000020 */ -#define TAMP_CR3_ITAMP6NOER TAMP_CR3_ITAMP6NOER_Msk -#define TAMP_CR3_ITAMP7NOER_Pos (6U) -#define TAMP_CR3_ITAMP7NOER_Msk (0x1UL << TAMP_CR3_ITAMP7NOER) -#define TAMP_CR3_ITAMP7NOER TAMP_CR3_ITAMP7NOER_Msk -#define TAMP_CR3_ITAMP8NOER_Pos (7U) -#define TAMP_CR3_ITAMP8NOER_Msk (0x1UL << TAMP_CR3_ITAMP8NOER_Pos) /*!< 0x00000040 */ -#define TAMP_CR3_ITAMP8NOER TAMP_CR3_ITAMP8NOER_Msk -#define TAMP_CR3_ITAMP9NOER_Pos (8U) -#define TAMP_CR3_ITAMP9NOER_Msk (0x1UL << TAMP_CR3_ITAMP9NOER_Pos) /*!< 0x00000100 */ -#define TAMP_CR3_ITAMP9NOER TAMP_CR3_ITAMP9NOER_Msk -#define TAMP_CR3_ITAMP11NOER_Pos (10U) -#define TAMP_CR3_ITAMP11NOER_Msk (0x1UL << TAMP_CR3_ITAMP11NOER_Pos) /*!< 0x00000800 */ -#define TAMP_CR3_ITAMP11NOER TAMP_CR3_ITAMP11NOER_Msk -#define TAMP_CR3_ITAMP12NOER_Pos (11U) -#define TAMP_CR3_ITAMP12NOER_Msk (0x1UL << TAMP_CR3_ITAMP12NOER_Pos) /*!< 0x00000800 */ -#define TAMP_CR3_ITAMP12NOER TAMP_CR3_ITAMP12NOER_Msk -#define TAMP_CR3_ITAMP13NOER_Pos (12U) -#define TAMP_CR3_ITAMP13NOER_Msk (0x1UL << TAMP_CR3_ITAMP13NOER_Pos) /*!< 0x00000800 */ -#define TAMP_CR3_ITAMP13NOER TAMP_CR3_ITAMP13NOER_Msk - -/******************** Bits definition for TAMP_FLTCR register ***************/ -#define TAMP_FLTCR_TAMPFREQ_Pos (0U) -#define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */ -#define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk -#define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */ -#define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */ -#define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */ -#define TAMP_FLTCR_TAMPFLT_Pos (3U) -#define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */ -#define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk -#define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */ -#define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */ -#define TAMP_FLTCR_TAMPPRCH_Pos (5U) -#define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */ -#define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk -#define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */ -#define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */ -#define TAMP_FLTCR_TAMPPUDIS_Pos (7U) -#define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */ -#define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk - -/******************** Bits definition for TAMP_ATCR1 register ***************/ -#define TAMP_ATCR1_TAMP1AM_Pos (0U) -#define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */ -#define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk -#define TAMP_ATCR1_TAMP2AM_Pos (1U) -#define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */ -#define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk -#define TAMP_ATCR1_TAMP3AM_Pos (2U) -#define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */ -#define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk -#define TAMP_ATCR1_TAMP4AM_Pos (3U) -#define TAMP_ATCR1_TAMP4AM_Msk (0x1UL << TAMP_ATCR1_TAMP4AM_Pos) /*!< 0x00000008 */ -#define TAMP_ATCR1_TAMP4AM TAMP_ATCR1_TAMP4AM_Msk -#define TAMP_ATCR1_TAMP5AM_Pos (4U) -#define TAMP_ATCR1_TAMP5AM_Msk (0x1UL << TAMP_ATCR1_TAMP5AM_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR1_TAMP5AM TAMP_ATCR1_TAMP5AM_Msk -#define TAMP_ATCR1_TAMP6AM_Pos (5U) -#define TAMP_ATCR1_TAMP6AM_Msk (0x1UL << TAMP_ATCR1_TAMP6AM_Pos) /*!< 0x00000010 */ -#define TAMP_ATCR1_TAMP6AM TAMP_ATCR1_TAMP6AM_Msk -#define TAMP_ATCR1_TAMP7AM_Pos (6U) -#define TAMP_ATCR1_TAMP7AM_Msk (0x1UL << TAMP_ATCR1_TAMP7AM_Pos) /*!< 0x00000040 */ -#define TAMP_ATCR1_TAMP7AM TAMP_ATCR1_TAMP7AM_Msk -#define TAMP_ATCR1_TAMP8AM_Pos (7U) -#define TAMP_ATCR1_TAMP8AM_Msk (0x1UL << TAMP_ATCR1_TAMP8AM_Pos) /*!< 0x00000080 */ -#define TAMP_ATCR1_TAMP8AM TAMP_ATCR1_TAMP8AM_Msk -#define TAMP_ATCR1_ATOSEL1_Pos (8U) -#define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */ -#define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk -#define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR1_ATOSEL2_Pos (10U) -#define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */ -#define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk -#define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR1_ATOSEL3_Pos (12U) -#define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */ -#define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk -#define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR1_ATOSEL4_Pos (14U) -#define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */ -#define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk -#define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR1_ATCKSEL_Pos (16U) -#define TAMP_ATCR1_ATCKSEL_Msk (0xFUL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x000F0000 */ -#define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk -#define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR1_ATCKSEL_3 (0x8UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR1_ATPER_Pos (24U) -#define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */ -#define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk -#define TAMP_ATCR1_ATPER_0 (0x1UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR1_ATPER_1 (0x2UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR1_ATPER_2 (0x4UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR1_ATOSHARE_Pos (30U) -#define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk -#define TAMP_ATCR1_FLTEN_Pos (31U) -#define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */ -#define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk - -/******************** Bits definition for TAMP_ATSEEDR register ******************/ -#define TAMP_ATSEEDR_SEED_Pos (0U) -#define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk - -/******************** Bits definition for TAMP_ATOR register ******************/ -#define TAMP_ATOR_PRNG_Pos (0U) -#define TAMP_ATOR_PRNG_Msk (0xFF << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */ -#define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk -#define TAMP_ATOR_PRNG_0 (0x1UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000001 */ -#define TAMP_ATOR_PRNG_1 (0x2UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000002 */ -#define TAMP_ATOR_PRNG_2 (0x4UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000004 */ -#define TAMP_ATOR_PRNG_3 (0x8UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000008 */ -#define TAMP_ATOR_PRNG_4 (0x10UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000010 */ -#define TAMP_ATOR_PRNG_5 (0x20UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000020 */ -#define TAMP_ATOR_PRNG_6 (0x40UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000040 */ -#define TAMP_ATOR_PRNG_7 (0x80UL << TAMP_ATOR_PRNG_Pos) /*!< 0x00000080 */ -#define TAMP_ATOR_SEEDF_Pos (14U) -#define TAMP_ATOR_SEEDF_Msk (1UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */ -#define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk -#define TAMP_ATOR_INITS_Pos (15U) -#define TAMP_ATOR_INITS_Msk (1UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */ -#define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk - -/******************** Bits definition for TAMP_ATCR2 register ***************/ -#define TAMP_ATCR2_ATOSEL1_Pos (8U) -#define TAMP_ATCR2_ATOSEL1_Msk (0x7UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000700 */ -#define TAMP_ATCR2_ATOSEL1 TAMP_ATCR2_ATOSEL1_Msk -#define TAMP_ATCR2_ATOSEL1_0 (0x1UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000100 */ -#define TAMP_ATCR2_ATOSEL1_1 (0x2UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000200 */ -#define TAMP_ATCR2_ATOSEL1_2 (0x4UL << TAMP_ATCR2_ATOSEL1_Pos) /*!< 0x00000400 */ -#define TAMP_ATCR2_ATOSEL2_Pos (11U) -#define TAMP_ATCR2_ATOSEL2_Msk (0x7UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00003800 */ -#define TAMP_ATCR2_ATOSEL2 TAMP_ATCR2_ATOSEL2_Msk -#define TAMP_ATCR2_ATOSEL2_0 (0x1UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00000800 */ -#define TAMP_ATCR2_ATOSEL2_1 (0x2UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00001000 */ -#define TAMP_ATCR2_ATOSEL2_2 (0x4UL << TAMP_ATCR2_ATOSEL2_Pos) /*!< 0x00002000 */ -#define TAMP_ATCR2_ATOSEL3_Pos (14U) -#define TAMP_ATCR2_ATOSEL3_Msk (0x7UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x0001C000 */ -#define TAMP_ATCR2_ATOSEL3 TAMP_ATCR2_ATOSEL3_Msk -#define TAMP_ATCR2_ATOSEL3_0 (0x1UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00004000 */ -#define TAMP_ATCR2_ATOSEL3_1 (0x2UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00008000 */ -#define TAMP_ATCR2_ATOSEL3_2 (0x4UL << TAMP_ATCR2_ATOSEL3_Pos) /*!< 0x00010000 */ -#define TAMP_ATCR2_ATOSEL4_Pos (17U) -#define TAMP_ATCR2_ATOSEL4_Msk (0x7UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x000E0000 */ -#define TAMP_ATCR2_ATOSEL4 TAMP_ATCR2_ATOSEL4_Msk -#define TAMP_ATCR2_ATOSEL4_0 (0x1UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00020000 */ -#define TAMP_ATCR2_ATOSEL4_1 (0x2UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00040000 */ -#define TAMP_ATCR2_ATOSEL4_2 (0x4UL << TAMP_ATCR2_ATOSEL4_Pos) /*!< 0x00080000 */ -#define TAMP_ATCR2_ATOSEL5_Pos (20U) -#define TAMP_ATCR2_ATOSEL5_Msk (0x7UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00700000 */ -#define TAMP_ATCR2_ATOSEL5 TAMP_ATCR2_ATOSEL5_Msk -#define TAMP_ATCR2_ATOSEL5_0 (0x1UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00100000 */ -#define TAMP_ATCR2_ATOSEL5_1 (0x2UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00200000 */ -#define TAMP_ATCR2_ATOSEL5_2 (0x4UL << TAMP_ATCR2_ATOSEL5_Pos) /*!< 0x00400000 */ -#define TAMP_ATCR2_ATOSEL6_Pos (23U) -#define TAMP_ATCR2_ATOSEL6_Msk (0x7UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x03800000 */ -#define TAMP_ATCR2_ATOSEL6 TAMP_ATCR2_ATOSEL6_Msk -#define TAMP_ATCR2_ATOSEL6_0 (0x1UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x00800000 */ -#define TAMP_ATCR2_ATOSEL6_1 (0x2UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x01000000 */ -#define TAMP_ATCR2_ATOSEL6_2 (0x4UL << TAMP_ATCR2_ATOSEL6_Pos) /*!< 0x02000000 */ -#define TAMP_ATCR2_ATOSEL7_Pos (26U) -#define TAMP_ATCR2_ATOSEL7_Msk (0x7UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x1C000000 */ -#define TAMP_ATCR2_ATOSEL7 TAMP_ATCR2_ATOSEL7_Msk -#define TAMP_ATCR2_ATOSEL7_0 (0x1UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x04000000 */ -#define TAMP_ATCR2_ATOSEL7_1 (0x2UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x08000000 */ -#define TAMP_ATCR2_ATOSEL7_2 (0x4UL << TAMP_ATCR2_ATOSEL7_Pos) /*!< 0x10000000 */ -#define TAMP_ATCR2_ATOSEL8_Pos (29U) -#define TAMP_ATCR2_ATOSEL8_Msk (0x7UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0xE0000000 */ -#define TAMP_ATCR2_ATOSEL8 TAMP_ATCR2_ATOSEL8_Msk -#define TAMP_ATCR2_ATOSEL8_0 (0x1UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x20000000 */ -#define TAMP_ATCR2_ATOSEL8_1 (0x2UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x40000000 */ -#define TAMP_ATCR2_ATOSEL8_2 (0x4UL << TAMP_ATCR2_ATOSEL8_Pos) /*!< 0x80000000 */ - -/******************** Bits definition for TAMP_SECCFGR register *************/ -#define TAMP_SECCFGR_BKPRWSEC_Pos (0U) -#define TAMP_SECCFGR_BKPRWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x000000FF */ -#define TAMP_SECCFGR_BKPRWSEC TAMP_SECCFGR_BKPRWSEC_Msk -#define TAMP_SECCFGR_BKPRWSEC_0 (0x1UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000001 */ -#define TAMP_SECCFGR_BKPRWSEC_1 (0x2UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000002 */ -#define TAMP_SECCFGR_BKPRWSEC_2 (0x4UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000004 */ -#define TAMP_SECCFGR_BKPRWSEC_3 (0x8UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000008 */ -#define TAMP_SECCFGR_BKPRWSEC_4 (0x10UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000010 */ -#define TAMP_SECCFGR_BKPRWSEC_5 (0x20UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000020 */ -#define TAMP_SECCFGR_BKPRWSEC_6 (0x40UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000040 */ -#define TAMP_SECCFGR_BKPRWSEC_7 (0x80UL << TAMP_SECCFGR_BKPRWSEC_Pos) /*!< 0x00000080 */ -#define TAMP_SECCFGR_CNT1SEC_Pos (15U) -#define TAMP_SECCFGR_CNT1SEC_Msk (0x1UL << TAMP_SECCFGR_CNT1SEC_Pos) /*!< 0x00008000 */ -#define TAMP_SECCFGR_CNT1SEC TAMP_SECCFGR_CNT1SEC_Msk -#define TAMP_SECCFGR_BKPWSEC_Pos (16U) -#define TAMP_SECCFGR_BKPWSEC_Msk (0xFFUL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00FF0000 */ -#define TAMP_SECCFGR_BKPWSEC TAMP_SECCFGR_BKPWSEC_Msk -#define TAMP_SECCFGR_BKPWSEC_0 (0x1UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00010000 */ -#define TAMP_SECCFGR_BKPWSEC_1 (0x2UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00020000 */ -#define TAMP_SECCFGR_BKPWSEC_2 (0x4UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00040000 */ -#define TAMP_SECCFGR_BKPWSEC_3 (0x8UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00080000 */ -#define TAMP_SECCFGR_BKPWSEC_4 (0x10UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00100000 */ -#define TAMP_SECCFGR_BKPWSEC_5 (0x20UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00200000 */ -#define TAMP_SECCFGR_BKPWSEC_6 (0x40UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00400000 */ -#define TAMP_SECCFGR_BKPWSEC_7 (0x80UL << TAMP_SECCFGR_BKPWSEC_Pos) /*!< 0x00800000 */ -#define TAMP_SECCFGR_BHKLOCK_Pos (30U) -#define TAMP_SECCFGR_BHKLOCK_Msk (0x1UL << TAMP_SECCFGR_BHKLOCK_Pos) /*!< 0x40000000 */ -#define TAMP_SECCFGR_BHKLOCK TAMP_SECCFGR_BHKLOCK_Msk -#define TAMP_SECCFGR_TAMPSEC_Pos (31U) -#define TAMP_SECCFGR_TAMPSEC_Msk (0x1UL << TAMP_SECCFGR_TAMPSEC_Pos) /*!< 0x80000000 */ -#define TAMP_SECCFGR_TAMPSEC TAMP_SECCFGR_TAMPSEC_Msk - -/******************** Bits definition for TAMP_PRIVCFGR register ************/ -#define TAMP_PRIVCFGR_CNT1PRIV_Pos (15U) -#define TAMP_PRIVCFGR_CNT1PRIV_Msk (0x1UL << TAMP_PRIVCFGR_CNT1PRIV_Pos) /*!< 0x20000000 */ -#define TAMP_PRIVCFGR_CNT1PRIV TAMP_PRIVCFGR_CNT1PRIV_Msk -#define TAMP_PRIVCFGR_BKPRWPRIV_Pos (29U) -#define TAMP_PRIVCFGR_BKPRWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPRWPRIV_Pos) /*!< 0x20000000 */ -#define TAMP_PRIVCFGR_BKPRWPRIV TAMP_PRIVCFGR_BKPRWPRIV_Msk -#define TAMP_PRIVCFGR_BKPWPRIV_Pos (30U) -#define TAMP_PRIVCFGR_BKPWPRIV_Msk (0x1UL << TAMP_PRIVCFGR_BKPWPRIV_Pos) /*!< 0x40000000 */ -#define TAMP_PRIVCFGR_BKPWPRIV TAMP_PRIVCFGR_BKPWPRIV_Msk -#define TAMP_PRIVCFGR_TAMPPRIV_Pos (31U) -#define TAMP_PRIVCFGR_TAMPPRIV_Msk (0x1UL << TAMP_PRIVCFGR_TAMPPRIV_Pos) /*!< 0x80000000 */ -#define TAMP_PRIVCFGR_TAMPPRIV TAMP_PRIVCFGR_TAMPPRIV_Msk - -/******************** Bits definition for TAMP_IER register *****************/ -#define TAMP_IER_TAMP1IE_Pos (0U) -#define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */ -#define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk -#define TAMP_IER_TAMP2IE_Pos (1U) -#define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */ -#define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk -#define TAMP_IER_TAMP3IE_Pos (2U) -#define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */ -#define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk -#define TAMP_IER_TAMP4IE_Pos (3U) -#define TAMP_IER_TAMP4IE_Msk (0x1UL << TAMP_IER_TAMP4IE_Pos) /*!< 0x00000008 */ -#define TAMP_IER_TAMP4IE TAMP_IER_TAMP4IE_Msk -#define TAMP_IER_TAMP5IE_Pos (4U) -#define TAMP_IER_TAMP5IE_Msk (0x1UL << TAMP_IER_TAMP5IE_Pos) /*!< 0x00000010 */ -#define TAMP_IER_TAMP5IE TAMP_IER_TAMP5IE_Msk -#define TAMP_IER_TAMP6IE_Pos (5U) -#define TAMP_IER_TAMP6IE_Msk (0x1UL << TAMP_IER_TAMP6IE_Pos) /*!< 0x00000020 */ -#define TAMP_IER_TAMP6IE TAMP_IER_TAMP6IE_Msk -#define TAMP_IER_TAMP7IE_Pos (6U) -#define TAMP_IER_TAMP7IE_Msk (0x1UL << TAMP_IER_TAMP7IE_Pos) /*!< 0x00000040 */ -#define TAMP_IER_TAMP7IE TAMP_IER_TAMP7IE_Msk -#define TAMP_IER_TAMP8IE_Pos (7U) -#define TAMP_IER_TAMP8IE_Msk (0x1UL << TAMP_IER_TAMP8IE_Pos) /*!< 0x00000080 */ -#define TAMP_IER_TAMP8IE TAMP_IER_TAMP8IE_Msk -#define TAMP_IER_ITAMP1IE_Pos (16U) -#define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */ -#define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk -#define TAMP_IER_ITAMP2IE_Pos (17U) -#define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */ -#define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk -#define TAMP_IER_ITAMP3IE_Pos (18U) -#define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */ -#define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk -#define TAMP_IER_ITAMP5IE_Pos (20U) -#define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */ -#define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk -#define TAMP_IER_ITAMP6IE_Pos (21U) -#define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */ -#define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk -#define TAMP_IER_ITAMP7IE_Pos (22U) -#define TAMP_IER_ITAMP7IE_Msk (0x1UL << TAMP_IER_ITAMP7IE_Pos) /*!< 0x00400000 */ -#define TAMP_IER_ITAMP7IE TAMP_IER_ITAMP7IE_Msk -#define TAMP_IER_ITAMP8IE_Pos (23U) -#define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */ -#define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk -#define TAMP_IER_ITAMP9IE_Pos (24U) -#define TAMP_IER_ITAMP9IE_Msk (0x1UL << TAMP_IER_ITAMP9IE_Pos) /*!< 0x01000000 */ -#define TAMP_IER_ITAMP9IE TAMP_IER_ITAMP9IE_Msk -#define TAMP_IER_ITAMP11IE_Pos (26U) -#define TAMP_IER_ITAMP11IE_Msk (0x1UL << TAMP_IER_ITAMP11IE_Pos) /*!< 0x04000000 */ -#define TAMP_IER_ITAMP11IE TAMP_IER_ITAMP11IE_Msk -#define TAMP_IER_ITAMP12IE_Pos (27U) -#define TAMP_IER_ITAMP12IE_Msk (0x1UL << TAMP_IER_ITAMP12IE_Pos) /*!< 0x08000000 */ -#define TAMP_IER_ITAMP12IE TAMP_IER_ITAMP12IE_Msk -#define TAMP_IER_ITAMP13IE_Pos (28U) -#define TAMP_IER_ITAMP13IE_Msk (0x1UL << TAMP_IER_ITAMP13IE_Pos) /*!< 0x10000000 */ -#define TAMP_IER_ITAMP13IE TAMP_IER_ITAMP13IE_Msk - -/******************** Bits definition for TAMP_SR register *****************/ -#define TAMP_SR_TAMP1F_Pos (0U) -#define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */ -#define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk -#define TAMP_SR_TAMP2F_Pos (1U) -#define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */ -#define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk -#define TAMP_SR_TAMP3F_Pos (2U) -#define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */ -#define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk -#define TAMP_SR_TAMP4F_Pos (3U) -#define TAMP_SR_TAMP4F_Msk (0x1UL << TAMP_SR_TAMP4F_Pos) /*!< 0x00000008 */ -#define TAMP_SR_TAMP4F TAMP_SR_TAMP4F_Msk -#define TAMP_SR_TAMP5F_Pos (4U) -#define TAMP_SR_TAMP5F_Msk (0x1UL << TAMP_SR_TAMP5F_Pos) /*!< 0x00000010 */ -#define TAMP_SR_TAMP5F TAMP_SR_TAMP5F_Msk -#define TAMP_SR_TAMP6F_Pos (5U) -#define TAMP_SR_TAMP6F_Msk (0x1UL << TAMP_SR_TAMP6F_Pos) /*!< 0x00000020 */ -#define TAMP_SR_TAMP6F TAMP_SR_TAMP6F_Msk -#define TAMP_SR_TAMP7F_Pos (6U) -#define TAMP_SR_TAMP7F_Msk (0x1UL << TAMP_SR_TAMP7F_Pos) /*!< 0x00000040 */ -#define TAMP_SR_TAMP7F TAMP_SR_TAMP7F_Msk -#define TAMP_SR_TAMP8F_Pos (7U) -#define TAMP_SR_TAMP8F_Msk (0x1UL << TAMP_SR_TAMP8F_Pos) /*!< 0x00000080 */ -#define TAMP_SR_TAMP8F TAMP_SR_TAMP8F_Msk -#define TAMP_SR_ITAMP1F_Pos (16U) -#define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */ -#define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk -#define TAMP_SR_ITAMP2F_Pos (17U) -#define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00010000 */ -#define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk -#define TAMP_SR_ITAMP3F_Pos (18U) -#define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */ -#define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk -#define TAMP_SR_ITAMP5F_Pos (20U) -#define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */ -#define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk -#define TAMP_SR_ITAMP6F_Pos (21U) -#define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */ -#define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk -#define TAMP_SR_ITAMP7F_Pos (22U) -#define TAMP_SR_ITAMP7F_Msk (0x1UL << TAMP_SR_ITAMP7F_Pos) /*!< 0x00400000 */ -#define TAMP_SR_ITAMP7F TAMP_SR_ITAMP7F_Msk -#define TAMP_SR_ITAMP8F_Pos (23U) -#define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */ -#define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk -#define TAMP_SR_ITAMP9F_Pos (24U) -#define TAMP_SR_ITAMP9F_Msk (0x1UL << TAMP_SR_ITAMP9F_Pos) /*!< 0x01000000 */ -#define TAMP_SR_ITAMP9F TAMP_SR_ITAMP9F_Msk -#define TAMP_SR_ITAMP11F_Pos (26U) -#define TAMP_SR_ITAMP11F_Msk (0x1UL << TAMP_SR_ITAMP11F_Pos) /*!< 0x04000000 */ -#define TAMP_SR_ITAMP11F TAMP_SR_ITAMP11F_Msk -#define TAMP_SR_ITAMP12F_Pos (27U) -#define TAMP_SR_ITAMP12F_Msk (0x1UL << TAMP_SR_ITAMP12F_Pos) /*!< 0x08000000 */ -#define TAMP_SR_ITAMP12F TAMP_SR_ITAMP12F_Msk -#define TAMP_SR_ITAMP13F_Pos (28U) -#define TAMP_SR_ITAMP13F_Msk (0x1UL << TAMP_SR_ITAMP13F_Pos) /*!< 0x10000000 */ -#define TAMP_SR_ITAMP13F TAMP_SR_ITAMP13F_Msk - -/******************** Bits definition for TAMP_MISR register ****************/ -#define TAMP_MISR_TAMP1MF_Pos (0U) -#define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */ -#define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk -#define TAMP_MISR_TAMP2MF_Pos (1U) -#define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */ -#define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk -#define TAMP_MISR_TAMP3MF_Pos (2U) -#define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */ -#define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk -#define TAMP_MISR_TAMP4MF_Pos (3U) -#define TAMP_MISR_TAMP4MF_Msk (0x1UL << TAMP_MISR_TAMP4MF_Pos) /*!< 0x00000008 */ -#define TAMP_MISR_TAMP4MF TAMP_MISR_TAMP4MF_Msk -#define TAMP_MISR_TAMP5MF_Pos (4U) -#define TAMP_MISR_TAMP5MF_Msk (0x1UL << TAMP_MISR_TAMP5MF_Pos) /*!< 0x00000010 */ -#define TAMP_MISR_TAMP5MF TAMP_MISR_TAMP5MF_Msk -#define TAMP_MISR_TAMP6MF_Pos (5U) -#define TAMP_MISR_TAMP6MF_Msk (0x1UL << TAMP_MISR_TAMP6MF_Pos) /*!< 0x00000020 */ -#define TAMP_MISR_TAMP6MF TAMP_MISR_TAMP6MF_Msk -#define TAMP_MISR_TAMP7MF_Pos (6U) -#define TAMP_MISR_TAMP7MF_Msk (0x1UL << TAMP_MISR_TAMP7MF_Pos) /*!< 0x00000040 */ -#define TAMP_MISR_TAMP7MF TAMP_MISR_TAMP7MF_Msk -#define TAMP_MISR_TAMP8MF_Pos (7U) -#define TAMP_MISR_TAMP8MF_Msk (0x1UL << TAMP_MISR_TAMP8MF_Pos) /*!< 0x00000080 */ -#define TAMP_MISR_TAMP8MF TAMP_MISR_TAMP8MF_Msk -#define TAMP_MISR_ITAMP1MF_Pos (16U) -#define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk -#define TAMP_MISR_ITAMP2MF_Pos (17U) -#define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00010000 */ -#define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk -#define TAMP_MISR_ITAMP3MF_Pos (18U) -#define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk -#define TAMP_MISR_ITAMP5MF_Pos (20U) -#define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk -#define TAMP_MISR_ITAMP6MF_Pos (21U) -#define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk -#define TAMP_MISR_ITAMP7MF_Pos (22U) -#define TAMP_MISR_ITAMP7MF_Msk (0x1UL << TAMP_MISR_ITAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_MISR_ITAMP7MF TAMP_MISR_ITAMP7MF_Msk -#define TAMP_MISR_ITAMP8MF_Pos (23U) -#define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk -#define TAMP_MISR_ITAMP9MF_Pos (24U) -#define TAMP_MISR_ITAMP9MF_Msk (0x1UL << TAMP_MISR_ITAMP9MF_Pos) /*!< 0x01000000 */ -#define TAMP_MISR_ITAMP9MF TAMP_MISR_ITAMP9MF_Msk -#define TAMP_MISR_ITAMP11MF_Pos (26U) -#define TAMP_MISR_ITAMP11MF_Msk (0x1UL << TAMP_MISR_ITAMP11MF_Pos) /*!< 0x04000000 */ -#define TAMP_MISR_ITAMP11MF TAMP_MISR_ITAMP11MF_Msk -#define TAMP_MISR_ITAMP12MF_Pos (27U) -#define TAMP_MISR_ITAMP12MF_Msk (0x1UL << TAMP_MISR_ITAMP12MF_Pos) /*!< 0x08000000 */ -#define TAMP_MISR_ITAMP12MF TAMP_MISR_ITAMP12MF_Msk -#define TAMP_MISR_ITAMP13MF_Pos (28U) -#define TAMP_MISR_ITAMP13MF_Msk (0x1UL << TAMP_MISR_ITAMP13MF_Pos) /*!< 0x10000000 */ -#define TAMP_MISR_ITAMP13MF TAMP_MISR_ITAMP13MF_Msk - -/******************** Bits definition for TAMP_SMISR register ************ *****/ -#define TAMP_SMISR_TAMP1MF_Pos (0U) -#define TAMP_SMISR_TAMP1MF_Msk (0x1UL << TAMP_SMISR_TAMP1MF_Pos) /*!< 0x00000001 */ -#define TAMP_SMISR_TAMP1MF TAMP_SMISR_TAMP1MF_Msk -#define TAMP_SMISR_TAMP2MF_Pos (1U) -#define TAMP_SMISR_TAMP2MF_Msk (0x1UL << TAMP_SMISR_TAMP2MF_Pos) /*!< 0x00000002 */ -#define TAMP_SMISR_TAMP2MF TAMP_SMISR_TAMP2MF_Msk -#define TAMP_SMISR_TAMP3MF_Pos (2U) -#define TAMP_SMISR_TAMP3MF_Msk (0x1UL << TAMP_SMISR_TAMP3MF_Pos) /*!< 0x00000004 */ -#define TAMP_SMISR_TAMP3MF TAMP_SMISR_TAMP3MF_Msk -#define TAMP_SMISR_TAMP4MF_Pos (3U) -#define TAMP_SMISR_TAMP4MF_Msk (0x1UL << TAMP_SMISR_TAMP4MF_Pos) /*!< 0x00000008 */ -#define TAMP_SMISR_TAMP4MF TAMP_SMISR_TAMP4MF_Msk -#define TAMP_SMISR_TAMP5MF_Pos (4U) -#define TAMP_SMISR_TAMP5MF_Msk (0x1UL << TAMP_SMISR_TAMP5MF_Pos) /*!< 0x00000010 */ -#define TAMP_SMISR_TAMP5MF TAMP_SMISR_TAMP5MF_Msk -#define TAMP_SMISR_TAMP6MF_Pos (5U) -#define TAMP_SMISR_TAMP6MF_Msk (0x1UL << TAMP_SMISR_TAMP6MF_Pos) /*!< 0x00000020 */ -#define TAMP_SMISR_TAMP6MF TAMP_SMISR_TAMP6MF_Msk -#define TAMP_SMISR_TAMP7MF_Pos (6U) -#define TAMP_SMISR_TAMP7MF_Msk (0x1UL << TAMP_SMISR_TAMP7MF_Pos) /*!< 0x00000040 */ -#define TAMP_SMISR_TAMP7MF TAMP_SMISR_TAMP7MF_Msk -#define TAMP_SMISR_TAMP8MF_Pos (7U) -#define TAMP_SMISR_TAMP8MF_Msk (0x1UL << TAMP_SMISR_TAMP8MF_Pos) /*!< 0x00000080 */ -#define TAMP_SMISR_TAMP8MF TAMP_SMISR_TAMP8MF_Msk -#define TAMP_SMISR_ITAMP1MF_Pos (16U) -#define TAMP_SMISR_ITAMP1MF_Msk (0x1UL << TAMP_SMISR_ITAMP1MF_Pos) /*!< 0x00010000 */ -#define TAMP_SMISR_ITAMP1MF TAMP_SMISR_ITAMP1MF_Msk -#define TAMP_SMISR_ITAMP2MF_Pos (17U) -#define TAMP_SMISR_ITAMP2MF_Msk (0x1UL << TAMP_SMISR_ITAMP2MF_Pos) /*!< 0x00010000 */ -#define TAMP_SMISR_ITAMP2MF TAMP_SMISR_ITAMP2MF_Msk -#define TAMP_SMISR_ITAMP3MF_Pos (18U) -#define TAMP_SMISR_ITAMP3MF_Msk (0x1UL << TAMP_SMISR_ITAMP3MF_Pos) /*!< 0x00040000 */ -#define TAMP_SMISR_ITAMP3MF TAMP_SMISR_ITAMP3MF_Msk -#define TAMP_SMISR_ITAMP5MF_Pos (20U) -#define TAMP_SMISR_ITAMP5MF_Msk (0x1UL << TAMP_SMISR_ITAMP5MF_Pos) /*!< 0x00100000 */ -#define TAMP_SMISR_ITAMP5MF TAMP_SMISR_ITAMP5MF_Msk -#define TAMP_SMISR_ITAMP6MF_Pos (21U) -#define TAMP_SMISR_ITAMP6MF_Msk (0x1UL << TAMP_SMISR_ITAMP6MF_Pos) /*!< 0x00200000 */ -#define TAMP_SMISR_ITAMP6MF TAMP_SMISR_ITAMP6MF_Msk -#define TAMP_SMISR_ITAMP7MF_Pos (22U) -#define TAMP_SMISR_ITAMP7MF_Msk (0x1UL << TAMP_SMISR_ITAMP7MF_Pos) /*!< 0x00400000 */ -#define TAMP_SMISR_ITAMP7MF TAMP_SMISR_ITAMP7MF_Msk -#define TAMP_SMISR_ITAMP8MF_Pos (23U) -#define TAMP_SMISR_ITAMP8MF_Msk (0x1UL << TAMP_SMISR_ITAMP8MF_Pos) /*!< 0x00800000 */ -#define TAMP_SMISR_ITAMP8MF TAMP_SMISR_ITAMP8MF_Msk -#define TAMP_SMISR_ITAMP9MF_Pos (24U) -#define TAMP_SMISR_ITAMP9MF_Msk (0x1UL << TAMP_SMISR_ITAMP9MF_Pos) /*!< 0x01000000 */ -#define TAMP_SMISR_ITAMP9MF TAMP_SMISR_ITAMP9MF_Msk -#define TAMP_SMISR_ITAMP11MF_Pos (26U) -#define TAMP_SMISR_ITAMP11MF_Msk (0x1UL << TAMP_SMISR_ITAMP11MF_Pos) /*!< 0x04000000 */ -#define TAMP_SMISR_ITAMP11MF TAMP_SMISR_ITAMP11MF_Msk -#define TAMP_SMISR_ITAMP12MF_Pos (27U) -#define TAMP_SMISR_ITAMP12MF_Msk (0x1UL << TAMP_SMISR_ITAMP12MF_Pos) /*!< 0x08000000 */ -#define TAMP_SMISR_ITAMP12MF TAMP_SMISR_ITAMP12MF_Msk -#define TAMP_SMISR_ITAMP13MF_Pos (28U) -#define TAMP_SMISR_ITAMP13MF_Msk (0x1UL << TAMP_SMISR_ITAMP13MF_Pos) /*!< 0x10000000 */ -#define TAMP_SMISR_ITAMP13MF TAMP_SMISR_ITAMP13MF_Msk - -/******************** Bits definition for TAMP_SCR register *****************/ -#define TAMP_SCR_CTAMP1F_Pos (0U) -#define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */ -#define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk -#define TAMP_SCR_CTAMP2F_Pos (1U) -#define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */ -#define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk -#define TAMP_SCR_CTAMP3F_Pos (2U) -#define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */ -#define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk -#define TAMP_SCR_CTAMP4F_Pos (3U) -#define TAMP_SCR_CTAMP4F_Msk (0x1UL << TAMP_SCR_CTAMP4F_Pos) /*!< 0x00000008 */ -#define TAMP_SCR_CTAMP4F TAMP_SCR_CTAMP4F_Msk -#define TAMP_SCR_CTAMP5F_Pos (4U) -#define TAMP_SCR_CTAMP5F_Msk (0x1UL << TAMP_SCR_CTAMP5F_Pos) /*!< 0x00000010 */ -#define TAMP_SCR_CTAMP5F TAMP_SCR_CTAMP5F_Msk -#define TAMP_SCR_CTAMP6F_Pos (5U) -#define TAMP_SCR_CTAMP6F_Msk (0x1UL << TAMP_SCR_CTAMP6F_Pos) /*!< 0x00000020 */ -#define TAMP_SCR_CTAMP6F TAMP_SCR_CTAMP6F_Msk -#define TAMP_SCR_CTAMP7F_Pos (6U) -#define TAMP_SCR_CTAMP7F_Msk (0x1UL << TAMP_SCR_CTAMP7F_Pos) /*!< 0x00000040 */ -#define TAMP_SCR_CTAMP7F TAMP_SCR_CTAMP7F_Msk -#define TAMP_SCR_CTAMP8F_Pos (7U) -#define TAMP_SCR_CTAMP8F_Msk (0x1UL << TAMP_SCR_CTAMP8F_Pos) /*!< 0x00000080 */ -#define TAMP_SCR_CTAMP8F TAMP_SCR_CTAMP8F_Msk -#define TAMP_SCR_CITAMP1F_Pos (16U) -#define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */ -#define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk -#define TAMP_SCR_CITAMP2F_Pos (17U) -#define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00010000 */ -#define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk -#define TAMP_SCR_CITAMP3F_Pos (18U) -#define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */ -#define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk -#define TAMP_SCR_CITAMP5F_Pos (20U) -#define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */ -#define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk -#define TAMP_SCR_CITAMP6F_Pos (21U) -#define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */ -#define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk -#define TAMP_SCR_CITAMP7F_Pos (22U) -#define TAMP_SCR_CITAMP7F_Msk (0x1UL << TAMP_SCR_CITAMP7F_Pos) /*!< 0x00400000 */ -#define TAMP_SCR_CITAMP7F TAMP_SCR_CITAMP7F_Msk -#define TAMP_SCR_CITAMP8F_Pos (23U) -#define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */ -#define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk -#define TAMP_SCR_CITAMP9F_Pos (24U) -#define TAMP_SCR_CITAMP9F_Msk (0x1UL << TAMP_SCR_CITAMP9F_Pos) /*!< 0x01000000 */ -#define TAMP_SCR_CITAMP9F TAMP_SCR_CITAMP9F_Msk -#define TAMP_SCR_CITAMP11F_Pos (26U) -#define TAMP_SCR_CITAMP11F_Msk (0x1UL << TAMP_SCR_CITAMP11F_Pos) /*!< 0x04000000 */ -#define TAMP_SCR_CITAMP11F TAMP_SCR_CITAMP11F_Msk -#define TAMP_SCR_CITAMP12F_Pos (27U) -#define TAMP_SCR_CITAMP12F_Msk (0x1UL << TAMP_SCR_CITAMP12F_Pos) /*!< 0x08000000 */ -#define TAMP_SCR_CITAMP12F TAMP_SCR_CITAMP12F_Msk -#define TAMP_SCR_CITAMP13F_Pos (28U) -#define TAMP_SCR_CITAMP13F_Msk (0x1UL << TAMP_SCR_CITAMP13F_Pos) /*!< 0x10000000 */ -#define TAMP_SCR_CITAMP13F TAMP_SCR_CITAMP13F_Msk - -/******************** Bits definition for TAMP_COUNTR register ***************/ -#define TAMP_COUNTR_Pos (16U) -#define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */ -#define TAMP_COUNTR TAMP_COUNTR_Msk - -/******************** Bits definition for TAMP_ERCFGR register ***************/ -#define TAMP_ERCFGR0_Pos (0U) -#define TAMP_ERCFGR0_Msk (0x1UL << TAMP_ERCFGR0_Pos) /*!< 0x00000001 */ -#define TAMP_ERCFGR0 TAMP_ERCFGR0_Msk - -/******************** Bits definition for TAMP_BKP0R register ***************/ -#define TAMP_BKP0R_Pos (0U) -#define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP0R TAMP_BKP0R_Msk - -/******************** Bits definition for TAMP_BKP1R register ****************/ -#define TAMP_BKP1R_Pos (0U) -#define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP1R TAMP_BKP1R_Msk - -/******************** Bits definition for TAMP_BKP2R register ****************/ -#define TAMP_BKP2R_Pos (0U) -#define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP2R TAMP_BKP2R_Msk - -/******************** Bits definition for TAMP_BKP3R register ****************/ -#define TAMP_BKP3R_Pos (0U) -#define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP3R TAMP_BKP3R_Msk - -/******************** Bits definition for TAMP_BKP4R register ****************/ -#define TAMP_BKP4R_Pos (0U) -#define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP4R TAMP_BKP4R_Msk - -/******************** Bits definition for TAMP_BKP5R register ****************/ -#define TAMP_BKP5R_Pos (0U) -#define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP5R TAMP_BKP5R_Msk - -/******************** Bits definition for TAMP_BKP6R register ****************/ -#define TAMP_BKP6R_Pos (0U) -#define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP6R TAMP_BKP6R_Msk - -/******************** Bits definition for TAMP_BKP7R register ****************/ -#define TAMP_BKP7R_Pos (0U) -#define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP7R TAMP_BKP7R_Msk - -/******************** Bits definition for TAMP_BKP8R register ****************/ -#define TAMP_BKP8R_Pos (0U) -#define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP8R TAMP_BKP8R_Msk - -/******************** Bits definition for TAMP_BKP9R register ****************/ -#define TAMP_BKP9R_Pos (0U) -#define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP9R TAMP_BKP9R_Msk - -/******************** Bits definition for TAMP_BKP10R register ***************/ -#define TAMP_BKP10R_Pos (0U) -#define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP10R TAMP_BKP10R_Msk - -/******************** Bits definition for TAMP_BKP11R register ***************/ -#define TAMP_BKP11R_Pos (0U) -#define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP11R TAMP_BKP11R_Msk - -/******************** Bits definition for TAMP_BKP12R register ***************/ -#define TAMP_BKP12R_Pos (0U) -#define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP12R TAMP_BKP12R_Msk - -/******************** Bits definition for TAMP_BKP13R register ***************/ -#define TAMP_BKP13R_Pos (0U) -#define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP13R TAMP_BKP13R_Msk - -/******************** Bits definition for TAMP_BKP14R register ***************/ -#define TAMP_BKP14R_Pos (0U) -#define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP14R TAMP_BKP14R_Msk - -/******************** Bits definition for TAMP_BKP15R register ***************/ -#define TAMP_BKP15R_Pos (0U) -#define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP15R TAMP_BKP15R_Msk - -/******************** Bits definition for TAMP_BKP16R register ***************/ -#define TAMP_BKP16R_Pos (0U) -#define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP16R TAMP_BKP16R_Msk - -/******************** Bits definition for TAMP_BKP17R register ***************/ -#define TAMP_BKP17R_Pos (0U) -#define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP17R TAMP_BKP17R_Msk - -/******************** Bits definition for TAMP_BKP18R register ***************/ -#define TAMP_BKP18R_Pos (0U) -#define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP18R TAMP_BKP18R_Msk - -/******************** Bits definition for TAMP_BKP19R register ***************/ -#define TAMP_BKP19R_Pos (0U) -#define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP19R TAMP_BKP19R_Msk - -/******************** Bits definition for TAMP_BKP20R register ***************/ -#define TAMP_BKP20R_Pos (0U) -#define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP20R TAMP_BKP20R_Msk - -/******************** Bits definition for TAMP_BKP21R register ***************/ -#define TAMP_BKP21R_Pos (0U) -#define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP21R TAMP_BKP21R_Msk - -/******************** Bits definition for TAMP_BKP22R register ***************/ -#define TAMP_BKP22R_Pos (0U) -#define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP22R TAMP_BKP22R_Msk - -/******************** Bits definition for TAMP_BKP23R register ***************/ -#define TAMP_BKP23R_Pos (0U) -#define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP23R TAMP_BKP23R_Msk - -/******************** Bits definition for TAMP_BKP24R register ***************/ -#define TAMP_BKP24R_Pos (0U) -#define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP24R TAMP_BKP24R_Msk - -/******************** Bits definition for TAMP_BKP25R register ***************/ -#define TAMP_BKP25R_Pos (0U) -#define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP25R TAMP_BKP25R_Msk - -/******************** Bits definition for TAMP_BKP26R register ***************/ -#define TAMP_BKP26R_Pos (0U) -#define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP26R TAMP_BKP26R_Msk - -/******************** Bits definition for TAMP_BKP27R register ***************/ -#define TAMP_BKP27R_Pos (0U) -#define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP27R TAMP_BKP27R_Msk - -/******************** Bits definition for TAMP_BKP28R register ***************/ -#define TAMP_BKP28R_Pos (0U) -#define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP28R TAMP_BKP28R_Msk - -/******************** Bits definition for TAMP_BKP29R register ***************/ -#define TAMP_BKP29R_Pos (0U) -#define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP29R TAMP_BKP29R_Msk - -/******************** Bits definition for TAMP_BKP30R register ***************/ -#define TAMP_BKP30R_Pos (0U) -#define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP30R TAMP_BKP30R_Msk - -/******************** Bits definition for TAMP_BKP31R register ***************/ -#define TAMP_BKP31R_Pos (0U) -#define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */ -#define TAMP_BKP31R TAMP_BKP31R_Msk - -/******************************************************************************/ -/* */ -/* Touch Sensing Controller (TSC) */ -/* */ -/******************************************************************************/ -/******************* Bit definition for TSC_CR register *********************/ -#define TSC_CR_TSCE_Pos (0U) -#define TSC_CR_TSCE_Msk (0x1UL << TSC_CR_TSCE_Pos) /*!< 0x00000001 */ -#define TSC_CR_TSCE TSC_CR_TSCE_Msk /*!>2) /*!< Input modulus number of bits */ -#define PKA_MONTGOMERY_PARAM_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Compute Montgomery parameter output data */ -#define PKA_MONTGOMERY_PARAM_OUT_PARAMETER ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output Montgomery parameter */ - -/* Compute modular exponentiation input data */ -#define PKA_MODULAR_EXP_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent number of bits */ -#define PKA_MODULAR_EXP_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ -#define PKA_MODULAR_EXP_IN_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ -#define PKA_MODULAR_EXP_IN_EXPONENT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process */ -#define PKA_MODULAR_EXP_IN_MODULUS ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ -#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT_BASE ((0x16C8UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the protected exponentiation */ -#define PKA_MODULAR_EXP_PROTECT_IN_EXPONENT ((0x14B8UL - PKA_RAM_OFFSET)>>2) /*!< Input exponent to process protected exponentiation*/ -#define PKA_MODULAR_EXP_PROTECT_IN_MODULUS ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus to process protected exponentiation */ -#define PKA_MODULAR_EXP_PROTECT_IN_PHI ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input phi to process protected exponentiation */ - -/* Compute modular exponentiation output data */ -#define PKA_MODULAR_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result of the exponentiation */ -#define PKA_MODULAR_EXP_OUT_ERROR ((0x1298UL - PKA_RAM_OFFSET)>>2) /*!< Output error of the exponentiation */ -#define PKA_MODULAR_EXP_OUT_MONTGOMERY_PARAM ((0x0620UL - PKA_RAM_OFFSET)>>2) /*!< Output storage area for Montgomery parameter */ -#define PKA_MODULAR_EXP_OUT_EXPONENT_BASE ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Output base of the exponentiation */ - -/* Compute ECC scalar multiplication input data */ -#define PKA_ECC_SCALAR_MUL_IN_EXP_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input curve prime order n number of bits */ -#define PKA_ECC_SCALAR_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECC_SCALAR_MUL_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_ECC_SCALAR_MUL_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_SCALAR_MUL_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' of KP */ -#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_SCALAR_MUL_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_SCALAR_MUL_IN_N_PRIME_ORDER ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input prime order n */ - -/* Compute ECC scalar multiplication output data */ -#define PKA_ECC_SCALAR_MUL_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ -#define PKA_ECC_SCALAR_MUL_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ -#define PKA_ECC_SCALAR_MUL_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/* Point check input data */ -#define PKA_POINT_CHECK_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_POINT_CHECK_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_POINT_CHECK_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_POINT_CHECK_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_POINT_CHECK_IN_MOD_GF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_POINT_CHECK_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_POINT_CHECK_IN_INITIAL_POINT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_POINT_CHECK_IN_MONTGOMERY_PARAM ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ - -/* Point check output data */ -#define PKA_POINT_CHECK_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ - -/* ECDSA signature input data */ -#define PKA_ECDSA_SIGN_IN_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ -#define PKA_ECDSA_SIGN_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECDSA_SIGN_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECDSA_SIGN_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECDSA_SIGN_IN_B_COEFF ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'b' coefficient */ -#define PKA_ECDSA_SIGN_IN_MOD_GF ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECDSA_SIGN_IN_K ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input k value of the ECDSA */ -#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECDSA_SIGN_IN_HASH_E ((0x0FE8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ -#define PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D ((0x0F28UL - PKA_RAM_OFFSET)>>2) /*!< Input d, private key */ -#define PKA_ECDSA_SIGN_IN_ORDER_N ((0x0F88UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ - -/* ECDSA signature output data */ -#define PKA_ECDSA_SIGN_OUT_ERROR ((0x0FE0UL - PKA_RAM_OFFSET)>>2) /*!< Output error */ -#define PKA_ECDSA_SIGN_OUT_SIGNATURE_R ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Output signature r */ -#define PKA_ECDSA_SIGN_OUT_SIGNATURE_S ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Output signature s */ -#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_X ((0x1400UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point X coordinate */ -#define PKA_ECDSA_SIGN_OUT_FINAL_POINT_Y ((0x1458UL - PKA_RAM_OFFSET)>>2) /*!< Extended output result point Y coordinate */ - -/* ECDSA verification input data */ -#define PKA_ECDSA_VERIF_IN_ORDER_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input order number of bits */ -#define PKA_ECDSA_VERIF_IN_MOD_NB_BITS ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus number of bits */ -#define PKA_ECDSA_VERIF_IN_A_COEFF_SIGN ((0x0468UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECDSA_VERIF_IN_A_COEFF ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve 'a' coefficient */ -#define PKA_ECDSA_VERIF_IN_MOD_GF ((0x04D0UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_X ((0x0678UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y ((0x06D0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X ((0x12F8UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point X coordinate */ -#define PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y ((0x1350UL - PKA_RAM_OFFSET)>>2) /*!< Input public key point Y coordinate */ -#define PKA_ECDSA_VERIF_IN_SIGNATURE_R ((0x10E0UL - PKA_RAM_OFFSET)>>2) /*!< Input r, part of the signature */ -#define PKA_ECDSA_VERIF_IN_SIGNATURE_S ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input s, part of the signature */ -#define PKA_ECDSA_VERIF_IN_HASH_E ((0x13A8UL - PKA_RAM_OFFSET)>>2) /*!< Input e, hash of the message */ -#define PKA_ECDSA_VERIF_IN_ORDER_N ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ - -/* ECDSA verification output data */ -#define PKA_ECDSA_VERIF_OUT_RESULT ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* RSA CRT exponentiation input data */ -#define PKA_RSA_CRT_EXP_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operands number of bits */ -#define PKA_RSA_CRT_EXP_IN_DP_CRT ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input Dp CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_DQ_CRT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Input Dq CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_QINV_CRT ((0x0948UL - PKA_RAM_OFFSET)>>2) /*!< Input qInv CRT parameter */ -#define PKA_RSA_CRT_EXP_IN_PRIME_P ((0x0B60UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime p */ -#define PKA_RSA_CRT_EXP_IN_PRIME_Q ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input Prime q */ -#define PKA_RSA_CRT_EXP_IN_EXPONENT_BASE ((0x12A0UL - PKA_RAM_OFFSET)>>2) /*!< Input base of the exponentiation */ - -/* RSA CRT exponentiation output data */ -#define PKA_RSA_CRT_EXP_OUT_RESULT ((0x0838UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular reduction input data */ -#define PKA_MODULAR_REDUC_IN_OP_LENGTH ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input operand length */ -#define PKA_MODULAR_REDUC_IN_MOD_LENGTH ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus length */ -#define PKA_MODULAR_REDUC_IN_OPERAND ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand */ -#define PKA_MODULAR_REDUC_IN_MODULUS ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Modular reduction output data */ -#define PKA_MODULAR_REDUC_OUT_RESULT ((0xE78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic addition input data */ -#define PKA_ARITHMETIC_ADD_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic addition output data */ -#define PKA_ARITHMETIC_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic subtraction input data */ -#define PKA_ARITHMETIC_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic subtraction output data */ -#define PKA_ARITHMETIC_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Arithmetic multiplication input data */ -#define PKA_ARITHMETIC_MUL_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Arithmetic multiplication output data */ -#define PKA_ARITHMETIC_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Comparison input data */ -#define PKA_COMPARISON_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_COMPARISON_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_COMPARISON_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Comparison output data */ -#define PKA_COMPARISON_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular addition input data */ -#define PKA_MODULAR_ADD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_ADD_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_ADD_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MODULAR_ADD_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 (modulus) */ - -/* Modular addition output data */ -#define PKA_MODULAR_ADD_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular inversion input data */ -#define PKA_MODULAR_INV_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_INV_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_INV_IN_OP2_MOD ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 (modulus) */ - -/* Modular inversion output data */ -#define PKA_MODULAR_INV_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Modular subtraction input data */ -#define PKA_MODULAR_SUB_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MODULAR_SUB_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MODULAR_SUB_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MODULAR_SUB_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op3 */ - -/* Modular subtraction output data */ -#define PKA_MODULAR_SUB_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Montgomery multiplication input data */ -#define PKA_MONTGOMERY_MUL_IN_OP_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_MONTGOMERY_MUL_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_MONTGOMERY_MUL_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_MONTGOMERY_MUL_IN_OP3_MOD ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus */ - -/* Montgomery multiplication output data */ -#define PKA_MONTGOMERY_MUL_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result */ - -/* Generic Arithmetic input data */ -#define PKA_ARITHMETIC_ALL_OPS_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input operand number of bits */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP1 ((0x0A50UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op1 */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP2 ((0x0C68UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ -#define PKA_ARITHMETIC_ALL_OPS_IN_OP3 ((0x1088UL - PKA_RAM_OFFSET)>>2) /*!< Input operand op2 */ - -/* Generic Arithmetic output data */ -#define PKA_ARITHMETIC_ALL_OPS_OUT_RESULT ((0x0E78UL - PKA_RAM_OFFSET)>>2) /*!< Output result for arithmetic operations */ - -/* Compute ECC complete addition input data */ -#define PKA_ECC_COMPLETE_ADD_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_COMPLETE_ADD_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ -#define PKA_ECC_COMPLETE_ADD_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ - -/* Compute ECC complete addition output data */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate */ -#define PKA_ECC_COMPLETE_ADD_OUT_RESULT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Output result Z coordinate */ - -/* Compute ECC double base ladder input data */ -#define PKA_ECC_DOUBLE_LADDER_IN_PRIME_ORDER_NB_BITS ((0x0400UL - PKA_RAM_OFFSET)>>2) /*!< Input n, order of the curve */ -#define PKA_ECC_DOUBLE_LADDER_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF_SIGN ((0x0410UL - PKA_RAM_OFFSET)>>2) /*!< Input sign of the 'a' coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_A_COEFF ((0x0418UL - PKA_RAM_OFFSET)>>2) /*!< Input ECC curve '|a|' coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_DOUBLE_LADDER_IN_K_INTEGER ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Input 'k' integer coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_M_INTEGER ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Input 'm' integer coefficient */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_X ((0x0628UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P X coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Y ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Y coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT1_Z ((0x06D8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point P Z coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_X ((0x0730UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q X coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Y ((0x0788UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Y coordinate */ -#define PKA_ECC_DOUBLE_LADDER_IN_POINT2_Z ((0x07E0UL - PKA_RAM_OFFSET)>>2) /*!< Input initial point Q Z coordinate */ - -/* Compute ECC double base ladder output data */ -#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result X coordinate (affine coordinate) */ -#define PKA_ECC_DOUBLE_LADDER_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result Y coordinate (affine coordinate) */ -#define PKA_ECC_DOUBLE_LADDER_OUT_ERROR ((0x0520UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/* Compute ECC projective to affine conversion input data */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_NB_BITS ((0x0408UL - PKA_RAM_OFFSET)>>2) /*!< Input Modulus number of bits */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MOD_P ((0x0470UL - PKA_RAM_OFFSET)>>2) /*!< Input modulus GF(p) */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_X ((0x0D60UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P X coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Y ((0x0DB8UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Y coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_POINT_Z ((0x0E10UL - PKA_RAM_OFFSET)>>2) /*!< Input initial projective point P Z coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_IN_MONTGOMERY_PARAM_R2 ((0x04C8UL - PKA_RAM_OFFSET)>>2) /*!< Input storage area for Montgomery parameter */ - -/* Compute ECC projective to affine conversion output data */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_X ((0x0578UL - PKA_RAM_OFFSET)>>2) /*!< Output result x affine coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_RESULT_Y ((0x05D0UL - PKA_RAM_OFFSET)>>2) /*!< Output result y affine coordinate */ -#define PKA_ECC_PROJECTIVE_AFF_OUT_ERROR ((0x0680UL - PKA_RAM_OFFSET)>>2) /*!< Output result error */ - -/** @addtogroup STM32U5xx_Peripheral_Exported_macros - * @{ - */ - -/******************************* ADC Instances ********************************/ -#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS)|| \ - ((INSTANCE) == ADC1_S) || \ - ((INSTANCE) == ADC4_NS)|| \ - ((INSTANCE) == ADC4_S)) - -#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == ADC1_NS) || \ - ((INSTANCE) == ADC1_S)) - -#define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON_NS) || \ - ((INSTANCE) == ADC12_COMMON_S) || \ - ((INSTANCE) == ADC4_COMMON_NS) || \ - ((INSTANCE) == ADC4_COMMON_S)) - -/******************************* AES Instances ********************************/ -#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES_NS) || ((INSTANCE) == AES_S)) - -/******************************* PKA Instances ********************************/ -#define IS_PKA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == PKA_NS) || ((INSTANCE) == PKA_S)) - -/******************************** FDCAN Instances *****************************/ -#define IS_FDCAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FDCAN1_NS) || ((INSTANCE) == FDCAN1_S)) - -/******************************** COMP Instances ******************************/ -#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ - ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) - -/******************** COMP Instances with window mode capability **************/ -#define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) (((INSTANCE) == COMP1_NS) || ((INSTANCE) == COMP1_S) || \ - ((INSTANCE) == COMP2_NS) || ((INSTANCE) == COMP2_S)) - -/******************************* CORDIC Instances *****************************/ -#define IS_CORDIC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CORDIC_NS) || ((INSTANCE) == CORDIC_S)) - -/******************************* CRC Instances ********************************/ -#define IS_CRC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CRC_NS) || ((INSTANCE) == CRC_S)) - -/******************************* DAC Instances ********************************/ -#define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1_NS) || ((INSTANCE) == DAC1_S)) - -/******************************* DELAYBLOCK Instances *******************************/ -#define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1_NS) || \ - ((INSTANCE) == DLYB_SDMMC2_NS) || \ - ((INSTANCE) == DLYB_SDMMC1_S) || \ - ((INSTANCE) == DLYB_SDMMC2_S) || \ - ((INSTANCE) == DLYB_OCTOSPI1_NS) || \ - ((INSTANCE) == DLYB_OCTOSPI2_NS) || \ - ((INSTANCE) == DLYB_OCTOSPI1_S) || \ - ((INSTANCE) == DLYB_OCTOSPI2_S )) - -/******************************** DMA Instances *******************************/ -#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ - ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ - ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ - ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ - ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ - ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ - ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ - ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ - ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ - ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ - ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ - ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ - ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ - ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ - ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ - ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S) || \ - ((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ - ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ - ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ - ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) - -#define IS_GPDMA_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel0_NS) || ((INSTANCE) == GPDMA1_Channel0_S) || \ - ((INSTANCE) == GPDMA1_Channel1_NS) || ((INSTANCE) == GPDMA1_Channel1_S) || \ - ((INSTANCE) == GPDMA1_Channel2_NS) || ((INSTANCE) == GPDMA1_Channel2_S) || \ - ((INSTANCE) == GPDMA1_Channel3_NS) || ((INSTANCE) == GPDMA1_Channel3_S) || \ - ((INSTANCE) == GPDMA1_Channel4_NS) || ((INSTANCE) == GPDMA1_Channel4_S) || \ - ((INSTANCE) == GPDMA1_Channel5_NS) || ((INSTANCE) == GPDMA1_Channel5_S) || \ - ((INSTANCE) == GPDMA1_Channel6_NS) || ((INSTANCE) == GPDMA1_Channel6_S) || \ - ((INSTANCE) == GPDMA1_Channel7_NS) || ((INSTANCE) == GPDMA1_Channel7_S) || \ - ((INSTANCE) == GPDMA1_Channel8_NS) || ((INSTANCE) == GPDMA1_Channel8_S) || \ - ((INSTANCE) == GPDMA1_Channel9_NS) || ((INSTANCE) == GPDMA1_Channel9_S) || \ - ((INSTANCE) == GPDMA1_Channel10_NS) || ((INSTANCE) == GPDMA1_Channel10_S) || \ - ((INSTANCE) == GPDMA1_Channel11_NS) || ((INSTANCE) == GPDMA1_Channel11_S) || \ - ((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ - ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ - ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ - ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) - -#define IS_LPDMA_INSTANCE(INSTANCE) (((INSTANCE) == LPDMA1_Channel0_NS) || ((INSTANCE) == LPDMA1_Channel0_S) || \ - ((INSTANCE) == LPDMA1_Channel1_NS) || ((INSTANCE) == LPDMA1_Channel1_S) || \ - ((INSTANCE) == LPDMA1_Channel2_NS) || ((INSTANCE) == LPDMA1_Channel2_S) || \ - ((INSTANCE) == LPDMA1_Channel3_NS) || ((INSTANCE) == LPDMA1_Channel3_S)) - -#define IS_DMA_2D_ADDRESSING_INSTANCE(INSTANCE) (((INSTANCE) == GPDMA1_Channel12_NS) || ((INSTANCE) == GPDMA1_Channel12_S) || \ - ((INSTANCE) == GPDMA1_Channel13_NS) || ((INSTANCE) == GPDMA1_Channel13_S) || \ - ((INSTANCE) == GPDMA1_Channel14_NS) || ((INSTANCE) == GPDMA1_Channel14_S) || \ - ((INSTANCE) == GPDMA1_Channel15_NS) || ((INSTANCE) == GPDMA1_Channel15_S)) - -/****************************** OTFDEC Instances ********************************/ -#define IS_OTFDEC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OTFDEC1_NS) || ((INSTANCE) == OTFDEC1_S) || \ - ((INSTANCE) == OTFDEC2_NS) || ((INSTANCE) == OTFDEC2_S)) - -/****************************** RAMCFG Instances ********************************/ -#define IS_RAMCFG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM1_NS) || ((INSTANCE) == RAMCFG_SRAM1_S) || \ - ((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ - ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ - ((INSTANCE) == RAMCFG_SRAM4_NS) || ((INSTANCE) == RAMCFG_SRAM4_S) || \ - ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) - -/***************************** RAMCFG ECC Instances *****************************/ -#define IS_RAMCFG_ECC_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ - ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ - ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) - -/***************************** RAMCFG IT Instances ******************************/ -#define IS_RAMCFG_IT_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S) || \ - ((INSTANCE) == RAMCFG_SRAM3_NS) || ((INSTANCE) == RAMCFG_SRAM3_S) || \ - ((INSTANCE) == RAMCFG_BKPRAM_NS) || ((INSTANCE) == RAMCFG_BKPRAM_S)) - -/************************ RAMCFG Write Protection Instances *********************/ -#define IS_RAMCFG_WP_INSTANCE(INSTANCE) (((INSTANCE) == RAMCFG_SRAM2_NS) || ((INSTANCE) == RAMCFG_SRAM2_S)) - -/******************************** FMAC Instances ******************************/ -#define IS_FMAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == FMAC_NS) || ((INSTANCE) == FMAC_S)) - -/******************************* GPIO Instances *******************************/ -#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA_NS) || ((INSTANCE) == GPIOA_S) || \ - ((INSTANCE) == GPIOB_NS) || ((INSTANCE) == GPIOB_S) || \ - ((INSTANCE) == GPIOC_NS) || ((INSTANCE) == GPIOC_S) || \ - ((INSTANCE) == GPIOD_NS) || ((INSTANCE) == GPIOD_S) || \ - ((INSTANCE) == GPIOE_NS) || ((INSTANCE) == GPIOE_S) || \ - ((INSTANCE) == GPIOF_NS) || ((INSTANCE) == GPIOF_S) || \ - ((INSTANCE) == GPIOG_NS) || ((INSTANCE) == GPIOG_S) || \ - ((INSTANCE) == GPIOH_NS) || ((INSTANCE) == GPIOH_S) || \ - ((INSTANCE) == GPIOI_NS) || ((INSTANCE) == GPIOI_S) || \ - ((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) - -/******************************* LPGPIO Instances *****************************/ -#define IS_LPGPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == LPGPIO1_NS) || ((INSTANCE) == LPGPIO1_S)) - -/******************************* DMA2D Instances *******************************/ -#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA2D_NS) || ((__INSTANCE__) == DMA2D_S)) - -/******************************* DCMI Instances *******************************/ -#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DCMI_NS) || ((__INSTANCE__) == DCMI_S)) - -/******************************* DCACHE Instances *****************************/ -#define IS_DCACHE_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DCACHE1_NS) || ((INSTANCE) == DCACHE1_S)) - -/******************************* PSSI Instances *******************************/ -#define IS_PSSI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == PSSI_NS) || ((__INSTANCE__) == PSSI_S)) - -/******************************* GPIO AF Instances ****************************/ -/* On U5, all GPIO Bank support AF */ -#define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/**************************** GPIO Lock Instances *****************************/ -/* On U5, all GPIO Bank support the Lock mechanism */ -#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE) - -/******************************** I2C Instances *******************************/ -#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ - ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ - ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ - ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) - -/****************** I2C Instances : wakeup capability from stop modes *********/ -#define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE) - -/******************* I2C Instances : Group belongingness *********************/ -#define IS_I2C_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ - ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ - ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) - -#define IS_I2C_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) - -/****************************** OPAMP Instances *******************************/ -#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1_NS) || ((INSTANCE) == OPAMP1_S) || \ - ((INSTANCE) == OPAMP2_NS) || ((INSTANCE) == OPAMP2_S)) - -/******************************* OSPI Instances *******************************/ -#define IS_OSPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OCTOSPI1_NS) || ((INSTANCE) == OCTOSPI1_S) || \ - ((INSTANCE) == OCTOSPI2_NS) || ((INSTANCE) == OCTOSPI2_S)) - -/******************************* RNG Instances ********************************/ -#define IS_RNG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RNG_NS) || ((INSTANCE) == RNG_S)) - -/****************************** RTC Instances *********************************/ -#define IS_RTC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RTC_NS) || ((INSTANCE) == RTC_S)) - -/******************************** SAI Instances *******************************/ -#define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A_NS) || ((INSTANCE) == SAI1_Block_A_S) || \ - ((INSTANCE) == SAI1_Block_B_NS) || ((INSTANCE) == SAI1_Block_B_S) || \ - ((INSTANCE) == SAI2_Block_A_NS) || ((INSTANCE) == SAI2_Block_A_S) || \ - ((INSTANCE) == SAI2_Block_B_NS) || ((INSTANCE) == SAI2_Block_B_S)) - -/****************************** SDMMC Instances *******************************/ -#define IS_SDMMC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SDMMC1_NS) || ((INSTANCE) == SDMMC1_S) || \ - ((INSTANCE) == SDMMC2_NS) || ((INSTANCE) == SDMMC2_S)) - -/****************************** SMBUS Instances *******************************/ -#define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ - ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ - ((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S) || \ - ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) - -/******************* SMBUS Instances : Group belongingness *********************/ -#define IS_SMBUS_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == I2C1_NS) || ((INSTANCE) == I2C1_S) || \ - ((INSTANCE) == I2C2_NS) || ((INSTANCE) == I2C2_S) || \ - ((INSTANCE) == I2C4_NS) || ((INSTANCE) == I2C4_S)) - -#define IS_SMBUS_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == I2C3_NS) || ((INSTANCE) == I2C3_S)) - -/******************************** SPI Instances *******************************/ -#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ - ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S) || \ - ((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) - -#define IS_SPI_LIMITED_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) - -#define IS_SPI_FULL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ - ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) - -#define IS_SPI_GRP1_INSTANCE(INSTANCE) (((INSTANCE) == SPI1_NS) || ((INSTANCE) == SPI1_S) || \ - ((INSTANCE) == SPI2_NS) || ((INSTANCE) == SPI2_S)) - -#define IS_SPI_GRP2_INSTANCE(INSTANCE) (((INSTANCE) == SPI3_NS) || ((INSTANCE) == SPI3_S)) - -/****************** LPTIM Instances : All supported instances *****************/ -#define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ - ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ - ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ - ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) - -/****************** LPTIM Instances : DMA supported instances *****************/ -#define IS_LPTIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ - ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ - ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) - -/************* LPTIM Instances : at least 1 capture/compare channel ***********/ -#define IS_LPTIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ - ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ - ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S) ||\ - ((INSTANCE) == LPTIM4_NS) || ((INSTANCE) == LPTIM4_S)) - -/************* LPTIM Instances : at least 2 capture/compare channel ***********/ -#define IS_LPTIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ - ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ - ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) - -/****************** LPTIM Instances : supporting encoder interface **************/ -#define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ - ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S)) - -/****************** LPTIM Instances : supporting Input Capture **************/ -#define IS_LPTIM_INPUT_CAPTURE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1_NS) || ((INSTANCE) == LPTIM1_S) ||\ - ((INSTANCE) == LPTIM2_NS) || ((INSTANCE) == LPTIM2_S) ||\ - ((INSTANCE) == LPTIM3_NS) || ((INSTANCE) == LPTIM3_S)) - -/****************** TIM Instances : All supported instances *******************/ -#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ - ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****************** TIM Instances : supporting 32 bits counter ****************/ -#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) - -/****************** TIM Instances : supporting the break function *************/ -#define IS_TIM_BREAK_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/************** TIM Instances : supporting Break source selection *************/ -#define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****************** TIM Instances : supporting 2 break inputs *****************/ -#define IS_TIM_BKIN2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/************* TIM Instances : at least 1 capture/compare channel *************/ -#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/************ TIM Instances : at least 2 capture/compare channels *************/ -#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) - -/************ TIM Instances : at least 3 capture/compare channels *************/ -#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/************ TIM Instances : at least 4 capture/compare channels *************/ -#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : at least 5 capture/compare channels *******/ -#define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : at least 6 capture/compare channels *******/ -#define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : DMA requests generation (TIMx_DIER.UDE) ***/ -#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ - ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/************ TIM Instances : DMA requests generation (TIMx_DIER.CCxDE) *******/ -#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/******************** TIM Instances : DMA burst feature ***********************/ -#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/******************* TIM Instances : output(s) available **********************/ -#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \ - (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_5) || \ - ((CHANNEL) == TIM_CHANNEL_6))) \ - || \ - ((((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ - ((((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ - ((((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ - ((((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ - ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4) || \ - ((CHANNEL) == TIM_CHANNEL_5) || \ - ((CHANNEL) == TIM_CHANNEL_6))) \ - || \ - ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2))) \ - || \ - ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1))) \ - || \ - ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1)))) - -/****************** TIM Instances : supporting complementary output(s) ********/ -#define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \ - (((((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ - ((((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) && \ - (((CHANNEL) == TIM_CHANNEL_1) || \ - ((CHANNEL) == TIM_CHANNEL_2) || \ - ((CHANNEL) == TIM_CHANNEL_3) || \ - ((CHANNEL) == TIM_CHANNEL_4))) \ - || \ - ((((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) && \ - ((CHANNEL) == TIM_CHANNEL_1)) \ - || \ - ((((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)) && \ - ((CHANNEL) == TIM_CHANNEL_1)) \ - || \ - ((((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) && \ - ((CHANNEL) == TIM_CHANNEL_1))) - -/****************** TIM Instances : supporting clock division *****************/ -#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****** TIM Instances : supporting external clock mode 1 for ETRF input *******/ -#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****** TIM Instances : supporting external clock mode 2 for ETRF input *******/ -#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/ -#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) - -/****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/ -#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) - -/****************** TIM Instances : supporting combined 3-phase PWM mode ******/ -#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : supporting commutation event generation ***/ -#define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****************** TIM Instances : supporting counting mode selection ********/ -#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : supporting encoder interface **************/ -#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : supporting Hall sensor interface **********/ -#define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/**************** TIM Instances : external trigger input available ************/ -#define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****** TIM Instances : Master mode available (TIMx_CR2.MMS available )********/ -#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM6_NS) || ((INSTANCE) == TIM6_S) || \ - ((INSTANCE) == TIM7_NS) || ((INSTANCE) == TIM7_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) - -/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/ -#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) - -/****************** TIM Instances : supporting OCxREF clear *******************/ -#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****************** TIM Instances : remapping capability **********************/ -#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : supporting repetition counter *************/ -#define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S) || \ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) || \ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ -#define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/******************* TIM Instances : Timer input XOR function *****************/ -#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) || \ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) || \ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) || \ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) || \ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)) - -/******************* TIM Instances : Timer input selection ********************/ -#define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) ||\ - ((INSTANCE) == TIM2_NS) || ((INSTANCE) == TIM2_S) ||\ - ((INSTANCE) == TIM3_NS) || ((INSTANCE) == TIM3_S) ||\ - ((INSTANCE) == TIM4_NS) || ((INSTANCE) == TIM4_S) ||\ - ((INSTANCE) == TIM5_NS) || ((INSTANCE) == TIM5_S) ||\ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S) ||\ - ((INSTANCE) == TIM15_NS) || ((INSTANCE) == TIM15_S)||\ - ((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S)||\ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/******************* TIM Instances : supporting HSE32 as input ********************/ -#define IS_TIM_HSE32_INSTANCE(INSTANCE) (((INSTANCE) == TIM16_NS) || ((INSTANCE) == TIM16_S) ||\ - ((INSTANCE) == TIM17_NS) || ((INSTANCE) == TIM17_S)) - -/****************** TIM Instances : Advanced timer instances *******************/ -#define IS_TIM_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TIM1_NS) || ((INSTANCE) == TIM1_S) || \ - ((INSTANCE) == TIM8_NS) || ((INSTANCE) == TIM8_S)) - -/****************** TIM Instances : supporting synchronization ****************/ -#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1_NS) || ((__INSTANCE__) == TIM1_S) || \ - ((__INSTANCE__) == TIM2_NS) || ((__INSTANCE__) == TIM2_S) || \ - ((__INSTANCE__) == TIM3_NS) || ((__INSTANCE__) == TIM3_S) || \ - ((__INSTANCE__) == TIM4_NS) || ((__INSTANCE__) == TIM4_S) || \ - ((__INSTANCE__) == TIM5_NS) || ((__INSTANCE__) == TIM5_S) || \ - ((__INSTANCE__) == TIM6_NS) || ((__INSTANCE__) == TIM6_S) || \ - ((__INSTANCE__) == TIM7_NS) || ((__INSTANCE__) == TIM7_S) || \ - ((__INSTANCE__) == TIM8_NS) || ((__INSTANCE__) == TIM8_S) || \ - ((__INSTANCE__) == TIM15_NS) || ((__INSTANCE__) == TIM15_S)) - -/****************************** TSC Instances *********************************/ -#define IS_TSC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == TSC_NS) || ((INSTANCE) == TSC_S)) - -/******************** USART Instances : Synchronous mode **********************/ -#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) - -/******************** UART Instances : Asynchronous mode **********************/ -#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) - -/*********************** UART Instances : FIFO mode ***************************/ -#define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ - ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/*********************** UART Instances : SPI Slave mode **********************/ -#define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) - -/****************** UART Instances : Auto Baud Rate detection ****************/ -#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) - -/****************** UART Instances : Driver Enable *****************/ -#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ - ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/******************** UART Instances : Half-Duplex mode **********************/ -#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ - ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/****************** UART Instances : Hardware Flow control ********************/ -#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ - ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/******************** UART Instances : LIN mode **********************/ -#define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) - -/******************** UART Instances : Wake-up from Stop mode **********************/ -#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ - ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/*********************** UART Instances : IRDA mode ***************************/ -#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S)) - -/********************* USART Instances : Smard card mode ***********************/ -#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S)) - -/******************** LPUART Instance *****************************************/ -#define IS_LPUART_INSTANCE(INSTANCE) (((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/*********************** UART Instances : AUTONOMOUS mode ***************************/ -#define IS_UART_AUTONOMOUS_INSTANCE(INSTANCE) (((INSTANCE) == USART1_NS) || ((INSTANCE) == USART1_S) || \ - ((INSTANCE) == USART2_NS) || ((INSTANCE) == USART2_S) || \ - ((INSTANCE) == USART3_NS) || ((INSTANCE) == USART3_S) || \ - ((INSTANCE) == UART4_NS) || ((INSTANCE) == UART4_S) || \ - ((INSTANCE) == UART5_NS) || ((INSTANCE) == UART5_S) || \ - ((INSTANCE) == LPUART1_NS) || ((INSTANCE) == LPUART1_S)) - -/****************************** IWDG Instances ********************************/ -#define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG_NS) || ((INSTANCE) == IWDG_S)) - -/****************************** WWDG Instances ********************************/ -#define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG_NS) || ((INSTANCE) == WWDG_S)) - -/****************************** UCPD Instances ********************************/ -#define IS_UCPD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == UCPD1_NS) || ((INSTANCE) == UCPD1_S)) - -/******************************* OTG FS HCD Instances *************************/ -#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS_NS) || ((INSTANCE) == USB_OTG_FS_S)) - -/******************************* OTG FS PCD Instances *************************/ -#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS_NS) || ((INSTANCE) == USB_OTG_FS_S)) - -/******************************* MDF/ADF Instances ****************************/ -#define IS_MDF_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDF1_Filter0_NS) || ((INSTANCE) == MDF1_Filter0_S) || \ - ((INSTANCE) == MDF1_Filter1_NS) || ((INSTANCE) == MDF1_Filter1_S) || \ - ((INSTANCE) == MDF1_Filter2_NS) || ((INSTANCE) == MDF1_Filter2_S) || \ - ((INSTANCE) == MDF1_Filter3_NS) || ((INSTANCE) == MDF1_Filter3_S) || \ - ((INSTANCE) == MDF1_Filter4_NS) || ((INSTANCE) == MDF1_Filter4_S) || \ - ((INSTANCE) == MDF1_Filter5_NS) || ((INSTANCE) == MDF1_Filter5_S) || \ - ((INSTANCE) == ADF1_Filter0_NS) || ((INSTANCE) == ADF1_Filter0_S)) - - -/** @} */ /* End of group STM32U5xx_Peripheral_Exported_macros */ - -/** @} */ /* End of group STM32U585xx */ - -/** @} */ /* End of group ST */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U585xx_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h deleted file mode 100644 index ecff76b3a..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/stm32u5xx.h +++ /dev/null @@ -1,268 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx.h - * @author MCD Application Team - * @brief CMSIS STM32U5xx Device Peripheral Access Layer Header File. - * - * The file is the unique include file that the application programmer - * is using in the C source code, usually in main.c. This file contains: - * - Configuration section that allows to select: - * - The STM32U5xx device used in the target application - * - To use or not the peripheral's drivers in application code(i.e. - * code will be based on direct access to peripheral's registers - * rather than drivers API), this option is controlled by - * "#define USE_HAL_DRIVER" - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32u5xx - * @{ - */ - -#ifndef STM32U5xx_H -#define STM32U5xx_H - -#ifdef __cplusplus - extern "C" { -#endif /* __cplusplus */ - -/** @addtogroup Library_configuration_section - * @{ - */ - -/** - * @brief STM32 Family - */ -#if !defined (STM32U5) -#define STM32U5 -#endif /* STM32U5 */ - -/* Uncomment the line below according to the target STM32U5 device used in your - application - */ - -#if !defined (STM32U575xx) && !defined (STM32U585xx) \ - && !defined (STM32U595xx) && !defined (STM32U599xx) \ - && !defined (STM32U5A5xx) && !defined (STM32U5A9xx) \ - && !defined (STM32U5F7xx) && !defined (STM32U5G7xx) \ - && !defined (STM32U5F9xx) && !defined (STM32U5G9xx) \ - && !defined (STM32U535xx) && !defined (STM32U545xx) \ - /* #define STM32U575xx */ /*!< STM32U575CIU6 STM32U575CIT6 STM32U575RIT6 STM32U575VIT6 STM32U575ZIT6 STM32U575QII6 STM32U575AII6 STM32U575CIU6Q STM32U575CIT6Q STM32U575OIY6Q STM32U575VIT6Q STM32U575QII6Q STM32U575ZIT6Q STM32U575RIT6Q STM32U575CGU6 STM32U575CGT6 STM32U575RGT6 STM32U575VGT6 STM32U575ZGT6 STM32U575QGI6 STM32U575AGI6 STM32U575CGU6Q STM32U575CGT6Q STM32U575OGY6Q STM32U575VGT6Q STM32U575QGI6Q STM32U575ZGT6Q STM32U575RGT6Q STM32U575AGI6Q Devices */ - /* #define STM32U585xx */ /*!< STM32U585CIU6 STM32U585CIT6 STM32U585RIT6 STM32U585VIT6 STM32U585AII6 STM32U585QII6 STM32U585ZIT6 STM32U585OIY6Q STM32U585VIT6Q STM32U585QEI6Q STM32U585RIT6Q STM32U585AII6Q STM32U585CIU6Q STM32U585CIT6Q STM32U585ZET6Q Devices */ - /* #define STM32U595xx */ /*!< STM32U595AJH6 STM32U595ZJT6 STM32U595QJI6 STM32U595VJT6 STM32U595RJT6 STM32U595AJH6Q STM32U595ZJY6QTR STM32U595ZJT6Q STM32U595QJI6Q STM32U595VJT6Q STM32U595RJT6Q STM32U595AIH6 STM32U595ZIT6 STM32U595QII6 STM32U595VIT6 STM32U595RIT6 STM32U595AIH6Q STM32U595ZIY6QTR STM32U595ZIT6Q STM32U595QII6Q STM32U595VIT6Q STM32U595RIT6Q Devices */ - /* #define STM32U599xx */ /*!< STM32U599VJT6 STM32U599NJH6Q STM32U599BJY6QTR STM32U599ZJY6QTR STM32U599ZJT6Q STM32U599VJT6Q STM32U599NIH6Q STM32U599ZIY6QTR STM32U599ZIT6Q STM32U599VIT6Q Devices */ - /* #define STM32U5A5xx */ /*!< STM32U5A5AJH6 STM32U5A5ZJT6 STM32U5A5QJI6 STM32U5A5VJT6 STM32U5A5RJT6 STM32U5A5AJH6Q STM32U5A5ZJY6QTR STM32U5A5ZJT6Q STM32U5A5QJI6Q STM32U5A5VJT6Q STM32U5A5RJT6Q STM32U5A5QII3Q Devices */ - /* #define STM32U5A9xx */ /*!< STM32U5A9NJH6Q STM32U5A9BJY6QTR STM32U5A9ZJY6QTR STM32U5A9ZJT6Q STM32U5A9VJT6Q Devices */ - /* #define STM32U5F7xx */ /*!< STM32U5F7VJT6Q STM32U5F7VJT6 STM32U5F7VIT6Q STM32U5F7VIT6 Devices */ - /* #define STM32U5G7xx */ /*!< STM32U5G7VJT6Q STM32U5G7VJT6 Devices */ - /* #define STM32U5F9xx */ /*!< STM32U5F9NJH6Q STM32U5F9BJY6QTR STM32U5F9ZJJ6QTR STM32U5F9ZJT6Q STM32U5F9VJT6Q STM32U5F9ZIJ6QTR STM32U5F9ZIT6Q STM32U5F9VIT6Q Devices */ - /* #define STM32U5G9xx */ /*!< STM32U5G9NJH6Q STM32U5G9BJY6QTR STM32U5G9ZJJ6QTR STM32U5G9ZJT6Q STM32U5G9VJT6Q Devices */ - /* #define STM32U535xx */ /*!< STM32U535CET6 STM32U535CEU6 STM32U535RET6 STM32U535REI6 STM32U535VET6 STM32U535VEI6 STM32U535CET6Q STM32U535CEU6Q STM32U535RET6Q STM32U535REI6Q STM32U535VET6Q STM32U535VEI6Q STM32U535NEY6Q STM32U535JEY6Q Devices */ - /* #define STM32U545xx */ /*!< STM32U545CET6 STM32U545CEU6 STM32U545RET6 STM32U545REI6 STM32U545VET6 STM32U545VEI6 STM32U545CET6Q STM32U545CEU6Q STM32U545RET6Q STM32U545REI6Q STM32U545VET6Q STM32U545VEI6Q STM32U545NEY6Q STM32U545JEY6Q Devices */ -#endif - -/* Tip: To avoid modifying this file each time you need to switch between these - devices, you can define the device in your toolchain compiler preprocessor. - */ -#if !defined (USE_HAL_DRIVER) -/** - * @brief Comment the line below if you will not use the peripherals drivers. - In this case, these drivers will not be included and the application code will - be based on direct access to peripherals registers - */ - /*#define USE_HAL_DRIVER */ -#endif /* USE_HAL_DRIVER */ - -/** - * @brief CMSIS Device version number 1.4.0 - */ -#define __STM32U5_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */ -#define __STM32U5_CMSIS_VERSION_SUB1 (0x04) /*!< [23:16] sub1 version */ -#define __STM32U5_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */ -#define __STM32U5_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */ -#define __STM32U5_CMSIS_VERSION ((__STM32U5_CMSIS_VERSION_MAIN << 24U)\ - |(__STM32U5_CMSIS_VERSION_SUB1 << 16U)\ - |(__STM32U5_CMSIS_VERSION_SUB2 << 8U )\ - |(__STM32U5_CMSIS_VERSION_RC)) - -/** - * @} - */ - -/** @addtogroup Device_Included - * @{ - */ - -#if defined(STM32U575xx) - #include "stm32u575xx.h" -#elif defined(STM32U585xx) - #include "stm32u585xx.h" -#elif defined(STM32U595xx) - #include "stm32u595xx.h" -#elif defined(STM32U599xx) - #include "stm32u599xx.h" -#elif defined(STM32U5A5xx) - #include "stm32u5a5xx.h" -#elif defined(STM32U5A9xx) - #include "stm32u5a9xx.h" -#elif defined(STM32U5F9xx) - #include "stm32u5f9xx.h" -#elif defined(STM32U5G9xx) - #include "stm32u5g9xx.h" -#elif defined(STM32U5F7xx) - #include "stm32u5f7xx.h" -#elif defined(STM32U5G7xx) - #include "stm32u5g7xx.h" -#elif defined(STM32U535xx) - #include "stm32u535xx.h" -#elif defined(STM32U545xx) - #include "stm32u545xx.h" -#else - #error "Please select first the target STM32U5xx device used in your application (in stm32u5xx.h file)" -#endif - -/** - * @} - */ - -/** @addtogroup Exported_types - * @{ - */ -typedef enum -{ - RESET = 0, - SET = !RESET -} FlagStatus, ITStatus; - -typedef enum -{ - DISABLE = 0, - ENABLE = !DISABLE -} FunctionalState; -#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE)) - -typedef enum -{ - SUCCESS = 0, - ERROR = !SUCCESS -} ErrorStatus; - -/** - * @} - */ - - -/** @addtogroup Exported_macros - * @{ - */ -#define SET_BIT(REG, BIT) ((REG) |= (BIT)) - -#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) - -#define READ_BIT(REG, BIT) ((REG) & (BIT)) - -#define CLEAR_REG(REG) ((REG) = (0x0)) - -#define WRITE_REG(REG, VAL) ((REG) = (VAL)) - -#define READ_REG(REG) ((REG)) - -#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) - -/* Use of CMSIS compiler intrinsics for register exclusive access */ -/* Atomic 32-bit register access macro to set one or several bits */ -#define ATOMIC_SET_BIT(REG, BIT) \ - do { \ - uint32_t val; \ - do { \ - val = __LDREXW((__IO uint32_t *)&(REG)) | (BIT); \ - } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 32-bit register access macro to clear one or several bits */ -#define ATOMIC_CLEAR_BIT(REG, BIT) \ - do { \ - uint32_t val; \ - do { \ - val = __LDREXW((__IO uint32_t *)&(REG)) & ~(BIT); \ - } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 32-bit register access macro to clear and set one or several bits */ -#define ATOMIC_MODIFY_REG(REG, CLEARMSK, SETMASK) \ - do { \ - uint32_t val; \ - do { \ - val = (__LDREXW((__IO uint32_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ - } while ((__STREXW(val,(__IO uint32_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 16-bit register access macro to set one or several bits */ -#define ATOMIC_SETH_BIT(REG, BIT) \ - do { \ - uint16_t val; \ - do { \ - val = __LDREXH((__IO uint16_t *)&(REG)) | (BIT); \ - } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 16-bit register access macro to clear one or several bits */ -#define ATOMIC_CLEARH_BIT(REG, BIT) \ - do { \ - uint16_t val; \ - do { \ - val = __LDREXH((__IO uint16_t *)&(REG)) & ~(BIT); \ - } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ - } while(0) - -/* Atomic 16-bit register access macro to clear and set one or several bits */ -#define ATOMIC_MODIFYH_REG(REG, CLEARMSK, SETMASK) \ - do { \ - uint16_t val; \ - do { \ - val = (__LDREXH((__IO uint16_t *)&(REG)) & ~(CLEARMSK)) | (SETMASK); \ - } while ((__STREXH(val,(__IO uint16_t *)&(REG))) != 0U); \ - } while(0) - -#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL))) - - -/** - * @} - */ - -#if defined (USE_HAL_DRIVER) - #include "stm32u5xx_hal.h" -#endif /* USE_HAL_DRIVER */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* STM32U5xx_H */ -/** - * @} - */ - -/** - * @} - */ - - - - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h deleted file mode 100644 index 811a27024..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/Include/system_stm32u5xx.h +++ /dev/null @@ -1,109 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32u5xx.h - * @author MCD Application Team - * @brief CMSIS Cortex-M33 Device System Source File for STM32U5xx devices. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup stm32u5xx_system - * @{ - */ - -#ifndef SYSTEM_STM32U5XX_H -#define SYSTEM_STM32U5XX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup STM32U5xx_System_Includes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Exported_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetSysClockFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -extern const uint8_t AHBPrescTable[16]; /*!< AHB prescalers table values */ -extern const uint8_t APBPrescTable[8]; /*!< APB prescalers table values */ -extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ - -/** - * @} - */ - - -/** @addtogroup STM32U5xx_System_Exported_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - - -/** - * @brief Update SystemCoreClock variable. - * - * Updates the SystemCoreClock with current core Clock retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - - -/** - * @brief Update SystemCoreClock variable from secure application and return its value - * when security is implemented in the system (Non-secure callable function). - * - * Returns the SystemCoreClock value with current core Clock retrieved from cpu registers. - */ -extern uint32_t SECURE_SystemCoreClockUpdate(void); - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_STM32U5XX_H */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md deleted file mode 100644 index d1a7d01b0..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.md +++ /dev/null @@ -1,201 +0,0 @@ - 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We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright 2021 STMicroelectronics - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. \ No newline at end of file diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt deleted file mode 100644 index 872e82b46..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Device/ST/STM32U5xx/LICENSE.txt +++ /dev/null @@ -1,6 +0,0 @@ -This software component is provided to you as part of a software package and -applicable license terms are in the Package_license file. If you received this -software component outside of a package or without applicable license terms, -the terms of the Apache-2.0 license shall apply. -You may obtain a copy of the Apache-2.0 at: -https://opensource.org/licenses/Apache-2.0 diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cachel1_armv7.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cachel1_armv7.h deleted file mode 100644 index abebc95f9..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cachel1_armv7.h +++ /dev/null @@ -1,411 +0,0 @@ -/****************************************************************************** - * @file cachel1_armv7.h - * @brief CMSIS Level 1 Cache API for Armv7-M and later - * @version V1.0.1 - * @date 19. April 2021 - ******************************************************************************/ -/* - * Copyright (c) 2020-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_CACHEL1_ARMV7_H -#define ARM_CACHEL1_ARMV7_H - -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#ifndef __SCB_DCACHE_LINE_SIZE -#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -#ifndef __SCB_ICACHE_LINE_SIZE -#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#endif - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (volatile void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (volatile void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ - -#endif /* ARM_CACHEL1_ARMV7_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armcc.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armcc.h deleted file mode 100644 index a955d4713..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armcc.h +++ /dev/null @@ -1,888 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armcc.h - * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file - * @version V5.3.2 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_ARMCC_H -#define __CMSIS_ARMCC_H - - -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) - #error "Please use Arm Compiler Toolchain V4.0.677 or later!" -#endif - -/* CMSIS compiler control architecture macros */ -#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ - (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) - #define __ARM_ARCH_6M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) - #define __ARM_ARCH_7M__ 1 -#endif - -#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) - #define __ARM_ARCH_7EM__ 1 -#endif - - /* __ARM_ARCH_8M_BASE__ not applicable */ - /* __ARM_ARCH_8M_MAIN__ not applicable */ - /* __ARM_ARCH_8_1M_MAIN__ not applicable */ - -/* CMSIS compiler control DSP macros */ -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __ARM_FEATURE_DSP 1 -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE static __forceinline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __declspec(noreturn) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed)) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT __packed struct -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION __packed union -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __memory_changed() -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __nop - - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __dsb(0xF) - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV __rev - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) -{ - rev16 r0, r0 - bx lr -} -#endif - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) -{ - revsh r0, r0 - bx lr -} -#endif - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -#define __ROR __ror - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __breakpoint(value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - #define __RBIT __rbit -#else -__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ - return result; -} -#endif - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -#define __CLZ __clz - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) -#else - #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) -#else - #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) -#else - #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXB(value, ptr) __strex(value, ptr) -#else - #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXH(value, ptr) __strex(value, ptr) -#else - #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) - #define __STREXW(value, ptr) __strex(value, ptr) -#else - #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") -#endif - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __clrex - - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -#ifndef __NO_EMBEDDED_ASM -__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) -{ - rrx r0, r0 - bx lr -} -#endif - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRBT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRHT(value, ptr) __strt(value, ptr) - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -#define __STRT(value, ptr) __strt(value, ptr) - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __enable_irq(); */ - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -/* intrinsic void __disable_irq(); */ - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_INLINE uint32_t __get_CONTROL(void) -{ - register uint32_t __regControl __ASM("control"); - return(__regControl); -} - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_INLINE void __set_CONTROL(uint32_t control) -{ - register uint32_t __regControl __ASM("control"); - __regControl = control; - __ISB(); -} - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_INLINE uint32_t __get_IPSR(void) -{ - register uint32_t __regIPSR __ASM("ipsr"); - return(__regIPSR); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_INLINE uint32_t __get_APSR(void) -{ - register uint32_t __regAPSR __ASM("apsr"); - return(__regAPSR); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_INLINE uint32_t __get_xPSR(void) -{ - register uint32_t __regXPSR __ASM("xpsr"); - return(__regXPSR); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_INLINE uint32_t __get_PSP(void) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - return(__regProcessStackPointer); -} - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) -{ - register uint32_t __regProcessStackPointer __ASM("psp"); - __regProcessStackPointer = topOfProcStack; -} - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_INLINE uint32_t __get_MSP(void) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - return(__regMainStackPointer); -} - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) -{ - register uint32_t __regMainStackPointer __ASM("msp"); - __regMainStackPointer = topOfMainStack; -} - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_INLINE uint32_t __get_PRIMASK(void) -{ - register uint32_t __regPriMask __ASM("primask"); - return(__regPriMask); -} - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) -{ - register uint32_t __regPriMask __ASM("primask"); - __regPriMask = (priMask); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __enable_fault_irq __enable_fiq - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -#define __disable_fault_irq __disable_fiq - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_INLINE uint32_t __get_BASEPRI(void) -{ - register uint32_t __regBasePri __ASM("basepri"); - return(__regBasePri); -} - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) -{ - register uint32_t __regBasePri __ASM("basepri"); - __regBasePri = (basePri & 0xFFU); -} - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - register uint32_t __regBasePriMax __ASM("basepri_max"); - __regBasePriMax = (basePri & 0xFFU); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_INLINE uint32_t __get_FAULTMASK(void) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - return(__regFaultMask); -} - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) -{ - register uint32_t __regFaultMask __ASM("faultmask"); - __regFaultMask = (faultMask & (uint32_t)1U); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_INLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - return(__regfpscr); -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - register uint32_t __regfpscr __ASM("fpscr"); - __regfpscr = (fpscr); -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) - -#define __SADD8 __sadd8 -#define __QADD8 __qadd8 -#define __SHADD8 __shadd8 -#define __UADD8 __uadd8 -#define __UQADD8 __uqadd8 -#define __UHADD8 __uhadd8 -#define __SSUB8 __ssub8 -#define __QSUB8 __qsub8 -#define __SHSUB8 __shsub8 -#define __USUB8 __usub8 -#define __UQSUB8 __uqsub8 -#define __UHSUB8 __uhsub8 -#define __SADD16 __sadd16 -#define __QADD16 __qadd16 -#define __SHADD16 __shadd16 -#define __UADD16 __uadd16 -#define __UQADD16 __uqadd16 -#define __UHADD16 __uhadd16 -#define __SSUB16 __ssub16 -#define __QSUB16 __qsub16 -#define __SHSUB16 __shsub16 -#define __USUB16 __usub16 -#define __UQSUB16 __uqsub16 -#define __UHSUB16 __uhsub16 -#define __SASX __sasx -#define __QASX __qasx -#define __SHASX __shasx -#define __UASX __uasx -#define __UQASX __uqasx -#define __UHASX __uhasx -#define __SSAX __ssax -#define __QSAX __qsax -#define __SHSAX __shsax -#define __USAX __usax -#define __UQSAX __uqsax -#define __UHSAX __uhsax -#define __USAD8 __usad8 -#define __USADA8 __usada8 -#define __SSAT16 __ssat16 -#define __USAT16 __usat16 -#define __UXTB16 __uxtb16 -#define __UXTAB16 __uxtab16 -#define __SXTB16 __sxtb16 -#define __SXTAB16 __sxtab16 -#define __SMUAD __smuad -#define __SMUADX __smuadx -#define __SMLAD __smlad -#define __SMLADX __smladx -#define __SMLALD __smlald -#define __SMLALDX __smlaldx -#define __SMUSD __smusd -#define __SMUSDX __smusdx -#define __SMLSD __smlsd -#define __SMLSDX __smlsdx -#define __SMLSLD __smlsld -#define __SMLSLDX __smlsldx -#define __SEL __sel -#define __QADD __qadd -#define __QSUB __qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ - ((int64_t)(ARG3) << 32U) ) >> 32U)) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCC_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armclang.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armclang.h deleted file mode 100644 index 691141774..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armclang.h +++ /dev/null @@ -1,1503 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V5.4.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__ ) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) ) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) || \ - (defined (__ARM_ARCH_8_1M_MAIN__) && (__ARM_ARCH_8_1M_MAIN__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -#define __SADD8 __builtin_arm_sadd8 -#define __QADD8 __builtin_arm_qadd8 -#define __SHADD8 __builtin_arm_shadd8 -#define __UADD8 __builtin_arm_uadd8 -#define __UQADD8 __builtin_arm_uqadd8 -#define __UHADD8 __builtin_arm_uhadd8 -#define __SSUB8 __builtin_arm_ssub8 -#define __QSUB8 __builtin_arm_qsub8 -#define __SHSUB8 __builtin_arm_shsub8 -#define __USUB8 __builtin_arm_usub8 -#define __UQSUB8 __builtin_arm_uqsub8 -#define __UHSUB8 __builtin_arm_uhsub8 -#define __SADD16 __builtin_arm_sadd16 -#define __QADD16 __builtin_arm_qadd16 -#define __SHADD16 __builtin_arm_shadd16 -#define __UADD16 __builtin_arm_uadd16 -#define __UQADD16 __builtin_arm_uqadd16 -#define __UHADD16 __builtin_arm_uhadd16 -#define __SSUB16 __builtin_arm_ssub16 -#define __QSUB16 __builtin_arm_qsub16 -#define __SHSUB16 __builtin_arm_shsub16 -#define __USUB16 __builtin_arm_usub16 -#define __UQSUB16 __builtin_arm_uqsub16 -#define __UHSUB16 __builtin_arm_uhsub16 -#define __SASX __builtin_arm_sasx -#define __QASX __builtin_arm_qasx -#define __SHASX __builtin_arm_shasx -#define __UASX __builtin_arm_uasx -#define __UQASX __builtin_arm_uqasx -#define __UHASX __builtin_arm_uhasx -#define __SSAX __builtin_arm_ssax -#define __QSAX __builtin_arm_qsax -#define __SHSAX __builtin_arm_shsax -#define __USAX __builtin_arm_usax -#define __UQSAX __builtin_arm_uqsax -#define __UHSAX __builtin_arm_uhsax -#define __USAD8 __builtin_arm_usad8 -#define __USADA8 __builtin_arm_usada8 -#define __SSAT16 __builtin_arm_ssat16 -#define __USAT16 __builtin_arm_usat16 -#define __UXTB16 __builtin_arm_uxtb16 -#define __UXTAB16 __builtin_arm_uxtab16 -#define __SXTB16 __builtin_arm_sxtb16 -#define __SXTAB16 __builtin_arm_sxtab16 -#define __SMUAD __builtin_arm_smuad -#define __SMUADX __builtin_arm_smuadx -#define __SMLAD __builtin_arm_smlad -#define __SMLADX __builtin_arm_smladx -#define __SMLALD __builtin_arm_smlald -#define __SMLALDX __builtin_arm_smlaldx -#define __SMUSD __builtin_arm_smusd -#define __SMUSDX __builtin_arm_smusdx -#define __SMLSD __builtin_arm_smlsd -#define __SMLSDX __builtin_arm_smlsdx -#define __SMLSLD __builtin_arm_smlsld -#define __SMLSLDX __builtin_arm_smlsldx -#define __SEL __builtin_arm_sel -#define __QADD __builtin_arm_qadd -#define __QSUB __builtin_arm_qsub - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armclang_ltm.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armclang_ltm.h deleted file mode 100644 index 1e255d590..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_armclang_ltm.h +++ /dev/null @@ -1,1928 +0,0 @@ -/**************************************************************************//** - * @file cmsis_armclang_ltm.h - * @brief CMSIS compiler armclang (Arm Compiler 6) header file - * @version V1.5.3 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ - -#ifndef __CMSIS_ARMCLANG_H -#define __CMSIS_ARMCLANG_H - -#pragma clang system_header /* treat file as system include file */ - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE __inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static __inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma clang diagnostic push - #pragma clang diagnostic ignored "-Wpacked" -/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma clang diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START -#define __PROGRAM_START __main -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section("RESET"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL Image$$STACKSEAL$$ZI$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP __builtin_arm_nop - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI __builtin_arm_wfi - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE __builtin_arm_wfe - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV __builtin_arm_sev - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -#define __ISB() __builtin_arm_isb(0xF) - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -#define __DSB() __builtin_arm_dsb(0xF) - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -#define __DMB() __builtin_arm_dmb(0xF) - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV(value) __builtin_bswap32(value) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REV16(value) __ROR(__REV(value), 16) - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -#define __REVSH(value) (int16_t)__builtin_bswap16(value) - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -#define __RBIT __builtin_arm_rbit - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDREXB (uint8_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDREXH (uint16_t)__builtin_arm_ldrex - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDREXW (uint32_t)__builtin_arm_ldrex - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXB (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXH (uint32_t)__builtin_arm_strex - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STREXW (uint32_t)__builtin_arm_strex - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -#define __CLREX __builtin_arm_clrex - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT __builtin_arm_ssat - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT __builtin_arm_usat - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -#define __LDAEXB (uint8_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -#define __LDAEXH (uint16_t)__builtin_arm_ldaex - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -#define __LDAEX (uint32_t)__builtin_arm_ldaex - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXB (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEXH (uint32_t)__builtin_arm_stlex - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -#define __STLEX (uint32_t)__builtin_arm_stlex - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} -#endif - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -#ifndef __ARM_COMPAT_H -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} -#endif - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr -#else -#define __get_FPSCR() ((uint32_t)0U) -#endif - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#define __set_FPSCR __builtin_arm_set_fpscr -#else -#define __set_FPSCR(x) ((void)(x)) -#endif - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1,ARG2) \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -#define __USAT16(ARG1,ARG2) \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ - ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) - -#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ - ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#endif /* __CMSIS_ARMCLANG_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_compiler.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_compiler.h deleted file mode 100644 index adbf296f1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_compiler.h +++ /dev/null @@ -1,283 +0,0 @@ -/**************************************************************************//** - * @file cmsis_compiler.h - * @brief CMSIS compiler generic header file - * @version V5.1.0 - * @date 09. October 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_COMPILER_H -#define __CMSIS_COMPILER_H - -#include - -/* - * Arm Compiler 4/5 - */ -#if defined ( __CC_ARM ) - #include "cmsis_armcc.h" - - -/* - * Arm Compiler 6.6 LTM (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) - #include "cmsis_armclang_ltm.h" - - /* - * Arm Compiler above 6.10.1 (armclang) - */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) - #include "cmsis_armclang.h" - - -/* - * GNU Compiler - */ -#elif defined ( __GNUC__ ) - #include "cmsis_gcc.h" - - -/* - * IAR Compiler - */ -#elif defined ( __ICCARM__ ) - #include - - -/* - * TI Arm Compiler - */ -#elif defined ( __TI_ARM__ ) - #include - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __attribute__((packed)) - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed)) - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed)) - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) - #endif - #ifndef __RESTRICT - #define __RESTRICT __restrict - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * TASKING Compiler - */ -#elif defined ( __TASKING__ ) - /* - * The CMSIS functions have been implemented as intrinsics in the compiler. - * Please use "carm -?i" to get an up to date list of all intrinsics, - * Including the CMSIS ones. - */ - - #ifndef __ASM - #define __ASM __asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - #define __NO_RETURN __attribute__((noreturn)) - #endif - #ifndef __USED - #define __USED __attribute__((used)) - #endif - #ifndef __WEAK - #define __WEAK __attribute__((weak)) - #endif - #ifndef __PACKED - #define __PACKED __packed__ - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __packed__ - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION union __packed__ - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - struct __packed__ T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #define __ALIGNED(x) __align(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -/* - * COSMIC Compiler - */ -#elif defined ( __CSMC__ ) - #include - - #ifndef __ASM - #define __ASM _asm - #endif - #ifndef __INLINE - #define __INLINE inline - #endif - #ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline - #endif - #ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __STATIC_INLINE - #endif - #ifndef __NO_RETURN - // NO RETURN is automatically detected hence no warning here - #define __NO_RETURN - #endif - #ifndef __USED - #warning No compiler specific solution for __USED. __USED is ignored. - #define __USED - #endif - #ifndef __WEAK - #define __WEAK __weak - #endif - #ifndef __PACKED - #define __PACKED @packed - #endif - #ifndef __PACKED_STRUCT - #define __PACKED_STRUCT @packed struct - #endif - #ifndef __PACKED_UNION - #define __PACKED_UNION @packed union - #endif - #ifndef __UNALIGNED_UINT32 /* deprecated */ - @packed struct T_UINT32 { uint32_t v; }; - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) - #endif - #ifndef __UNALIGNED_UINT16_WRITE - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT16_READ - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) - #endif - #ifndef __UNALIGNED_UINT32_WRITE - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) - #endif - #ifndef __UNALIGNED_UINT32_READ - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) - #endif - #ifndef __ALIGNED - #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. - #define __ALIGNED(x) - #endif - #ifndef __RESTRICT - #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. - #define __RESTRICT - #endif - #ifndef __COMPILER_BARRIER - #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. - #define __COMPILER_BARRIER() (void)0 - #endif - - -#else - #error Unknown compiler. -#endif - - -#endif /* __CMSIS_COMPILER_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_gcc.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_gcc.h deleted file mode 100644 index 67bda4ef3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_gcc.h +++ /dev/null @@ -1,2211 +0,0 @@ -/**************************************************************************//** - * @file cmsis_gcc.h - * @brief CMSIS compiler GCC header file - * @version V5.4.1 - * @date 27. May 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef __CMSIS_GCC_H -#define __CMSIS_GCC_H - -/* ignore some GCC warnings */ -#pragma GCC diagnostic push -#pragma GCC diagnostic ignored "-Wsign-conversion" -#pragma GCC diagnostic ignored "-Wconversion" -#pragma GCC diagnostic ignored "-Wunused-parameter" - -/* Fallback for __has_builtin */ -#ifndef __has_builtin - #define __has_builtin(x) (0) -#endif - -/* CMSIS compiler specific defines */ -#ifndef __ASM - #define __ASM __asm -#endif -#ifndef __INLINE - #define __INLINE inline -#endif -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline -#endif -#ifndef __NO_RETURN - #define __NO_RETURN __attribute__((__noreturn__)) -#endif -#ifndef __USED - #define __USED __attribute__((used)) -#endif -#ifndef __WEAK - #define __WEAK __attribute__((weak)) -#endif -#ifndef __PACKED - #define __PACKED __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_STRUCT - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) -#endif -#ifndef __PACKED_UNION - #define __PACKED_UNION union __attribute__((packed, aligned(1))) -#endif -#ifndef __UNALIGNED_UINT32 /* deprecated */ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - struct __attribute__((packed)) T_UINT32 { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) -#endif -#ifndef __UNALIGNED_UINT16_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT16_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) -#endif -#ifndef __UNALIGNED_UINT32_WRITE - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) -#endif -#ifndef __UNALIGNED_UINT32_READ - #pragma GCC diagnostic push - #pragma GCC diagnostic ignored "-Wpacked" - #pragma GCC diagnostic ignored "-Wattributes" - __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; - #pragma GCC diagnostic pop - #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) -#endif -#ifndef __ALIGNED - #define __ALIGNED(x) __attribute__((aligned(x))) -#endif -#ifndef __RESTRICT - #define __RESTRICT __restrict -#endif -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -/* ######################### Startup and Lowlevel Init ######################## */ - -#ifndef __PROGRAM_START - -/** - \brief Initializes data and bss sections - \details This default implementations initialized all data and additional bss - sections relying on .copy.table and .zero.table specified properly - in the used linker script. - - */ -__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) -{ - extern void _start(void) __NO_RETURN; - - typedef struct { - uint32_t const* src; - uint32_t* dest; - uint32_t wlen; - } __copy_table_t; - - typedef struct { - uint32_t* dest; - uint32_t wlen; - } __zero_table_t; - - extern const __copy_table_t __copy_table_start__; - extern const __copy_table_t __copy_table_end__; - extern const __zero_table_t __zero_table_start__; - extern const __zero_table_t __zero_table_end__; - - for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = pTable->src[i]; - } - } - - for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { - for(uint32_t i=0u; iwlen; ++i) { - pTable->dest[i] = 0u; - } - } - - _start(); -} - -#define __PROGRAM_START __cmsis_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP __StackTop -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT __StackLimit -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __Vectors -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE __attribute__((used, section(".vectors"))) -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL __StackSeal -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - - -/* ########################## Core Instruction Access ######################### */ -/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface - Access to dedicated instructions - @{ -*/ - -/* Define macros for porting to both thumb1 and thumb2. - * For thumb1, use low register (r0-r7), specified by constraint "l" - * Otherwise, use general registers, specified by constraint "r" */ -#if defined (__thumb__) && !defined (__thumb2__) -#define __CMSIS_GCC_OUT_REG(r) "=l" (r) -#define __CMSIS_GCC_RW_REG(r) "+l" (r) -#define __CMSIS_GCC_USE_REG(r) "l" (r) -#else -#define __CMSIS_GCC_OUT_REG(r) "=r" (r) -#define __CMSIS_GCC_RW_REG(r) "+r" (r) -#define __CMSIS_GCC_USE_REG(r) "r" (r) -#endif - -/** - \brief No Operation - \details No Operation does nothing. This instruction can be used for code alignment purposes. - */ -#define __NOP() __ASM volatile ("nop") - -/** - \brief Wait For Interrupt - \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. - */ -#define __WFI() __ASM volatile ("wfi":::"memory") - - -/** - \brief Wait For Event - \details Wait For Event is a hint instruction that permits the processor to enter - a low-power state until one of a number of events occurs. - */ -#define __WFE() __ASM volatile ("wfe":::"memory") - - -/** - \brief Send Event - \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. - */ -#define __SEV() __ASM volatile ("sev") - - -/** - \brief Instruction Synchronization Barrier - \details Instruction Synchronization Barrier flushes the pipeline in the processor, - so that all instructions following the ISB are fetched from cache or memory, - after the instruction has been completed. - */ -__STATIC_FORCEINLINE void __ISB(void) -{ - __ASM volatile ("isb 0xF":::"memory"); -} - - -/** - \brief Data Synchronization Barrier - \details Acts as a special kind of Data Memory Barrier. - It completes when all explicit memory accesses before this instruction complete. - */ -__STATIC_FORCEINLINE void __DSB(void) -{ - __ASM volatile ("dsb 0xF":::"memory"); -} - - -/** - \brief Data Memory Barrier - \details Ensures the apparent order of the explicit memory operations before - and after the instruction, without ensuring their completion. - */ -__STATIC_FORCEINLINE void __DMB(void) -{ - __ASM volatile ("dmb 0xF":::"memory"); -} - - -/** - \brief Reverse byte order (32 bit) - \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) - return __builtin_bswap32(value); -#else - uint32_t result; - - __ASM ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) -{ - uint32_t result; - - __ASM ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -} - - -/** - \brief Reverse byte order (16 bit) - \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) -{ -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - return (int16_t)__builtin_bswap16(value); -#else - int16_t result; - - __ASM ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return result; -#endif -} - - -/** - \brief Rotate Right in unsigned value (32 bit) - \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. - \param [in] op1 Value to rotate - \param [in] op2 Number of Bits to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) -{ - op2 %= 32U; - if (op2 == 0U) - { - return op1; - } - return (op1 >> op2) | (op1 << (32U - op2)); -} - - -/** - \brief Breakpoint - \details Causes the processor to enter Debug state. - Debug tools can use this to investigate system state when the instruction at a particular address is reached. - \param [in] value is ignored by the processor. - If required, a debugger can use it to store additional information about the breakpoint. - */ -#define __BKPT(value) __ASM volatile ("bkpt "#value) - - -/** - \brief Reverse bit order of value - \details Reverses the bit order of the given value. - \param [in] value Value to reverse - \return Reversed value - */ -__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) -{ - uint32_t result; - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) - __ASM ("rbit %0, %1" : "=r" (result) : "r" (value) ); -#else - uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ - - result = value; /* r will be reversed bits of v; first get LSB of v */ - for (value >>= 1U; value != 0U; value >>= 1U) - { - result <<= 1U; - result |= value & 1U; - s--; - } - result <<= s; /* shift when v's highest bits are zero */ -#endif - return result; -} - - -/** - \brief Count leading zeros - \details Counts the number of leading zeros of a data value. - \param [in] value Value to count the leading zeros - \return number of leading zeros in value - */ -__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) -{ - /* Even though __builtin_clz produces a CLZ instruction on ARM, formally - __builtin_clz(0) is undefined behaviour, so handle this case specially. - This guarantees ARM-compatible results if happening to compile on a non-ARM - target, and ensures the compiler doesn't decide to activate any - optimisations using the logic "value was passed to __builtin_clz, so it - is non-zero". - ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a - single CLZ instruction. - */ - if (value == 0U) - { - return 32U; - } - return __builtin_clz(value); -} - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief LDR Exclusive (8 bit) - \details Executes a exclusive LDR instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (16 bit) - \details Executes a exclusive LDR instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDR Exclusive (32 bit) - \details Executes a exclusive LDR instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); - return(result); -} - - -/** - \brief STR Exclusive (8 bit) - \details Executes a exclusive STR instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (16 bit) - \details Executes a exclusive STR instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) -{ - uint32_t result; - - __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); - return(result); -} - - -/** - \brief STR Exclusive (32 bit) - \details Executes a exclusive STR instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) -{ - uint32_t result; - - __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); - return(result); -} - - -/** - \brief Remove the exclusive lock - \details Removes the exclusive lock which is created by LDREX. - */ -__STATIC_FORCEINLINE void __CLREX(void) -{ - __ASM volatile ("clrex" ::: "memory"); -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (1..32) - \return Saturated value - */ -#define __SSAT(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] ARG1 Value to be saturated - \param [in] ARG2 Bit position to saturate to (0..31) - \return Saturated value - */ -#define __USAT(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - - -/** - \brief Rotate Right with Extend (32 bit) - \details Moves each bit of a bitstring right by one bit. - The carry input is shifted in at the left end of the bitstring. - \param [in] value Value to rotate - \return Rotated value - */ -__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) -{ - uint32_t result; - - __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); - return(result); -} - - -/** - \brief LDRT Unprivileged (8 bit) - \details Executes a Unprivileged LDRT instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint8_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (16 bit) - \details Executes a Unprivileged LDRT instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) -{ - uint32_t result; - -#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) - __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); -#else - /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not - accepted by assembler. So has to use following less efficient pattern. - */ - __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); -#endif - return ((uint16_t) result); /* Add explicit type cast here */ -} - - -/** - \brief LDRT Unprivileged (32 bit) - \details Executes a Unprivileged LDRT instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); - return(result); -} - - -/** - \brief STRT Unprivileged (8 bit) - \details Executes a Unprivileged STRT instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (16 bit) - \details Executes a Unprivileged STRT instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); -} - - -/** - \brief STRT Unprivileged (32 bit) - \details Executes a Unprivileged STRT instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); -} - -#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - -/** - \brief Signed Saturate - \details Saturates a signed value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (1..32) - \return Saturated value - */ -__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) -{ - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; -} - -/** - \brief Unsigned Saturate - \details Saturates an unsigned value. - \param [in] value Value to be saturated - \param [in] sat Bit position to saturate to (0..31) - \return Saturated value - */ -__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) -{ - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; -} - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) -/** - \brief Load-Acquire (8 bit) - \details Executes a LDAB instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire (16 bit) - \details Executes a LDAH instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire (32 bit) - \details Executes a LDA instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release (8 bit) - \details Executes a STLB instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) -{ - __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (16 bit) - \details Executes a STLH instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) -{ - __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Store-Release (32 bit) - \details Executes a STL instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - */ -__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) -{ - __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); -} - - -/** - \brief Load-Acquire Exclusive (8 bit) - \details Executes a LDAB exclusive instruction for 8 bit value. - \param [in] ptr Pointer to data - \return value of type uint8_t at (*ptr) - */ -__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint8_t) result); -} - - -/** - \brief Load-Acquire Exclusive (16 bit) - \details Executes a LDAH exclusive instruction for 16 bit values. - \param [in] ptr Pointer to data - \return value of type uint16_t at (*ptr) - */ -__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return ((uint16_t) result); -} - - -/** - \brief Load-Acquire Exclusive (32 bit) - \details Executes a LDA exclusive instruction for 32 bit values. - \param [in] ptr Pointer to data - \return value of type uint32_t at (*ptr) - */ -__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (8 bit) - \details Executes a STLB exclusive instruction for 8 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (16 bit) - \details Executes a STLH exclusive instruction for 16 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - - -/** - \brief Store-Release Exclusive (32 bit) - \details Executes a STL exclusive instruction for 32 bit values. - \param [in] value Value to store - \param [in] ptr Pointer to location - \return 0 Function succeeded - \return 1 Function failed - */ -__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) -{ - uint32_t result; - - __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) : "memory" ); - return(result); -} - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - -/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ - - -/* ########################### Core Function Access ########################### */ -/** \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions - @{ - */ - -/** - \brief Enable IRQ Interrupts - \details Enables IRQ interrupts by clearing special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_irq(void) -{ - __ASM volatile ("cpsie i" : : : "memory"); -} - - -/** - \brief Disable IRQ Interrupts - \details Disables IRQ interrupts by setting special-purpose register PRIMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_irq(void) -{ - __ASM volatile ("cpsid i" : : : "memory"); -} - - -/** - \brief Get Control Register - \details Returns the content of the Control Register. - \return Control Register value - */ -__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Control Register (non-secure) - \details Returns the content of the non-secure Control Register when in secure mode. - \return non-secure Control Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Control Register - \details Writes the given value to the Control Register. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); - __ISB(); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Control Register (non-secure) - \details Writes the given value to the non-secure Control Register when in secure state. - \param [in] control Control Register value to set - */ -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); - __ISB(); -} -#endif - - -/** - \brief Get IPSR Register - \details Returns the content of the IPSR Register. - \return IPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_IPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get APSR Register - \details Returns the content of the APSR Register. - \return APSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_APSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, apsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get xPSR Register - \details Returns the content of the xPSR Register. - \return xPSR Register value - */ -__STATIC_FORCEINLINE uint32_t __get_xPSR(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); - return(result); -} - - -/** - \brief Get Process Stack Pointer - \details Returns the current value of the Process Stack Pointer (PSP). - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer (non-secure) - \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. - \return PSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Process Stack Pointer - \details Assigns the given value to the Process Stack Pointer (PSP). - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. - \param [in] topOfProcStack Process Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) -{ - __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); -} -#endif - - -/** - \brief Get Main Stack Pointer - \details Returns the current value of the Main Stack Pointer (MSP). - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSP(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer (non-secure) - \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. - \return MSP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Main Stack Pointer - \details Assigns the given value to the Main Stack Pointer (MSP). - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. - \param [in] topOfMainStack Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) -{ - __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); -} -#endif - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Stack Pointer (non-secure) - \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. - \return SP Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); - return(result); -} - - -/** - \brief Set Stack Pointer (non-secure) - \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. - \param [in] topOfStack Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) -{ - __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); -} -#endif - - -/** - \brief Get Priority Mask - \details Returns the current state of the priority mask bit from the Priority Mask Register. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Priority Mask (non-secure) - \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. - \return Priority Mask value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Priority Mask - \details Assigns the given value to the Priority Mask Register. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) -{ - __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Priority Mask (non-secure) - \details Assigns the given value to the non-secure Priority Mask Register when in secure state. - \param [in] priMask Priority Mask - */ -__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) -{ - __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); -} -#endif - - -#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) -/** - \brief Enable FIQ - \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __enable_fault_irq(void) -{ - __ASM volatile ("cpsie f" : : : "memory"); -} - - -/** - \brief Disable FIQ - \details Disables FIQ interrupts by setting special-purpose register FAULTMASK. - Can only be executed in Privileged modes. - */ -__STATIC_FORCEINLINE void __disable_fault_irq(void) -{ - __ASM volatile ("cpsid f" : : : "memory"); -} - - -/** - \brief Get Base Priority - \details Returns the current value of the Base Priority register. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Base Priority (non-secure) - \details Returns the current value of the non-secure Base Priority register when in secure state. - \return Base Priority register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Base Priority - \details Assigns the given value to the Base Priority register. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) -{ - __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Base Priority (non-secure) - \details Assigns the given value to the non-secure Base Priority register when in secure state. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); -} -#endif - - -/** - \brief Set Base Priority with condition - \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, - or the new value increases the BASEPRI priority level. - \param [in] basePri Base Priority value to set - */ -__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) -{ - __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); -} - - -/** - \brief Get Fault Mask - \details Returns the current value of the Fault Mask register. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); - return(result); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Fault Mask (non-secure) - \details Returns the current value of the non-secure Fault Mask register when in secure state. - \return Fault Mask register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) -{ - uint32_t result; - - __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); - return(result); -} -#endif - - -/** - \brief Set Fault Mask - \details Assigns the given value to the Fault Mask register. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Fault Mask (non-secure) - \details Assigns the given value to the non-secure Fault Mask register when in secure state. - \param [in] faultMask Fault Mask value to set - */ -__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) -{ - __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); -} -#endif - -#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ - (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ - (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ - - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - -/** - \brief Get Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim" : "=r" (result) ); - return result; -#endif -} - -#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Process Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \return PSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Process Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Process Stack Pointer (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. - \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)ProcStackPtrLimit; -#else - __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); -#endif -} -#endif - - -/** - \brief Get Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always in non-secure - mode. - - \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim" : "=r" (result) ); - return result; -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Get Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence zero is returned always. - - \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. - \return MSPLIM Register value - */ -__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - return 0U; -#else - uint32_t result; - __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); - return result; -#endif -} -#endif - - -/** - \brief Set Main Stack Pointer Limit - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored in non-secure - mode. - - \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). - \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set - */ -__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); -#endif -} - - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) -/** - \brief Set Main Stack Pointer Limit (non-secure) - Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure - Stack Pointer Limit register hence the write is silently ignored. - - \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. - \param [in] MainStackPtrLimit Main Stack Pointer value to set - */ -__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) -{ -#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)MainStackPtrLimit; -#else - __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); -#endif -} -#endif - -#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ - - -/** - \brief Get FPSCR - \details Returns the current value of the Floating Point Status/Control register. - \return Floating Point Status/Control register value - */ -__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_get_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - return __builtin_arm_get_fpscr(); -#else - uint32_t result; - - __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); - return(result); -#endif -#else - return(0U); -#endif -} - - -/** - \brief Set FPSCR - \details Assigns the given value to the Floating Point Status/Control register. - \param [in] fpscr Floating Point Status/Control value to set - */ -__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) -{ -#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) -#if __has_builtin(__builtin_arm_set_fpscr) -// Re-enable using built-in when GCC has been fixed -// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) - /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ - __builtin_arm_set_fpscr(fpscr); -#else - __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); -#endif -#else - (void)fpscr; -#endif -} - - -/*@} end of CMSIS_Core_RegAccFunctions */ - - -/* ################### Compiler specific Intrinsics ########################### */ -/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics - Access to dedicated SIMD instructions - @{ -*/ - -#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) - -__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#define __SSAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - int32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -#define __USAT16(ARG1, ARG2) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1); \ - __ASM volatile ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) : "cc" ); \ - __RES; \ - }) - -__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) -{ - uint32_t result; - - __ASM ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTB16_RORn(uint32_t op1, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtb16 %0, %1, ROR %2" : "=r" (result) : "r" (op1), "i" (rotate) ); - } else { - result = __SXTB16(__ROR(op1, rotate)) ; - } - return result; -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SXTAB16_RORn(uint32_t op1, uint32_t op2, uint32_t rotate) -{ - uint32_t result; - if (__builtin_constant_p(rotate) && ((rotate == 8U) || (rotate == 16U) || (rotate == 24U))) { - __ASM volatile ("sxtab16 %0, %1, %2, ROR %3" : "=r" (result) : "r" (op1) , "r" (op2) , "i" (rotate)); - } else { - result = __SXTAB16(op1, __ROR(op2, rotate)); - } - return result; -} - - -__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) -{ - uint32_t result; - - __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) -{ - union llreg_u{ - uint32_t w32[2]; - uint64_t w64; - } llr; - llr.w64 = acc; - -#ifndef __ARMEB__ /* Little endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); -#else /* Big endian */ - __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); -#endif - - return(llr.w64); -} - -__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) -{ - uint32_t result; - - __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - -__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) -{ - int32_t result; - - __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); - return(result); -} - - -#define __PKHBT(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - -#define __PKHTB(ARG1,ARG2,ARG3) \ -__extension__ \ -({ \ - uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ - if (ARG3 == 0) \ - __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ - else \ - __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ - __RES; \ - }) - - -__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) -{ - int32_t result; - - __ASM ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); - return(result); -} - -#endif /* (__ARM_FEATURE_DSP == 1) */ -/*@} end of group CMSIS_SIMD_intrinsics */ - - -#pragma GCC diagnostic pop - -#endif /* __CMSIS_GCC_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_iccarm.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_iccarm.h deleted file mode 100644 index 65b824b00..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_iccarm.h +++ /dev/null @@ -1,1002 +0,0 @@ -/**************************************************************************//** - * @file cmsis_iccarm.h - * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file - * @version V5.3.0 - * @date 14. April 2021 - ******************************************************************************/ - -//------------------------------------------------------------------------------ -// -// Copyright (c) 2017-2021 IAR Systems -// Copyright (c) 2017-2021 Arm Limited. All rights reserved. -// -// SPDX-License-Identifier: Apache-2.0 -// -// Licensed under the Apache License, Version 2.0 (the "License") -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// http://www.apache.org/licenses/LICENSE-2.0 -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -//------------------------------------------------------------------------------ - - -#ifndef __CMSIS_ICCARM_H__ -#define __CMSIS_ICCARM_H__ - -#ifndef __ICCARM__ - #error This file should only be compiled by ICCARM -#endif - -#pragma system_include - -#define __IAR_FT _Pragma("inline=forced") __intrinsic - -#if (__VER__ >= 8000000) - #define __ICCARM_V8 1 -#else - #define __ICCARM_V8 0 -#endif - -#ifndef __ALIGNED - #if __ICCARM_V8 - #define __ALIGNED(x) __attribute__((aligned(x))) - #elif (__VER__ >= 7080000) - /* Needs IAR language extensions */ - #define __ALIGNED(x) __attribute__((aligned(x))) - #else - #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. - #define __ALIGNED(x) - #endif -#endif - - -/* Define compiler macros for CPU architecture, used in CMSIS 5. - */ -#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ -/* Macros already defined */ -#else - #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' - #if __ARM_ARCH == 6 - #define __ARM_ARCH_6M__ 1 - #elif __ARM_ARCH == 7 - #if __ARM_FEATURE_DSP - #define __ARM_ARCH_7EM__ 1 - #else - #define __ARM_ARCH_7M__ 1 - #endif - #endif /* __ARM_ARCH */ - #endif /* __ARM_ARCH_PROFILE == 'M' */ -#endif - -/* Alternativ core deduction for older ICCARM's */ -#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ - !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) - #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) - #define __ARM_ARCH_6M__ 1 - #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) - #define __ARM_ARCH_7M__ 1 - #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) - #define __ARM_ARCH_7EM__ 1 - #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) - #define __ARM_ARCH_8M_BASE__ 1 - #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) - #define __ARM_ARCH_8M_MAIN__ 1 - #else - #error "Unknown target." - #endif -#endif - - - -#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 - #define __IAR_M0_FAMILY 1 -#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 - #define __IAR_M0_FAMILY 1 -#else - #define __IAR_M0_FAMILY 0 -#endif - - -#ifndef __ASM - #define __ASM __asm -#endif - -#ifndef __COMPILER_BARRIER - #define __COMPILER_BARRIER() __ASM volatile("":::"memory") -#endif - -#ifndef __INLINE - #define __INLINE inline -#endif - -#ifndef __NO_RETURN - #if __ICCARM_V8 - #define __NO_RETURN __attribute__((__noreturn__)) - #else - #define __NO_RETURN _Pragma("object_attribute=__noreturn") - #endif -#endif - -#ifndef __PACKED - #if __ICCARM_V8 - #define __PACKED __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED __packed - #endif -#endif - -#ifndef __PACKED_STRUCT - #if __ICCARM_V8 - #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_STRUCT __packed struct - #endif -#endif - -#ifndef __PACKED_UNION - #if __ICCARM_V8 - #define __PACKED_UNION union __attribute__((packed, aligned(1))) - #else - /* Needs IAR language extensions */ - #define __PACKED_UNION __packed union - #endif -#endif - -#ifndef __RESTRICT - #if __ICCARM_V8 - #define __RESTRICT __restrict - #else - /* Needs IAR language extensions */ - #define __RESTRICT restrict - #endif -#endif - -#ifndef __STATIC_INLINE - #define __STATIC_INLINE static inline -#endif - -#ifndef __FORCEINLINE - #define __FORCEINLINE _Pragma("inline=forced") -#endif - -#ifndef __STATIC_FORCEINLINE - #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE -#endif - -#ifndef __UNALIGNED_UINT16_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint16_t __iar_uint16_read(void const *ptr) -{ - return *(__packed uint16_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) -#endif - - -#ifndef __UNALIGNED_UINT16_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) -{ - *(__packed uint16_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32_READ -#pragma language=save -#pragma language=extended -__IAR_FT uint32_t __iar_uint32_read(void const *ptr) -{ - return *(__packed uint32_t*)(ptr); -} -#pragma language=restore -#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) -#endif - -#ifndef __UNALIGNED_UINT32_WRITE -#pragma language=save -#pragma language=extended -__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) -{ - *(__packed uint32_t*)(ptr) = val;; -} -#pragma language=restore -#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) -#endif - -#ifndef __UNALIGNED_UINT32 /* deprecated */ -#pragma language=save -#pragma language=extended -__packed struct __iar_u32 { uint32_t v; }; -#pragma language=restore -#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) -#endif - -#ifndef __USED - #if __ICCARM_V8 - #define __USED __attribute__((used)) - #else - #define __USED _Pragma("__root") - #endif -#endif - -#undef __WEAK /* undo the definition from DLib_Defaults.h */ -#ifndef __WEAK - #if __ICCARM_V8 - #define __WEAK __attribute__((weak)) - #else - #define __WEAK _Pragma("__weak") - #endif -#endif - -#ifndef __PROGRAM_START -#define __PROGRAM_START __iar_program_start -#endif - -#ifndef __INITIAL_SP -#define __INITIAL_SP CSTACK$$Limit -#endif - -#ifndef __STACK_LIMIT -#define __STACK_LIMIT CSTACK$$Base -#endif - -#ifndef __VECTOR_TABLE -#define __VECTOR_TABLE __vector_table -#endif - -#ifndef __VECTOR_TABLE_ATTRIBUTE -#define __VECTOR_TABLE_ATTRIBUTE @".intvec" -#endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#ifndef __STACK_SEAL -#define __STACK_SEAL STACKSEAL$$Base -#endif - -#ifndef __TZ_STACK_SEAL_SIZE -#define __TZ_STACK_SEAL_SIZE 8U -#endif - -#ifndef __TZ_STACK_SEAL_VALUE -#define __TZ_STACK_SEAL_VALUE 0xFEF5EDA5FEF5EDA5ULL -#endif - -__STATIC_FORCEINLINE void __TZ_set_STACKSEAL_S (uint32_t* stackTop) { - *((uint64_t *)stackTop) = __TZ_STACK_SEAL_VALUE; -} -#endif - -#ifndef __ICCARM_INTRINSICS_VERSION__ - #define __ICCARM_INTRINSICS_VERSION__ 0 -#endif - -#if __ICCARM_INTRINSICS_VERSION__ == 2 - - #if defined(__CLZ) - #undef __CLZ - #endif - #if defined(__REVSH) - #undef __REVSH - #endif - #if defined(__RBIT) - #undef __RBIT - #endif - #if defined(__SSAT) - #undef __SSAT - #endif - #if defined(__USAT) - #undef __USAT - #endif - - #include "iccarm_builtin.h" - - #define __disable_fault_irq __iar_builtin_disable_fiq - #define __disable_irq __iar_builtin_disable_interrupt - #define __enable_fault_irq __iar_builtin_enable_fiq - #define __enable_irq __iar_builtin_enable_interrupt - #define __arm_rsr __iar_builtin_rsr - #define __arm_wsr __iar_builtin_wsr - - - #define __get_APSR() (__arm_rsr("APSR")) - #define __get_BASEPRI() (__arm_rsr("BASEPRI")) - #define __get_CONTROL() (__arm_rsr("CONTROL")) - #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) - - #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) - #define __get_FPSCR() (__arm_rsr("FPSCR")) - #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) - #else - #define __get_FPSCR() ( 0 ) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #define __get_IPSR() (__arm_rsr("IPSR")) - #define __get_MSP() (__arm_rsr("MSP")) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __get_MSPLIM() (0U) - #else - #define __get_MSPLIM() (__arm_rsr("MSPLIM")) - #endif - #define __get_PRIMASK() (__arm_rsr("PRIMASK")) - #define __get_PSP() (__arm_rsr("PSP")) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __get_PSPLIM() (0U) - #else - #define __get_PSPLIM() (__arm_rsr("PSPLIM")) - #endif - - #define __get_xPSR() (__arm_rsr("xPSR")) - - #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) - #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) - -__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) -{ - __arm_wsr("CONTROL", control); - __iar_builtin_ISB(); -} - - #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) - #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - #define __set_MSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) - #endif - #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) - #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __set_PSPLIM(VALUE) ((void)(VALUE)) - #else - #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) - #endif - - #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) - -__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) -{ - __arm_wsr("CONTROL_NS", control); - __iar_builtin_ISB(); -} - - #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) - #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) - #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) - #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) - #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) - #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) - #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) - #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) - #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) - #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) - #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) - #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) - - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - #define __TZ_get_PSPLIM_NS() (0U) - #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) - #else - #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) - #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) - #endif - - #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) - #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) - - #define __NOP __iar_builtin_no_operation - - #define __CLZ __iar_builtin_CLZ - #define __CLREX __iar_builtin_CLREX - - #define __DMB __iar_builtin_DMB - #define __DSB __iar_builtin_DSB - #define __ISB __iar_builtin_ISB - - #define __LDREXB __iar_builtin_LDREXB - #define __LDREXH __iar_builtin_LDREXH - #define __LDREXW __iar_builtin_LDREX - - #define __RBIT __iar_builtin_RBIT - #define __REV __iar_builtin_REV - #define __REV16 __iar_builtin_REV16 - - __IAR_FT int16_t __REVSH(int16_t val) - { - return (int16_t) __iar_builtin_REVSH(val); - } - - #define __ROR __iar_builtin_ROR - #define __RRX __iar_builtin_RRX - - #define __SEV __iar_builtin_SEV - - #if !__IAR_M0_FAMILY - #define __SSAT __iar_builtin_SSAT - #endif - - #define __STREXB __iar_builtin_STREXB - #define __STREXH __iar_builtin_STREXH - #define __STREXW __iar_builtin_STREX - - #if !__IAR_M0_FAMILY - #define __USAT __iar_builtin_USAT - #endif - - #define __WFE __iar_builtin_WFE - #define __WFI __iar_builtin_WFI - - #if __ARM_MEDIA__ - #define __SADD8 __iar_builtin_SADD8 - #define __QADD8 __iar_builtin_QADD8 - #define __SHADD8 __iar_builtin_SHADD8 - #define __UADD8 __iar_builtin_UADD8 - #define __UQADD8 __iar_builtin_UQADD8 - #define __UHADD8 __iar_builtin_UHADD8 - #define __SSUB8 __iar_builtin_SSUB8 - #define __QSUB8 __iar_builtin_QSUB8 - #define __SHSUB8 __iar_builtin_SHSUB8 - #define __USUB8 __iar_builtin_USUB8 - #define __UQSUB8 __iar_builtin_UQSUB8 - #define __UHSUB8 __iar_builtin_UHSUB8 - #define __SADD16 __iar_builtin_SADD16 - #define __QADD16 __iar_builtin_QADD16 - #define __SHADD16 __iar_builtin_SHADD16 - #define __UADD16 __iar_builtin_UADD16 - #define __UQADD16 __iar_builtin_UQADD16 - #define __UHADD16 __iar_builtin_UHADD16 - #define __SSUB16 __iar_builtin_SSUB16 - #define __QSUB16 __iar_builtin_QSUB16 - #define __SHSUB16 __iar_builtin_SHSUB16 - #define __USUB16 __iar_builtin_USUB16 - #define __UQSUB16 __iar_builtin_UQSUB16 - #define __UHSUB16 __iar_builtin_UHSUB16 - #define __SASX __iar_builtin_SASX - #define __QASX __iar_builtin_QASX - #define __SHASX __iar_builtin_SHASX - #define __UASX __iar_builtin_UASX - #define __UQASX __iar_builtin_UQASX - #define __UHASX __iar_builtin_UHASX - #define __SSAX __iar_builtin_SSAX - #define __QSAX __iar_builtin_QSAX - #define __SHSAX __iar_builtin_SHSAX - #define __USAX __iar_builtin_USAX - #define __UQSAX __iar_builtin_UQSAX - #define __UHSAX __iar_builtin_UHSAX - #define __USAD8 __iar_builtin_USAD8 - #define __USADA8 __iar_builtin_USADA8 - #define __SSAT16 __iar_builtin_SSAT16 - #define __USAT16 __iar_builtin_USAT16 - #define __UXTB16 __iar_builtin_UXTB16 - #define __UXTAB16 __iar_builtin_UXTAB16 - #define __SXTB16 __iar_builtin_SXTB16 - #define __SXTAB16 __iar_builtin_SXTAB16 - #define __SMUAD __iar_builtin_SMUAD - #define __SMUADX __iar_builtin_SMUADX - #define __SMMLA __iar_builtin_SMMLA - #define __SMLAD __iar_builtin_SMLAD - #define __SMLADX __iar_builtin_SMLADX - #define __SMLALD __iar_builtin_SMLALD - #define __SMLALDX __iar_builtin_SMLALDX - #define __SMUSD __iar_builtin_SMUSD - #define __SMUSDX __iar_builtin_SMUSDX - #define __SMLSD __iar_builtin_SMLSD - #define __SMLSDX __iar_builtin_SMLSDX - #define __SMLSLD __iar_builtin_SMLSLD - #define __SMLSLDX __iar_builtin_SMLSLDX - #define __SEL __iar_builtin_SEL - #define __QADD __iar_builtin_QADD - #define __QSUB __iar_builtin_QSUB - #define __PKHBT __iar_builtin_PKHBT - #define __PKHTB __iar_builtin_PKHTB - #endif - -#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #define __CLZ __cmsis_iar_clz_not_active - #define __SSAT __cmsis_iar_ssat_not_active - #define __USAT __cmsis_iar_usat_not_active - #define __RBIT __cmsis_iar_rbit_not_active - #define __get_APSR __cmsis_iar_get_APSR_not_active - #endif - - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #define __get_FPSCR __cmsis_iar_get_FPSR_not_active - #define __set_FPSCR __cmsis_iar_set_FPSR_not_active - #endif - - #ifdef __INTRINSICS_INCLUDED - #error intrinsics.h is already included previously! - #endif - - #include - - #if __IAR_M0_FAMILY - /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ - #undef __CLZ - #undef __SSAT - #undef __USAT - #undef __RBIT - #undef __get_APSR - - __STATIC_INLINE uint8_t __CLZ(uint32_t data) - { - if (data == 0U) { return 32U; } - - uint32_t count = 0U; - uint32_t mask = 0x80000000U; - - while ((data & mask) == 0U) - { - count += 1U; - mask = mask >> 1U; - } - return count; - } - - __STATIC_INLINE uint32_t __RBIT(uint32_t v) - { - uint8_t sc = 31U; - uint32_t r = v; - for (v >>= 1U; v; v >>= 1U) - { - r <<= 1U; - r |= v & 1U; - sc--; - } - return (r << sc); - } - - __STATIC_INLINE uint32_t __get_APSR(void) - { - uint32_t res; - __asm("MRS %0,APSR" : "=r" (res)); - return res; - } - - #endif - - #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ - (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) - #undef __get_FPSCR - #undef __set_FPSCR - #define __get_FPSCR() (0) - #define __set_FPSCR(VALUE) ((void)VALUE) - #endif - - #pragma diag_suppress=Pe940 - #pragma diag_suppress=Pe177 - - #define __enable_irq __enable_interrupt - #define __disable_irq __disable_interrupt - #define __NOP __no_operation - - #define __get_xPSR __get_PSR - - #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) - - __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) - { - return __LDREX((unsigned long *)ptr); - } - - __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) - { - return __STREX(value, (unsigned long *)ptr); - } - #endif - - - /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - #if (__CORTEX_M >= 0x03) - - __IAR_FT uint32_t __RRX(uint32_t value) - { - uint32_t result; - __ASM volatile("RRX %0, %1" : "=r"(result) : "r" (value)); - return(result); - } - - __IAR_FT void __set_BASEPRI_MAX(uint32_t value) - { - __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); - } - - - #define __enable_fault_irq __enable_fiq - #define __disable_fault_irq __disable_fiq - - - #endif /* (__CORTEX_M >= 0x03) */ - - __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) - { - return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); - } - - #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - __IAR_FT uint32_t __get_MSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,MSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_MSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure MSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR MSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __get_PSPLIM(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __set_PSPLIM(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) - { - __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); - __iar_builtin_ISB(); - } - - __IAR_FT uint32_t __TZ_get_PSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PSP_NS(uint32_t value) - { - __asm volatile("MSR PSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_MSP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSP_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSP_NS(uint32_t value) - { - __asm volatile("MSR MSP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_SP_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,SP_NS" : "=r" (res)); - return res; - } - __IAR_FT void __TZ_set_SP_NS(uint32_t value) - { - __asm volatile("MSR SP_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) - { - __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) - { - __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) - { - __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); - } - - __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) - { - uint32_t res; - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - res = 0U; - #else - __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); - #endif - return res; - } - - __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) - { - #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ - (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) - // without main extensions, the non-secure PSPLIM is RAZ/WI - (void)value; - #else - __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); - #endif - } - - __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) - { - uint32_t res; - __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); - return res; - } - - __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) - { - __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); - } - - #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ - -#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) - -#if __IAR_M0_FAMILY - __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) - { - if ((sat >= 1U) && (sat <= 32U)) - { - const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); - const int32_t min = -1 - max ; - if (val > max) - { - return max; - } - else if (val < min) - { - return min; - } - } - return val; - } - - __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) - { - if (sat <= 31U) - { - const uint32_t max = ((1U << sat) - 1U); - if (val > (int32_t)max) - { - return max; - } - else if (val < 0) - { - return 0U; - } - } - return (uint32_t)val; - } -#endif - -#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ - - __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) - { - uint32_t res; - __ASM volatile ("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) - { - uint32_t res; - __ASM volatile ("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) - { - uint32_t res; - __ASM volatile ("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); - return res; - } - - __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) - { - __ASM volatile ("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) - { - __ASM volatile ("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); - } - - __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) - { - __ASM volatile ("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); - } - -#endif /* (__CORTEX_M >= 0x03) */ - -#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ - (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) - - - __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) - { - __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) - { - __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) - { - __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); - } - - __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint8_t)res); - } - - __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return ((uint16_t)res); - } - - __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - - __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) - { - uint32_t res; - __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); - return res; - } - -#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ - -#undef __IAR_FT -#undef __IAR_M0_FAMILY -#undef __ICCARM_V8 - -#pragma diag_default=Pe940 -#pragma diag_default=Pe177 - -#define __SXTB16_RORn(ARG1, ARG2) __SXTB16(__ROR(ARG1, ARG2)) - -#define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3)) - -#endif /* __CMSIS_ICCARM_H__ */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_version.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_version.h deleted file mode 100644 index 8b4765f18..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/cmsis_version.h +++ /dev/null @@ -1,39 +0,0 @@ -/**************************************************************************//** - * @file cmsis_version.h - * @brief CMSIS Core(M) Version definitions - * @version V5.0.5 - * @date 02. February 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2022 ARM Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CMSIS_VERSION_H -#define __CMSIS_VERSION_H - -/* CMSIS Version definitions */ -#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ -#define __CM_CMSIS_VERSION_SUB ( 6U) /*!< [15:0] CMSIS Core(M) sub version */ -#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ - __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ -#endif diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv81mml.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv81mml.h deleted file mode 100644 index 94128a1a7..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv81mml.h +++ /dev/null @@ -1,4228 +0,0 @@ -/**************************************************************************//** - * @file core_armv81mml.h - * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File - * @version V1.4.2 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_ARMV81MML_H_GENERIC -#define __CORE_ARMV81MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMV81MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS ARMV81MML definitions */ -#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (81U) /*!< Cortex-M Core */ - -#if defined ( __CC_ARM ) - #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV81MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV81MML_H_DEPENDANT -#define __CORE_ARMV81MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv81MML_REV - #define __ARMv81MML_REV 0x0000U - #warning "__ARMv81MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #if __FPU_PRESENT != 0U - #ifndef __FPU_DP - #define __FPU_DP 0U - #warning "__FPU_DP not defined in device header file; using default!" - #endif - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __PMU_PRESENT - #define __PMU_PRESENT 0U - #warning "__PMU_PRESENT not defined in device header file; using default!" - #endif - - #if __PMU_PRESENT != 0U - #ifndef __PMU_NUM_EVENTCNT - #define __PMU_NUM_EVENTCNT 2U - #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" - #elif (__PMU_NUM_EVENTCNT > 31 || __PMU_NUM_EVENTCNT < 2) - #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ - #endif - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv81MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ - uint32_t RESERVED4[14U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ - -#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ - -#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ - -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ - -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ - -#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ - -#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ - -#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ - -#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ - -#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ - -#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ - -#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ - -/* SCB Debug Feature Register 0 Definitions */ -#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ - -#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB RAS Fault Status Register Definitions */ -#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ - -#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ - -#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) - \brief Type definitions for the Performance Monitoring Unit (PMU) - @{ - */ - -/** - \brief Structure type to access the Performance Monitoring Unit (PMU). - */ -typedef struct -{ - __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ - uint32_t RESERVED1[224]; - __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ - uint32_t RESERVED3[480]; - __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ - uint32_t RESERVED4[7]; - __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ - uint32_t RESERVED5[7]; - __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ - uint32_t RESERVED6[7]; - __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ - uint32_t RESERVED7[7]; - __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ - uint32_t RESERVED8[7]; - __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ - uint32_t RESERVED9[7]; - __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ - uint32_t RESERVED10[79]; - __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ - uint32_t RESERVED11[108]; - __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ - __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ - uint32_t RESERVED12[3]; - __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ - __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ - uint32_t RESERVED13[3]; - __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ - __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ - __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ - __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ - __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ - __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ - __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ - __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -} PMU_Type; - -/** \brief PMU Event Counter Registers (0-30) Definitions */ - -#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ - -/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ - -#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ - -/** \brief PMU Count Enable Set Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ - -#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ - -#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ - -#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ - -#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ - -#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ - -#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ - -#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ - -#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ - -#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ - -#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ - -#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ - -#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ - -#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ - -#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ - -#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ - -#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ - -#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ - -#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ - -#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ - -#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ - -#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ - -#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ - -#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ - -#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ - -#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ - -#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ - -#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ - -#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ - -#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ - -#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ - -#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ - -/** \brief PMU Count Enable Clear Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ - -#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ - -#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ - -/** \brief PMU Interrupt Enable Set Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ - -/** \brief PMU Interrupt Enable Clear Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ - -#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ - -/** \brief PMU Overflow Flag Status Set Register Definitions */ - -#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ - -#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ - -#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ - -#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ - -#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ - -#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ - -#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ - -#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ - -#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ - -#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ - -#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ - -#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ - -#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ - -#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ - -#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ - -#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ - -#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ - -#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ - -#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ - -#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ - -#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ - -#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ - -#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ - -#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ - -#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ - -#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ - -#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ - -#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ - -#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ - -#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ - -#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ - -#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ - -/** \brief PMU Overflow Flag Status Clear Register Definitions */ - -#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ - -#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ - -#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ - -/** \brief PMU Software Increment Counter */ - -#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ - -#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ - -#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ - -#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ - -#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ - -#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ - -#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ - -#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ - -#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ - -#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ - -#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ - -#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ - -#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ - -#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ - -#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ - -#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ - -#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ - -#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ - -#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ - -#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ - -#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ - -#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ - -#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ - -#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ - -#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ - -#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ - -#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ - -#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ - -#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ - -#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ - -#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ - -/** \brief PMU Control Register Definitions */ - -#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ - -#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ - -#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ - -#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ - -/** \brief PMU Type Register Definitions */ - -#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ - -#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ - -#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ - -#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ - -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ - -/** \brief PMU Authentication Status Register Definitions */ - -#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ - -/*@} end of group CMSIS_PMU */ -#endif - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ - -#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ - -#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ - -#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ - -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ - -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ - -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ - -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ - -#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ - -#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ - -#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ - -#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ - -#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ - -#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ - -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ - -#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ - #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## PMU functions and events #################################### */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - -#include "pmu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - -/* ########################## MVE functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_MveFunctions MVE Functions - \brief Function that provides MVE type. - @{ - */ - -/** - \brief get MVE type - \details returns the MVE type - \returns - - \b 0: No Vector Extension (MVE) - - \b 1: Integer Vector Extension (MVE-I) - - \b 2: Floating-point Vector Extension (MVE-F) - */ -__STATIC_INLINE uint32_t SCB_GetMVEType(void) -{ - const uint32_t mvfr1 = FPU->MVFR1; - if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) - { - return 2U; - } - else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) - { - return 1U; - } - else - { - return 0U; - } -} - - -/*@} end of CMSIS_Core_MveFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV81MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv8mbl.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv8mbl.h deleted file mode 100644 index 932d3d188..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv8mbl.h +++ /dev/null @@ -1,2222 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mbl.h - * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 27. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_ARMV8MBL_H_GENERIC -#define __CORE_ARMV8MBL_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MBL - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (2U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MBL_H_DEPENDANT -#define __CORE_ARMV8MBL_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MBL_REV - #define __ARMv8MBL_REV 0x0000U - #warning "__ARMv8MBL_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MBL */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv8mml.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv8mml.h deleted file mode 100644 index c119fbf24..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_armv8mml.h +++ /dev/null @@ -1,3209 +0,0 @@ -/**************************************************************************//** - * @file core_armv8mml.h - * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File - * @version V5.2.3 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_ARMV8MML_H_GENERIC -#define __CORE_ARMV8MML_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_ARMv8MML - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS Armv8MML definitions */ -#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ - __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (80U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_ARMV8MML_H_DEPENDANT -#define __CORE_ARMV8MML_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __ARMv8MML_REV - #define __ARMv8MML_REV 0x0000U - #warning "__ARMv8MML_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group ARMv8MML */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_ARMV8MML_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm0.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm0.h deleted file mode 100644 index 6441ff341..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm0.h +++ /dev/null @@ -1,952 +0,0 @@ -/**************************************************************************//** - * @file core_cm0.h - * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File - * @version V5.0.8 - * @date 21. August 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0_H_GENERIC -#define __CORE_CM0_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M0 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0 definitions */ -#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ - __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0_H_DEPENDANT -#define __CORE_CM0_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0_REV - #define __CM0_REV 0x0000U - #warning "__CM0_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M0 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ - /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm0plus.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm0plus.h deleted file mode 100644 index 4e7179a61..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm0plus.h +++ /dev/null @@ -1,1087 +0,0 @@ -/**************************************************************************//** - * @file core_cm0plus.h - * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File - * @version V5.0.9 - * @date 21. August 2019 - ******************************************************************************/ -/* - * Copyright (c) 2009-2019 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM0PLUS_H_GENERIC -#define __CORE_CM0PLUS_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex-M0+ - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM0+ definitions */ -#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ - __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (0U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM0PLUS_H_DEPENDANT -#define __CORE_CM0PLUS_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM0PLUS_REV - #define __CM0PLUS_REV 0x0000U - #warning "__CM0PLUS_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex-M0+ */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M0+ header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - *(vectors + (int32_t)IRQn) = vector; /* use pointer arithmetic to access vector */ -#endif - /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -#else - uint32_t *vectors = (uint32_t *)(NVIC_USER_IRQ_OFFSET << 2); /* point to 1st user interrupt */ - return *(vectors + (int32_t)IRQn); /* use pointer arithmetic to access vector */ -#endif -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM0PLUS_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm1.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm1.h deleted file mode 100644 index 76b456974..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm1.h +++ /dev/null @@ -1,979 +0,0 @@ -/**************************************************************************//** - * @file core_cm1.h - * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File - * @version V1.0.1 - * @date 12. November 2018 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM1_H_GENERIC -#define __CORE_CM1_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M1 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM1 definitions */ -#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ - __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (1U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM1_H_DEPENDANT -#define __CORE_CM1_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM1_REV - #define __CM1_REV 0x0100U - #warning "__CM1_REV not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M1 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - uint32_t RESERVED0; - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ - -#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ -#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the Cortex-M1 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - Address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)0x0U; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)0x0U; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM1_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm23.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm23.h deleted file mode 100644 index 55fff9950..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm23.h +++ /dev/null @@ -1,2297 +0,0 @@ -/**************************************************************************//** - * @file core_cm23.h - * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File - * @version V5.1.0 - * @date 11. February 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM23_H_GENERIC -#define __CORE_CM23_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M23 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS definitions */ -#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ - __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (23U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM23_H_DEPENDANT -#define __CORE_CM23_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM23_REV - #define __CM23_REV 0x0000U - #warning "__CM23_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif - - #ifndef __ETM_PRESENT - #define __ETM_PRESENT 0U - #warning "__ETM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MTB_PRESENT - #define __MTB_PRESENT 0U - #warning "__MTB_PRESENT not defined in device header file; using default!" - #endif - -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M23 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ -#else - uint32_t RESERVED0; -#endif - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED1; - __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - uint32_t RESERVED0[6U]; - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - uint32_t RESERVED0[7U]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 1U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#endif -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register */ -#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: DWTENA Position */ -#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< \deprecated CoreDebug DEMCR: DWTENA Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - -#define __NVIC_SetPriorityGrouping(X) (void)(X) -#define __NVIC_GetPriorityGrouping() (0U) - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - If VTOR is not present address 0 must be mapped to SRAM. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ -#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) - uint32_t *vectors = (uint32_t *)SCB->VTOR; -#else - uint32_t *vectors = (uint32_t *)0x0U; -#endif - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM23_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm3.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm3.h deleted file mode 100644 index 74fb87e5c..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm3.h +++ /dev/null @@ -1,1943 +0,0 @@ -/**************************************************************************//** - * @file core_cm3.h - * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File - * @version V5.1.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM3_H_GENERIC -#define __CORE_CM3_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M3 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM3 definitions */ -#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ - __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (3U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM3_H_DEPENDANT -#define __CORE_CM3_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM3_REV - #define __CM3_REV 0x0200U - #warning "__CM3_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M3 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#else -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ -#endif - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -#else - uint32_t RESERVED1[1U]; -#endif -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ -#endif - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM3_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm33.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm33.h deleted file mode 100644 index 18a2e6fb0..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm33.h +++ /dev/null @@ -1,3277 +0,0 @@ -/**************************************************************************//** - * @file core_cm33.h - * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File - * @version V5.2.3 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM33_H_GENERIC -#define __CORE_CM33_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M33 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM33 definitions */ -#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ - __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (33U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM33_H_DEPENDANT -#define __CORE_CM33_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM33_REV - #define __CM33_REV 0x0000U - #warning "__CM33_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M33 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM33_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm35p.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm35p.h deleted file mode 100644 index 3843d9542..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm35p.h +++ /dev/null @@ -1,3277 +0,0 @@ -/**************************************************************************//** - * @file core_cm35p.h - * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File - * @version V1.1.3 - * @date 13. October 2021 - ******************************************************************************/ -/* - * Copyright (c) 2018-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM35P_H_GENERIC -#define __CORE_CM35P_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M35P - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM35P definitions */ -#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ - __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (35U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM35P_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM35P_H_DEPENDANT -#define __CORE_CM35P_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM35P_REV - #define __CM35P_REV 0x0000U - #warning "__CM35P_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M35P */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM35P_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm4.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm4.h deleted file mode 100644 index e21cd1492..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm4.h +++ /dev/null @@ -1,2129 +0,0 @@ -/**************************************************************************//** - * @file core_cm4.h - * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File - * @version V5.1.2 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM4_H_GENERIC -#define __CORE_CM4_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M4 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM4 definitions */ -#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ - __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (4U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM4_H_DEPENDANT -#define __CORE_CM4_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM4_REV - #define __CM4_REV 0x0000U - #warning "__CM4_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M4 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ -#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ - -#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ -#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM4_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm55.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm55.h deleted file mode 100644 index faa30ce36..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm55.h +++ /dev/null @@ -1,4817 +0,0 @@ -/**************************************************************************//** - * @file core_cm55.h - * @brief CMSIS Cortex-M55 Core Peripheral Access Layer Header File - * @version V1.2.4 - * @date 21. April 2022 - ******************************************************************************/ -/* - * Copyright (c) 2018-2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM55_H_GENERIC -#define __CORE_CM55_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M55 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM55 definitions */ -#define __CM55_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM55_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM55_CMSIS_VERSION ((__CM55_CMSIS_VERSION_MAIN << 16U) | \ - __CM55_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (55U) /*!< Cortex-M Core */ - -#if defined ( __CC_ARM ) - #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM55_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM55_H_DEPENDANT -#define __CORE_CM55_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM55_REV - #define __CM55_REV 0x0000U - #warning "__CM55_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #if __FPU_PRESENT != 0U - #ifndef __FPU_DP - #define __FPU_DP 0U - #warning "__FPU_DP not defined in device header file; using default!" - #endif - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __PMU_PRESENT - #define __PMU_PRESENT 0U - #warning "__PMU_PRESENT not defined in device header file; using default!" - #endif - - #if __PMU_PRESENT != 0U - #ifndef __PMU_NUM_EVENTCNT - #define __PMU_NUM_EVENTCNT 8U - #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" - #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) - #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ - #endif - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M55 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core EWIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core PMU Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ - uint32_t RESERVED4[14U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ - -#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ - -#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ - -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ - -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ - -#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ - -#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ - -#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ - -#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ - -#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ - -#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ - -#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ - -/* SCB Debug Feature Register 0 Definitions */ -#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ - -#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB RAS Fault Status Register Definitions */ -#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ - -#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ - -#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ICB Implementation Control Block register (ICB) - \brief Type definitions for the Implementation Control Block Register - @{ - */ - -/** - \brief Structure type to access the Implementation Control Block (ICB). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} ICB_Type; - -/* Auxiliary Control Register Definitions */ -#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ -#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ - -#define ICB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ -#define ICB_ACTLR_DISDI_Msk (3UL << ICB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ - -#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ -#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ - -#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ -#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ - -#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ -#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ - -#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define ICB_ACTLR_DISOLAP_Pos 7U /*!< ACTLR: DISOLAP Position */ -#define ICB_ACTLR_DISOLAP_Msk (1UL << ICB_ACTLR_DISOLAP_Pos) /*!< ACTLR: DISOLAP Mask */ - -#define ICB_ACTLR_DISOLAPS_Pos 6U /*!< ACTLR: DISOLAPS Position */ -#define ICB_ACTLR_DISOLAPS_Msk (1UL << ICB_ACTLR_DISOLAPS_Pos) /*!< ACTLR: DISOLAPS Mask */ - -#define ICB_ACTLR_DISLOBR_Pos 5U /*!< ACTLR: DISLOBR Position */ -#define ICB_ACTLR_DISLOBR_Msk (1UL << ICB_ACTLR_DISLOBR_Pos) /*!< ACTLR: DISLOBR Mask */ - -#define ICB_ACTLR_DISLO_Pos 4U /*!< ACTLR: DISLO Position */ -#define ICB_ACTLR_DISLO_Msk (1UL << ICB_ACTLR_DISLO_Pos) /*!< ACTLR: DISLO Mask */ - -#define ICB_ACTLR_DISLOLEP_Pos 3U /*!< ACTLR: DISLOLEP Position */ -#define ICB_ACTLR_DISLOLEP_Msk (1UL << ICB_ACTLR_DISLOLEP_Pos) /*!< ACTLR: DISLOLEP Mask */ - -#define ICB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define ICB_ACTLR_DISFOLD_Msk (1UL << ICB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -/* Interrupt Controller Type Register Definitions */ -#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_ICB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) - @{ - */ - -/** - \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). - */ -typedef struct -{ - __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ - __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ - uint32_t RESERVED1[2U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ - __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ - uint32_t RESERVED2[313U]; - __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ - __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ - uint32_t RESERVED3[2U]; - __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ - uint32_t RESERVED4[44U]; - __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ - __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ - uint32_t RESERVED5[2U]; - __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ -} MemSysCtl_Type; - -/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ -#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ -#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ - -#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ -#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ - -#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ -#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ - -#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ -#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ - -#define MEMSYSCTL_MSCR_TECCCHKDIS_Pos 4U /*!< MEMSYSCTL MSCR: TECCCHKDIS Position */ -#define MEMSYSCTL_MSCR_TECCCHKDIS_Msk (0x1UL << MEMSYSCTL_MSCR_TECCCHKDIS_Pos) /*!< MEMSYSCTL MSCR: TECCCHKDIS Mask */ - -#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ -#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ - -#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ -#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ - -#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ -#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ - -/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ -#define MEMSYSCTL_PFCR_MAX_OS_Pos 7U /*!< MEMSYSCTL PFCR: MAX_OS Position */ -#define MEMSYSCTL_PFCR_MAX_OS_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_OS_Pos) /*!< MEMSYSCTL PFCR: MAX_OS Mask */ - -#define MEMSYSCTL_PFCR_MAX_LA_Pos 4U /*!< MEMSYSCTL PFCR: MAX_LA Position */ -#define MEMSYSCTL_PFCR_MAX_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MAX_LA_Pos) /*!< MEMSYSCTL PFCR: MAX_LA Mask */ - -#define MEMSYSCTL_PFCR_MIN_LA_Pos 1U /*!< MEMSYSCTL PFCR: MIN_LA Position */ -#define MEMSYSCTL_PFCR_MIN_LA_Msk (0x7UL << MEMSYSCTL_PFCR_MIN_LA_Pos) /*!< MEMSYSCTL PFCR: MIN_LA Mask */ - -#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ -#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ - -/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ -#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ -#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ - -#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ -#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ - -/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ -#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ -#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ - -#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ -#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ - -/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ -#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ -#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ - -#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ -#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ - -/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ - -/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ - - -/*@}*/ /* end of group MemSysCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PwrModCtl_Type Power Mode Control Registers - \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) - @{ - */ - -/** - \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). - */ -typedef struct -{ - __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ - __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ -} PwrModCtl_Type; - -/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ - -/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ - -/*@}*/ /* end of group PwrModCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup EWIC_Type External Wakeup Interrupt Controller Registers - \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) - @{ - */ - -/** - \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). - */ -typedef struct -{ - __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ - uint32_t RESERVED0[31U]; - __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ - __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ -} EWIC_Type; - -/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ -#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ -#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ - -#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ -#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ - -#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ -#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ -#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ -#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ - -#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ -#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ - -#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ -#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ -#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ -#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ - -/*@}*/ /* end of group EWIC_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Error Banking Registers (ERRBNK) - @{ - */ - -/** - \brief Structure type to access the Error Banking Registers (ERRBNK). - */ -typedef struct -{ - __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ - __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ - uint32_t RESERVED0[2U]; - __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ - __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ - uint32_t RESERVED1[2U]; - __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ -} ErrBnk_Type; - -/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ -#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ -#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ - -#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ -#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ - -#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ -#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ - -#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ -#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ - -#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ -#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ - -/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ -#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ -#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ - -#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ -#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ - -#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ -#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ - -#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ -#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ - -#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ -#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ -#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ -#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ - -#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ -#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ - -#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ -#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ - -#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ -#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ - -#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ -#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ - -#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ -#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ -#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ -#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ - -#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ -#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ - -#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ -#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ - -#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ -#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ - -#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ -#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ - -#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ -#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ -#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ -#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ - -#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ -#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ - -#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ -#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ - -#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ -#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ - -#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ -#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ - -#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ -#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ - -#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ -#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ -#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ -#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ - -#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ -#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ - -#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ -#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ - -#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ -#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ - -#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ -#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ - -#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ -#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ - -#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ -#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ - -/*@}*/ /* end of group ErrBnk_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) - @{ - */ - -/** - \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). - */ -typedef struct -{ - __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ - __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ -} PrcCfgInf_Type; - -/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ - -/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ - -/*@}*/ /* end of group PrcCfgInf_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup STL_Type Software Test Library Observation Registers - \brief Type definitions for the Software Test Library Observation Registerss (STL) - @{ - */ - -/** - \brief Structure type to access the Software Test Library Observation Registerss (STL). - */ -typedef struct -{ - __IM uint32_t STLNVICPENDOR; /*!< Offset: 0x000 (R/ ) NVIC Pending Priority Tree Register */ - __IM uint32_t STLNVICACTVOR; /*!< Offset: 0x004 (R/ ) NVIC Active Priority Tree Register */ - uint32_t RESERVED0[2U]; - __OM uint32_t STLIDMPUSR; /*!< Offset: 0x010 ( /W) MPU Sanple Register */ - __IM uint32_t STLIMPUOR; /*!< Offset: 0x014 (R/ ) MPU Region Hit Register */ - __IM uint32_t STLD0MPUOR; /*!< Offset: 0x018 (R/ ) MPU Memory Attributes Register 0 */ - __IM uint32_t STLD1MPUOR; /*!< Offset: 0x01C (R/ ) MPU Memory Attributes Register 1 */ - -} STL_Type; - -/* STL Software Test Library Observation Register (STLNVICPENDOR) Definitions */ -#define STL_STLNVICPENDOR_VALID_Pos 18U /*!< STL STLNVICPENDOR: VALID Position */ -#define STL_STLNVICPENDOR_VALID_Msk (0x1UL << STL_STLNVICPENDOR_VALID_Pos) /*!< STL STLNVICPENDOR: VALID Mask */ - -#define STL_STLNVICPENDOR_TARGET_Pos 17U /*!< STL STLNVICPENDOR: TARGET Position */ -#define STL_STLNVICPENDOR_TARGET_Msk (0x1UL << STL_STLNVICPENDOR_TARGET_Pos) /*!< STL STLNVICPENDOR: TARGET Mask */ - -#define STL_STLNVICPENDOR_PRIORITY_Pos 9U /*!< STL STLNVICPENDOR: PRIORITY Position */ -#define STL_STLNVICPENDOR_PRIORITY_Msk (0xFFUL << STL_STLNVICPENDOR_PRIORITY_Pos) /*!< STL STLNVICPENDOR: PRIORITY Mask */ - -#define STL_STLNVICPENDOR_INTNUM_Pos 0U /*!< STL STLNVICPENDOR: INTNUM Position */ -#define STL_STLNVICPENDOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICPENDOR_INTNUM_Pos*/) /*!< STL STLNVICPENDOR: INTNUM Mask */ - -/* STL Software Test Library Observation Register (STLNVICACTVOR) Definitions */ -#define STL_STLNVICACTVOR_VALID_Pos 18U /*!< STL STLNVICACTVOR: VALID Position */ -#define STL_STLNVICACTVOR_VALID_Msk (0x1UL << STL_STLNVICACTVOR_VALID_Pos) /*!< STL STLNVICACTVOR: VALID Mask */ - -#define STL_STLNVICACTVOR_TARGET_Pos 17U /*!< STL STLNVICACTVOR: TARGET Position */ -#define STL_STLNVICACTVOR_TARGET_Msk (0x1UL << STL_STLNVICACTVOR_TARGET_Pos) /*!< STL STLNVICACTVOR: TARGET Mask */ - -#define STL_STLNVICACTVOR_PRIORITY_Pos 9U /*!< STL STLNVICACTVOR: PRIORITY Position */ -#define STL_STLNVICACTVOR_PRIORITY_Msk (0xFFUL << STL_STLNVICACTVOR_PRIORITY_Pos) /*!< STL STLNVICACTVOR: PRIORITY Mask */ - -#define STL_STLNVICACTVOR_INTNUM_Pos 0U /*!< STL STLNVICACTVOR: INTNUM Position */ -#define STL_STLNVICACTVOR_INTNUM_Msk (0x1FFUL /*<< STL_STLNVICACTVOR_INTNUM_Pos*/) /*!< STL STLNVICACTVOR: INTNUM Mask */ - -/* STL Software Test Library Observation Register (STLIDMPUSR) Definitions */ -#define STL_STLIDMPUSR_ADDR_Pos 5U /*!< STL STLIDMPUSR: ADDR Position */ -#define STL_STLIDMPUSR_ADDR_Msk (0x7FFFFFFUL << STL_STLIDMPUSR_ADDR_Pos) /*!< STL STLIDMPUSR: ADDR Mask */ - -#define STL_STLIDMPUSR_INSTR_Pos 2U /*!< STL STLIDMPUSR: INSTR Position */ -#define STL_STLIDMPUSR_INSTR_Msk (0x1UL << STL_STLIDMPUSR_INSTR_Pos) /*!< STL STLIDMPUSR: INSTR Mask */ - -#define STL_STLIDMPUSR_DATA_Pos 1U /*!< STL STLIDMPUSR: DATA Position */ -#define STL_STLIDMPUSR_DATA_Msk (0x1UL << STL_STLIDMPUSR_DATA_Pos) /*!< STL STLIDMPUSR: DATA Mask */ - -/* STL Software Test Library Observation Register (STLIMPUOR) Definitions */ -#define STL_STLIMPUOR_HITREGION_Pos 9U /*!< STL STLIMPUOR: HITREGION Position */ -#define STL_STLIMPUOR_HITREGION_Msk (0xFFUL << STL_STLIMPUOR_HITREGION_Pos) /*!< STL STLIMPUOR: HITREGION Mask */ - -#define STL_STLIMPUOR_ATTR_Pos 0U /*!< STL STLIMPUOR: ATTR Position */ -#define STL_STLIMPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLIMPUOR_ATTR_Pos*/) /*!< STL STLIMPUOR: ATTR Mask */ - -/* STL Software Test Library Observation Register (STLD0MPUOR) Definitions */ -#define STL_STLD0MPUOR_HITREGION_Pos 9U /*!< STL STLD0MPUOR: HITREGION Position */ -#define STL_STLD0MPUOR_HITREGION_Msk (0xFFUL << STL_STLD0MPUOR_HITREGION_Pos) /*!< STL STLD0MPUOR: HITREGION Mask */ - -#define STL_STLD0MPUOR_ATTR_Pos 0U /*!< STL STLD0MPUOR: ATTR Position */ -#define STL_STLD0MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD0MPUOR_ATTR_Pos*/) /*!< STL STLD0MPUOR: ATTR Mask */ - -/* STL Software Test Library Observation Register (STLD1MPUOR) Definitions */ -#define STL_STLD1MPUOR_HITREGION_Pos 9U /*!< STL STLD1MPUOR: HITREGION Position */ -#define STL_STLD1MPUOR_HITREGION_Msk (0xFFUL << STL_STLD1MPUOR_HITREGION_Pos) /*!< STL STLD1MPUOR: HITREGION Mask */ - -#define STL_STLD1MPUOR_ATTR_Pos 0U /*!< STL STLD1MPUOR: ATTR Position */ -#define STL_STLD1MPUOR_ATTR_Msk (0x1FFUL /*<< STL_STLD1MPUOR_ATTR_Pos*/) /*!< STL STLD1MPUOR: ATTR Mask */ - -/*@}*/ /* end of group STL_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) - \brief Type definitions for the Performance Monitoring Unit (PMU) - @{ - */ - -/** - \brief Structure type to access the Performance Monitoring Unit (PMU). - */ -typedef struct -{ - __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ - uint32_t RESERVED1[224]; - __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ - uint32_t RESERVED3[480]; - __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ - uint32_t RESERVED4[7]; - __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ - uint32_t RESERVED5[7]; - __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ - uint32_t RESERVED6[7]; - __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ - uint32_t RESERVED7[7]; - __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ - uint32_t RESERVED8[7]; - __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ - uint32_t RESERVED9[7]; - __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ - uint32_t RESERVED10[79]; - __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ - uint32_t RESERVED11[108]; - __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ - __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ - uint32_t RESERVED12[3]; - __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ - __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ - uint32_t RESERVED13[3]; - __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ - __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ - __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ - __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ - __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ - __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ - __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ - __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -} PMU_Type; - -/** \brief PMU Event Counter Registers (0-30) Definitions */ - -#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ - -/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ - -#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ - -/** \brief PMU Count Enable Set Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ - -#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ - -#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ - -#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ - -#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ - -#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ - -#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ - -#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ - -#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ - -#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ - -#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ - -#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ - -#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ - -#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ - -#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ - -#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ - -#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ - -#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ - -#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ - -#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ - -#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ - -#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ - -#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ - -#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ - -#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ - -#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ - -#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ - -#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ - -#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ - -#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ - -#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ - -#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ - -/** \brief PMU Count Enable Clear Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ - -#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ - -#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ - -/** \brief PMU Interrupt Enable Set Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ - -/** \brief PMU Interrupt Enable Clear Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ - -#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ - -/** \brief PMU Overflow Flag Status Set Register Definitions */ - -#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ - -#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ - -#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ - -#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ - -#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ - -#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ - -#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ - -#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ - -#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ - -#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ - -#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ - -#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ - -#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ - -#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ - -#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ - -#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ - -#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ - -#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ - -#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ - -#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ - -#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ - -#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ - -#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ - -#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ - -#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ - -#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ - -#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ - -#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ - -#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ - -#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ - -#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ - -#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ - -/** \brief PMU Overflow Flag Status Clear Register Definitions */ - -#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ - -#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ - -#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ - -/** \brief PMU Software Increment Counter */ - -#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ - -#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ - -#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ - -#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ - -#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ - -#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ - -#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ - -#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ - -#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ - -#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ - -#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ - -#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ - -#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ - -#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ - -#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ - -#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ - -#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ - -#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ - -#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ - -#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ - -#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ - -#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ - -#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ - -#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ - -#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ - -#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ - -#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ - -#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ - -#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ - -#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ - -#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ - -/** \brief PMU Control Register Definitions */ - -#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ - -#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ - -#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ - -#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ - -/** \brief PMU Type Register Definitions */ - -#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ - -#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ - -#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ - -#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ - -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ - -/** \brief PMU Authentication Status Register Definitions */ - -#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ - - -/*@} end of group CMSIS_PMU */ -#endif - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ - -#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ - -#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ - -#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ - -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ - -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ - -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ - -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ - -#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ - -#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ - -#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ - -#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ - -#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ - -#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ - -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ - -#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ - #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ - #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ - #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ - #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ - #define STL_BASE (0xE001E800UL) /*!< Software Test Library Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ - #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ - #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ - #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ - #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ - #define STL ((STL_Type *) STL_BASE ) /*!< Software Test Library configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ - #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ -#define ID_ADR (ID_AFR) /*!< SCB Auxiliary Feature Register */ - -/* 'SCnSCB' is deprecated and replaced by 'ICB' */ -typedef ICB_Type SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISCRITAXIRUW_Pos (ICB_ACTLR_DISCRITAXIRUW_Pos) -#define SCnSCB_ACTLR_DISCRITAXIRUW_Msk (ICB_ACTLR_DISCRITAXIRUW_Msk) - -#define SCnSCB_ACTLR_DISDI_Pos (ICB_ACTLR_DISDI_Pos) -#define SCnSCB_ACTLR_DISDI_Msk (ICB_ACTLR_DISDI_Msk) - -#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos (ICB_ACTLR_DISCRITAXIRUR_Pos) -#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (ICB_ACTLR_DISCRITAXIRUR_Msk) - -#define SCnSCB_ACTLR_EVENTBUSEN_Pos (ICB_ACTLR_EVENTBUSEN_Pos) -#define SCnSCB_ACTLR_EVENTBUSEN_Msk (ICB_ACTLR_EVENTBUSEN_Msk) - -#define SCnSCB_ACTLR_EVENTBUSEN_S_Pos (ICB_ACTLR_EVENTBUSEN_S_Pos) -#define SCnSCB_ACTLR_EVENTBUSEN_S_Msk (ICB_ACTLR_EVENTBUSEN_S_Msk) - -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos (ICB_ACTLR_DISITMATBFLUSH_Pos) -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (ICB_ACTLR_DISITMATBFLUSH_Msk) - -#define SCnSCB_ACTLR_DISNWAMODE_Pos (ICB_ACTLR_DISNWAMODE_Pos) -#define SCnSCB_ACTLR_DISNWAMODE_Msk (ICB_ACTLR_DISNWAMODE_Msk) - -#define SCnSCB_ACTLR_FPEXCODIS_Pos (ICB_ACTLR_FPEXCODIS_Pos) -#define SCnSCB_ACTLR_FPEXCODIS_Msk (ICB_ACTLR_FPEXCODIS_Msk) - -#define SCnSCB_ACTLR_DISOLAP_Pos (ICB_ACTLR_DISOLAP_Pos) -#define SCnSCB_ACTLR_DISOLAP_Msk (ICB_ACTLR_DISOLAP_Msk) - -#define SCnSCB_ACTLR_DISOLAPS_Pos (ICB_ACTLR_DISOLAPS_Pos) -#define SCnSCB_ACTLR_DISOLAPS_Msk (ICB_ACTLR_DISOLAPS_Msk) - -#define SCnSCB_ACTLR_DISLOBR_Pos (ICB_ACTLR_DISLOBR_Pos) -#define SCnSCB_ACTLR_DISLOBR_Msk (ICB_ACTLR_DISLOBR_Msk) - -#define SCnSCB_ACTLR_DISLO_Pos (ICB_ACTLR_DISLO_Pos) -#define SCnSCB_ACTLR_DISLO_Msk (ICB_ACTLR_DISLO_Msk) - -#define SCnSCB_ACTLR_DISLOLEP_Pos (ICB_ACTLR_DISLOLEP_Pos) -#define SCnSCB_ACTLR_DISLOLEP_Msk (ICB_ACTLR_DISLOLEP_Msk) - -#define SCnSCB_ACTLR_DISFOLD_Pos (ICB_ACTLR_DISFOLD_Pos) -#define SCnSCB_ACTLR_DISFOLD_Msk (ICB_ACTLR_DISFOLD_Msk) - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos (ICB_ICTR_INTLINESNUM_Pos) -#define SCnSCB_ICTR_INTLINESNUM_Msk (ICB_ICTR_INTLINESNUM_Msk) - -#define SCnSCB (ICB) -#define SCnSCB_NS (ICB_NS) - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## PMU functions and events #################################### */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - -#include "pmu_armv8.h" - -/** - \brief Cortex-M55 PMU events - \note Architectural PMU events can be found in pmu_armv8.h -*/ - -#define ARMCM55_PMU_ECC_ERR 0xC000 /*!< Any ECC error */ -#define ARMCM55_PMU_ECC_ERR_FATAL 0xC001 /*!< Any fatal ECC error */ -#define ARMCM55_PMU_ECC_ERR_DCACHE 0xC010 /*!< Any ECC error in the data cache */ -#define ARMCM55_PMU_ECC_ERR_ICACHE 0xC011 /*!< Any ECC error in the instruction cache */ -#define ARMCM55_PMU_ECC_ERR_FATAL_DCACHE 0xC012 /*!< Any fatal ECC error in the data cache */ -#define ARMCM55_PMU_ECC_ERR_FATAL_ICACHE 0xC013 /*!< Any fatal ECC error in the instruction cache*/ -#define ARMCM55_PMU_ECC_ERR_DTCM 0xC020 /*!< Any ECC error in the DTCM */ -#define ARMCM55_PMU_ECC_ERR_ITCM 0xC021 /*!< Any ECC error in the ITCM */ -#define ARMCM55_PMU_ECC_ERR_FATAL_DTCM 0xC022 /*!< Any fatal ECC error in the DTCM */ -#define ARMCM55_PMU_ECC_ERR_FATAL_ITCM 0xC023 /*!< Any fatal ECC error in the ITCM */ -#define ARMCM55_PMU_PF_LINEFILL 0xC100 /*!< A prefetcher starts a line-fill */ -#define ARMCM55_PMU_PF_CANCEL 0xC101 /*!< A prefetcher stops prefetching */ -#define ARMCM55_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ -#define ARMCM55_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ -#define ARMCM55_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ -#define ARMCM55_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ -#define ARMCM55_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access to the P-AHB write interface */ -#define ARMCM55_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ -#define ARMCM55_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ -#define ARMCM55_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ -#define ARMCM55_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - -/* ########################## MVE functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_MveFunctions MVE Functions - \brief Function that provides MVE type. - @{ - */ - -/** - \brief get MVE type - \details returns the MVE type - \returns - - \b 0: No Vector Extension (MVE) - - \b 1: Integer Vector Extension (MVE-I) - - \b 2: Floating-point Vector Extension (MVE-F) - */ -__STATIC_INLINE uint32_t SCB_GetMVEType(void) -{ - const uint32_t mvfr1 = FPU->MVFR1; - if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) - { - return 2U; - } - else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) - { - return 1U; - } - else - { - return 0U; - } -} - - -/*@} end of CMSIS_Core_MveFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM55_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm7.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm7.h deleted file mode 100644 index 010506e9f..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm7.h +++ /dev/null @@ -1,2366 +0,0 @@ -/**************************************************************************//** - * @file core_cm7.h - * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File - * @version V5.1.6 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_CM7_H_GENERIC -#define __CORE_CM7_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M7 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM7 definitions */ -#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ - __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_M (7U) /*!< Cortex-M Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM7_H_DEPENDANT -#define __CORE_CM7_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM7_REV - #define __CM7_REV 0x0000U - #warning "__CM7_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M7 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ - uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED3[93U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ - uint32_t RESERVED7[5U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ - __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ - __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ - __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ - uint32_t RESERVED8[1U]; - __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ - -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ -#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ - -#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ -#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ -#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ - -#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ -#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* AHBP Control Register Definitions */ -#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ -#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ - -#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ -#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -#define SCB_CACR_ECCEN_Pos 1U /*!< \deprecated SCB CACR: ECCEN Position */ -#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< \deprecated SCB CACR: ECCEN Mask */ - -#define SCB_CACR_ECCDIS_Pos 1U /*!< SCB CACR: ECCDIS Position */ -#define SCB_CACR_ECCDIS_Msk (1UL << SCB_CACR_ECCDIS_Pos) /*!< SCB CACR: ECCDIS Mask */ - -#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ -#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ - -/* AHBS Control Register Definitions */ -#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ -#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBSCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ - -#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ -#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBSCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ - -#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ -#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBSCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ - -/* Auxiliary Bus Fault Status Register Definitions */ -#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ -#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ - -#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ -#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ - -#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ -#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ - -#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ -#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ - -#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ -#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ - -#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ -#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ -#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ - -#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ -#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ - -#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ -#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ - -#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ -#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ - -#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ -#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ - -#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ -#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ - -#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED3[981U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and FP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and FP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and FP Feature Register 2 Definitions */ - -#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ -#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ -#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ -#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ -#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv7.h" - -#endif - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = SCB->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - -/*@} end of CMSIS_Core_FpuFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM7_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm85.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm85.h deleted file mode 100644 index 604631118..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_cm85.h +++ /dev/null @@ -1,4672 +0,0 @@ -/**************************************************************************//** - * @file core_cm85.h - * @brief CMSIS Cortex-M85 Core Peripheral Access Layer Header File - * @version V1.0.4 - * @date 21. April 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_CM85_H_GENERIC -#define __CORE_CM85_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup Cortex_M85 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS CM85 definitions */ - -#define __CORTEX_M (85U) /*!< Cortex-M Core */ - -#if defined ( __CC_ARM ) - #error Legacy Arm Compiler does not support Armv8.1-M target architecture. -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined(__ARM_FEATURE_DSP) - #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM85_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_CM85_H_DEPENDANT -#define __CORE_CM85_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __CM85_REV - #define __CM85_REV 0x0001U - #warning "__CM85_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #if __FPU_PRESENT != 0U - #ifndef __FPU_DP - #define __FPU_DP 0U - #warning "__FPU_DP not defined in device header file; using default!" - #endif - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __PMU_PRESENT - #define __PMU_PRESENT 0U - #warning "__PMU_PRESENT not defined in device header file; using default!" - #endif - - #if __PMU_PRESENT != 0U - #ifndef __PMU_NUM_EVENTCNT - #define __PMU_NUM_EVENTCNT 8U - #warning "__PMU_NUM_EVENTCNT not defined in device header file; using default!" - #elif (__PMU_NUM_EVENTCNT > 8 || __PMU_NUM_EVENTCNT < 2) - #error "__PMU_NUM_EVENTCNT is out of range in device header file!" */ - #endif - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group Cortex_M85 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core EWIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core PMU Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:1; /*!< bit: 20 Reserved */ - uint32_t B:1; /*!< bit: 21 BTI active (read 0) */ - uint32_t _reserved2:2; /*!< bit: 22..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_B_Pos 21U /*!< xPSR: B Position */ -#define xPSR_B_Msk (1UL << xPSR_B_Pos) /*!< xPSR: B Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t BTI_EN:1; /*!< bit: 4 Privileged branch target identification enable */ - uint32_t UBTI_EN:1; /*!< bit: 5 Unprivileged branch target identification enable */ - uint32_t PAC_EN:1; /*!< bit: 6 Privileged pointer authentication enable */ - uint32_t UPAC_EN:1; /*!< bit: 7 Unprivileged pointer authentication enable */ - uint32_t _reserved1:24; /*!< bit: 8..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_UPAC_EN_Pos 7U /*!< CONTROL: UPAC_EN Position */ -#define CONTROL_UPAC_EN_Msk (1UL << CONTROL_UPAC_EN_Pos) /*!< CONTROL: UPAC_EN Mask */ - -#define CONTROL_PAC_EN_Pos 6U /*!< CONTROL: PAC_EN Position */ -#define CONTROL_PAC_EN_Msk (1UL << CONTROL_PAC_EN_Pos) /*!< CONTROL: PAC_EN Mask */ - -#define CONTROL_UBTI_EN_Pos 5U /*!< CONTROL: UBTI_EN Position */ -#define CONTROL_UBTI_EN_Msk (1UL << CONTROL_UBTI_EN_Pos) /*!< CONTROL: UBTI_EN Mask */ - -#define CONTROL_BTI_EN_Pos 4U /*!< CONTROL: BTI_EN Position */ -#define CONTROL_BTI_EN_Msk (1UL << CONTROL_BTI_EN_Pos) /*!< CONTROL: BTI_EN Mask */ - -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED7[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ - __IOM uint32_t RFSR; /*!< Offset: 0x204 (R/W) RAS Fault Status Register */ - uint32_t RESERVED4[14U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ - __OM uint32_t BPIALL; /*!< Offset: 0x278 ( /W) Branch Predictor Invalidate All */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_IESB_Pos 5U /*!< SCB AIRCR: Implicit ESB Enable Position */ -#define SCB_AIRCR_IESB_Msk (1UL << SCB_AIRCR_IESB_Pos) /*!< SCB AIRCR: Implicit ESB Enable Mask */ - -#define SCB_AIRCR_DIT_Pos 4U /*!< SCB AIRCR: Data Independent Timing Position */ -#define SCB_AIRCR_DIT_Msk (1UL << SCB_AIRCR_DIT_Pos) /*!< SCB AIRCR: Data Independent Timing Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_TRD_Pos 20U /*!< SCB CCR: TRD Position */ -#define SCB_CCR_TRD_Msk (1UL << SCB_CCR_TRD_Pos) /*!< SCB CCR: TRD Mask */ - -#define SCB_CCR_LOB_Pos 19U /*!< SCB CCR: LOB Position */ -#define SCB_CCR_LOB_Msk (1UL << SCB_CCR_LOB_Pos) /*!< SCB CCR: LOB Mask */ - -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_PMU_Pos 5U /*!< SCB DFSR: PMU Position */ -#define SCB_DFSR_PMU_Msk (1UL << SCB_DFSR_PMU_Pos) /*!< SCB DFSR: PMU Mask */ - -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CP7_Pos 7U /*!< SCB NSACR: CP7 Position */ -#define SCB_NSACR_CP7_Msk (1UL << SCB_NSACR_CP7_Pos) /*!< SCB NSACR: CP7 Mask */ - -#define SCB_NSACR_CP6_Pos 6U /*!< SCB NSACR: CP6 Position */ -#define SCB_NSACR_CP6_Msk (1UL << SCB_NSACR_CP6_Pos) /*!< SCB NSACR: CP6 Mask */ - -#define SCB_NSACR_CP5_Pos 5U /*!< SCB NSACR: CP5 Position */ -#define SCB_NSACR_CP5_Msk (1UL << SCB_NSACR_CP5_Pos) /*!< SCB NSACR: CP5 Mask */ - -#define SCB_NSACR_CP4_Pos 4U /*!< SCB NSACR: CP4 Position */ -#define SCB_NSACR_CP4_Msk (1UL << SCB_NSACR_CP4_Pos) /*!< SCB NSACR: CP4 Mask */ - -#define SCB_NSACR_CP3_Pos 3U /*!< SCB NSACR: CP3 Position */ -#define SCB_NSACR_CP3_Msk (1UL << SCB_NSACR_CP3_Pos) /*!< SCB NSACR: CP3 Mask */ - -#define SCB_NSACR_CP2_Pos 2U /*!< SCB NSACR: CP2 Position */ -#define SCB_NSACR_CP2_Msk (1UL << SCB_NSACR_CP2_Pos) /*!< SCB NSACR: CP2 Mask */ - -#define SCB_NSACR_CP1_Pos 1U /*!< SCB NSACR: CP1 Position */ -#define SCB_NSACR_CP1_Msk (1UL << SCB_NSACR_CP1_Pos) /*!< SCB NSACR: CP1 Mask */ - -#define SCB_NSACR_CP0_Pos 0U /*!< SCB NSACR: CP0 Position */ -#define SCB_NSACR_CP0_Msk (1UL /*<< SCB_NSACR_CP0_Pos*/) /*!< SCB NSACR: CP0 Mask */ - -/* SCB Debug Feature Register 0 Definitions */ -#define SCB_ID_DFR_UDE_Pos 28U /*!< SCB ID_DFR: UDE Position */ -#define SCB_ID_DFR_UDE_Msk (0xFUL << SCB_ID_DFR_UDE_Pos) /*!< SCB ID_DFR: UDE Mask */ - -#define SCB_ID_DFR_MProfDbg_Pos 20U /*!< SCB ID_DFR: MProfDbg Position */ -#define SCB_ID_DFR_MProfDbg_Msk (0xFUL << SCB_ID_DFR_MProfDbg_Pos) /*!< SCB ID_DFR: MProfDbg Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB RAS Fault Status Register Definitions */ -#define SCB_RFSR_V_Pos 31U /*!< SCB RFSR: V Position */ -#define SCB_RFSR_V_Msk (1UL << SCB_RFSR_V_Pos) /*!< SCB RFSR: V Mask */ - -#define SCB_RFSR_IS_Pos 16U /*!< SCB RFSR: IS Position */ -#define SCB_RFSR_IS_Msk (0x7FFFUL << SCB_RFSR_IS_Pos) /*!< SCB RFSR: IS Mask */ - -#define SCB_RFSR_UET_Pos 0U /*!< SCB RFSR: UET Position */ -#define SCB_RFSR_UET_Msk (3UL /*<< SCB_RFSR_UET_Pos*/) /*!< SCB RFSR: UET Mask */ - -/* SCB D-Cache Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean by Set-way Register Definitions */ -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ICB Implementation Control Block register (ICB) - \brief Type definitions for the Implementation Control Block Register - @{ - */ - -/** - \brief Structure type to access the Implementation Control Block (ICB). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} ICB_Type; - -/* Auxiliary Control Register Definitions */ -#define ICB_ACTLR_DISCRITAXIRUW_Pos 27U /*!< ACTLR: DISCRITAXIRUW Position */ -#define ICB_ACTLR_DISCRITAXIRUW_Msk (1UL << ICB_ACTLR_DISCRITAXIRUW_Pos) /*!< ACTLR: DISCRITAXIRUW Mask */ - -#define ICB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ -#define ICB_ACTLR_DISCRITAXIRUR_Msk (1UL << ICB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ - -#define ICB_ACTLR_EVENTBUSEN_Pos 14U /*!< ACTLR: EVENTBUSEN Position */ -#define ICB_ACTLR_EVENTBUSEN_Msk (1UL << ICB_ACTLR_EVENTBUSEN_Pos) /*!< ACTLR: EVENTBUSEN Mask */ - -#define ICB_ACTLR_EVENTBUSEN_S_Pos 13U /*!< ACTLR: EVENTBUSEN_S Position */ -#define ICB_ACTLR_EVENTBUSEN_S_Msk (1UL << ICB_ACTLR_EVENTBUSEN_S_Pos) /*!< ACTLR: EVENTBUSEN_S Mask */ - -#define ICB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ -#define ICB_ACTLR_DISITMATBFLUSH_Msk (1UL << ICB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ - -#define ICB_ACTLR_DISNWAMODE_Pos 11U /*!< ACTLR: DISNWAMODE Position */ -#define ICB_ACTLR_DISNWAMODE_Msk (1UL << ICB_ACTLR_DISNWAMODE_Pos) /*!< ACTLR: DISNWAMODE Mask */ - -#define ICB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ -#define ICB_ACTLR_FPEXCODIS_Msk (1UL << ICB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ - -/* Interrupt Controller Type Register Definitions */ -#define ICB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define ICB_ICTR_INTLINESNUM_Msk (0xFUL /*<< ICB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_ICB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[3U]; - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) ITM Device Type Register */ - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup MemSysCtl_Type Memory System Control Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Memory System Control Registers (MEMSYSCTL) - @{ - */ - -/** - \brief Structure type to access the Memory System Control Registers (MEMSYSCTL). - */ -typedef struct -{ - __IOM uint32_t MSCR; /*!< Offset: 0x000 (R/W) Memory System Control Register */ - __IOM uint32_t PFCR; /*!< Offset: 0x004 (R/W) Prefetcher Control Register */ - uint32_t RESERVED1[2U]; - __IOM uint32_t ITCMCR; /*!< Offset: 0x010 (R/W) ITCM Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x014 (R/W) DTCM Control Register */ - __IOM uint32_t PAHBCR; /*!< Offset: 0x018 (R/W) P-AHB Control Register */ - uint32_t RESERVED2[313U]; - __IOM uint32_t ITGU_CTRL; /*!< Offset: 0x500 (R/W) ITGU Control Register */ - __IOM uint32_t ITGU_CFG; /*!< Offset: 0x504 (R/W) ITGU Configuration Register */ - uint32_t RESERVED3[2U]; - __IOM uint32_t ITGU_LUT[16U]; /*!< Offset: 0x510 (R/W) ITGU Look Up Table Register */ - uint32_t RESERVED4[44U]; - __IOM uint32_t DTGU_CTRL; /*!< Offset: 0x600 (R/W) DTGU Control Registers */ - __IOM uint32_t DTGU_CFG; /*!< Offset: 0x604 (R/W) DTGU Configuration Register */ - uint32_t RESERVED5[2U]; - __IOM uint32_t DTGU_LUT[16U]; /*!< Offset: 0x610 (R/W) DTGU Look Up Table Register */ -} MemSysCtl_Type; - -/* MEMSYSCTL Memory System Control Register (MSCR) Register Definitions */ -#define MEMSYSCTL_MSCR_CPWRDN_Pos 17U /*!< MEMSYSCTL MSCR: CPWRDN Position */ -#define MEMSYSCTL_MSCR_CPWRDN_Msk (0x1UL << MEMSYSCTL_MSCR_CPWRDN_Pos) /*!< MEMSYSCTL MSCR: CPWRDN Mask */ - -#define MEMSYSCTL_MSCR_DCCLEAN_Pos 16U /*!< MEMSYSCTL MSCR: DCCLEAN Position */ -#define MEMSYSCTL_MSCR_DCCLEAN_Msk (0x1UL << MEMSYSCTL_MSCR_DCCLEAN_Pos) /*!< MEMSYSCTL MSCR: DCCLEAN Mask */ - -#define MEMSYSCTL_MSCR_ICACTIVE_Pos 13U /*!< MEMSYSCTL MSCR: ICACTIVE Position */ -#define MEMSYSCTL_MSCR_ICACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_ICACTIVE_Pos) /*!< MEMSYSCTL MSCR: ICACTIVE Mask */ - -#define MEMSYSCTL_MSCR_DCACTIVE_Pos 12U /*!< MEMSYSCTL MSCR: DCACTIVE Position */ -#define MEMSYSCTL_MSCR_DCACTIVE_Msk (0x1UL << MEMSYSCTL_MSCR_DCACTIVE_Pos) /*!< MEMSYSCTL MSCR: DCACTIVE Mask */ - -#define MEMSYSCTL_MSCR_EVECCFAULT_Pos 3U /*!< MEMSYSCTL MSCR: EVECCFAULT Position */ -#define MEMSYSCTL_MSCR_EVECCFAULT_Msk (0x1UL << MEMSYSCTL_MSCR_EVECCFAULT_Pos) /*!< MEMSYSCTL MSCR: EVECCFAULT Mask */ - -#define MEMSYSCTL_MSCR_FORCEWT_Pos 2U /*!< MEMSYSCTL MSCR: FORCEWT Position */ -#define MEMSYSCTL_MSCR_FORCEWT_Msk (0x1UL << MEMSYSCTL_MSCR_FORCEWT_Pos) /*!< MEMSYSCTL MSCR: FORCEWT Mask */ - -#define MEMSYSCTL_MSCR_ECCEN_Pos 1U /*!< MEMSYSCTL MSCR: ECCEN Position */ -#define MEMSYSCTL_MSCR_ECCEN_Msk (0x1UL << MEMSYSCTL_MSCR_ECCEN_Pos) /*!< MEMSYSCTL MSCR: ECCEN Mask */ - -/* MEMSYSCTL Prefetcher Control Register (PFCR) Register Definitions */ -#define MEMSYSCTL_PFCR_DIS_NLP_Pos 7U /*!< MEMSYSCTL PFCR: DIS_NLP Position */ -#define MEMSYSCTL_PFCR_DIS_NLP_Msk (0x1UL << MEMSYSCTL_PFCR_DIS_NLP_Pos) /*!< MEMSYSCTL PFCR: DIS_NLP Mask */ - -#define MEMSYSCTL_PFCR_ENABLE_Pos 0U /*!< MEMSYSCTL PFCR: ENABLE Position */ -#define MEMSYSCTL_PFCR_ENABLE_Msk (0x1UL /*<< MEMSYSCTL_PFCR_ENABLE_Pos*/) /*!< MEMSYSCTL PFCR: ENABLE Mask */ - -/* MEMSYSCTL ITCM Control Register (ITCMCR) Register Definitions */ -#define MEMSYSCTL_ITCMCR_SZ_Pos 3U /*!< MEMSYSCTL ITCMCR: SZ Position */ -#define MEMSYSCTL_ITCMCR_SZ_Msk (0xFUL << MEMSYSCTL_ITCMCR_SZ_Pos) /*!< MEMSYSCTL ITCMCR: SZ Mask */ - -#define MEMSYSCTL_ITCMCR_EN_Pos 0U /*!< MEMSYSCTL ITCMCR: EN Position */ -#define MEMSYSCTL_ITCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_ITCMCR_EN_Pos*/) /*!< MEMSYSCTL ITCMCR: EN Mask */ - -/* MEMSYSCTL DTCM Control Register (DTCMCR) Register Definitions */ -#define MEMSYSCTL_DTCMCR_SZ_Pos 3U /*!< MEMSYSCTL DTCMCR: SZ Position */ -#define MEMSYSCTL_DTCMCR_SZ_Msk (0xFUL << MEMSYSCTL_DTCMCR_SZ_Pos) /*!< MEMSYSCTL DTCMCR: SZ Mask */ - -#define MEMSYSCTL_DTCMCR_EN_Pos 0U /*!< MEMSYSCTL DTCMCR: EN Position */ -#define MEMSYSCTL_DTCMCR_EN_Msk (0x1UL /*<< MEMSYSCTL_DTCMCR_EN_Pos*/) /*!< MEMSYSCTL DTCMCR: EN Mask */ - -/* MEMSYSCTL P-AHB Control Register (PAHBCR) Register Definitions */ -#define MEMSYSCTL_PAHBCR_SZ_Pos 1U /*!< MEMSYSCTL PAHBCR: SZ Position */ -#define MEMSYSCTL_PAHBCR_SZ_Msk (0x7UL << MEMSYSCTL_PAHBCR_SZ_Pos) /*!< MEMSYSCTL PAHBCR: SZ Mask */ - -#define MEMSYSCTL_PAHBCR_EN_Pos 0U /*!< MEMSYSCTL PAHBCR: EN Position */ -#define MEMSYSCTL_PAHBCR_EN_Msk (0x1UL /*<< MEMSYSCTL_PAHBCR_EN_Pos*/) /*!< MEMSYSCTL PAHBCR: EN Mask */ - -/* MEMSYSCTL ITGU Control Register (ITGU_CTRL) Register Definitions */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL ITGU_CTRL: DEREN Position */ -#define MEMSYSCTL_ITGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_ITGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL ITGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL ITGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_ITGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_ITGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL ITGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL ITGU Configuration Register (ITGU_CFG) Register Definitions */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL ITGU_CFG: PRESENT Position */ -#define MEMSYSCTL_ITGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_ITGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL ITGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_ITGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_ITGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL ITGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL ITGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_ITGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_ITGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL ITGU_CFG: BLKSZ Mask */ - -/* MEMSYSCTL DTGU Control Registers (DTGU_CTRL) Register Definitions */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Pos 1U /*!< MEMSYSCTL DTGU_CTRL: DEREN Position */ -#define MEMSYSCTL_DTGU_CTRL_DEREN_Msk (0x1UL << MEMSYSCTL_DTGU_CTRL_DEREN_Pos) /*!< MEMSYSCTL DTGU_CTRL: DEREN Mask */ - -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Pos 0U /*!< MEMSYSCTL DTGU_CTRL: DBFEN Position */ -#define MEMSYSCTL_DTGU_CTRL_DBFEN_Msk (0x1UL /*<< MEMSYSCTL_DTGU_CTRL_DBFEN_Pos*/) /*!< MEMSYSCTL DTGU_CTRL: DBFEN Mask */ - -/* MEMSYSCTL DTGU Configuration Register (DTGU_CFG) Register Definitions */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Pos 31U /*!< MEMSYSCTL DTGU_CFG: PRESENT Position */ -#define MEMSYSCTL_DTGU_CFG_PRESENT_Msk (0x1UL << MEMSYSCTL_DTGU_CFG_PRESENT_Pos) /*!< MEMSYSCTL DTGU_CFG: PRESENT Mask */ - -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos 8U /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Position */ -#define MEMSYSCTL_DTGU_CFG_NUMBLKS_Msk (0xFUL << MEMSYSCTL_DTGU_CFG_NUMBLKS_Pos) /*!< MEMSYSCTL DTGU_CFG: NUMBLKS Mask */ - -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Pos 0U /*!< MEMSYSCTL DTGU_CFG: BLKSZ Position */ -#define MEMSYSCTL_DTGU_CFG_BLKSZ_Msk (0xFUL /*<< MEMSYSCTL_DTGU_CFG_BLKSZ_Pos*/) /*!< MEMSYSCTL DTGU_CFG: BLKSZ Mask */ - - -/*@}*/ /* end of group MemSysCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PwrModCtl_Type Power Mode Control Registers - \brief Type definitions for the Power Mode Control Registers (PWRMODCTL) - @{ - */ - -/** - \brief Structure type to access the Power Mode Control Registers (PWRMODCTL). - */ -typedef struct -{ - __IOM uint32_t CPDLPSTATE; /*!< Offset: 0x000 (R/W) Core Power Domain Low Power State Register */ - __IOM uint32_t DPDLPSTATE; /*!< Offset: 0x004 (R/W) Debug Power Domain Low Power State Register */ -} PwrModCtl_Type; - -/* PWRMODCTL Core Power Domain Low Power State (CPDLPSTATE) Register Definitions */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos 8U /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_RLPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_RLPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: RLPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos 4U /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_ELPSTATE_Msk (0x3UL << PWRMODCTL_CPDLPSTATE_ELPSTATE_Pos) /*!< PWRMODCTL CPDLPSTATE: ELPSTATE Mask */ - -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos 0U /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Position */ -#define PWRMODCTL_CPDLPSTATE_CLPSTATE_Msk (0x3UL /*<< PWRMODCTL_CPDLPSTATE_CLPSTATE_Pos*/) /*!< PWRMODCTL CPDLPSTATE: CLPSTATE Mask */ - -/* PWRMODCTL Debug Power Domain Low Power State (DPDLPSTATE) Register Definitions */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos 0U /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Position */ -#define PWRMODCTL_DPDLPSTATE_DLPSTATE_Msk (0x3UL /*<< PWRMODCTL_DPDLPSTATE_DLPSTATE_Pos*/) /*!< PWRMODCTL DPDLPSTATE: DLPSTATE Mask */ - -/*@}*/ /* end of group PwrModCtl_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup EWIC_Type External Wakeup Interrupt Controller Registers - \brief Type definitions for the External Wakeup Interrupt Controller Registers (EWIC) - @{ - */ - -/** - \brief Structure type to access the External Wakeup Interrupt Controller Registers (EWIC). - */ -typedef struct -{ - __OM uint32_t EVENTSPR; /*!< Offset: 0x000 ( /W) Event Set Pending Register */ - uint32_t RESERVED0[31U]; - __IM uint32_t EVENTMASKA; /*!< Offset: 0x080 (R/W) Event Mask A Register */ - __IM uint32_t EVENTMASK[15]; /*!< Offset: 0x084 (R/W) Event Mask Register */ -} EWIC_Type; - -/* EWIC External Wakeup Interrupt Controller (EVENTSPR) Register Definitions */ -#define EWIC_EVENTSPR_EDBGREQ_Pos 2U /*!< EWIC EVENTSPR: EDBGREQ Position */ -#define EWIC_EVENTSPR_EDBGREQ_Msk (0x1UL << EWIC_EVENTSPR_EDBGREQ_Pos) /*!< EWIC EVENTSPR: EDBGREQ Mask */ - -#define EWIC_EVENTSPR_NMI_Pos 1U /*!< EWIC EVENTSPR: NMI Position */ -#define EWIC_EVENTSPR_NMI_Msk (0x1UL << EWIC_EVENTSPR_NMI_Pos) /*!< EWIC EVENTSPR: NMI Mask */ - -#define EWIC_EVENTSPR_EVENT_Pos 0U /*!< EWIC EVENTSPR: EVENT Position */ -#define EWIC_EVENTSPR_EVENT_Msk (0x1UL /*<< EWIC_EVENTSPR_EVENT_Pos*/) /*!< EWIC EVENTSPR: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASKA) Register Definitions */ -#define EWIC_EVENTMASKA_EDBGREQ_Pos 2U /*!< EWIC EVENTMASKA: EDBGREQ Position */ -#define EWIC_EVENTMASKA_EDBGREQ_Msk (0x1UL << EWIC_EVENTMASKA_EDBGREQ_Pos) /*!< EWIC EVENTMASKA: EDBGREQ Mask */ - -#define EWIC_EVENTMASKA_NMI_Pos 1U /*!< EWIC EVENTMASKA: NMI Position */ -#define EWIC_EVENTMASKA_NMI_Msk (0x1UL << EWIC_EVENTMASKA_NMI_Pos) /*!< EWIC EVENTMASKA: NMI Mask */ - -#define EWIC_EVENTMASKA_EVENT_Pos 0U /*!< EWIC EVENTMASKA: EVENT Position */ -#define EWIC_EVENTMASKA_EVENT_Msk (0x1UL /*<< EWIC_EVENTMASKA_EVENT_Pos*/) /*!< EWIC EVENTMASKA: EVENT Mask */ - -/* EWIC External Wakeup Interrupt Controller (EVENTMASK) Register Definitions */ -#define EWIC_EVENTMASK_IRQ_Pos 0U /*!< EWIC EVENTMASKA: IRQ Position */ -#define EWIC_EVENTMASK_IRQ_Msk (0xFFFFFFFFUL /*<< EWIC_EVENTMASKA_IRQ_Pos*/) /*!< EWIC EVENTMASKA: IRQ Mask */ - -/*@}*/ /* end of group EWIC_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup ErrBnk_Type Error Banking Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Error Banking Registers (ERRBNK) - @{ - */ - -/** - \brief Structure type to access the Error Banking Registers (ERRBNK). - */ -typedef struct -{ - __IOM uint32_t IEBR0; /*!< Offset: 0x000 (R/W) Instruction Cache Error Bank Register 0 */ - __IOM uint32_t IEBR1; /*!< Offset: 0x004 (R/W) Instruction Cache Error Bank Register 1 */ - uint32_t RESERVED0[2U]; - __IOM uint32_t DEBR0; /*!< Offset: 0x010 (R/W) Data Cache Error Bank Register 0 */ - __IOM uint32_t DEBR1; /*!< Offset: 0x014 (R/W) Data Cache Error Bank Register 1 */ - uint32_t RESERVED1[2U]; - __IOM uint32_t TEBR0; /*!< Offset: 0x020 (R/W) TCM Error Bank Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t TEBR1; /*!< Offset: 0x028 (R/W) TCM Error Bank Register 1 */ -} ErrBnk_Type; - -/* ERRBNK Instruction Cache Error Bank Register 0 (IEBR0) Register Definitions */ -#define ERRBNK_IEBR0_SWDEF_Pos 30U /*!< ERRBNK IEBR0: SWDEF Position */ -#define ERRBNK_IEBR0_SWDEF_Msk (0x3UL << ERRBNK_IEBR0_SWDEF_Pos) /*!< ERRBNK IEBR0: SWDEF Mask */ - -#define ERRBNK_IEBR0_BANK_Pos 16U /*!< ERRBNK IEBR0: BANK Position */ -#define ERRBNK_IEBR0_BANK_Msk (0x1UL << ERRBNK_IEBR0_BANK_Pos) /*!< ERRBNK IEBR0: BANK Mask */ - -#define ERRBNK_IEBR0_LOCATION_Pos 2U /*!< ERRBNK IEBR0: LOCATION Position */ -#define ERRBNK_IEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR0_LOCATION_Pos) /*!< ERRBNK IEBR0: LOCATION Mask */ - -#define ERRBNK_IEBR0_LOCKED_Pos 1U /*!< ERRBNK IEBR0: LOCKED Position */ -#define ERRBNK_IEBR0_LOCKED_Msk (0x1UL << ERRBNK_IEBR0_LOCKED_Pos) /*!< ERRBNK IEBR0: LOCKED Mask */ - -#define ERRBNK_IEBR0_VALID_Pos 0U /*!< ERRBNK IEBR0: VALID Position */ -#define ERRBNK_IEBR0_VALID_Msk (0x1UL << /*ERRBNK_IEBR0_VALID_Pos*/) /*!< ERRBNK IEBR0: VALID Mask */ - -/* ERRBNK Instruction Cache Error Bank Register 1 (IEBR1) Register Definitions */ -#define ERRBNK_IEBR1_SWDEF_Pos 30U /*!< ERRBNK IEBR1: SWDEF Position */ -#define ERRBNK_IEBR1_SWDEF_Msk (0x3UL << ERRBNK_IEBR1_SWDEF_Pos) /*!< ERRBNK IEBR1: SWDEF Mask */ - -#define ERRBNK_IEBR1_BANK_Pos 16U /*!< ERRBNK IEBR1: BANK Position */ -#define ERRBNK_IEBR1_BANK_Msk (0x1UL << ERRBNK_IEBR1_BANK_Pos) /*!< ERRBNK IEBR1: BANK Mask */ - -#define ERRBNK_IEBR1_LOCATION_Pos 2U /*!< ERRBNK IEBR1: LOCATION Position */ -#define ERRBNK_IEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_IEBR1_LOCATION_Pos) /*!< ERRBNK IEBR1: LOCATION Mask */ - -#define ERRBNK_IEBR1_LOCKED_Pos 1U /*!< ERRBNK IEBR1: LOCKED Position */ -#define ERRBNK_IEBR1_LOCKED_Msk (0x1UL << ERRBNK_IEBR1_LOCKED_Pos) /*!< ERRBNK IEBR1: LOCKED Mask */ - -#define ERRBNK_IEBR1_VALID_Pos 0U /*!< ERRBNK IEBR1: VALID Position */ -#define ERRBNK_IEBR1_VALID_Msk (0x1UL << /*ERRBNK_IEBR1_VALID_Pos*/) /*!< ERRBNK IEBR1: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 0 (DEBR0) Register Definitions */ -#define ERRBNK_DEBR0_SWDEF_Pos 30U /*!< ERRBNK DEBR0: SWDEF Position */ -#define ERRBNK_DEBR0_SWDEF_Msk (0x3UL << ERRBNK_DEBR0_SWDEF_Pos) /*!< ERRBNK DEBR0: SWDEF Mask */ - -#define ERRBNK_DEBR0_TYPE_Pos 17U /*!< ERRBNK DEBR0: TYPE Position */ -#define ERRBNK_DEBR0_TYPE_Msk (0x1UL << ERRBNK_DEBR0_TYPE_Pos) /*!< ERRBNK DEBR0: TYPE Mask */ - -#define ERRBNK_DEBR0_BANK_Pos 16U /*!< ERRBNK DEBR0: BANK Position */ -#define ERRBNK_DEBR0_BANK_Msk (0x1UL << ERRBNK_DEBR0_BANK_Pos) /*!< ERRBNK DEBR0: BANK Mask */ - -#define ERRBNK_DEBR0_LOCATION_Pos 2U /*!< ERRBNK DEBR0: LOCATION Position */ -#define ERRBNK_DEBR0_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR0_LOCATION_Pos) /*!< ERRBNK DEBR0: LOCATION Mask */ - -#define ERRBNK_DEBR0_LOCKED_Pos 1U /*!< ERRBNK DEBR0: LOCKED Position */ -#define ERRBNK_DEBR0_LOCKED_Msk (0x1UL << ERRBNK_DEBR0_LOCKED_Pos) /*!< ERRBNK DEBR0: LOCKED Mask */ - -#define ERRBNK_DEBR0_VALID_Pos 0U /*!< ERRBNK DEBR0: VALID Position */ -#define ERRBNK_DEBR0_VALID_Msk (0x1UL << /*ERRBNK_DEBR0_VALID_Pos*/) /*!< ERRBNK DEBR0: VALID Mask */ - -/* ERRBNK Data Cache Error Bank Register 1 (DEBR1) Register Definitions */ -#define ERRBNK_DEBR1_SWDEF_Pos 30U /*!< ERRBNK DEBR1: SWDEF Position */ -#define ERRBNK_DEBR1_SWDEF_Msk (0x3UL << ERRBNK_DEBR1_SWDEF_Pos) /*!< ERRBNK DEBR1: SWDEF Mask */ - -#define ERRBNK_DEBR1_TYPE_Pos 17U /*!< ERRBNK DEBR1: TYPE Position */ -#define ERRBNK_DEBR1_TYPE_Msk (0x1UL << ERRBNK_DEBR1_TYPE_Pos) /*!< ERRBNK DEBR1: TYPE Mask */ - -#define ERRBNK_DEBR1_BANK_Pos 16U /*!< ERRBNK DEBR1: BANK Position */ -#define ERRBNK_DEBR1_BANK_Msk (0x1UL << ERRBNK_DEBR1_BANK_Pos) /*!< ERRBNK DEBR1: BANK Mask */ - -#define ERRBNK_DEBR1_LOCATION_Pos 2U /*!< ERRBNK DEBR1: LOCATION Position */ -#define ERRBNK_DEBR1_LOCATION_Msk (0x3FFFUL << ERRBNK_DEBR1_LOCATION_Pos) /*!< ERRBNK DEBR1: LOCATION Mask */ - -#define ERRBNK_DEBR1_LOCKED_Pos 1U /*!< ERRBNK DEBR1: LOCKED Position */ -#define ERRBNK_DEBR1_LOCKED_Msk (0x1UL << ERRBNK_DEBR1_LOCKED_Pos) /*!< ERRBNK DEBR1: LOCKED Mask */ - -#define ERRBNK_DEBR1_VALID_Pos 0U /*!< ERRBNK DEBR1: VALID Position */ -#define ERRBNK_DEBR1_VALID_Msk (0x1UL << /*ERRBNK_DEBR1_VALID_Pos*/) /*!< ERRBNK DEBR1: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 0 (TEBR0) Register Definitions */ -#define ERRBNK_TEBR0_SWDEF_Pos 30U /*!< ERRBNK TEBR0: SWDEF Position */ -#define ERRBNK_TEBR0_SWDEF_Msk (0x3UL << ERRBNK_TEBR0_SWDEF_Pos) /*!< ERRBNK TEBR0: SWDEF Mask */ - -#define ERRBNK_TEBR0_POISON_Pos 28U /*!< ERRBNK TEBR0: POISON Position */ -#define ERRBNK_TEBR0_POISON_Msk (0x1UL << ERRBNK_TEBR0_POISON_Pos) /*!< ERRBNK TEBR0: POISON Mask */ - -#define ERRBNK_TEBR0_TYPE_Pos 27U /*!< ERRBNK TEBR0: TYPE Position */ -#define ERRBNK_TEBR0_TYPE_Msk (0x1UL << ERRBNK_TEBR0_TYPE_Pos) /*!< ERRBNK TEBR0: TYPE Mask */ - -#define ERRBNK_TEBR0_BANK_Pos 24U /*!< ERRBNK TEBR0: BANK Position */ -#define ERRBNK_TEBR0_BANK_Msk (0x3UL << ERRBNK_TEBR0_BANK_Pos) /*!< ERRBNK TEBR0: BANK Mask */ - -#define ERRBNK_TEBR0_LOCATION_Pos 2U /*!< ERRBNK TEBR0: LOCATION Position */ -#define ERRBNK_TEBR0_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR0_LOCATION_Pos) /*!< ERRBNK TEBR0: LOCATION Mask */ - -#define ERRBNK_TEBR0_LOCKED_Pos 1U /*!< ERRBNK TEBR0: LOCKED Position */ -#define ERRBNK_TEBR0_LOCKED_Msk (0x1UL << ERRBNK_TEBR0_LOCKED_Pos) /*!< ERRBNK TEBR0: LOCKED Mask */ - -#define ERRBNK_TEBR0_VALID_Pos 0U /*!< ERRBNK TEBR0: VALID Position */ -#define ERRBNK_TEBR0_VALID_Msk (0x1UL << /*ERRBNK_TEBR0_VALID_Pos*/) /*!< ERRBNK TEBR0: VALID Mask */ - -/* ERRBNK TCM Error Bank Register 1 (TEBR1) Register Definitions */ -#define ERRBNK_TEBR1_SWDEF_Pos 30U /*!< ERRBNK TEBR1: SWDEF Position */ -#define ERRBNK_TEBR1_SWDEF_Msk (0x3UL << ERRBNK_TEBR1_SWDEF_Pos) /*!< ERRBNK TEBR1: SWDEF Mask */ - -#define ERRBNK_TEBR1_POISON_Pos 28U /*!< ERRBNK TEBR1: POISON Position */ -#define ERRBNK_TEBR1_POISON_Msk (0x1UL << ERRBNK_TEBR1_POISON_Pos) /*!< ERRBNK TEBR1: POISON Mask */ - -#define ERRBNK_TEBR1_TYPE_Pos 27U /*!< ERRBNK TEBR1: TYPE Position */ -#define ERRBNK_TEBR1_TYPE_Msk (0x1UL << ERRBNK_TEBR1_TYPE_Pos) /*!< ERRBNK TEBR1: TYPE Mask */ - -#define ERRBNK_TEBR1_BANK_Pos 24U /*!< ERRBNK TEBR1: BANK Position */ -#define ERRBNK_TEBR1_BANK_Msk (0x3UL << ERRBNK_TEBR1_BANK_Pos) /*!< ERRBNK TEBR1: BANK Mask */ - -#define ERRBNK_TEBR1_LOCATION_Pos 2U /*!< ERRBNK TEBR1: LOCATION Position */ -#define ERRBNK_TEBR1_LOCATION_Msk (0x3FFFFFUL << ERRBNK_TEBR1_LOCATION_Pos) /*!< ERRBNK TEBR1: LOCATION Mask */ - -#define ERRBNK_TEBR1_LOCKED_Pos 1U /*!< ERRBNK TEBR1: LOCKED Position */ -#define ERRBNK_TEBR1_LOCKED_Msk (0x1UL << ERRBNK_TEBR1_LOCKED_Pos) /*!< ERRBNK TEBR1: LOCKED Mask */ - -#define ERRBNK_TEBR1_VALID_Pos 0U /*!< ERRBNK TEBR1: VALID Position */ -#define ERRBNK_TEBR1_VALID_Msk (0x1UL << /*ERRBNK_TEBR1_VALID_Pos*/) /*!< ERRBNK TEBR1: VALID Mask */ - -/*@}*/ /* end of group ErrBnk_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup PrcCfgInf_Type Processor Configuration Information Registers (IMPLEMENTATION DEFINED) - \brief Type definitions for the Processor Configuration Information Registerss (PRCCFGINF) - @{ - */ - -/** - \brief Structure type to access the Processor Configuration Information Registerss (PRCCFGINF). - */ -typedef struct -{ - __OM uint32_t CFGINFOSEL; /*!< Offset: 0x000 ( /W) Processor Configuration Information Selection Register */ - __IM uint32_t CFGINFORD; /*!< Offset: 0x004 (R/ ) Processor Configuration Information Read Data Register */ -} PrcCfgInf_Type; - -/* PRCCFGINF Processor Configuration Information Selection Register (CFGINFOSEL) Definitions */ - -/* PRCCFGINF Processor Configuration Information Read Data Register (CFGINFORD) Definitions */ - -/*@}*/ /* end of group PrcCfgInf_Type */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[809U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ - uint32_t RESERVED4[4U]; - __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ -#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFmt_Pos 0U /*!< TPI FFCR: EnFmt Position */ -#define TPI_FFCR_EnFmt_Msk (0x3UL << /*TPI_FFCR_EnFmt_Pos*/) /*!< TPI FFCR: EnFmt Mask */ - -/* TPI Periodic Synchronization Control Register Definitions */ -#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ -#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ - -/* TPI Software Lock Status Register Definitions */ -#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ -#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ - -#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ -#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ - -#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ -#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_PMU Performance Monitoring Unit (PMU) - \brief Type definitions for the Performance Monitoring Unit (PMU) - @{ - */ - -/** - \brief Structure type to access the Performance Monitoring Unit (PMU). - */ -typedef struct -{ - __IOM uint32_t EVCNTR[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x0 (R/W) PMU Event Counter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED0[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCNTR; /*!< Offset: 0x7C (R/W) PMU Cycle Counter Register */ - uint32_t RESERVED1[224]; - __IOM uint32_t EVTYPER[__PMU_NUM_EVENTCNT]; /*!< Offset: 0x400 (R/W) PMU Event Type and Filter Registers */ -#if __PMU_NUM_EVENTCNT<31 - uint32_t RESERVED2[31U-__PMU_NUM_EVENTCNT]; -#endif - __IOM uint32_t CCFILTR; /*!< Offset: 0x47C (R/W) PMU Cycle Counter Filter Register */ - uint32_t RESERVED3[480]; - __IOM uint32_t CNTENSET; /*!< Offset: 0xC00 (R/W) PMU Count Enable Set Register */ - uint32_t RESERVED4[7]; - __IOM uint32_t CNTENCLR; /*!< Offset: 0xC20 (R/W) PMU Count Enable Clear Register */ - uint32_t RESERVED5[7]; - __IOM uint32_t INTENSET; /*!< Offset: 0xC40 (R/W) PMU Interrupt Enable Set Register */ - uint32_t RESERVED6[7]; - __IOM uint32_t INTENCLR; /*!< Offset: 0xC60 (R/W) PMU Interrupt Enable Clear Register */ - uint32_t RESERVED7[7]; - __IOM uint32_t OVSCLR; /*!< Offset: 0xC80 (R/W) PMU Overflow Flag Status Clear Register */ - uint32_t RESERVED8[7]; - __IOM uint32_t SWINC; /*!< Offset: 0xCA0 (R/W) PMU Software Increment Register */ - uint32_t RESERVED9[7]; - __IOM uint32_t OVSSET; /*!< Offset: 0xCC0 (R/W) PMU Overflow Flag Status Set Register */ - uint32_t RESERVED10[79]; - __IOM uint32_t TYPE; /*!< Offset: 0xE00 (R/W) PMU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0xE04 (R/W) PMU Control Register */ - uint32_t RESERVED11[108]; - __IOM uint32_t AUTHSTATUS; /*!< Offset: 0xFB8 (R/W) PMU Authentication Status Register */ - __IOM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/W) PMU Device Architecture Register */ - uint32_t RESERVED12[3]; - __IOM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/W) PMU Device Type Register */ - __IOM uint32_t PIDR4; /*!< Offset: 0xFD0 (R/W) PMU Peripheral Identification Register 4 */ - uint32_t RESERVED13[3]; - __IOM uint32_t PIDR0; /*!< Offset: 0xFE0 (R/W) PMU Peripheral Identification Register 0 */ - __IOM uint32_t PIDR1; /*!< Offset: 0xFE4 (R/W) PMU Peripheral Identification Register 1 */ - __IOM uint32_t PIDR2; /*!< Offset: 0xFE8 (R/W) PMU Peripheral Identification Register 2 */ - __IOM uint32_t PIDR3; /*!< Offset: 0xFEC (R/W) PMU Peripheral Identification Register 3 */ - __IOM uint32_t CIDR0; /*!< Offset: 0xFF0 (R/W) PMU Component Identification Register 0 */ - __IOM uint32_t CIDR1; /*!< Offset: 0xFF4 (R/W) PMU Component Identification Register 1 */ - __IOM uint32_t CIDR2; /*!< Offset: 0xFF8 (R/W) PMU Component Identification Register 2 */ - __IOM uint32_t CIDR3; /*!< Offset: 0xFFC (R/W) PMU Component Identification Register 3 */ -} PMU_Type; - -/** \brief PMU Event Counter Registers (0-30) Definitions */ - -#define PMU_EVCNTR_CNT_Pos 0U /*!< PMU EVCNTR: Counter Position */ -#define PMU_EVCNTR_CNT_Msk (0xFFFFUL /*<< PMU_EVCNTRx_CNT_Pos*/) /*!< PMU EVCNTR: Counter Mask */ - -/** \brief PMU Event Type and Filter Registers (0-30) Definitions */ - -#define PMU_EVTYPER_EVENTTOCNT_Pos 0U /*!< PMU EVTYPER: Event to Count Position */ -#define PMU_EVTYPER_EVENTTOCNT_Msk (0xFFFFUL /*<< EVTYPERx_EVENTTOCNT_Pos*/) /*!< PMU EVTYPER: Event to Count Mask */ - -/** \brief PMU Count Enable Set Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENSET: Event Counter 0 Enable Set Position */ -#define PMU_CNTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENSET_CNT0_ENABLE_Pos*/) /*!< PMU CNTENSET: Event Counter 0 Enable Set Mask */ - -#define PMU_CNTENSET_CNT1_ENABLE_Pos 1U /*!< PMU CNTENSET: Event Counter 1 Enable Set Position */ -#define PMU_CNTENSET_CNT1_ENABLE_Msk (1UL << PMU_CNTENSET_CNT1_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 1 Enable Set Mask */ - -#define PMU_CNTENSET_CNT2_ENABLE_Pos 2U /*!< PMU CNTENSET: Event Counter 2 Enable Set Position */ -#define PMU_CNTENSET_CNT2_ENABLE_Msk (1UL << PMU_CNTENSET_CNT2_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 2 Enable Set Mask */ - -#define PMU_CNTENSET_CNT3_ENABLE_Pos 3U /*!< PMU CNTENSET: Event Counter 3 Enable Set Position */ -#define PMU_CNTENSET_CNT3_ENABLE_Msk (1UL << PMU_CNTENSET_CNT3_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 3 Enable Set Mask */ - -#define PMU_CNTENSET_CNT4_ENABLE_Pos 4U /*!< PMU CNTENSET: Event Counter 4 Enable Set Position */ -#define PMU_CNTENSET_CNT4_ENABLE_Msk (1UL << PMU_CNTENSET_CNT4_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 4 Enable Set Mask */ - -#define PMU_CNTENSET_CNT5_ENABLE_Pos 5U /*!< PMU CNTENSET: Event Counter 5 Enable Set Position */ -#define PMU_CNTENSET_CNT5_ENABLE_Msk (1UL << PMU_CNTENSET_CNT5_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 5 Enable Set Mask */ - -#define PMU_CNTENSET_CNT6_ENABLE_Pos 6U /*!< PMU CNTENSET: Event Counter 6 Enable Set Position */ -#define PMU_CNTENSET_CNT6_ENABLE_Msk (1UL << PMU_CNTENSET_CNT6_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 6 Enable Set Mask */ - -#define PMU_CNTENSET_CNT7_ENABLE_Pos 7U /*!< PMU CNTENSET: Event Counter 7 Enable Set Position */ -#define PMU_CNTENSET_CNT7_ENABLE_Msk (1UL << PMU_CNTENSET_CNT7_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 7 Enable Set Mask */ - -#define PMU_CNTENSET_CNT8_ENABLE_Pos 8U /*!< PMU CNTENSET: Event Counter 8 Enable Set Position */ -#define PMU_CNTENSET_CNT8_ENABLE_Msk (1UL << PMU_CNTENSET_CNT8_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 8 Enable Set Mask */ - -#define PMU_CNTENSET_CNT9_ENABLE_Pos 9U /*!< PMU CNTENSET: Event Counter 9 Enable Set Position */ -#define PMU_CNTENSET_CNT9_ENABLE_Msk (1UL << PMU_CNTENSET_CNT9_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 9 Enable Set Mask */ - -#define PMU_CNTENSET_CNT10_ENABLE_Pos 10U /*!< PMU CNTENSET: Event Counter 10 Enable Set Position */ -#define PMU_CNTENSET_CNT10_ENABLE_Msk (1UL << PMU_CNTENSET_CNT10_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 10 Enable Set Mask */ - -#define PMU_CNTENSET_CNT11_ENABLE_Pos 11U /*!< PMU CNTENSET: Event Counter 11 Enable Set Position */ -#define PMU_CNTENSET_CNT11_ENABLE_Msk (1UL << PMU_CNTENSET_CNT11_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 11 Enable Set Mask */ - -#define PMU_CNTENSET_CNT12_ENABLE_Pos 12U /*!< PMU CNTENSET: Event Counter 12 Enable Set Position */ -#define PMU_CNTENSET_CNT12_ENABLE_Msk (1UL << PMU_CNTENSET_CNT12_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 12 Enable Set Mask */ - -#define PMU_CNTENSET_CNT13_ENABLE_Pos 13U /*!< PMU CNTENSET: Event Counter 13 Enable Set Position */ -#define PMU_CNTENSET_CNT13_ENABLE_Msk (1UL << PMU_CNTENSET_CNT13_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 13 Enable Set Mask */ - -#define PMU_CNTENSET_CNT14_ENABLE_Pos 14U /*!< PMU CNTENSET: Event Counter 14 Enable Set Position */ -#define PMU_CNTENSET_CNT14_ENABLE_Msk (1UL << PMU_CNTENSET_CNT14_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 14 Enable Set Mask */ - -#define PMU_CNTENSET_CNT15_ENABLE_Pos 15U /*!< PMU CNTENSET: Event Counter 15 Enable Set Position */ -#define PMU_CNTENSET_CNT15_ENABLE_Msk (1UL << PMU_CNTENSET_CNT15_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 15 Enable Set Mask */ - -#define PMU_CNTENSET_CNT16_ENABLE_Pos 16U /*!< PMU CNTENSET: Event Counter 16 Enable Set Position */ -#define PMU_CNTENSET_CNT16_ENABLE_Msk (1UL << PMU_CNTENSET_CNT16_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 16 Enable Set Mask */ - -#define PMU_CNTENSET_CNT17_ENABLE_Pos 17U /*!< PMU CNTENSET: Event Counter 17 Enable Set Position */ -#define PMU_CNTENSET_CNT17_ENABLE_Msk (1UL << PMU_CNTENSET_CNT17_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 17 Enable Set Mask */ - -#define PMU_CNTENSET_CNT18_ENABLE_Pos 18U /*!< PMU CNTENSET: Event Counter 18 Enable Set Position */ -#define PMU_CNTENSET_CNT18_ENABLE_Msk (1UL << PMU_CNTENSET_CNT18_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 18 Enable Set Mask */ - -#define PMU_CNTENSET_CNT19_ENABLE_Pos 19U /*!< PMU CNTENSET: Event Counter 19 Enable Set Position */ -#define PMU_CNTENSET_CNT19_ENABLE_Msk (1UL << PMU_CNTENSET_CNT19_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 19 Enable Set Mask */ - -#define PMU_CNTENSET_CNT20_ENABLE_Pos 20U /*!< PMU CNTENSET: Event Counter 20 Enable Set Position */ -#define PMU_CNTENSET_CNT20_ENABLE_Msk (1UL << PMU_CNTENSET_CNT20_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 20 Enable Set Mask */ - -#define PMU_CNTENSET_CNT21_ENABLE_Pos 21U /*!< PMU CNTENSET: Event Counter 21 Enable Set Position */ -#define PMU_CNTENSET_CNT21_ENABLE_Msk (1UL << PMU_CNTENSET_CNT21_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 21 Enable Set Mask */ - -#define PMU_CNTENSET_CNT22_ENABLE_Pos 22U /*!< PMU CNTENSET: Event Counter 22 Enable Set Position */ -#define PMU_CNTENSET_CNT22_ENABLE_Msk (1UL << PMU_CNTENSET_CNT22_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 22 Enable Set Mask */ - -#define PMU_CNTENSET_CNT23_ENABLE_Pos 23U /*!< PMU CNTENSET: Event Counter 23 Enable Set Position */ -#define PMU_CNTENSET_CNT23_ENABLE_Msk (1UL << PMU_CNTENSET_CNT23_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 23 Enable Set Mask */ - -#define PMU_CNTENSET_CNT24_ENABLE_Pos 24U /*!< PMU CNTENSET: Event Counter 24 Enable Set Position */ -#define PMU_CNTENSET_CNT24_ENABLE_Msk (1UL << PMU_CNTENSET_CNT24_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 24 Enable Set Mask */ - -#define PMU_CNTENSET_CNT25_ENABLE_Pos 25U /*!< PMU CNTENSET: Event Counter 25 Enable Set Position */ -#define PMU_CNTENSET_CNT25_ENABLE_Msk (1UL << PMU_CNTENSET_CNT25_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 25 Enable Set Mask */ - -#define PMU_CNTENSET_CNT26_ENABLE_Pos 26U /*!< PMU CNTENSET: Event Counter 26 Enable Set Position */ -#define PMU_CNTENSET_CNT26_ENABLE_Msk (1UL << PMU_CNTENSET_CNT26_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 26 Enable Set Mask */ - -#define PMU_CNTENSET_CNT27_ENABLE_Pos 27U /*!< PMU CNTENSET: Event Counter 27 Enable Set Position */ -#define PMU_CNTENSET_CNT27_ENABLE_Msk (1UL << PMU_CNTENSET_CNT27_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 27 Enable Set Mask */ - -#define PMU_CNTENSET_CNT28_ENABLE_Pos 28U /*!< PMU CNTENSET: Event Counter 28 Enable Set Position */ -#define PMU_CNTENSET_CNT28_ENABLE_Msk (1UL << PMU_CNTENSET_CNT28_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 28 Enable Set Mask */ - -#define PMU_CNTENSET_CNT29_ENABLE_Pos 29U /*!< PMU CNTENSET: Event Counter 29 Enable Set Position */ -#define PMU_CNTENSET_CNT29_ENABLE_Msk (1UL << PMU_CNTENSET_CNT29_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 29 Enable Set Mask */ - -#define PMU_CNTENSET_CNT30_ENABLE_Pos 30U /*!< PMU CNTENSET: Event Counter 30 Enable Set Position */ -#define PMU_CNTENSET_CNT30_ENABLE_Msk (1UL << PMU_CNTENSET_CNT30_ENABLE_Pos) /*!< PMU CNTENSET: Event Counter 30 Enable Set Mask */ - -#define PMU_CNTENSET_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENSET: Cycle Counter Enable Set Position */ -#define PMU_CNTENSET_CCNTR_ENABLE_Msk (1UL << PMU_CNTENSET_CCNTR_ENABLE_Pos) /*!< PMU CNTENSET: Cycle Counter Enable Set Mask */ - -/** \brief PMU Count Enable Clear Register Definitions */ - -#define PMU_CNTENSET_CNT0_ENABLE_Pos 0U /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Position */ -#define PMU_CNTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_CNTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU CNTENCLR: Event Counter 0 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU CNTENCLR: Event Counter 1 Enable Clear Position */ -#define PMU_CNTENCLR_CNT1_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT1_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 1 Enable Clear */ - -#define PMU_CNTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Position */ -#define PMU_CNTENCLR_CNT2_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT2_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 2 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Position */ -#define PMU_CNTENCLR_CNT3_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT3_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 3 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Position */ -#define PMU_CNTENCLR_CNT4_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT4_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 4 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Position */ -#define PMU_CNTENCLR_CNT5_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT5_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 5 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Position */ -#define PMU_CNTENCLR_CNT6_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT6_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 6 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Position */ -#define PMU_CNTENCLR_CNT7_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT7_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 7 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Position */ -#define PMU_CNTENCLR_CNT8_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT8_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 8 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Position */ -#define PMU_CNTENCLR_CNT9_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT9_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 9 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Position */ -#define PMU_CNTENCLR_CNT10_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT10_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 10 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Position */ -#define PMU_CNTENCLR_CNT11_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT11_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 11 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Position */ -#define PMU_CNTENCLR_CNT12_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT12_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 12 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Position */ -#define PMU_CNTENCLR_CNT13_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT13_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 13 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Position */ -#define PMU_CNTENCLR_CNT14_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT14_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 14 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Position */ -#define PMU_CNTENCLR_CNT15_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT15_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 15 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Position */ -#define PMU_CNTENCLR_CNT16_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT16_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 16 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Position */ -#define PMU_CNTENCLR_CNT17_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT17_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 17 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Position */ -#define PMU_CNTENCLR_CNT18_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT18_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 18 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Position */ -#define PMU_CNTENCLR_CNT19_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT19_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 19 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Position */ -#define PMU_CNTENCLR_CNT20_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT20_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 20 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Position */ -#define PMU_CNTENCLR_CNT21_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT21_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 21 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Position */ -#define PMU_CNTENCLR_CNT22_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT22_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 22 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Position */ -#define PMU_CNTENCLR_CNT23_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT23_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 23 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Position */ -#define PMU_CNTENCLR_CNT24_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT24_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 24 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Position */ -#define PMU_CNTENCLR_CNT25_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT25_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 25 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Position */ -#define PMU_CNTENCLR_CNT26_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT26_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 26 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Position */ -#define PMU_CNTENCLR_CNT27_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT27_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 27 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Position */ -#define PMU_CNTENCLR_CNT28_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT28_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 28 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Position */ -#define PMU_CNTENCLR_CNT29_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT29_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 29 Enable Clear Mask */ - -#define PMU_CNTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Position */ -#define PMU_CNTENCLR_CNT30_ENABLE_Msk (1UL << PMU_CNTENCLR_CNT30_ENABLE_Pos) /*!< PMU CNTENCLR: Event Counter 30 Enable Clear Mask */ - -#define PMU_CNTENCLR_CCNTR_ENABLE_Pos 31U /*!< PMU CNTENCLR: Cycle Counter Enable Clear Position */ -#define PMU_CNTENCLR_CCNTR_ENABLE_Msk (1UL << PMU_CNTENCLR_CCNTR_ENABLE_Pos) /*!< PMU CNTENCLR: Cycle Counter Enable Clear Mask */ - -/** \brief PMU Interrupt Enable Set Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENSET_CNT0_ENABLE_Pos*/) /*!< PMU INTENSET: Event Counter 0 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT1_ENABLE_Pos 1U /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT1_ENABLE_Msk (1UL << PMU_INTENSET_CNT1_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 1 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT2_ENABLE_Pos 2U /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT2_ENABLE_Msk (1UL << PMU_INTENSET_CNT2_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 2 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT3_ENABLE_Pos 3U /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT3_ENABLE_Msk (1UL << PMU_INTENSET_CNT3_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 3 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT4_ENABLE_Pos 4U /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT4_ENABLE_Msk (1UL << PMU_INTENSET_CNT4_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 4 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT5_ENABLE_Pos 5U /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT5_ENABLE_Msk (1UL << PMU_INTENSET_CNT5_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 5 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT6_ENABLE_Pos 6U /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT6_ENABLE_Msk (1UL << PMU_INTENSET_CNT6_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 6 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT7_ENABLE_Pos 7U /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT7_ENABLE_Msk (1UL << PMU_INTENSET_CNT7_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 7 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT8_ENABLE_Pos 8U /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT8_ENABLE_Msk (1UL << PMU_INTENSET_CNT8_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 8 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT9_ENABLE_Pos 9U /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT9_ENABLE_Msk (1UL << PMU_INTENSET_CNT9_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 9 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT10_ENABLE_Pos 10U /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT10_ENABLE_Msk (1UL << PMU_INTENSET_CNT10_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 10 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT11_ENABLE_Pos 11U /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT11_ENABLE_Msk (1UL << PMU_INTENSET_CNT11_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 11 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT12_ENABLE_Pos 12U /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT12_ENABLE_Msk (1UL << PMU_INTENSET_CNT12_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 12 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT13_ENABLE_Pos 13U /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT13_ENABLE_Msk (1UL << PMU_INTENSET_CNT13_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 13 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT14_ENABLE_Pos 14U /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT14_ENABLE_Msk (1UL << PMU_INTENSET_CNT14_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 14 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT15_ENABLE_Pos 15U /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT15_ENABLE_Msk (1UL << PMU_INTENSET_CNT15_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 15 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT16_ENABLE_Pos 16U /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT16_ENABLE_Msk (1UL << PMU_INTENSET_CNT16_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 16 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT17_ENABLE_Pos 17U /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT17_ENABLE_Msk (1UL << PMU_INTENSET_CNT17_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 17 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT18_ENABLE_Pos 18U /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT18_ENABLE_Msk (1UL << PMU_INTENSET_CNT18_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 18 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT19_ENABLE_Pos 19U /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT19_ENABLE_Msk (1UL << PMU_INTENSET_CNT19_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 19 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT20_ENABLE_Pos 20U /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT20_ENABLE_Msk (1UL << PMU_INTENSET_CNT20_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 20 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT21_ENABLE_Pos 21U /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT21_ENABLE_Msk (1UL << PMU_INTENSET_CNT21_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 21 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT22_ENABLE_Pos 22U /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT22_ENABLE_Msk (1UL << PMU_INTENSET_CNT22_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 22 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT23_ENABLE_Pos 23U /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT23_ENABLE_Msk (1UL << PMU_INTENSET_CNT23_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 23 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT24_ENABLE_Pos 24U /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT24_ENABLE_Msk (1UL << PMU_INTENSET_CNT24_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 24 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT25_ENABLE_Pos 25U /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT25_ENABLE_Msk (1UL << PMU_INTENSET_CNT25_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 25 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT26_ENABLE_Pos 26U /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT26_ENABLE_Msk (1UL << PMU_INTENSET_CNT26_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 26 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT27_ENABLE_Pos 27U /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT27_ENABLE_Msk (1UL << PMU_INTENSET_CNT27_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 27 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT28_ENABLE_Pos 28U /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT28_ENABLE_Msk (1UL << PMU_INTENSET_CNT28_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 28 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT29_ENABLE_Pos 29U /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT29_ENABLE_Msk (1UL << PMU_INTENSET_CNT29_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 29 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CNT30_ENABLE_Pos 30U /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Position */ -#define PMU_INTENSET_CNT30_ENABLE_Msk (1UL << PMU_INTENSET_CNT30_ENABLE_Pos) /*!< PMU INTENSET: Event Counter 30 Interrupt Enable Set Mask */ - -#define PMU_INTENSET_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Position */ -#define PMU_INTENSET_CCYCNT_ENABLE_Msk (1UL << PMU_INTENSET_CYCCNT_ENABLE_Pos) /*!< PMU INTENSET: Cycle Counter Interrupt Enable Set Mask */ - -/** \brief PMU Interrupt Enable Clear Register Definitions */ - -#define PMU_INTENSET_CNT0_ENABLE_Pos 0U /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT0_ENABLE_Msk (1UL /*<< PMU_INTENCLR_CNT0_ENABLE_Pos*/) /*!< PMU INTENCLR: Event Counter 0 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT1_ENABLE_Pos 1U /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT1_ENABLE_Msk (1UL << PMU_INTENCLR_CNT1_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 1 Interrupt Enable Clear */ - -#define PMU_INTENCLR_CNT2_ENABLE_Pos 2U /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT2_ENABLE_Msk (1UL << PMU_INTENCLR_CNT2_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 2 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT3_ENABLE_Pos 3U /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT3_ENABLE_Msk (1UL << PMU_INTENCLR_CNT3_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 3 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT4_ENABLE_Pos 4U /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT4_ENABLE_Msk (1UL << PMU_INTENCLR_CNT4_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 4 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT5_ENABLE_Pos 5U /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT5_ENABLE_Msk (1UL << PMU_INTENCLR_CNT5_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 5 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT6_ENABLE_Pos 6U /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT6_ENABLE_Msk (1UL << PMU_INTENCLR_CNT6_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 6 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT7_ENABLE_Pos 7U /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT7_ENABLE_Msk (1UL << PMU_INTENCLR_CNT7_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 7 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT8_ENABLE_Pos 8U /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT8_ENABLE_Msk (1UL << PMU_INTENCLR_CNT8_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 8 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT9_ENABLE_Pos 9U /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT9_ENABLE_Msk (1UL << PMU_INTENCLR_CNT9_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 9 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT10_ENABLE_Pos 10U /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT10_ENABLE_Msk (1UL << PMU_INTENCLR_CNT10_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 10 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT11_ENABLE_Pos 11U /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT11_ENABLE_Msk (1UL << PMU_INTENCLR_CNT11_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 11 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT12_ENABLE_Pos 12U /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT12_ENABLE_Msk (1UL << PMU_INTENCLR_CNT12_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 12 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT13_ENABLE_Pos 13U /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT13_ENABLE_Msk (1UL << PMU_INTENCLR_CNT13_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 13 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT14_ENABLE_Pos 14U /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT14_ENABLE_Msk (1UL << PMU_INTENCLR_CNT14_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 14 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT15_ENABLE_Pos 15U /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT15_ENABLE_Msk (1UL << PMU_INTENCLR_CNT15_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 15 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT16_ENABLE_Pos 16U /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT16_ENABLE_Msk (1UL << PMU_INTENCLR_CNT16_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 16 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT17_ENABLE_Pos 17U /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT17_ENABLE_Msk (1UL << PMU_INTENCLR_CNT17_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 17 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT18_ENABLE_Pos 18U /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT18_ENABLE_Msk (1UL << PMU_INTENCLR_CNT18_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 18 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT19_ENABLE_Pos 19U /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT19_ENABLE_Msk (1UL << PMU_INTENCLR_CNT19_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 19 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT20_ENABLE_Pos 20U /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT20_ENABLE_Msk (1UL << PMU_INTENCLR_CNT20_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 20 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT21_ENABLE_Pos 21U /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT21_ENABLE_Msk (1UL << PMU_INTENCLR_CNT21_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 21 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT22_ENABLE_Pos 22U /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT22_ENABLE_Msk (1UL << PMU_INTENCLR_CNT22_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 22 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT23_ENABLE_Pos 23U /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT23_ENABLE_Msk (1UL << PMU_INTENCLR_CNT23_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 23 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT24_ENABLE_Pos 24U /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT24_ENABLE_Msk (1UL << PMU_INTENCLR_CNT24_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 24 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT25_ENABLE_Pos 25U /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT25_ENABLE_Msk (1UL << PMU_INTENCLR_CNT25_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 25 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT26_ENABLE_Pos 26U /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT26_ENABLE_Msk (1UL << PMU_INTENCLR_CNT26_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 26 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT27_ENABLE_Pos 27U /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT27_ENABLE_Msk (1UL << PMU_INTENCLR_CNT27_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 27 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT28_ENABLE_Pos 28U /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT28_ENABLE_Msk (1UL << PMU_INTENCLR_CNT28_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 28 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT29_ENABLE_Pos 29U /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT29_ENABLE_Msk (1UL << PMU_INTENCLR_CNT29_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 29 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CNT30_ENABLE_Pos 30U /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CNT30_ENABLE_Msk (1UL << PMU_INTENCLR_CNT30_ENABLE_Pos) /*!< PMU INTENCLR: Event Counter 30 Interrupt Enable Clear Mask */ - -#define PMU_INTENCLR_CYCCNT_ENABLE_Pos 31U /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Position */ -#define PMU_INTENCLR_CYCCNT_ENABLE_Msk (1UL << PMU_INTENCLR_CYCCNT_ENABLE_Pos) /*!< PMU INTENCLR: Cycle Counter Interrupt Enable Clear Mask */ - -/** \brief PMU Overflow Flag Status Set Register Definitions */ - -#define PMU_OVSSET_CNT0_STATUS_Pos 0U /*!< PMU OVSSET: Event Counter 0 Overflow Set Position */ -#define PMU_OVSSET_CNT0_STATUS_Msk (1UL /*<< PMU_OVSSET_CNT0_STATUS_Pos*/) /*!< PMU OVSSET: Event Counter 0 Overflow Set Mask */ - -#define PMU_OVSSET_CNT1_STATUS_Pos 1U /*!< PMU OVSSET: Event Counter 1 Overflow Set Position */ -#define PMU_OVSSET_CNT1_STATUS_Msk (1UL << PMU_OVSSET_CNT1_STATUS_Pos) /*!< PMU OVSSET: Event Counter 1 Overflow Set Mask */ - -#define PMU_OVSSET_CNT2_STATUS_Pos 2U /*!< PMU OVSSET: Event Counter 2 Overflow Set Position */ -#define PMU_OVSSET_CNT2_STATUS_Msk (1UL << PMU_OVSSET_CNT2_STATUS_Pos) /*!< PMU OVSSET: Event Counter 2 Overflow Set Mask */ - -#define PMU_OVSSET_CNT3_STATUS_Pos 3U /*!< PMU OVSSET: Event Counter 3 Overflow Set Position */ -#define PMU_OVSSET_CNT3_STATUS_Msk (1UL << PMU_OVSSET_CNT3_STATUS_Pos) /*!< PMU OVSSET: Event Counter 3 Overflow Set Mask */ - -#define PMU_OVSSET_CNT4_STATUS_Pos 4U /*!< PMU OVSSET: Event Counter 4 Overflow Set Position */ -#define PMU_OVSSET_CNT4_STATUS_Msk (1UL << PMU_OVSSET_CNT4_STATUS_Pos) /*!< PMU OVSSET: Event Counter 4 Overflow Set Mask */ - -#define PMU_OVSSET_CNT5_STATUS_Pos 5U /*!< PMU OVSSET: Event Counter 5 Overflow Set Position */ -#define PMU_OVSSET_CNT5_STATUS_Msk (1UL << PMU_OVSSET_CNT5_STATUS_Pos) /*!< PMU OVSSET: Event Counter 5 Overflow Set Mask */ - -#define PMU_OVSSET_CNT6_STATUS_Pos 6U /*!< PMU OVSSET: Event Counter 6 Overflow Set Position */ -#define PMU_OVSSET_CNT6_STATUS_Msk (1UL << PMU_OVSSET_CNT6_STATUS_Pos) /*!< PMU OVSSET: Event Counter 6 Overflow Set Mask */ - -#define PMU_OVSSET_CNT7_STATUS_Pos 7U /*!< PMU OVSSET: Event Counter 7 Overflow Set Position */ -#define PMU_OVSSET_CNT7_STATUS_Msk (1UL << PMU_OVSSET_CNT7_STATUS_Pos) /*!< PMU OVSSET: Event Counter 7 Overflow Set Mask */ - -#define PMU_OVSSET_CNT8_STATUS_Pos 8U /*!< PMU OVSSET: Event Counter 8 Overflow Set Position */ -#define PMU_OVSSET_CNT8_STATUS_Msk (1UL << PMU_OVSSET_CNT8_STATUS_Pos) /*!< PMU OVSSET: Event Counter 8 Overflow Set Mask */ - -#define PMU_OVSSET_CNT9_STATUS_Pos 9U /*!< PMU OVSSET: Event Counter 9 Overflow Set Position */ -#define PMU_OVSSET_CNT9_STATUS_Msk (1UL << PMU_OVSSET_CNT9_STATUS_Pos) /*!< PMU OVSSET: Event Counter 9 Overflow Set Mask */ - -#define PMU_OVSSET_CNT10_STATUS_Pos 10U /*!< PMU OVSSET: Event Counter 10 Overflow Set Position */ -#define PMU_OVSSET_CNT10_STATUS_Msk (1UL << PMU_OVSSET_CNT10_STATUS_Pos) /*!< PMU OVSSET: Event Counter 10 Overflow Set Mask */ - -#define PMU_OVSSET_CNT11_STATUS_Pos 11U /*!< PMU OVSSET: Event Counter 11 Overflow Set Position */ -#define PMU_OVSSET_CNT11_STATUS_Msk (1UL << PMU_OVSSET_CNT11_STATUS_Pos) /*!< PMU OVSSET: Event Counter 11 Overflow Set Mask */ - -#define PMU_OVSSET_CNT12_STATUS_Pos 12U /*!< PMU OVSSET: Event Counter 12 Overflow Set Position */ -#define PMU_OVSSET_CNT12_STATUS_Msk (1UL << PMU_OVSSET_CNT12_STATUS_Pos) /*!< PMU OVSSET: Event Counter 12 Overflow Set Mask */ - -#define PMU_OVSSET_CNT13_STATUS_Pos 13U /*!< PMU OVSSET: Event Counter 13 Overflow Set Position */ -#define PMU_OVSSET_CNT13_STATUS_Msk (1UL << PMU_OVSSET_CNT13_STATUS_Pos) /*!< PMU OVSSET: Event Counter 13 Overflow Set Mask */ - -#define PMU_OVSSET_CNT14_STATUS_Pos 14U /*!< PMU OVSSET: Event Counter 14 Overflow Set Position */ -#define PMU_OVSSET_CNT14_STATUS_Msk (1UL << PMU_OVSSET_CNT14_STATUS_Pos) /*!< PMU OVSSET: Event Counter 14 Overflow Set Mask */ - -#define PMU_OVSSET_CNT15_STATUS_Pos 15U /*!< PMU OVSSET: Event Counter 15 Overflow Set Position */ -#define PMU_OVSSET_CNT15_STATUS_Msk (1UL << PMU_OVSSET_CNT15_STATUS_Pos) /*!< PMU OVSSET: Event Counter 15 Overflow Set Mask */ - -#define PMU_OVSSET_CNT16_STATUS_Pos 16U /*!< PMU OVSSET: Event Counter 16 Overflow Set Position */ -#define PMU_OVSSET_CNT16_STATUS_Msk (1UL << PMU_OVSSET_CNT16_STATUS_Pos) /*!< PMU OVSSET: Event Counter 16 Overflow Set Mask */ - -#define PMU_OVSSET_CNT17_STATUS_Pos 17U /*!< PMU OVSSET: Event Counter 17 Overflow Set Position */ -#define PMU_OVSSET_CNT17_STATUS_Msk (1UL << PMU_OVSSET_CNT17_STATUS_Pos) /*!< PMU OVSSET: Event Counter 17 Overflow Set Mask */ - -#define PMU_OVSSET_CNT18_STATUS_Pos 18U /*!< PMU OVSSET: Event Counter 18 Overflow Set Position */ -#define PMU_OVSSET_CNT18_STATUS_Msk (1UL << PMU_OVSSET_CNT18_STATUS_Pos) /*!< PMU OVSSET: Event Counter 18 Overflow Set Mask */ - -#define PMU_OVSSET_CNT19_STATUS_Pos 19U /*!< PMU OVSSET: Event Counter 19 Overflow Set Position */ -#define PMU_OVSSET_CNT19_STATUS_Msk (1UL << PMU_OVSSET_CNT19_STATUS_Pos) /*!< PMU OVSSET: Event Counter 19 Overflow Set Mask */ - -#define PMU_OVSSET_CNT20_STATUS_Pos 20U /*!< PMU OVSSET: Event Counter 20 Overflow Set Position */ -#define PMU_OVSSET_CNT20_STATUS_Msk (1UL << PMU_OVSSET_CNT20_STATUS_Pos) /*!< PMU OVSSET: Event Counter 20 Overflow Set Mask */ - -#define PMU_OVSSET_CNT21_STATUS_Pos 21U /*!< PMU OVSSET: Event Counter 21 Overflow Set Position */ -#define PMU_OVSSET_CNT21_STATUS_Msk (1UL << PMU_OVSSET_CNT21_STATUS_Pos) /*!< PMU OVSSET: Event Counter 21 Overflow Set Mask */ - -#define PMU_OVSSET_CNT22_STATUS_Pos 22U /*!< PMU OVSSET: Event Counter 22 Overflow Set Position */ -#define PMU_OVSSET_CNT22_STATUS_Msk (1UL << PMU_OVSSET_CNT22_STATUS_Pos) /*!< PMU OVSSET: Event Counter 22 Overflow Set Mask */ - -#define PMU_OVSSET_CNT23_STATUS_Pos 23U /*!< PMU OVSSET: Event Counter 23 Overflow Set Position */ -#define PMU_OVSSET_CNT23_STATUS_Msk (1UL << PMU_OVSSET_CNT23_STATUS_Pos) /*!< PMU OVSSET: Event Counter 23 Overflow Set Mask */ - -#define PMU_OVSSET_CNT24_STATUS_Pos 24U /*!< PMU OVSSET: Event Counter 24 Overflow Set Position */ -#define PMU_OVSSET_CNT24_STATUS_Msk (1UL << PMU_OVSSET_CNT24_STATUS_Pos) /*!< PMU OVSSET: Event Counter 24 Overflow Set Mask */ - -#define PMU_OVSSET_CNT25_STATUS_Pos 25U /*!< PMU OVSSET: Event Counter 25 Overflow Set Position */ -#define PMU_OVSSET_CNT25_STATUS_Msk (1UL << PMU_OVSSET_CNT25_STATUS_Pos) /*!< PMU OVSSET: Event Counter 25 Overflow Set Mask */ - -#define PMU_OVSSET_CNT26_STATUS_Pos 26U /*!< PMU OVSSET: Event Counter 26 Overflow Set Position */ -#define PMU_OVSSET_CNT26_STATUS_Msk (1UL << PMU_OVSSET_CNT26_STATUS_Pos) /*!< PMU OVSSET: Event Counter 26 Overflow Set Mask */ - -#define PMU_OVSSET_CNT27_STATUS_Pos 27U /*!< PMU OVSSET: Event Counter 27 Overflow Set Position */ -#define PMU_OVSSET_CNT27_STATUS_Msk (1UL << PMU_OVSSET_CNT27_STATUS_Pos) /*!< PMU OVSSET: Event Counter 27 Overflow Set Mask */ - -#define PMU_OVSSET_CNT28_STATUS_Pos 28U /*!< PMU OVSSET: Event Counter 28 Overflow Set Position */ -#define PMU_OVSSET_CNT28_STATUS_Msk (1UL << PMU_OVSSET_CNT28_STATUS_Pos) /*!< PMU OVSSET: Event Counter 28 Overflow Set Mask */ - -#define PMU_OVSSET_CNT29_STATUS_Pos 29U /*!< PMU OVSSET: Event Counter 29 Overflow Set Position */ -#define PMU_OVSSET_CNT29_STATUS_Msk (1UL << PMU_OVSSET_CNT29_STATUS_Pos) /*!< PMU OVSSET: Event Counter 29 Overflow Set Mask */ - -#define PMU_OVSSET_CNT30_STATUS_Pos 30U /*!< PMU OVSSET: Event Counter 30 Overflow Set Position */ -#define PMU_OVSSET_CNT30_STATUS_Msk (1UL << PMU_OVSSET_CNT30_STATUS_Pos) /*!< PMU OVSSET: Event Counter 30 Overflow Set Mask */ - -#define PMU_OVSSET_CYCCNT_STATUS_Pos 31U /*!< PMU OVSSET: Cycle Counter Overflow Set Position */ -#define PMU_OVSSET_CYCCNT_STATUS_Msk (1UL << PMU_OVSSET_CYCCNT_STATUS_Pos) /*!< PMU OVSSET: Cycle Counter Overflow Set Mask */ - -/** \brief PMU Overflow Flag Status Clear Register Definitions */ - -#define PMU_OVSCLR_CNT0_STATUS_Pos 0U /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Position */ -#define PMU_OVSCLR_CNT0_STATUS_Msk (1UL /*<< PMU_OVSCLR_CNT0_STATUS_Pos*/) /*!< PMU OVSCLR: Event Counter 0 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT1_STATUS_Pos 1U /*!< PMU OVSCLR: Event Counter 1 Overflow Clear Position */ -#define PMU_OVSCLR_CNT1_STATUS_Msk (1UL << PMU_OVSCLR_CNT1_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 1 Overflow Clear */ - -#define PMU_OVSCLR_CNT2_STATUS_Pos 2U /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Position */ -#define PMU_OVSCLR_CNT2_STATUS_Msk (1UL << PMU_OVSCLR_CNT2_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 2 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT3_STATUS_Pos 3U /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Position */ -#define PMU_OVSCLR_CNT3_STATUS_Msk (1UL << PMU_OVSCLR_CNT3_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 3 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT4_STATUS_Pos 4U /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Position */ -#define PMU_OVSCLR_CNT4_STATUS_Msk (1UL << PMU_OVSCLR_CNT4_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 4 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT5_STATUS_Pos 5U /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Position */ -#define PMU_OVSCLR_CNT5_STATUS_Msk (1UL << PMU_OVSCLR_CNT5_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 5 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT6_STATUS_Pos 6U /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Position */ -#define PMU_OVSCLR_CNT6_STATUS_Msk (1UL << PMU_OVSCLR_CNT6_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 6 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT7_STATUS_Pos 7U /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Position */ -#define PMU_OVSCLR_CNT7_STATUS_Msk (1UL << PMU_OVSCLR_CNT7_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 7 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT8_STATUS_Pos 8U /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Position */ -#define PMU_OVSCLR_CNT8_STATUS_Msk (1UL << PMU_OVSCLR_CNT8_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 8 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT9_STATUS_Pos 9U /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Position */ -#define PMU_OVSCLR_CNT9_STATUS_Msk (1UL << PMU_OVSCLR_CNT9_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 9 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT10_STATUS_Pos 10U /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Position */ -#define PMU_OVSCLR_CNT10_STATUS_Msk (1UL << PMU_OVSCLR_CNT10_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 10 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT11_STATUS_Pos 11U /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Position */ -#define PMU_OVSCLR_CNT11_STATUS_Msk (1UL << PMU_OVSCLR_CNT11_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 11 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT12_STATUS_Pos 12U /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Position */ -#define PMU_OVSCLR_CNT12_STATUS_Msk (1UL << PMU_OVSCLR_CNT12_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 12 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT13_STATUS_Pos 13U /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Position */ -#define PMU_OVSCLR_CNT13_STATUS_Msk (1UL << PMU_OVSCLR_CNT13_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 13 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT14_STATUS_Pos 14U /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Position */ -#define PMU_OVSCLR_CNT14_STATUS_Msk (1UL << PMU_OVSCLR_CNT14_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 14 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT15_STATUS_Pos 15U /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Position */ -#define PMU_OVSCLR_CNT15_STATUS_Msk (1UL << PMU_OVSCLR_CNT15_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 15 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT16_STATUS_Pos 16U /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Position */ -#define PMU_OVSCLR_CNT16_STATUS_Msk (1UL << PMU_OVSCLR_CNT16_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 16 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT17_STATUS_Pos 17U /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Position */ -#define PMU_OVSCLR_CNT17_STATUS_Msk (1UL << PMU_OVSCLR_CNT17_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 17 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT18_STATUS_Pos 18U /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Position */ -#define PMU_OVSCLR_CNT18_STATUS_Msk (1UL << PMU_OVSCLR_CNT18_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 18 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT19_STATUS_Pos 19U /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Position */ -#define PMU_OVSCLR_CNT19_STATUS_Msk (1UL << PMU_OVSCLR_CNT19_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 19 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT20_STATUS_Pos 20U /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Position */ -#define PMU_OVSCLR_CNT20_STATUS_Msk (1UL << PMU_OVSCLR_CNT20_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 20 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT21_STATUS_Pos 21U /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Position */ -#define PMU_OVSCLR_CNT21_STATUS_Msk (1UL << PMU_OVSCLR_CNT21_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 21 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT22_STATUS_Pos 22U /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Position */ -#define PMU_OVSCLR_CNT22_STATUS_Msk (1UL << PMU_OVSCLR_CNT22_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 22 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT23_STATUS_Pos 23U /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Position */ -#define PMU_OVSCLR_CNT23_STATUS_Msk (1UL << PMU_OVSCLR_CNT23_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 23 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT24_STATUS_Pos 24U /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Position */ -#define PMU_OVSCLR_CNT24_STATUS_Msk (1UL << PMU_OVSCLR_CNT24_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 24 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT25_STATUS_Pos 25U /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Position */ -#define PMU_OVSCLR_CNT25_STATUS_Msk (1UL << PMU_OVSCLR_CNT25_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 25 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT26_STATUS_Pos 26U /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Position */ -#define PMU_OVSCLR_CNT26_STATUS_Msk (1UL << PMU_OVSCLR_CNT26_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 26 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT27_STATUS_Pos 27U /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Position */ -#define PMU_OVSCLR_CNT27_STATUS_Msk (1UL << PMU_OVSCLR_CNT27_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 27 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT28_STATUS_Pos 28U /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Position */ -#define PMU_OVSCLR_CNT28_STATUS_Msk (1UL << PMU_OVSCLR_CNT28_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 28 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT29_STATUS_Pos 29U /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Position */ -#define PMU_OVSCLR_CNT29_STATUS_Msk (1UL << PMU_OVSCLR_CNT29_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 29 Overflow Clear Mask */ - -#define PMU_OVSCLR_CNT30_STATUS_Pos 30U /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Position */ -#define PMU_OVSCLR_CNT30_STATUS_Msk (1UL << PMU_OVSCLR_CNT30_STATUS_Pos) /*!< PMU OVSCLR: Event Counter 30 Overflow Clear Mask */ - -#define PMU_OVSCLR_CYCCNT_STATUS_Pos 31U /*!< PMU OVSCLR: Cycle Counter Overflow Clear Position */ -#define PMU_OVSCLR_CYCCNT_STATUS_Msk (1UL << PMU_OVSCLR_CYCCNT_STATUS_Pos) /*!< PMU OVSCLR: Cycle Counter Overflow Clear Mask */ - -/** \brief PMU Software Increment Counter */ - -#define PMU_SWINC_CNT0_Pos 0U /*!< PMU SWINC: Event Counter 0 Software Increment Position */ -#define PMU_SWINC_CNT0_Msk (1UL /*<< PMU_SWINC_CNT0_Pos */) /*!< PMU SWINC: Event Counter 0 Software Increment Mask */ - -#define PMU_SWINC_CNT1_Pos 1U /*!< PMU SWINC: Event Counter 1 Software Increment Position */ -#define PMU_SWINC_CNT1_Msk (1UL << PMU_SWINC_CNT1_Pos) /*!< PMU SWINC: Event Counter 1 Software Increment Mask */ - -#define PMU_SWINC_CNT2_Pos 2U /*!< PMU SWINC: Event Counter 2 Software Increment Position */ -#define PMU_SWINC_CNT2_Msk (1UL << PMU_SWINC_CNT2_Pos) /*!< PMU SWINC: Event Counter 2 Software Increment Mask */ - -#define PMU_SWINC_CNT3_Pos 3U /*!< PMU SWINC: Event Counter 3 Software Increment Position */ -#define PMU_SWINC_CNT3_Msk (1UL << PMU_SWINC_CNT3_Pos) /*!< PMU SWINC: Event Counter 3 Software Increment Mask */ - -#define PMU_SWINC_CNT4_Pos 4U /*!< PMU SWINC: Event Counter 4 Software Increment Position */ -#define PMU_SWINC_CNT4_Msk (1UL << PMU_SWINC_CNT4_Pos) /*!< PMU SWINC: Event Counter 4 Software Increment Mask */ - -#define PMU_SWINC_CNT5_Pos 5U /*!< PMU SWINC: Event Counter 5 Software Increment Position */ -#define PMU_SWINC_CNT5_Msk (1UL << PMU_SWINC_CNT5_Pos) /*!< PMU SWINC: Event Counter 5 Software Increment Mask */ - -#define PMU_SWINC_CNT6_Pos 6U /*!< PMU SWINC: Event Counter 6 Software Increment Position */ -#define PMU_SWINC_CNT6_Msk (1UL << PMU_SWINC_CNT6_Pos) /*!< PMU SWINC: Event Counter 6 Software Increment Mask */ - -#define PMU_SWINC_CNT7_Pos 7U /*!< PMU SWINC: Event Counter 7 Software Increment Position */ -#define PMU_SWINC_CNT7_Msk (1UL << PMU_SWINC_CNT7_Pos) /*!< PMU SWINC: Event Counter 7 Software Increment Mask */ - -#define PMU_SWINC_CNT8_Pos 8U /*!< PMU SWINC: Event Counter 8 Software Increment Position */ -#define PMU_SWINC_CNT8_Msk (1UL << PMU_SWINC_CNT8_Pos) /*!< PMU SWINC: Event Counter 8 Software Increment Mask */ - -#define PMU_SWINC_CNT9_Pos 9U /*!< PMU SWINC: Event Counter 9 Software Increment Position */ -#define PMU_SWINC_CNT9_Msk (1UL << PMU_SWINC_CNT9_Pos) /*!< PMU SWINC: Event Counter 9 Software Increment Mask */ - -#define PMU_SWINC_CNT10_Pos 10U /*!< PMU SWINC: Event Counter 10 Software Increment Position */ -#define PMU_SWINC_CNT10_Msk (1UL << PMU_SWINC_CNT10_Pos) /*!< PMU SWINC: Event Counter 10 Software Increment Mask */ - -#define PMU_SWINC_CNT11_Pos 11U /*!< PMU SWINC: Event Counter 11 Software Increment Position */ -#define PMU_SWINC_CNT11_Msk (1UL << PMU_SWINC_CNT11_Pos) /*!< PMU SWINC: Event Counter 11 Software Increment Mask */ - -#define PMU_SWINC_CNT12_Pos 12U /*!< PMU SWINC: Event Counter 12 Software Increment Position */ -#define PMU_SWINC_CNT12_Msk (1UL << PMU_SWINC_CNT12_Pos) /*!< PMU SWINC: Event Counter 12 Software Increment Mask */ - -#define PMU_SWINC_CNT13_Pos 13U /*!< PMU SWINC: Event Counter 13 Software Increment Position */ -#define PMU_SWINC_CNT13_Msk (1UL << PMU_SWINC_CNT13_Pos) /*!< PMU SWINC: Event Counter 13 Software Increment Mask */ - -#define PMU_SWINC_CNT14_Pos 14U /*!< PMU SWINC: Event Counter 14 Software Increment Position */ -#define PMU_SWINC_CNT14_Msk (1UL << PMU_SWINC_CNT14_Pos) /*!< PMU SWINC: Event Counter 14 Software Increment Mask */ - -#define PMU_SWINC_CNT15_Pos 15U /*!< PMU SWINC: Event Counter 15 Software Increment Position */ -#define PMU_SWINC_CNT15_Msk (1UL << PMU_SWINC_CNT15_Pos) /*!< PMU SWINC: Event Counter 15 Software Increment Mask */ - -#define PMU_SWINC_CNT16_Pos 16U /*!< PMU SWINC: Event Counter 16 Software Increment Position */ -#define PMU_SWINC_CNT16_Msk (1UL << PMU_SWINC_CNT16_Pos) /*!< PMU SWINC: Event Counter 16 Software Increment Mask */ - -#define PMU_SWINC_CNT17_Pos 17U /*!< PMU SWINC: Event Counter 17 Software Increment Position */ -#define PMU_SWINC_CNT17_Msk (1UL << PMU_SWINC_CNT17_Pos) /*!< PMU SWINC: Event Counter 17 Software Increment Mask */ - -#define PMU_SWINC_CNT18_Pos 18U /*!< PMU SWINC: Event Counter 18 Software Increment Position */ -#define PMU_SWINC_CNT18_Msk (1UL << PMU_SWINC_CNT18_Pos) /*!< PMU SWINC: Event Counter 18 Software Increment Mask */ - -#define PMU_SWINC_CNT19_Pos 19U /*!< PMU SWINC: Event Counter 19 Software Increment Position */ -#define PMU_SWINC_CNT19_Msk (1UL << PMU_SWINC_CNT19_Pos) /*!< PMU SWINC: Event Counter 19 Software Increment Mask */ - -#define PMU_SWINC_CNT20_Pos 20U /*!< PMU SWINC: Event Counter 20 Software Increment Position */ -#define PMU_SWINC_CNT20_Msk (1UL << PMU_SWINC_CNT20_Pos) /*!< PMU SWINC: Event Counter 20 Software Increment Mask */ - -#define PMU_SWINC_CNT21_Pos 21U /*!< PMU SWINC: Event Counter 21 Software Increment Position */ -#define PMU_SWINC_CNT21_Msk (1UL << PMU_SWINC_CNT21_Pos) /*!< PMU SWINC: Event Counter 21 Software Increment Mask */ - -#define PMU_SWINC_CNT22_Pos 22U /*!< PMU SWINC: Event Counter 22 Software Increment Position */ -#define PMU_SWINC_CNT22_Msk (1UL << PMU_SWINC_CNT22_Pos) /*!< PMU SWINC: Event Counter 22 Software Increment Mask */ - -#define PMU_SWINC_CNT23_Pos 23U /*!< PMU SWINC: Event Counter 23 Software Increment Position */ -#define PMU_SWINC_CNT23_Msk (1UL << PMU_SWINC_CNT23_Pos) /*!< PMU SWINC: Event Counter 23 Software Increment Mask */ - -#define PMU_SWINC_CNT24_Pos 24U /*!< PMU SWINC: Event Counter 24 Software Increment Position */ -#define PMU_SWINC_CNT24_Msk (1UL << PMU_SWINC_CNT24_Pos) /*!< PMU SWINC: Event Counter 24 Software Increment Mask */ - -#define PMU_SWINC_CNT25_Pos 25U /*!< PMU SWINC: Event Counter 25 Software Increment Position */ -#define PMU_SWINC_CNT25_Msk (1UL << PMU_SWINC_CNT25_Pos) /*!< PMU SWINC: Event Counter 25 Software Increment Mask */ - -#define PMU_SWINC_CNT26_Pos 26U /*!< PMU SWINC: Event Counter 26 Software Increment Position */ -#define PMU_SWINC_CNT26_Msk (1UL << PMU_SWINC_CNT26_Pos) /*!< PMU SWINC: Event Counter 26 Software Increment Mask */ - -#define PMU_SWINC_CNT27_Pos 27U /*!< PMU SWINC: Event Counter 27 Software Increment Position */ -#define PMU_SWINC_CNT27_Msk (1UL << PMU_SWINC_CNT27_Pos) /*!< PMU SWINC: Event Counter 27 Software Increment Mask */ - -#define PMU_SWINC_CNT28_Pos 28U /*!< PMU SWINC: Event Counter 28 Software Increment Position */ -#define PMU_SWINC_CNT28_Msk (1UL << PMU_SWINC_CNT28_Pos) /*!< PMU SWINC: Event Counter 28 Software Increment Mask */ - -#define PMU_SWINC_CNT29_Pos 29U /*!< PMU SWINC: Event Counter 29 Software Increment Position */ -#define PMU_SWINC_CNT29_Msk (1UL << PMU_SWINC_CNT29_Pos) /*!< PMU SWINC: Event Counter 29 Software Increment Mask */ - -#define PMU_SWINC_CNT30_Pos 30U /*!< PMU SWINC: Event Counter 30 Software Increment Position */ -#define PMU_SWINC_CNT30_Msk (1UL << PMU_SWINC_CNT30_Pos) /*!< PMU SWINC: Event Counter 30 Software Increment Mask */ - -/** \brief PMU Control Register Definitions */ - -#define PMU_CTRL_ENABLE_Pos 0U /*!< PMU CTRL: ENABLE Position */ -#define PMU_CTRL_ENABLE_Msk (1UL /*<< PMU_CTRL_ENABLE_Pos*/) /*!< PMU CTRL: ENABLE Mask */ - -#define PMU_CTRL_EVENTCNT_RESET_Pos 1U /*!< PMU CTRL: Event Counter Reset Position */ -#define PMU_CTRL_EVENTCNT_RESET_Msk (1UL << PMU_CTRL_EVENTCNT_RESET_Pos) /*!< PMU CTRL: Event Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_RESET_Pos 2U /*!< PMU CTRL: Cycle Counter Reset Position */ -#define PMU_CTRL_CYCCNT_RESET_Msk (1UL << PMU_CTRL_CYCCNT_RESET_Pos) /*!< PMU CTRL: Cycle Counter Reset Mask */ - -#define PMU_CTRL_CYCCNT_DISABLE_Pos 5U /*!< PMU CTRL: Disable Cycle Counter Position */ -#define PMU_CTRL_CYCCNT_DISABLE_Msk (1UL << PMU_CTRL_CYCCNT_DISABLE_Pos) /*!< PMU CTRL: Disable Cycle Counter Mask */ - -#define PMU_CTRL_FRZ_ON_OV_Pos 9U /*!< PMU CTRL: Freeze-on-overflow Position */ -#define PMU_CTRL_FRZ_ON_OV_Msk (1UL << PMU_CTRL_FRZ_ON_OVERFLOW_Pos) /*!< PMU CTRL: Freeze-on-overflow Mask */ - -#define PMU_CTRL_TRACE_ON_OV_Pos 11U /*!< PMU CTRL: Trace-on-overflow Position */ -#define PMU_CTRL_TRACE_ON_OV_Msk (1UL << PMU_CTRL_TRACE_ON_OVERFLOW_Pos) /*!< PMU CTRL: Trace-on-overflow Mask */ - -/** \brief PMU Type Register Definitions */ - -#define PMU_TYPE_NUM_CNTS_Pos 0U /*!< PMU TYPE: Number of Counters Position */ -#define PMU_TYPE_NUM_CNTS_Msk (0xFFUL /*<< PMU_TYPE_NUM_CNTS_Pos*/) /*!< PMU TYPE: Number of Counters Mask */ - -#define PMU_TYPE_SIZE_CNTS_Pos 8U /*!< PMU TYPE: Size of Counters Position */ -#define PMU_TYPE_SIZE_CNTS_Msk (0x3FUL << PMU_TYPE_SIZE_CNTS_Pos) /*!< PMU TYPE: Size of Counters Mask */ - -#define PMU_TYPE_CYCCNT_PRESENT_Pos 14U /*!< PMU TYPE: Cycle Counter Present Position */ -#define PMU_TYPE_CYCCNT_PRESENT_Msk (1UL << PMU_TYPE_CYCCNT_PRESENT_Pos) /*!< PMU TYPE: Cycle Counter Present Mask */ - -#define PMU_TYPE_FRZ_OV_SUPPORT_Pos 21U /*!< PMU TYPE: Freeze-on-overflow Support Position */ -#define PMU_TYPE_FRZ_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Freeze-on-overflow Support Mask */ - -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Pos 23U /*!< PMU TYPE: Trace-on-overflow Support Position */ -#define PMU_TYPE_TRACE_ON_OV_SUPPORT_Msk (1UL << PMU_TYPE_FRZ_OV_SUPPORT_Pos) /*!< PMU TYPE: Trace-on-overflow Support Mask */ - -/** \brief PMU Authentication Status Register Definitions */ - -#define PMU_AUTHSTATUS_NSID_Pos 0U /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSID_Msk (0x3UL /*<< PMU_AUTHSTATUS_NSID_Pos*/) /*!< PMU AUTHSTATUS: Non-secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSNID_Pos 2U /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSNID_Msk (0x3UL << PMU_AUTHSTATUS_NSNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SID_Pos 4U /*!< PMU AUTHSTATUS: Secure Invasive Debug Position */ -#define PMU_AUTHSTATUS_SID_Msk (0x3UL << PMU_AUTHSTATUS_SID_Pos) /*!< PMU AUTHSTATUS: Secure Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SNID_Pos 6U /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SNID_Msk (0x3UL << PMU_AUTHSTATUS_SNID_Pos) /*!< PMU AUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUID_Pos 16U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUID_Msk (0x3UL << PMU_AUTHSTATUS_NSUID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_NSUNID_Pos 18U /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_NSUNID_Msk (0x3UL << PMU_AUTHSTATUS_NSUNID_Pos) /*!< PMU AUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUID_Pos 20U /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Position */ -#define PMU_AUTHSTATUS_SUID_Msk (0x3UL << PMU_AUTHSTATUS_SUID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Invasive Debug Mask */ - -#define PMU_AUTHSTATUS_SUNID_Pos 22U /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Position */ -#define PMU_AUTHSTATUS_SUNID_Msk (0x3UL << PMU_AUTHSTATUS_SUNID_Pos) /*!< PMU AUTHSTATUS: Secure Unprivileged Non-invasive Debug Mask */ - - -/*@} end of group CMSIS_PMU */ -#endif - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ -#define MPU_RLAR_PXN_Msk (1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -#define FPU_FPDSCR_FZ16_Pos 19U /*!< FPDSCR: FZ16 bit Position */ -#define FPU_FPDSCR_FZ16_Msk (1UL << FPU_FPDSCR_FZ16_Pos) /*!< FPDSCR: FZ16 bit Mask */ - -#define FPU_FPDSCR_LTPSIZE_Pos 16U /*!< FPDSCR: LTPSIZE bit Position */ -#define FPU_FPDSCR_LTPSIZE_Msk (7UL << FPU_FPDSCR_LTPSIZE_Pos) /*!< FPDSCR: LTPSIZE bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FPRound_Pos 28U /*!< MVFR0: FPRound bits Position */ -#define FPU_MVFR0_FPRound_Msk (0xFUL << FPU_MVFR0_FPRound_Pos) /*!< MVFR0: FPRound bits Mask */ - -#define FPU_MVFR0_FPSqrt_Pos 20U /*!< MVFR0: FPSqrt bits Position */ -#define FPU_MVFR0_FPSqrt_Msk (0xFUL << FPU_MVFR0_FPSqrt_Pos) /*!< MVFR0: FPSqrt bits Mask */ - -#define FPU_MVFR0_FPDivide_Pos 16U /*!< MVFR0: FPDivide bits Position */ -#define FPU_MVFR0_FPDivide_Msk (0xFUL << FPU_MVFR0_FPDivide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FPDP_Pos 8U /*!< MVFR0: FPDP bits Position */ -#define FPU_MVFR0_FPDP_Msk (0xFUL << FPU_MVFR0_FPDP_Pos) /*!< MVFR0: FPDP bits Mask */ - -#define FPU_MVFR0_FPSP_Pos 4U /*!< MVFR0: FPSP bits Position */ -#define FPU_MVFR0_FPSP_Msk (0xFUL << FPU_MVFR0_FPSP_Pos) /*!< MVFR0: FPSP bits Mask */ - -#define FPU_MVFR0_SIMDReg_Pos 0U /*!< MVFR0: SIMDReg bits Position */ -#define FPU_MVFR0_SIMDReg_Msk (0xFUL /*<< FPU_MVFR0_SIMDReg_Pos*/) /*!< MVFR0: SIMDReg bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FMAC_Pos 28U /*!< MVFR1: FMAC bits Position */ -#define FPU_MVFR1_FMAC_Msk (0xFUL << FPU_MVFR1_FMAC_Pos) /*!< MVFR1: FMAC bits Mask */ - -#define FPU_MVFR1_FPHP_Pos 24U /*!< MVFR1: FPHP bits Position */ -#define FPU_MVFR1_FPHP_Msk (0xFUL << FPU_MVFR1_FPHP_Pos) /*!< MVFR1: FPHP bits Mask */ - -#define FPU_MVFR1_FP16_Pos 20U /*!< MVFR1: FP16 bits Position */ -#define FPU_MVFR1_FP16_Msk (0xFUL << FPU_MVFR1_FP16_Pos) /*!< MVFR1: FP16 bits Mask */ - -#define FPU_MVFR1_MVE_Pos 8U /*!< MVFR1: MVE bits Position */ -#define FPU_MVFR1_MVE_Msk (0xFUL << FPU_MVFR1_MVE_Pos) /*!< MVFR1: MVE bits Mask */ - -#define FPU_MVFR1_FPDNaN_Pos 4U /*!< MVFR1: FPDNaN bits Position */ -#define FPU_MVFR1_FPDNaN_Msk (0xFUL << FPU_MVFR1_FPDNaN_Pos) /*!< MVFR1: FPDNaN bits Mask */ - -#define FPU_MVFR1_FPFtZ_Pos 0U /*!< MVFR1: FPFtZ bits Position */ -#define FPU_MVFR1_FPFtZ_Msk (0xFUL /*<< FPU_MVFR1_FPFtZ_Pos*/) /*!< MVFR1: FPFtZ bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - -/* CoreDebug is deprecated. replaced by DCB (Debug Control Block) */ -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief \deprecated Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< \deprecated CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< \deprecated CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Position */ -#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESTART_ST Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< \deprecated CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_FPD_Pos 23U /*!< \deprecated CoreDebug DHCSR: S_FPD Position */ -#define CoreDebug_DHCSR_S_FPD_Msk (1UL << CoreDebug_DHCSR_S_FPD_Pos) /*!< \deprecated CoreDebug DHCSR: S_FPD Mask */ - -#define CoreDebug_DHCSR_S_SUIDE_Pos 22U /*!< \deprecated CoreDebug DHCSR: S_SUIDE Position */ -#define CoreDebug_DHCSR_S_SUIDE_Msk (1UL << CoreDebug_DHCSR_S_SUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SUIDE Mask */ - -#define CoreDebug_DHCSR_S_NSUIDE_Pos 21U /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Position */ -#define CoreDebug_DHCSR_S_NSUIDE_Msk (1UL << CoreDebug_DHCSR_S_NSUIDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_NSUIDE Mask */ - -#define CoreDebug_DHCSR_S_SDE_Pos 20U /*!< \deprecated CoreDebug DHCSR: S_SDE Position */ -#define CoreDebug_DHCSR_S_SDE_Msk (1UL << CoreDebug_DHCSR_S_SDE_Pos) /*!< \deprecated CoreDebug DHCSR: S_SDE Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< \deprecated CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< \deprecated CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< \deprecated CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< \deprecated CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< \deprecated CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< \deprecated CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_PMOV_Pos 6U /*!< \deprecated CoreDebug DHCSR: C_PMOV Position */ -#define CoreDebug_DHCSR_C_PMOV_Msk (1UL << CoreDebug_DHCSR_C_PMOV_Pos) /*!< \deprecated CoreDebug DHCSR: C_PMOV Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< \deprecated CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< \deprecated CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< \deprecated CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< \deprecated CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< \deprecated CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< \deprecated CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< \deprecated CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< \deprecated CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< \deprecated CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< \deprecated CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< \deprecated CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< \deprecated CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< \deprecated CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< \deprecated CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< \deprecated CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< \deprecated CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< \deprecated CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< \deprecated CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< \deprecated CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< \deprecated CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< \deprecated CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< \deprecated CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< \deprecated CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< \deprecated CoreDebug DEMCR: VC_CORERESET Mask */ - -/* Debug Set Clear Exception and Monitor Control Register Definitions */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_CLR_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_CLR_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: CLR_MON_PEND, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_REQ_Pos 3U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Position */ -#define CoreDebug_DSCEMCR_SET_MON_REQ_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_REQ_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_REQ, Mask */ - -#define CoreDebug_DSCEMCR_SET_MON_PEND_Pos 1U /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Position */ -#define CoreDebug_DSCEMCR_SET_MON_PEND_Msk (1UL << CoreDebug_DSCEMCR_SET_MON_PEND_Pos) /*!< \deprecated CoreDebug DSCEMCR: SET_MON_PEND, Mask */ - -/* Debug Authentication Control Register Definitions */ -#define CoreDebug_DAUTHCTRL_UIDEN_Pos 10U /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_UIDAPEN_Pos 9U /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Position */ -#define CoreDebug_DAUTHCTRL_UIDAPEN_Msk (1UL << CoreDebug_DAUTHCTRL_UIDAPEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: UIDAPEN, Mask */ - -#define CoreDebug_DAUTHCTRL_FSDMA_Pos 8U /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Position */ -#define CoreDebug_DAUTHCTRL_FSDMA_Msk (1UL << CoreDebug_DAUTHCTRL_FSDMA_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: FSDMA, Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ -#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ - -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ - -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Position */ -#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< \deprecated CoreDebug DAUTHCTRL: INTSPIDEN Mask */ - -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Position */ -#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< \deprecated CoreDebug DAUTHCTRL: SPIDENSEL Mask */ - -/* Debug Security Control and Status Register Definitions */ -#define CoreDebug_DSCSR_CDS_Pos 16U /*!< \deprecated CoreDebug DSCSR: CDS Position */ -#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< \deprecated CoreDebug DSCSR: CDS Mask */ - -#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< \deprecated CoreDebug DSCSR: SBRSEL Position */ -#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< \deprecated CoreDebug DSCSR: SBRSEL Mask */ - -#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< \deprecated CoreDebug DSCSR: SBRSELEN Position */ -#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< \deprecated CoreDebug DSCSR: SBRSELEN Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - __OM uint32_t DSCEMCR; /*!< Offset: 0x010 ( /W) Debug Set Clear Exception and Monitor Control Register */ - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_FPD_Pos 23U /*!< DCB DHCSR: Floating-point registers Debuggable Position */ -#define DCB_DHCSR_S_FPD_Msk (0x1UL << DCB_DHCSR_S_FPD_Pos) /*!< DCB DHCSR: Floating-point registers Debuggable Mask */ - -#define DCB_DHCSR_S_SUIDE_Pos 22U /*!< DCB DHCSR: Secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_SUIDE_Msk (0x1UL << DCB_DHCSR_S_SUIDE_Pos) /*!< DCB DHCSR: Secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_NSUIDE_Pos 21U /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Position */ -#define DCB_DHCSR_S_NSUIDE_Msk (0x1UL << DCB_DHCSR_S_NSUIDE_Pos) /*!< DCB DHCSR: Non-secure unprivileged halting debug enabled Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_PMOV_Pos 6U /*!< DCB DHCSR: Halt on PMU overflow control Position */ -#define DCB_DHCSR_C_PMOV_Msk (0x1UL << DCB_DHCSR_C_PMOV_Pos) /*!< DCB DHCSR: Halt on PMU overflow control Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DSCEMCR, Debug Set Clear Exception and Monitor Control Register Definitions */ -#define DCB_DSCEMCR_CLR_MON_REQ_Pos 19U /*!< DCB DSCEMCR: Clear monitor request Position */ -#define DCB_DSCEMCR_CLR_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_REQ_Pos) /*!< DCB DSCEMCR: Clear monitor request Mask */ - -#define DCB_DSCEMCR_CLR_MON_PEND_Pos 17U /*!< DCB DSCEMCR: Clear monitor pend Position */ -#define DCB_DSCEMCR_CLR_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_CLR_MON_PEND_Pos) /*!< DCB DSCEMCR: Clear monitor pend Mask */ - -#define DCB_DSCEMCR_SET_MON_REQ_Pos 3U /*!< DCB DSCEMCR: Set monitor request Position */ -#define DCB_DSCEMCR_SET_MON_REQ_Msk (0x1UL << DCB_DSCEMCR_SET_MON_REQ_Pos) /*!< DCB DSCEMCR: Set monitor request Mask */ - -#define DCB_DSCEMCR_SET_MON_PEND_Pos 1U /*!< DCB DSCEMCR: Set monitor pend Position */ -#define DCB_DSCEMCR_SET_MON_PEND_Msk (0x1UL << DCB_DSCEMCR_SET_MON_PEND_Pos) /*!< DCB DSCEMCR: Set monitor pend Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_UIDEN_Pos 10U /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Position */ -#define DCB_DAUTHCTRL_UIDEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive Debug Enable Mask */ - -#define DCB_DAUTHCTRL_UIDAPEN_Pos 9U /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Position */ -#define DCB_DAUTHCTRL_UIDAPEN_Msk (0x1UL << DCB_DAUTHCTRL_UIDAPEN_Pos) /*!< DCB DAUTHCTRL: Unprivileged Invasive DAP Access Enable Mask */ - -#define DCB_DAUTHCTRL_FSDMA_Pos 8U /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Position */ -#define DCB_DAUTHCTRL_FSDMA_Msk (0x1UL << DCB_DAUTHCTRL_FSDMA_Pos) /*!< DCB DAUTHCTRL: Force Secure DebugMonitor Allowed Mask */ - -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SUNID_Pos 22U /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUNID_Msk (0x3UL << DIB_DAUTHSTATUS_SUNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Non-invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SUID_Pos 20U /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_SUID_Msk (0x3UL << DIB_DAUTHSTATUS_SUID_Pos ) /*!< DIB DAUTHSTATUS: Secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_NSUNID_Pos 18U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Position */ -#define DIB_DAUTHSTATUS_NSUNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Non-invasive Debug Allo Mask */ - -#define DIB_DAUTHSTATUS_NSUID_Pos 16U /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Position */ -#define DIB_DAUTHSTATUS_NSUID_Msk (0x3UL << DIB_DAUTHSTATUS_NSUID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Unprivileged Invasive Debug Allowed Mask */ - -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define MEMSYSCTL_BASE (0xE001E000UL) /*!< Memory System Control Base Address */ - #define ERRBNK_BASE (0xE001E100UL) /*!< Error Banking Base Address */ - #define PWRMODCTL_BASE (0xE001E300UL) /*!< Power Mode Control Base Address */ - #define EWIC_BASE (0xE001E400UL) /*!< External Wakeup Interrupt Controller Base Address */ - #define PRCCFGINF_BASE (0xE001E700UL) /*!< Processor Configuration Information Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define CoreDebug_BASE (0xE000EDF0UL) /*!< \deprecated Core Debug Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ - #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ - #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - - #define ICB ((ICB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ - #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ - #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ - #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ - #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ - #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ - #define MEMSYSCTL ((MemSysCtl_Type *) MEMSYSCTL_BASE ) /*!< Memory System Control configuration struct */ - #define ERRBNK ((ErrBnk_Type *) ERRBNK_BASE ) /*!< Error Banking configuration struct */ - #define PWRMODCTL ((PwrModCtl_Type *) PWRMODCTL_BASE ) /*!< Power Mode Control configuration struct */ - #define EWIC ((EWIC_Type *) EWIC_BASE ) /*!< EWIC configuration struct */ - #define PRCCFGINF ((PrcCfgInf_Type *) PRCCFGINF_BASE ) /*!< Processor Configuration Information configuration struct */ - #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< \deprecated Core Debug configuration struct */ - #define DCB ((DCB_Type *) DCB_BASE ) /*!< DCB configuration struct */ - #define DIB ((DIB_Type *) DIB_BASE ) /*!< DIB configuration struct */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ - #endif - - #if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - #define PMU_BASE (0xE0003000UL) /*!< PMU Base Address */ - #define PMU ((PMU_Type *) PMU_BASE ) /*!< PMU configuration struct */ - #endif - - #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ - #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ - #endif - - #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ - #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ - #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< \deprecated Core Debug Base Address (non-secure address space) */ - #define DCB_BASE_NS (0xE002EDF0UL) /*!< DCB Base Address (non-secure address space) */ - #define DIB_BASE_NS (0xE002EFB0UL) /*!< DIB Base Address (non-secure address space) */ - #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ - #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ - #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ - - #define ICB_NS ((ICB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ - #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ - #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ - #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ - #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< \deprecated Core Debug configuration struct (non-secure address space) */ - #define DCB_NS ((DCB_Type *) DCB_BASE_NS ) /*!< DCB configuration struct (non-secure address space) */ - #define DIB_NS ((DIB_Type *) DIB_BASE_NS ) /*!< DIB configuration struct (non-secure address space) */ - - #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ - #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ - #endif - - #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ - #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/*@} */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_register_aliases Backwards Compatibility Aliases - \brief Register alias definitions for backwards compatibility. - @{ - */ - -/*@} */ - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* Special LR values for Secure/Non-Secure call handling and exception handling */ - -/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ -#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ - -/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ -#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ -#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ -#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ -#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ -#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ -#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ -#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ - -/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ -#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ -#else -#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ -#endif - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## PMU functions and events #################################### */ - -#if defined (__PMU_PRESENT) && (__PMU_PRESENT == 1U) - -#include "pmu_armv8.h" - -/** - \brief Cortex-M85 PMU events - \note Architectural PMU events can be found in pmu_armv8.h -*/ - -#define ARMCM85_PMU_ECC_ERR 0xC000 /*!< One or more Error Correcting Code (ECC) errors detected */ -#define ARMCM85_PMU_ECC_ERR_MBIT 0xC001 /*!< One or more multi-bit ECC errors detected */ -#define ARMCM85_PMU_ECC_ERR_DCACHE 0xC010 /*!< One or more ECC errors in the data cache */ -#define ARMCM85_PMU_ECC_ERR_ICACHE 0xC011 /*!< One or more ECC errors in the instruction cache */ -#define ARMCM85_PMU_ECC_ERR_MBIT_DCACHE 0xC012 /*!< One or more multi-bit ECC errors in the data cache */ -#define ARMCM85_PMU_ECC_ERR_MBIT_ICACHE 0xC013 /*!< One or more multi-bit ECC errors in the instruction cache */ -#define ARMCM85_PMU_ECC_ERR_DTCM 0xC020 /*!< One or more ECC errors in the Data Tightly Coupled Memory (DTCM) */ -#define ARMCM85_PMU_ECC_ERR_ITCM 0xC021 /*!< One or more ECC errors in the Instruction Tightly Coupled Memory (ITCM) */ -#define ARMCM85_PMU_ECC_ERR_MBIT_DTCM 0xC022 /*!< One or more multi-bit ECC errors in the DTCM */ -#define ARMCM85_PMU_ECC_ERR_MBIT_ITCM 0xC023 /*!< One or more multi-bit ECC errors in the ITCM */ -#define ARMCM85_PMU_PF_LINEFILL 0xC100 /*!< The prefetcher starts a line-fill */ -#define ARMCM85_PMU_PF_CANCEL 0xC101 /*!< The prefetcher stops prefetching */ -#define ARMCM85_PMU_PF_DROP_LINEFILL 0xC102 /*!< A linefill triggered by a prefetcher has been dropped because of lack of buffering */ -#define ARMCM85_PMU_NWAMODE_ENTER 0xC200 /*!< No write-allocate mode entry */ -#define ARMCM85_PMU_NWAMODE 0xC201 /*!< Write-allocate store is not allocated into the data cache due to no-write-allocate mode */ -#define ARMCM85_PMU_SAHB_ACCESS 0xC300 /*!< Read or write access on the S-AHB interface to the TCM */ -#define ARMCM85_PMU_PAHB_ACCESS 0xC301 /*!< Read or write access on the P-AHB write interface */ -#define ARMCM85_PMU_AXI_WRITE_ACCESS 0xC302 /*!< Any beat access to M-AXI write interface */ -#define ARMCM85_PMU_AXI_READ_ACCESS 0xC303 /*!< Any beat access to M-AXI read interface */ -#define ARMCM85_PMU_DOSTIMEOUT_DOUBLE 0xC400 /*!< Denial of Service timeout has fired twice and caused buffers to drain to allow forward progress */ -#define ARMCM85_PMU_DOSTIMEOUT_TRIPLE 0xC401 /*!< Denial of Service timeout has fired three times and blocked the LSU to force forward progress */ - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_FPSP_Msk | FPU_MVFR0_FPDP_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - -/* ########################## MVE functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_MveFunctions MVE Functions - \brief Function that provides MVE type. - @{ - */ - -/** - \brief get MVE type - \details returns the MVE type - \returns - - \b 0: No Vector Extension (MVE) - - \b 1: Integer Vector Extension (MVE-I) - - \b 2: Floating-point Vector Extension (MVE-F) - */ -__STATIC_INLINE uint32_t SCB_GetMVEType(void) -{ - const uint32_t mvfr1 = FPU->MVFR1; - if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x2U << FPU_MVFR1_MVE_Pos)) - { - return 2U; - } - else if ((mvfr1 & FPU_MVFR1_MVE_Msk) == (0x1U << FPU_MVFR1_MVE_Pos)) - { - return 1U; - } - else - { - return 0U; - } -} - - -/*@} end of CMSIS_Core_MveFunctions */ - - -/* ########################## Cache functions #################################### */ - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) -#include "cachel1_armv7.h" -#endif - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - -/* ################### PAC Key functions ########################### */ - -#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) -#include "pac_armv81.h" -#endif - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_CM85_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_sc000.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_sc000.h deleted file mode 100644 index dbc755fff..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_sc000.h +++ /dev/null @@ -1,1030 +0,0 @@ -/**************************************************************************//** - * @file core_sc000.h - * @brief CMSIS SC000 Core Peripheral Access Layer Header File - * @version V5.0.7 - * @date 27. March 2020 - ******************************************************************************/ -/* - * Copyright (c) 2009-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC000_H_GENERIC -#define __CORE_SC000_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC000 definitions */ -#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ - __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (000U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC000_H_DEPENDANT -#define __CORE_SC000_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC000_REV - #define __SC000_REV 0x0000U - #warning "__SC000_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 0U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 2U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC000 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t _reserved0:1; /*!< bit: 0 Reserved */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[31U]; - __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[31U]; - __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[31U]; - __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[31U]; - uint32_t RESERVED4[64U]; - __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ -} NVIC_Type; - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - uint32_t RESERVED1[154U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. - Therefore they are not covered by the SC000 header file. - @{ - */ -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else -/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ -/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ -/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/* Interrupt Priorities are WORD accessible only under Armv6-M */ -/* The following MACROS handle generation of the register offset and byte masks */ -#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) -#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) -#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } - else - { - SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | - (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - SCB_AIRCR_SYSRESETREQ_Msk); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC000_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_sc300.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_sc300.h deleted file mode 100644 index d66621031..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_sc300.h +++ /dev/null @@ -1,1917 +0,0 @@ -/**************************************************************************//** - * @file core_sc300.h - * @brief CMSIS SC300 Core Peripheral Access Layer Header File - * @version V5.0.10 - * @date 04. June 2021 - ******************************************************************************/ -/* - * Copyright (c) 2009-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef __CORE_SC300_H_GENERIC -#define __CORE_SC300_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup SC3000 - @{ - */ - -#include "cmsis_version.h" - -/* CMSIS SC300 definitions */ -#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ -#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ -#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ - __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ - -#define __CORTEX_SC (300U) /*!< Cortex secure core */ - -/** __FPU_USED indicates whether an FPU is used or not. - This core does not support an FPU at all -*/ -#define __FPU_USED 0U - -#if defined ( __CC_ARM ) - #if defined __TARGET_FPU_VFP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined __ARM_FP - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __ICCARM__ ) - #if defined __ARMVFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TI_ARM__ ) - #if defined __TI_VFP_SUPPORT__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __TASKING__ ) - #if defined __FPU_VFP__ - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_SC300_H_DEPENDANT -#define __CORE_SC300_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __SC300_REV - #define __SC300_REV 0x0000U - #warning "__SC300_REV not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __VTOR_PRESENT - #define __VTOR_PRESENT 1U - #warning "__VTOR_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group SC300 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for Cortex-M processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:1; /*!< bit: 9 Reserved */ - uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ - uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit */ - uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ -#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ -#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ - uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[24U]; - __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RESERVED1[24U]; - __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[24U]; - __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[24U]; - __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[56U]; - __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED5[644U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[5U]; - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - uint32_t RESERVED1[129U]; - __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ -} SCB_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ -#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ -#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ - -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ -#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ -#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ -#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/* Auxiliary Control Register Definitions */ -#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ -#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ - -#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ -#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ - -#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ -#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[6U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ -#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED0[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Mask Register Definitions */ -#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ -#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ -#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ - -#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ -#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ -#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ - -#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ -#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ - -#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ -#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ - -#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ -#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ - -#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ -#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ - __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ - __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration ETM Data Register Definitions (FIFO0) */ -#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ -#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ - -#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ -#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ - -#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ -#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ - -#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ -#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ - -#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ -#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ - -#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ -#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ - -#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ -#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ - -/* TPI ITATBCTR2 Register Definitions */ -#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ -#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ - -#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ -#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ - -/* TPI Integration ITM Data Register Definitions (FIFO1) */ -#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ -#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ - -#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ -#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ - -#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ -#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ - -#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ -#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ - -#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ -#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ - -#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ -#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ - -#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ -#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ - -/* TPI ITATBCTR0 Register Definitions */ -#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ -#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ - -#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ -#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ -#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ - -#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ -#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ - __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ - __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ - __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ -} MPU_Type; - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ -#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ - -#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ -#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ - -#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ -#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ - -/* MPU Region Attribute and Size Register Definitions */ -#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ -#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ - -#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ -#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ - -#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ -#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ - -#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ -#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ - -#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ -#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ - -#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ -#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ - -#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ -#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ - -#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ -#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ - -#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ -#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ - -#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ -#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) - \brief Type definitions for the Core Debug Registers - @{ - */ - -/** - \brief Structure type to access the Core Debug Register (CoreDebug). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ -} CoreDebug_Type; - -/* Debug Halting Control and Status Register Definitions */ -#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ -#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ - -#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ -#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ - -#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ -#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ - -#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ -#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ - -#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ -#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ - -#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ -#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ - -#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ -#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ - -#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ -#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ - -#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ -#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ - -#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ -#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ - -#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ -#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ - -#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ -#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ - -/* Debug Core Register Selector Register Definitions */ -#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ -#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ - -#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ -#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ - -/* Debug Exception and Monitor Control Register Definitions */ -#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ -#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ - -#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ -#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ - -#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ -#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ - -#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ -#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ - -#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ -#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ - -#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ -#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ - -#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ -#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ - -#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ -#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ - -#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ -#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ - -#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ -#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ - -#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ -#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ - -#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ -#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ - -#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ -#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ - -/*@} end of group CMSIS_CoreDebug */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ -#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ -#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ -#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ -#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ -#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ -#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ -#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ -#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ - -#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ -#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ -#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ -#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ -#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ -#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ -#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ -#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ - #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ -#endif - -/*@} */ - - - -/******************************************************************************* - * Hardware Abstraction Layer - Core Function Interface contains: - - Core NVIC Functions - - Core SysTick Functions - - Core Debug Functions - - Core Register Access Functions - ******************************************************************************/ -/** - \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference -*/ - - - -/* ########################## NVIC functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_NVICFunctions NVIC Functions - \brief Functions that manage interrupts and exceptions via the NVIC. - @{ - */ - -#ifdef CMSIS_NVIC_VIRTUAL - #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE - #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" - #endif - #include CMSIS_NVIC_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping - #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping - #define NVIC_EnableIRQ __NVIC_EnableIRQ - #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ - #define NVIC_DisableIRQ __NVIC_DisableIRQ - #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ - #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ - #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ - #define NVIC_GetActive __NVIC_GetActive - #define NVIC_SetPriority __NVIC_SetPriority - #define NVIC_GetPriority __NVIC_GetPriority - #define NVIC_SystemReset __NVIC_SystemReset -#endif /* CMSIS_NVIC_VIRTUAL */ - -#ifdef CMSIS_VECTAB_VIRTUAL - #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE - #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" - #endif - #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE -#else - #define NVIC_SetVector __NVIC_SetVector - #define NVIC_GetVector __NVIC_GetVector -#endif /* (CMSIS_VECTAB_VIRTUAL) */ - -#define NVIC_USER_IRQ_OFFSET 16 - - -/* The following EXC_RETURN values are saved the LR on exception entry */ -#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ -#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ -#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ - - -/** - \brief Set Priority Grouping - \details Sets the priority grouping field using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses included - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/*@} end of CMSIS_Core_NVICFunctions */ - - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - return 0U; /* No FPU */ -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_SC300_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_starmc1.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_starmc1.h deleted file mode 100644 index d86c8d385..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/core_starmc1.h +++ /dev/null @@ -1,3592 +0,0 @@ -/**************************************************************************//** - * @file core_starmc1.h - * @brief CMSIS ArmChina STAR-MC1 Core Peripheral Access Layer Header File - * @version V1.0.2 - * @date 07. April 2022 - ******************************************************************************/ -/* - * Copyright (c) 2009-2018 Arm Limited. - * Copyright (c) 2018-2022 Arm China. - * All rights reserved. - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#elif defined ( __GNUC__ ) - #pragma GCC diagnostic ignored "-Wpedantic" /* disable pedantic warning due to unnamed structs/unions */ -#endif - -#ifndef __CORE_STAR_H_GENERIC -#define __CORE_STAR_H_GENERIC - -#include - -#ifdef __cplusplus - extern "C" { -#endif - -/** - \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions - CMSIS violates the following MISRA-C:2004 rules: - - \li Required Rule 8.5, object/function definition in header file.
- Function definitions in header files are used to allow 'inlining'. - - \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
- Unions are used for effective representation of core registers. - - \li Advisory Rule 19.7, Function-like macro defined.
- Function-like macros are used to allow more efficient code. - */ - - -/******************************************************************************* - * CMSIS definitions - ******************************************************************************/ -/** - \ingroup STAR-MC1 - @{ - */ - -#include "cmsis_version.h" - -/* Macro Define for STAR-MC1 */ -#define __STAR_MC (1U) /*!< STAR-MC Core */ - -/** __FPU_USED indicates whether an FPU is used or not. - For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. -*/ -#if defined ( __CC_ARM ) - #if defined (__TARGET_FPU_VFP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) - #if defined (__ARM_FP) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __GNUC__ ) - #if defined (__VFP_FP__) && !defined(__SOFTFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __ICCARM__ ) - #if defined (__ARMVFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - - #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) - #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) - #define __DSP_USED 1U - #else - #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" - #define __DSP_USED 0U - #endif - #else - #define __DSP_USED 0U - #endif - -#elif defined ( __TI_ARM__ ) - #if defined (__TI_VFP_SUPPORT__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __TASKING__ ) - #if defined (__FPU_VFP__) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#elif defined ( __CSMC__ ) - #if ( __CSMC__ & 0x400U) - #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) - #define __FPU_USED 1U - #else - #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" - #define __FPU_USED 0U - #endif - #else - #define __FPU_USED 0U - #endif - -#endif - -#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_STAR_H_GENERIC */ - -#ifndef __CMSIS_GENERIC - -#ifndef __CORE_STAR_H_DEPENDANT -#define __CORE_STAR_H_DEPENDANT - -#ifdef __cplusplus - extern "C" { -#endif - -/* check device defines and use defaults */ -#if defined __CHECK_DEVICE_DEFINES - #ifndef __STAR_REV - #define __STAR_REV 0x0000U - #warning "__STAR_REV not defined in device header file; using default!" - #endif - - #ifndef __FPU_PRESENT - #define __FPU_PRESENT 0U - #warning "__FPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __MPU_PRESENT - #define __MPU_PRESENT 0U - #warning "__MPU_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __SAUREGION_PRESENT - #define __SAUREGION_PRESENT 0U - #warning "__SAUREGION_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DSP_PRESENT - #define __DSP_PRESENT 0U - #warning "__DSP_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __ICACHE_PRESENT - #define __ICACHE_PRESENT 0U - #warning "__ICACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DCACHE_PRESENT - #define __DCACHE_PRESENT 0U - #warning "__DCACHE_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __DTCM_PRESENT - #define __DTCM_PRESENT 0U - #warning "__DTCM_PRESENT not defined in device header file; using default!" - #endif - - #ifndef __NVIC_PRIO_BITS - #define __NVIC_PRIO_BITS 3U - #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" - #endif - - #ifndef __Vendor_SysTickConfig - #define __Vendor_SysTickConfig 0U - #warning "__Vendor_SysTickConfig not defined in device header file; using default!" - #endif -#endif - -/* IO definitions (access restrictions to peripheral registers) */ -/** - \defgroup CMSIS_glob_defs CMSIS Global Defines - - IO Type Qualifiers are used - \li to specify the access to peripheral variables. - \li for automatic generation of peripheral register debug information. -*/ -#ifdef __cplusplus - #define __I volatile /*!< Defines 'read only' permissions */ -#else - #define __I volatile const /*!< Defines 'read only' permissions */ -#endif -#define __O volatile /*!< Defines 'write only' permissions */ -#define __IO volatile /*!< Defines 'read / write' permissions */ - -/* following defines should be used for structure members */ -#define __IM volatile const /*! Defines 'read only' structure member permissions */ -#define __OM volatile /*! Defines 'write only' structure member permissions */ -#define __IOM volatile /*! Defines 'read / write' structure member permissions */ - -/*@} end of group STAR-MC1 */ - - - -/******************************************************************************* - * Register Abstraction - Core Register contain: - - Core Register - - Core NVIC Register - - Core SCB Register - - Core SysTick Register - - Core Debug Register - - Core MPU Register - - Core SAU Register - - Core FPU Register - ******************************************************************************/ -/** - \defgroup CMSIS_core_register Defines and Type Definitions - \brief Type definitions and defines for STAR-MC1 processor based devices. -*/ - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_CORE Status and Control Registers - \brief Core Register type definitions. - @{ - */ - -/** - \brief Union type to access the Application Program Status Register (APSR). - */ -typedef union -{ - struct - { - uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} APSR_Type; - -/* APSR Register Definitions */ -#define APSR_N_Pos 31U /*!< APSR: N Position */ -#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ - -#define APSR_Z_Pos 30U /*!< APSR: Z Position */ -#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ - -#define APSR_C_Pos 29U /*!< APSR: C Position */ -#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ - -#define APSR_V_Pos 28U /*!< APSR: V Position */ -#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ - -#define APSR_Q_Pos 27U /*!< APSR: Q Position */ -#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ - -#define APSR_GE_Pos 16U /*!< APSR: GE Position */ -#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ - - -/** - \brief Union type to access the Interrupt Program Status Register (IPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} IPSR_Type; - -/* IPSR Register Definitions */ -#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ -#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ - - -/** - \brief Union type to access the Special-Purpose Program Status Registers (xPSR). - */ -typedef union -{ - struct - { - uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ - uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ - uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ - uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ - uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ - uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ - uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ - uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ - uint32_t C:1; /*!< bit: 29 Carry condition code flag */ - uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ - uint32_t N:1; /*!< bit: 31 Negative condition code flag */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} xPSR_Type; - -/* xPSR Register Definitions */ -#define xPSR_N_Pos 31U /*!< xPSR: N Position */ -#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ - -#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ -#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ - -#define xPSR_C_Pos 29U /*!< xPSR: C Position */ -#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ - -#define xPSR_V_Pos 28U /*!< xPSR: V Position */ -#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ - -#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ -#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ - -#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ -#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ - -#define xPSR_T_Pos 24U /*!< xPSR: T Position */ -#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ - -#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ -#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ - -#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ -#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ - - -/** - \brief Union type to access the Control Registers (CONTROL). - */ -typedef union -{ - struct - { - uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ - uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ - uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ - uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ - uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ - } b; /*!< Structure used for bit access */ - uint32_t w; /*!< Type used for word access */ -} CONTROL_Type; - -/* CONTROL Register Definitions */ -#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ -#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ - -#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ -#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ - -#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ -#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ - -#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ -#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ - -/*@} end of group CMSIS_CORE */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) - \brief Type definitions for the NVIC Registers - @{ - */ - -/** - \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). - */ -typedef struct -{ - __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ - uint32_t RESERVED0[16U]; - __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ - uint32_t RSERVED1[16U]; - __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ - uint32_t RESERVED2[16U]; - __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ - uint32_t RESERVED3[16U]; - __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ - uint32_t RESERVED4[16U]; - __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ - uint32_t RESERVED5[16U]; - __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ - uint32_t RESERVED6[580U]; - __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ -} NVIC_Type; - -/* Software Triggered Interrupt Register Definitions */ -#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ -#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_NVIC */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCB System Control Block (SCB) - \brief Type definitions for the System Control Block Registers - @{ - */ - -/** - \brief Structure type to access the System Control Block (SCB). - */ -typedef struct -{ - __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ - __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ - __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ - __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ - __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ - __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ - __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ - __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ - __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ - __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ - __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ - __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ - __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ - __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ - __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ - __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ - __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ - __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ - __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ - uint32_t RESERVED0[1U]; - __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ - __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ - __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ - __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ - __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ - __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ - uint32_t RESERVED_ADD1[21U]; - __IOM uint32_t SFSR; /*!< Offset: 0x0E4 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x0E8 (R/W) Secure Fault Address Register */ - uint32_t RESERVED3[69U]; - __OM uint32_t STIR; /*!< Offset: F00-D00=0x200 ( /W) Software Triggered Interrupt Register */ - uint32_t RESERVED4[15U]; - __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ - uint32_t RESERVED5[1U]; - __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ - uint32_t RESERVED6[1U]; - __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ - __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ - __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ - __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ - __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ - __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ - __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ - __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ -} SCB_Type; - -typedef struct -{ - __IOM uint32_t CACR; /*!< Offset: 0x0 (R/W) L1 Cache Control Register */ - __IOM uint32_t ITCMCR; /*!< Offset: 0x10 (R/W) Instruction Tightly-Coupled Memory Control Register */ - __IOM uint32_t DTCMCR; /*!< Offset: 0x14 (R/W) Data Tightly-Coupled Memory Control Registers */ -}EMSS_Type; - -/* SCB CPUID Register Definitions */ -#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ -#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ - -#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ -#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ - -#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ -#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ - -#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ -#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ - -#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ -#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ - -/* SCB Interrupt Control State Register Definitions */ -#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ -#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ - -#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ -#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ - -#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ -#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ - -#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ -#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ - -#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ -#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ - -#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ -#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ - -#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ -#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ - -#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ -#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ - -#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ -#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ - -#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ -#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ - -#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ -#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ - -#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ -#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ - -#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ -#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ - -/* SCB Vector Table Offset Register Definitions */ -#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ -#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ - -/* SCB Application Interrupt and Reset Control Register Definitions */ -#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ -#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ - -#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ -#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ - -#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ -#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ - -#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ -#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ - -#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ -#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ - -#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ -#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ - -#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ -#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ - -#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ -#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ - -#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ -#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ - -/* SCB System Control Register Definitions */ -#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ -#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ - -#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ -#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ - -#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ -#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ - -#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ -#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ - -/* SCB Configuration Control Register Definitions */ -#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ -#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ - -#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ -#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ - -#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ -#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ - -#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ -#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ - -#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ -#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ - -#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ -#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ - -#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ -#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ - -#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ -#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ - -/* SCB System Handler Control and State Register Definitions */ -#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ -#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ -#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ - -#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ -#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ - -#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ -#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ - -#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ -#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ - -#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ -#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ - -#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ -#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ - -#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ -#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ - -#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ -#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ - -#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ -#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ - -#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ -#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ - -#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ -#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ - -#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ -#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ - -#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ -#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ - -#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ -#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ - -#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ -#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ - -#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ -#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ - -#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ -#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ - -#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ -#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ - -#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ -#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ - -/* SCB Configurable Fault Status Register Definitions */ -#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ -#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ - -#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ -#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ - -#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ -#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ - -/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_MMARVALID_Pos (SCB_CFSR_MEMFAULTSR_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ -#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ - -#define SCB_CFSR_MLSPERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ -#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ - -#define SCB_CFSR_MSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ -#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ - -#define SCB_CFSR_MUNSTKERR_Pos (SCB_CFSR_MEMFAULTSR_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ -#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ - -#define SCB_CFSR_DACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ -#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ - -#define SCB_CFSR_IACCVIOL_Pos (SCB_CFSR_MEMFAULTSR_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ -#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ - -/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ -#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ - -#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ -#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ - -#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ -#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ - -#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ -#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ - -#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ -#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ - -#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ -#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ - -#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ -#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ - -/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ -#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ -#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ - -#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ -#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ - -#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ -#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ - -#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ -#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ - -#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ -#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ - -#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ -#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ - -#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ -#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ - -/* SCB Hard Fault Status Register Definitions */ -#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ -#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ - -#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ -#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ - -#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ -#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ - -/* SCB Debug Fault Status Register Definitions */ -#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ -#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ - -#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ -#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ - -#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ -#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ - -#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ -#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ - -#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ -#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ - -/* SCB Non-Secure Access Control Register Definitions */ -#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ -#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ - -#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ -#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ - -#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ -#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ - -/* SCB Cache Level ID Register Definitions */ -#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ -#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ - -#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ -#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ - -#define SCB_CLIDR_IC_Pos 0U /*!< SCB CLIDR: IC Position */ -#define SCB_CLIDR_IC_Msk (1UL << SCB_CLIDR_IC_Pos) /*!< SCB CLIDR: IC Mask */ - -#define SCB_CLIDR_DC_Pos 1U /*!< SCB CLIDR: DC Position */ -#define SCB_CLIDR_DC_Msk (1UL << SCB_CLIDR_DC_Pos) /*!< SCB CLIDR: DC Mask */ - - - -/* SCB Cache Type Register Definitions */ -#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ -#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ - -#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ -#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ - -#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ -#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ - -#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ -#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ - -#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ -#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ - -/* SCB Cache Size ID Register Definitions */ -#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ -#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ - -#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ -#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ - -#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ -#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ - -#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ -#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ - -#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ -#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ - -#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ -#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ - -#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ -#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ - -/* SCB Cache Size Selection Register Definitions */ -#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ -#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ - -#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ -#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ - -/* SCB Software Triggered Interrupt Register Definitions */ -#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ -#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ - -/* SCB D-Cache line Invalidate by Set-way Register Definitions */ -#define SCB_DCISW_LEVEL_Pos 1U /*!< SCB DCISW: Level Position */ -#define SCB_DCISW_LEVEL_Msk (7UL << SCB_DCISW_LEVEL_Pos) /*!< SCB DCISW: Level Mask */ - -#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ -#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ - -#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ -#define SCB_DCISW_SET_Msk (0xFFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ - -/* SCB D-Cache Clean line by Set-way Register Definitions */ -#define SCB_DCCSW_LEVEL_Pos 1U /*!< SCB DCCSW: Level Position */ -#define SCB_DCCSW_LEVEL_Msk (7UL << SCB_DCCSW_LEVEL_Pos) /*!< SCB DCCSW: Level Mask */ - -#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ -#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ - -#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ -#define SCB_DCCSW_SET_Msk (0xFFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ - -/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ -#define SCB_DCCISW_LEVEL_Pos 1U /*!< SCB DCCISW: Level Position */ -#define SCB_DCCISW_LEVEL_Msk (7UL << SCB_DCCISW_LEVEL_Pos) /*!< SCB DCCISW: Level Mask */ - -#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ -#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ - -#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ -#define SCB_DCCISW_SET_Msk (0xFFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ - -/* ArmChina: Implementation Defined */ -/* Instruction Tightly-Coupled Memory Control Register Definitions */ -#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ -#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ - -#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ -#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ - -/* Data Tightly-Coupled Memory Control Register Definitions */ -#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ -#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ - -#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ -#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ - -/* L1 Cache Control Register Definitions */ -#define SCB_CACR_DCCLEAN_Pos 16U /*!< SCB CACR: DCCLEAN Position */ -#define SCB_CACR_DCCLEAN_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCCLEAN Mask */ - -#define SCB_CACR_ICACTIVE_Pos 13U /*!< SCB CACR: ICACTIVE Position */ -#define SCB_CACR_ICACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: ICACTIVE Mask */ - -#define SCB_CACR_DCACTIVE_Pos 12U /*!< SCB CACR: DCACTIVE Position */ -#define SCB_CACR_DCACTIVE_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: DCACTIVE Mask */ - -#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ -#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ - -/*@} end of group CMSIS_SCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) - \brief Type definitions for the System Control and ID Register not in the SCB - @{ - */ - -/** - \brief Structure type to access the System Control and ID Register not in the SCB. - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ - __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ - __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ -} SCnSCB_Type; - -/* Interrupt Controller Type Register Definitions */ -#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ -#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ - -/*@} end of group CMSIS_SCnotSCB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SysTick System Tick Timer (SysTick) - \brief Type definitions for the System Timer Registers. - @{ - */ - -/** - \brief Structure type to access the System Timer (SysTick). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ - __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ - __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ - __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ -} SysTick_Type; - -/* SysTick Control / Status Register Definitions */ -#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ -#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ - -#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ -#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ - -#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ -#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ - -#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ -#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ - -/* SysTick Reload Register Definitions */ -#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ -#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ - -/* SysTick Current Register Definitions */ -#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ -#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ - -/* SysTick Calibration Register Definitions */ -#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ -#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ - -#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ -#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ - -#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ -#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ - -/*@} end of group CMSIS_SysTick */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) - \brief Type definitions for the Instrumentation Trace Macrocell (ITM) - @{ - */ - -/** - \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). - */ -typedef struct -{ - __OM union - { - __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ - __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ - __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ - } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ - uint32_t RESERVED0[864U]; - __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ - uint32_t RESERVED1[15U]; - __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ - uint32_t RESERVED2[15U]; - __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ - uint32_t RESERVED3[32U]; - uint32_t RESERVED4[43U]; - __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ - uint32_t RESERVED5[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ - uint32_t RESERVED6[4U]; - __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ - __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ - __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ - __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ - __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ - __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ - __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ - __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ - __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ - __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ - __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ - __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ -} ITM_Type; - -/* ITM Stimulus Port Register Definitions */ -#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ -#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ - -#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ -#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ - -/* ITM Trace Privilege Register Definitions */ -#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ -#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ - -/* ITM Trace Control Register Definitions */ -#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ -#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ - -#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ -#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ - -#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ -#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ - -#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ -#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ - -#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ -#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ - -#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ -#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ - -#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ -#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ - -#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ -#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ - -#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ -#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ - -#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ -#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ - -/* ITM Lock Status Register Definitions */ -#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ -#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ - -#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ -#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ - -#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ -#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ - -/*@}*/ /* end of group CMSIS_ITM */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) - \brief Type definitions for the Data Watchpoint and Trace (DWT) - @{ - */ - -/** - \brief Structure type to access the Data Watchpoint and Trace Register (DWT). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ - __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ - __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ - __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ - __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ - __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ - __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ - __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ - __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ - uint32_t RESERVED1[1U]; - __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ - uint32_t RESERVED2[1U]; - __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ - uint32_t RESERVED3[1U]; - __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ - uint32_t RESERVED4[1U]; - __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ - uint32_t RESERVED5[1U]; - __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ - uint32_t RESERVED6[1U]; - __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ - uint32_t RESERVED7[1U]; - __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ - uint32_t RESERVED8[1U]; - __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ - uint32_t RESERVED9[1U]; - __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ - uint32_t RESERVED10[1U]; - __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ - uint32_t RESERVED11[1U]; - __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ - uint32_t RESERVED12[1U]; - __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ - uint32_t RESERVED13[1U]; - __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ - uint32_t RESERVED14[1U]; - __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ - uint32_t RESERVED15[1U]; - __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ - uint32_t RESERVED16[1U]; - __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ - uint32_t RESERVED17[1U]; - __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ - uint32_t RESERVED18[1U]; - __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ - uint32_t RESERVED19[1U]; - __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ - uint32_t RESERVED20[1U]; - __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ - uint32_t RESERVED21[1U]; - __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ - uint32_t RESERVED22[1U]; - __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ - uint32_t RESERVED23[1U]; - __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ - uint32_t RESERVED24[1U]; - __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ - uint32_t RESERVED25[1U]; - __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ - uint32_t RESERVED26[1U]; - __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ - uint32_t RESERVED27[1U]; - __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ - uint32_t RESERVED28[1U]; - __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ - uint32_t RESERVED29[1U]; - __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ - uint32_t RESERVED30[1U]; - __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ - uint32_t RESERVED31[1U]; - __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ - uint32_t RESERVED32[934U]; - __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ - uint32_t RESERVED33[1U]; - __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ -} DWT_Type; - -/* DWT Control Register Definitions */ -#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ -#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ - -#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ -#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ - -#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ -#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ - -#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ -#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ - -#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ -#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ - -#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ -#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ - -#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ -#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ - -#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ -#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ - -#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ -#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ - -#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ -#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ - -#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ -#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ - -#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ -#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ - -#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ -#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ - -#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ -#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ - -#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ -#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ - -#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ -#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ - -#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ -#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ - -#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ -#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ - -#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ -#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ - -/* DWT CPI Count Register Definitions */ -#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ -#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ - -/* DWT Exception Overhead Count Register Definitions */ -#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ -#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ - -/* DWT Sleep Count Register Definitions */ -#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ -#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ - -/* DWT LSU Count Register Definitions */ -#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ -#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ - -/* DWT Folded-instruction Count Register Definitions */ -#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ -#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ - -/* DWT Comparator Function Register Definitions */ -#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ -#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ - -#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ -#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ - -#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ -#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ - -#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ -#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ - -#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ -#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ - -/*@}*/ /* end of group CMSIS_DWT */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_TPI Trace Port Interface (TPI) - \brief Type definitions for the Trace Port Interface (TPI) - @{ - */ - -/** - \brief Structure type to access the Trace Port Interface Register (TPI). - */ -typedef struct -{ - __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ - __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ - uint32_t RESERVED0[2U]; - __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ - uint32_t RESERVED1[55U]; - __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ - uint32_t RESERVED2[131U]; - __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ - __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ - __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ - uint32_t RESERVED3[759U]; - __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ - __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ - __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ - uint32_t RESERVED4[1U]; - __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ - __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ - __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ - uint32_t RESERVED5[39U]; - __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ - __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ - uint32_t RESERVED7[8U]; - __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ - __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ -} TPI_Type; - -/* TPI Asynchronous Clock Prescaler Register Definitions */ -#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ -#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ - -/* TPI Selected Pin Protocol Register Definitions */ -#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ -#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ - -/* TPI Formatter and Flush Status Register Definitions */ -#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ -#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ - -#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ -#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ - -#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ -#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ - -#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ -#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ - -/* TPI Formatter and Flush Control Register Definitions */ -#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ -#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ - -#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ -#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ - -#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ -#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ - -/* TPI TRIGGER Register Definitions */ -#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ -#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ - -/* TPI Integration Test FIFO Test Data 0 Register Definitions */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ -#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ -#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ -#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ - -#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ -#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ - -/* TPI Integration Test ATB Control Register 2 Register Definitions */ -#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ -#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ - -#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ -#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ - -#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ -#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ - -#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ -#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ - -/* TPI Integration Test FIFO Test Data 1 Register Definitions */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ -#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ - -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ -#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ - -#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ -#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ -#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ -#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ - -#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ -#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ - -/* TPI Integration Test ATB Control Register 0 Definitions */ -#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ -#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ - -#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ -#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ - -#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ -#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ - -#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ -#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ - -/* TPI Integration Mode Control Register Definitions */ -#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ -#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ - -/* TPI DEVID Register Definitions */ -#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ -#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ - -#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ -#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ - -#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ -#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ - -#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ -#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ - -#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ -#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ - -/* TPI DEVTYPE Register Definitions */ -#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ -#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ - -#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ -#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ - -/*@}*/ /* end of group CMSIS_TPI */ - - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_MPU Memory Protection Unit (MPU) - \brief Type definitions for the Memory Protection Unit (MPU) - @{ - */ - -/** - \brief Structure type to access the Memory Protection Unit (MPU). - */ -typedef struct -{ - __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ - __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ - __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ - __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ - __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ - __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ - __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ - __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ - uint32_t RESERVED0[1]; - union { - __IOM uint32_t MAIR[2]; - struct { - __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ - __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ - }; - }; -} MPU_Type; - -#define MPU_TYPE_RALIASES 4U - -/* MPU Type Register Definitions */ -#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ -#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ - -#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ -#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ - -#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ -#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ - -/* MPU Control Register Definitions */ -#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ -#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ - -#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ -#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ - -#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ -#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ - -/* MPU Region Number Register Definitions */ -#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ -#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ - -/* MPU Region Base Address Register Definitions */ -#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ -#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ - -#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ -#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ - -#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ -#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ - -#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ -#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ - -/* MPU Region Limit Address Register Definitions */ -#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ -#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ - -#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ -#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ - -#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ -#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ - -/* MPU Memory Attribute Indirection Register 0 Definitions */ -#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ -#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ - -#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ -#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ - -#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ -#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ - -#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ -#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ - -/* MPU Memory Attribute Indirection Register 1 Definitions */ -#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ -#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ - -#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ -#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ - -#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ -#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ - -#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ -#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ - -/*@} end of group CMSIS_MPU */ -#endif - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_SAU Security Attribution Unit (SAU) - \brief Type definitions for the Security Attribution Unit (SAU) - @{ - */ - -/** - \brief Structure type to access the Security Attribution Unit (SAU). - */ -typedef struct -{ - __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ - __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) - __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ - __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ - __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ -#else - uint32_t RESERVED0[3]; -#endif - __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ - __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ -} SAU_Type; - -/* SAU Control Register Definitions */ -#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ -#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ - -#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ -#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ - -/* SAU Type Register Definitions */ -#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ -#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ - -#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) -/* SAU Region Number Register Definitions */ -#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ -#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ - -/* SAU Region Base Address Register Definitions */ -#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ -#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ - -/* SAU Region Limit Address Register Definitions */ -#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ -#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ - -#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ -#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ - -#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ -#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ - -#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ - -/* Secure Fault Status Register Definitions */ -#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ -#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ - -#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ -#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ - -#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ -#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ - -#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ -#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ - -#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ -#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ - -#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ -#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ - -#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ -#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ - -#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ -#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ - -/*@} end of group CMSIS_SAU */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_FPU Floating Point Unit (FPU) - \brief Type definitions for the Floating Point Unit (FPU) - @{ - */ - -/** - \brief Structure type to access the Floating Point Unit (FPU). - */ -typedef struct -{ - uint32_t RESERVED0[1U]; - __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ - __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ - __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ - __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and VFP Feature Register 0 */ - __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and VFP Feature Register 1 */ - __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and VFP Feature Register 2 */ -} FPU_Type; - -/* Floating-Point Context Control Register Definitions */ -#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ -#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ - -#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ -#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ - -#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ -#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ - -#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ -#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ - -#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ -#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ - -#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ -#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ - -#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ -#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ - -#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ -#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ - -#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ -#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ - -#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ -#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ - -#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ -#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ - -#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ -#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ - -#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ -#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ - -#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ -#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ - -#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ -#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ - -#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ -#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ - -#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ -#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ - -/* Floating-Point Context Address Register Definitions */ -#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ -#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ - -/* Floating-Point Default Status Control Register Definitions */ -#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ -#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ - -#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ -#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ - -#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ -#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ - -#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ -#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ - -/* Media and VFP Feature Register 0 Definitions */ -#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ -#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ - -#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ -#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ - -#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ -#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ - -#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ -#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ - -#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ -#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ - -#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ -#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ - -#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ -#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ - -#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ -#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ - -/* Media and VFP Feature Register 1 Definitions */ -#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ -#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ - -#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ -#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ - -#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ -#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ - -#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ -#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ - -/* Media and VFP Feature Register 2 Definitions */ -#define FPU_MVFR2_FPMisc_Pos 4U /*!< MVFR2: FPMisc bits Position */ -#define FPU_MVFR2_FPMisc_Msk (0xFUL << FPU_MVFR2_FPMisc_Pos) /*!< MVFR2: FPMisc bits Mask */ - -/*@} end of group CMSIS_FPU */ - - - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DCB Debug Control Block - \brief Type definitions for the Debug Control Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Control Block Registers (DCB). - */ -typedef struct -{ - __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ - __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ - __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ - __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ - uint32_t RESERVED0[1U]; - __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ - __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ -} DCB_Type; - -/* DHCSR, Debug Halting Control and Status Register Definitions */ -#define DCB_DHCSR_DBGKEY_Pos 16U /*!< DCB DHCSR: Debug key Position */ -#define DCB_DHCSR_DBGKEY_Msk (0xFFFFUL << DCB_DHCSR_DBGKEY_Pos) /*!< DCB DHCSR: Debug key Mask */ - -#define DCB_DHCSR_S_RESTART_ST_Pos 26U /*!< DCB DHCSR: Restart sticky status Position */ -#define DCB_DHCSR_S_RESTART_ST_Msk (0x1UL << DCB_DHCSR_S_RESTART_ST_Pos) /*!< DCB DHCSR: Restart sticky status Mask */ - -#define DCB_DHCSR_S_RESET_ST_Pos 25U /*!< DCB DHCSR: Reset sticky status Position */ -#define DCB_DHCSR_S_RESET_ST_Msk (0x1UL << DCB_DHCSR_S_RESET_ST_Pos) /*!< DCB DHCSR: Reset sticky status Mask */ - -#define DCB_DHCSR_S_RETIRE_ST_Pos 24U /*!< DCB DHCSR: Retire sticky status Position */ -#define DCB_DHCSR_S_RETIRE_ST_Msk (0x1UL << DCB_DHCSR_S_RETIRE_ST_Pos) /*!< DCB DHCSR: Retire sticky status Mask */ - -#define DCB_DHCSR_S_SDE_Pos 20U /*!< DCB DHCSR: Secure debug enabled Position */ -#define DCB_DHCSR_S_SDE_Msk (0x1UL << DCB_DHCSR_S_SDE_Pos) /*!< DCB DHCSR: Secure debug enabled Mask */ - -#define DCB_DHCSR_S_LOCKUP_Pos 19U /*!< DCB DHCSR: Lockup status Position */ -#define DCB_DHCSR_S_LOCKUP_Msk (0x1UL << DCB_DHCSR_S_LOCKUP_Pos) /*!< DCB DHCSR: Lockup status Mask */ - -#define DCB_DHCSR_S_SLEEP_Pos 18U /*!< DCB DHCSR: Sleeping status Position */ -#define DCB_DHCSR_S_SLEEP_Msk (0x1UL << DCB_DHCSR_S_SLEEP_Pos) /*!< DCB DHCSR: Sleeping status Mask */ - -#define DCB_DHCSR_S_HALT_Pos 17U /*!< DCB DHCSR: Halted status Position */ -#define DCB_DHCSR_S_HALT_Msk (0x1UL << DCB_DHCSR_S_HALT_Pos) /*!< DCB DHCSR: Halted status Mask */ - -#define DCB_DHCSR_S_REGRDY_Pos 16U /*!< DCB DHCSR: Register ready status Position */ -#define DCB_DHCSR_S_REGRDY_Msk (0x1UL << DCB_DHCSR_S_REGRDY_Pos) /*!< DCB DHCSR: Register ready status Mask */ - -#define DCB_DHCSR_C_SNAPSTALL_Pos 5U /*!< DCB DHCSR: Snap stall control Position */ -#define DCB_DHCSR_C_SNAPSTALL_Msk (0x1UL << DCB_DHCSR_C_SNAPSTALL_Pos) /*!< DCB DHCSR: Snap stall control Mask */ - -#define DCB_DHCSR_C_MASKINTS_Pos 3U /*!< DCB DHCSR: Mask interrupts control Position */ -#define DCB_DHCSR_C_MASKINTS_Msk (0x1UL << DCB_DHCSR_C_MASKINTS_Pos) /*!< DCB DHCSR: Mask interrupts control Mask */ - -#define DCB_DHCSR_C_STEP_Pos 2U /*!< DCB DHCSR: Step control Position */ -#define DCB_DHCSR_C_STEP_Msk (0x1UL << DCB_DHCSR_C_STEP_Pos) /*!< DCB DHCSR: Step control Mask */ - -#define DCB_DHCSR_C_HALT_Pos 1U /*!< DCB DHCSR: Halt control Position */ -#define DCB_DHCSR_C_HALT_Msk (0x1UL << DCB_DHCSR_C_HALT_Pos) /*!< DCB DHCSR: Halt control Mask */ - -#define DCB_DHCSR_C_DEBUGEN_Pos 0U /*!< DCB DHCSR: Debug enable control Position */ -#define DCB_DHCSR_C_DEBUGEN_Msk (0x1UL /*<< DCB_DHCSR_C_DEBUGEN_Pos*/) /*!< DCB DHCSR: Debug enable control Mask */ - -/* DCRSR, Debug Core Register Select Register Definitions */ -#define DCB_DCRSR_REGWnR_Pos 16U /*!< DCB DCRSR: Register write/not-read Position */ -#define DCB_DCRSR_REGWnR_Msk (0x1UL << DCB_DCRSR_REGWnR_Pos) /*!< DCB DCRSR: Register write/not-read Mask */ - -#define DCB_DCRSR_REGSEL_Pos 0U /*!< DCB DCRSR: Register selector Position */ -#define DCB_DCRSR_REGSEL_Msk (0x7FUL /*<< DCB_DCRSR_REGSEL_Pos*/) /*!< DCB DCRSR: Register selector Mask */ - -/* DCRDR, Debug Core Register Data Register Definitions */ -#define DCB_DCRDR_DBGTMP_Pos 0U /*!< DCB DCRDR: Data temporary buffer Position */ -#define DCB_DCRDR_DBGTMP_Msk (0xFFFFFFFFUL /*<< DCB_DCRDR_DBGTMP_Pos*/) /*!< DCB DCRDR: Data temporary buffer Mask */ - -/* DEMCR, Debug Exception and Monitor Control Register Definitions */ -#define DCB_DEMCR_TRCENA_Pos 24U /*!< DCB DEMCR: Trace enable Position */ -#define DCB_DEMCR_TRCENA_Msk (0x1UL << DCB_DEMCR_TRCENA_Pos) /*!< DCB DEMCR: Trace enable Mask */ - -#define DCB_DEMCR_MONPRKEY_Pos 23U /*!< DCB DEMCR: Monitor pend req key Position */ -#define DCB_DEMCR_MONPRKEY_Msk (0x1UL << DCB_DEMCR_MONPRKEY_Pos) /*!< DCB DEMCR: Monitor pend req key Mask */ - -#define DCB_DEMCR_UMON_EN_Pos 21U /*!< DCB DEMCR: Unprivileged monitor enable Position */ -#define DCB_DEMCR_UMON_EN_Msk (0x1UL << DCB_DEMCR_UMON_EN_Pos) /*!< DCB DEMCR: Unprivileged monitor enable Mask */ - -#define DCB_DEMCR_SDME_Pos 20U /*!< DCB DEMCR: Secure DebugMonitor enable Position */ -#define DCB_DEMCR_SDME_Msk (0x1UL << DCB_DEMCR_SDME_Pos) /*!< DCB DEMCR: Secure DebugMonitor enable Mask */ - -#define DCB_DEMCR_MON_REQ_Pos 19U /*!< DCB DEMCR: Monitor request Position */ -#define DCB_DEMCR_MON_REQ_Msk (0x1UL << DCB_DEMCR_MON_REQ_Pos) /*!< DCB DEMCR: Monitor request Mask */ - -#define DCB_DEMCR_MON_STEP_Pos 18U /*!< DCB DEMCR: Monitor step Position */ -#define DCB_DEMCR_MON_STEP_Msk (0x1UL << DCB_DEMCR_MON_STEP_Pos) /*!< DCB DEMCR: Monitor step Mask */ - -#define DCB_DEMCR_MON_PEND_Pos 17U /*!< DCB DEMCR: Monitor pend Position */ -#define DCB_DEMCR_MON_PEND_Msk (0x1UL << DCB_DEMCR_MON_PEND_Pos) /*!< DCB DEMCR: Monitor pend Mask */ - -#define DCB_DEMCR_MON_EN_Pos 16U /*!< DCB DEMCR: Monitor enable Position */ -#define DCB_DEMCR_MON_EN_Msk (0x1UL << DCB_DEMCR_MON_EN_Pos) /*!< DCB DEMCR: Monitor enable Mask */ - -#define DCB_DEMCR_VC_SFERR_Pos 11U /*!< DCB DEMCR: Vector Catch SecureFault Position */ -#define DCB_DEMCR_VC_SFERR_Msk (0x1UL << DCB_DEMCR_VC_SFERR_Pos) /*!< DCB DEMCR: Vector Catch SecureFault Mask */ - -#define DCB_DEMCR_VC_HARDERR_Pos 10U /*!< DCB DEMCR: Vector Catch HardFault errors Position */ -#define DCB_DEMCR_VC_HARDERR_Msk (0x1UL << DCB_DEMCR_VC_HARDERR_Pos) /*!< DCB DEMCR: Vector Catch HardFault errors Mask */ - -#define DCB_DEMCR_VC_INTERR_Pos 9U /*!< DCB DEMCR: Vector Catch interrupt errors Position */ -#define DCB_DEMCR_VC_INTERR_Msk (0x1UL << DCB_DEMCR_VC_INTERR_Pos) /*!< DCB DEMCR: Vector Catch interrupt errors Mask */ - -#define DCB_DEMCR_VC_BUSERR_Pos 8U /*!< DCB DEMCR: Vector Catch BusFault errors Position */ -#define DCB_DEMCR_VC_BUSERR_Msk (0x1UL << DCB_DEMCR_VC_BUSERR_Pos) /*!< DCB DEMCR: Vector Catch BusFault errors Mask */ - -#define DCB_DEMCR_VC_STATERR_Pos 7U /*!< DCB DEMCR: Vector Catch state errors Position */ -#define DCB_DEMCR_VC_STATERR_Msk (0x1UL << DCB_DEMCR_VC_STATERR_Pos) /*!< DCB DEMCR: Vector Catch state errors Mask */ - -#define DCB_DEMCR_VC_CHKERR_Pos 6U /*!< DCB DEMCR: Vector Catch check errors Position */ -#define DCB_DEMCR_VC_CHKERR_Msk (0x1UL << DCB_DEMCR_VC_CHKERR_Pos) /*!< DCB DEMCR: Vector Catch check errors Mask */ - -#define DCB_DEMCR_VC_NOCPERR_Pos 5U /*!< DCB DEMCR: Vector Catch NOCP errors Position */ -#define DCB_DEMCR_VC_NOCPERR_Msk (0x1UL << DCB_DEMCR_VC_NOCPERR_Pos) /*!< DCB DEMCR: Vector Catch NOCP errors Mask */ - -#define DCB_DEMCR_VC_MMERR_Pos 4U /*!< DCB DEMCR: Vector Catch MemManage errors Position */ -#define DCB_DEMCR_VC_MMERR_Msk (0x1UL << DCB_DEMCR_VC_MMERR_Pos) /*!< DCB DEMCR: Vector Catch MemManage errors Mask */ - -#define DCB_DEMCR_VC_CORERESET_Pos 0U /*!< DCB DEMCR: Vector Catch Core reset Position */ -#define DCB_DEMCR_VC_CORERESET_Msk (0x1UL /*<< DCB_DEMCR_VC_CORERESET_Pos*/) /*!< DCB DEMCR: Vector Catch Core reset Mask */ - -/* DAUTHCTRL, Debug Authentication Control Register Definitions */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPNIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPNIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure non-invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPNIDENSEL_Msk (0x1UL << DCB_DAUTHCTRL_SPNIDENSEL_Pos) /*!< DCB DAUTHCTRL: Secure non-invasive debug enable select Mask */ - -#define DCB_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Position */ -#define DCB_DAUTHCTRL_INTSPIDEN_Msk (0x1UL << DCB_DAUTHCTRL_INTSPIDEN_Pos) /*!< DCB DAUTHCTRL: Internal Secure invasive debug enable Mask */ - -#define DCB_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< DCB DAUTHCTRL: Secure invasive debug enable select Position */ -#define DCB_DAUTHCTRL_SPIDENSEL_Msk (0x1UL /*<< DCB_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< DCB DAUTHCTRL: Secure invasive debug enable select Mask */ - -/* DSCSR, Debug Security Control and Status Register Definitions */ -#define DCB_DSCSR_CDSKEY_Pos 17U /*!< DCB DSCSR: CDS write-enable key Position */ -#define DCB_DSCSR_CDSKEY_Msk (0x1UL << DCB_DSCSR_CDSKEY_Pos) /*!< DCB DSCSR: CDS write-enable key Mask */ - -#define DCB_DSCSR_CDS_Pos 16U /*!< DCB DSCSR: Current domain Secure Position */ -#define DCB_DSCSR_CDS_Msk (0x1UL << DCB_DSCSR_CDS_Pos) /*!< DCB DSCSR: Current domain Secure Mask */ - -#define DCB_DSCSR_SBRSEL_Pos 1U /*!< DCB DSCSR: Secure banked register select Position */ -#define DCB_DSCSR_SBRSEL_Msk (0x1UL << DCB_DSCSR_SBRSEL_Pos) /*!< DCB DSCSR: Secure banked register select Mask */ - -#define DCB_DSCSR_SBRSELEN_Pos 0U /*!< DCB DSCSR: Secure banked register select enable Position */ -#define DCB_DSCSR_SBRSELEN_Msk (0x1UL /*<< DCB_DSCSR_SBRSELEN_Pos*/) /*!< DCB DSCSR: Secure banked register select enable Mask */ - -/*@} end of group CMSIS_DCB */ - - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_DIB Debug Identification Block - \brief Type definitions for the Debug Identification Block Registers - @{ - */ - -/** - \brief Structure type to access the Debug Identification Block Registers (DIB). - */ -typedef struct -{ - __OM uint32_t DLAR; /*!< Offset: 0x000 ( /W) SCS Software Lock Access Register */ - __IM uint32_t DLSR; /*!< Offset: 0x004 (R/ ) SCS Software Lock Status Register */ - __IM uint32_t DAUTHSTATUS; /*!< Offset: 0x008 (R/ ) Debug Authentication Status Register */ - __IM uint32_t DDEVARCH; /*!< Offset: 0x00C (R/ ) SCS Device Architecture Register */ - __IM uint32_t DDEVTYPE; /*!< Offset: 0x010 (R/ ) SCS Device Type Register */ -} DIB_Type; - -/* DLAR, SCS Software Lock Access Register Definitions */ -#define DIB_DLAR_KEY_Pos 0U /*!< DIB DLAR: KEY Position */ -#define DIB_DLAR_KEY_Msk (0xFFFFFFFFUL /*<< DIB_DLAR_KEY_Pos */) /*!< DIB DLAR: KEY Mask */ - -/* DLSR, SCS Software Lock Status Register Definitions */ -#define DIB_DLSR_nTT_Pos 2U /*!< DIB DLSR: Not thirty-two bit Position */ -#define DIB_DLSR_nTT_Msk (0x1UL << DIB_DLSR_nTT_Pos ) /*!< DIB DLSR: Not thirty-two bit Mask */ - -#define DIB_DLSR_SLK_Pos 1U /*!< DIB DLSR: Software Lock status Position */ -#define DIB_DLSR_SLK_Msk (0x1UL << DIB_DLSR_SLK_Pos ) /*!< DIB DLSR: Software Lock status Mask */ - -#define DIB_DLSR_SLI_Pos 0U /*!< DIB DLSR: Software Lock implemented Position */ -#define DIB_DLSR_SLI_Msk (0x1UL /*<< DIB_DLSR_SLI_Pos*/) /*!< DIB DLSR: Software Lock implemented Mask */ - -/* DAUTHSTATUS, Debug Authentication Status Register Definitions */ -#define DIB_DAUTHSTATUS_SNID_Pos 6U /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_SNID_Msk (0x3UL << DIB_DAUTHSTATUS_SNID_Pos ) /*!< DIB DAUTHSTATUS: Secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_SID_Pos 4U /*!< DIB DAUTHSTATUS: Secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_SID_Msk (0x3UL << DIB_DAUTHSTATUS_SID_Pos ) /*!< DIB DAUTHSTATUS: Secure Invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSNID_Pos 2U /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSNID_Msk (0x3UL << DIB_DAUTHSTATUS_NSNID_Pos ) /*!< DIB DAUTHSTATUS: Non-secure Non-invasive Debug Mask */ - -#define DIB_DAUTHSTATUS_NSID_Pos 0U /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Position */ -#define DIB_DAUTHSTATUS_NSID_Msk (0x3UL /*<< DIB_DAUTHSTATUS_NSID_Pos*/) /*!< DIB DAUTHSTATUS: Non-secure Invasive Debug Mask */ - -/* DDEVARCH, SCS Device Architecture Register Definitions */ -#define DIB_DDEVARCH_ARCHITECT_Pos 21U /*!< DIB DDEVARCH: Architect Position */ -#define DIB_DDEVARCH_ARCHITECT_Msk (0x7FFUL << DIB_DDEVARCH_ARCHITECT_Pos ) /*!< DIB DDEVARCH: Architect Mask */ - -#define DIB_DDEVARCH_PRESENT_Pos 20U /*!< DIB DDEVARCH: DEVARCH Present Position */ -#define DIB_DDEVARCH_PRESENT_Msk (0x1FUL << DIB_DDEVARCH_PRESENT_Pos ) /*!< DIB DDEVARCH: DEVARCH Present Mask */ - -#define DIB_DDEVARCH_REVISION_Pos 16U /*!< DIB DDEVARCH: Revision Position */ -#define DIB_DDEVARCH_REVISION_Msk (0xFUL << DIB_DDEVARCH_REVISION_Pos ) /*!< DIB DDEVARCH: Revision Mask */ - -#define DIB_DDEVARCH_ARCHVER_Pos 12U /*!< DIB DDEVARCH: Architecture Version Position */ -#define DIB_DDEVARCH_ARCHVER_Msk (0xFUL << DIB_DDEVARCH_ARCHVER_Pos ) /*!< DIB DDEVARCH: Architecture Version Mask */ - -#define DIB_DDEVARCH_ARCHPART_Pos 0U /*!< DIB DDEVARCH: Architecture Part Position */ -#define DIB_DDEVARCH_ARCHPART_Msk (0xFFFUL /*<< DIB_DDEVARCH_ARCHPART_Pos*/) /*!< DIB DDEVARCH: Architecture Part Mask */ - -/* DDEVTYPE, SCS Device Type Register Definitions */ -#define DIB_DDEVTYPE_SUB_Pos 4U /*!< DIB DDEVTYPE: Sub-type Position */ -#define DIB_DDEVTYPE_SUB_Msk (0xFUL << DIB_DDEVTYPE_SUB_Pos ) /*!< DIB DDEVTYPE: Sub-type Mask */ - -#define DIB_DDEVTYPE_MAJOR_Pos 0U /*!< DIB DDEVTYPE: Major type Position */ -#define DIB_DDEVTYPE_MAJOR_Msk (0xFUL /*<< DIB_DDEVTYPE_MAJOR_Pos*/) /*!< DIB DDEVTYPE: Major type Mask */ - - -/*@} end of group CMSIS_DIB */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_bitfield Core register bit field macros - \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). - @{ - */ - -/** - \brief Mask and shift a bit field value for use in a register bit range. - \param[in] field Name of the register bit field. - \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. - \return Masked and shifted value. -*/ -#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) - -/** - \brief Mask and shift a register value to extract a bit filed value. - \param[in] field Name of the register bit field. - \param[in] value Value of register. This parameter is interpreted as an uint32_t type. - \return Masked and shifted bit field value. -*/ -#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) - -/*@} end of group CMSIS_core_bitfield */ - - -/** - \ingroup CMSIS_core_register - \defgroup CMSIS_core_base Core Definitions - \brief Definitions for base addresses, unions, and structures. - @{ - */ - -/* Memory mapping of Core Hardware */ - #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ - #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ - #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ - #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ - #define DCB_BASE (0xE000EDF0UL) /*!< DCB Base Address */ - #define DIB_BASE (0xE000EFB0UL) /*!< DIB Base Address */ - #define EMSS_BASE (0xE001E000UL) /*!AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping - \details Reads the priority grouping field from the NVIC Interrupt Controller. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) -{ - return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt - \details Enables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - __COMPILER_BARRIER(); - NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __COMPILER_BARRIER(); - } -} - - -/** - \brief Get Interrupt Enable status - \details Returns a device specific interrupt enable status from the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt - \details Disables a device specific interrupt in the NVIC interrupt controller. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - __DSB(); - __ISB(); - } -} - - -/** - \brief Get Pending Interrupt - \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt - \details Sets the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt - \details Clears the pending bit of a device specific interrupt in the NVIC pending register. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt - \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Interrupt Target State - \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - \return 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Target State - \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Clear Interrupt Target State - \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 if interrupt is assigned to Secure - 1 if interrupt is assigned to Non Secure - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); - return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - -/** - \brief Set Interrupt Priority - \details Sets the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every processor exception. - */ -__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority - \details Reads the priority of a device specific interrupt or a processor exception. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. - Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} - - -/** - \brief Encode Priority - \details Encodes the priority for an interrupt with the given priority group, - preemptive priority value, and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Used priority group. - \param [in] PreemptPriority Preemptive priority value (starting from 0). - \param [in] SubPriority Subpriority value (starting from 0). - \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). - */ -__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - return ( - ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | - ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) - ); -} - - -/** - \brief Decode Priority - \details Decodes an interrupt priority value with a given priority group to - preemptive priority value and subpriority value. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. - \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). - \param [in] PriorityGroup Used priority group. - \param [out] pPreemptPriority Preemptive priority value (starting from 0). - \param [out] pSubPriority Subpriority value (starting from 0). - */ -__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) -{ - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - uint32_t PreemptPriorityBits; - uint32_t SubPriorityBits; - - PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); - SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); - - *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); - *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); -} - - -/** - \brief Set Interrupt Vector - \details Sets an interrupt vector in SRAM based interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - VTOR must been relocated to SRAM before. - \param [in] IRQn Interrupt number - \param [in] vector Address of interrupt handler function - */ -__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; - __DSB(); -} - - -/** - \brief Get Interrupt Vector - \details Reads an interrupt vector from interrupt vector table. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Address of interrupt handler function - */ -__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) -{ - uint32_t *vectors = (uint32_t *)SCB->VTOR; - return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; -} - - -/** - \brief System Reset - \details Initiates a system reset request to reset the MCU. - */ -__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses including - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | - SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - -/** - \brief Software Reset - \details Initiates a system reset request to reset the CPU. - */ -__NO_RETURN __STATIC_INLINE void __SW_SystemReset(void) -{ - __DSB(); /* Ensure all outstanding memory accesses including - buffered write are completed before reset */ - SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (SCB->AIRCR & SCB_AIRCR_BFHFNMINS_Msk) | /* Keep BFHFNMINS unchanged. Use this Reset function in case your case need to keep it */ - (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | /* Keep priority group unchanged */ - SCB_AIRCR_SYSRESETREQ_Msk ); - __DSB(); /* Ensure completion of memory access */ - - for(;;) /* wait until reset */ - { - __NOP(); - } -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Priority Grouping (non-secure) - \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. - The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. - Only values from 0..7 are used. - In case of a conflict between priority grouping and available - priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. - \param [in] PriorityGroup Priority grouping field. - */ -__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) -{ - uint32_t reg_value; - uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ - - reg_value = SCB_NS->AIRCR; /* read old register configuration */ - reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ - reg_value = (reg_value | - ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | - (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ - SCB_NS->AIRCR = reg_value; -} - - -/** - \brief Get Priority Grouping (non-secure) - \details Reads the priority grouping field from the non-secure NVIC when in secure state. - \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) -{ - return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); -} - - -/** - \brief Enable Interrupt (non-secure) - \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Interrupt Enable status (non-secure) - \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt is not enabled. - \return 1 Interrupt is enabled. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Disable Interrupt (non-secure) - \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Pending Interrupt (non-secure) - \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not pending. - \return 1 Interrupt status is pending. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Pending Interrupt (non-secure) - \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Clear Pending Interrupt (non-secure) - \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. - \param [in] IRQn Device specific interrupt number. - \note IRQn must not be negative. - */ -__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); - } -} - - -/** - \brief Get Active Interrupt (non-secure) - \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. - \param [in] IRQn Device specific interrupt number. - \return 0 Interrupt status is not active. - \return 1 Interrupt status is active. - \note IRQn must not be negative. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) -{ - if ((int32_t)(IRQn) >= 0) - { - return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); - } - else - { - return(0U); - } -} - - -/** - \brief Set Interrupt Priority (non-secure) - \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \param [in] priority Priority to set. - \note The priority cannot be set for every non-secure processor exception. - */ -__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) -{ - if ((int32_t)(IRQn) >= 0) - { - NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } - else - { - SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); - } -} - - -/** - \brief Get Interrupt Priority (non-secure) - \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. - The interrupt number can be positive to specify a device specific interrupt, - or negative to specify a processor exception. - \param [in] IRQn Interrupt number. - \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. - */ -__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) -{ - - if ((int32_t)(IRQn) >= 0) - { - return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); - } - else - { - return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); - } -} -#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_NVICFunctions */ - -/* ########################## MPU functions #################################### */ - -#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) - -#include "mpu_armv8.h" - -#endif - -/* ########################## FPU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_FpuFunctions FPU Functions - \brief Function that provides FPU type. - @{ - */ - -/** - \brief get FPU type - \details returns the FPU type - \returns - - \b 0: No FPU - - \b 1: Single precision FPU - - \b 2: Double + Single precision FPU - */ -__STATIC_INLINE uint32_t SCB_GetFPUType(void) -{ - uint32_t mvfr0; - - mvfr0 = FPU->MVFR0; - if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) - { - return 2U; /* Double + Single precision FPU */ - } - else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) - { - return 1U; /* Single precision FPU */ - } - else - { - return 0U; /* No FPU */ - } -} - - -/*@} end of CMSIS_Core_FpuFunctions */ - - - -/* ########################## SAU functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SAUFunctions SAU Functions - \brief Functions that configure the SAU. - @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - \brief Enable SAU - \details Enables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Enable(void) -{ - SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); -} - - - -/** - \brief Disable SAU - \details Disables the Security Attribution Unit (SAU). - */ -__STATIC_INLINE void TZ_SAU_Disable(void) -{ - SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); -} - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_SAUFunctions */ - - - -/* ################################## Debug Control function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DCBFunctions Debug Control Functions - \brief Functions that access the Debug Control Block. - @{ - */ - - -/** - \brief Set Debug Authentication Control Register - \details writes to Debug Authentication Control register. - \param [in] value value to be writen. - */ -__STATIC_INLINE void DCB_SetAuthCtrl(uint32_t value) -{ - __DSB(); - __ISB(); - DCB->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register - \details Reads Debug Authentication Control register. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t DCB_GetAuthCtrl(void) -{ - return (DCB->DAUTHCTRL); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Set Debug Authentication Control Register (non-secure) - \details writes to non-secure Debug Authentication Control register when in secure state. - \param [in] value value to be writen - */ -__STATIC_INLINE void TZ_DCB_SetAuthCtrl_NS(uint32_t value) -{ - __DSB(); - __ISB(); - DCB_NS->DAUTHCTRL = value; - __DSB(); - __ISB(); -} - - -/** - \brief Get Debug Authentication Control Register (non-secure) - \details Reads non-secure Debug Authentication Control register when in secure state. - \return Debug Authentication Control Register. - */ -__STATIC_INLINE uint32_t TZ_DCB_GetAuthCtrl_NS(void) -{ - return (DCB_NS->DAUTHCTRL); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - - - -/* ################################## Debug Identification function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_DIBFunctions Debug Identification Functions - \brief Functions that access the Debug Identification Block. - @{ - */ - - -/** - \brief Get Debug Authentication Status Register - \details Reads Debug Authentication Status register. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t DIB_GetAuthStatus(void) -{ - return (DIB->DAUTHSTATUS); -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief Get Debug Authentication Status Register (non-secure) - \details Reads non-secure Debug Authentication Status register when in secure state. - \return Debug Authentication Status Register. - */ -__STATIC_INLINE uint32_t TZ_DIB_GetAuthStatus_NS(void) -{ - return (DIB_NS->DAUTHSTATUS); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/*@} end of CMSIS_Core_DCBFunctions */ - - -#if ((defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)) || \ - (defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U))) - -/* ########################## Cache functions #################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_CacheFunctions Cache Functions - \brief Functions that configure Instruction and Data cache. - @{ - */ - -/* Cache Size ID Register Macros */ -#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) -#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) - -#define __SCB_DCACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ -#define __SCB_ICACHE_LINE_SIZE 32U /*!< STAR-MC1 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ - -/** - \brief Enable I-Cache - \details Turns on I-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ - - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable I-Cache - \details Turns off I-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ - SCB->ICIALLU = 0UL; /* invalidate I-Cache */ - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate I-Cache - \details Invalidates I-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateICache (void) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - __DSB(); - __ISB(); - SCB->ICIALLU = 0UL; - __DSB(); - __ISB(); - #endif -} - - -/** - \brief I-Cache Invalidate by address - \details Invalidates I-Cache for the given address. - I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - I-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] isize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) -{ - #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) - if ( isize > 0 ) { - int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_ICACHE_LINE_SIZE; - op_size -= __SCB_ICACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief Enable D-Cache - \details Turns on D-Cache - */ -__STATIC_FORCEINLINE void SCB_EnableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - __DSB(); - - SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Disable D-Cache - \details Turns off D-Cache - */ -__STATIC_FORCEINLINE void SCB_DisableDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Invalidate D-Cache - \details Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | - ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean D-Cache - \details Cleans D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | - ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief Clean & Invalidate D-Cache - \details Cleans and Invalidates D-Cache - */ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - uint32_t ccsidr; - uint32_t sets; - uint32_t ways; - - SCB->CSSELR = 0U; /* select Level 1 data cache */ - __DSB(); - - ccsidr = SCB->CCSIDR; - - /* clean & invalidate D-Cache */ - sets = (uint32_t)(CCSIDR_SETS(ccsidr)); - do { - ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); - do { - SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | - ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); - #if defined ( __CC_ARM ) - __schedule_barrier(); - #endif - } while (ways-- != 0U); - } while(sets-- != 0U); - - __DSB(); - __ISB(); - #endif -} - - -/** - \brief D-Cache Invalidate by address - \details Invalidates D-Cache for the given address. - D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are invalidated. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean by address - \details Cleans D-Cache for the given address - D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned. - \param[in] addr address - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - - -/** - \brief D-Cache Clean and Invalidate by address - \details Cleans and invalidates D_Cache for the given address - D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. - D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. - \param[in] addr address (aligned to 32-byte boundary) - \param[in] dsize size of memory block (in number of bytes) -*/ -__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) -{ - #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) - if ( dsize > 0 ) { - int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); - uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; - - __DSB(); - - do { - SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ - op_addr += __SCB_DCACHE_LINE_SIZE; - op_size -= __SCB_DCACHE_LINE_SIZE; - } while ( op_size > 0 ); - - __DSB(); - __ISB(); - } - #endif -} - -/*@} end of CMSIS_Core_CacheFunctions */ -#endif - - -/* ################################## SysTick function ############################################ */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_SysTickFunctions SysTick Functions - \brief Functions that configure the System. - @{ - */ - -#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) - -/** - \brief System Tick Configuration - \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function SysTick_Config is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - */ -__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - \brief System Tick Configuration (non-secure) - \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. - Counter is in free running mode to generate periodic interrupts. - \param [in] ticks Number of ticks between two interrupts. - \return 0 Function succeeded. - \return 1 Function failed. - \note When the variable __Vendor_SysTickConfig is set to 1, then the - function TZ_SysTick_Config_NS is not included. In this case, the file device.h - must contain a vendor-specific implementation of this function. - - */ -__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) -{ - if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - return (1UL); /* Reload value impossible */ - } - - SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ - TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ - SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_TICKINT_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ - return (0UL); /* Function successful */ -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#endif - -/*@} end of CMSIS_Core_SysTickFunctions */ - - - -/* ##################################### Debug In/Output function ########################################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_core_DebugFunctions ITM Functions - \brief Functions that access the ITM debug interface. - @{ - */ - -extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ -#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ - - -/** - \brief ITM Send Character - \details Transmits a character via the ITM channel 0, and - \li Just returns when no debugger is connected that has booked the output. - \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. - \param [in] ch Character to transmit. - \returns Character to transmit. - */ -__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) -{ - if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ - ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ - { - while (ITM->PORT[0U].u32 == 0UL) - { - __NOP(); - } - ITM->PORT[0U].u8 = (uint8_t)ch; - } - return (ch); -} - - -/** - \brief ITM Receive Character - \details Inputs a character via the external variable \ref ITM_RxBuffer. - \return Received character. - \return -1 No character pending. - */ -__STATIC_INLINE int32_t ITM_ReceiveChar (void) -{ - int32_t ch = -1; /* no character available */ - - if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) - { - ch = ITM_RxBuffer; - ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ - } - - return (ch); -} - - -/** - \brief ITM Check Character - \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. - \return 0 No character available. - \return 1 Character available. - */ -__STATIC_INLINE int32_t ITM_CheckChar (void) -{ - - if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) - { - return (0); /* no character available */ - } - else - { - return (1); /* character available */ - } -} - -/*@} end of CMSIS_core_DebugFunctions */ - - - - -#ifdef __cplusplus -} -#endif - -#endif /* __CORE_STAR_H_DEPENDANT */ - -#endif /* __CMSIS_GENERIC */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/mpu_armv7.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/mpu_armv7.h deleted file mode 100644 index d9eedf81a..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/mpu_armv7.h +++ /dev/null @@ -1,275 +0,0 @@ -/****************************************************************************** - * @file mpu_armv7.h - * @brief CMSIS MPU API for Armv7-M MPU - * @version V5.1.2 - * @date 25. May 2020 - ******************************************************************************/ -/* - * Copyright (c) 2017-2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV7_H -#define ARM_MPU_ARMV7_H - -#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes -#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes -#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes -#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes -#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes -#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte -#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes -#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes -#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes -#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes -#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes -#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes -#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes -#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes -#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes -#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte -#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes -#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes -#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes -#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes -#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes -#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes -#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes -#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes -#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes -#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte -#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes -#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes - -#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access -#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only -#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only -#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access -#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only -#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access - -/** MPU Region Base Address Register Value -* -* \param Region The region to be configured, number 0 to 15. -* \param BaseAddress The base address for the region. -*/ -#define ARM_MPU_RBAR(Region, BaseAddress) \ - (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ - ((Region) & MPU_RBAR_REGION_Msk) | \ - (MPU_RBAR_VALID_Msk)) - -/** -* MPU Memory Access Attributes -* -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -*/ -#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ - ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ - (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ - (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ - (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ - ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ - (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ - (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ - (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ - (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ - (((MPU_RASR_ENABLE_Msk)))) - -/** -* MPU Region Attribute and Size Register Value -* -* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. -* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. -* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. -* \param IsShareable Region is shareable between multiple bus masters. -* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. -* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. -* \param SubRegionDisable Sub-region disable field. -* \param Size Region size of the region to be configured, for example 4K, 8K. -*/ -#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ - ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) - -/** -* MPU Memory Access Attribute for strongly ordered memory. -* - TEX: 000b -* - Shareable -* - Non-cacheable -* - Non-bufferable -*/ -#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) - -/** -* MPU Memory Access Attribute for device memory. -* - TEX: 000b (if shareable) or 010b (if non-shareable) -* - Shareable or non-shareable -* - Non-cacheable -* - Bufferable (if shareable) or non-bufferable (if non-shareable) -* -* \param IsShareable Configures the device memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) - -/** -* MPU Memory Access Attribute for normal memory. -* - TEX: 1BBb (reflecting outer cacheability rules) -* - Shareable or non-shareable -* - Cacheable or non-cacheable (reflecting inner cacheability rules) -* - Bufferable or non-bufferable (reflecting inner cacheability rules) -* -* \param OuterCp Configures the outer cache policy. -* \param InnerCp Configures the inner cache policy. -* \param IsShareable Configures the memory as shareable or non-shareable. -*/ -#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) >> 1U), ((InnerCp) & 1U)) - -/** -* MPU Memory Access Attribute non-cacheable policy. -*/ -#define ARM_MPU_CACHEP_NOCACHE 0U - -/** -* MPU Memory Access Attribute write-back, write and read allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_WRA 1U - -/** -* MPU Memory Access Attribute write-through, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WT_NWA 2U - -/** -* MPU Memory Access Attribute write-back, no write allocate policy. -*/ -#define ARM_MPU_CACHEP_WB_NWA 3U - - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; //!< The region base address register value (RBAR) - uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - MPU->RNR = rnr; - MPU->RASR = 0U; -} - -/** Configure an MPU region. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) -{ - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rasr Value for RASR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) -{ - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RASR = rasr; -} - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_Load(). -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - while (cnt > MPU_TYPE_RALIASES) { - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); - table += MPU_TYPE_RALIASES; - cnt -= MPU_TYPE_RALIASES; - } - ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); -} - -#endif diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/mpu_armv8.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/mpu_armv8.h deleted file mode 100644 index 3de16efc8..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/mpu_armv8.h +++ /dev/null @@ -1,352 +0,0 @@ -/****************************************************************************** - * @file mpu_armv8.h - * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU - * @version V5.1.3 - * @date 03. February 2021 - ******************************************************************************/ -/* - * Copyright (c) 2017-2021 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_MPU_ARMV8_H -#define ARM_MPU_ARMV8_H - -/** \brief Attribute for device memory (outer only) */ -#define ARM_MPU_ATTR_DEVICE ( 0U ) - -/** \brief Attribute for non-cacheable, normal memory */ -#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) - -/** \brief Attribute for normal memory (outer and inner) -* \param NT Non-Transient: Set to 1 for non-transient data. -* \param WB Write-Back: Set to 1 to use write-back update policy. -* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. -* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. -*/ -#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ - ((((NT) & 1U) << 3U) | (((WB) & 1U) << 2U) | (((RA) & 1U) << 1U) | ((WA) & 1U)) - -/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) - -/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) - -/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_nGRE (2U) - -/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ -#define ARM_MPU_ATTR_DEVICE_GRE (3U) - -/** \brief Memory Attribute -* \param O Outer memory attributes -* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes -*/ -#define ARM_MPU_ATTR(O, I) ((((O) & 0xFU) << 4U) | ((((O) & 0xFU) != 0U) ? ((I) & 0xFU) : (((I) & 0x3U) << 2U))) - -/** \brief Normal memory non-shareable */ -#define ARM_MPU_SH_NON (0U) - -/** \brief Normal memory outer shareable */ -#define ARM_MPU_SH_OUTER (2U) - -/** \brief Normal memory inner shareable */ -#define ARM_MPU_SH_INNER (3U) - -/** \brief Memory access permissions -* \param RO Read-Only: Set to 1 for read-only memory. -* \param NP Non-Privileged: Set to 1 for non-privileged memory. -*/ -#define ARM_MPU_AP_(RO, NP) ((((RO) & 1U) << 1U) | ((NP) & 1U)) - -/** \brief Region Base Address Register value -* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. -* \param SH Defines the Shareability domain for this memory region. -* \param RO Read-Only: Set to 1 for a read-only memory region. -* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. -* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. -*/ -#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ - (((BASE) & MPU_RBAR_BASE_Msk) | \ - (((SH) << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ - ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ - (((XN) << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) - -/** \brief Region Limit Address Register value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR(LIMIT, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#if defined(MPU_RLAR_PXN_Pos) - -/** \brief Region Limit Address Register with PXN value -* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. -* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. -* \param IDX The attribute index to be associated with this memory region. -*/ -#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ - (((LIMIT) & MPU_RLAR_LIMIT_Msk) | \ - (((PXN) << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ - (((IDX) << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ - (MPU_RLAR_EN_Msk)) - -#endif - -/** -* Struct for a single MPU Region -*/ -typedef struct { - uint32_t RBAR; /*!< Region Base Address Register value */ - uint32_t RLAR; /*!< Region Limit Address Register value */ -} ARM_MPU_Region_t; - -/** Enable the MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} - -#ifdef MPU_NS -/** Enable the Non-secure MPU. -* \param MPU_Control Default access permissions for unconfigured regions. -*/ -__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; -#endif - __DSB(); - __ISB(); -} - -/** Disable the Non-secure MPU. -*/ -__STATIC_INLINE void ARM_MPU_Disable_NS(void) -{ - __DMB(); -#ifdef SCB_SHCSR_MEMFAULTENA_Msk - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; -#endif - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - __DSB(); - __ISB(); -} -#endif - -/** Set the memory attribute encoding to the given MPU. -* \param mpu Pointer to the MPU to be configured. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) -{ - const uint8_t reg = idx / 4U; - const uint32_t pos = ((idx % 4U) * 8U); - const uint32_t mask = 0xFFU << pos; - - if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { - return; // invalid index - } - - mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); -} - -/** Set the memory attribute encoding. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU, idx, attr); -} - -#ifdef MPU_NS -/** Set the memory attribute encoding to the Non-secure MPU. -* \param idx The attribute index to be set [0-7] -* \param attr The attribute value to be set. -*/ -__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) -{ - ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); -} -#endif - -/** Clear and disable the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) -{ - mpu->RNR = rnr; - mpu->RLAR = 0U; -} - -/** Clear and disable the given MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU, rnr); -} - -#ifdef MPU_NS -/** Clear and disable the given Non-secure MPU region. -* \param rnr Region number to be cleared. -*/ -__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) -{ - ARM_MPU_ClrRegionEx(MPU_NS, rnr); -} -#endif - -/** Configure the given MPU region of the given MPU. -* \param mpu Pointer to MPU to be used. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - mpu->RNR = rnr; - mpu->RBAR = rbar; - mpu->RLAR = rlar; -} - -/** Configure the given MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); -} - -#ifdef MPU_NS -/** Configure the given Non-secure MPU region. -* \param rnr Region number to be configured. -* \param rbar Value for RBAR register. -* \param rlar Value for RLAR register. -*/ -__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) -{ - ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); -} -#endif - -/** Memcpy with strictly ordered memory access, e.g. used by code in ARM_MPU_LoadEx() -* \param dst Destination data is copied to. -* \param src Source data is copied from. -* \param len Amount of data words to be copied. -*/ -__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) -{ - uint32_t i; - for (i = 0U; i < len; ++i) - { - dst[i] = src[i]; - } -} - -/** Load the given number of MPU regions from a table to the given MPU. -* \param mpu Pointer to the MPU registers to be used. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; - if (cnt == 1U) { - mpu->RNR = rnr; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); - } else { - uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); - uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; - - mpu->RNR = rnrBase; - while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { - uint32_t c = MPU_TYPE_RALIASES - rnrOffset; - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - table += c; - cnt -= c; - rnrOffset = 0U; - rnrBase += MPU_TYPE_RALIASES; - mpu->RNR = rnrBase; - } - - ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); - } -} - -/** Load the given number of MPU regions from a table. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU, rnr, table, cnt); -} - -#ifdef MPU_NS -/** Load the given number of MPU regions from a table to the Non-secure MPU. -* \param rnr First region number to be configured. -* \param table Pointer to the MPU configuration table. -* \param cnt Amount of regions to be configured. -*/ -__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) -{ - ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); -} -#endif - -#endif - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/pac_armv81.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/pac_armv81.h deleted file mode 100644 index 854b60a20..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/pac_armv81.h +++ /dev/null @@ -1,206 +0,0 @@ -/****************************************************************************** - * @file pac_armv81.h - * @brief CMSIS PAC key functions for Armv8.1-M PAC extension - * @version V1.0.0 - * @date 23. March 2022 - ******************************************************************************/ -/* - * Copyright (c) 2022 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef PAC_ARMV81_H -#define PAC_ARMV81_H - - -/* ################### PAC Key functions ########################### */ -/** - \ingroup CMSIS_Core_FunctionInterface - \defgroup CMSIS_Core_PacKeyFunctions PAC Key functions - \brief Functions that access the PAC keys. - @{ - */ - -#if (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) - -/** - \brief read the PAC key used for privileged mode - \details Reads the PAC key stored in the PAC_KEY_P registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode - \details writes the given PAC key to the PAC_KEY_P registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_P (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode - \details Reads the PAC key stored in the PAC_KEY_U registers. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __get_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode - \details writes the given PAC key to the PAC_KEY_U registers. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __set_PAC_KEY_U (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) - -/** - \brief read the PAC key used for privileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_P registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_p_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_p_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_p_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_p_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for privileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_P registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_P_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_p_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_p_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_p_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_p_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief read the PAC key used for unprivileged mode (non-secure) - \details Reads the PAC key stored in the non-secure PAC_KEY_U registers when in secure mode. - \param [out] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_get_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "mrs r1, pac_key_u_0_ns\n" - "str r1,[%0,#0]\n" - "mrs r1, pac_key_u_1_ns\n" - "str r1,[%0,#4]\n" - "mrs r1, pac_key_u_2_ns\n" - "str r1,[%0,#8]\n" - "mrs r1, pac_key_u_3_ns\n" - "str r1,[%0,#12]\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -/** - \brief write the PAC key used for unprivileged mode (non-secure) - \details writes the given PAC key to the non-secure PAC_KEY_U registers when in secure mode. - \param [in] pPacKey 128bit PAC key - */ -__STATIC_FORCEINLINE void __TZ_set_PAC_KEY_U_NS (uint32_t* pPacKey) { - __ASM volatile ( - "ldr r1,[%0,#0]\n" - "msr pac_key_u_0_ns, r1\n" - "ldr r1,[%0,#4]\n" - "msr pac_key_u_1_ns, r1\n" - "ldr r1,[%0,#8]\n" - "msr pac_key_u_2_ns, r1\n" - "ldr r1,[%0,#12]\n" - "msr pac_key_u_3_ns, r1\n" - : : "r" (pPacKey) : "memory", "r1" - ); -} - -#endif /* (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) */ - -#endif /* (defined (__ARM_FEATURE_PAUTH) && (__ARM_FEATURE_PAUTH == 1)) */ - -/*@} end of CMSIS_Core_PacKeyFunctions */ - - -#endif /* PAC_ARMV81_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/pmu_armv8.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/pmu_armv8.h deleted file mode 100644 index f8f3d8935..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/pmu_armv8.h +++ /dev/null @@ -1,337 +0,0 @@ -/****************************************************************************** - * @file pmu_armv8.h - * @brief CMSIS PMU API for Armv8.1-M PMU - * @version V1.0.1 - * @date 15. April 2020 - ******************************************************************************/ -/* - * Copyright (c) 2020 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef ARM_PMU_ARMV8_H -#define ARM_PMU_ARMV8_H - -/** - * \brief PMU Events - * \note See the Armv8.1-M Architecture Reference Manual for full details on these PMU events. - * */ - -#define ARM_PMU_SW_INCR 0x0000 /*!< Software update to the PMU_SWINC register, architecturally executed and condition code check pass */ -#define ARM_PMU_L1I_CACHE_REFILL 0x0001 /*!< L1 I-Cache refill */ -#define ARM_PMU_L1D_CACHE_REFILL 0x0003 /*!< L1 D-Cache refill */ -#define ARM_PMU_L1D_CACHE 0x0004 /*!< L1 D-Cache access */ -#define ARM_PMU_LD_RETIRED 0x0006 /*!< Memory-reading instruction architecturally executed and condition code check pass */ -#define ARM_PMU_ST_RETIRED 0x0007 /*!< Memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_INST_RETIRED 0x0008 /*!< Instruction architecturally executed */ -#define ARM_PMU_EXC_TAKEN 0x0009 /*!< Exception entry */ -#define ARM_PMU_EXC_RETURN 0x000A /*!< Exception return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_PC_WRITE_RETIRED 0x000C /*!< Software change to the Program Counter (PC). Instruction is architecturally executed and condition code check pass */ -#define ARM_PMU_BR_IMMED_RETIRED 0x000D /*!< Immediate branch architecturally executed */ -#define ARM_PMU_BR_RETURN_RETIRED 0x000E /*!< Function return instruction architecturally executed and the condition code check pass */ -#define ARM_PMU_UNALIGNED_LDST_RETIRED 0x000F /*!< Unaligned memory memory-reading or memory-writing instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BR_MIS_PRED 0x0010 /*!< Mispredicted or not predicted branch speculatively executed */ -#define ARM_PMU_CPU_CYCLES 0x0011 /*!< Cycle */ -#define ARM_PMU_BR_PRED 0x0012 /*!< Predictable branch speculatively executed */ -#define ARM_PMU_MEM_ACCESS 0x0013 /*!< Data memory access */ -#define ARM_PMU_L1I_CACHE 0x0014 /*!< Level 1 instruction cache access */ -#define ARM_PMU_L1D_CACHE_WB 0x0015 /*!< Level 1 data cache write-back */ -#define ARM_PMU_L2D_CACHE 0x0016 /*!< Level 2 data cache access */ -#define ARM_PMU_L2D_CACHE_REFILL 0x0017 /*!< Level 2 data cache refill */ -#define ARM_PMU_L2D_CACHE_WB 0x0018 /*!< Level 2 data cache write-back */ -#define ARM_PMU_BUS_ACCESS 0x0019 /*!< Bus access */ -#define ARM_PMU_MEMORY_ERROR 0x001A /*!< Local memory error */ -#define ARM_PMU_INST_SPEC 0x001B /*!< Instruction speculatively executed */ -#define ARM_PMU_BUS_CYCLES 0x001D /*!< Bus cycles */ -#define ARM_PMU_CHAIN 0x001E /*!< For an odd numbered counter, increment when an overflow occurs on the preceding even-numbered counter on the same PE */ -#define ARM_PMU_L1D_CACHE_ALLOCATE 0x001F /*!< Level 1 data cache allocation without refill */ -#define ARM_PMU_L2D_CACHE_ALLOCATE 0x0020 /*!< Level 2 data cache allocation without refill */ -#define ARM_PMU_BR_RETIRED 0x0021 /*!< Branch instruction architecturally executed */ -#define ARM_PMU_BR_MIS_PRED_RETIRED 0x0022 /*!< Mispredicted branch instruction architecturally executed */ -#define ARM_PMU_STALL_FRONTEND 0x0023 /*!< No operation issued because of the frontend */ -#define ARM_PMU_STALL_BACKEND 0x0024 /*!< No operation issued because of the backend */ -#define ARM_PMU_L2I_CACHE 0x0027 /*!< Level 2 instruction cache access */ -#define ARM_PMU_L2I_CACHE_REFILL 0x0028 /*!< Level 2 instruction cache refill */ -#define ARM_PMU_L3D_CACHE_ALLOCATE 0x0029 /*!< Level 3 data cache allocation without refill */ -#define ARM_PMU_L3D_CACHE_REFILL 0x002A /*!< Level 3 data cache refill */ -#define ARM_PMU_L3D_CACHE 0x002B /*!< Level 3 data cache access */ -#define ARM_PMU_L3D_CACHE_WB 0x002C /*!< Level 3 data cache write-back */ -#define ARM_PMU_LL_CACHE_RD 0x0036 /*!< Last level data cache read */ -#define ARM_PMU_LL_CACHE_MISS_RD 0x0037 /*!< Last level data cache read miss */ -#define ARM_PMU_L1D_CACHE_MISS_RD 0x0039 /*!< Level 1 data cache read miss */ -#define ARM_PMU_OP_COMPLETE 0x003A /*!< Operation retired */ -#define ARM_PMU_OP_SPEC 0x003B /*!< Operation speculatively executed */ -#define ARM_PMU_STALL 0x003C /*!< Stall cycle for instruction or operation not sent for execution */ -#define ARM_PMU_STALL_OP_BACKEND 0x003D /*!< Stall cycle for instruction or operation not sent for execution due to pipeline backend */ -#define ARM_PMU_STALL_OP_FRONTEND 0x003E /*!< Stall cycle for instruction or operation not sent for execution due to pipeline frontend */ -#define ARM_PMU_STALL_OP 0x003F /*!< Instruction or operation slots not occupied each cycle */ -#define ARM_PMU_L1D_CACHE_RD 0x0040 /*!< Level 1 data cache read */ -#define ARM_PMU_LE_RETIRED 0x0100 /*!< Loop end instruction executed */ -#define ARM_PMU_LE_SPEC 0x0101 /*!< Loop end instruction speculatively executed */ -#define ARM_PMU_BF_RETIRED 0x0104 /*!< Branch future instruction architecturally executed and condition code check pass */ -#define ARM_PMU_BF_SPEC 0x0105 /*!< Branch future instruction speculatively executed and condition code check pass */ -#define ARM_PMU_LE_CANCEL 0x0108 /*!< Loop end instruction not taken */ -#define ARM_PMU_BF_CANCEL 0x0109 /*!< Branch future instruction not taken */ -#define ARM_PMU_SE_CALL_S 0x0114 /*!< Call to secure function, resulting in Security state change */ -#define ARM_PMU_SE_CALL_NS 0x0115 /*!< Call to non-secure function, resulting in Security state change */ -#define ARM_PMU_DWT_CMPMATCH0 0x0118 /*!< DWT comparator 0 match */ -#define ARM_PMU_DWT_CMPMATCH1 0x0119 /*!< DWT comparator 1 match */ -#define ARM_PMU_DWT_CMPMATCH2 0x011A /*!< DWT comparator 2 match */ -#define ARM_PMU_DWT_CMPMATCH3 0x011B /*!< DWT comparator 3 match */ -#define ARM_PMU_MVE_INST_RETIRED 0x0200 /*!< MVE instruction architecturally executed */ -#define ARM_PMU_MVE_INST_SPEC 0x0201 /*!< MVE instruction speculatively executed */ -#define ARM_PMU_MVE_FP_RETIRED 0x0204 /*!< MVE floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SPEC 0x0205 /*!< MVE floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_HP_RETIRED 0x0208 /*!< MVE half-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_HP_SPEC 0x0209 /*!< MVE half-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_SP_RETIRED 0x020C /*!< MVE single-precision floating-point instruction architecturally executed */ -#define ARM_PMU_MVE_FP_SP_SPEC 0x020D /*!< MVE single-precision floating-point instruction speculatively executed */ -#define ARM_PMU_MVE_FP_MAC_RETIRED 0x0214 /*!< MVE floating-point multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_FP_MAC_SPEC 0x0215 /*!< MVE floating-point multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_INT_RETIRED 0x0224 /*!< MVE integer instruction architecturally executed */ -#define ARM_PMU_MVE_INT_SPEC 0x0225 /*!< MVE integer instruction speculatively executed */ -#define ARM_PMU_MVE_INT_MAC_RETIRED 0x0228 /*!< MVE multiply or multiply-accumulate instruction architecturally executed */ -#define ARM_PMU_MVE_INT_MAC_SPEC 0x0229 /*!< MVE multiply or multiply-accumulate instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_RETIRED 0x0238 /*!< MVE load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_SPEC 0x0239 /*!< MVE load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_RETIRED 0x023C /*!< MVE load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_SPEC 0x023D /*!< MVE load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_RETIRED 0x0240 /*!< MVE store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_SPEC 0x0241 /*!< MVE store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_CONTIG_RETIRED 0x0244 /*!< MVE contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_CONTIG_SPEC 0x0245 /*!< MVE contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_CONTIG_RETIRED 0x0248 /*!< MVE contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_CONTIG_SPEC 0x0249 /*!< MVE contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_CONTIG_RETIRED 0x024C /*!< MVE contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_CONTIG_SPEC 0x024D /*!< MVE contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_RETIRED 0x0250 /*!< MVE non-contiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_NONCONTIG_SPEC 0x0251 /*!< MVE non-contiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_RETIRED 0x0254 /*!< MVE non-contiguous load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_NONCONTIG_SPEC 0x0255 /*!< MVE non-contiguous load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_RETIRED 0x0258 /*!< MVE non-contiguous store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_NONCONTIG_SPEC 0x0259 /*!< MVE non-contiguous store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_MULTI_RETIRED 0x025C /*!< MVE memory instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LDST_MULTI_SPEC 0x025D /*!< MVE memory instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LD_MULTI_RETIRED 0x0260 /*!< MVE memory load instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_LD_MULTI_SPEC 0x0261 /*!< MVE memory load instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_ST_MULTI_RETIRED 0x0261 /*!< MVE memory store instruction targeting multiple registers architecturally executed */ -#define ARM_PMU_MVE_ST_MULTI_SPEC 0x0265 /*!< MVE memory store instruction targeting multiple registers speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_RETIRED 0x028C /*!< MVE unaligned memory load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_SPEC 0x028D /*!< MVE unaligned memory load or store instruction speculatively executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_RETIRED 0x0290 /*!< MVE unaligned load instruction architecturally executed */ -#define ARM_PMU_MVE_LD_UNALIGNED_SPEC 0x0291 /*!< MVE unaligned load instruction speculatively executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_RETIRED 0x0294 /*!< MVE unaligned store instruction architecturally executed */ -#define ARM_PMU_MVE_ST_UNALIGNED_SPEC 0x0295 /*!< MVE unaligned store instruction speculatively executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_RETIRED 0x0298 /*!< MVE unaligned noncontiguous load or store instruction architecturally executed */ -#define ARM_PMU_MVE_LDST_UNALIGNED_NONCONTIG_SPEC 0x0299 /*!< MVE unaligned noncontiguous load or store instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_RETIRED 0x02A0 /*!< MVE vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_SPEC 0x02A1 /*!< MVE vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_FP_RETIRED 0x02A4 /*!< MVE floating-point vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_FP_SPEC 0x02A5 /*!< MVE floating-point vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_VREDUCE_INT_RETIRED 0x02A8 /*!< MVE integer vector reduction instruction architecturally executed */ -#define ARM_PMU_MVE_VREDUCE_INT_SPEC 0x02A9 /*!< MVE integer vector reduction instruction speculatively executed */ -#define ARM_PMU_MVE_PRED 0x02B8 /*!< Cycles where one or more predicated beats architecturally executed */ -#define ARM_PMU_MVE_STALL 0x02CC /*!< Stall cycles caused by an MVE instruction */ -#define ARM_PMU_MVE_STALL_RESOURCE 0x02CD /*!< Stall cycles caused by an MVE instruction because of resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_MEM 0x02CE /*!< Stall cycles caused by an MVE instruction because of memory resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_FP 0x02CF /*!< Stall cycles caused by an MVE instruction because of floating-point resource conflicts */ -#define ARM_PMU_MVE_STALL_RESOURCE_INT 0x02D0 /*!< Stall cycles caused by an MVE instruction because of integer resource conflicts */ -#define ARM_PMU_MVE_STALL_BREAK 0x02D3 /*!< Stall cycles caused by an MVE chain break */ -#define ARM_PMU_MVE_STALL_DEPENDENCY 0x02D4 /*!< Stall cycles caused by MVE register dependency */ -#define ARM_PMU_ITCM_ACCESS 0x4007 /*!< Instruction TCM access */ -#define ARM_PMU_DTCM_ACCESS 0x4008 /*!< Data TCM access */ -#define ARM_PMU_TRCEXTOUT0 0x4010 /*!< ETM external output 0 */ -#define ARM_PMU_TRCEXTOUT1 0x4011 /*!< ETM external output 1 */ -#define ARM_PMU_TRCEXTOUT2 0x4012 /*!< ETM external output 2 */ -#define ARM_PMU_TRCEXTOUT3 0x4013 /*!< ETM external output 3 */ -#define ARM_PMU_CTI_TRIGOUT4 0x4018 /*!< Cross-trigger Interface output trigger 4 */ -#define ARM_PMU_CTI_TRIGOUT5 0x4019 /*!< Cross-trigger Interface output trigger 5 */ -#define ARM_PMU_CTI_TRIGOUT6 0x401A /*!< Cross-trigger Interface output trigger 6 */ -#define ARM_PMU_CTI_TRIGOUT7 0x401B /*!< Cross-trigger Interface output trigger 7 */ - -/** \brief PMU Functions */ - -__STATIC_INLINE void ARM_PMU_Enable(void); -__STATIC_INLINE void ARM_PMU_Disable(void); - -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type); - -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void); -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void); - -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void); -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num); - -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void); -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask); -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask); - -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask); - -/** - \brief Enable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Enable(void) -{ - PMU->CTRL |= PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Disable the PMU -*/ -__STATIC_INLINE void ARM_PMU_Disable(void) -{ - PMU->CTRL &= ~PMU_CTRL_ENABLE_Msk; -} - -/** - \brief Set event to count for PMU eventer counter - \param [in] num Event counter (0-30) to configure - \param [in] type Event to count -*/ -__STATIC_INLINE void ARM_PMU_Set_EVTYPER(uint32_t num, uint32_t type) -{ - PMU->EVTYPER[num] = type; -} - -/** - \brief Reset cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CYCCNT_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_CYCCNT_RESET_Msk; -} - -/** - \brief Reset all event counters -*/ -__STATIC_INLINE void ARM_PMU_EVCNTR_ALL_Reset(void) -{ - PMU->CTRL |= PMU_CTRL_EVENTCNT_RESET_Msk; -} - -/** - \brief Enable counters - \param [in] mask Counters to enable - \note Enables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Enable(uint32_t mask) -{ - PMU->CNTENSET = mask; -} - -/** - \brief Disable counters - \param [in] mask Counters to enable - \note Disables one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Disable(uint32_t mask) -{ - PMU->CNTENCLR = mask; -} - -/** - \brief Read cycle counter - \return Cycle count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CCNTR(void) -{ - return PMU->CCNTR; -} - -/** - \brief Read event counter - \param [in] num Event counter (0-30) to read - \return Event count -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_EVCNTR(uint32_t num) -{ - return PMU_EVCNTR_CNT_Msk & PMU->EVCNTR[num]; -} - -/** - \brief Read counter overflow status - \return Counter overflow status bits for the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE uint32_t ARM_PMU_Get_CNTR_OVS(void) -{ - return PMU->OVSSET; -} - -/** - \brief Clear counter overflow status - \param [in] mask Counter overflow status bits to clear - \note Clears overflow status bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_OVS(uint32_t mask) -{ - PMU->OVSCLR = mask; -} - -/** - \brief Enable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to set - \note Sets overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Enable(uint32_t mask) -{ - PMU->INTENSET = mask; -} - -/** - \brief Disable counter overflow interrupt request - \param [in] mask Counter overflow interrupt request bits to clear - \note Clears overflow interrupt request bits for one or more of the following: - - event counters (0-30) - - cycle counter -*/ -__STATIC_INLINE void ARM_PMU_Set_CNTR_IRQ_Disable(uint32_t mask) -{ - PMU->INTENCLR = mask; -} - -/** - \brief Software increment event counter - \param [in] mask Counters to increment - \note Software increment bits for one or more event counters (0-30) -*/ -__STATIC_INLINE void ARM_PMU_CNTR_Increment(uint32_t mask) -{ - PMU->SWINC = mask; -} - -#endif diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/tz_context.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/tz_context.h deleted file mode 100644 index 0d09749f3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/Include/tz_context.h +++ /dev/null @@ -1,70 +0,0 @@ -/****************************************************************************** - * @file tz_context.h - * @brief Context Management for Armv8-M TrustZone - * @version V1.0.1 - * @date 10. January 2018 - ******************************************************************************/ -/* - * Copyright (c) 2017-2018 Arm Limited. All rights reserved. - * - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the License); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an AS IS BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if defined ( __ICCARM__ ) - #pragma system_include /* treat file as system include file for MISRA check */ -#elif defined (__clang__) - #pragma clang system_header /* treat file as system include file */ -#endif - -#ifndef TZ_CONTEXT_H -#define TZ_CONTEXT_H - -#include - -#ifndef TZ_MODULEID_T -#define TZ_MODULEID_T -/// \details Data type that identifies secure software modules called by a process. -typedef uint32_t TZ_ModuleId_t; -#endif - -/// \details TZ Memory ID identifies an allocated memory slot. -typedef uint32_t TZ_MemoryId_t; - -/// Initialize secure context memory system -/// \return execution status (1: success, 0: error) -uint32_t TZ_InitContextSystem_S (void); - -/// Allocate context memory for calling secure software modules in TrustZone -/// \param[in] module identifies software modules called from non-secure mode -/// \return value != 0 id TrustZone memory slot identifier -/// \return value 0 no memory available or internal error -TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); - -/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); - -/// Load secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); - -/// Store secure context (called on RTOS thread context switch) -/// \param[in] id TrustZone memory slot identifier -/// \return execution status (1: success, 0: error) -uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); - -#endif // TZ_CONTEXT_H diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/LICENSE.txt b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/LICENSE.txt deleted file mode 100644 index 8dada3eda..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/CMSIS/LICENSE.txt +++ /dev/null @@ -1,201 +0,0 @@ - Apache License - Version 2.0, January 2004 - http://www.apache.org/licenses/ - - TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION - - 1. 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We also recommend that a - file or class name and description of purpose be included on the - same "printed page" as the copyright notice for easier - identification within third-party archives. - - Copyright {yyyy} {name of copyright owner} - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h deleted file mode 100644 index 60f2d9178..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ /dev/null @@ -1,4353 +0,0 @@ -/** - ****************************************************************************** - * @file stm32_hal_legacy.h - * @author MCD Application Team - * @brief This file contains aliases definition for the STM32Cube HAL constants - * macros and functions maintained for legacy purpose. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32_HAL_LEGACY -#define STM32_HAL_LEGACY - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Defines HAL CRYP Aliased Defines maintained for legacy purpose - * @{ - */ -#define AES_FLAG_RDERR CRYP_FLAG_RDERR -#define AES_FLAG_WRERR CRYP_FLAG_WRERR -#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF -#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR -#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32H7) || defined(STM32MP1) -#define CRYP_DATATYPE_32B CRYP_NO_SWAP -#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP -#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP -#define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#endif /* STM32H7 || STM32MP1 */ -/** - * @} - */ - -/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose - * @{ - */ -#define ADC_RESOLUTION12b ADC_RESOLUTION_12B -#define ADC_RESOLUTION10b ADC_RESOLUTION_10B -#define ADC_RESOLUTION8b ADC_RESOLUTION_8B -#define ADC_RESOLUTION6b ADC_RESOLUTION_6B -#define OVR_DATA_OVERWRITTEN ADC_OVR_DATA_OVERWRITTEN -#define OVR_DATA_PRESERVED ADC_OVR_DATA_PRESERVED -#define EOC_SINGLE_CONV ADC_EOC_SINGLE_CONV -#define EOC_SEQ_CONV ADC_EOC_SEQ_CONV -#define EOC_SINGLE_SEQ_CONV ADC_EOC_SINGLE_SEQ_CONV -#define REGULAR_GROUP ADC_REGULAR_GROUP -#define INJECTED_GROUP ADC_INJECTED_GROUP -#define REGULAR_INJECTED_GROUP ADC_REGULAR_INJECTED_GROUP -#define AWD_EVENT ADC_AWD_EVENT -#define AWD1_EVENT ADC_AWD1_EVENT -#define AWD2_EVENT ADC_AWD2_EVENT -#define AWD3_EVENT ADC_AWD3_EVENT -#define OVR_EVENT ADC_OVR_EVENT -#define JQOVF_EVENT ADC_JQOVF_EVENT -#define ALL_CHANNELS ADC_ALL_CHANNELS -#define REGULAR_CHANNELS ADC_REGULAR_CHANNELS -#define INJECTED_CHANNELS ADC_INJECTED_CHANNELS -#define SYSCFG_FLAG_SENSOR_ADC ADC_FLAG_SENSOR -#define SYSCFG_FLAG_VREF_ADC ADC_FLAG_VREFINT -#define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 -#define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 -#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 -#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6 -#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8 -#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO -#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2 -#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO -#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4 -#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO -#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11 -#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1 -#define ADC_EXTERNALTRIG_EDGE_NONE ADC_EXTERNALTRIGCONVEDGE_NONE -#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING -#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING -#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING -#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5 - -#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY -#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY -#define HAL_ADC_STATE_EOC_REG HAL_ADC_STATE_REG_EOC -#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC -#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL -#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL -#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1 - -#if defined(STM32H7) -#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT -#endif /* STM32H7 */ - -#if defined(STM32U5) -#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES -#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES -#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 -#endif /* STM32U5 */ - -#if defined(STM32H5) -#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE -#endif /* STM32H5 */ -/** - * @} - */ - -/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose - * @{ - */ -#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE -#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE -#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1 -#define COMP_EXTI_LINE_COMP2_EVENT COMP_EXTI_LINE_COMP2 -#define COMP_EXTI_LINE_COMP3_EVENT COMP_EXTI_LINE_COMP3 -#define COMP_EXTI_LINE_COMP4_EVENT COMP_EXTI_LINE_COMP4 -#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5 -#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 -#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 -#if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM - input 1 for COMP1, LPTIM input 2 for COMP2 */ -#endif -#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR -#if defined(STM32F373xC) || defined(STM32F378xx) -#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1 -#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR -#endif /* STM32F373xC || STM32F378xx */ - -#if defined(STM32L0) || defined(STM32L4) -#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON - -#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1 -#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2 -#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3 -#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4 -#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5 -#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6 - -#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT -#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT -#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT -#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT -#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1 -#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1 -#if defined(STM32L0) -/* Issue fixed on STM32L0 COMP driver: only 2 dedicated IO (IO1 and IO2), */ -/* IO2 was wrongly assigned to IO shared with DAC and IO3 was corresponding */ -/* to the second dedicated IO (only for COMP2). */ -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_DAC1_CH2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO2 -#else -#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2 -#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3 -#endif -#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4 -#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5 - -#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW -#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH - -/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */ -/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */ -#if defined(COMP_CSR_LOCK) -#define COMP_FLAG_LOCK COMP_CSR_LOCK -#elif defined(COMP_CSR_COMP1LOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK -#elif defined(COMP_CSR_COMPxLOCK) -#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK -#endif - -#if defined(STM32L4) -#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1 -#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1 -#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2 -#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2 -#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2 -#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE -#endif - -#if defined(STM32L0) -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER -#else -#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED -#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED -#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER -#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER -#endif - -#endif - -#if defined(STM32U5) -#define __HAL_COMP_COMP1_EXTI_CLEAR_RASING_FLAG __HAL_COMP_COMP1_EXTI_CLEAR_RISING_FLAG -#endif - -/** - * @} - */ - -/** @defgroup HAL_CORTEX_Aliased_Defines HAL CORTEX Aliased Defines maintained for legacy purpose - * @{ - */ -#define __HAL_CORTEX_SYSTICKCLK_CONFIG HAL_SYSTICK_CLKSourceConfig -#if defined(STM32U5) -#define MPU_DEVICE_nGnRnE MPU_DEVICE_NGNRNE -#define MPU_DEVICE_nGnRE MPU_DEVICE_NGNRE -#define MPU_DEVICE_nGRE MPU_DEVICE_NGRE -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup CRC_Aliases CRC API aliases - * @{ - */ -#if defined(STM32H5) || defined(STM32C0) -#else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for - inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for - inter STM32 series compatibility */ -#endif -/** - * @} - */ - -/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE -#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Defines HAL DAC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define DAC1_CHANNEL_1 DAC_CHANNEL_1 -#define DAC1_CHANNEL_2 DAC_CHANNEL_2 -#define DAC2_CHANNEL_1 DAC_CHANNEL_1 -#define DAC_WAVE_NONE 0x00000000U -#define DAC_WAVE_NOISE DAC_CR_WAVE1_0 -#define DAC_WAVE_TRIANGLE DAC_CR_WAVE1_1 -#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE -#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE -#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE - -#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) -#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL -#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL -#endif - -#if defined(STM32U5) -#define DAC_TRIGGER_STOP_LPTIM1_OUT DAC_TRIGGER_STOP_LPTIM1_CH1 -#define DAC_TRIGGER_STOP_LPTIM3_OUT DAC_TRIGGER_STOP_LPTIM3_CH1 -#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 -#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 -#endif - -#if defined(STM32H5) -#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 -#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 -#endif - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ - defined(STM32F4) || defined(STM32G4) -#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID -#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID -#endif - -/** - * @} - */ - -/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2 -#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4 -#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5 -#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4 -#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2 -#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32 -#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6 -#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7 -#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67 -#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67 -#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76 -#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6 -#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7 -#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6 - -#define IS_HAL_REMAPDMA IS_DMA_REMAP -#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE -#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE - -#if defined(STM32L4) - -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI1 HAL_DMAMUX1_REQ_GEN_EXTI1 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI2 HAL_DMAMUX1_REQ_GEN_EXTI2 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI3 HAL_DMAMUX1_REQ_GEN_EXTI3 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI4 HAL_DMAMUX1_REQ_GEN_EXTI4 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI5 HAL_DMAMUX1_REQ_GEN_EXTI5 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI6 HAL_DMAMUX1_REQ_GEN_EXTI6 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI7 HAL_DMAMUX1_REQ_GEN_EXTI7 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI8 HAL_DMAMUX1_REQ_GEN_EXTI8 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI9 HAL_DMAMUX1_REQ_GEN_EXTI9 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI10 HAL_DMAMUX1_REQ_GEN_EXTI10 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI11 HAL_DMAMUX1_REQ_GEN_EXTI11 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI12 HAL_DMAMUX1_REQ_GEN_EXTI12 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI13 HAL_DMAMUX1_REQ_GEN_EXTI13 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI14 HAL_DMAMUX1_REQ_GEN_EXTI14 -#define HAL_DMAMUX1_REQUEST_GEN_EXTI15 HAL_DMAMUX1_REQ_GEN_EXTI15 -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH3_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH3_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_DSI_TE HAL_DMAMUX1_REQ_GEN_DSI_TE -#define HAL_DMAMUX1_REQUEST_GEN_DSI_EOT HAL_DMAMUX1_REQ_GEN_DSI_EOT -#define HAL_DMAMUX1_REQUEST_GEN_DMA2D_EOT HAL_DMAMUX1_REQ_GEN_DMA2D_EOT -#define HAL_DMAMUX1_REQUEST_GEN_LTDC_IT HAL_DMAMUX1_REQ_GEN_LTDC_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ - defined(STM32L4S7xx) || defined(STM32L4S9xx) -#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif - -#endif /* STM32L4 */ - -#if defined(STM32G0) -#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2 -#define DMA_REQUEST_TIM16_TRIG_COM DMA_REQUEST_TIM16_COM -#define DMA_REQUEST_TIM17_TRIG_COM DMA_REQUEST_TIM17_COM - -#define LL_DMAMUX_REQ_TIM16_TRIG_COM LL_DMAMUX_REQ_TIM16_COM -#define LL_DMAMUX_REQ_TIM17_TRIG_COM LL_DMAMUX_REQ_TIM17_COM -#endif - -#if defined(STM32H7) - -#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 -#define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2 - -#define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX -#define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX - -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT -#define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0 -#define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO - -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT -#define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT -#define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP -#define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0 -#define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2 -#define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT -#define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT -#define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT -#define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT -#define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT - -#define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT -#define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING -#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING -#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING - -#define DFSDM_FILTER_EXT_TRIG_LPTIM1 DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT -#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT - -#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT -#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT - -#endif /* STM32H7 */ - -#if defined(STM32U5) -#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD -#define TYPEPROGRAM_DOUBLEWORD FLASH_TYPEPROGRAM_DOUBLEWORD -#define TYPEERASE_SECTORS FLASH_TYPEERASE_SECTORS -#define TYPEERASE_PAGES FLASH_TYPEERASE_PAGES -#define TYPEERASE_PAGEERASE FLASH_TYPEERASE_PAGES -#define TYPEERASE_MASSERASE FLASH_TYPEERASE_MASSERASE -#define WRPSTATE_DISABLE OB_WRPSTATE_DISABLE -#define WRPSTATE_ENABLE OB_WRPSTATE_ENABLE -#define HAL_FLASH_TIMEOUT_VALUE FLASH_TIMEOUT_VALUE -#define OBEX_PCROP OPTIONBYTE_PCROP -#define OBEX_BOOTCONFIG OPTIONBYTE_BOOTCONFIG -#define PCROPSTATE_DISABLE OB_PCROP_STATE_DISABLE -#define PCROPSTATE_ENABLE OB_PCROP_STATE_ENABLE -#define TYPEERASEDATA_BYTE FLASH_TYPEERASEDATA_BYTE -#define TYPEERASEDATA_HALFWORD FLASH_TYPEERASEDATA_HALFWORD -#define TYPEERASEDATA_WORD FLASH_TYPEERASEDATA_WORD -#define TYPEPROGRAMDATA_BYTE FLASH_TYPEPROGRAMDATA_BYTE -#define TYPEPROGRAMDATA_HALFWORD FLASH_TYPEPROGRAMDATA_HALFWORD -#define TYPEPROGRAMDATA_WORD FLASH_TYPEPROGRAMDATA_WORD -#define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE -#define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD -#define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD -#define PAGESIZE FLASH_PAGE_SIZE -#define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE -#define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD -#define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD -#define VOLTAGE_RANGE_1 FLASH_VOLTAGE_RANGE_1 -#define VOLTAGE_RANGE_2 FLASH_VOLTAGE_RANGE_2 -#define VOLTAGE_RANGE_3 FLASH_VOLTAGE_RANGE_3 -#define VOLTAGE_RANGE_4 FLASH_VOLTAGE_RANGE_4 -#define TYPEPROGRAM_FAST FLASH_TYPEPROGRAM_FAST -#define TYPEPROGRAM_FAST_AND_LAST FLASH_TYPEPROGRAM_FAST_AND_LAST -#define WRPAREA_BANK1_AREAA OB_WRPAREA_BANK1_AREAA -#define WRPAREA_BANK1_AREAB OB_WRPAREA_BANK1_AREAB -#define WRPAREA_BANK2_AREAA OB_WRPAREA_BANK2_AREAA -#define WRPAREA_BANK2_AREAB OB_WRPAREA_BANK2_AREAB -#define IWDG_STDBY_FREEZE OB_IWDG_STDBY_FREEZE -#define IWDG_STDBY_ACTIVE OB_IWDG_STDBY_RUN -#define IWDG_STOP_FREEZE OB_IWDG_STOP_FREEZE -#define IWDG_STOP_ACTIVE OB_IWDG_STOP_RUN -#define FLASH_ERROR_NONE HAL_FLASH_ERROR_NONE -#define FLASH_ERROR_RD HAL_FLASH_ERROR_RD -#define FLASH_ERROR_PG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_PGP HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_WRP HAL_FLASH_ERROR_WRP -#define FLASH_ERROR_OPTV HAL_FLASH_ERROR_OPTV -#define FLASH_ERROR_OPTVUSR HAL_FLASH_ERROR_OPTVUSR -#define FLASH_ERROR_PROG HAL_FLASH_ERROR_PROG -#define FLASH_ERROR_OP HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_PGA HAL_FLASH_ERROR_PGA -#define FLASH_ERROR_SIZE HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_SIZ HAL_FLASH_ERROR_SIZE -#define FLASH_ERROR_PGS HAL_FLASH_ERROR_PGS -#define FLASH_ERROR_MIS HAL_FLASH_ERROR_MIS -#define FLASH_ERROR_FAST HAL_FLASH_ERROR_FAST -#define FLASH_ERROR_FWWERR HAL_FLASH_ERROR_FWWERR -#define FLASH_ERROR_NOTZERO HAL_FLASH_ERROR_NOTZERO -#define FLASH_ERROR_OPERATION HAL_FLASH_ERROR_OPERATION -#define FLASH_ERROR_ERS HAL_FLASH_ERROR_ERS -#define OB_WDG_SW OB_IWDG_SW -#define OB_WDG_HW OB_IWDG_HW -#define OB_SDADC12_VDD_MONITOR_SET OB_SDACD_VDD_MONITOR_SET -#define OB_SDADC12_VDD_MONITOR_RESET OB_SDACD_VDD_MONITOR_RESET -#define OB_RAM_PARITY_CHECK_SET OB_SRAM_PARITY_SET -#define OB_RAM_PARITY_CHECK_RESET OB_SRAM_PARITY_RESET -#define IS_OB_SDADC12_VDD_MONITOR IS_OB_SDACD_VDD_MONITOR -#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0 -#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1 -#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2 -#if defined(STM32G0) || defined(STM32C0) -#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE -#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH -#else -#define OB_BOOT_ENTRY_FORCED_NONE OB_BOOT_LOCK_DISABLE -#define OB_BOOT_ENTRY_FORCED_FLASH OB_BOOT_LOCK_ENABLE -#endif -#if defined(STM32H7) -#define FLASH_FLAG_SNECCE_BANK1RR FLASH_FLAG_SNECCERR_BANK1 -#define FLASH_FLAG_DBECCE_BANK1RR FLASH_FLAG_DBECCERR_BANK1 -#define FLASH_FLAG_STRBER_BANK1R FLASH_FLAG_STRBERR_BANK1 -#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 -#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 -#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 -#define FLASH_FLAG_WDW FLASH_FLAG_WBNE -#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL -#endif /* STM32H7 */ -#if defined(STM32U5) -#define OB_USER_nRST_STOP OB_USER_NRST_STOP -#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY -#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW -#define OB_USER_nSWBOOT0 OB_USER_NSWBOOT0 -#define OB_USER_nBOOT0 OB_USER_NBOOT0 -#define OB_nBOOT0_RESET OB_NBOOT0_RESET -#define OB_nBOOT0_SET OB_NBOOT0_SET -#define OB_USER_SRAM134_RST OB_USER_SRAM_RST -#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE -#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE -#endif /* STM32U5 */ -#if defined(STM32U0) -#define OB_USER_nRST_STOP OB_USER_NRST_STOP -#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY -#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW -#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL -#define OB_USER_nBOOT0 OB_USER_NBOOT0 -#define OB_USER_nBOOT1 OB_USER_NBOOT1 -#define OB_nBOOT0_RESET OB_NBOOT0_RESET -#define OB_nBOOT0_SET OB_NBOOT0_SET -#endif /* STM32U0 */ - -/** - * @} - */ - -/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose - * @{ - */ - -#if defined(STM32H7) -#define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE -#define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE -#define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET -#define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose - * @{ - */ - -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 I2C_FASTMODEPLUS_PB7 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 I2C_FASTMODEPLUS_PB8 -#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 I2C_FASTMODEPLUS_PB9 -#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 -#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 -#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 -#if defined(STM32G4) - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster -#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD -#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD -#endif /* STM32G4 */ - -#if defined(STM32H5) -#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC -#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC -#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC -#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC -#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC -#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC - -#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC -#define SYSCFG_BREAK_PVD SBS_BREAK_PVD -#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC -#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP - -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 -#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 -#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 - -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE - -#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 -#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 -#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 -#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 - -#define SYSCFG_ETH_MII SBS_ETH_MII -#define SYSCFG_ETH_RMII SBS_ETH_RMII -#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG - -#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE -#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR -#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG - -#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG - -#define SYSCFG_MPU_NSEC SBS_MPU_NSEC -#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SYSCFG_SAU SBS_SAU -#define SYSCFG_MPU_SEC SBS_MPU_SEC -#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC -#define SYSCFG_LOCK_ALL SBS_LOCK_ALL -#else -#define SYSCFG_LOCK_ALL SBS_LOCK_ALL -#endif /* __ARM_FEATURE_CMSE */ - -#define SYSCFG_CLK SBS_CLK -#define SYSCFG_CLASSB SBS_CLASSB -#define SYSCFG_FPU SBS_FPU -#define SYSCFG_ALL SBS_ALL - -#define SYSCFG_SEC SBS_SEC -#define SYSCFG_NSEC SBS_NSEC - -#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE -#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE - -#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK -#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK -#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK - -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE - -#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS -#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS - -#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT -#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG -#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE -#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE -#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING -#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS -#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES -#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES -#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS - -#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig -#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig -#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig -#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF -#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF - -#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster -#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster -#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect - -#define HAL_SYSCFG_Lock HAL_SBS_Lock -#define HAL_SYSCFG_GetLock HAL_SBS_GetLock - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes -#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes -#endif /* __ARM_FEATURE_CMSE */ - -#endif /* STM32H5 */ - - -/** - * @} - */ - - -/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose - * @{ - */ -#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4) -#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE -#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE -#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 -#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 FMC_NAND_MEM_BUS_WIDTH_16 -#elif defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) -#define FMC_NAND_WAIT_FEATURE_DISABLE FMC_NAND_PCC_WAIT_FEATURE_DISABLE -#define FMC_NAND_WAIT_FEATURE_ENABLE FMC_NAND_PCC_WAIT_FEATURE_ENABLE -#define FMC_NAND_MEM_BUS_WIDTH_8 FMC_NAND_PCC_MEM_BUS_WIDTH_8 -#define FMC_NAND_MEM_BUS_WIDTH_16 FMC_NAND_PCC_MEM_BUS_WIDTH_16 -#endif -/** - * @} - */ - -/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef -#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef -/** - * @} - */ - -/** @defgroup HAL_GPIO_Aliased_Macros HAL GPIO Aliased Macros maintained for legacy purpose - * @{ - */ -#define GET_GPIO_SOURCE GPIO_GET_INDEX -#define GET_GPIO_INDEX GPIO_GET_INDEX - -#if defined(STM32F4) -#define GPIO_AF12_SDMMC GPIO_AF12_SDIO -#define GPIO_AF12_SDMMC1 GPIO_AF12_SDIO -#endif - -#if defined(STM32F7) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32L4) -#define GPIO_AF12_SDIO GPIO_AF12_SDMMC1 -#define GPIO_AF12_SDMMC GPIO_AF12_SDMMC1 -#endif - -#if defined(STM32H7) -#define GPIO_AF7_SDIO1 GPIO_AF7_SDMMC1 -#define GPIO_AF8_SDIO1 GPIO_AF8_SDMMC1 -#define GPIO_AF12_SDIO1 GPIO_AF12_SDMMC1 -#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 -#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 -#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 - -#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) || \ - defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx) -#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS -#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS -#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ - STM32H757xx */ -#endif /* STM32H7 */ - -#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 -#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 -#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 - -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ - defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7 || STM32WB || STM32U5*/ - -#if defined(STM32L1) -#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH -#endif /* STM32L1 */ - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1) -#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW -#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM -#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH -#endif /* STM32F0 || STM32F3 || STM32F1 */ - -#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 - -#if defined(STM32U5) || defined(STM32H5) -#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ -#endif /* STM32U5 || STM32H5 */ -#if defined(STM32U5) -#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP -#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_GTZC_Aliased_Defines HAL GTZC Aliased Defines maintained for legacy purpose - * @{ - */ -#if defined(STM32U5) -#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI -#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB -#endif /* STM32U5 */ -#if defined(STM32H5) -#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 -#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC -#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB -#endif /* STM32H5 */ -#if defined(STM32H5) || defined(STM32U5) -#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX -#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX -#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED -#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED -#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC -#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC -#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV -#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV -#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF -#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON -#endif /* STM32H5 || STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define HRTIM_TIMDELAYEDPROTECTION_DISABLED HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV68 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT1_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 -#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 -#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 - -#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER -#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER -#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD -#define __HAL_HRTIM_GetPeriod __HAL_HRTIM_GETPERIOD -#define __HAL_HRTIM_SetClockPrescaler __HAL_HRTIM_SETCLOCKPRESCALER -#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER -#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE -#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE - -#if defined(STM32G4) -#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig -#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable -#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable -#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset -#define HRTIM_TIMEEVENT_A HRTIM_EVENTCOUNTER_A -#define HRTIM_TIMEEVENT_B HRTIM_EVENTCOUNTER_B -#define HRTIM_TIMEEVENTRESETMODE_UNCONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_UNCONDITIONAL -#define HRTIM_TIMEEVENTRESETMODE_CONDITIONAL HRTIM_EVENTCOUNTER_RSTMODE_CONDITIONAL -#endif /* STM32G4 */ - -#if defined(STM32H7) -#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 - -#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9 -#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1 -#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2 -#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3 -#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4 -#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5 -#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6 -#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7 -#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8 -#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9 -#endif /* STM32H7 */ - -#if defined(STM32F3) -/** @brief Constants defining available sources associated to external events. - */ -#define HRTIM_EVENTSRC_1 (0x00000000U) -#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0) -#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1) -#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) - -/** @brief Constants defining the DLL calibration periods (in micro seconds) - */ -#define HRTIM_CALIBRATIONRATE_7300 0x00000000U -#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) -#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) -#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - -#endif /* STM32F3 */ -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Defines HAL I2C Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2C_DUALADDRESS_DISABLED I2C_DUALADDRESS_DISABLE -#define I2C_DUALADDRESS_ENABLED I2C_DUALADDRESS_ENABLE -#define I2C_GENERALCALL_DISABLED I2C_GENERALCALL_DISABLE -#define I2C_GENERALCALL_ENABLED I2C_GENERALCALL_ENABLE -#define I2C_NOSTRETCH_DISABLED I2C_NOSTRETCH_DISABLE -#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE -#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE -#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ - defined(STM32L1) || defined(STM32F7) -#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX -#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX -#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX -#endif -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Defines HAL IRDA Aliased Defines maintained for legacy purpose - * @{ - */ -#define IRDA_ONE_BIT_SAMPLE_DISABLED IRDA_ONE_BIT_SAMPLE_DISABLE -#define IRDA_ONE_BIT_SAMPLE_ENABLED IRDA_ONE_BIT_SAMPLE_ENABLE - -/** - * @} - */ - -/** @defgroup HAL_IWDG_Aliased_Defines HAL IWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define KR_KEY_RELOAD IWDG_KEY_RELOAD -#define KR_KEY_ENABLE IWDG_KEY_ENABLE -#define KR_KEY_EWA IWDG_KEY_WRITE_ACCESS_ENABLE -#define KR_KEY_DWA IWDG_KEY_WRITE_ACCESS_DISABLE -/** - * @} - */ - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ - -#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSISTION LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION -#define LPTIM_CLOCKSAMPLETIME_2TRANSISTIONS LPTIM_CLOCKSAMPLETIME_2TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_4TRANSISTIONS LPTIM_CLOCKSAMPLETIME_4TRANSITIONS -#define LPTIM_CLOCKSAMPLETIME_8TRANSISTIONS LPTIM_CLOCKSAMPLETIME_8TRANSITIONS - -#define LPTIM_CLOCKPOLARITY_RISINGEDGE LPTIM_CLOCKPOLARITY_RISING -#define LPTIM_CLOCKPOLARITY_FALLINGEDGE LPTIM_CLOCKPOLARITY_FALLING -#define LPTIM_CLOCKPOLARITY_BOTHEDGES LPTIM_CLOCKPOLARITY_RISING_FALLING - -#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION -#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS - -/* The following 3 definition have also been present in a temporary version of lptim.h */ -/* They need to be renamed also to the right name, just in case */ -#define LPTIM_TRIGSAMPLETIME_2TRANSITION LPTIM_TRIGSAMPLETIME_2TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS -#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS - - -/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue -/** - * @} - */ - -#if defined(STM32U5) -#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF -#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF -#define LPTIM_CHANNEL_ALL 0x00000000U -#endif /* STM32U5 */ -/** - * @} - */ - -/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b -#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b -#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b -#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b - -#define NAND_AddressTypedef NAND_AddressTypeDef - -#define __ARRAY_ADDRESS ARRAY_ADDRESS -#define __ADDR_1st_CYCLE ADDR_1ST_CYCLE -#define __ADDR_2nd_CYCLE ADDR_2ND_CYCLE -#define __ADDR_3rd_CYCLE ADDR_3RD_CYCLE -#define __ADDR_4th_CYCLE ADDR_4TH_CYCLE -/** - * @} - */ - -/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose - * @{ - */ -#define NOR_StatusTypedef HAL_NOR_StatusTypeDef -#define NOR_SUCCESS HAL_NOR_STATUS_SUCCESS -#define NOR_ONGOING HAL_NOR_STATUS_ONGOING -#define NOR_ERROR HAL_NOR_STATUS_ERROR -#define NOR_TIMEOUT HAL_NOR_STATUS_TIMEOUT - -#define __NOR_WRITE NOR_WRITE -#define __NOR_ADDR_SHIFT NOR_ADDR_SHIFT -/** - * @} - */ - -/** @defgroup HAL_OPAMP_Aliased_Defines HAL OPAMP Aliased Defines maintained for legacy purpose - * @{ - */ - -#define OPAMP_NONINVERTINGINPUT_VP0 OPAMP_NONINVERTINGINPUT_IO0 -#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1 -#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2 -#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3 - -#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0 -#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1 -#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2 -#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3 - -#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define IOPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0 -#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1 - -#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0 -#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1 - -#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO -#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 -#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 - -#if defined(STM32L1) || defined(STM32L4) || defined(STM32L5) || defined(STM32H7) || defined(STM32G4) || defined(STM32U5) -#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID -#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID -#endif - -#if defined(STM32L4) || defined(STM32L5) -#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALPOWER -#elif defined(STM32G4) -#define OPAMP_POWERMODE_NORMAL OPAMP_POWERMODE_NORMALSPEED -#endif - -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Defines HAL I2S Aliased Defines maintained for legacy purpose - * @{ - */ -#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS - -#if defined(STM32H7) -#define I2S_IT_TXE I2S_IT_TXP -#define I2S_IT_RXNE I2S_IT_RXP - -#define I2S_FLAG_TXE I2S_FLAG_TXP -#define I2S_FLAG_RXNE I2S_FLAG_RXP -#endif - -#if defined(STM32F7) -#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL -#endif -/** - * @} - */ - -/** @defgroup HAL_PCCARD_Aliased_Defines HAL PCCARD Aliased Defines maintained for legacy purpose - * @{ - */ - -/* Compact Flash-ATA registers description */ -#define CF_DATA ATA_DATA -#define CF_SECTOR_COUNT ATA_SECTOR_COUNT -#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER -#define CF_CYLINDER_LOW ATA_CYLINDER_LOW -#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH -#define CF_CARD_HEAD ATA_CARD_HEAD -#define CF_STATUS_CMD ATA_STATUS_CMD -#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE -#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA - -/* Compact Flash-ATA commands */ -#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD -#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD -#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD -#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD - -#define PCCARD_StatusTypedef HAL_PCCARD_StatusTypeDef -#define PCCARD_SUCCESS HAL_PCCARD_STATUS_SUCCESS -#define PCCARD_ONGOING HAL_PCCARD_STATUS_ONGOING -#define PCCARD_ERROR HAL_PCCARD_STATUS_ERROR -#define PCCARD_TIMEOUT HAL_PCCARD_STATUS_TIMEOUT -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose - * @{ - */ - -#define FORMAT_BIN RTC_FORMAT_BIN -#define FORMAT_BCD RTC_FORMAT_BCD - -#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE -#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE -#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE - -#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE -#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE -#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE -#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT -#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT - -#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT -#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1 -#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2 - -#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE -#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1 -#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1 - -#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT -#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 -#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 - -#if defined(STM32H5) || defined(STM32H7RS) -#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE -#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 || STM32H7RS */ - -#if defined(STM32WBA) -#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE -#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 -#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK -#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE -#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH -#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM -#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL -#endif /* STM32WBA */ - -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) -#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE -#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA || STM32H7RS */ - -#if defined(STM32F7) -#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK -#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ - -#if defined(STM32H7) -#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X -#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT -#endif /* STM32H7 */ - -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) -#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 -#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 -#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 -#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ - -/** - * @} - */ - - -/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMARTCARD_NACK_ENABLED SMARTCARD_NACK_ENABLE -#define SMARTCARD_NACK_DISABLED SMARTCARD_NACK_DISABLE - -#define SMARTCARD_ONEBIT_SAMPLING_DISABLED SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLED SMARTCARD_ONE_BIT_SAMPLE_ENABLE -#define SMARTCARD_ONEBIT_SAMPLING_DISABLE SMARTCARD_ONE_BIT_SAMPLE_DISABLE -#define SMARTCARD_ONEBIT_SAMPLING_ENABLE SMARTCARD_ONE_BIT_SAMPLE_ENABLE - -#define SMARTCARD_TIMEOUT_DISABLED SMARTCARD_TIMEOUT_DISABLE -#define SMARTCARD_TIMEOUT_ENABLED SMARTCARD_TIMEOUT_ENABLE - -#define SMARTCARD_LASTBIT_DISABLED SMARTCARD_LASTBIT_DISABLE -#define SMARTCARD_LASTBIT_ENABLED SMARTCARD_LASTBIT_ENABLE -/** - * @} - */ - - -/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose - * @{ - */ -#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE -#define SMBUS_DUALADDRESS_ENABLED SMBUS_DUALADDRESS_ENABLE -#define SMBUS_GENERALCALL_DISABLED SMBUS_GENERALCALL_DISABLE -#define SMBUS_GENERALCALL_ENABLED SMBUS_GENERALCALL_ENABLE -#define SMBUS_NOSTRETCH_DISABLED SMBUS_NOSTRETCH_DISABLE -#define SMBUS_NOSTRETCH_ENABLED SMBUS_NOSTRETCH_ENABLE -#define SMBUS_ANALOGFILTER_ENABLED SMBUS_ANALOGFILTER_ENABLE -#define SMBUS_ANALOGFILTER_DISABLED SMBUS_ANALOGFILTER_DISABLE -#define SMBUS_PEC_DISABLED SMBUS_PEC_DISABLE -#define SMBUS_PEC_ENABLED SMBUS_PEC_ENABLE -#define HAL_SMBUS_STATE_SLAVE_LISTEN HAL_SMBUS_STATE_LISTEN -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose - * @{ - */ -#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE -#define SPI_TIMODE_ENABLED SPI_TIMODE_ENABLE - -#define SPI_CRCCALCULATION_DISABLED SPI_CRCCALCULATION_DISABLE -#define SPI_CRCCALCULATION_ENABLED SPI_CRCCALCULATION_ENABLE - -#define SPI_NSS_PULSE_DISABLED SPI_NSS_PULSE_DISABLE -#define SPI_NSS_PULSE_ENABLED SPI_NSS_PULSE_ENABLE - -#if defined(STM32H7) - -#define SPI_FLAG_TXE SPI_FLAG_TXP -#define SPI_FLAG_RXNE SPI_FLAG_RXP - -#define SPI_IT_TXE SPI_IT_TXP -#define SPI_IT_RXNE SPI_IT_RXP - -#define SPI_FRLVL_EMPTY SPI_RX_FIFO_0PACKET -#define SPI_FRLVL_QUARTER_FULL SPI_RX_FIFO_1PACKET -#define SPI_FRLVL_HALF_FULL SPI_RX_FIFO_2PACKET -#define SPI_FRLVL_FULL SPI_RX_FIFO_3PACKET - -#endif /* STM32H7 */ - -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose - * @{ - */ -#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK -#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK - -#define TIM_DMABase_CR1 TIM_DMABASE_CR1 -#define TIM_DMABase_CR2 TIM_DMABASE_CR2 -#define TIM_DMABase_SMCR TIM_DMABASE_SMCR -#define TIM_DMABase_DIER TIM_DMABASE_DIER -#define TIM_DMABase_SR TIM_DMABASE_SR -#define TIM_DMABase_EGR TIM_DMABASE_EGR -#define TIM_DMABase_CCMR1 TIM_DMABASE_CCMR1 -#define TIM_DMABase_CCMR2 TIM_DMABASE_CCMR2 -#define TIM_DMABase_CCER TIM_DMABASE_CCER -#define TIM_DMABase_CNT TIM_DMABASE_CNT -#define TIM_DMABase_PSC TIM_DMABASE_PSC -#define TIM_DMABase_ARR TIM_DMABASE_ARR -#define TIM_DMABase_RCR TIM_DMABASE_RCR -#define TIM_DMABase_CCR1 TIM_DMABASE_CCR1 -#define TIM_DMABase_CCR2 TIM_DMABASE_CCR2 -#define TIM_DMABase_CCR3 TIM_DMABASE_CCR3 -#define TIM_DMABase_CCR4 TIM_DMABASE_CCR4 -#define TIM_DMABase_BDTR TIM_DMABASE_BDTR -#define TIM_DMABase_DCR TIM_DMABASE_DCR -#define TIM_DMABase_DMAR TIM_DMABASE_DMAR -#define TIM_DMABase_OR1 TIM_DMABASE_OR1 -#define TIM_DMABase_CCMR3 TIM_DMABASE_CCMR3 -#define TIM_DMABase_CCR5 TIM_DMABASE_CCR5 -#define TIM_DMABase_CCR6 TIM_DMABASE_CCR6 -#define TIM_DMABase_OR2 TIM_DMABASE_OR2 -#define TIM_DMABase_OR3 TIM_DMABASE_OR3 -#define TIM_DMABase_OR TIM_DMABASE_OR - -#define TIM_EventSource_Update TIM_EVENTSOURCE_UPDATE -#define TIM_EventSource_CC1 TIM_EVENTSOURCE_CC1 -#define TIM_EventSource_CC2 TIM_EVENTSOURCE_CC2 -#define TIM_EventSource_CC3 TIM_EVENTSOURCE_CC3 -#define TIM_EventSource_CC4 TIM_EVENTSOURCE_CC4 -#define TIM_EventSource_COM TIM_EVENTSOURCE_COM -#define TIM_EventSource_Trigger TIM_EVENTSOURCE_TRIGGER -#define TIM_EventSource_Break TIM_EVENTSOURCE_BREAK -#define TIM_EventSource_Break2 TIM_EVENTSOURCE_BREAK2 - -#define TIM_DMABurstLength_1Transfer TIM_DMABURSTLENGTH_1TRANSFER -#define TIM_DMABurstLength_2Transfers TIM_DMABURSTLENGTH_2TRANSFERS -#define TIM_DMABurstLength_3Transfers TIM_DMABURSTLENGTH_3TRANSFERS -#define TIM_DMABurstLength_4Transfers TIM_DMABURSTLENGTH_4TRANSFERS -#define TIM_DMABurstLength_5Transfers TIM_DMABURSTLENGTH_5TRANSFERS -#define TIM_DMABurstLength_6Transfers TIM_DMABURSTLENGTH_6TRANSFERS -#define TIM_DMABurstLength_7Transfers TIM_DMABURSTLENGTH_7TRANSFERS -#define TIM_DMABurstLength_8Transfers TIM_DMABURSTLENGTH_8TRANSFERS -#define TIM_DMABurstLength_9Transfers TIM_DMABURSTLENGTH_9TRANSFERS -#define TIM_DMABurstLength_10Transfers TIM_DMABURSTLENGTH_10TRANSFERS -#define TIM_DMABurstLength_11Transfers TIM_DMABURSTLENGTH_11TRANSFERS -#define TIM_DMABurstLength_12Transfers TIM_DMABURSTLENGTH_12TRANSFERS -#define TIM_DMABurstLength_13Transfers TIM_DMABURSTLENGTH_13TRANSFERS -#define TIM_DMABurstLength_14Transfers TIM_DMABURSTLENGTH_14TRANSFERS -#define TIM_DMABurstLength_15Transfers TIM_DMABURSTLENGTH_15TRANSFERS -#define TIM_DMABurstLength_16Transfers TIM_DMABURSTLENGTH_16TRANSFERS -#define TIM_DMABurstLength_17Transfers TIM_DMABURSTLENGTH_17TRANSFERS -#define TIM_DMABurstLength_18Transfers TIM_DMABURSTLENGTH_18TRANSFERS - -#if defined(STM32L0) -#define TIM22_TI1_GPIO1 TIM22_TI1_GPIO -#define TIM22_TI1_GPIO2 TIM22_TI1_GPIO -#endif - -#if defined(STM32F3) -#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE -#endif - -#if defined(STM32H7) -#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1 -#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2 -#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1 -#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2 -#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1 -#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2 -#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1 -#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1 -#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2 -#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1 -#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2 -#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2 -#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1 -#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2 -#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 -#endif - -#if defined(STM32U5) -#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS -#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK -#endif -/** - * @} - */ - -/** @defgroup HAL_TSC_Aliased_Defines HAL TSC Aliased Defines maintained for legacy purpose - * @{ - */ -#define TSC_SYNC_POL_FALL TSC_SYNC_POLARITY_FALLING -#define TSC_SYNC_POL_RISE_HIGH TSC_SYNC_POLARITY_RISING -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Defines HAL UART Aliased Defines maintained for legacy purpose - * @{ - */ -#define UART_ONEBIT_SAMPLING_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONEBIT_SAMPLING_ENABLED UART_ONE_BIT_SAMPLE_ENABLE -#define UART_ONE_BIT_SAMPLE_DISABLED UART_ONE_BIT_SAMPLE_DISABLE -#define UART_ONE_BIT_SAMPLE_ENABLED UART_ONE_BIT_SAMPLE_ENABLE - -#define __HAL_UART_ONEBIT_ENABLE __HAL_UART_ONE_BIT_SAMPLE_ENABLE -#define __HAL_UART_ONEBIT_DISABLE __HAL_UART_ONE_BIT_SAMPLE_DISABLE - -#define __DIV_SAMPLING16 UART_DIV_SAMPLING16 -#define __DIVMANT_SAMPLING16 UART_DIVMANT_SAMPLING16 -#define __DIVFRAQ_SAMPLING16 UART_DIVFRAQ_SAMPLING16 -#define __UART_BRR_SAMPLING16 UART_BRR_SAMPLING16 - -#define __DIV_SAMPLING8 UART_DIV_SAMPLING8 -#define __DIVMANT_SAMPLING8 UART_DIVMANT_SAMPLING8 -#define __DIVFRAQ_SAMPLING8 UART_DIVFRAQ_SAMPLING8 -#define __UART_BRR_SAMPLING8 UART_BRR_SAMPLING8 - -#define __DIV_LPUART UART_DIV_LPUART - -#define UART_WAKEUPMETHODE_IDLELINE UART_WAKEUPMETHOD_IDLELINE -#define UART_WAKEUPMETHODE_ADDRESSMARK UART_WAKEUPMETHOD_ADDRESSMARK - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose - * @{ - */ - -#define USART_CLOCK_DISABLED USART_CLOCK_DISABLE -#define USART_CLOCK_ENABLED USART_CLOCK_ENABLE - -#define USARTNACK_ENABLED USART_NACK_ENABLE -#define USARTNACK_DISABLED USART_NACK_DISABLE -/** - * @} - */ - -/** @defgroup HAL_WWDG_Aliased_Defines HAL WWDG Aliased Defines maintained for legacy purpose - * @{ - */ -#define CFR_BASE WWDG_CFR_BASE - -/** - * @} - */ - -/** @defgroup HAL_CAN_Aliased_Defines HAL CAN Aliased Defines maintained for legacy purpose - * @{ - */ -#define CAN_FilterFIFO0 CAN_FILTER_FIFO0 -#define CAN_FilterFIFO1 CAN_FILTER_FIFO1 -#define CAN_IT_RQCP0 CAN_IT_TME -#define CAN_IT_RQCP1 CAN_IT_TME -#define CAN_IT_RQCP2 CAN_IT_TME -#define INAK_TIMEOUT CAN_TIMEOUT_VALUE -#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE -#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U) -#define CAN_TXSTATUS_OK ((uint8_t)0x01U) -#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U) - -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose - * @{ - */ - -#define VLAN_TAG ETH_VLAN_TAG -#define MIN_ETH_PAYLOAD ETH_MIN_ETH_PAYLOAD -#define MAX_ETH_PAYLOAD ETH_MAX_ETH_PAYLOAD -#define JUMBO_FRAME_PAYLOAD ETH_JUMBO_FRAME_PAYLOAD -#define MACMIIAR_CR_MASK ETH_MACMIIAR_CR_MASK -#define MACCR_CLEAR_MASK ETH_MACCR_CLEAR_MASK -#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK -#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK - -#define ETH_MMCCR 0x00000100U -#define ETH_MMCRIR 0x00000104U -#define ETH_MMCTIR 0x00000108U -#define ETH_MMCRIMR 0x0000010CU -#define ETH_MMCTIMR 0x00000110U -#define ETH_MMCTGFSCCR 0x0000014CU -#define ETH_MMCTGFMSCCR 0x00000150U -#define ETH_MMCTGFCR 0x00000168U -#define ETH_MMCRFCECR 0x00000194U -#define ETH_MMCRFAECR 0x00000198U -#define ETH_MMCRGUFCR 0x000001C4U - -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to - the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from - MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus - or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status - of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and - transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input - frame for transmission */ -#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ -#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control - de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control - activate threshold */ -#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ -#if defined(STM32F1) -#else -#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ -#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status - (or time-stamp) */ -#endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and - status */ -#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ -#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ -#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE 0x00000004U /* MAC small FIFO write controller active */ -#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ -#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ - -#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ - -/** - * @} - */ - -/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose - * @{ - */ -#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR -#define DCMI_IT_OVF DCMI_IT_OVR -#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI -#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI - -#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop -#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop -#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop - -/** - * @} - */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) -/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose - * @{ - */ -#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888 -#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888 -#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565 -#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555 -#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444 - -#define CM_ARGB8888 DMA2D_INPUT_ARGB8888 -#define CM_RGB888 DMA2D_INPUT_RGB888 -#define CM_RGB565 DMA2D_INPUT_RGB565 -#define CM_ARGB1555 DMA2D_INPUT_ARGB1555 -#define CM_ARGB4444 DMA2D_INPUT_ARGB4444 -#define CM_L8 DMA2D_INPUT_L8 -#define CM_AL44 DMA2D_INPUT_AL44 -#define CM_AL88 DMA2D_INPUT_AL88 -#define CM_L4 DMA2D_INPUT_L4 -#define CM_A8 DMA2D_INPUT_A8 -#define CM_A4 DMA2D_INPUT_A4 -/** - * @} - */ -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 */ - -#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) \ - || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) \ - || defined(STM32H7) || defined(STM32U5) -/** @defgroup DMA2D_Aliases DMA2D API Aliases - * @{ - */ -#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort - for compatibility with legacy code */ -/** - * @} - */ - -#endif /* STM32L4 || STM32F7 || STM32F4 || STM32H7 || STM32U5 */ - -/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_CRYP_Aliased_Functions HAL CRYP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback -/** - * @} - */ - -/** @defgroup HAL_DCACHE_Aliased_Functions HAL DCACHE Aliased Functions maintained for legacy purpose - * @{ - */ - -#if defined(STM32U5) -#define HAL_DCACHE_CleanInvalidateByAddr HAL_DCACHE_CleanInvalidByAddr -#define HAL_DCACHE_CleanInvalidateByAddr_IT HAL_DCACHE_CleanInvalidByAddr_IT -#endif /* STM32U5 */ - -/** - * @} - */ - -#if !defined(STM32F2) -/** @defgroup HASH_alias HASH API alias - * @{ - */ -#define HAL_HASHEx_IRQHandler HAL_HASH_IRQHandler /*!< Redirection for compatibility with legacy code */ -/** - * - * @} - */ -#endif /* STM32F2 */ -/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef -#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef -#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish -#define HAL_HMAC_SHA1_Finish HAL_HASH_SHA1_Finish -#define HAL_HMAC_SHA224_Finish HAL_HASH_SHA224_Finish -#define HAL_HMAC_SHA256_Finish HAL_HASH_SHA256_Finish - -/*HASH Algorithm Selection*/ - -#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1 -#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224 -#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256 -#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5 - -#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH -#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC - -#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY -#define HASH_HMACKeyType_LongKey HASH_HMAC_KEYTYPE_LONGKEY - -#if defined(STM32L4) || defined(STM32L5) || defined(STM32F2) || defined(STM32F4) || defined(STM32F7) || defined(STM32H7) - -#define HAL_HASH_MD5_Accumulate HAL_HASH_MD5_Accmlt -#define HAL_HASH_MD5_Accumulate_End HAL_HASH_MD5_Accmlt_End -#define HAL_HASH_MD5_Accumulate_IT HAL_HASH_MD5_Accmlt_IT -#define HAL_HASH_MD5_Accumulate_End_IT HAL_HASH_MD5_Accmlt_End_IT - -#define HAL_HASH_SHA1_Accumulate HAL_HASH_SHA1_Accmlt -#define HAL_HASH_SHA1_Accumulate_End HAL_HASH_SHA1_Accmlt_End -#define HAL_HASH_SHA1_Accumulate_IT HAL_HASH_SHA1_Accmlt_IT -#define HAL_HASH_SHA1_Accumulate_End_IT HAL_HASH_SHA1_Accmlt_End_IT - -#define HAL_HASHEx_SHA224_Accumulate HAL_HASHEx_SHA224_Accmlt -#define HAL_HASHEx_SHA224_Accumulate_End HAL_HASHEx_SHA224_Accmlt_End -#define HAL_HASHEx_SHA224_Accumulate_IT HAL_HASHEx_SHA224_Accmlt_IT -#define HAL_HASHEx_SHA224_Accumulate_End_IT HAL_HASHEx_SHA224_Accmlt_End_IT - -#define HAL_HASHEx_SHA256_Accumulate HAL_HASHEx_SHA256_Accmlt -#define HAL_HASHEx_SHA256_Accumulate_End HAL_HASHEx_SHA256_Accmlt_End -#define HAL_HASHEx_SHA256_Accumulate_IT HAL_HASHEx_SHA256_Accmlt_IT -#define HAL_HASHEx_SHA256_Accumulate_End_IT HAL_HASHEx_SHA256_Accmlt_End_IT - -#endif /* STM32L4 || STM32L5 || STM32F2 || STM32F4 || STM32F7 || STM32H7 */ -/** - * @} - */ - -/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_EnableDBGSleepMode HAL_DBGMCU_EnableDBGSleepMode -#define HAL_DisableDBGSleepMode HAL_DBGMCU_DisableDBGSleepMode -#define HAL_EnableDBGStopMode HAL_DBGMCU_EnableDBGStopMode -#define HAL_DisableDBGStopMode HAL_DBGMCU_DisableDBGStopMode -#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode -#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode -#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ - HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) -#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect -#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) -#if defined(STM32L0) -#else -#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT()) -#endif -#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) -#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ - HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ - defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) -#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode -#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode -#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode -#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode -#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */ - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Functions HAL FLASH Aliased Functions maintained for legacy purpose - * @{ - */ -#define FLASH_HalfPageProgram HAL_FLASHEx_HalfPageProgram -#define FLASH_EnableRunPowerDown HAL_FLASHEx_EnableRunPowerDown -#define FLASH_DisableRunPowerDown HAL_FLASHEx_DisableRunPowerDown -#define HAL_DATA_EEPROMEx_Unlock HAL_FLASHEx_DATAEEPROM_Unlock -#define HAL_DATA_EEPROMEx_Lock HAL_FLASHEx_DATAEEPROM_Lock -#define HAL_DATA_EEPROMEx_Erase HAL_FLASHEx_DATAEEPROM_Erase -#define HAL_DATA_EEPROMEx_Program HAL_FLASHEx_DATAEEPROM_Program - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter -#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter -#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter -#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter - -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ - HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ - HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) - -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ - defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ - defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT -#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT -#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT -#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || - STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ - defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) -#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA -#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA -#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA -#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ - -#if defined(STM32F4) -#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT -#define HAL_FMPI2C_Master_Sequential_Receive_IT HAL_FMPI2C_Master_Seq_Receive_IT -#define HAL_FMPI2C_Slave_Sequential_Transmit_IT HAL_FMPI2C_Slave_Seq_Transmit_IT -#define HAL_FMPI2C_Slave_Sequential_Receive_IT HAL_FMPI2C_Slave_Seq_Receive_IT -#define HAL_FMPI2C_Master_Sequential_Transmit_DMA HAL_FMPI2C_Master_Seq_Transmit_DMA -#define HAL_FMPI2C_Master_Sequential_Receive_DMA HAL_FMPI2C_Master_Seq_Receive_DMA -#define HAL_FMPI2C_Slave_Sequential_Transmit_DMA HAL_FMPI2C_Slave_Seq_Transmit_DMA -#define HAL_FMPI2C_Slave_Sequential_Receive_DMA HAL_FMPI2C_Slave_Seq_Receive_DMA -#endif /* STM32F4 */ -/** - * @} - */ - -/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose - * @{ - */ - -#if defined(STM32G0) -#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD -#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD -#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD -#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler -#endif -#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD -#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg -#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown -#define HAL_PWR_DisableVddio2Monitor HAL_PWREx_DisableVddio2Monitor -#define HAL_PWR_EnableBkUpReg HAL_PWREx_EnableBkUpReg -#define HAL_PWR_EnableFlashPowerDown HAL_PWREx_EnableFlashPowerDown -#define HAL_PWR_EnableVddio2Monitor HAL_PWREx_EnableVddio2Monitor -#define HAL_PWR_PVD_PVM_IRQHandler HAL_PWREx_PVD_PVM_IRQHandler -#define HAL_PWR_PVDLevelConfig HAL_PWR_ConfigPVD -#define HAL_PWR_Vddio2Monitor_IRQHandler HAL_PWREx_Vddio2Monitor_IRQHandler -#define HAL_PWR_Vddio2MonitorCallback HAL_PWREx_Vddio2MonitorCallback -#define HAL_PWREx_ActivateOverDrive HAL_PWREx_EnableOverDrive -#define HAL_PWREx_DeactivateOverDrive HAL_PWREx_DisableOverDrive -#define HAL_PWREx_DisableSDADCAnalog HAL_PWREx_DisableSDADC -#define HAL_PWREx_EnableSDADCAnalog HAL_PWREx_EnableSDADC -#define HAL_PWREx_PVMConfig HAL_PWREx_ConfigPVM - -#define PWR_MODE_NORMAL PWR_PVD_MODE_NORMAL -#define PWR_MODE_IT_RISING PWR_PVD_MODE_IT_RISING -#define PWR_MODE_IT_FALLING PWR_PVD_MODE_IT_FALLING -#define PWR_MODE_IT_RISING_FALLING PWR_PVD_MODE_IT_RISING_FALLING -#define PWR_MODE_EVENT_RISING PWR_PVD_MODE_EVENT_RISING -#define PWR_MODE_EVENT_FALLING PWR_PVD_MODE_EVENT_FALLING -#define PWR_MODE_EVENT_RISING_FALLING PWR_PVD_MODE_EVENT_RISING_FALLING - -#define CR_OFFSET_BB PWR_CR_OFFSET_BB -#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB -#define PMODE_BIT_NUMBER VOS_BIT_NUMBER -#define CR_PMODE_BB CR_VOS_BB - -#define DBP_BitNumber DBP_BIT_NUMBER -#define PVDE_BitNumber PVDE_BIT_NUMBER -#define PMODE_BitNumber PMODE_BIT_NUMBER -#define EWUP_BitNumber EWUP_BIT_NUMBER -#define FPDS_BitNumber FPDS_BIT_NUMBER -#define ODEN_BitNumber ODEN_BIT_NUMBER -#define ODSWEN_BitNumber ODSWEN_BIT_NUMBER -#define MRLVDS_BitNumber MRLVDS_BIT_NUMBER -#define LPLVDS_BitNumber LPLVDS_BIT_NUMBER -#define BRE_BitNumber BRE_BIT_NUMBER - -#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL - -#if defined (STM32U5) -#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP -#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP -#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP -#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP -#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP -#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP -#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP -#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP -#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP -#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP -#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP -#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP -#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP - -#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP -#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP -#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP - -#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP -#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP -#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP -#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP -#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP -#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP -#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP -#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP -#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP -#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP -#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP -#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP -#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP -#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP - -#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP - -#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP -#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP -#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP -#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP -#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP -#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP -#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP -#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP -#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP -#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP -#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP -#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP -#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP -#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP - -#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP -#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP -#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP -#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP -#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP -#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP -#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP -#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP -#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP - - -#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP -#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP -#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP -#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP -#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP -#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP -#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP -#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP -#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP - - -#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY -#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY -#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY - -#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN -#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN -#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN -#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN -#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN -#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN - -#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK -#endif - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose - * @{ - */ -#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) -#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey -#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock -#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock -#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA || STM32H7RS */ - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT -#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback -#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Functions HAL SPI Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_TIM_DMADelayPulseCplt TIM_DMADelayPulseCplt -#define HAL_TIM_DMAError TIM_DMAError -#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt -#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ - defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) -#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro -#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT -#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback -#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent -#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT -#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA -#endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */ -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback -#define HAL_LTDC_Relaod HAL_LTDC_Reload -#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig -#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig -/** - * @} - */ - - -/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -/* Exported macros ------------------------------------------------------------*/ - -/** @defgroup HAL_AES_Aliased_Macros HAL CRYP Aliased Macros maintained for legacy purpose - * @{ - */ -#define AES_IT_CC CRYP_IT_CC -#define AES_IT_ERR CRYP_IT_ERR -#define AES_FLAG_CCF CRYP_FLAG_CCF -/** - * @} - */ - -/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_GET_BOOT_MODE __HAL_SYSCFG_GET_BOOT_MODE -#define __HAL_REMAPMEMORY_FLASH __HAL_SYSCFG_REMAPMEMORY_FLASH -#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH -#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM -#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC -#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM -#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC -#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI -#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK -#define __HAL_GET_FLAG __HAL_SYSCFG_GET_FLAG -#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG -#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE -#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE -#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE - -#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY -#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48 -#define IS_SYSCFG_FASTMODEPLUS_CONFIG IS_I2C_FASTMODEPLUS -#define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER -#define CMP_PD_BitNumber CMP_PD_BIT_NUMBER - -/** - * @} - */ - - -/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __ADC_ENABLE __HAL_ADC_ENABLE -#define __ADC_DISABLE __HAL_ADC_DISABLE -#define __HAL_ADC_ENABLING_CONDITIONS ADC_ENABLING_CONDITIONS -#define __HAL_ADC_DISABLING_CONDITIONS ADC_DISABLING_CONDITIONS -#define __HAL_ADC_IS_ENABLED ADC_IS_ENABLE -#define __ADC_IS_ENABLED ADC_IS_ENABLE -#define __HAL_ADC_IS_SOFTWARE_START_REGULAR ADC_IS_SOFTWARE_START_REGULAR -#define __HAL_ADC_IS_SOFTWARE_START_INJECTED ADC_IS_SOFTWARE_START_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING_REGULAR ADC_IS_CONVERSION_ONGOING_REGULAR -#define __HAL_ADC_IS_CONVERSION_ONGOING_INJECTED ADC_IS_CONVERSION_ONGOING_INJECTED -#define __HAL_ADC_IS_CONVERSION_ONGOING ADC_IS_CONVERSION_ONGOING -#define __HAL_ADC_CLEAR_ERRORCODE ADC_CLEAR_ERRORCODE - -#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION -#define __HAL_ADC_JSQR_RK ADC_JSQR_RK -#define __HAL_ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_SHIFT -#define __HAL_ADC_CFGR_AWD23CR ADC_CFGR_AWD23CR -#define __HAL_ADC_CFGR_INJECT_AUTO_CONVERSION ADC_CFGR_INJECT_AUTO_CONVERSION -#define __HAL_ADC_CFGR_INJECT_CONTEXT_QUEUE ADC_CFGR_INJECT_CONTEXT_QUEUE -#define __HAL_ADC_CFGR_INJECT_DISCCONTINUOUS ADC_CFGR_INJECT_DISCCONTINUOUS -#define __HAL_ADC_CFGR_REG_DISCCONTINUOUS ADC_CFGR_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR_DISCONTINUOUS_NUM ADC_CFGR_DISCONTINUOUS_NUM -#define __HAL_ADC_CFGR_AUTOWAIT ADC_CFGR_AUTOWAIT -#define __HAL_ADC_CFGR_CONTINUOUS ADC_CFGR_CONTINUOUS -#define __HAL_ADC_CFGR_OVERRUN ADC_CFGR_OVERRUN -#define __HAL_ADC_CFGR_DMACONTREQ ADC_CFGR_DMACONTREQ -#define __HAL_ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_SET -#define __HAL_ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_SET -#define __HAL_ADC_OFR_CHANNEL ADC_OFR_CHANNEL -#define __HAL_ADC_DIFSEL_CHANNEL ADC_DIFSEL_CHANNEL -#define __HAL_ADC_CALFACT_DIFF_SET ADC_CALFACT_DIFF_SET -#define __HAL_ADC_CALFACT_DIFF_GET ADC_CALFACT_DIFF_GET -#define __HAL_ADC_TRX_HIGHTHRESHOLD ADC_TRX_HIGHTHRESHOLD - -#define __HAL_ADC_OFFSET_SHIFT_RESOLUTION ADC_OFFSET_SHIFT_RESOLUTION -#define __HAL_ADC_AWD1THRESHOLD_SHIFT_RESOLUTION ADC_AWD1THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_AWD23THRESHOLD_SHIFT_RESOLUTION ADC_AWD23THRESHOLD_SHIFT_RESOLUTION -#define __HAL_ADC_COMMON_REGISTER ADC_COMMON_REGISTER -#define __HAL_ADC_COMMON_CCR_MULTI ADC_COMMON_CCR_MULTI -#define __HAL_ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __ADC_MULTIMODE_IS_ENABLED ADC_MULTIMODE_IS_ENABLE -#define __HAL_ADC_NONMULTIMODE_OR_MULTIMODEMASTER ADC_NONMULTIMODE_OR_MULTIMODEMASTER -#define __HAL_ADC_COMMON_ADC_OTHER ADC_COMMON_ADC_OTHER -#define __HAL_ADC_MULTI_SLAVE ADC_MULTI_SLAVE - -#define __HAL_ADC_SQR1_L ADC_SQR1_L_SHIFT -#define __HAL_ADC_JSQR_JL ADC_JSQR_JL_SHIFT -#define __HAL_ADC_JSQR_RK_JL ADC_JSQR_RK_JL -#define __HAL_ADC_CR1_DISCONTINUOUS_NUM ADC_CR1_DISCONTINUOUS_NUM -#define __HAL_ADC_CR1_SCAN ADC_CR1_SCAN_SET -#define __HAL_ADC_CONVCYCLES_MAX_RANGE ADC_CONVCYCLES_MAX_RANGE -#define __HAL_ADC_CLOCK_PRESCALER_RANGE ADC_CLOCK_PRESCALER_RANGE -#define __HAL_ADC_GET_CLOCK_PRESCALER ADC_GET_CLOCK_PRESCALER - -#define __HAL_ADC_SQR1 ADC_SQR1 -#define __HAL_ADC_SMPR1 ADC_SMPR1 -#define __HAL_ADC_SMPR2 ADC_SMPR2 -#define __HAL_ADC_SQR3_RK ADC_SQR3_RK -#define __HAL_ADC_SQR2_RK ADC_SQR2_RK -#define __HAL_ADC_SQR1_RK ADC_SQR1_RK -#define __HAL_ADC_CR2_CONTINUOUS ADC_CR2_CONTINUOUS -#define __HAL_ADC_CR1_DISCONTINUOUS ADC_CR1_DISCONTINUOUS -#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV -#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection -#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq -#define __HAL_ADC_JSQR ADC_JSQR - -#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL -#define __HAL_ADC_CFGR1_REG_DISCCONTINUOUS ADC_CFGR1_REG_DISCCONTINUOUS -#define __HAL_ADC_CFGR1_AUTOOFF ADC_CFGR1_AUTOOFF -#define __HAL_ADC_CFGR1_AUTOWAIT ADC_CFGR1_AUTOWAIT -#define __HAL_ADC_CFGR1_CONTINUOUS ADC_CFGR1_CONTINUOUS -#define __HAL_ADC_CFGR1_OVERRUN ADC_CFGR1_OVERRUN -#define __HAL_ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR -#define __HAL_ADC_CFGR1_DMACONTREQ ADC_CFGR1_DMACONTREQ - -/** - * @} - */ - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_DHR12R1_ALIGNEMENT DAC_DHR12R1_ALIGNMENT -#define __HAL_DHR12R2_ALIGNEMENT DAC_DHR12R2_ALIGNMENT -#define __HAL_DHR12RD_ALIGNEMENT DAC_DHR12RD_ALIGNMENT -#define IS_DAC_GENERATE_WAVE IS_DAC_WAVE - -/** - * @} - */ - -/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_FREEZE_TIM1_DBGMCU __HAL_DBGMCU_FREEZE_TIM1 -#define __HAL_UNFREEZE_TIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM1 -#define __HAL_FREEZE_TIM2_DBGMCU __HAL_DBGMCU_FREEZE_TIM2 -#define __HAL_UNFREEZE_TIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM2 -#define __HAL_FREEZE_TIM3_DBGMCU __HAL_DBGMCU_FREEZE_TIM3 -#define __HAL_UNFREEZE_TIM3_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM3 -#define __HAL_FREEZE_TIM4_DBGMCU __HAL_DBGMCU_FREEZE_TIM4 -#define __HAL_UNFREEZE_TIM4_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM4 -#define __HAL_FREEZE_TIM5_DBGMCU __HAL_DBGMCU_FREEZE_TIM5 -#define __HAL_UNFREEZE_TIM5_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM5 -#define __HAL_FREEZE_TIM6_DBGMCU __HAL_DBGMCU_FREEZE_TIM6 -#define __HAL_UNFREEZE_TIM6_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM6 -#define __HAL_FREEZE_TIM7_DBGMCU __HAL_DBGMCU_FREEZE_TIM7 -#define __HAL_UNFREEZE_TIM7_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM7 -#define __HAL_FREEZE_TIM8_DBGMCU __HAL_DBGMCU_FREEZE_TIM8 -#define __HAL_UNFREEZE_TIM8_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM8 - -#define __HAL_FREEZE_TIM9_DBGMCU __HAL_DBGMCU_FREEZE_TIM9 -#define __HAL_UNFREEZE_TIM9_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM9 -#define __HAL_FREEZE_TIM10_DBGMCU __HAL_DBGMCU_FREEZE_TIM10 -#define __HAL_UNFREEZE_TIM10_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM10 -#define __HAL_FREEZE_TIM11_DBGMCU __HAL_DBGMCU_FREEZE_TIM11 -#define __HAL_UNFREEZE_TIM11_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM11 -#define __HAL_FREEZE_TIM12_DBGMCU __HAL_DBGMCU_FREEZE_TIM12 -#define __HAL_UNFREEZE_TIM12_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM12 -#define __HAL_FREEZE_TIM13_DBGMCU __HAL_DBGMCU_FREEZE_TIM13 -#define __HAL_UNFREEZE_TIM13_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM13 -#define __HAL_FREEZE_TIM14_DBGMCU __HAL_DBGMCU_FREEZE_TIM14 -#define __HAL_UNFREEZE_TIM14_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM14 -#define __HAL_FREEZE_CAN2_DBGMCU __HAL_DBGMCU_FREEZE_CAN2 -#define __HAL_UNFREEZE_CAN2_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN2 - - -#define __HAL_FREEZE_TIM15_DBGMCU __HAL_DBGMCU_FREEZE_TIM15 -#define __HAL_UNFREEZE_TIM15_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM15 -#define __HAL_FREEZE_TIM16_DBGMCU __HAL_DBGMCU_FREEZE_TIM16 -#define __HAL_UNFREEZE_TIM16_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM16 -#define __HAL_FREEZE_TIM17_DBGMCU __HAL_DBGMCU_FREEZE_TIM17 -#define __HAL_UNFREEZE_TIM17_DBGMCU __HAL_DBGMCU_UNFREEZE_TIM17 -#define __HAL_FREEZE_RTC_DBGMCU __HAL_DBGMCU_FREEZE_RTC -#define __HAL_UNFREEZE_RTC_DBGMCU __HAL_DBGMCU_UNFREEZE_RTC -#if defined(STM32H7) -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG1 -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UnFreeze_WWDG1 -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG1 -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UnFreeze_IWDG1 -#else -#define __HAL_FREEZE_WWDG_DBGMCU __HAL_DBGMCU_FREEZE_WWDG -#define __HAL_UNFREEZE_WWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_WWDG -#define __HAL_FREEZE_IWDG_DBGMCU __HAL_DBGMCU_FREEZE_IWDG -#define __HAL_UNFREEZE_IWDG_DBGMCU __HAL_DBGMCU_UNFREEZE_IWDG -#endif /* STM32H7 */ -#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT -#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT -#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT -#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT -#define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT -#define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT -#define __HAL_FREEZE_CAN1_DBGMCU __HAL_DBGMCU_FREEZE_CAN1 -#define __HAL_UNFREEZE_CAN1_DBGMCU __HAL_DBGMCU_UNFREEZE_CAN1 -#define __HAL_FREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM1 -#define __HAL_UNFREEZE_LPTIM1_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM1 -#define __HAL_FREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_FREEZE_LPTIM2 -#define __HAL_UNFREEZE_LPTIM2_DBGMCU __HAL_DBGMCU_UNFREEZE_LPTIM2 - -/** - * @} - */ - -/** @defgroup HAL_COMP_Aliased_Macros HAL COMP Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32F3) -#define COMP_START __HAL_COMP_ENABLE -#define COMP_STOP __HAL_COMP_DISABLE -#define COMP_LOCK __HAL_COMP_LOCK - -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ - defined(STM32F334x8) || defined(STM32F328xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -#endif -#if defined(STM32F302xE) || defined(STM32F302xC) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP6_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP6_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -#endif -#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_RISING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_FALLING_EDGE() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_ENABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_DISABLE_IT() : \ - ((__EXTILINE__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP7_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_GET_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP7_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ - ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -#endif -#if defined(STM32F373xC) ||defined(STM32F378xx) -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif -#else -#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_RISING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_FALLING_EDGE() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_FALLING_EDGE()) -#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_ENABLE_IT()) -#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_IT() : \ - __HAL_COMP_COMP2_EXTI_DISABLE_IT()) -#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_GET_FLAG() : \ - __HAL_COMP_COMP2_EXTI_GET_FLAG()) -#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ - __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -#endif - -#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE - -#if defined(STM32L0) || defined(STM32L4) -/* Note: On these STM32 families, the only argument of this macro */ -/* is COMP_FLAG_LOCK. */ -/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */ -/* argument. */ -#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__)) -#endif -/** - * @} - */ - -#if defined(STM32L0) || defined(STM32L4) -/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose - * @{ - */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is - done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is - done into HAL_COMP_Init() */ -/** - * @} - */ -#endif - -/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \ - ((WAVE) == DAC_WAVE_NOISE)|| \ - ((WAVE) == DAC_WAVE_TRIANGLE)) - -/** - * @} - */ - -/** @defgroup HAL_FLASH_Aliased_Macros HAL FLASH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_WRPAREA IS_OB_WRPAREA -#define IS_TYPEPROGRAM IS_FLASH_TYPEPROGRAM -#define IS_TYPEPROGRAMFLASH IS_FLASH_TYPEPROGRAM -#define IS_TYPEERASE IS_FLASH_TYPEERASE -#define IS_NBSECTORS IS_FLASH_NBSECTORS -#define IS_OB_WDG_SOURCE IS_OB_IWDG_SOURCE - -/** - * @} - */ - -/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2 -#define __HAL_I2C_GENERATE_START I2C_GENERATE_START -#if defined(STM32F1) -#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE -#else -#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE -#endif /* STM32F1 */ -#define __HAL_I2C_RISE_TIME I2C_RISE_TIME -#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD -#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST -#define __HAL_I2C_SPEED I2C_SPEED -#define __HAL_I2C_7BIT_ADD_WRITE I2C_7BIT_ADD_WRITE -#define __HAL_I2C_7BIT_ADD_READ I2C_7BIT_ADD_READ -#define __HAL_I2C_10BIT_ADDRESS I2C_10BIT_ADDRESS -#define __HAL_I2C_10BIT_HEADER_WRITE I2C_10BIT_HEADER_WRITE -#define __HAL_I2C_10BIT_HEADER_READ I2C_10BIT_HEADER_READ -#define __HAL_I2C_MEM_ADD_MSB I2C_MEM_ADD_MSB -#define __HAL_I2C_MEM_ADD_LSB I2C_MEM_ADD_LSB -#define __HAL_I2C_FREQRANGE I2C_FREQRANGE -/** - * @} - */ - -/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose - * @{ - */ - -#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE -#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT - -#if defined(STM32H7) -#define __HAL_I2S_CLEAR_FREFLAG __HAL_I2S_CLEAR_TIFREFLAG -#endif - -/** - * @} - */ - -/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __IRDA_DISABLE __HAL_IRDA_DISABLE -#define __IRDA_ENABLE __HAL_IRDA_ENABLE - -#define __HAL_IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __HAL_IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION -#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE -#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION - -#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE - - -/** - * @} - */ - - -/** @defgroup HAL_IWDG_Aliased_Macros HAL IWDG Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_IWDG_ENABLE_WRITE_ACCESS IWDG_ENABLE_WRITE_ACCESS -#define __HAL_IWDG_DISABLE_WRITE_ACCESS IWDG_DISABLE_WRITE_ACCESS -/** - * @} - */ - - -/** @defgroup HAL_LPTIM_Aliased_Macros HAL LPTIM Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_LPTIM_ENABLE_INTERRUPT __HAL_LPTIM_ENABLE_IT -#define __HAL_LPTIM_DISABLE_INTERRUPT __HAL_LPTIM_DISABLE_IT -#define __HAL_LPTIM_GET_ITSTATUS __HAL_LPTIM_GET_IT_SOURCE - -/** - * @} - */ - - -/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose - * @{ - */ -#define __OPAMP_CSR_OPAXPD OPAMP_CSR_OPAXPD -#define __OPAMP_CSR_S3SELX OPAMP_CSR_S3SELX -#define __OPAMP_CSR_S4SELX OPAMP_CSR_S4SELX -#define __OPAMP_CSR_S5SELX OPAMP_CSR_S5SELX -#define __OPAMP_CSR_S6SELX OPAMP_CSR_S6SELX -#define __OPAMP_CSR_OPAXCAL_L OPAMP_CSR_OPAXCAL_L -#define __OPAMP_CSR_OPAXCAL_H OPAMP_CSR_OPAXCAL_H -#define __OPAMP_CSR_OPAXLPM OPAMP_CSR_OPAXLPM -#define __OPAMP_CSR_ALL_SWITCHES OPAMP_CSR_ALL_SWITCHES -#define __OPAMP_CSR_ANAWSELX OPAMP_CSR_ANAWSELX -#define __OPAMP_CSR_OPAXCALOUT OPAMP_CSR_OPAXCALOUT -#define __OPAMP_OFFSET_TRIM_BITSPOSITION OPAMP_OFFSET_TRIM_BITSPOSITION -#define __OPAMP_OFFSET_TRIM_SET OPAMP_OFFSET_TRIM_SET - -/** - * @} - */ - - -/** @defgroup HAL_PWR_Aliased_Macros HAL PWR Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_PVD_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PVD_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PVM_EVENT_DISABLE __HAL_PWR_PVM_EVENT_DISABLE -#define __HAL_PVM_EVENT_ENABLE __HAL_PWR_PVM_EVENT_ENABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_FALLINGTRIGGER_ENABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_DISABLE -#define __HAL_PVM_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVM_EXTI_RISINGTRIGGER_ENABLE -#define __HAL_PWR_INTERNALWAKEUP_DISABLE HAL_PWREx_DisableInternalWakeUpLine -#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig -#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) -#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT -#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ - HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ - } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ - HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ - } while(0) -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention -#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention -#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 -#define __HAL_PWR_VDDIO2_ENABLE HAL_PWREx_EnableVddIO2 -#define __HAL_PWR_VDDIO2_EXTI_CLEAR_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_DISABLE_FALLING_EDGE -#define __HAL_PWR_VDDIO2_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_VDDIO2_EXTI_ENABLE_FALLING_EDGE -#define __HAL_PWR_VDDUSB_DISABLE HAL_PWREx_DisableVddUSB -#define __HAL_PWR_VDDUSB_ENABLE HAL_PWREx_EnableVddUSB - -#if defined (STM32F4) -#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT() -#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT() -#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG() -#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG() -#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT() -#else -#define __HAL_PVD_EXTI_CLEAR_FLAG __HAL_PWR_PVD_EXTI_CLEAR_FLAG -#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT -#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT -#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT -#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG -#endif /* STM32F4 */ -/** - * @} - */ - - -/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose - * @{ - */ - -#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI -#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI - -#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ - HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) - -#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE -#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE -#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE -#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE -#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET -#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET -#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE -#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE -#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET -#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET -#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE -#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE -#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE -#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE -#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET -#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET -#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE -#define __ADC3_CLK_ENABLE __HAL_RCC_ADC3_CLK_ENABLE -#define __ADC3_FORCE_RESET __HAL_RCC_ADC3_FORCE_RESET -#define __ADC3_RELEASE_RESET __HAL_RCC_ADC3_RELEASE_RESET -#define __AES_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __AES_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __AES_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __AES_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __AES_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __AES_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#define __CRYP_CLK_SLEEP_ENABLE __HAL_RCC_CRYP_CLK_SLEEP_ENABLE -#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE -#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE -#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE -#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET -#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET -#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE -#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE -#define __AFIO_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET -#define __AFIO_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET -#define __AHB_FORCE_RESET __HAL_RCC_AHB_FORCE_RESET -#define __AHB_RELEASE_RESET __HAL_RCC_AHB_RELEASE_RESET -#define __AHB1_FORCE_RESET __HAL_RCC_AHB1_FORCE_RESET -#define __AHB1_RELEASE_RESET __HAL_RCC_AHB1_RELEASE_RESET -#define __AHB2_FORCE_RESET __HAL_RCC_AHB2_FORCE_RESET -#define __AHB2_RELEASE_RESET __HAL_RCC_AHB2_RELEASE_RESET -#define __AHB3_FORCE_RESET __HAL_RCC_AHB3_FORCE_RESET -#define __AHB3_RELEASE_RESET __HAL_RCC_AHB3_RELEASE_RESET -#define __APB1_FORCE_RESET __HAL_RCC_APB1_FORCE_RESET -#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET -#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET -#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET -#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE -#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE -#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET -#define __BKP_RELEASE_RESET __HAL_RCC_BKP_RELEASE_RESET -#define __CAN1_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN1_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN1_CLK_SLEEP_DISABLE __HAL_RCC_CAN1_CLK_SLEEP_DISABLE -#define __CAN1_CLK_SLEEP_ENABLE __HAL_RCC_CAN1_CLK_SLEEP_ENABLE -#define __CAN1_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN1_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN_CLK_DISABLE __HAL_RCC_CAN1_CLK_DISABLE -#define __CAN_CLK_ENABLE __HAL_RCC_CAN1_CLK_ENABLE -#define __CAN_FORCE_RESET __HAL_RCC_CAN1_FORCE_RESET -#define __CAN_RELEASE_RESET __HAL_RCC_CAN1_RELEASE_RESET -#define __CAN2_CLK_DISABLE __HAL_RCC_CAN2_CLK_DISABLE -#define __CAN2_CLK_ENABLE __HAL_RCC_CAN2_CLK_ENABLE -#define __CAN2_FORCE_RESET __HAL_RCC_CAN2_FORCE_RESET -#define __CAN2_RELEASE_RESET __HAL_RCC_CAN2_RELEASE_RESET -#define __CEC_CLK_DISABLE __HAL_RCC_CEC_CLK_DISABLE -#define __CEC_CLK_ENABLE __HAL_RCC_CEC_CLK_ENABLE -#define __COMP_CLK_DISABLE __HAL_RCC_COMP_CLK_DISABLE -#define __COMP_CLK_ENABLE __HAL_RCC_COMP_CLK_ENABLE -#define __COMP_FORCE_RESET __HAL_RCC_COMP_FORCE_RESET -#define __COMP_RELEASE_RESET __HAL_RCC_COMP_RELEASE_RESET -#define __COMP_CLK_SLEEP_ENABLE __HAL_RCC_COMP_CLK_SLEEP_ENABLE -#define __COMP_CLK_SLEEP_DISABLE __HAL_RCC_COMP_CLK_SLEEP_DISABLE -#define __CEC_FORCE_RESET __HAL_RCC_CEC_FORCE_RESET -#define __CEC_RELEASE_RESET __HAL_RCC_CEC_RELEASE_RESET -#define __CRC_CLK_DISABLE __HAL_RCC_CRC_CLK_DISABLE -#define __CRC_CLK_ENABLE __HAL_RCC_CRC_CLK_ENABLE -#define __CRC_CLK_SLEEP_DISABLE __HAL_RCC_CRC_CLK_SLEEP_DISABLE -#define __CRC_CLK_SLEEP_ENABLE __HAL_RCC_CRC_CLK_SLEEP_ENABLE -#define __CRC_FORCE_RESET __HAL_RCC_CRC_FORCE_RESET -#define __CRC_RELEASE_RESET __HAL_RCC_CRC_RELEASE_RESET -#define __DAC_CLK_DISABLE __HAL_RCC_DAC_CLK_DISABLE -#define __DAC_CLK_ENABLE __HAL_RCC_DAC_CLK_ENABLE -#define __DAC_FORCE_RESET __HAL_RCC_DAC_FORCE_RESET -#define __DAC_RELEASE_RESET __HAL_RCC_DAC_RELEASE_RESET -#define __DAC1_CLK_DISABLE __HAL_RCC_DAC1_CLK_DISABLE -#define __DAC1_CLK_ENABLE __HAL_RCC_DAC1_CLK_ENABLE -#define __DAC1_CLK_SLEEP_DISABLE __HAL_RCC_DAC1_CLK_SLEEP_DISABLE -#define __DAC1_CLK_SLEEP_ENABLE __HAL_RCC_DAC1_CLK_SLEEP_ENABLE -#define __DAC1_FORCE_RESET __HAL_RCC_DAC1_FORCE_RESET -#define __DAC1_RELEASE_RESET __HAL_RCC_DAC1_RELEASE_RESET -#define __DBGMCU_CLK_ENABLE __HAL_RCC_DBGMCU_CLK_ENABLE -#define __DBGMCU_CLK_DISABLE __HAL_RCC_DBGMCU_CLK_DISABLE -#define __DBGMCU_FORCE_RESET __HAL_RCC_DBGMCU_FORCE_RESET -#define __DBGMCU_RELEASE_RESET __HAL_RCC_DBGMCU_RELEASE_RESET -#define __DFSDM_CLK_DISABLE __HAL_RCC_DFSDM_CLK_DISABLE -#define __DFSDM_CLK_ENABLE __HAL_RCC_DFSDM_CLK_ENABLE -#define __DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE -#define __DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE -#define __DFSDM_FORCE_RESET __HAL_RCC_DFSDM_FORCE_RESET -#define __DFSDM_RELEASE_RESET __HAL_RCC_DFSDM_RELEASE_RESET -#define __DMA1_CLK_DISABLE __HAL_RCC_DMA1_CLK_DISABLE -#define __DMA1_CLK_ENABLE __HAL_RCC_DMA1_CLK_ENABLE -#define __DMA1_CLK_SLEEP_DISABLE __HAL_RCC_DMA1_CLK_SLEEP_DISABLE -#define __DMA1_CLK_SLEEP_ENABLE __HAL_RCC_DMA1_CLK_SLEEP_ENABLE -#define __DMA1_FORCE_RESET __HAL_RCC_DMA1_FORCE_RESET -#define __DMA1_RELEASE_RESET __HAL_RCC_DMA1_RELEASE_RESET -#define __DMA2_CLK_DISABLE __HAL_RCC_DMA2_CLK_DISABLE -#define __DMA2_CLK_ENABLE __HAL_RCC_DMA2_CLK_ENABLE -#define __DMA2_CLK_SLEEP_DISABLE __HAL_RCC_DMA2_CLK_SLEEP_DISABLE -#define __DMA2_CLK_SLEEP_ENABLE __HAL_RCC_DMA2_CLK_SLEEP_ENABLE -#define __DMA2_FORCE_RESET __HAL_RCC_DMA2_FORCE_RESET -#define __DMA2_RELEASE_RESET __HAL_RCC_DMA2_RELEASE_RESET -#define __ETHMAC_CLK_DISABLE __HAL_RCC_ETHMAC_CLK_DISABLE -#define __ETHMAC_CLK_ENABLE __HAL_RCC_ETHMAC_CLK_ENABLE -#define __ETHMAC_FORCE_RESET __HAL_RCC_ETHMAC_FORCE_RESET -#define __ETHMAC_RELEASE_RESET __HAL_RCC_ETHMAC_RELEASE_RESET -#define __ETHMACRX_CLK_DISABLE __HAL_RCC_ETHMACRX_CLK_DISABLE -#define __ETHMACRX_CLK_ENABLE __HAL_RCC_ETHMACRX_CLK_ENABLE -#define __ETHMACTX_CLK_DISABLE __HAL_RCC_ETHMACTX_CLK_DISABLE -#define __ETHMACTX_CLK_ENABLE __HAL_RCC_ETHMACTX_CLK_ENABLE -#define __FIREWALL_CLK_DISABLE __HAL_RCC_FIREWALL_CLK_DISABLE -#define __FIREWALL_CLK_ENABLE __HAL_RCC_FIREWALL_CLK_ENABLE -#define __FLASH_CLK_DISABLE __HAL_RCC_FLASH_CLK_DISABLE -#define __FLASH_CLK_ENABLE __HAL_RCC_FLASH_CLK_ENABLE -#define __FLASH_CLK_SLEEP_DISABLE __HAL_RCC_FLASH_CLK_SLEEP_DISABLE -#define __FLASH_CLK_SLEEP_ENABLE __HAL_RCC_FLASH_CLK_SLEEP_ENABLE -#define __FLASH_FORCE_RESET __HAL_RCC_FLASH_FORCE_RESET -#define __FLASH_RELEASE_RESET __HAL_RCC_FLASH_RELEASE_RESET -#define __FLITF_CLK_DISABLE __HAL_RCC_FLITF_CLK_DISABLE -#define __FLITF_CLK_ENABLE __HAL_RCC_FLITF_CLK_ENABLE -#define __FLITF_FORCE_RESET __HAL_RCC_FLITF_FORCE_RESET -#define __FLITF_RELEASE_RESET __HAL_RCC_FLITF_RELEASE_RESET -#define __FLITF_CLK_SLEEP_ENABLE __HAL_RCC_FLITF_CLK_SLEEP_ENABLE -#define __FLITF_CLK_SLEEP_DISABLE __HAL_RCC_FLITF_CLK_SLEEP_DISABLE -#define __FMC_CLK_DISABLE __HAL_RCC_FMC_CLK_DISABLE -#define __FMC_CLK_ENABLE __HAL_RCC_FMC_CLK_ENABLE -#define __FMC_CLK_SLEEP_DISABLE __HAL_RCC_FMC_CLK_SLEEP_DISABLE -#define __FMC_CLK_SLEEP_ENABLE __HAL_RCC_FMC_CLK_SLEEP_ENABLE -#define __FMC_FORCE_RESET __HAL_RCC_FMC_FORCE_RESET -#define __FMC_RELEASE_RESET __HAL_RCC_FMC_RELEASE_RESET -#define __FSMC_CLK_DISABLE __HAL_RCC_FSMC_CLK_DISABLE -#define __FSMC_CLK_ENABLE __HAL_RCC_FSMC_CLK_ENABLE -#define __GPIOA_CLK_DISABLE __HAL_RCC_GPIOA_CLK_DISABLE -#define __GPIOA_CLK_ENABLE __HAL_RCC_GPIOA_CLK_ENABLE -#define __GPIOA_CLK_SLEEP_DISABLE __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE -#define __GPIOA_CLK_SLEEP_ENABLE __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE -#define __GPIOA_FORCE_RESET __HAL_RCC_GPIOA_FORCE_RESET -#define __GPIOA_RELEASE_RESET __HAL_RCC_GPIOA_RELEASE_RESET -#define __GPIOB_CLK_DISABLE __HAL_RCC_GPIOB_CLK_DISABLE -#define __GPIOB_CLK_ENABLE __HAL_RCC_GPIOB_CLK_ENABLE -#define __GPIOB_CLK_SLEEP_DISABLE __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE -#define __GPIOB_CLK_SLEEP_ENABLE __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE -#define __GPIOB_FORCE_RESET __HAL_RCC_GPIOB_FORCE_RESET -#define __GPIOB_RELEASE_RESET __HAL_RCC_GPIOB_RELEASE_RESET -#define __GPIOC_CLK_DISABLE __HAL_RCC_GPIOC_CLK_DISABLE -#define __GPIOC_CLK_ENABLE __HAL_RCC_GPIOC_CLK_ENABLE -#define __GPIOC_CLK_SLEEP_DISABLE __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE -#define __GPIOC_CLK_SLEEP_ENABLE __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE -#define __GPIOC_FORCE_RESET __HAL_RCC_GPIOC_FORCE_RESET -#define __GPIOC_RELEASE_RESET __HAL_RCC_GPIOC_RELEASE_RESET -#define __GPIOD_CLK_DISABLE __HAL_RCC_GPIOD_CLK_DISABLE -#define __GPIOD_CLK_ENABLE __HAL_RCC_GPIOD_CLK_ENABLE -#define __GPIOD_CLK_SLEEP_DISABLE __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE -#define __GPIOD_CLK_SLEEP_ENABLE __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE -#define __GPIOD_FORCE_RESET __HAL_RCC_GPIOD_FORCE_RESET -#define __GPIOD_RELEASE_RESET __HAL_RCC_GPIOD_RELEASE_RESET -#define __GPIOE_CLK_DISABLE __HAL_RCC_GPIOE_CLK_DISABLE -#define __GPIOE_CLK_ENABLE __HAL_RCC_GPIOE_CLK_ENABLE -#define __GPIOE_CLK_SLEEP_DISABLE __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE -#define __GPIOE_CLK_SLEEP_ENABLE __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE -#define __GPIOE_FORCE_RESET __HAL_RCC_GPIOE_FORCE_RESET -#define __GPIOE_RELEASE_RESET __HAL_RCC_GPIOE_RELEASE_RESET -#define __GPIOF_CLK_DISABLE __HAL_RCC_GPIOF_CLK_DISABLE -#define __GPIOF_CLK_ENABLE __HAL_RCC_GPIOF_CLK_ENABLE -#define __GPIOF_CLK_SLEEP_DISABLE __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE -#define __GPIOF_CLK_SLEEP_ENABLE __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE -#define __GPIOF_FORCE_RESET __HAL_RCC_GPIOF_FORCE_RESET -#define __GPIOF_RELEASE_RESET __HAL_RCC_GPIOF_RELEASE_RESET -#define __GPIOG_CLK_DISABLE __HAL_RCC_GPIOG_CLK_DISABLE -#define __GPIOG_CLK_ENABLE __HAL_RCC_GPIOG_CLK_ENABLE -#define __GPIOG_CLK_SLEEP_DISABLE __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE -#define __GPIOG_CLK_SLEEP_ENABLE __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE -#define __GPIOG_FORCE_RESET __HAL_RCC_GPIOG_FORCE_RESET -#define __GPIOG_RELEASE_RESET __HAL_RCC_GPIOG_RELEASE_RESET -#define __GPIOH_CLK_DISABLE __HAL_RCC_GPIOH_CLK_DISABLE -#define __GPIOH_CLK_ENABLE __HAL_RCC_GPIOH_CLK_ENABLE -#define __GPIOH_CLK_SLEEP_DISABLE __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE -#define __GPIOH_CLK_SLEEP_ENABLE __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE -#define __GPIOH_FORCE_RESET __HAL_RCC_GPIOH_FORCE_RESET -#define __GPIOH_RELEASE_RESET __HAL_RCC_GPIOH_RELEASE_RESET -#define __I2C1_CLK_DISABLE __HAL_RCC_I2C1_CLK_DISABLE -#define __I2C1_CLK_ENABLE __HAL_RCC_I2C1_CLK_ENABLE -#define __I2C1_CLK_SLEEP_DISABLE __HAL_RCC_I2C1_CLK_SLEEP_DISABLE -#define __I2C1_CLK_SLEEP_ENABLE __HAL_RCC_I2C1_CLK_SLEEP_ENABLE -#define __I2C1_FORCE_RESET __HAL_RCC_I2C1_FORCE_RESET -#define __I2C1_RELEASE_RESET __HAL_RCC_I2C1_RELEASE_RESET -#define __I2C2_CLK_DISABLE __HAL_RCC_I2C2_CLK_DISABLE -#define __I2C2_CLK_ENABLE __HAL_RCC_I2C2_CLK_ENABLE -#define __I2C2_CLK_SLEEP_DISABLE __HAL_RCC_I2C2_CLK_SLEEP_DISABLE -#define __I2C2_CLK_SLEEP_ENABLE __HAL_RCC_I2C2_CLK_SLEEP_ENABLE -#define __I2C2_FORCE_RESET __HAL_RCC_I2C2_FORCE_RESET -#define __I2C2_RELEASE_RESET __HAL_RCC_I2C2_RELEASE_RESET -#define __I2C3_CLK_DISABLE __HAL_RCC_I2C3_CLK_DISABLE -#define __I2C3_CLK_ENABLE __HAL_RCC_I2C3_CLK_ENABLE -#define __I2C3_CLK_SLEEP_DISABLE __HAL_RCC_I2C3_CLK_SLEEP_DISABLE -#define __I2C3_CLK_SLEEP_ENABLE __HAL_RCC_I2C3_CLK_SLEEP_ENABLE -#define __I2C3_FORCE_RESET __HAL_RCC_I2C3_FORCE_RESET -#define __I2C3_RELEASE_RESET __HAL_RCC_I2C3_RELEASE_RESET -#define __LCD_CLK_DISABLE __HAL_RCC_LCD_CLK_DISABLE -#define __LCD_CLK_ENABLE __HAL_RCC_LCD_CLK_ENABLE -#define __LCD_CLK_SLEEP_DISABLE __HAL_RCC_LCD_CLK_SLEEP_DISABLE -#define __LCD_CLK_SLEEP_ENABLE __HAL_RCC_LCD_CLK_SLEEP_ENABLE -#define __LCD_FORCE_RESET __HAL_RCC_LCD_FORCE_RESET -#define __LCD_RELEASE_RESET __HAL_RCC_LCD_RELEASE_RESET -#define __LPTIM1_CLK_DISABLE __HAL_RCC_LPTIM1_CLK_DISABLE -#define __LPTIM1_CLK_ENABLE __HAL_RCC_LPTIM1_CLK_ENABLE -#define __LPTIM1_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE -#define __LPTIM1_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE -#define __LPTIM1_FORCE_RESET __HAL_RCC_LPTIM1_FORCE_RESET -#define __LPTIM1_RELEASE_RESET __HAL_RCC_LPTIM1_RELEASE_RESET -#define __LPTIM2_CLK_DISABLE __HAL_RCC_LPTIM2_CLK_DISABLE -#define __LPTIM2_CLK_ENABLE __HAL_RCC_LPTIM2_CLK_ENABLE -#define __LPTIM2_CLK_SLEEP_DISABLE __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE -#define __LPTIM2_CLK_SLEEP_ENABLE __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE -#define __LPTIM2_FORCE_RESET __HAL_RCC_LPTIM2_FORCE_RESET -#define __LPTIM2_RELEASE_RESET __HAL_RCC_LPTIM2_RELEASE_RESET -#define __LPUART1_CLK_DISABLE __HAL_RCC_LPUART1_CLK_DISABLE -#define __LPUART1_CLK_ENABLE __HAL_RCC_LPUART1_CLK_ENABLE -#define __LPUART1_CLK_SLEEP_DISABLE __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE -#define __LPUART1_CLK_SLEEP_ENABLE __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE -#define __LPUART1_FORCE_RESET __HAL_RCC_LPUART1_FORCE_RESET -#define __LPUART1_RELEASE_RESET __HAL_RCC_LPUART1_RELEASE_RESET -#define __OPAMP_CLK_DISABLE __HAL_RCC_OPAMP_CLK_DISABLE -#define __OPAMP_CLK_ENABLE __HAL_RCC_OPAMP_CLK_ENABLE -#define __OPAMP_CLK_SLEEP_DISABLE __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE -#define __OPAMP_CLK_SLEEP_ENABLE __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE -#define __OPAMP_FORCE_RESET __HAL_RCC_OPAMP_FORCE_RESET -#define __OPAMP_RELEASE_RESET __HAL_RCC_OPAMP_RELEASE_RESET -#define __OTGFS_CLK_DISABLE __HAL_RCC_OTGFS_CLK_DISABLE -#define __OTGFS_CLK_ENABLE __HAL_RCC_OTGFS_CLK_ENABLE -#define __OTGFS_CLK_SLEEP_DISABLE __HAL_RCC_OTGFS_CLK_SLEEP_DISABLE -#define __OTGFS_CLK_SLEEP_ENABLE __HAL_RCC_OTGFS_CLK_SLEEP_ENABLE -#define __OTGFS_FORCE_RESET __HAL_RCC_OTGFS_FORCE_RESET -#define __OTGFS_RELEASE_RESET __HAL_RCC_OTGFS_RELEASE_RESET -#define __PWR_CLK_DISABLE __HAL_RCC_PWR_CLK_DISABLE -#define __PWR_CLK_ENABLE __HAL_RCC_PWR_CLK_ENABLE -#define __PWR_CLK_SLEEP_DISABLE __HAL_RCC_PWR_CLK_SLEEP_DISABLE -#define __PWR_CLK_SLEEP_ENABLE __HAL_RCC_PWR_CLK_SLEEP_ENABLE -#define __PWR_FORCE_RESET __HAL_RCC_PWR_FORCE_RESET -#define __PWR_RELEASE_RESET __HAL_RCC_PWR_RELEASE_RESET -#define __QSPI_CLK_DISABLE __HAL_RCC_QSPI_CLK_DISABLE -#define __QSPI_CLK_ENABLE __HAL_RCC_QSPI_CLK_ENABLE -#define __QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QSPI_CLK_SLEEP_DISABLE -#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE -#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET -#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET - -#if defined(STM32WB) -#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE -#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET -#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET -#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED -#define QSPI_IRQHandler QUADSPI_IRQHandler -#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */ - -#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE -#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE -#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE -#define __RNG_CLK_SLEEP_ENABLE __HAL_RCC_RNG_CLK_SLEEP_ENABLE -#define __RNG_FORCE_RESET __HAL_RCC_RNG_FORCE_RESET -#define __RNG_RELEASE_RESET __HAL_RCC_RNG_RELEASE_RESET -#define __SAI1_CLK_DISABLE __HAL_RCC_SAI1_CLK_DISABLE -#define __SAI1_CLK_ENABLE __HAL_RCC_SAI1_CLK_ENABLE -#define __SAI1_CLK_SLEEP_DISABLE __HAL_RCC_SAI1_CLK_SLEEP_DISABLE -#define __SAI1_CLK_SLEEP_ENABLE __HAL_RCC_SAI1_CLK_SLEEP_ENABLE -#define __SAI1_FORCE_RESET __HAL_RCC_SAI1_FORCE_RESET -#define __SAI1_RELEASE_RESET __HAL_RCC_SAI1_RELEASE_RESET -#define __SAI2_CLK_DISABLE __HAL_RCC_SAI2_CLK_DISABLE -#define __SAI2_CLK_ENABLE __HAL_RCC_SAI2_CLK_ENABLE -#define __SAI2_CLK_SLEEP_DISABLE __HAL_RCC_SAI2_CLK_SLEEP_DISABLE -#define __SAI2_CLK_SLEEP_ENABLE __HAL_RCC_SAI2_CLK_SLEEP_ENABLE -#define __SAI2_FORCE_RESET __HAL_RCC_SAI2_FORCE_RESET -#define __SAI2_RELEASE_RESET __HAL_RCC_SAI2_RELEASE_RESET -#define __SDIO_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __SDIO_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __SDMMC_CLK_DISABLE __HAL_RCC_SDMMC_CLK_DISABLE -#define __SDMMC_CLK_ENABLE __HAL_RCC_SDMMC_CLK_ENABLE -#define __SDMMC_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC_CLK_SLEEP_DISABLE -#define __SDMMC_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC_CLK_SLEEP_ENABLE -#define __SDMMC_FORCE_RESET __HAL_RCC_SDMMC_FORCE_RESET -#define __SDMMC_RELEASE_RESET __HAL_RCC_SDMMC_RELEASE_RESET -#define __SPI1_CLK_DISABLE __HAL_RCC_SPI1_CLK_DISABLE -#define __SPI1_CLK_ENABLE __HAL_RCC_SPI1_CLK_ENABLE -#define __SPI1_CLK_SLEEP_DISABLE __HAL_RCC_SPI1_CLK_SLEEP_DISABLE -#define __SPI1_CLK_SLEEP_ENABLE __HAL_RCC_SPI1_CLK_SLEEP_ENABLE -#define __SPI1_FORCE_RESET __HAL_RCC_SPI1_FORCE_RESET -#define __SPI1_RELEASE_RESET __HAL_RCC_SPI1_RELEASE_RESET -#define __SPI2_CLK_DISABLE __HAL_RCC_SPI2_CLK_DISABLE -#define __SPI2_CLK_ENABLE __HAL_RCC_SPI2_CLK_ENABLE -#define __SPI2_CLK_SLEEP_DISABLE __HAL_RCC_SPI2_CLK_SLEEP_DISABLE -#define __SPI2_CLK_SLEEP_ENABLE __HAL_RCC_SPI2_CLK_SLEEP_ENABLE -#define __SPI2_FORCE_RESET __HAL_RCC_SPI2_FORCE_RESET -#define __SPI2_RELEASE_RESET __HAL_RCC_SPI2_RELEASE_RESET -#define __SPI3_CLK_DISABLE __HAL_RCC_SPI3_CLK_DISABLE -#define __SPI3_CLK_ENABLE __HAL_RCC_SPI3_CLK_ENABLE -#define __SPI3_CLK_SLEEP_DISABLE __HAL_RCC_SPI3_CLK_SLEEP_DISABLE -#define __SPI3_CLK_SLEEP_ENABLE __HAL_RCC_SPI3_CLK_SLEEP_ENABLE -#define __SPI3_FORCE_RESET __HAL_RCC_SPI3_FORCE_RESET -#define __SPI3_RELEASE_RESET __HAL_RCC_SPI3_RELEASE_RESET -#define __SRAM_CLK_DISABLE __HAL_RCC_SRAM_CLK_DISABLE -#define __SRAM_CLK_ENABLE __HAL_RCC_SRAM_CLK_ENABLE -#define __SRAM1_CLK_SLEEP_DISABLE __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE -#define __SRAM1_CLK_SLEEP_ENABLE __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE -#define __SRAM2_CLK_SLEEP_DISABLE __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE -#define __SRAM2_CLK_SLEEP_ENABLE __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE -#define __SWPMI1_CLK_DISABLE __HAL_RCC_SWPMI1_CLK_DISABLE -#define __SWPMI1_CLK_ENABLE __HAL_RCC_SWPMI1_CLK_ENABLE -#define __SWPMI1_CLK_SLEEP_DISABLE __HAL_RCC_SWPMI1_CLK_SLEEP_DISABLE -#define __SWPMI1_CLK_SLEEP_ENABLE __HAL_RCC_SWPMI1_CLK_SLEEP_ENABLE -#define __SWPMI1_FORCE_RESET __HAL_RCC_SWPMI1_FORCE_RESET -#define __SWPMI1_RELEASE_RESET __HAL_RCC_SWPMI1_RELEASE_RESET -#define __SYSCFG_CLK_DISABLE __HAL_RCC_SYSCFG_CLK_DISABLE -#define __SYSCFG_CLK_ENABLE __HAL_RCC_SYSCFG_CLK_ENABLE -#define __SYSCFG_CLK_SLEEP_DISABLE __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE -#define __SYSCFG_CLK_SLEEP_ENABLE __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE -#define __SYSCFG_FORCE_RESET __HAL_RCC_SYSCFG_FORCE_RESET -#define __SYSCFG_RELEASE_RESET __HAL_RCC_SYSCFG_RELEASE_RESET -#define __TIM1_CLK_DISABLE __HAL_RCC_TIM1_CLK_DISABLE -#define __TIM1_CLK_ENABLE __HAL_RCC_TIM1_CLK_ENABLE -#define __TIM1_CLK_SLEEP_DISABLE __HAL_RCC_TIM1_CLK_SLEEP_DISABLE -#define __TIM1_CLK_SLEEP_ENABLE __HAL_RCC_TIM1_CLK_SLEEP_ENABLE -#define __TIM1_FORCE_RESET __HAL_RCC_TIM1_FORCE_RESET -#define __TIM1_RELEASE_RESET __HAL_RCC_TIM1_RELEASE_RESET -#define __TIM10_CLK_DISABLE __HAL_RCC_TIM10_CLK_DISABLE -#define __TIM10_CLK_ENABLE __HAL_RCC_TIM10_CLK_ENABLE -#define __TIM10_FORCE_RESET __HAL_RCC_TIM10_FORCE_RESET -#define __TIM10_RELEASE_RESET __HAL_RCC_TIM10_RELEASE_RESET -#define __TIM11_CLK_DISABLE __HAL_RCC_TIM11_CLK_DISABLE -#define __TIM11_CLK_ENABLE __HAL_RCC_TIM11_CLK_ENABLE -#define __TIM11_FORCE_RESET __HAL_RCC_TIM11_FORCE_RESET -#define __TIM11_RELEASE_RESET __HAL_RCC_TIM11_RELEASE_RESET -#define __TIM12_CLK_DISABLE __HAL_RCC_TIM12_CLK_DISABLE -#define __TIM12_CLK_ENABLE __HAL_RCC_TIM12_CLK_ENABLE -#define __TIM12_FORCE_RESET __HAL_RCC_TIM12_FORCE_RESET -#define __TIM12_RELEASE_RESET __HAL_RCC_TIM12_RELEASE_RESET -#define __TIM13_CLK_DISABLE __HAL_RCC_TIM13_CLK_DISABLE -#define __TIM13_CLK_ENABLE __HAL_RCC_TIM13_CLK_ENABLE -#define __TIM13_FORCE_RESET __HAL_RCC_TIM13_FORCE_RESET -#define __TIM13_RELEASE_RESET __HAL_RCC_TIM13_RELEASE_RESET -#define __TIM14_CLK_DISABLE __HAL_RCC_TIM14_CLK_DISABLE -#define __TIM14_CLK_ENABLE __HAL_RCC_TIM14_CLK_ENABLE -#define __TIM14_FORCE_RESET __HAL_RCC_TIM14_FORCE_RESET -#define __TIM14_RELEASE_RESET __HAL_RCC_TIM14_RELEASE_RESET -#define __TIM15_CLK_DISABLE __HAL_RCC_TIM15_CLK_DISABLE -#define __TIM15_CLK_ENABLE __HAL_RCC_TIM15_CLK_ENABLE -#define __TIM15_CLK_SLEEP_DISABLE __HAL_RCC_TIM15_CLK_SLEEP_DISABLE -#define __TIM15_CLK_SLEEP_ENABLE __HAL_RCC_TIM15_CLK_SLEEP_ENABLE -#define __TIM15_FORCE_RESET __HAL_RCC_TIM15_FORCE_RESET -#define __TIM15_RELEASE_RESET __HAL_RCC_TIM15_RELEASE_RESET -#define __TIM16_CLK_DISABLE __HAL_RCC_TIM16_CLK_DISABLE -#define __TIM16_CLK_ENABLE __HAL_RCC_TIM16_CLK_ENABLE -#define __TIM16_CLK_SLEEP_DISABLE __HAL_RCC_TIM16_CLK_SLEEP_DISABLE -#define __TIM16_CLK_SLEEP_ENABLE __HAL_RCC_TIM16_CLK_SLEEP_ENABLE -#define __TIM16_FORCE_RESET __HAL_RCC_TIM16_FORCE_RESET -#define __TIM16_RELEASE_RESET __HAL_RCC_TIM16_RELEASE_RESET -#define __TIM17_CLK_DISABLE __HAL_RCC_TIM17_CLK_DISABLE -#define __TIM17_CLK_ENABLE __HAL_RCC_TIM17_CLK_ENABLE -#define __TIM17_CLK_SLEEP_DISABLE __HAL_RCC_TIM17_CLK_SLEEP_DISABLE -#define __TIM17_CLK_SLEEP_ENABLE __HAL_RCC_TIM17_CLK_SLEEP_ENABLE -#define __TIM17_FORCE_RESET __HAL_RCC_TIM17_FORCE_RESET -#define __TIM17_RELEASE_RESET __HAL_RCC_TIM17_RELEASE_RESET -#define __TIM2_CLK_DISABLE __HAL_RCC_TIM2_CLK_DISABLE -#define __TIM2_CLK_ENABLE __HAL_RCC_TIM2_CLK_ENABLE -#define __TIM2_CLK_SLEEP_DISABLE __HAL_RCC_TIM2_CLK_SLEEP_DISABLE -#define __TIM2_CLK_SLEEP_ENABLE __HAL_RCC_TIM2_CLK_SLEEP_ENABLE -#define __TIM2_FORCE_RESET __HAL_RCC_TIM2_FORCE_RESET -#define __TIM2_RELEASE_RESET __HAL_RCC_TIM2_RELEASE_RESET -#define __TIM3_CLK_DISABLE __HAL_RCC_TIM3_CLK_DISABLE -#define __TIM3_CLK_ENABLE __HAL_RCC_TIM3_CLK_ENABLE -#define __TIM3_CLK_SLEEP_DISABLE __HAL_RCC_TIM3_CLK_SLEEP_DISABLE -#define __TIM3_CLK_SLEEP_ENABLE __HAL_RCC_TIM3_CLK_SLEEP_ENABLE -#define __TIM3_FORCE_RESET __HAL_RCC_TIM3_FORCE_RESET -#define __TIM3_RELEASE_RESET __HAL_RCC_TIM3_RELEASE_RESET -#define __TIM4_CLK_DISABLE __HAL_RCC_TIM4_CLK_DISABLE -#define __TIM4_CLK_ENABLE __HAL_RCC_TIM4_CLK_ENABLE -#define __TIM4_CLK_SLEEP_DISABLE __HAL_RCC_TIM4_CLK_SLEEP_DISABLE -#define __TIM4_CLK_SLEEP_ENABLE __HAL_RCC_TIM4_CLK_SLEEP_ENABLE -#define __TIM4_FORCE_RESET __HAL_RCC_TIM4_FORCE_RESET -#define __TIM4_RELEASE_RESET __HAL_RCC_TIM4_RELEASE_RESET -#define __TIM5_CLK_DISABLE __HAL_RCC_TIM5_CLK_DISABLE -#define __TIM5_CLK_ENABLE __HAL_RCC_TIM5_CLK_ENABLE -#define __TIM5_CLK_SLEEP_DISABLE __HAL_RCC_TIM5_CLK_SLEEP_DISABLE -#define __TIM5_CLK_SLEEP_ENABLE __HAL_RCC_TIM5_CLK_SLEEP_ENABLE -#define __TIM5_FORCE_RESET __HAL_RCC_TIM5_FORCE_RESET -#define __TIM5_RELEASE_RESET __HAL_RCC_TIM5_RELEASE_RESET -#define __TIM6_CLK_DISABLE __HAL_RCC_TIM6_CLK_DISABLE -#define __TIM6_CLK_ENABLE __HAL_RCC_TIM6_CLK_ENABLE -#define __TIM6_CLK_SLEEP_DISABLE __HAL_RCC_TIM6_CLK_SLEEP_DISABLE -#define __TIM6_CLK_SLEEP_ENABLE __HAL_RCC_TIM6_CLK_SLEEP_ENABLE -#define __TIM6_FORCE_RESET __HAL_RCC_TIM6_FORCE_RESET -#define __TIM6_RELEASE_RESET __HAL_RCC_TIM6_RELEASE_RESET -#define __TIM7_CLK_DISABLE __HAL_RCC_TIM7_CLK_DISABLE -#define __TIM7_CLK_ENABLE __HAL_RCC_TIM7_CLK_ENABLE -#define __TIM7_CLK_SLEEP_DISABLE __HAL_RCC_TIM7_CLK_SLEEP_DISABLE -#define __TIM7_CLK_SLEEP_ENABLE __HAL_RCC_TIM7_CLK_SLEEP_ENABLE -#define __TIM7_FORCE_RESET __HAL_RCC_TIM7_FORCE_RESET -#define __TIM7_RELEASE_RESET __HAL_RCC_TIM7_RELEASE_RESET -#define __TIM8_CLK_DISABLE __HAL_RCC_TIM8_CLK_DISABLE -#define __TIM8_CLK_ENABLE __HAL_RCC_TIM8_CLK_ENABLE -#define __TIM8_CLK_SLEEP_DISABLE __HAL_RCC_TIM8_CLK_SLEEP_DISABLE -#define __TIM8_CLK_SLEEP_ENABLE __HAL_RCC_TIM8_CLK_SLEEP_ENABLE -#define __TIM8_FORCE_RESET __HAL_RCC_TIM8_FORCE_RESET -#define __TIM8_RELEASE_RESET __HAL_RCC_TIM8_RELEASE_RESET -#define __TIM9_CLK_DISABLE __HAL_RCC_TIM9_CLK_DISABLE -#define __TIM9_CLK_ENABLE __HAL_RCC_TIM9_CLK_ENABLE -#define __TIM9_FORCE_RESET __HAL_RCC_TIM9_FORCE_RESET -#define __TIM9_RELEASE_RESET __HAL_RCC_TIM9_RELEASE_RESET -#define __TSC_CLK_DISABLE __HAL_RCC_TSC_CLK_DISABLE -#define __TSC_CLK_ENABLE __HAL_RCC_TSC_CLK_ENABLE -#define __TSC_CLK_SLEEP_DISABLE __HAL_RCC_TSC_CLK_SLEEP_DISABLE -#define __TSC_CLK_SLEEP_ENABLE __HAL_RCC_TSC_CLK_SLEEP_ENABLE -#define __TSC_FORCE_RESET __HAL_RCC_TSC_FORCE_RESET -#define __TSC_RELEASE_RESET __HAL_RCC_TSC_RELEASE_RESET -#define __UART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __UART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __UART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __UART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __UART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __UART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __UART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __UART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __UART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __UART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __UART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __UART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART1_CLK_DISABLE __HAL_RCC_USART1_CLK_DISABLE -#define __USART1_CLK_ENABLE __HAL_RCC_USART1_CLK_ENABLE -#define __USART1_CLK_SLEEP_DISABLE __HAL_RCC_USART1_CLK_SLEEP_DISABLE -#define __USART1_CLK_SLEEP_ENABLE __HAL_RCC_USART1_CLK_SLEEP_ENABLE -#define __USART1_FORCE_RESET __HAL_RCC_USART1_FORCE_RESET -#define __USART1_RELEASE_RESET __HAL_RCC_USART1_RELEASE_RESET -#define __USART2_CLK_DISABLE __HAL_RCC_USART2_CLK_DISABLE -#define __USART2_CLK_ENABLE __HAL_RCC_USART2_CLK_ENABLE -#define __USART2_CLK_SLEEP_DISABLE __HAL_RCC_USART2_CLK_SLEEP_DISABLE -#define __USART2_CLK_SLEEP_ENABLE __HAL_RCC_USART2_CLK_SLEEP_ENABLE -#define __USART2_FORCE_RESET __HAL_RCC_USART2_FORCE_RESET -#define __USART2_RELEASE_RESET __HAL_RCC_USART2_RELEASE_RESET -#define __USART3_CLK_DISABLE __HAL_RCC_USART3_CLK_DISABLE -#define __USART3_CLK_ENABLE __HAL_RCC_USART3_CLK_ENABLE -#define __USART3_CLK_SLEEP_DISABLE __HAL_RCC_USART3_CLK_SLEEP_DISABLE -#define __USART3_CLK_SLEEP_ENABLE __HAL_RCC_USART3_CLK_SLEEP_ENABLE -#define __USART3_FORCE_RESET __HAL_RCC_USART3_FORCE_RESET -#define __USART3_RELEASE_RESET __HAL_RCC_USART3_RELEASE_RESET -#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE -#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE -#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE -#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE -#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET -#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET -#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE -#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE -#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE -#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE -#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET -#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET -#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __USART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __USART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __USART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __USART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __USART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __USART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __USART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __USB_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE -#define __USB_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE -#define __USB_FORCE_RESET __HAL_RCC_USB_FORCE_RESET -#define __USB_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE -#define __USB_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE -#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE -#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE -#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET - -#if defined(STM32H7) -#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE -#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE - -#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/ -#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/ - - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED -#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED -#define RCC_SPI4CLKSOURCE_D2PCLK1 RCC_SPI4CLKSOURCE_D2PCLK2 -#define RCC_SPI5CLKSOURCE_D2PCLK1 RCC_SPI5CLKSOURCE_D2PCLK2 -#define RCC_SPI45CLKSOURCE_D2PCLK1 RCC_SPI45CLKSOURCE_D2PCLK2 -#define RCC_SPI45CLKSOURCE_CDPCLK1 RCC_SPI45CLKSOURCE_CDPCLK2 -#define RCC_SPI45CLKSOURCE_PCLK1 RCC_SPI45CLKSOURCE_PCLK2 -#endif - -#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE -#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE -#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE -#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE -#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET -#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET - -#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE -#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE -#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET -#define __TIM21_RELEASE_RESET __HAL_RCC_TIM21_RELEASE_RESET -#define __TIM21_CLK_SLEEP_ENABLE __HAL_RCC_TIM21_CLK_SLEEP_ENABLE -#define __TIM21_CLK_SLEEP_DISABLE __HAL_RCC_TIM21_CLK_SLEEP_DISABLE -#define __TIM22_CLK_ENABLE __HAL_RCC_TIM22_CLK_ENABLE -#define __TIM22_CLK_DISABLE __HAL_RCC_TIM22_CLK_DISABLE -#define __TIM22_FORCE_RESET __HAL_RCC_TIM22_FORCE_RESET -#define __TIM22_RELEASE_RESET __HAL_RCC_TIM22_RELEASE_RESET -#define __TIM22_CLK_SLEEP_ENABLE __HAL_RCC_TIM22_CLK_SLEEP_ENABLE -#define __TIM22_CLK_SLEEP_DISABLE __HAL_RCC_TIM22_CLK_SLEEP_DISABLE -#define __CRS_CLK_DISABLE __HAL_RCC_CRS_CLK_DISABLE -#define __CRS_CLK_ENABLE __HAL_RCC_CRS_CLK_ENABLE -#define __CRS_CLK_SLEEP_DISABLE __HAL_RCC_CRS_CLK_SLEEP_DISABLE -#define __CRS_CLK_SLEEP_ENABLE __HAL_RCC_CRS_CLK_SLEEP_ENABLE -#define __CRS_FORCE_RESET __HAL_RCC_CRS_FORCE_RESET -#define __CRS_RELEASE_RESET __HAL_RCC_CRS_RELEASE_RESET -#define __RCC_BACKUPRESET_FORCE __HAL_RCC_BACKUPRESET_FORCE -#define __RCC_BACKUPRESET_RELEASE __HAL_RCC_BACKUPRESET_RELEASE - -#define __USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET -#define __USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE -#define __USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE -#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE -#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE -#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE -#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE -#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE -#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE -#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE -#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE -#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE -#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE -#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE -#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE -#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE -#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET -#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET -#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE -#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE -#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE -#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE -#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE -#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET -#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET -#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE -#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE -#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE -#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE -#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET -#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET -#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE -#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE -#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE -#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE -#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET -#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET -#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE -#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE -#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE -#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE -#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE -#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE -#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE -#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE -#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE -#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE -#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE -#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE -#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE -#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE -#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE -#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE -#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE -#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE -#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE -#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE -#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET -#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET -#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE -#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE -#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE -#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE -#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET -#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET -#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE -#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE -#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE -#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE -#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET -#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET -#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE -#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE -#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE -#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE -#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET -#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET -#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE -#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE -#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE -#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE -#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET -#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE -#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE -#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE -#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE -#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE -#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE -#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET -#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET -#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE -#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE -#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE -#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE -#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET -#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET -#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE -#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE -#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE -#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE -#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET -#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET -#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE -#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE -#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED -#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET -#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE -#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED -#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE -#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE -#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE -#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE -#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE -#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE -#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE -#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE -#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET -#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET -#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE -#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE -#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE -#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE -#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET -#define __DMA2D_RELEASE_RESET __HAL_RCC_DMA2D_RELEASE_RESET -#define __DMA2D_CLK_SLEEP_ENABLE __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE -#define __DMA2D_CLK_SLEEP_DISABLE __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE - -/* alias define maintained for legacy */ -#define __HAL_RCC_OTGFS_FORCE_RESET __HAL_RCC_USB_OTG_FS_FORCE_RESET -#define __HAL_RCC_OTGFS_RELEASE_RESET __HAL_RCC_USB_OTG_FS_RELEASE_RESET - -#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE -#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE -#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE -#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE -#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE -#define __TIM18_CLK_DISABLE __HAL_RCC_TIM18_CLK_DISABLE -#define __TIM19_CLK_ENABLE __HAL_RCC_TIM19_CLK_ENABLE -#define __TIM19_CLK_DISABLE __HAL_RCC_TIM19_CLK_DISABLE -#define __TIM20_CLK_ENABLE __HAL_RCC_TIM20_CLK_ENABLE -#define __TIM20_CLK_DISABLE __HAL_RCC_TIM20_CLK_DISABLE -#define __HRTIM1_CLK_ENABLE __HAL_RCC_HRTIM1_CLK_ENABLE -#define __HRTIM1_CLK_DISABLE __HAL_RCC_HRTIM1_CLK_DISABLE -#define __SDADC1_CLK_ENABLE __HAL_RCC_SDADC1_CLK_ENABLE -#define __SDADC2_CLK_ENABLE __HAL_RCC_SDADC2_CLK_ENABLE -#define __SDADC3_CLK_ENABLE __HAL_RCC_SDADC3_CLK_ENABLE -#define __SDADC1_CLK_DISABLE __HAL_RCC_SDADC1_CLK_DISABLE -#define __SDADC2_CLK_DISABLE __HAL_RCC_SDADC2_CLK_DISABLE -#define __SDADC3_CLK_DISABLE __HAL_RCC_SDADC3_CLK_DISABLE - -#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET -#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET -#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET -#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET -#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET -#define __TIM18_RELEASE_RESET __HAL_RCC_TIM18_RELEASE_RESET -#define __TIM19_FORCE_RESET __HAL_RCC_TIM19_FORCE_RESET -#define __TIM19_RELEASE_RESET __HAL_RCC_TIM19_RELEASE_RESET -#define __TIM20_FORCE_RESET __HAL_RCC_TIM20_FORCE_RESET -#define __TIM20_RELEASE_RESET __HAL_RCC_TIM20_RELEASE_RESET -#define __HRTIM1_FORCE_RESET __HAL_RCC_HRTIM1_FORCE_RESET -#define __HRTIM1_RELEASE_RESET __HAL_RCC_HRTIM1_RELEASE_RESET -#define __SDADC1_FORCE_RESET __HAL_RCC_SDADC1_FORCE_RESET -#define __SDADC2_FORCE_RESET __HAL_RCC_SDADC2_FORCE_RESET -#define __SDADC3_FORCE_RESET __HAL_RCC_SDADC3_FORCE_RESET -#define __SDADC1_RELEASE_RESET __HAL_RCC_SDADC1_RELEASE_RESET -#define __SDADC2_RELEASE_RESET __HAL_RCC_SDADC2_RELEASE_RESET -#define __SDADC3_RELEASE_RESET __HAL_RCC_SDADC3_RELEASE_RESET - -#define __ADC1_IS_CLK_ENABLED __HAL_RCC_ADC1_IS_CLK_ENABLED -#define __ADC1_IS_CLK_DISABLED __HAL_RCC_ADC1_IS_CLK_DISABLED -#define __ADC12_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __ADC12_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __ADC34_IS_CLK_ENABLED __HAL_RCC_ADC34_IS_CLK_ENABLED -#define __ADC34_IS_CLK_DISABLED __HAL_RCC_ADC34_IS_CLK_DISABLED -#define __CEC_IS_CLK_ENABLED __HAL_RCC_CEC_IS_CLK_ENABLED -#define __CEC_IS_CLK_DISABLED __HAL_RCC_CEC_IS_CLK_DISABLED -#define __CRC_IS_CLK_ENABLED __HAL_RCC_CRC_IS_CLK_ENABLED -#define __CRC_IS_CLK_DISABLED __HAL_RCC_CRC_IS_CLK_DISABLED -#define __DAC1_IS_CLK_ENABLED __HAL_RCC_DAC1_IS_CLK_ENABLED -#define __DAC1_IS_CLK_DISABLED __HAL_RCC_DAC1_IS_CLK_DISABLED -#define __DAC2_IS_CLK_ENABLED __HAL_RCC_DAC2_IS_CLK_ENABLED -#define __DAC2_IS_CLK_DISABLED __HAL_RCC_DAC2_IS_CLK_DISABLED -#define __DMA1_IS_CLK_ENABLED __HAL_RCC_DMA1_IS_CLK_ENABLED -#define __DMA1_IS_CLK_DISABLED __HAL_RCC_DMA1_IS_CLK_DISABLED -#define __DMA2_IS_CLK_ENABLED __HAL_RCC_DMA2_IS_CLK_ENABLED -#define __DMA2_IS_CLK_DISABLED __HAL_RCC_DMA2_IS_CLK_DISABLED -#define __FLITF_IS_CLK_ENABLED __HAL_RCC_FLITF_IS_CLK_ENABLED -#define __FLITF_IS_CLK_DISABLED __HAL_RCC_FLITF_IS_CLK_DISABLED -#define __FMC_IS_CLK_ENABLED __HAL_RCC_FMC_IS_CLK_ENABLED -#define __FMC_IS_CLK_DISABLED __HAL_RCC_FMC_IS_CLK_DISABLED -#define __GPIOA_IS_CLK_ENABLED __HAL_RCC_GPIOA_IS_CLK_ENABLED -#define __GPIOA_IS_CLK_DISABLED __HAL_RCC_GPIOA_IS_CLK_DISABLED -#define __GPIOB_IS_CLK_ENABLED __HAL_RCC_GPIOB_IS_CLK_ENABLED -#define __GPIOB_IS_CLK_DISABLED __HAL_RCC_GPIOB_IS_CLK_DISABLED -#define __GPIOC_IS_CLK_ENABLED __HAL_RCC_GPIOC_IS_CLK_ENABLED -#define __GPIOC_IS_CLK_DISABLED __HAL_RCC_GPIOC_IS_CLK_DISABLED -#define __GPIOD_IS_CLK_ENABLED __HAL_RCC_GPIOD_IS_CLK_ENABLED -#define __GPIOD_IS_CLK_DISABLED __HAL_RCC_GPIOD_IS_CLK_DISABLED -#define __GPIOE_IS_CLK_ENABLED __HAL_RCC_GPIOE_IS_CLK_ENABLED -#define __GPIOE_IS_CLK_DISABLED __HAL_RCC_GPIOE_IS_CLK_DISABLED -#define __GPIOF_IS_CLK_ENABLED __HAL_RCC_GPIOF_IS_CLK_ENABLED -#define __GPIOF_IS_CLK_DISABLED __HAL_RCC_GPIOF_IS_CLK_DISABLED -#define __GPIOG_IS_CLK_ENABLED __HAL_RCC_GPIOG_IS_CLK_ENABLED -#define __GPIOG_IS_CLK_DISABLED __HAL_RCC_GPIOG_IS_CLK_DISABLED -#define __GPIOH_IS_CLK_ENABLED __HAL_RCC_GPIOH_IS_CLK_ENABLED -#define __GPIOH_IS_CLK_DISABLED __HAL_RCC_GPIOH_IS_CLK_DISABLED -#define __HRTIM1_IS_CLK_ENABLED __HAL_RCC_HRTIM1_IS_CLK_ENABLED -#define __HRTIM1_IS_CLK_DISABLED __HAL_RCC_HRTIM1_IS_CLK_DISABLED -#define __I2C1_IS_CLK_ENABLED __HAL_RCC_I2C1_IS_CLK_ENABLED -#define __I2C1_IS_CLK_DISABLED __HAL_RCC_I2C1_IS_CLK_DISABLED -#define __I2C2_IS_CLK_ENABLED __HAL_RCC_I2C2_IS_CLK_ENABLED -#define __I2C2_IS_CLK_DISABLED __HAL_RCC_I2C2_IS_CLK_DISABLED -#define __I2C3_IS_CLK_ENABLED __HAL_RCC_I2C3_IS_CLK_ENABLED -#define __I2C3_IS_CLK_DISABLED __HAL_RCC_I2C3_IS_CLK_DISABLED -#define __PWR_IS_CLK_ENABLED __HAL_RCC_PWR_IS_CLK_ENABLED -#define __PWR_IS_CLK_DISABLED __HAL_RCC_PWR_IS_CLK_DISABLED -#define __SYSCFG_IS_CLK_ENABLED __HAL_RCC_SYSCFG_IS_CLK_ENABLED -#define __SYSCFG_IS_CLK_DISABLED __HAL_RCC_SYSCFG_IS_CLK_DISABLED -#define __SPI1_IS_CLK_ENABLED __HAL_RCC_SPI1_IS_CLK_ENABLED -#define __SPI1_IS_CLK_DISABLED __HAL_RCC_SPI1_IS_CLK_DISABLED -#define __SPI2_IS_CLK_ENABLED __HAL_RCC_SPI2_IS_CLK_ENABLED -#define __SPI2_IS_CLK_DISABLED __HAL_RCC_SPI2_IS_CLK_DISABLED -#define __SPI3_IS_CLK_ENABLED __HAL_RCC_SPI3_IS_CLK_ENABLED -#define __SPI3_IS_CLK_DISABLED __HAL_RCC_SPI3_IS_CLK_DISABLED -#define __SPI4_IS_CLK_ENABLED __HAL_RCC_SPI4_IS_CLK_ENABLED -#define __SPI4_IS_CLK_DISABLED __HAL_RCC_SPI4_IS_CLK_DISABLED -#define __SDADC1_IS_CLK_ENABLED __HAL_RCC_SDADC1_IS_CLK_ENABLED -#define __SDADC1_IS_CLK_DISABLED __HAL_RCC_SDADC1_IS_CLK_DISABLED -#define __SDADC2_IS_CLK_ENABLED __HAL_RCC_SDADC2_IS_CLK_ENABLED -#define __SDADC2_IS_CLK_DISABLED __HAL_RCC_SDADC2_IS_CLK_DISABLED -#define __SDADC3_IS_CLK_ENABLED __HAL_RCC_SDADC3_IS_CLK_ENABLED -#define __SDADC3_IS_CLK_DISABLED __HAL_RCC_SDADC3_IS_CLK_DISABLED -#define __SRAM_IS_CLK_ENABLED __HAL_RCC_SRAM_IS_CLK_ENABLED -#define __SRAM_IS_CLK_DISABLED __HAL_RCC_SRAM_IS_CLK_DISABLED -#define __TIM1_IS_CLK_ENABLED __HAL_RCC_TIM1_IS_CLK_ENABLED -#define __TIM1_IS_CLK_DISABLED __HAL_RCC_TIM1_IS_CLK_DISABLED -#define __TIM2_IS_CLK_ENABLED __HAL_RCC_TIM2_IS_CLK_ENABLED -#define __TIM2_IS_CLK_DISABLED __HAL_RCC_TIM2_IS_CLK_DISABLED -#define __TIM3_IS_CLK_ENABLED __HAL_RCC_TIM3_IS_CLK_ENABLED -#define __TIM3_IS_CLK_DISABLED __HAL_RCC_TIM3_IS_CLK_DISABLED -#define __TIM4_IS_CLK_ENABLED __HAL_RCC_TIM4_IS_CLK_ENABLED -#define __TIM4_IS_CLK_DISABLED __HAL_RCC_TIM4_IS_CLK_DISABLED -#define __TIM5_IS_CLK_ENABLED __HAL_RCC_TIM5_IS_CLK_ENABLED -#define __TIM5_IS_CLK_DISABLED __HAL_RCC_TIM5_IS_CLK_DISABLED -#define __TIM6_IS_CLK_ENABLED __HAL_RCC_TIM6_IS_CLK_ENABLED -#define __TIM6_IS_CLK_DISABLED __HAL_RCC_TIM6_IS_CLK_DISABLED -#define __TIM7_IS_CLK_ENABLED __HAL_RCC_TIM7_IS_CLK_ENABLED -#define __TIM7_IS_CLK_DISABLED __HAL_RCC_TIM7_IS_CLK_DISABLED -#define __TIM8_IS_CLK_ENABLED __HAL_RCC_TIM8_IS_CLK_ENABLED -#define __TIM8_IS_CLK_DISABLED __HAL_RCC_TIM8_IS_CLK_DISABLED -#define __TIM12_IS_CLK_ENABLED __HAL_RCC_TIM12_IS_CLK_ENABLED -#define __TIM12_IS_CLK_DISABLED __HAL_RCC_TIM12_IS_CLK_DISABLED -#define __TIM13_IS_CLK_ENABLED __HAL_RCC_TIM13_IS_CLK_ENABLED -#define __TIM13_IS_CLK_DISABLED __HAL_RCC_TIM13_IS_CLK_DISABLED -#define __TIM14_IS_CLK_ENABLED __HAL_RCC_TIM14_IS_CLK_ENABLED -#define __TIM14_IS_CLK_DISABLED __HAL_RCC_TIM14_IS_CLK_DISABLED -#define __TIM15_IS_CLK_ENABLED __HAL_RCC_TIM15_IS_CLK_ENABLED -#define __TIM15_IS_CLK_DISABLED __HAL_RCC_TIM15_IS_CLK_DISABLED -#define __TIM16_IS_CLK_ENABLED __HAL_RCC_TIM16_IS_CLK_ENABLED -#define __TIM16_IS_CLK_DISABLED __HAL_RCC_TIM16_IS_CLK_DISABLED -#define __TIM17_IS_CLK_ENABLED __HAL_RCC_TIM17_IS_CLK_ENABLED -#define __TIM17_IS_CLK_DISABLED __HAL_RCC_TIM17_IS_CLK_DISABLED -#define __TIM18_IS_CLK_ENABLED __HAL_RCC_TIM18_IS_CLK_ENABLED -#define __TIM18_IS_CLK_DISABLED __HAL_RCC_TIM18_IS_CLK_DISABLED -#define __TIM19_IS_CLK_ENABLED __HAL_RCC_TIM19_IS_CLK_ENABLED -#define __TIM19_IS_CLK_DISABLED __HAL_RCC_TIM19_IS_CLK_DISABLED -#define __TIM20_IS_CLK_ENABLED __HAL_RCC_TIM20_IS_CLK_ENABLED -#define __TIM20_IS_CLK_DISABLED __HAL_RCC_TIM20_IS_CLK_DISABLED -#define __TSC_IS_CLK_ENABLED __HAL_RCC_TSC_IS_CLK_ENABLED -#define __TSC_IS_CLK_DISABLED __HAL_RCC_TSC_IS_CLK_DISABLED -#define __UART4_IS_CLK_ENABLED __HAL_RCC_UART4_IS_CLK_ENABLED -#define __UART4_IS_CLK_DISABLED __HAL_RCC_UART4_IS_CLK_DISABLED -#define __UART5_IS_CLK_ENABLED __HAL_RCC_UART5_IS_CLK_ENABLED -#define __UART5_IS_CLK_DISABLED __HAL_RCC_UART5_IS_CLK_DISABLED -#define __USART1_IS_CLK_ENABLED __HAL_RCC_USART1_IS_CLK_ENABLED -#define __USART1_IS_CLK_DISABLED __HAL_RCC_USART1_IS_CLK_DISABLED -#define __USART2_IS_CLK_ENABLED __HAL_RCC_USART2_IS_CLK_ENABLED -#define __USART2_IS_CLK_DISABLED __HAL_RCC_USART2_IS_CLK_DISABLED -#define __USART3_IS_CLK_ENABLED __HAL_RCC_USART3_IS_CLK_ENABLED -#define __USART3_IS_CLK_DISABLED __HAL_RCC_USART3_IS_CLK_DISABLED -#define __USB_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED -#define __USB_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED -#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED -#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED - -#if defined(STM32L1) -#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE -#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE -#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE -#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET -#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET -#endif /* STM32L1 */ - -#if defined(STM32F4) -#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET -#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDMMC1_CLK_ENABLE __HAL_RCC_SDIO_CLK_ENABLE -#define __HAL_RCC_SDMMC1_CLK_DISABLE __HAL_RCC_SDIO_CLK_DISABLE -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED __HAL_RCC_SDIO_IS_CLK_ENABLED -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED __HAL_RCC_SDIO_IS_CLK_DISABLED -#define Sdmmc1ClockSelection SdioClockSelection -#define RCC_PERIPHCLK_SDMMC1 RCC_PERIPHCLK_SDIO -#define RCC_SDMMC1CLKSOURCE_CLK48 RCC_SDIOCLKSOURCE_CK48 -#define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_SDIOCLKSOURCE_SYSCLK -#define __HAL_RCC_SDMMC1_CONFIG __HAL_RCC_SDIO_CONFIG -#define __HAL_RCC_GET_SDMMC1_SOURCE __HAL_RCC_GET_SDIO_SOURCE -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define __HAL_RCC_SDIO_FORCE_RESET __HAL_RCC_SDMMC1_FORCE_RESET -#define __HAL_RCC_SDIO_RELEASE_RESET __HAL_RCC_SDMMC1_RELEASE_RESET -#define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE -#define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE -#define __HAL_RCC_SDIO_CLK_ENABLE __HAL_RCC_SDMMC1_CLK_ENABLE -#define __HAL_RCC_SDIO_CLK_DISABLE __HAL_RCC_SDMMC1_CLK_DISABLE -#define __HAL_RCC_SDIO_IS_CLK_ENABLED __HAL_RCC_SDMMC1_IS_CLK_ENABLED -#define __HAL_RCC_SDIO_IS_CLK_DISABLED __HAL_RCC_SDMMC1_IS_CLK_DISABLED -#define SdioClockSelection Sdmmc1ClockSelection -#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1 -#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG -#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE -#endif - -#if defined(STM32F7) -#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48 -#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK -#endif - -#if defined(STM32H7) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE() - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE() -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET() -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE() -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE() -#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE() -#endif - -#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG -#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG - -#define __RCC_PLLSRC RCC_GET_PLL_OSCSOURCE - -#define IS_RCC_MSIRANGE IS_RCC_MSI_CLOCK_RANGE -#define IS_RCC_RTCCLK_SOURCE IS_RCC_RTCCLKSOURCE -#define IS_RCC_SYSCLK_DIV IS_RCC_HCLK -#define IS_RCC_HCLK_DIV IS_RCC_PCLK -#define IS_RCC_PERIPHCLK IS_RCC_PERIPHCLOCK - -#define RCC_IT_HSI14 RCC_IT_HSI14RDY - -#define RCC_IT_CSSLSE RCC_IT_LSECSS -#define RCC_IT_CSSHSE RCC_IT_CSS - -#define RCC_PLLMUL_3 RCC_PLL_MUL3 -#define RCC_PLLMUL_4 RCC_PLL_MUL4 -#define RCC_PLLMUL_6 RCC_PLL_MUL6 -#define RCC_PLLMUL_8 RCC_PLL_MUL8 -#define RCC_PLLMUL_12 RCC_PLL_MUL12 -#define RCC_PLLMUL_16 RCC_PLL_MUL16 -#define RCC_PLLMUL_24 RCC_PLL_MUL24 -#define RCC_PLLMUL_32 RCC_PLL_MUL32 -#define RCC_PLLMUL_48 RCC_PLL_MUL48 - -#define RCC_PLLDIV_2 RCC_PLL_DIV2 -#define RCC_PLLDIV_3 RCC_PLL_DIV3 -#define RCC_PLLDIV_4 RCC_PLL_DIV4 - -#define IS_RCC_MCOSOURCE IS_RCC_MCO1SOURCE -#define __HAL_RCC_MCO_CONFIG __HAL_RCC_MCO1_CONFIG -#define RCC_MCO_NODIV RCC_MCODIV_1 -#define RCC_MCO_DIV1 RCC_MCODIV_1 -#define RCC_MCO_DIV2 RCC_MCODIV_2 -#define RCC_MCO_DIV4 RCC_MCODIV_4 -#define RCC_MCO_DIV8 RCC_MCODIV_8 -#define RCC_MCO_DIV16 RCC_MCODIV_16 -#define RCC_MCO_DIV32 RCC_MCODIV_32 -#define RCC_MCO_DIV64 RCC_MCODIV_64 -#define RCC_MCO_DIV128 RCC_MCODIV_128 -#define RCC_MCOSOURCE_NONE RCC_MCO1SOURCE_NOCLOCK -#define RCC_MCOSOURCE_LSI RCC_MCO1SOURCE_LSI -#define RCC_MCOSOURCE_LSE RCC_MCO1SOURCE_LSE -#define RCC_MCOSOURCE_SYSCLK RCC_MCO1SOURCE_SYSCLK -#define RCC_MCOSOURCE_HSI RCC_MCO1SOURCE_HSI -#define RCC_MCOSOURCE_HSI14 RCC_MCO1SOURCE_HSI14 -#define RCC_MCOSOURCE_HSI48 RCC_MCO1SOURCE_HSI48 -#define RCC_MCOSOURCE_HSE RCC_MCO1SOURCE_HSE -#define RCC_MCOSOURCE_PLLCLK_DIV1 RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK -#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 - -#if defined(STM32U0) -#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK -#endif - -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0) -#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE -#else -#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK -#endif - -#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1 -#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL -#define RCC_USBCLK_MSI RCC_USBCLKSOURCE_MSI -#define RCC_USBCLKSOURCE_PLLCLK RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1 RCC_USBCLKSOURCE_PLL -#define RCC_USBPLLCLK_DIV1_5 RCC_USBCLKSOURCE_PLL_DIV1_5 -#define RCC_USBPLLCLK_DIV2 RCC_USBCLKSOURCE_PLL_DIV2 -#define RCC_USBPLLCLK_DIV3 RCC_USBCLKSOURCE_PLL_DIV3 - -#define HSION_BitNumber RCC_HSION_BIT_NUMBER -#define HSION_BITNUMBER RCC_HSION_BIT_NUMBER -#define HSEON_BitNumber RCC_HSEON_BIT_NUMBER -#define HSEON_BITNUMBER RCC_HSEON_BIT_NUMBER -#define MSION_BITNUMBER RCC_MSION_BIT_NUMBER -#define CSSON_BitNumber RCC_CSSON_BIT_NUMBER -#define CSSON_BITNUMBER RCC_CSSON_BIT_NUMBER -#define PLLON_BitNumber RCC_PLLON_BIT_NUMBER -#define PLLON_BITNUMBER RCC_PLLON_BIT_NUMBER -#define PLLI2SON_BitNumber RCC_PLLI2SON_BIT_NUMBER -#define I2SSRC_BitNumber RCC_I2SSRC_BIT_NUMBER -#define RTCEN_BitNumber RCC_RTCEN_BIT_NUMBER -#define RTCEN_BITNUMBER RCC_RTCEN_BIT_NUMBER -#define BDRST_BitNumber RCC_BDRST_BIT_NUMBER -#define BDRST_BITNUMBER RCC_BDRST_BIT_NUMBER -#define RTCRST_BITNUMBER RCC_RTCRST_BIT_NUMBER -#define LSION_BitNumber RCC_LSION_BIT_NUMBER -#define LSION_BITNUMBER RCC_LSION_BIT_NUMBER -#define LSEON_BitNumber RCC_LSEON_BIT_NUMBER -#define LSEON_BITNUMBER RCC_LSEON_BIT_NUMBER -#define LSEBYP_BITNUMBER RCC_LSEBYP_BIT_NUMBER -#define PLLSAION_BitNumber RCC_PLLSAION_BIT_NUMBER -#define TIMPRE_BitNumber RCC_TIMPRE_BIT_NUMBER -#define RMVF_BitNumber RCC_RMVF_BIT_NUMBER -#define RMVF_BITNUMBER RCC_RMVF_BIT_NUMBER -#define RCC_CR2_HSI14TRIM_BitNumber RCC_HSI14TRIM_BIT_NUMBER -#define CR_BYTE2_ADDRESS RCC_CR_BYTE2_ADDRESS -#define CIR_BYTE1_ADDRESS RCC_CIR_BYTE1_ADDRESS -#define CIR_BYTE2_ADDRESS RCC_CIR_BYTE2_ADDRESS -#define BDCR_BYTE0_ADDRESS RCC_BDCR_BYTE0_ADDRESS -#define DBP_TIMEOUT_VALUE RCC_DBP_TIMEOUT_VALUE -#define LSE_TIMEOUT_VALUE RCC_LSE_TIMEOUT_VALUE - -#define CR_HSION_BB RCC_CR_HSION_BB -#define CR_CSSON_BB RCC_CR_CSSON_BB -#define CR_PLLON_BB RCC_CR_PLLON_BB -#define CR_PLLI2SON_BB RCC_CR_PLLI2SON_BB -#define CR_MSION_BB RCC_CR_MSION_BB -#define CSR_LSION_BB RCC_CSR_LSION_BB -#define CSR_LSEON_BB RCC_CSR_LSEON_BB -#define CSR_LSEBYP_BB RCC_CSR_LSEBYP_BB -#define CSR_RTCEN_BB RCC_CSR_RTCEN_BB -#define CSR_RTCRST_BB RCC_CSR_RTCRST_BB -#define CFGR_I2SSRC_BB RCC_CFGR_I2SSRC_BB -#define BDCR_RTCEN_BB RCC_BDCR_RTCEN_BB -#define BDCR_BDRST_BB RCC_BDCR_BDRST_BB -#define CR_HSEON_BB RCC_CR_HSEON_BB -#define CSR_RMVF_BB RCC_CSR_RMVF_BB -#define CR_PLLSAION_BB RCC_CR_PLLSAION_BB -#define DCKCFGR_TIMPRE_BB RCC_DCKCFGR_TIMPRE_BB - -#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE -#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE -#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE -#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE -#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE - -#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT - -#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN -#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF - -#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48 -#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ -#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP -#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ -#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE -#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48 - -#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE -#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED -#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET -#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET -#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE -#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED -#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED -#define DfsdmClockSelection Dfsdm1ClockSelection -#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1 -#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK -#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG -#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE -#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 -#if !defined(STM32U0) -#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 -#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 -#endif - -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1 -#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2 -#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2 -#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2 -#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1 -#if defined(STM32U5) -#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL -#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL -#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE -#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE -#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE -#define __HAL_RCC_AHB21_CLK_Disable_Clear __HAL_RCC_AHB2_1_CLK_ENABLE -#define __HAL_RCC_AHB22_CLK_Disable_Clear __HAL_RCC_AHB2_2_CLK_ENABLE -#define __HAL_RCC_AHB3_CLK_Disable_Clear __HAL_RCC_AHB3_CLK_ENABLE -#define __HAL_RCC_APB1_CLK_Disable_Clear __HAL_RCC_APB1_CLK_ENABLE -#define __HAL_RCC_APB2_CLK_Disable_Clear __HAL_RCC_APB2_CLK_ENABLE -#define __HAL_RCC_APB3_CLK_Disable_Clear __HAL_RCC_APB3_CLK_ENABLE -#define IS_RCC_MSIPLLModeSelection IS_RCC_MSIPLLMODE_SELECT -#define RCC_PERIPHCLK_CLK48 RCC_PERIPHCLK_ICLK -#define RCC_CLK48CLKSOURCE_HSI48 RCC_ICLK_CLKSOURCE_HSI48 -#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2 -#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1 -#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK -#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE -#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE -#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED -#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED -#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET -#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET -#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE -#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE -#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE -#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE -#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE -#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG -#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE -#endif /* STM32U5 */ - -#if defined(STM32H5) -#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE -#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE -#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG -#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE - -#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE -#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI -#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI -#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE -#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 -#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 -#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 -#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 -#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE -#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM - -#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE -#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE -#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE -#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE -#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE -#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE -#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE -#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE -#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE -#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE - -#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE -#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE -#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE -#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE -#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG -#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG -#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG -#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE -#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE -#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE -#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE -#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE -#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG - -#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE -#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE -#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE -#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE -#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG -#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG - -#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE -#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE -#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE -#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE -#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG -#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG - -#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 -#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 -#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 -#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 - -#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE -#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM - -#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE -#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI -#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI -#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE - -#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 -#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 -#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 -#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 - -#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE -#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM - -#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE -#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI -#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI -#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE - - -#endif /* STM32H5 */ - -/** - * @} - */ - -/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose - * @{ - */ -#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit) - -/** - * @} - */ - -/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ - defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0) -#else -#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG -#endif -#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT -#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT - -#if defined (STM32F1) -#define __HAL_RTC_EXTI_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() - -#define __HAL_RTC_EXTI_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_ENABLE_IT() - -#define __HAL_RTC_EXTI_DISABLE_IT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_DISABLE_IT() - -#define __HAL_RTC_EXTI_GET_FLAG(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GET_FLAG() - -#define __HAL_RTC_EXTI_GENERATE_SWIT(RTC_EXTI_LINE_ALARM_EVENT) __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() -#else -#define __HAL_RTC_EXTI_CLEAR_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_CLEAR_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_CLEAR_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_CLEAR_FLAG())) -#define __HAL_RTC_EXTI_ENABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_ENABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_ENABLE_IT())) -#define __HAL_RTC_EXTI_DISABLE_IT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_DISABLE_IT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_DISABLE_IT())) -#define __HAL_RTC_EXTI_GET_FLAG(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GET_FLAG() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GET_FLAG() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG())) -#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTI_LINE__) (((__EXTI_LINE__) == RTC_EXTI_LINE_ALARM_EVENT) ? __HAL_RTC_ALARM_EXTI_GENERATE_SWIT() : \ - (((__EXTI_LINE__) == RTC_EXTI_LINE_WAKEUPTIMER_EVENT) ? __HAL_RTC_WAKEUPTIMER_EXTI_GENERATE_SWIT() : \ - __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) -#endif /* STM32F1 */ - -#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ - defined (STM32H7) || \ - defined (STM32L0) || defined (STM32L1) || \ - defined (STM32WB) -#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG -#endif - -#define IS_ALARM IS_RTC_ALARM -#define IS_ALARM_MASK IS_RTC_ALARM_MASK -#define IS_TAMPER IS_RTC_TAMPER -#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE -#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER -#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT -#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE -#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION -#define IS_TAMPER_PULLUP_STATE IS_RTC_TAMPER_PULLUP_STATE -#define IS_TAMPER_SAMPLING_FREQ IS_RTC_TAMPER_SAMPLING_FREQ -#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION IS_RTC_TAMPER_TIMESTAMPONTAMPER_DETECTION -#define IS_TAMPER_TRIGGER IS_RTC_TAMPER_TRIGGER -#define IS_WAKEUP_CLOCK IS_RTC_WAKEUP_CLOCK -#define IS_WAKEUP_COUNTER IS_RTC_WAKEUP_COUNTER - -#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE -#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE - -#if defined (STM32H5) -#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE -#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE -#endif /* STM32H5 */ - -/** - * @} - */ - -/** @defgroup HAL_SD_Aliased_Macros HAL SD/MMC Aliased Macros maintained for legacy purpose - * @{ - */ - -#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE -#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS - -#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1) -#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE -#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE -#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE - -#define SDMMC_NSpeed_CLK_DIV SDMMC_NSPEED_CLK_DIV -#define SDMMC_HSpeed_CLK_DIV SDMMC_HSPEED_CLK_DIV -#endif - -#if defined(STM32F4) || defined(STM32F2) -#define SD_SDMMC_DISABLED SD_SDIO_DISABLED -#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY -#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED -#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION -#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND -#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT -#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED -#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE -#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE -#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE -#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL -#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT -#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT -#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG -#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG -#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT -#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT -#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS -#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT -#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND -/* alias CMSIS */ -#define SDMMC1_IRQn SDIO_IRQn -#define SDMMC1_IRQHandler SDIO_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32L4) -#define SD_SDIO_DISABLED SD_SDMMC_DISABLED -#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY -#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED -#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION -#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND -#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT -#define SD_CMD_SDIO_RW_EXTENDED SD_CMD_SDMMC_RW_EXTENDED -#define __HAL_SD_SDIO_ENABLE __HAL_SD_SDMMC_ENABLE -#define __HAL_SD_SDIO_DISABLE __HAL_SD_SDMMC_DISABLE -#define __HAL_SD_SDIO_DMA_ENABLE __HAL_SD_SDMMC_DMA_ENABLE -#define __HAL_SD_SDIO_DMA_DISABL __HAL_SD_SDMMC_DMA_DISABLE -#define __HAL_SD_SDIO_ENABLE_IT __HAL_SD_SDMMC_ENABLE_IT -#define __HAL_SD_SDIO_DISABLE_IT __HAL_SD_SDMMC_DISABLE_IT -#define __HAL_SD_SDIO_GET_FLAG __HAL_SD_SDMMC_GET_FLAG -#define __HAL_SD_SDIO_CLEAR_FLAG __HAL_SD_SDMMC_CLEAR_FLAG -#define __HAL_SD_SDIO_GET_IT __HAL_SD_SDMMC_GET_IT -#define __HAL_SD_SDIO_CLEAR_IT __HAL_SD_SDMMC_CLEAR_IT -#define SDIO_STATIC_FLAGS SDMMC_STATIC_FLAGS -#define SDIO_CMD0TIMEOUT SDMMC_CMD0TIMEOUT -#define SD_SDIO_SEND_IF_COND SD_SDMMC_SEND_IF_COND -/* alias CMSIS for compatibilities */ -#define SDIO_IRQn SDMMC1_IRQn -#define SDIO_IRQHandler SDMMC1_IRQHandler -#endif - -#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7) -#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef -#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef -#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef -#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef -#endif - -#if defined(STM32H7) || defined(STM32L5) -#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback -#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback -#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback -#define HAL_SD_DriveTransciver_1_8V_Callback HAL_SD_DriveTransceiver_1_8V_Callback -#endif -/** - * @} - */ - -/** @defgroup HAL_SMARTCARD_Aliased_Macros HAL SMARTCARD Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __SMARTCARD_ENABLE_IT __HAL_SMARTCARD_ENABLE_IT -#define __SMARTCARD_DISABLE_IT __HAL_SMARTCARD_DISABLE_IT -#define __SMARTCARD_ENABLE __HAL_SMARTCARD_ENABLE -#define __SMARTCARD_DISABLE __HAL_SMARTCARD_DISABLE -#define __SMARTCARD_DMA_REQUEST_ENABLE __HAL_SMARTCARD_DMA_REQUEST_ENABLE -#define __SMARTCARD_DMA_REQUEST_DISABLE __HAL_SMARTCARD_DMA_REQUEST_DISABLE - -#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE -#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE - -#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE - -/** - * @} - */ - -/** @defgroup HAL_SMBUS_Aliased_Macros HAL SMBUS Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_SMBUS_RESET_CR1 SMBUS_RESET_CR1 -#define __HAL_SMBUS_RESET_CR2 SMBUS_RESET_CR2 -#define __HAL_SMBUS_GENERATE_START SMBUS_GENERATE_START -#define __HAL_SMBUS_GET_ADDR_MATCH SMBUS_GET_ADDR_MATCH -#define __HAL_SMBUS_GET_DIR SMBUS_GET_DIR -#define __HAL_SMBUS_GET_STOP_MODE SMBUS_GET_STOP_MODE -#define __HAL_SMBUS_GET_PEC_MODE SMBUS_GET_PEC_MODE -#define __HAL_SMBUS_GET_ALERT_ENABLED SMBUS_GET_ALERT_ENABLED -/** - * @} - */ - -/** @defgroup HAL_SPI_Aliased_Macros HAL SPI Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_SPI_1LINE_TX SPI_1LINE_TX -#define __HAL_SPI_1LINE_RX SPI_1LINE_RX -#define __HAL_SPI_RESET_CRC SPI_RESET_CRC - -/** - * @} - */ - -/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __HAL_UART_MASK_COMPUTATION UART_MASK_COMPUTATION -#define __UART_GETCLOCKSOURCE UART_GETCLOCKSOURCE -#define __UART_MASK_COMPUTATION UART_MASK_COMPUTATION - -#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD - -#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE -#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE - -/** - * @} - */ - - -/** @defgroup HAL_USART_Aliased_Macros HAL USART Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __USART_ENABLE_IT __HAL_USART_ENABLE_IT -#define __USART_DISABLE_IT __HAL_USART_DISABLE_IT -#define __USART_ENABLE __HAL_USART_ENABLE -#define __USART_DISABLE __HAL_USART_DISABLE - -#define __HAL_USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE -#define __USART_GETCLOCKSOURCE USART_GETCLOCKSOURCE - -#if defined(STM32F0) || defined(STM32F3) || defined(STM32F7) -#define USART_OVERSAMPLING_16 0x00000000U -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 - -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) -#endif /* STM32F0 || STM32F3 || STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_USB_Aliased_Macros HAL USB Aliased Macros maintained for legacy purpose - * @{ - */ -#define USB_EXTI_LINE_WAKEUP USB_WAKEUP_EXTI_LINE - -#define USB_FS_EXTI_TRIGGER_RISING_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE -#define USB_FS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE -#define USB_FS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_FS_EXTI_LINE_WAKEUP USB_OTG_FS_WAKEUP_EXTI_LINE - -#define USB_HS_EXTI_TRIGGER_RISING_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE -#define USB_HS_EXTI_TRIGGER_FALLING_EDGE USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE -#define USB_HS_EXTI_TRIGGER_BOTH_EDGE USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE -#define USB_HS_EXTI_LINE_WAKEUP USB_OTG_HS_WAKEUP_EXTI_LINE - -#define __HAL_USB_EXTI_ENABLE_IT __HAL_USB_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_EXTI_DISABLE_IT __HAL_USB_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_EXTI_GET_FLAG __HAL_USB_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_EXTI_CLEAR_FLAG __HAL_USB_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE - -#define __HAL_USB_FS_EXTI_ENABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_FS_EXTI_DISABLE_IT __HAL_USB_OTG_FS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_FS_EXTI_GET_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_FS_EXTI_CLEAR_FLAG __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_FS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_FS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_FS_EXTI_GENERATE_SWIT __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT - -#define __HAL_USB_HS_EXTI_ENABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT -#define __HAL_USB_HS_EXTI_DISABLE_IT __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT -#define __HAL_USB_HS_EXTI_GET_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG -#define __HAL_USB_HS_EXTI_CLEAR_FLAG __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_USB_HS_EXTI_SET_RISING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE -#define __HAL_USB_HS_EXTI_SET_FALLINGRISING_TRIGGER __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE -#define __HAL_USB_HS_EXTI_GENERATE_SWIT __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT - -#define HAL_PCD_ActiveRemoteWakeup HAL_PCD_ActivateRemoteWakeup -#define HAL_PCD_DeActiveRemoteWakeup HAL_PCD_DeActivateRemoteWakeup - -#define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo -#define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo -/** - * @} - */ - -/** @defgroup HAL_TIM_Aliased_Macros HAL TIM Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_TIM_SetICPrescalerValue TIM_SET_ICPRESCALERVALUE -#define __HAL_TIM_ResetICPrescalerValue TIM_RESET_ICPRESCALERVALUE - -#define TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE -#define TIM_GET_CLEAR_IT __HAL_TIM_CLEAR_IT - -#define __HAL_TIM_GET_ITSTATUS __HAL_TIM_GET_IT_SOURCE - -#define __HAL_TIM_DIRECTION_STATUS __HAL_TIM_IS_TIM_COUNTING_DOWN -#define __HAL_TIM_PRESCALER __HAL_TIM_SET_PRESCALER -#define __HAL_TIM_SetCounter __HAL_TIM_SET_COUNTER -#define __HAL_TIM_GetCounter __HAL_TIM_GET_COUNTER -#define __HAL_TIM_SetAutoreload __HAL_TIM_SET_AUTORELOAD -#define __HAL_TIM_GetAutoreload __HAL_TIM_GET_AUTORELOAD -#define __HAL_TIM_SetClockDivision __HAL_TIM_SET_CLOCKDIVISION -#define __HAL_TIM_GetClockDivision __HAL_TIM_GET_CLOCKDIVISION -#define __HAL_TIM_SetICPrescaler __HAL_TIM_SET_ICPRESCALER -#define __HAL_TIM_GetICPrescaler __HAL_TIM_GET_ICPRESCALER -#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE -#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE - -#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 - -#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 -/** - * @} - */ - -/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose - * @{ - */ - -#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT -#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT -#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG -#define __HAL_ETH_EXTI_CLEAR_FLAG __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG -#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER -#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER - -#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE -#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE -#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE -/** - * @} - */ - -/** @defgroup HAL_LTDC_Aliased_Macros HAL LTDC Aliased Macros maintained for legacy purpose - * @{ - */ -#define __HAL_LTDC_LAYER LTDC_LAYER -#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG -/** - * @} - */ - -/** @defgroup HAL_SAI_Aliased_Macros HAL SAI Aliased Macros maintained for legacy purpose - * @{ - */ -#define SAI_OUTPUTDRIVE_DISABLED SAI_OUTPUTDRIVE_DISABLE -#define SAI_OUTPUTDRIVE_ENABLED SAI_OUTPUTDRIVE_ENABLE -#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE -#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE -#define SAI_STREOMODE SAI_STEREOMODE -#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY -#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL -#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL -#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL -#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL -#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL -#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE -#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1 -#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE -/** - * @} - */ - -/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined(STM32H7) -#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow -#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT -#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA -#endif -/** - * @} - */ - -/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose - * @{ - */ -#if defined (STM32H7) || defined (STM32G4) || defined (STM32F3) -#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT -#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA -#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart -#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT -#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA -#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop -#endif -/** - * @} - */ - -/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32L4) || defined (STM32F4) || defined (STM32F7) || defined(STM32H7) -#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE -#endif /* STM32L4 || STM32F4 || STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_Generic_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose - * @{ - */ -#if defined (STM32F7) -#define ART_ACCLERATOR_ENABLE ART_ACCELERATOR_ENABLE -#endif /* STM32F7 */ -/** - * @} - */ - -/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose - * @{ - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32_HAL_LEGACY */ - - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h deleted file mode 100644 index 08fef12a8..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal.h +++ /dev/null @@ -1,832 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal.h - * @author MCD Application Team - * @brief This file contains all the functions prototypes for the HAL - * module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32U5xx_HAL_H -#define __STM32U5xx_HAL_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_conf.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup HAL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup HAL_Exported_Types HAL Exported Types - * @{ - */ - -/** @defgroup HAL_TICK_FREQ Tick Frequency - * @{ - */ -typedef enum -{ - HAL_TICK_FREQ_10HZ = 100U, - HAL_TICK_FREQ_100HZ = 10U, - HAL_TICK_FREQ_1KHZ = 1U, - HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ -} HAL_TickFreqTypeDef; -/** - * @} - */ - -/** - * @} - */ - -/* Exported variables --------------------------------------------------------*/ -/** @defgroup HAL_Exported_Variables HAL Exported Variables - * @{ - */ -extern __IO uint32_t uwTick; -extern uint32_t uwTickPrio; -extern HAL_TickFreqTypeDef uwTickFreq; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup REV_ID device revision ID - * @{ - */ -#define REV_ID_A 0x1000U /*!< STM32U5 rev.A */ -#define REV_ID_B 0x2000U /*!< STM32U5 rev.B */ -/** - * @} - */ - - -/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants - * @{ - */ - -/** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts - * @{ - */ -#define SYSCFG_IT_FPU_IOC SYSCFG_FPUIMR_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ -#define SYSCFG_IT_FPU_DZC SYSCFG_FPUIMR_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ -#define SYSCFG_IT_FPU_UFC SYSCFG_FPUIMR_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ -#define SYSCFG_IT_FPU_OFC SYSCFG_FPUIMR_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ -#define SYSCFG_IT_FPU_IDC SYSCFG_FPUIMR_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ -#define SYSCFG_IT_FPU_IXC SYSCFG_FPUIMR_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ - -/** - * @} - */ - -/** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale - * @{ - */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 2 (VREF_OUT3) */ -#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 (VREFBUF_CSR_VRS_0 | VREFBUF_CSR_VRS_1) /*!< Voltage reference scale 3 (VREF_OUT4) */ - -/** - * @} - */ - -/** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance - * @{ - */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to - Voltage reference buffer output */ -#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ - -/** - * @} - */ - -/** @defgroup SYSCFG_flags_definition Flags - * @{ - */ - -#define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ -#define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ - -/** - * @} - */ - -/** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO - * @{ - */ - -/** @brief Fast-mode Plus driving capability on a specific GPIO - */ -#define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ -#define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ -#define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ -#define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ - -/** - * @} - */ - -/** @defgroup SYSCFG_Lock_items SYSCFG Lock items - * @brief SYSCFG items to set lock on - * @{ - */ -#define SYSCFG_MPU_NSEC SYSCFG_CNSLCKR_LOCKNSMPU /*!< Non-secure MPU lock (privileged secure or non-secure only) */ -#define SYSCFG_VTOR_NSEC SYSCFG_CNSLCKR_LOCKNSVTOR /*!< Non-secure VTOR lock (privileged secure or non-secure only) */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define SYSCFG_SAU (SYSCFG_CSLCKR_LOCKSAU << 16U) /*!< SAU lock (privileged secure code only) */ -#define SYSCFG_MPU_SEC (SYSCFG_CSLCKR_LOCKSMPU << 16U) /*!< Secure MPU lock (privileged secure code only) */ -#define SYSCFG_VTOR_AIRCR_SEC (SYSCFG_CSLCKR_LOCKSVTAIRCR << 16U) /*!< VTOR_S and AIRCR lock (privileged secure code only) */ -#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC|SYSCFG_SAU|SYSCFG_MPU_SEC|SYSCFG_VTOR_AIRCR_SEC) /*!< All */ -#else -#define SYSCFG_LOCK_ALL (SYSCFG_MPU_NSEC|SYSCFG_VTOR_NSEC) /*!< All (privileged secure or non-secure only) */ -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @defgroup SYSCFG_Attributes_items SYSCFG Attributes items - * @brief SYSCFG items to configure secure or non-secure attributes on - * @{ - */ -#define SYSCFG_CLK SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock control */ -#define SYSCFG_CLASSB SYSCFG_SECCFGR_CLASSBSEC /*!< Class B */ -#define SYSCFG_FPU SYSCFG_SECCFGR_FPUSEC /*!< FPU */ -#define SYSCFG_ALL (SYSCFG_CLK | SYSCFG_CLASSB | SYSCFG_FPU) /*!< All */ -/** - * @} - */ - -/** @defgroup SYSCFG_attributes SYSCFG attributes - * @brief SYSCFG secure or non-secure attributes - * @{ - */ -#define SYSCFG_SEC 0x00000001U /*!< Secure attribute */ -#define SYSCFG_NSEC 0x00000000U /*!< Non-secure attribute */ -/** - * @} - */ - -#endif /* __ARM_FEATURE_CMSE */ - -#ifdef SYSCFG_OTGHSPHYCR_EN -/** @defgroup SYSCFG_OTG_PHY_RefenceClockSelection OTG PHY Reference Clock Selection - * @{ - */ - -/** @brief OTG HS PHY reference clock frequency selection - */ -#define SYSCFG_OTG_HS_PHY_CLK_SELECT_1 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1) /*!< 16Mhz */ -#define SYSCFG_OTG_HS_PHY_CLK_SELECT_2 SYSCFG_OTGHSPHYCR_CLKSEL_3 /*!< 19.2Mhz */ -#define SYSCFG_OTG_HS_PHY_CLK_SELECT_3 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 20Mhz */ -#define SYSCFG_OTG_HS_PHY_CLK_SELECT_4 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 24Mhz */ -#define SYSCFG_OTG_HS_PHY_CLK_SELECT_5 (SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_2 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 26Mhz */ -#define SYSCFG_OTG_HS_PHY_CLK_SELECT_6 (SYSCFG_OTGHSPHYCR_CLKSEL_0 | SYSCFG_OTGHSPHYCR_CLKSEL_1 | SYSCFG_OTGHSPHYCR_CLKSEL_3) /*!< 32Mhz */ -/** - * @} - */ - -/** @defgroup SYSCFG_OTG_PHY_PowerDown OTG PHY Power Down - * @{ - */ - -/** @brief OTG HS PHY Power Down config - */ - -#define SYSCFG_OTG_HS_PHY_POWER_ON 0x00000000U /*!< PHY state machine, bias and OTG PHY PLL are powered down */ -#define SYSCFG_OTG_HS_PHY_POWER_DOWN SYSCFG_OTGHSPHYCR_PDCTRL /*!< PHY state machine, bias and OTG PHY PLL remain powered */ - -/** - * @} - */ - -/** @defgroup SYSCFG_OTG_PHY_Enable OTG PHY Enable - * @{ - */ - -#define SYSCFG_OTG_HS_PHY_UNDERRESET 0x00000000U /*!< PHY under reset */ -#define SYSCFG_OTG_HS_PHY_ENABLE SYSCFG_OTGHSPHYCR_EN /*!< PHY enabled */ - -/** - * @} - */ - -/** @defgroup SYSCFG_OTG_PHYTUNER_PreemphasisCurrent OTG PHYTUNER Preemphasis Current - * @{ - */ - -/** @brief High-speed (HS) transmitter preemphasis current control - */ -#define SYSCFG_OTG_HS_PHY_PREEMP_DISABLED 0x00000000U /*!< HS transmitter preemphasis circuit disabled */ -#define SYSCFG_OTG_HS_PHY_PREEMP_1X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 /*!< HS transmitter preemphasis circuit sources 1x preemphasis current */ -#define SYSCFG_OTG_HS_PHY_PREEMP_2X SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1 /*!< HS transmitter preemphasis circuit sources 2x preemphasis current */ -#define SYSCFG_OTG_HS_PHY_PREEMP_3X (SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_0 | SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE_1) /*!< HS transmitter preemphasis circuit sources 3x preemphasis current */ - -/** - * @} - */ - -/** @defgroup SYSCFG_OTG_PHYTUNER_SquelchThreshold OTG PHYTUNER Squelch Threshold - * @{ - */ - -/** @brief Squelch threshold adjustment - */ -#define SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT 0x00000000U /*!< +15% (recommended value) */ -#define SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT (SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_0 | SYSCFG_OTGHSPHYTUNER2_SQRXTUNE_1) /*!< 0% (default value) */ - -/** - * @} - */ - -/** @defgroup SYSCFG_OTG_PHYTUNER_DisconnectThreshold OTG PHYTUNER Disconnect Threshold - * @{ - */ - -/** @brief Disconnect threshold adjustment - */ -#define SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_1 /*!< +5.9% (recommended value) */ -#define SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE_0 /*!< 0% (default value) */ - -/** - * @} - */ - -#endif /* SYSCFG_OTGHSPHYCR_EN */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros - * @{ - */ - -/** @brief Freeze/Unfreeze Peripherals in Debug mode - */ -#if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM2_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM3_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM4_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM5_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM6_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_TIM7_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_WWDG_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_IWDG_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#define __HAL_DBGMCU_FREEZE_I2C1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_I2C1_STOP */ - -#if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#define __HAL_DBGMCU_FREEZE_I2C2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) -#endif /* DBGMCU_APB1FZR1_DBG_I2C2_STOP */ - -#if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#define __HAL_DBGMCU_FREEZE_I2C4() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C4() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) -#endif /* DBGMCU_APB1FZR2_DBG_I2C4_STOP */ - -#if defined(DBGMCU_APB1FZR2_DBG_I2C5_STOP) -#define __HAL_DBGMCU_FREEZE_I2C5() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C5() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C5_STOP) -#endif /* DBGMCU_APB1FZR2_DBG_I2C5_STOP */ - -#if defined(DBGMCU_APB1FZR2_DBG_I2C6_STOP) -#define __HAL_DBGMCU_FREEZE_I2C6() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C6() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C6_STOP) -#endif /* DBGMCU_APB1FZR2_DBG_I2C6_STOP */ - -#if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) -#endif /* DBGMCU_APB1FZR2_DBG_LPTIM2_STOP */ - -#if defined(DBGMCU_APB2FZR_DBG_TIM1_STOP) -#define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM1_STOP) -#endif /* DBGMCU_APB2FZR_DBG_TIM1_STOP */ - -#if defined(DBGMCU_APB2FZR_DBG_TIM8_STOP) -#define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM8_STOP) -#endif /* DBGMCU_APB2FZR_DBG_TIM8_STOP */ - -#if defined(DBGMCU_APB2FZR_DBG_TIM15_STOP) -#define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM15_STOP) -#endif /* DBGMCU_APB2FZR_DBG_TIM15_STOP */ - -#if defined(DBGMCU_APB2FZR_DBG_TIM16_STOP) -#define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM16_STOP) -#endif /* DBGMCU_APB2FZR_DBG_TIM16_STOP */ - -#if defined(DBGMCU_APB2FZR_DBG_TIM17_STOP) -#define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) -#define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZR, DBGMCU_APB2FZR_DBG_TIM17_STOP) -#endif /* DBGMCU_APB2FZR_DBG_TIM17_STOP */ - -#if defined(DBGMCU_APB3FZR_DBG_I2C3_STOP) -#define __HAL_DBGMCU_FREEZE_I2C3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) -#define __HAL_DBGMCU_UNFREEZE_I2C3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_I2C3_STOP) -#endif /* DBGMCU_APB3FZR_DBG_I2C3_STOP */ - -#if defined(DBGMCU_APB3FZR_DBG_LPTIM1_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM1_STOP) -#endif /* DBGMCU_APB3FZR_DBG_LPTIM1_STOP */ - -#if defined(DBGMCU_APB3FZR_DBG_LPTIM3_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM3() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM3() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM3_STOP) -#endif /* DBGMCU_APB3FZR_DBG_LPTIM3_STOP */ - -#if defined(DBGMCU_APB3FZR_DBG_LPTIM4_STOP) -#define __HAL_DBGMCU_FREEZE_LPTIM4() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPTIM4() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_LPTIM4_STOP) -#endif /* DBGMCU_APB3FZR_DBG_LPTIM4_STOP */ - -#if defined(DBGMCU_APB3FZR_DBG_RTC_STOP) -#define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) -#define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB3FZR, DBGMCU_APB3FZR_DBG_RTC_STOP) -#endif /* DBGMCU_APB3FZR_DBG_RTC_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA0() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA0() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA0_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA0_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA1() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA1() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA1_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA1_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA2() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA2() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA2_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA2_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA3() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA3() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA3_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA3_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA4() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA4() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA4_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA4_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA5() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA5() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA5_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA5_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA6() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA6() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA6_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA6_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA7() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA7() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA7_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA7_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA8() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA8() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA8_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA8_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA9() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA9() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA9_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA9_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA10() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA10() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA10_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA10_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA11() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA11() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA11_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA11_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA12() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA12() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA12_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA12_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA13() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA13() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA13_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA13_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA14() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA14() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA14_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA14_STOP */ - -#if defined(DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) -#define __HAL_DBGMCU_FREEZE_GPDMA15() SET_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) -#define __HAL_DBGMCU_UNFREEZE_GPDMA15() CLEAR_BIT(DBGMCU->AHB1FZR, DBGMCU_AHB1FZR_DBG_GPDMA15_STOP) -#endif /* DBGMCU_AHB1FZR_DBG_GPDMA15_STOP */ - -#if defined(DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) -#define __HAL_DBGMCU_FREEZE_LPDMA0() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPDMA0() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA0_STOP) -#endif /* DBGMCU_AHB3FZR_DBG_LPDMA0_STOP */ - -#if defined(DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) -#define __HAL_DBGMCU_FREEZE_LPDMA1() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPDMA1() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA1_STOP) -#endif /* DBGMCU_AHB3FZR_DBG_LPDMA1_STOP */ - -#if defined(DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) -#define __HAL_DBGMCU_FREEZE_LPDMA2() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPDMA2() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA2_STOP) -#endif /* DBGMCU_AHB3FZR_DBG_LPDMA2_STOP */ - -#if defined(DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) -#define __HAL_DBGMCU_FREEZE_LPDMA3() SET_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) -#define __HAL_DBGMCU_UNFREEZE_LPDMA3() CLEAR_BIT(DBGMCU->AHB3FZR, DBGMCU_AHB3FZR_DBG_LPDMA3_STOP) -#endif /* DBGMCU_AHB3FZR_DBG_LPDMA3_STOP */ - -/** - * @} - */ - -/** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros - * @{ - */ - -/** @brief Floating Point Unit interrupt enable/disable macros - * @param __INTERRUPT__: This parameter can be a value of @ref SYSCFG_FPU_Interrupts - */ -#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ - SET_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ - }while(0) - -#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ - CLEAR_BIT(SYSCFG->FPUIMR, (__INTERRUPT__));\ - }while(0) - -/** @brief SYSCFG Break ECC lock. - * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) - -/** @brief SYSCFG Break Cortex-M33 Lockup lock. - * Enable and lock the connection of Cortex-M33 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) - -/** @brief SYSCFG Break PVD lock. - * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in - * the PWR_CR2 register. - * @note The selected configuration is locked and can be unlocked only by system reset. - */ -#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) - -/** @brief SYSCFG Break SRAM2 parity lock. - * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. - * @note The selected configuration is locked and can be unlocked by system reset. - */ -#define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) - -/** @brief Check SYSCFG flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag - * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2)\ - & (__FLAG__))!= 0) ? 1 : 0) - -/** @brief Set the SPF bit to clear the SRAM Parity Error Flag. - */ -#define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) - -/** @brief Fast-mode Plus driving capability enable/disable macros - * @param __FASTMODEPLUS__: This parameter can be a value of : - * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 - * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 - * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 - * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 - */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) \ - do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) \ - do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ - CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ - }while(0) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros - * @{ - */ - -#define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ - (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) - -#define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ - ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ - ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ - ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) - -#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ - ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1) || \ - ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE2) || \ - ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE3)) - -#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ - ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) - -#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) - -#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ - (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -#define IS_SYSCFG_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == SYSCFG_SEC) ||\ - ((__ATTRIBUTES__) == SYSCFG_NSEC)) - -#define IS_SYSCFG_ITEMS_ATTRIBUTES(__ITEM__) ((((__ITEM__) & SYSCFG_CLK) == SYSCFG_CLK) || \ - (((__ITEM__) & SYSCFG_CLASSB) == SYSCFG_CLASSB) || \ - (((__ITEM__) & SYSCFG_FPU) == SYSCFG_FPU) || \ - (((__ITEM__) & ~(SYSCFG_ALL)) == 0U)) - -#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ - (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ - (((__ITEM__) & SYSCFG_SAU) == SYSCFG_SAU) || \ - (((__ITEM__) & SYSCFG_MPU_SEC) == SYSCFG_MPU_SEC) || \ - (((__ITEM__) & SYSCFG_VTOR_AIRCR_SEC) == SYSCFG_VTOR_AIRCR_SEC) || \ - (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) - -#else - -#define IS_SYSCFG_LOCK_ITEMS(__ITEM__) ((((__ITEM__) & SYSCFG_MPU_NSEC) == SYSCFG_MPU_NSEC) || \ - (((__ITEM__) & SYSCFG_VTOR_NSEC) == SYSCFG_VTOR_NSEC) || \ - (((__ITEM__) & ~(SYSCFG_LOCK_ALL)) == 0U)) - - -#endif /* __ARM_FEATURE_CMSE */ - -#ifdef SYSCFG_OTGHSPHYCR_EN -#define IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_1) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_2) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_3) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_4) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_5) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_CLK_SELECT_6)) - -#define IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_DOWN) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_POWER_ON)) - -#define IS_SYSCFG_OTGPHY_CONFIG(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_UNDERRESET) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_ENABLE)) - -#define IS_SYSCFG_OTGPHY_DISCONNECT(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_5_9PERCENT) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_DISCONNECT_0PERCENT)) - -#define IS_SYSCFG_OTGPHY_SQUELCH(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_0PERCENT) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_SQUELCH_15PERCENT)) - -#define IS_SYSCFG_OTGPHY_PREEMPHASIS(__VALUE__) (((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_DISABLED) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_1X) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_2X) || \ - ((__VALUE__) == SYSCFG_OTG_HS_PHY_PREEMP_3X)) -#endif /* SYSCFG_OTGHSPHYCR_EN */ - -/** - * @} - */ - -/** @defgroup HAL_Private_Macros HAL Private Macros - * @{ - */ -#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \ - ((FREQ) == HAL_TICK_FREQ_100HZ) || \ - ((FREQ) == HAL_TICK_FREQ_1KHZ)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @addtogroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_Init(void); -HAL_StatusTypeDef HAL_DeInit(void); -void HAL_MspInit(void); -void HAL_MspDeInit(void); -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_IncTick(void); -void HAL_Delay(uint32_t Delay); -uint32_t HAL_GetTick(void); -uint32_t HAL_GetTickPrio(void); -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq); -HAL_TickFreqTypeDef HAL_GetTickFreq(void); -void HAL_SuspendTick(void); -void HAL_ResumeTick(void); -uint32_t HAL_GetHalVersion(void); -uint32_t HAL_GetREVID(void); -uint32_t HAL_GetDEVID(void); -uint32_t HAL_GetUIDw0(void); -uint32_t HAL_GetUIDw1(void); -uint32_t HAL_GetUIDw2(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group3 HAL Debug functions - * @{ - */ - -/* DBGMCU Peripheral Control functions *****************************************/ -void HAL_DBGMCU_EnableDBGStopMode(void); -void HAL_DBGMCU_DisableDBGStopMode(void); -void HAL_DBGMCU_EnableDBGStandbyMode(void); -void HAL_DBGMCU_DisableDBGStandbyMode(void); - -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions - * @{ - */ - -/* SYSCFG Control functions ****************************************************/ -void HAL_SYSCFG_SRAM2Erase(void); - -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); -void HAL_SYSCFG_DisableVREFBUF(void); -#ifdef SYSCFG_OTGHSPHYCR_EN -void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection); -void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig); -void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig); -void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold); -void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold); -void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent); -#endif /* SYSCFG_OTGHSPHYCR_EN */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void); -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void); -void HAL_SYSCFG_EnableSRAMCached(void); -void HAL_SYSCFG_DisableSRAMCached(void); -void HAL_SYSCFG_EnableVddCompensationCell(void); -void HAL_SYSCFG_EnableVddIO2CompensationCell(void); -#if defined(SYSCFG_CCCSR_EN3) -void HAL_SYSCFG_EnableVddHSPICompensationCell(void); -#endif /* SYSCFG_CCCSR_EN3 */ -void HAL_SYSCFG_DisableVddCompensationCell(void); -void HAL_SYSCFG_DisableVddIO2CompensationCell(void); -#if defined(SYSCFG_CCCSR_EN3) -void HAL_SYSCFG_DisableVddHSPICompensationCell(void); -#endif /* SYSCFG_CCCSR_EN3 */ -/** - * @} - */ - -/** @addtogroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions - * @{ - */ - -/* SYSCFG Lock functions ********************************************/ -void HAL_SYSCFG_Lock(uint32_t Item); -HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem); - -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @addtogroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions - * @{ - */ - -/* SYSCFG Attributes functions ********************************************/ -void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes); -HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); - -/** - * @} - */ - -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32U5xx_HAL_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h deleted file mode 100644 index 77b64a5e2..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_cortex.h +++ /dev/null @@ -1,383 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32U5xx_HAL_CORTEX_H -#define __STM32U5xx_HAL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup CORTEX CORTEX - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Types CORTEX Exported Types - * @{ - */ - -/** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition - * @{ - */ -typedef struct -{ - uint8_t Enable; /*!< Specifies the status of the region. - This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ - uint8_t Number; /*!< Specifies the index of the region to protect. - This parameter can be a value of @ref CORTEX_MPU_Region_Number */ - uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ - uint32_t LimitAddress; /*!< Specifies the limit address of the region to protect. */ - uint8_t AttributesIndex; /*!< Specifies the memory attributes index. - This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ - uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter - can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ - uint8_t DisableExec; /*!< Specifies the instruction access status. - This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ - uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. - This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ -} MPU_Region_InitTypeDef; -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Attributes_Initialization_Structure_definition MPU Attributes - * Initialization Structure Definition - * @{ - */ -typedef struct -{ - uint8_t Number; /*!< Specifies the number of the memory attributes to configure. - This parameter can be a value of @ref CORTEX_MPU_Attributes_Number */ - - uint8_t Attributes; /*!< Specifies the memory attributes value. Attributes This parameter - can be a combination of @ref CORTEX_MPU_Attributes */ - -} MPU_Attributes_InitTypeDef; -/** - * @} - */ - - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group - * @{ - */ -#define NVIC_PRIORITYGROUP_0 0x7U /*!< 0 bit for pre-emption priority, - 4 bits for subpriority */ -#define NVIC_PRIORITYGROUP_1 0x6U /*!< 1 bit for pre-emption priority, - 3 bits for subpriority */ -#define NVIC_PRIORITYGROUP_2 0x5U /*!< 2 bits for pre-emption priority, - 2 bits for subpriority */ -#define NVIC_PRIORITYGROUP_3 0x4U /*!< 3 bits for pre-emption priority, - 1 bit for subpriority */ -#define NVIC_PRIORITYGROUP_4 0x3U /*!< 4 bits for pre-emption priority, - 0 bit for subpriority */ -/** - * @} - */ - -/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source - * @{ - */ -#define SYSTICK_CLKSOURCE_HCLK_DIV8 0x0U /*!< AHB clock divided by 8 selected as SysTick clock source */ -#define SYSTICK_CLKSOURCE_LSI 0x1U /*!< LSI clock selected as SysTick clock source */ -#define SYSTICK_CLKSOURCE_LSE 0x2U /*!< LSE clock selected as SysTick clock source */ -#define SYSTICK_CLKSOURCE_HCLK 0x4U /*!< AHB clock selected as SysTick clock source */ -/** - * @} - */ - -/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable - * @{ - */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access - * @{ - */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable - * @{ - */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes - * @{ - */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number - * @{ - */ -#define MPU_REGION_NUMBER0 0U -#define MPU_REGION_NUMBER1 1U -#define MPU_REGION_NUMBER2 2U -#define MPU_REGION_NUMBER3 3U -#define MPU_REGION_NUMBER4 4U -#define MPU_REGION_NUMBER5 5U -#define MPU_REGION_NUMBER6 6U -#define MPU_REGION_NUMBER7 7U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Attributes_Number CORTEX MPU Memory Attributes Number - * @{ - */ -#define MPU_ATTRIBUTES_NUMBER0 0U -#define MPU_ATTRIBUTES_NUMBER1 1U -#define MPU_ATTRIBUTES_NUMBER2 2U -#define MPU_ATTRIBUTES_NUMBER3 3U -#define MPU_ATTRIBUTES_NUMBER4 4U -#define MPU_ATTRIBUTES_NUMBER5 5U -#define MPU_ATTRIBUTES_NUMBER6 6U -#define MPU_ATTRIBUTES_NUMBER7 7U -/** - * @} - */ - -/** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes - * @{ - */ -#define MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros - * @{ - */ -#define OUTER(__ATTR__) ((__ATTR__) << 4U) -#define INNER_OUTER(__ATTR__) ((__ATTR__) | ((__ATTR__) << 4U)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and Configuration functions *****************************/ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); -void HAL_NVIC_SystemReset(void); -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); -/** - * @} - */ - -/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions - * @brief Cortex control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -uint32_t HAL_NVIC_GetPriorityGrouping(void); -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, - uint32_t *const pSubPriority); -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); -uint32_t HAL_SYSTICK_GetCLKSourceConfig(void); -void HAL_SYSTICK_IRQHandler(void); -void HAL_SYSTICK_Callback(void); - -void HAL_MPU_Enable(uint32_t MPU_Control); -void HAL_MPU_Disable(void); -void HAL_MPU_EnableRegion(uint32_t RegionNumber); -void HAL_MPU_DisableRegion(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit); -void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* MPU_NS Control functions ***********************************************/ -void HAL_MPU_Enable_NS(uint32_t MPU_Control); -void HAL_MPU_Disable_NS(void); -void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber); -void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber); -void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit); -void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/** - * @} - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Macros CORTEX Private Macros - * @{ - */ -#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ - ((GROUP) == NVIC_PRIORITYGROUP_1) || \ - ((GROUP) == NVIC_PRIORITYGROUP_2) || \ - ((GROUP) == NVIC_PRIORITYGROUP_3) || \ - ((GROUP) == NVIC_PRIORITYGROUP_4)) - -#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) - -#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < (1UL<<__NVIC_PRIO_BITS)) - -#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) > SysTick_IRQn) - -#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_LSI) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_LSE) || \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK)|| \ - ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_MPU_INSTANCE(INSTANCE) (((INSTANCE) == MPU) || ((INSTANCE) == MPU_NS)) -#endif /* __ARM_FEATURE_CMSE */ - -#define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ - ((STATE) == MPU_REGION_DISABLE)) - -#define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ - ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) - -#define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_OUTER_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_INNER_SHAREABLE) || \ - ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) - -#define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_PRIV_RW) || \ - ((TYPE) == MPU_REGION_ALL_RW) || \ - ((TYPE) == MPU_REGION_PRIV_RO) || \ - ((TYPE) == MPU_REGION_ALL_RO)) - -#define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ - ((NUMBER) == MPU_REGION_NUMBER1) || \ - ((NUMBER) == MPU_REGION_NUMBER2) || \ - ((NUMBER) == MPU_REGION_NUMBER3) || \ - ((NUMBER) == MPU_REGION_NUMBER4) || \ - ((NUMBER) == MPU_REGION_NUMBER5) || \ - ((NUMBER) == MPU_REGION_NUMBER6) || \ - ((NUMBER) == MPU_REGION_NUMBER7)) - -#define IS_MPU_ATTRIBUTES_NUMBER(NUMBER) (((NUMBER) == MPU_ATTRIBUTES_NUMBER0) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER1) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER2) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER3) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER4) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER5) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER6) || \ - ((NUMBER) == MPU_ATTRIBUTES_NUMBER7)) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32U5xx_HAL_CORTEX_H */ - - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h deleted file mode 100644 index 043f0df60..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_def.h +++ /dev/null @@ -1,229 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_def.h - * @author MCD Application Team - * @brief This file contains HAL common defines, enumeration, macros and - * structures definitions. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32U5xx_HAL_DEF -#define __STM32U5xx_HAL_DEF - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#include -#endif /* __ARM_FEATURE_CMSE */ - -#include "stm32u5xx.h" -#include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */ -#include -#include - -/* Exported types ------------------------------------------------------------*/ - -/** - * @brief HAL Status structures definition - */ -typedef enum -{ - HAL_OK = 0x00, - HAL_ERROR = 0x01, - HAL_BUSY = 0x02, - HAL_TIMEOUT = 0x03 -} HAL_StatusTypeDef; - -/** - * @brief HAL Lock structures definition - */ -typedef enum -{ - HAL_UNLOCKED = 0x00, - HAL_LOCKED = 0x01 -} HAL_LockTypeDef; - -/* Exported macros -----------------------------------------------------------*/ - -#define HAL_MAX_DELAY 0xFFFFFFFFU - -#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) == (BIT)) -#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) - -#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) - -#if !defined(UNUSED) -#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ -#endif /* UNUSED */ - -/** @brief Reset the Handle's State field. - * @param __HANDLE__: specifies the Peripheral Handle. - * @note This macro can be used for the following purpose: - * - When the Handle is declared as local variable; before passing it as parameter - * to HAL_PPP_Init() for the first time, it is mandatory to use this macro - * to set to 0 the Handle's "State" field. - * Otherwise, "State" field may have any random value and the first time the function - * HAL_PPP_Init() is called, the low level hardware initialization will be missed - * (i.e. HAL_PPP_MspInit() will not be executed). - * - When there is a need to reconfigure the low level hardware: instead of calling - * HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init(). - * In this later function, when the Handle's "State" field is set to 0, it will execute the function - * HAL_PPP_MspInit() which will reconfigure the low level hardware. - * @retval None - */ -#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) - -#if (USE_RTOS == 1) -/* Reserved for future use */ -#error " USE_RTOS should be 0 in the current HAL release " -#else -#define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - -#define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) -#endif /* USE_RTOS */ - -#if defined ( __GNUC__ ) -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ -#ifndef __packed -#define __packed __attribute__((__packed__)) -#endif /* __packed */ -#endif /* __GNUC__ */ - -#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#ifndef __weak -#define __weak __attribute__((weak)) -#endif /* __weak */ -#ifndef __packed -#define __packed __attribute__((packed)) -#endif /* __packed */ -#endif /* __ARMCC_VERSION */ - -/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used - instead */ -#if defined (__GNUC__) /* GNU Compiler */ -#ifndef __ALIGN_END -#define __ALIGN_END __attribute__ ((aligned (4))) -#endif /* __ALIGN_END */ -#ifndef __ALIGN_BEGIN -#define __ALIGN_BEGIN -#endif /* __ALIGN_BEGIN */ -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#ifndef __ALIGN_END -#define __ALIGN_END __ALIGNED(4) -#endif /* __ALIGN_END */ -#ifndef __ALIGN_BEGIN -#define __ALIGN_BEGIN -#endif /* __ALIGN_BEGIN */ -#else -#ifndef __ALIGN_END -#define __ALIGN_END -#endif /* __ALIGN_END */ -#ifndef __ALIGN_BEGIN -#if defined (__CC_ARM) /* ARM Compiler */ -#define __ALIGN_BEGIN __align(4) -#elif defined (__ICCARM__) /* IAR Compiler */ -#define __ALIGN_BEGIN -#endif /* __CC_ARM */ -#endif /* __ALIGN_BEGIN */ -#endif /* __GNUC__ */ - -/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */ -#if defined (__GNUC__) /* GNU Compiler */ -#define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32))) -#elif defined (__ICCARM__) /* IAR Compiler */ -#define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf -#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) -#define ALIGN_32BYTES(buf) __ALIGNED(32) buf -#elif defined (__CC_ARM) /* ARM Compiler */ -#define ALIGN_32BYTES(buf) __align(32) buf -#endif /* __GNUC__ */ - -/** - * @brief __RAM_FUNC definition - */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - -/* ARM Compiler - ------------ - RAM functions are defined using the toolchain options. - Functions that are executed in RAM should reside in a separate source module. - Using the 'Options for File' dialog you can simply change the 'Code / Const' - area of a module to a memory space in physical RAM. - Available memory areas are declared in the 'Target' tab of the 'Options for Target' - dialog. -*/ -#define __RAM_FUNC HAL_StatusTypeDef - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- - RAM functions are defined using a specific toolchain keyword "__ramfunc". -*/ -#define __RAM_FUNC __ramfunc HAL_StatusTypeDef - -#elif defined ( __GNUC__ ) -/* GNU Compiler - ------------ - RAM functions are defined using a specific toolchain attribute - "__attribute__((section(".RamFunc")))". -*/ -#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc"))) - -#endif /* __RAM_FUNC */ - -/** - * @brief __NOINLINE definition - */ -#if defined ( __CC_ARM ) || ((__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) -/* ARM & GNUCompiler - ---------------- -*/ -#define __NOINLINE __attribute__ ( (noinline) ) - -#elif defined ( __ICCARM__ ) -/* ICCARM Compiler - --------------- -*/ -#define __NOINLINE _Pragma("optimize = no_inline") - -#endif /* __NOINLINE */ - - -#ifdef __cplusplus -} -#endif - -#endif /* ___STM32U5xx_HAL_DEF */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h deleted file mode 100644 index 72153b44e..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma.h +++ /dev/null @@ -1,933 +0,0 @@ -/** - ********************************************************************************************************************** - * @file stm32u5xx_hal_dma.h - * @author MCD Application Team - * @brief Header file of DMA HAL module. - ********************************************************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ********************************************************************************************************************** - */ - -/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ -#ifndef STM32U5xx_HAL_DMA_H -#define STM32U5xx_HAL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ----------------------------------------------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - - -/* Exported types ----------------------------------------------------------------------------------------------------*/ - -/** @defgroup DMA_Exported_Types DMA Exported Types - * @brief DMA Exported Types - * @{ - */ - -/** - * @brief DMA Transfer Configuration Structure definition. - */ -typedef struct -{ - uint32_t Request; /*!< Specifies the DMA channel request. - This parameter can be a value of @ref DMA_Request_Selection */ - - uint32_t BlkHWRequest; /*!< Specifies the Block hardware request mode for DMA channel. - Block Hardware request feature can be used only with dedicated peripherals. - This parameter can be a value of @ref DMA_Block_Request */ - - uint32_t Direction; /*!< Specifies the transfer direction for DMA channel. - This parameter can be a value of @ref DMA_Transfer_Direction */ - - uint32_t SrcInc; /*!< Specifies the source increment mode for the DMA channel. - This parameter can be a value of @ref DMA_Source_Increment_Mode */ - - uint32_t DestInc; /*!< Specifies the destination increment mode for the DMA channel. - This parameter can be a value of @ref DMA_Destination_Increment_Mode */ - - uint32_t SrcDataWidth; /*!< Specifies the source data width for the DMA channel. - This parameter can be a value of @ref DMA_Source_Data_Width */ - - uint32_t DestDataWidth; /*!< Specifies the destination data width for the DMA channel. - This parameter can be a value of @ref DMA_Destination_Data_Width */ - - uint32_t Priority; /*!< Specifies the priority level for the DMA channel. - This parameter can be a value of @ref DMA_Priority_Level */ - - uint32_t SrcBurstLength; /*!< Specifies the source burst length (number of beats within a burst) for the DMA - channel. - This parameter can be a value between 1 and 64 */ - - uint32_t DestBurstLength; /*!< Specifies the destination burst length (number of beats within a burst) for the - DMA channel. - This parameter can be a value between 1 and 64 */ - - uint32_t TransferAllocatedPort; /*!< Specifies the transfer allocated ports. - This parameter can be a combination of @ref DMA_Transfer_Allocated_Port */ - - uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. - This parameter can be a value of @ref DMA_Transfer_Event_Mode */ - - uint32_t Mode; /*!< Specifies the transfer mode for the DMA channel. - This parameter can be a value of @ref DMA_Transfer_Mode */ - -} DMA_InitTypeDef; - -/** - * @brief DMA Linked-List Configuration Structure Definition. - */ -typedef struct -{ - uint32_t Priority; /*!< Specifies the priority level for the DMA channel. - This parameter can be a value of @ref DMA_Priority_Level */ - - uint32_t LinkStepMode; /*!< Specifies the link step mode for the DMA channel. - This parameter can be a value of @ref DMAEx_Link_Step_Mode */ - - uint32_t LinkAllocatedPort; /*!< Specifies the linked-list allocated port for the DMA channel. - This parameter can be a value of @ref DMAEx_Link_Allocated_Port */ - - uint32_t TransferEventMode; /*!< Specifies the transfer event mode for the DMA channel. - This parameter can be a value of @ref DMA_Transfer_Event_Mode */ - - uint32_t LinkedListMode; /*!< Specifies linked-list transfer mode for the DMA channel. - This parameter can be a value of @ref DMAEx_LinkedList_Mode */ - -} DMA_InitLinkedListTypeDef; - -/** - * @brief HAL DMA State Enumeration Definition. - */ -typedef enum -{ - HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ - HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ - HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ - HAL_DMA_STATE_ERROR = 0x03U, /*!< DMA error state */ - HAL_DMA_STATE_ABORT = 0x04U, /*!< DMA Abort state */ - HAL_DMA_STATE_SUSPEND = 0x05U, /*!< DMA Suspend state */ - -} HAL_DMA_StateTypeDef; - -/** - * @brief HAL DMA Level Complete Enumeration Definition. - */ -typedef enum -{ - HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full channel transfer */ - HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half channel transfer */ - -} HAL_DMA_LevelCompleteTypeDef; - -/** - * @brief HAL DMA Callbacks IDs Enumeration Definition. - */ -typedef enum -{ - HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Complete transfer callback ID */ - HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half complete transfer callback ID */ - HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error transfer callback ID */ - HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort transfer callback ID */ - HAL_DMA_XFER_SUSPEND_CB_ID = 0x04U, /*!< Suspend transfer callback ID */ - HAL_DMA_XFER_ALL_CB_ID = 0x05U /*!< All callback ID */ - -} HAL_DMA_CallbackIDTypeDef; - -/** - * @brief DMA handle Structure definition - */ -typedef struct __DMA_HandleTypeDef -{ - DMA_Channel_TypeDef *Instance; /*!< Register the DMA channel base address */ - - DMA_InitTypeDef Init; /*!< DMA channel init parameters */ - - DMA_InitLinkedListTypeDef InitLinkedList; /*!< DMA channel linked-list init parameters */ - - HAL_LockTypeDef Lock; /*!< DMA locking object */ - - uint32_t Mode; /*!< DMA transfer mode */ - - __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ - - __IO uint32_t ErrorCode; /*!< DMA error code */ - - void *Parent; /*!< Parent object state */ - - void (* XferCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer complete callback */ - - void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA half transfer complete callback */ - - void (* XferErrorCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer error callback */ - - void (* XferAbortCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Abort callback */ - - void (* XferSuspendCallback)(struct __DMA_HandleTypeDef *hdma); /*!< DMA transfer Suspend callback */ - - struct __DMA_QListTypeDef *LinkedListQueue; /*!< DMA linked-list queue */ - -} DMA_HandleTypeDef; -/** - * @} - */ - - -/* Exported constants ------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Constants DMA Exported Constants - * @brief DMA Exported constants - * @{ - */ - -/** @defgroup DMA_Error_Codes DMA Error Codes - * @brief DMA Error Codes - * @{ - */ -#define HAL_DMA_ERROR_NONE (0x0000U) /*!< No error */ -#define HAL_DMA_ERROR_DTE (0x0001U) /*!< Data transfer error */ -#define HAL_DMA_ERROR_ULE (0x0002U) /*!< Update linked-list item error */ -#define HAL_DMA_ERROR_USE (0x0004U) /*!< User setting error */ -#define HAL_DMA_ERROR_TO (0x0008U) /*!< Trigger overrun error */ -#define HAL_DMA_ERROR_TIMEOUT (0x0010U) /*!< Timeout error */ -#define HAL_DMA_ERROR_NO_XFER (0x0020U) /*!< No transfer ongoing error */ -#define HAL_DMA_ERROR_BUSY (0x0040U) /*!< Busy error */ -#define HAL_DMA_ERROR_INVALID_CALLBACK (0x0080U) /*!< Invalid callback error */ -#define HAL_DMA_ERROR_NOT_SUPPORTED (0x0100U) /*!< Not supported mode */ -/** - * @} - */ - -/** @defgroup DMA_Interrupt_Enable_Definition DMA Interrupt Enable Definition - * @brief DMA Interrupt Enable Definition - * @{ - */ -#define DMA_IT_TC DMA_CCR_TCIE /*!< Transfer complete interrupt */ -#define DMA_IT_HT DMA_CCR_HTIE /*!< Half transfer complete interrupt */ -#define DMA_IT_DTE DMA_CCR_DTEIE /*!< Data transfer error interrupt */ -#define DMA_IT_ULE DMA_CCR_ULEIE /*!< Update linked-list item error interrupt */ -#define DMA_IT_USE DMA_CCR_USEIE /*!< User eetting error interrupt */ -#define DMA_IT_SUSP DMA_CCR_SUSPIE /*!< Completed suspension interrupt */ -#define DMA_IT_TO DMA_CCR_TOIE /*!< Trigger overrun interrupt */ -/** - * @} - */ - -/** @defgroup DMA_Flag_Definition DMA Flag Definition - * @brief DMA Flag Definition - * @{ - */ -#define DMA_FLAG_IDLE DMA_CSR_IDLEF /*!< Idle flag */ -#define DMA_FLAG_TC DMA_CSR_TCF /*!< Transfer complete flag */ -#define DMA_FLAG_HT DMA_CSR_HTF /*!< Half transfer complete flag */ -#define DMA_FLAG_DTE DMA_CSR_DTEF /*!< Data transfer error flag */ -#define DMA_FLAG_ULE DMA_CSR_ULEF /*!< Update linked-list item error flag */ -#define DMA_FLAG_USE DMA_CSR_USEF /*!< User setting error flag */ -#define DMA_FLAG_SUSP DMA_CSR_SUSPF /*!< Completed suspension flag */ -#define DMA_FLAG_TO DMA_CSR_TOF /*!< Trigger overrun flag */ -/** - * @} - */ - -/** @defgroup DMA_Request_Selection DMA Request Selection - * @brief DMA Request Selection - * @{ - */ -/* GPDMA1 requests */ -#define GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW request is ADC1 */ -#define GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW request is ADC4 */ -#define GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW request is DAC1_CH1 */ -#define GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW request is DAC1_CH2 */ -#define GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW request is TIM6_UP */ -#define GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW request is TIM7_UP */ -#define GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW request is SPI1_RX */ -#define GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW request is SPI1_TX */ -#define GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW request is SPI2_RX */ -#define GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW request is SPI2_TX */ -#define GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW request is SPI3_RX */ -#define GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW request is SPI3_TX */ -#define GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW request is I2C1_RX */ -#define GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW request is I2C1_TX */ -#define GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW request is I2C1_EVC */ -#define GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW request is I2C2_RX */ -#define GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW request is I2C2_TX */ -#define GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW request is I2C2_EVC */ -#define GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW request is I2C3_RX */ -#define GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW request is I2C3_TX */ -#define GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW request is I2C3_EVC */ -#define GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW request is I2C4_RX */ -#define GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW request is I2C4_TX */ -#define GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW request is I2C4_EVC */ -#define GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW request is USART1_RX */ -#define GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW request is USART1_TX */ -#if defined(USART2) -#define GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW request is USART2_RX */ -#define GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW request is USART2_TX */ -#endif /* USART2 */ -#define GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW request is USART3_RX */ -#define GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW request is USART3_TX */ -#define GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW request is UART4_RX */ -#define GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW request is UART4_TX */ -#define GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW request is UART5_RX */ -#define GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW request is UART5_TX */ -#define GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW request is LPUART1_RX */ -#define GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW request is LPUART1_TX */ -#define GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW request is SAI1_A */ -#define GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW request is SAI1_B */ -#if defined(SAI2) -#define GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW request is SAI2_A */ -#define GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW request is SAI2_B */ -#endif /* SAI2 */ -#define GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW request is OCTOSPI1 */ -#if defined(OCTOSPI2) -#define GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW request is OCTOSPI2 */ -#endif /* OCTOSPI2 */ -#define GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW request is TIM1_CH1 */ -#define GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW request is TIM1_CH2 */ -#define GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW request is TIM1_CH3 */ -#define GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW request is TIM1_CH4 */ -#define GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW request is TIM1_UP */ -#define GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW request is TIM1_TRIG */ -#define GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW request is TIM1_COM */ -#define GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW request is TIM8_CH1 */ -#define GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW request is TIM8_CH2 */ -#define GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW request is TIM8_CH3 */ -#define GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW request is TIM8_CH4 */ -#define GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW request is TIM8_UP */ -#define GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW request is TIM8_TRIG */ -#define GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW request is TIM8_COM */ -#define GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW request is TIM2_CH1 */ -#define GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW request is TIM2_CH2 */ -#define GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW request is TIM2_CH3 */ -#define GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW request is TIM2_CH4 */ -#define GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW request is TIM2_UP */ -#define GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW request is TIM3_CH1 */ -#define GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW request is TIM3_CH2 */ -#define GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW request is TIM3_CH3 */ -#define GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW request is TIM3_CH4 */ -#define GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW request is TIM3_UP */ -#define GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW request is TIM3_TRIG */ -#define GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW request is TIM4_CH1 */ -#define GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW request is TIM4_CH2 */ -#define GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW request is TIM4_CH3 */ -#define GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW request is TIM4_CH4 */ -#define GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW request is TIM4_UP */ -#define GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW request is TIM5_CH1 */ -#define GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW request is TIM5_CH2 */ -#define GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW request is TIM5_CH3 */ -#define GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW request is TIM5_CH4 */ -#define GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW request is TIM5_UP */ -#define GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW request is TIM5_TRIG */ -#define GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW request is TIM15_CH1 */ -#define GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW request is TIM15_UP */ -#define GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW request is TIM15_TRIG */ -#define GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW request is TIM15_COM */ -#define GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW request is TIM16_CH1 */ -#define GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW request is TIM16_UP */ -#define GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW request is TIM17_CH1 */ -#define GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW request is TIM17_UP */ -#define GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW request is DCMI_PSSI */ -#define GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW request is AES_IN */ -#define GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW request is AES_OUT */ -#define GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW request is HASH_IN */ -#if defined(UCPD1) -#define GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW request is UCPD1_TX */ -#define GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW request is UCPD1_RX */ -#endif /* UCPD1 */ -#define GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW request is MDF1_FLT0 */ -#define GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW request is MDF1_FLT1 */ -#define GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW request is MDF1_FLT2 */ -#define GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW request is MDF1_FLT3 */ -#define GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW request is MDF1_FLT4 */ -#define GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW request is MDF1_FLT5 */ -#define GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW request is ADF1_FLT0 */ -#define GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW request is FMAC_READ */ -#define GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW request is FMAC_WRITE */ -#define GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW request is CORDIC_READ */ -#define GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW request is CORDIC_WRITE */ -#define GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW request is SAES_IN */ -#define GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW request is SAES_OUT */ -#define GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW request is LPTIM1_IC1 */ -#define GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW request is LPTIM1_IC2 */ -#define GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW request is LPTIM1_UE */ -#define GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW request is LPTIM2_IC1 */ -#define GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW request is LPTIM2_IC2 */ -#define GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW request is LPTIM2_UE */ -#define GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW request is LPTIM3_IC1 */ -#define GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW request is LPTIM3_IC2 */ -#define GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW request is LPTIM3_UE */ -#if defined (HSPI1_BASE) -#define GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ -#endif /* HSPI1_BASE */ -#if defined (I2C5) -#define GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ -#define GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ -#define GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ -#endif /* I2C5 */ -#if defined (I2C6) -#define GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ -#define GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ -#define GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ -#endif /* I2C6 */ -#if defined (USART6) -#define GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ -#define GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ -#endif /* USART6 */ -#if defined (ADC2) -#define GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ -#endif /* ADC2 */ -#if defined (JPEG) -#define GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ -#define GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ -#endif /* JPEG */ - -/* LPDMA1 requests */ -#define LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW request is LPUART1_RX */ -#define LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW request is LPUART1_TX */ -#define LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW request is SPI3_RX */ -#define LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW request is SPI3_TX */ -#define LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW request is I2C3_RX */ -#define LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW request is I2C3_TX */ -#define LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW request is I2C3_EVC */ -#define LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW request is ADC4 */ -#define LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW request is DAC1_CH1 */ -#define LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW request is DAC1_CH2 */ -#define LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW request is ADF1_FLT0 */ -#define LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW request is LPTIM1_IC1 */ -#define LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW request is LPTIM1_IC2 */ -#define LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW request is LPTIM1_UE */ -#define LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW request is LPTIM3_IC1 */ -#define LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW request is LPTIM3_IC2 */ -#define LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW request is LPTIM3_UE */ - -/* Software request */ -#define DMA_REQUEST_SW DMA_CTR2_SWREQ /*!< DMA SW request */ -/** - * @} - */ - -/** @defgroup DMA_Block_Request DMA Block Request - * @brief DMA Block Request - * @{ - */ -#define DMA_BREQ_SINGLE_BURST 0x00000000U /*!< Hardware request protocol at a single / burst level */ -#define DMA_BREQ_BLOCK DMA_CTR2_BREQ /*!< Hardware request protocol at a block level */ -/** - * @} - */ - -/** @defgroup DMA_Transfer_Direction DMA Transfer Direction - * @brief DMA transfer direction - * @{ - */ -#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define DMA_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ -#define DMA_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_Source_Increment_Mode DMA Source Increment Mode - * @brief DMA Source Increment Mode - * @{ - */ -#define DMA_SINC_FIXED 0x00000000U /*!< Source fixed single / burst */ -#define DMA_SINC_INCREMENTED DMA_CTR1_SINC /*!< Source incremented single / burst */ -/** - * @} - */ - -/** @defgroup DMA_Destination_Increment_Mode DMA Destination Increment Mode - * @brief DMA Destination Increment Mode - * @{ - */ -#define DMA_DINC_FIXED 0x00000000U /*!< Destination fixed single / burst */ -#define DMA_DINC_INCREMENTED DMA_CTR1_DINC /*!< Destination incremented single / burst */ -/** - * @} - */ - -/** @defgroup DMA_Source_Data_Width DMA Source Data Width - * @brief DMA Source Data Width - * @{ - */ -#define DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source data width : Byte */ -#define DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source data width : HalfWord */ -#define DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source data width : Word */ -/** - * @} - */ - -/** @defgroup DMA_Destination_Data_Width DMA destination Data Width - * @brief DMA destination Data Width - * @{ - */ -#define DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination data width : Byte */ -#define DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination data width : HalfWord */ -#define DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination data width : Word */ - -/** - * @} - */ - -/** @defgroup DMA_Priority_Level DMA Priority Level - * @brief DMA Priority Level - * @{ - */ -#define DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low weight */ -#define DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid weight */ -#define DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High weight */ -#define DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : HIGH Priority */ -/** - * @} - */ - -/** @defgroup DMA_Transfer_Allocated_Port DMA Transfer Allocated Port - * @brief DMA Transfer Allocated Port - * @{ - */ -#define DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source allocated Port 0 */ -#define DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source allocated Port 1 */ -#define DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination allocated Port 0 */ -#define DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination allocated Port 1 */ -/** - * @} - */ - -/** @defgroup DMA_Transfer_Event_Mode DMA Transfer Event Mode - * @brief DMA Transfer Event Mode - * @{ - */ -#define DMA_TCEM_BLOCK_TRANSFER 0x00000000U /*!< The TC event is generated at the end of each block and the - HT event is generated at the half of each block */ -#define DMA_TCEM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC event is generated at the end of the repeated block - and the HT event is generated at the half of the repeated - block */ -#define DMA_TCEM_EACH_LL_ITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC event is generated at the end of each linked-list - item and the HT event is generated at the half of each - linked-list item */ -#define DMA_TCEM_LAST_LL_ITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC event is generated at the end of the last - linked-list item and the HT event is generated at the half - of the last linked-list item */ -/** - * @} - */ - -/** @defgroup DMA_Transfer_Mode DMA Transfer Mode - * @brief DMA Transfer Mode - * @{ - */ -#define DMA_NORMAL (0x00U) /*!< Normal DMA transfer */ -/** - * @} - */ - -/** @defgroup DMA_Channel_Attributes DMA Channel Attributes - * @brief DMA Channel Security and Privilege Attributes - * @note Secure and non-secure attributes are only available from the secure world when TZEN = 1 - * @{ - */ -#define DMA_CHANNEL_PRIV (DMA_CHANNEL_ATTR_PRIV_MASK | 0x01U) /*!< Channel is privileged */ -#define DMA_CHANNEL_NPRIV (DMA_CHANNEL_ATTR_PRIV_MASK) /*!< Channel is unprivileged */ - -#define DMA_CHANNEL_SEC (DMA_CHANNEL_ATTR_SEC_MASK | 0x02U) /*!< Channel is secure */ -#define DMA_CHANNEL_NSEC (DMA_CHANNEL_ATTR_SEC_MASK) /*!< Channel is non-secure */ -#define DMA_CHANNEL_SRC_SEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK | 0x04U) /*!< Channel source is secure */ -#define DMA_CHANNEL_SRC_NSEC (DMA_CHANNEL_ATTR_SEC_SRC_MASK) /*!< Channel source is non-secure */ -#define DMA_CHANNEL_DEST_SEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK | 0x08U) /*!< Channel destination is secure */ -#define DMA_CHANNEL_DEST_NSEC (DMA_CHANNEL_ATTR_SEC_DEST_MASK) /*!< Channel destination is non-secure */ - -#define DMA_CHANNEL_ATTRIBUTE_UNLOCKED (0x00U) /*!< Channel attribute is unlocked */ -#define DMA_CHANNEL_ATTRIBUTE_LOCKED (0x01U) /*!< Channel attribute is locked */ -/** - * @} - */ - - - -/** - * @} - */ - - -/* Exported macro ----------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Macros DMA Exported Macros - * @brief DMA Exported Macros - * @{ - */ - -/** @brief Reset DMA handle state. - * @param __HANDLE__ : DMA handle. - * @retval None. - */ -#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) \ - ((__HANDLE__)->State = HAL_DMA_STATE_RESET) - -/** - * @brief Enable the specified DMA Channel. - * @param __HANDLE__ : DMA handle. - * @retval None - */ -#define __HAL_DMA_ENABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) - -/** - * @brief Disable the specified DMA Channel. - * @param __HANDLE__ : DMA handle. - * @retval None - */ -#define __HAL_DMA_DISABLE(__HANDLE__) \ - ((__HANDLE__)->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_RESET)) - -/** - * @brief Get the DMA channel pending flags. - * @param __HANDLE__ : DMA handle. - * @param __FLAG__ : Get the specified flag. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TC : Transfer Complete flag. - * @arg DMA_FLAG_HT : Half Transfer Complete flag. - * @arg DMA_FLAG_DTE : Data Transfer Error flag. - * @arg DMA_FLAG_ULE : Update linked-list Error flag. - * @arg DMA_FLAG_USE : User Setting Error flag. - * @arg DMA_FLAG_TO : Trigger Overrun flag. - * @arg DMA_FLAG_SUSP : Completed Suspension flag. - * @arg DMA_FLAG_IDLEF : Idle flag. - * @retval The state of FLAG (SET or RESET). - */ -#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) \ - ((__HANDLE__)->Instance->CSR & (__FLAG__)) - -/** - * @brief Clear the DMA Channel pending flags. - * @param __HANDLE__ : DMA handle. - * @param __FLAG__ : Specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg DMA_FLAG_TC : Transfer Complete flag. - * @arg DMA_FLAG_HT : Half Transfer Complete flag. - * @arg DMA_FLAG_DTE : Data Transfer Error flag. - * @arg DMA_FLAG_ULE : Update Linked-List Error flag. - * @arg DMA_FLAG_USE : User Setting Error flag. - * @arg DMA_FLAG_TO : Trigger Overrun flag. - * @arg DMA_FLAG_SUSP : Completed Suspension flag. - * @retval None - */ -#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - ((__HANDLE__)->Instance->CFCR = (__FLAG__)) - -/** - * @brief Enable the specified DMA Channel interrupts. - * @param __HANDLE__ : DMA handle. - * @param __INTERRUPT__ : Specifies the DMA interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC : Transfer Complete interrupt. - * @arg DMA_IT_HT : Half Transfer Complete interrupt. - * @arg DMA_IT_DTE : Data Transfer Error interrupt. - * @arg DMA_IT_ULE : Update Linked-List Error interrupt. - * @arg DMA_IT_USE : User Setting Error interrupt. - * @arg DMA_IT_TO : Trigger Overrun interrupt. - * @arg DMA_IT_SUSP : Completed Suspension interrupt. - * @retval None - */ -#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) - -/** - * @brief Disable the specified DMA Channel interrupts. - * @param __HANDLE__ : DMA handle. - * @param __INTERRUPT__ : specifies the DMA interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg DMA_IT_TC : Transfer Complete interrupt. - * @arg DMA_IT_HT : Half Transfer Complete interrupt. - * @arg DMA_IT_DTE : Data Transfer Error interrupt. - * @arg DMA_IT_ULE : Update Linked-List Error interrupt. - * @arg DMA_IT_USE : User Setting Error interrupt. - * @arg DMA_IT_TO : Trigger Overrun interrupt. - * @arg DMA_IT_SUSP : Completed Suspension interrupt. - * @retval None - */ -#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) - -/** - * @brief Checks whether the specified DMA Channel interrupt is enabled or not. - * @param __HANDLE__ : DMA handle. - * @param __INTERRUPT__ : specifies the DMA interrupt source to check. - * @arg DMA_IT_TC : Transfer Complete interrupt. - * @arg DMA_IT_HT : Half Transfer Complete interrupt. - * @arg DMA_IT_DTE : Data Transfer Error interrupt. - * @arg DMA_IT_ULE : Update Linked-List Error interrupt. - * @arg DMA_IT_USE : User Setting Error interrupt. - * @arg DMA_IT_TO : Trigger Overrun interrupt. - * @arg DMA_IT_SUSP : Completed Suspension interrupt. - * @retval The state of DMA_IT (SET or RESET). - */ -#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) - -/** - * @brief Writes the block number of bytes to be transferred from the source on the DMA Channel. - * @param __HANDLE__ : DMA handle. - * @param __COUNTER__ : Number of data bytes to be transferred from the source (from 0 to 65535). - */ -#define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) \ - MODIFY_REG((__HANDLE__)->Instance->CBR1, DMA_CBR1_BNDT, (__COUNTER__)) - -/** - * @brief Returns the number of remaining data bytes in the current DMA Channel transfer. - * @param __HANDLE__ : DMA handle. - * @retval The number of remaining data units in the current DMA Stream transfer. - */ -#define __HAL_DMA_GET_COUNTER(__HANDLE__) \ - (((__HANDLE__)->Instance->CBR1) & DMA_CBR1_BNDT) -/** - * @} - */ - - -/* Include DMA HAL Extension module */ -#include "stm32u5xx_hal_dma_ex.h" - - -/* Exported functions ------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Exported_Functions DMA Exported Functions - * @brief DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_Exported_Functions_Group1 Initialization and De-Initialization Functions - * @brief Initialization and De-Initialization Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma); -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group2 I/O Operation Functions - * @brief I/O Operation Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, - uint32_t SrcAddress, - uint32_t DstAddress, - uint32_t SrcDataSize); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, - uint32_t SrcAddress, - uint32_t DstAddress, - uint32_t SrcDataSize); -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, - HAL_DMA_LevelCompleteTypeDef CompleteLevel, - uint32_t Timeout); -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, - HAL_DMA_CallbackIDTypeDef CallbackID, - void (*const pCallback)(DMA_HandleTypeDef *const _hdma)); -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, - HAL_DMA_CallbackIDTypeDef CallbackID); -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group3 State and Error Functions - * @brief State and Error Functions - * @{ - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma); -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma); -/** - * @} - */ - -/** @defgroup DMA_Exported_Functions_Group4 DMA Attributes Functions - * @brief DMA Attributes Functions - * @{ - */ - -HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, - uint32_t ChannelAttributes); -HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, - uint32_t *const pChannelAttributes); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, - uint32_t *const pLockState); - - -/** - * @} - */ - -/** - * @} - */ - - -/* Private constants -------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Private_Constants DMA Private Constants - * @brief DMA Private Constants - * @{ - */ -#define HAL_TIMEOUT_DMA_ABORT (0x00000005U) /* DMA channel abort timeout 5 milli-second */ -#define HAL_DMA_CHANNEL_START (0x00000050U) /* DMA channel offset */ -#define HAL_DMA_CHANNEL_SIZE (0x00000080U) /* DMA channel size */ -#define HAL_DMA_OFFSET_MASK (0x00000FFFU) /* DMA channel offset mask */ -#define DMA_CHANNEL_ATTR_PRIV_MASK (0x00000010U) /* DMA channel privilege mask */ -#define DMA_CHANNEL_ATTR_SEC_MASK (0x00000020U) /* DMA channel secure mask */ -#define DMA_CHANNEL_ATTR_SEC_SRC_MASK (0x00000040U) /* DMA channel source secure mask */ -#define DMA_CHANNEL_ATTR_SEC_DEST_MASK (0x00000080U) /* DMA channel destination secure mask */ -#define DMA_CHANNEL_ATTR_VALUE_MASK (0x0000000FU) /* DMA channel attributes value mask */ -#define DMA_CHANNEL_ATTR_ITEM_MASK (0x000000F0U) /* DMA channel attributes item mask */ -#define DMA_CHANNEL_BURST_MIN (0x00000001U) /* DMA channel minimum burst size */ -#define DMA_CHANNEL_BURST_MAX (0x00000040U) /* DMA channel maximum burst size */ -/** - * @} - */ - - -/* Private macros ----------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Private_Macros DMA Private Macros - * @brief DMA Private Macros - * @{ - */ -#define GET_DMA_INSTANCE(__HANDLE__) \ - ((DMA_TypeDef *)((uint32_t)((__HANDLE__)->Instance) & (~HAL_DMA_OFFSET_MASK))) - -#define GET_DMA_CHANNEL(__HANDLE__) \ - ((((uint32_t)((__HANDLE__)->Instance) & HAL_DMA_OFFSET_MASK) - HAL_DMA_CHANNEL_START) / HAL_DMA_CHANNEL_SIZE) - -#define IS_DMA_MODE(MODE) \ - ((MODE) == DMA_NORMAL) - -#define IS_DMA_DIRECTION(DIRECTION) \ - (((DIRECTION) == DMA_PERIPH_TO_MEMORY) || \ - ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ - ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) - -#define IS_DMA_LEVEL_COMPLETE(LEVEL) \ - (((LEVEL) == HAL_DMA_FULL_TRANSFER) || \ - ((LEVEL) == HAL_DMA_HALF_TRANSFER)) - -#define IS_DMA_SOURCE_INC(INC) \ - (((INC) == DMA_SINC_FIXED) || \ - ((INC) == DMA_SINC_INCREMENTED)) - -#define IS_DMA_DESTINATION_INC(INC) \ - (((INC) == DMA_DINC_FIXED) || \ - ((INC) == DMA_DINC_INCREMENTED)) - -#define IS_DMA_SOURCE_DATA_WIDTH(WIDTH) \ - (((WIDTH) == DMA_SRC_DATAWIDTH_BYTE) || \ - ((WIDTH) == DMA_SRC_DATAWIDTH_HALFWORD) || \ - ((WIDTH) == DMA_SRC_DATAWIDTH_WORD)) - -#define IS_DMA_DESTINATION_DATA_WIDTH(WIDTH) \ - (((WIDTH) == DMA_DEST_DATAWIDTH_BYTE) || \ - ((WIDTH) == DMA_DEST_DATAWIDTH_HALFWORD) || \ - ((WIDTH) == DMA_DEST_DATAWIDTH_WORD)) - -#define IS_DMA_BURST_LENGTH(LENGTH) \ - (((LENGTH) >= DMA_CHANNEL_BURST_MIN) && \ - ((LENGTH) <= DMA_CHANNEL_BURST_MAX)) - -#define IS_DMA_PRIORITY(PRIORITY) \ - (((PRIORITY) == DMA_LOW_PRIORITY_LOW_WEIGHT) || \ - ((PRIORITY) == DMA_LOW_PRIORITY_MID_WEIGHT) || \ - ((PRIORITY) == DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ - ((PRIORITY) == DMA_HIGH_PRIORITY)) - -#define IS_DMA_TRANSFER_ALLOCATED_PORT(ALLOCATED_PORT) \ - (((ALLOCATED_PORT) & (~(DMA_CTR1_SAP | DMA_CTR1_DAP))) == 0U) - -#if defined (GPDMA1_REQUEST_JPEG_TX) -#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_JPEG_TX)) -#elif defined (GPDMA1_REQUEST_ADC2) -#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_ADC2)) -#else -#define IS_DMA_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_SW) || ((REQUEST) <= GPDMA1_REQUEST_LPTIM3_UE)) -#endif /* GPDMA1_REQUEST_JPEG_TX */ - -#define IS_DMA_BLOCK_HW_REQUEST(MODE) \ - (((MODE) == DMA_BREQ_SINGLE_BURST) || \ - ((MODE) == DMA_BREQ_BLOCK)) - -#define IS_DMA_TCEM_EVENT_MODE(MODE) \ - (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ - ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ - ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ - ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) - -#define IS_DMA_BLOCK_SIZE(SIZE) \ - (((SIZE) > 0U) && ((SIZE) <= DMA_CBR1_BNDT)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ - (((ATTRIBUTE) != 0U) && (((ATTRIBUTE) & (~(DMA_CHANNEL_ATTR_VALUE_MASK | DMA_CHANNEL_ATTR_ITEM_MASK))) == 0U) && \ - (((((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U) | ((ATTRIBUTE) & DMA_CHANNEL_ATTR_VALUE_MASK)) == \ - (((ATTRIBUTE) & DMA_CHANNEL_ATTR_ITEM_MASK) >> 4U))) -#else -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) \ - (((ATTRIBUTE) == DMA_CHANNEL_PRIV) || \ - ((ATTRIBUTE) == DMA_CHANNEL_NPRIV)) -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_DMA_GLOBAL_ACTIVE_FLAG_S(INSTANCE, GLOBAL_FLAG) \ - (((INSTANCE)->SMISR & (GLOBAL_FLAG))) -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -#define IS_DMA_GLOBAL_ACTIVE_FLAG_NS(INSTANCE, GLOBAL_FLAG) \ - (((INSTANCE)->MISR & (GLOBAL_FLAG))) - -/** - * @} - */ - - -/* Private functions -------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_DMA_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h deleted file mode 100644 index af230a52b..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_dma_ex.h +++ /dev/null @@ -1,735 +0,0 @@ -/** - ********************************************************************************************************************** - * @file stm32u5xx_hal_dma_ex.h - * @author MCD Application Team - * @brief Header file of DMA HAL extension module. - ********************************************************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ********************************************************************************************************************** - */ - -/* Define to prevent recursive inclusion -----------------------------------------------------------------------------*/ -#ifndef STM32U5xx_HAL_DMA_EX_H -#define STM32U5xx_HAL_DMA_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ----------------------------------------------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup DMAEx - * @{ - */ - -/* Exported types ----------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Types DMAEx Exported Types - * @brief DMAEx Exported types - * @{ - */ - -/** - * @brief DMAEx Data Handling Configuration Structure Definition. - */ -typedef struct -{ - uint32_t DataExchange; /*!< Specifies the DMA channel data exchange mode. - This parameter can be a value of @ref DMAEx_Data_Exchange */ - - uint32_t DataAlignment; /*!< Specifies the DMA channel data padding and alignment mode - This parameter can be a value of @ref DMAEx_Data_Alignment */ - -} DMA_DataHandlingConfTypeDef; - -/** - * @brief DMAEx Trigger Configuration Structure Definition. - */ -typedef struct -{ - uint32_t TriggerMode; /*!< Specifies the DMA channel trigger mode. - This parameter can be a value of @ref DMAEx_Trigger_Mode */ - - uint32_t TriggerPolarity; /*!< Specifies the DMA channel trigger event polarity. - This parameter can be a value of @ref DMAEx_Trigger_Polarity */ - - uint32_t TriggerSelection; /*!< Specifies the DMA channel trigger event selection. - This parameter can be a value of @ref DMAEx_Trigger_Selection */ - -} DMA_TriggerConfTypeDef; - -/** - * @brief DMAEx Repeated Block Configuration Structure Definition. - */ -typedef struct -{ - uint32_t RepeatCount; /*!< Specifies the DMA channel repeat count (the number of repetitions of block). - This parameter can be a value between 1 and 2048 */ - - int32_t SrcAddrOffset; /*!< Specifies the DMA channel single/burst source address offset : - This parameter can be a value between -8191 and 8191. - * If source address offset > 0 => Increment the source address by offset from where - the last single/burst transfer ends. - * If source address offset < 0 => Decrement the source address by offset from where - the last single/burst transfer ends. - * If source address offset == 0 => The next single/burst source address starts from - where the last transfer ends */ - - int32_t DestAddrOffset; /*!< Specifies the DMA channel single/burst destination address offset signed value : - This parameter can be a value between -8191 and 8191. - * If destination address offset > 0 => Increment the destination address by offset - from where the last single/burst transfer ends. - * If destination address offset < 0 => Decrement the destination address by offset - from where the last single/burst transfer ends. - * If destination address offset == 0 => The next single/burst destination address - starts from where the last transfer ends. */ - - int32_t BlkSrcAddrOffset; /*!< Specifies the DMA channel block source address offset signed value : - This parameter can be a value between -65535 and 65535. - * If block source address offset > 0 => Increment the block source address by offset - from where the last block ends. - * If block source address offset < 0 => Decrement the next block source address by - offset from where the last block ends. - * If block source address offset == 0 => the next block source address starts from - where the last block ends */ - - int32_t BlkDestAddrOffset; /*!< Specifies the DMA channel block destination address offset signed value : - This parameter can be a value between -65535 and 65535. - * If block destination address offset > 0 => Increment the block destination address - by offset from where the last block ends. - * If block destination address offset < 0 => Decrement the next block destination - address by offset from where the last block ends. - * If block destination address offset == 0 => the next block destination address - starts from where the last block ends */ - -} DMA_RepeatBlockConfTypeDef; - -/** - * @brief DMAEx Queue State Enumeration Definition. - */ -typedef enum -{ - HAL_DMA_QUEUE_STATE_RESET = 0x00U, /*!< DMA queue empty */ - HAL_DMA_QUEUE_STATE_READY = 0x01U, /*!< DMA queue ready for use */ - HAL_DMA_QUEUE_STATE_BUSY = 0x02U /*!< DMA queue execution on going */ - -} HAL_DMA_QStateTypeDef; - -/** - * @brief DMAEx Linked-List Node Configuration Structure Definition. - */ -typedef struct -{ - uint32_t NodeType; /*!< Specifies the DMA channel node type. - This parameter can be a value of @ref DMAEx_Node_Type */ - - DMA_InitTypeDef Init; /*!< Specifies the DMA channel basic configuration */ - - DMA_DataHandlingConfTypeDef DataHandlingConfig; /*!< Specifies the DMA channel data handling channel configuration */ - - DMA_TriggerConfTypeDef TriggerConfig; /*!< Specifies the DMA channel trigger configuration */ - - DMA_RepeatBlockConfTypeDef RepeatBlockConfig; /*!< Specifies the DMA channel repeated block configuration */ - - uint32_t SrcAddress; /*!< Specifies the source memory address */ - uint32_t DstAddress; /*!< Specifies the destination memory address */ - uint32_t DataSize; /*!< Specifies the source data size in bytes */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t SrcSecure; /*!< Specifies the source security attribute */ - uint32_t DestSecure; /*!< Specifies the destination security attribute */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -} DMA_NodeConfTypeDef; - -/** - * @brief DMAEx Linked-List Node Structure Definition. - */ -typedef struct -{ - uint32_t LinkRegisters[8U]; /*!< Physical Node register description */ - uint32_t NodeInfo; /*!< Node information */ - -} DMA_NodeTypeDef; - -/** - * @brief DMAEx Linked-List Queue Structure Definition. - */ -typedef struct __DMA_QListTypeDef -{ - DMA_NodeTypeDef *Head; /*!< Specifies the queue head node */ - - DMA_NodeTypeDef *FirstCircularNode; /*!< Specifies the queue first circular node */ - - uint32_t NodeNumber; /*!< Specifies the queue node number */ - - __IO HAL_DMA_QStateTypeDef State; /*!< Specifies the queue state */ - - __IO uint32_t ErrorCode; /*!< Specifies the queue error code */ - - __IO uint32_t Type; /*!< Specifies whether the queue is static or dynamic */ - -} DMA_QListTypeDef; -/** - * @} - */ - -/* Exported constants ------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Constants DMAEx Exported Constants - * @brief DMAEx Exported Constants - * @{ - */ - -/** @defgroup Queue_Error_Codes Queue Error Codes - * @brief Queue Error Codes - * @{ - */ -#define HAL_DMA_QUEUE_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_DMA_QUEUE_ERROR_BUSY (0x01U) /*!< Error busy */ -#define HAL_DMA_QUEUE_ERROR_EMPTY (0x02U) /*!< Error unallowed operation for empty queue */ -#define HAL_DMA_QUEUE_ERROR_UNSUPPORTED (0x03U) /*!< Error unsupported feature */ -#define HAL_DMA_QUEUE_ERROR_INVALIDTYPE (0x04U) /*!< Error incompatible node type or circular initialization - and queue circular types are incompatible */ -#define HAL_DMA_QUEUE_ERROR_OUTOFRANGE (0x05U) /*!< Error out of range node memory */ -#define HAL_DMA_QUEUE_ERROR_NOTFOUND (0x06U) /*!< Error node not found in queue */ -/** - * @} - */ - -/** @defgroup DMAEx_LinkedList_Mode DMAEx LinkedList Mode - * @brief DMAEx LinkedList Mode - * @{ - */ -#define DMA_LINKEDLIST_NORMAL DMA_LINKEDLIST /*!< Linear linked-list DMA channel transfer */ -#define DMA_LINKEDLIST_CIRCULAR (DMA_LINKEDLIST | (0x01U)) /*!< Circular linked-list DMA channel transfer */ -/** - * @} - */ - -/** @defgroup DMAEx_Data_Alignment DMAEx Data Alignment - * @brief DMAEx Data Alignment - * @{ - */ -#define DMA_DATA_RIGHTALIGN_ZEROPADDED 0x00000000U /*!< If source data width < destination data width - => Right aligned padded with 0 up to destination data - width */ -#define DMA_DATA_RIGHTALIGN_LEFTTRUNC 0x00000000U /*!< If source data width > destination data width - => Right aligned left Truncated down to destination - data width */ -#define DMA_DATA_RIGHTALIGN_SIGNEXT DMA_CTR1_PAM_0 /*!< If source data width < destination data width - => Right Aligned padded with sign extended up to - destination data width */ -#define DMA_DATA_LEFTALIGN_RIGHTTRUNC DMA_CTR1_PAM_0 /*!< If source data width > destination data width - => Left Aligned Right Truncated down to the - destination data width */ -#define DMA_DATA_PACK DMA_CTR1_PAM_1 /*!< If source data width < destination data width - => Packed at the destination data width - (Not available on LPDMA) */ -#define DMA_DATA_UNPACK DMA_CTR1_PAM_1 /*!< If source data width > destination data width - => Unpacked at the destination data width - (Not available on LPDMA) */ -/** - * @} - */ - -/** @defgroup DMAEx_Data_Exchange DMAEx Data Exchange - * @brief DMAEx Data Exchange - * @{ - */ -#define DMA_EXCHANGE_NONE 0x00000000U /*!< No data exchange */ -#define DMA_EXCHANGE_DEST_BYTE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width is > Byte */ -#define DMA_EXCHANGE_DEST_HALFWORD DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width is > Half-Word */ -#define DMA_EXCHANGE_SRC_BYTE DMA_CTR1_SBX /*!< Source Byte endianness exchange when source data width is word */ -/** - * @} - */ - -/** @defgroup DMAEx_Trigger_Polarity DMAEx Trigger Polarity - * @brief DMAEx Trigger Polarity - * @{ - */ -#define DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. Masked trigger event */ -#define DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising edge of the selected trigger event input */ -#define DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling edge of the selected trigger event input */ -/** - * @} - */ - -/** @defgroup DMAEx_Trigger_Mode DMAEx Trigger Mode - * @brief DMAEx Trigger Mode - * @{ - */ -#define DMA_TRIGM_BLOCK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) one hit trigger */ -#define DMA_TRIGM_REPEATED_BLOCK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) one hit trigger */ -#define DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) one hit trigger */ -#define DMA_TRIGM_SINGLE_BURST_TRANSFER DMA_CTR2_TRIGM /*!< A single/burst transfer is conditioned by (at least) one hit trigger */ -/** - * @} - */ - -/** @defgroup DMAEx_Trigger_Selection DMAEx Trigger Selection - * @brief DMAEx Trigger Selection - * @{ - */ -/* GPDMA1 triggers */ -#define GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger signal is EXTI_LINE0 */ -#define GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger signal is EXTI_LINE1 */ -#define GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger signal is EXTI_LINE2 */ -#define GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger signal is EXTI_LINE3 */ -#define GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger signal is EXTI_LINE4 */ -#define GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger signal is EXTI_LINE5 */ -#define GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger signal is EXTI_LINE6 */ -#define GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger signal is EXTI_LINE7 */ -#define GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger signal is TAMP_TRG1 */ -#define GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger signal is TAMP_TRG2 */ -#define GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger signal is TAMP_TRG3 */ -#define GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH1 */ -#define GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger signal is LPTIM1_CH2 */ -#define GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH1 */ -#define GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger signal is LPTIM2_CH2 */ -#define GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger signal is LPTIM4_OUT */ -#define GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger signal is COMP1_OUT */ -#if defined(COMP2) -#define GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger signal is COMP2_OUT */ -#endif /* COMP2 */ -#define GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger signal is RTC_ALRA_TRG */ -#define GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger signal is RTC_ALRB_TRG */ -#define GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger signal is RTC_WUT_TRG */ -#define GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH2_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH3_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH8_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH9_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH10_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH11_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH14_TCF */ -#define GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger signal is GPDMA1_CH15_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ -#define GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ -#define GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger signal is TIM2_TRGO */ -#define GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger signal is TIM15_TRGO */ -#if defined (TIM3_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ -#if defined (TIM4_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ -#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ -#if defined (TIM5_TRGO_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ -#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ -#if defined (LTDC) -#define GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ -#endif /* LTDC */ -#if defined (DSI) -#define GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ -#define GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ -#endif /* DSI */ -#if defined (DMA2D_TRIGGER_SUPPORT) -#define GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ -#define GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ -#define GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ -#endif /* DMA2D_TRIGGER_SUPPORT */ -#if defined (GPU2D) -#define GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ -#define GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ -#endif /* GPU2D */ -#define GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger signal is ADC4_AWD1 */ -#define GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger signal is ADC1_AWD1 */ -#if defined (GFXTIM) -#define GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ -#define GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ -#endif /* GFXTIM */ -#if defined (JPEG) -#define GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ -#define GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ -#define GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ -#define GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ -#define GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ -#endif /* JPEG */ - -/* LPDMA1 triggers */ -#define LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger signal is EXTI_LINE0 */ -#define LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger signal is EXTI_LINE1 */ -#define LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger signal is EXTI_LINE2 */ -#define LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger signal is EXTI_LINE3 */ -#define LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger signal is EXTI_LINE4 */ -#define LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger signal is TAMP_TRG1 */ -#define LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger signal is TAMP_TRG2 */ -#define LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger signal is TAMP_TRG3 */ -#define LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH1 */ -#define LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger signal is LPTIM1_CH2 */ -#define LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger signal is LPTIM3_CH1 */ -#define LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger signal is LPTIM4_OUT */ -#define LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger signal is COMP1_OUT */ -#if defined(COMP2) -#define LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger signal is COMP2_OUT */ -#endif /* COMP2 */ -#define LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger signal is RTC_ALRA_TRG */ -#define LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger signal is RTC_ALRB_TRG */ -#define LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger signal is RTC_WUT_TRG */ -#define LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger signal is ADC4_AWD1 */ -#define LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH0_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH1_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH2_TCF */ -#define LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger signal is LPDMA1_CH3_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH0_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH1_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH4_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH5_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH6_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH7_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH12_TCF */ -#define LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger signal is GPDMA1_CH13_TCF */ -#define LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger signal is TIM2_TRGO */ -#define LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger signal is TIM15_TRGO */ -/** - * @} - */ - -/** @defgroup DMAEx_Node_Type DMAEx Node Type - * @brief DMAEx Node Type - * @{ - */ -#define DMA_LPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_LPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the LPDMA linear addressing node type */ -#define DMA_GPDMA_LINEAR_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_LINEAR_ADDR) /*!< Defines the GPDMA linear addressing node type */ -#define DMA_GPDMA_2D_NODE (DMA_CHANNEL_TYPE_GPDMA | DMA_CHANNEL_TYPE_2D_ADDR) /*!< Defines the GPDMA 2 dimension addressing node type */ -/** - * @} - */ - -/** @defgroup DMAEx_Link_Allocated_Port DMAEx Linked-List Allocated Port - * @brief DMAEx Linked-List Allocated Port - * @{ - */ -#define DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Link allocated port 0 */ -#define DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Link allocated port 1 */ -/** - * @} - */ - -/** @defgroup DMAEx_Link_Step_Mode DMAEx Link Step Mode - * @brief DMAEx Link Step Mode - * @{ - */ -#define DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel is executed for the full linked-list */ -#define DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel is executed once for the current LLI */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions ------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions - * @brief DMAEx Exported functions - * @{ - */ - -/** @defgroup DMAEx_Exported_Functions_Group1 Linked-List Initialization and De-Initialization Functions - * @brief Linked-List Initialization and De-Initialization Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma); -/** - * @} - */ - -/** @defgroup DMAEx_Exported_Functions_Group2 Linked-List IO Operation Functions - * @brief Linked-List IO Operation Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma); -/** - * @} - */ - -/** @defgroup DMAEx_Exported_Functions_Group3 Linked-List Management Functions - * @brief Linked-List Management Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, - DMA_NodeTypeDef *const pNode); -HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, - DMA_NodeTypeDef const *const pNode); - -HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pPrevNode, - DMA_NodeTypeDef *const pNewNode); -HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode); -HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode); - -HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNode); -HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList); -HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList); - -HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pOldNode, - DMA_NodeTypeDef *const pNewNode); -HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode); -HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode); - -HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList); - -HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, - DMA_NodeTypeDef const *const pPrevNode, - DMA_QListTypeDef *const pDestQList); -HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, - DMA_QListTypeDef *const pDestQList); -HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, - DMA_QListTypeDef *const pDestQList); - -HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pFirstCircularNode); -HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList); -HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList); - -HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList); -HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList); - -HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, - DMA_QListTypeDef *const pQList); -HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma); -/** - * @} - */ - -/** @defgroup DMAEx_Exported_Functions_Group4 Data Handling, Repeated Block and Trigger Configuration Functions - * @brief Data Handling, Repeated Block and Trigger Configuration Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, - DMA_DataHandlingConfTypeDef const *const pConfigDataHandling); -HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, - DMA_TriggerConfTypeDef const *const pConfigTrigger); -HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, - DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock); -/** - * @} - */ - -/** @defgroup DMAEx_Exported_Functions_Group5 Suspend and Resume Operation Functions - * @brief Suspend and Resume Operation Functions - * @{ - */ -HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma); -HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma); -/** - * @} - */ - -/** @defgroup DMAEx_Exported_Functions_Group6 FIFO Status Function - * @brief FIFO Status Function - * @{ - */ -uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma); -/** - * @} - */ - -/** - * @} - */ - -/* Private types -----------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Types DMAEx Private Types - * @brief DMAEx Private Types - * @{ - */ - -/** - * @brief DMA Node in Queue Information Structure Definition. - */ -typedef struct -{ - uint32_t cllr_offset; /* CLLR register offset */ - - uint32_t previousnode_addr; /* Previous node address */ - - uint32_t currentnode_pos; /* Current node position */ - - uint32_t currentnode_addr; /* Current node address */ - - uint32_t nextnode_addr; /* Next node address */ - -} DMA_NodeInQInfoTypeDef; -/** - * @} - */ - -/* Private constants -------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Constants DMAEx Private Constants - * @brief DMAEx Private Constants - * @{ - */ -#define DMA_LINKEDLIST (0x0080U) /* DMA channel linked-list mode */ - -#define DMA_CHANNEL_TYPE_LINEAR_ADDR (0x0001U) /* DMA channel linear addressing mode */ -#define DMA_CHANNEL_TYPE_2D_ADDR (0x0002U) /* DMA channel 2D addressing mode */ -#define DMA_CHANNEL_TYPE_LPDMA (0x0010U) /* LPDMA channel node */ -#define DMA_CHANNEL_TYPE_GPDMA (0x0020U) /* GPDMA channel node */ - -#define NODE_TYPE_MASK (0x00FFU) /* DMA channel node type */ -#define NODE_CLLR_IDX (0x0700U) /* DMA channel node CLLR index mask */ -#define NODE_CLLR_IDX_POS (0x0008U) /* DMA channel node CLLR index position */ - -#define NODE_MAXIMUM_SIZE (0x0008U) /* Amount of registers of the node */ - -#define NODE_STATIC_FORMAT (0x0000U) /* DMA channel node static format */ -#define NODE_DYNAMIC_FORMAT (0x0001U) /* DMA channel node dynamic format */ - -#define UPDATE_CLLR_POSITION (0x0000U) /* DMA channel update CLLR position */ -#define UPDATE_CLLR_VALUE (0x0001U) /* DMA channel update CLLR value */ - -#define LASTNODE_ISNOT_CIRCULAR (0x0000U) /* Last node is not first circular node */ -#define LASTNODE_IS_CIRCULAR (0x0001U) /* Last node is first circular node */ - -#define QUEUE_TYPE_STATIC (0x0000U) /* DMA channel static queue */ -#define QUEUE_TYPE_DYNAMIC (0x0001U) /* DMA channel dynamic queue */ - -#define NODE_CTR1_DEFAULT_OFFSET (0x0000U) /* CTR1 default offset */ -#define NODE_CTR2_DEFAULT_OFFSET (0x0001U) /* CTR2 default offset */ -#define NODE_CBR1_DEFAULT_OFFSET (0x0002U) /* CBR1 default offset */ -#define NODE_CSAR_DEFAULT_OFFSET (0x0003U) /* CSAR default offset */ -#define NODE_CDAR_DEFAULT_OFFSET (0x0004U) /* CDAR default offset */ -#define NODE_CTR3_DEFAULT_OFFSET (0x0005U) /* CTR3 2D addressing default offset */ -#define NODE_CBR2_DEFAULT_OFFSET (0x0006U) /* CBR2 2D addressing default offset */ -#define NODE_CLLR_2D_DEFAULT_OFFSET (0x0007U) /* CLLR 2D addressing default offset */ -#define NODE_CLLR_LINEAR_DEFAULT_OFFSET (0x0005U) /* CLLR linear addressing default offset */ - -#define DMA_BURST_ADDR_OFFSET_MIN (-8192L) /* DMA burst minimum address offset */ -#define DMA_BURST_ADDR_OFFSET_MAX (8192L) /* DMA burst maximum address offset */ -#define DMA_BLOCK_ADDR_OFFSET_MIN (-65536L) /* DMA block minimum address offset */ -#define DMA_BLOCK_ADDR_OFFSET_MAX (65536L) /* DMA block maximum address offset */ -/** - * @} - */ - -/* Private macros ----------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Macros DMAEx Private Macros - * @brief DMAEx Private Macros - * @{ - */ -#define IS_DMA_DATA_ALIGNMENT(ALIGNMENT) \ - (((ALIGNMENT) == DMA_DATA_RIGHTALIGN_ZEROPADDED) || \ - ((ALIGNMENT) == DMA_DATA_RIGHTALIGN_SIGNEXT) || \ - ((ALIGNMENT) == DMA_DATA_PACK)) - -#define IS_DMA_DATA_EXCHANGE(EXCHANGE) \ - (((EXCHANGE) & (~(DMA_EXCHANGE_SRC_BYTE | DMA_EXCHANGE_DEST_BYTE | DMA_EXCHANGE_DEST_HALFWORD))) == 0U) - -#define IS_DMA_REPEAT_COUNT(COUNT) \ - (((COUNT) > 0U) && ((COUNT) <= (DMA_CBR1_BRC >> DMA_CBR1_BRC_Pos))) - -#define IS_DMA_BURST_ADDR_OFFSET(BURST_ADDR_OFFSET) \ - (((BURST_ADDR_OFFSET) > DMA_BURST_ADDR_OFFSET_MIN) && \ - ((BURST_ADDR_OFFSET) < DMA_BURST_ADDR_OFFSET_MAX)) - -#define IS_DMA_BLOCK_ADDR_OFFSET(BLOCK_ADDR_OFFSET) \ - (((BLOCK_ADDR_OFFSET) > DMA_BLOCK_ADDR_OFFSET_MIN) && \ - ((BLOCK_ADDR_OFFSET) < DMA_BLOCK_ADDR_OFFSET_MAX)) - -#define IS_DMA_LINK_ALLOCATED_PORT(LINK_ALLOCATED_PORT) \ - (((LINK_ALLOCATED_PORT) & (~(DMA_CCR_LAP))) == 0U) - -#define IS_DMA_LINK_STEP_MODE(MODE) \ - (((MODE) == DMA_LSM_FULL_EXECUTION) || \ - ((MODE) == DMA_LSM_1LINK_EXECUTION)) - -#define IS_DMA_TRIGGER_MODE(MODE) \ - (((MODE) == DMA_TRIGM_BLOCK_TRANSFER) || \ - ((MODE) == DMA_TRIGM_REPEATED_BLOCK_TRANSFER) || \ - ((MODE) == DMA_TRIGM_LLI_LINK_TRANSFER) || \ - ((MODE) == DMA_TRIGM_SINGLE_BURST_TRANSFER)) - -#define IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(MODE) \ - (((MODE) == DMA_TCEM_BLOCK_TRANSFER) || \ - ((MODE) == DMA_TCEM_REPEATED_BLOCK_TRANSFER) || \ - ((MODE) == DMA_TCEM_EACH_LL_ITEM_TRANSFER) || \ - ((MODE) == DMA_TCEM_LAST_LL_ITEM_TRANSFER)) - -#define IS_DMA_LINKEDLIST_MODE(MODE) \ - (((MODE) == DMA_LINKEDLIST_NORMAL) || \ - ((MODE) == DMA_LINKEDLIST_CIRCULAR)) - -#define IS_DMA_TRIGGER_POLARITY(POLARITY) \ - (((POLARITY) == DMA_TRIG_POLARITY_MASKED) || \ - ((POLARITY) == DMA_TRIG_POLARITY_RISING) || \ - ((POLARITY) == DMA_TRIG_POLARITY_FALLING)) - -#if defined (GPDMA1_TRIGGER_JPEG_OFT) -#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_JPEG_OFT) -#else -#define IS_DMA_TRIGGER_SELECTION(TRIGGER) ((TRIGGER) <= GPDMA1_TRIGGER_ADC1_AWD1) -#endif /* GPDMA1_TRIGGER_JPEG_OFT */ - -#define IS_DMA_NODE_TYPE(TYPE) \ - (((TYPE) == DMA_LPDMA_LINEAR_NODE) || \ - ((TYPE) == DMA_GPDMA_LINEAR_NODE) || \ - ((TYPE) == DMA_GPDMA_2D_NODE)) -/** - * @} - */ - - -/* Private functions -------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Functions DMAEx Private Functions - * @brief DMAEx Private Functions - * @{ - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* STM32U5xx_HAL_DMA_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h deleted file mode 100644 index 13afdd2da..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_exti.h +++ /dev/null @@ -1,393 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_exti.h - * @author MCD Application Team - * @brief Header file of EXTI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_EXTI_H -#define STM32U5xx_HAL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup EXTI EXTI - * @brief EXTI HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup EXTI_Exported_Types EXTI Exported Types - * @{ - */ -typedef enum -{ - HAL_EXTI_COMMON_CB_ID = 0x00U, - HAL_EXTI_RISING_CB_ID = 0x01U, - HAL_EXTI_FALLING_CB_ID = 0x02U, -} EXTI_CallbackIDTypeDef; - - -/** - * @brief EXTI Handle structure definition - */ -typedef struct -{ - uint32_t Line; /*!< Exti line number */ - void (* RisingCallback)(void); /*!< Exti rising callback */ - void (* FallingCallback)(void); /*!< Exti falling callback */ -} EXTI_HandleTypeDef; - -/** - * @brief EXTI Configuration structure definition - */ -typedef struct -{ - uint32_t Line; /*!< The Exti line to be configured. This parameter - can be a value of @ref EXTI_Line */ - uint32_t Mode; /*!< The Exit Mode to be configured for a core. - This parameter can be a combination of @ref EXTI_Mode */ - uint32_t Trigger; /*!< The Exti Trigger to be configured. This parameter - can be a value of @ref EXTI_Trigger */ - uint32_t GPIOSel; /*!< The Exti GPIO multiplexer selection to be configured. - This parameter is only possible for line 0 to 15. It - can be a value of @ref EXTI_GPIOSel */ -} EXTI_ConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_Line EXTI Line - * @{ - */ -#define EXTI_LINE_0 (EXTI_GPIO | EXTI_REG1 | 0x00U) -#define EXTI_LINE_1 (EXTI_GPIO | EXTI_REG1 | 0x01U) -#define EXTI_LINE_2 (EXTI_GPIO | EXTI_REG1 | 0x02U) -#define EXTI_LINE_3 (EXTI_GPIO | EXTI_REG1 | 0x03U) -#define EXTI_LINE_4 (EXTI_GPIO | EXTI_REG1 | 0x04U) -#define EXTI_LINE_5 (EXTI_GPIO | EXTI_REG1 | 0x05U) -#define EXTI_LINE_6 (EXTI_GPIO | EXTI_REG1 | 0x06U) -#define EXTI_LINE_7 (EXTI_GPIO | EXTI_REG1 | 0x07U) -#define EXTI_LINE_8 (EXTI_GPIO | EXTI_REG1 | 0x08U) -#define EXTI_LINE_9 (EXTI_GPIO | EXTI_REG1 | 0x09U) -#define EXTI_LINE_10 (EXTI_GPIO | EXTI_REG1 | 0x0AU) -#define EXTI_LINE_11 (EXTI_GPIO | EXTI_REG1 | 0x0BU) -#define EXTI_LINE_12 (EXTI_GPIO | EXTI_REG1 | 0x0CU) -#define EXTI_LINE_13 (EXTI_GPIO | EXTI_REG1 | 0x0DU) -#define EXTI_LINE_14 (EXTI_GPIO | EXTI_REG1 | 0x0EU) -#define EXTI_LINE_15 (EXTI_GPIO | EXTI_REG1 | 0x0FU) -#define EXTI_LINE_16 (EXTI_CONFIG | EXTI_REG1 | 0x10U) -#define EXTI_LINE_17 (EXTI_CONFIG | EXTI_REG1 | 0x11U) -#if defined(EXTI_IMR1_IM18) -#define EXTI_LINE_18 (EXTI_CONFIG | EXTI_REG1 | 0x12U) -#endif /* EXTI_IMR1_IM18 */ -#define EXTI_LINE_19 (EXTI_CONFIG | EXTI_REG1 | 0x13U) -#define EXTI_LINE_20 (EXTI_CONFIG | EXTI_REG1 | 0x14U) -#define EXTI_LINE_21 (EXTI_CONFIG | EXTI_REG1 | 0x15U) -#define EXTI_LINE_22 (EXTI_CONFIG | EXTI_REG1 | 0x16U) -#define EXTI_LINE_23 (EXTI_CONFIG | EXTI_REG1 | 0x17U) -#if defined(EXTI_IMR1_IM24) -#define EXTI_LINE_24 (EXTI_CONFIG | EXTI_REG1 | 0x18U) -#endif /* EXTI_IMR1_IM24 */ -#if defined(EXTI_IMR1_IM25) -#define EXTI_LINE_25 (EXTI_CONFIG | EXTI_REG1 | 0x19U) -#endif /* EXTI_IMR1_IM25 */ -/** - * @} - */ - -/** @defgroup EXTI_Mode EXTI Mode - * @{ - */ -#define EXTI_MODE_NONE 0x00000000U -#define EXTI_MODE_INTERRUPT 0x00000001U -#define EXTI_MODE_EVENT 0x00000002U -/** - * @} - */ - -/** @defgroup EXTI_Trigger EXTI Trigger - * @{ - */ -#define EXTI_TRIGGER_NONE 0x00000000U -#define EXTI_TRIGGER_RISING 0x00000001U -#define EXTI_TRIGGER_FALLING 0x00000002U -#define EXTI_TRIGGER_RISING_FALLING (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) -/** - * @} - */ - -/** @defgroup EXTI_GPIOSel EXTI GPIOSel - * @brief - * @{ - */ -#define EXTI_GPIOA 0x00000000U -#define EXTI_GPIOB 0x00000001U -#define EXTI_GPIOC 0x00000002U -#define EXTI_GPIOD 0x00000003U -#define EXTI_GPIOE 0x00000004U -#if defined(GPIOF) -#define EXTI_GPIOF 0x00000005U -#endif /* GPIOF */ -#define EXTI_GPIOG 0x00000006U -#define EXTI_GPIOH 0x00000007U -#if defined(GPIOI) -#define EXTI_GPIOI 0x00000008U -#endif /* GPIOI */ -#if defined(GPIOJ) -#define EXTI_GPIOJ 0x00000009U -#endif /* GPIOJ */ - -/** - * @} - */ - -/** @defgroup EXTI_Line_attributes EXTI line attributes - * @brief EXTI line secure or non-secure and privileged or non-privileged attributes - * @note secure and non-secure attributes are only available from secure state when the system - * implement the security (TZEN=1) - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/*!< Secure line attribute */ -#define EXTI_LINE_SEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000001U) -/*!< Non-secure line attribute */ -#define EXTI_LINE_NSEC (EXTI_LINE_ATTR_SEC_MASK | 0x00000000U) -#endif /* __ARM_FEATURE_CMSE */ -/*!< Privileged line attribute */ -#define EXTI_LINE_PRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000002U) -/*!< Non-privileged line attribute */ -#define EXTI_LINE_NPRIV (EXTI_LINE_ATTR_PRIV_MASK | 0x00000000U) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Private constants --------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ -/** - * @brief EXTI Line property definition - */ -#define EXTI_PROPERTY_SHIFT 24U -#define EXTI_DIRECT (0x01U << EXTI_PROPERTY_SHIFT) -#define EXTI_CONFIG (0x02U << EXTI_PROPERTY_SHIFT) -#define EXTI_GPIO ((0x04U << EXTI_PROPERTY_SHIFT) | EXTI_CONFIG) -#define EXTI_RESERVED (0x08U << EXTI_PROPERTY_SHIFT) -#define EXTI_PROPERTY_MASK (EXTI_DIRECT | EXTI_CONFIG | EXTI_GPIO) - -/** - * @brief EXTI Register and bit usage - */ -#define EXTI_REG_SHIFT 16U -#define EXTI_REG1 (0x00U << EXTI_REG_SHIFT) -#define EXTI_REG2 (0x01U << EXTI_REG_SHIFT) -#define EXTI_REG_MASK (EXTI_REG1 | EXTI_REG2) -#define EXTI_PIN_MASK 0x0000001FU - -/** - * @brief EXTI Mask for interrupt & event mode - */ -#define EXTI_MODE_MASK (EXTI_MODE_EVENT | EXTI_MODE_INTERRUPT) - -/** - * @brief EXTI Mask for trigger possibilities - */ -#define EXTI_TRIGGER_MASK (EXTI_TRIGGER_RISING | EXTI_TRIGGER_FALLING) - -/** - * @brief EXTI Line number - */ -#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) -#define EXTI_LINE_NB 26U -#else -#define EXTI_LINE_NB 24U -#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */ - -/** - * @brief EXTI Mask for secure & privilege attributes - */ -#define EXTI_LINE_ATTR_SEC_MASK 0x100U -#define EXTI_LINE_ATTR_PRIV_MASK 0x200U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup EXTI_Private_Macros EXTI Private Macros - * @{ - */ -#define IS_EXTI_LINE(__EXTI_LINE__) ((((__EXTI_LINE__) & ~(EXTI_PROPERTY_MASK | \ - EXTI_REG_MASK | EXTI_PIN_MASK)) == 0x00U) \ - &&((((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_DIRECT) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_CONFIG) || \ - (((__EXTI_LINE__) & EXTI_PROPERTY_MASK) == EXTI_GPIO)) && \ - (((__EXTI_LINE__) & (EXTI_REG_MASK | EXTI_PIN_MASK)) < \ - (((EXTI_LINE_NB / 32U) << EXTI_REG_SHIFT) | (EXTI_LINE_NB % 32U)))) - -#define IS_EXTI_MODE(__EXTI_LINE__) ((((__EXTI_LINE__) & EXTI_MODE_MASK) != 0x00U) && \ - (((__EXTI_LINE__) & ~EXTI_MODE_MASK) == 0x00U)) - -#define IS_EXTI_TRIGGER(__EXTI_LINE__) (((__EXTI_LINE__) & ~EXTI_TRIGGER_MASK) == 0x00U) - -#define IS_EXTI_PENDING_EDGE(__EXTI_LINE__) (((__EXTI_LINE__) == EXTI_TRIGGER_RISING) || \ - ((__EXTI_LINE__) == EXTI_TRIGGER_FALLING)) - -#define IS_EXTI_CONFIG_LINE(__EXTI_LINE__) (((__EXTI_LINE__) & EXTI_CONFIG) != 0x00U) - -#if defined(GPIOJ) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH) || \ - ((__PORT__) == EXTI_GPIOI) || \ - ((__PORT__) == EXTI_GPIOJ)) -#elif defined(GPIOF) && defined (GPIOI) -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOF) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH) || \ - ((__PORT__) == EXTI_GPIOI)) -#else -#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ - ((__PORT__) == EXTI_GPIOB) || \ - ((__PORT__) == EXTI_GPIOC) || \ - ((__PORT__) == EXTI_GPIOD) || \ - ((__PORT__) == EXTI_GPIOE) || \ - ((__PORT__) == EXTI_GPIOG) || \ - ((__PORT__) == EXTI_GPIOH)) -#endif /* GPIOJ */ - -#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16U) - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_SEC) == EXTI_LINE_SEC) || \ - (((__ATTRIBUTES__) & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) || \ - (((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ - (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ - (((__ATTRIBUTES__) & ~(EXTI_LINE_SEC|EXTI_LINE_NSEC|EXTI_LINE_PRIV| \ - EXTI_LINE_NPRIV)) == 0U)) - -#else - -#define IS_EXTI_LINE_ATTRIBUTES(__ATTRIBUTES__) (((((__ATTRIBUTES__) & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) || \ - (((__ATTRIBUTES__) & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV)) && \ - (((__ATTRIBUTES__) & ~(EXTI_LINE_PRIV|EXTI_LINE_NPRIV)) == 0U)) - -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_Exported_Functions EXTI Exported Functions - * @brief EXTI Exported Functions - * @{ - */ - -/** @defgroup EXTI_Exported_Functions_Group1 Configuration functions - * @brief Configuration functions - * @{ - */ -/* Configuration functions ****************************************************/ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, - void (*pPendingCbfn)(void)); -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); - -/** - * @} - */ - -/** @addtogroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions - * @{ - */ - -/* EXTI line attributes management functions **********************************/ -void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes); -HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -void HAL_EXTI_LockAttributes(void); -uint32_t HAL_EXTI_GetLockAttributes(void); -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_EXTI_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h deleted file mode 100644 index 1a003f2d7..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash.h +++ /dev/null @@ -1,1122 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_flash.h - * @author MCD Application Team - * @brief Header file of FLASH HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_FLASH_H -#define STM32U5xx_HAL_FLASH_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASH - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Types FLASH Exported Types - * @{ - */ - -/** - * @brief FLASH Erase structure definition - */ -typedef struct -{ - uint32_t TypeErase; /*!< Mass erase or page erase. - This parameter can be a value of @ref FLASH_Type_Erase */ - uint32_t Banks; /*!< Select bank to erase. - This parameter must be a value of @ref FLASH_Banks - (FLASH_BANK_BOTH should be used only for mass erase) */ - uint32_t Page; /*!< Initial Flash page to erase when page erase is disabled - This parameter must be a value between 0 and (max number of pages in the bank - 1) - (eg : 127 for 2MB dual bank) */ - uint32_t NbPages; /*!< Number of pages to be erased. This parameter must be a value between 1 and - (max number of pages in the bank - value of initial page)*/ -} FLASH_EraseInitTypeDef; - -/** - * @brief FLASH Option Bytes Program structure definition - */ -typedef struct -{ - uint32_t OptionType; /*!< Option byte to be configured. - This parameter can be a combination of the values of @ref FLASH_OB_Type */ - uint32_t WRPArea; /*!< Write protection area to be programmed (used for OPTIONBYTE_WRP). - Only one WRP area could be programmed at the same time. - This parameter can be value of @ref FLASH_OB_WRP_Area */ - uint32_t WRPStartOffset; /*!< Write protection start offset (used for OPTIONBYTE_WRP). - This parameter must be a value between 0 and (max number of pages in the bank - 1) */ - uint32_t WRPEndOffset; /*!< Write protection end offset (used for OPTIONBYTE_WRP). - This parameter must be a value between WRPStartOffset - and (max number of pages in the bank - 1) */ - FunctionalState WRPLock; /*!< Write protection lock (used for OPTIONBYTE_WRP). - This parameter can be set to ENABLE or DISABLE */ - uint32_t RDPLevel; /*!< Set the read protection level (used for OPTIONBYTE_RDP). - This parameter can be a value of @ref FLASH_OB_Read_Protection */ - uint32_t USERType; /*!< User option byte(s) to be configured (used for OPTIONBYTE_USER). - This parameter can be a combination of @ref FLASH_OB_USER_Type */ - uint32_t USERConfig; /*!< Value of the user option byte (used for OPTIONBYTE_USER). - This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, - @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, - @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, - @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, - @ref FLASH_OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, - @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, - @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, - @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, - @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, - @ref FLASH_OB_USER_IO_VDDIO2_HSLV, @ref FLASH_OB_USER_TZEN */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t WMSecConfig; /*!< Configuration of the Watermark-based Secure Area (used for OPTIONBYTE_WMSEC). - This parameter must be a value of @ref FLASH_OB_WMSEC */ - uint32_t WMSecStartPage; /*!< Start page of secure area (used for OPTIONBYTE_WMSEC). - This parameter must be a value between 0 and (max number of pages in the bank - 1) */ - uint32_t WMSecEndPage; /*!< End page of secure area (used for OPTIONBYTE_WMSEC). This parameter must be a value - between WMSecStartPage and (max number of pages in the bank - 1) */ - uint32_t WMHDPEndPage; /*!< End page of the secure hide protection (used for OPTIONBYTE_WMSEC). - This parameter must be a value between WMSecStartPage and WMSecEndPage */ - uint32_t BootLock; /*!< Configuration of the boot lock (used for OPTIONBYTE_BOOT_LOCK). - This parameter must be a value of @ref FLASH_OB_BOOT_LOCK */ -#endif /* __ARM_FEATURE_CMSE */ - uint32_t BootAddrConfig; /*!< Configuration of the Boot address (used for OPTIONBYTE_BOOTADDR). - This parameter must be a value of @ref FLASH_OB_BOOTADDR */ - uint32_t BootAddr; /*!< Boot address (used for OPTIONBYTE_BOOTADDR). - This parameter must be a value between 0x0 and 0xFFFFFF00 */ - uint32_t RDPKeyType; /*!< Configuration of the RDP OEM keys (used for OPTIONBYTE_RDPKEY). - This parameter can be a value of @ref FLASH_OB_RDP_Key_Type */ - uint32_t RDPKey1; /*!< Value of the RDP OEM key 1 (used for OPTIONBYTE_RDPKEY) */ - uint32_t RDPKey2; /*!< Value of the RDP OEM key 2 (used for OPTIONBYTE_RDPKEY) */ -} FLASH_OBProgramInitTypeDef; - -/** - * @brief FLASH handle Structure definition - */ -typedef struct -{ - HAL_LockTypeDef Lock; /* FLASH locking object */ - uint32_t ErrorCode; /* FLASH error code */ - uint32_t ProcedureOnGoing; /* Internal variable to indicate which procedure is ongoing - or not in IT context */ - uint32_t Address; /* Internal variable to save address selected for program - in IT context */ - uint32_t Bank; /* Internal variable to save current bank selected during erase - in IT context */ - uint32_t Page; /* Internal variable to define the current page which is being erased - in IT context */ - uint32_t NbPagesToErase; /* Internal variable to save the remaining pages to erase in IT context */ -} FLASH_ProcessTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Constants FLASH Exported Constants - * @{ - */ - -/** @defgroup FLASH_Flags FLASH Flags Definition - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define FLASH_FLAG_EOP FLASH_SECSR_EOP /*!< FLASH End of operation flag */ -#define FLASH_FLAG_OPERR FLASH_SECSR_OPERR /*!< FLASH Operation error flag */ -#define FLASH_FLAG_PROGERR FLASH_SECSR_PROGERR /*!< FLASH Programming error flag */ -#define FLASH_FLAG_WRPERR FLASH_SECSR_WRPERR /*!< FLASH Write protection error flag */ -#define FLASH_FLAG_PGAERR FLASH_SECSR_PGAERR /*!< FLASH Programming alignment error flag */ -#define FLASH_FLAG_SIZERR FLASH_SECSR_SIZERR /*!< FLASH Size error flag */ -#define FLASH_FLAG_PGSERR FLASH_SECSR_PGSERR /*!< FLASH Programming sequence error flag */ -#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ -#define FLASH_FLAG_BSY FLASH_SECSR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_WDW FLASH_SECSR_WDW /*!< FLASH Wait Data to Write flag */ -#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ -#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ - -#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR) -#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) -#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_OPTWERR | FLASH_FLAG_ECCR_ERRORS) -#else -#define FLASH_FLAG_EOP FLASH_NSSR_EOP /*!< FLASH End of operation flag */ -#define FLASH_FLAG_OPERR FLASH_NSSR_OPERR /*!< FLASH Operation error flag */ -#define FLASH_FLAG_PROGERR FLASH_NSSR_PROGERR /*!< FLASH Programming error flag */ -#define FLASH_FLAG_WRPERR FLASH_NSSR_WRPERR /*!< FLASH Write protection error flag */ -#define FLASH_FLAG_PGAERR FLASH_NSSR_PGAERR /*!< FLASH Programming alignment error flag */ -#define FLASH_FLAG_SIZERR FLASH_NSSR_SIZERR /*!< FLASH Size error flag */ -#define FLASH_FLAG_PGSERR FLASH_NSSR_PGSERR /*!< FLASH Programming sequence error flag */ -#define FLASH_FLAG_OPTWERR FLASH_NSSR_OPTWERR /*!< FLASH Option modification error flag */ -#define FLASH_FLAG_BSY FLASH_NSSR_BSY /*!< FLASH Busy flag */ -#define FLASH_FLAG_WDW FLASH_NSSR_WDW /*!< FLASH Wait Data to Write flag */ -#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ -#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ - -#define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ - FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ - FLASH_FLAG_OPTWERR) -#define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) -#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS) -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/** @defgroup FLASH_Interrupt_definition FLASH Interrupts Definition - * @brief FLASH Interrupt definition - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define FLASH_IT_EOP FLASH_SECCR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_OPERR FLASH_SECCR_ERRIE /*!< Error Interrupt source */ -#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ -#else -#define FLASH_IT_EOP FLASH_NSCR_EOPIE /*!< End of FLASH Operation Interrupt source */ -#define FLASH_IT_OPERR FLASH_NSCR_ERRIE /*!< Error Interrupt source */ -#define FLASH_IT_ECCC (FLASH_ECCR_ECCIE >> 24) /*!< ECC Correction Interrupt source */ -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/** @defgroup FLASH_Error FLASH Error - * @{ - */ -#define HAL_FLASH_ERROR_NONE 0x00000000U -#define HAL_FLASH_ERROR_OP FLASH_FLAG_OPERR -#define HAL_FLASH_ERROR_PROG FLASH_FLAG_PROGERR -#define HAL_FLASH_ERROR_WRP FLASH_FLAG_WRPERR -#define HAL_FLASH_ERROR_PGA FLASH_FLAG_PGAERR -#define HAL_FLASH_ERROR_SIZ FLASH_FLAG_SIZERR -#define HAL_FLASH_ERROR_PGS FLASH_FLAG_PGSERR -#define HAL_FLASH_ERROR_OPTW FLASH_FLAG_OPTWERR -#define HAL_FLASH_ERROR_ECCC FLASH_FLAG_ECCC -#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD -/** - * @} - */ - -/** @defgroup FLASH_Type_Erase FLASH Erase Type - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define FLASH_TYPEERASE_PAGES FLASH_SECCR_PER /*!< Secure pages erase - activation */ -#define FLASH_TYPEERASE_PAGES_NS (FLASH_NSCR_PER | FLASH_NON_SECURE_MASK) /*!< Non-secure pages erase - activation */ -#define FLASH_TYPEERASE_MASSERASE (FLASH_SECCR_MER1 | FLASH_SECCR_MER2) /*!< Secure flash mass erase - activation */ -#define FLASH_TYPEERASE_MASSERASE_NS (FLASH_NSCR_MER1 | FLASH_NSCR_MER2 | FLASH_NON_SECURE_MASK) /*!< Non-secure flash - mass erase activation */ -#else -#define FLASH_TYPEERASE_PAGES FLASH_NSCR_PER /*!< Pages erase activation */ -#define FLASH_TYPEERASE_MASSERASE (FLASH_NSCR_MER1 | FLASH_NSCR_MER2) /*!< Flash mass erase activation */ -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/** @defgroup FLASH_Banks FLASH Banks - * @{ - */ -#define FLASH_BANK_1 0x00000001U /*!< Bank 1 */ -#define FLASH_BANK_2 0x00000002U /*!< Bank 2 */ -#define FLASH_BANK_BOTH (FLASH_BANK_1 | FLASH_BANK_2) /*!< Bank1 and Bank2 */ -/** - * @} - */ - -/** @defgroup FLASH_Type_Program FLASH Program Type - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define FLASH_TYPEPROGRAM_QUADWORD FLASH_SECCR_PG /*!< Program a quad-word (128-bit) - at a specified secure address */ -#define FLASH_TYPEPROGRAM_QUADWORD_NS (FLASH_NSCR_PG | FLASH_NON_SECURE_MASK) /*!< Program a quad-word (128-bit) - at a specified non-secure address */ -#define FLASH_TYPEPROGRAM_BURST (FLASH_SECCR_PG | FLASH_SECCR_BWR) /*!< Program a burst (8xquad-word) - at a specified secure address */ -#define FLASH_TYPEPROGRAM_BURST_NS (FLASH_NSCR_PG | FLASH_NSCR_BWR | FLASH_NON_SECURE_MASK) /*!< Program a burst -(8xquad-word) at a specified non-secure address */ -#else -#define FLASH_TYPEPROGRAM_QUADWORD FLASH_NSCR_PG /*!ACR, FLASH_ACR_LATENCY, (__LATENCY__)) - -/** - * @brief Get the FLASH Latency. - * @retval FLASH Latency - * This return value can be one of the following values : - * @arg FLASH_LATENCY_0: FLASH Zero wait state - * @arg FLASH_LATENCY_1: FLASH One wait state - * @arg FLASH_LATENCY_2: FLASH Two wait states - * @arg FLASH_LATENCY_3: FLASH Three wait states - * @arg FLASH_LATENCY_4: FLASH Four wait states - * @arg FLASH_LATENCY_5: FLASH Five wait states - * @arg FLASH_LATENCY_6: FLASH Six wait states - * @arg FLASH_LATENCY_7: FLASH Seven wait states - * @arg FLASH_LATENCY_8: FLASH Eight wait states - * @arg FLASH_LATENCY_9: FLASH Nine wait states - * @arg FLASH_LATENCY_10: FLASH Ten wait states - * @arg FLASH_LATENCY_11: FLASH Eleven wait states - * @arg FLASH_LATENCY_12: FLASH Twelve wait states - * @arg FLASH_LATENCY_13: FLASH Thirteen wait states - * @arg FLASH_LATENCY_14: FLASH Fourteen wait states - * @arg FLASH_LATENCY_15: FLASH Fifteen wait states - */ -#define __HAL_FLASH_GET_LATENCY() READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY) - -/** - * @brief Enable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) - -/** - * @brief Disable the FLASH prefetch buffer. - * @retval None - */ -#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_PRFTEN) - -/** - * @brief Enable the FLASH power down during Low-Power sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE() SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @brief Disable the FLASH power down during Low-Power sleep mode - * @retval none - */ -#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE() CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD) - -/** - * @} - */ - -/** @defgroup FLASH_Interrupt FLASH Interrupts Macros - * @brief macros to handle FLASH interrupts - * @{ - */ - -/** - * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_ECCC: ECC Correction Interrupt - * @retval none - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* Enable secure FLASH interrupts from the secure world */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ - { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ - if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ - { SET_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) -/* Enable non-secure FLASH interrupts from the secure world */ -#define __HAL_FLASH_ENABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ - { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ - if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ - { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) -#else -/* Enable non-secure FLASH interrupts from the non-secure world */ -#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ - { SET_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ - if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ - { SET_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ FLASH interrupt - * This parameter can be any combination of the following values: - * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt - * @arg FLASH_IT_OPERR: Error Interrupt - * @arg FLASH_IT_ECCC: ECC Correction Interrupt - * @retval none - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* Disable secure FLASH interrupts from the secure world */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ - { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ - if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ - { CLEAR_BIT(FLASH->SECCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC)));}\ - } while(0) -/* Disable non-secure FLASH interrupts from the secure world */ -#define __HAL_FLASH_DISABLE_IT_NS(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ - { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); } \ - if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ - { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & \ - (~FLASH_IT_ECCC))); }\ - } while(0) -#else -/* Disable non-secure FLASH interrupts from the non-secure world */ -#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__) do { if(((__INTERRUPT__) & FLASH_IT_ECCC) != 0U) \ - { CLEAR_BIT(FLASH->ECCR, FLASH_ECCR_ECCIE); }\ - if(((__INTERRUPT__) & (~FLASH_IT_ECCC)) != 0U) \ - { CLEAR_BIT(FLASH->NSCR, ((__INTERRUPT__) & (~FLASH_IT_ECCC))); }\ - } while(0) -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Check whether the specified FLASH flag is set or not. - * @param __FLAG__ specifies the FLASH flag to check. - * This parameter can be one of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag - * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag - * @arg FLASH_FLAG_WDW: FLASH Wait Data to Write flag - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @retval The new state of FLASH_FLAG (SET or RESET). - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* Get secure FLASH flags from the secure world */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ - ((((__FLAG__) & (FLASH_FLAG_OPTWERR)) != 0U) ? \ - (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__)) : \ - (READ_BIT(FLASH->SECSR, (__FLAG__)) == (__FLAG__)))) -/* Get non-secure FLASH flags from the secure world */ -#define __HAL_FLASH_GET_FLAG_NS(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ - (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) -#else -/* Get non-secure FLASH flags from the non-secure world */ -#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ - (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ - (READ_BIT(FLASH->NSSR, (__FLAG__)) == (__FLAG__))) -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Clear the FLASH's pending flags. - * @param __FLAG__ specifies the FLASH flags to clear. - * This parameter can be any combination of the following values: - * @arg FLASH_FLAG_EOP: FLASH End of Operation flag - * @arg FLASH_FLAG_OPERR: FLASH Operation error flag - * @arg FLASH_FLAG_PROGERR: FLASH Programming error flag - * @arg FLASH_FLAG_WRPERR: FLASH Write protection error flag - * @arg FLASH_FLAG_PGAERR: FLASH Programming alignment error flag - * @arg FLASH_FLAG_SIZERR: FLASH Size error flag - * @arg FLASH_FLAG_PGSERR: FLASH Programming sequence error flag - * @arg FLASH_FLAG_OPTWERR: FLASH Option modification error flag (Only in non-secure) - * @arg FLASH_FLAG_ECCC: FLASH one ECC error has been detected and corrected - * @arg FLASH_FLAG_ECCD: FLASH two ECC errors have been detected - * @arg FLASH_FLAG_ALL_ERRORS: FLASH All errors flags - * @retval None - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* Clear secure FLASH flags from the secure world */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ - { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ - if(((__FLAG__) & FLASH_FLAG_OPTWERR) != 0U) \ - { SET_BIT(FLASH->NSSR, ((__FLAG__) & (FLASH_FLAG_OPTWERR))); }\ - if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS | \ - FLASH_FLAG_OPTWERR)) != 0U) \ - { WRITE_REG(FLASH->SECSR, ((__FLAG__) & \ - ~(FLASH_FLAG_ECCR_ERRORS | FLASH_FLAG_OPTWERR))); }\ - } while(0) -/* Clear non-secure FLASH flags from the secure world */ -#define __HAL_FLASH_CLEAR_FLAG_NS(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ - { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ - if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ - { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ - ~(FLASH_FLAG_ECCR_ERRORS))); }\ - } while(0) -#else -/* Clear non-secure FLASH flags from the non-secure world */ -#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & FLASH_FLAG_ECCR_ERRORS) != 0U) \ - { SET_BIT(FLASH->ECCR, ((__FLAG__) & FLASH_FLAG_ECCR_ERRORS)); }\ - if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) \ - { WRITE_REG(FLASH->NSSR, ((__FLAG__) & \ - ~(FLASH_FLAG_ECCR_ERRORS))); }\ - } while(0) -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/* Include FLASH HAL Extended module */ -#include "stm32u5xx_hal_flash_ex.h" - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASH_Exported_Functions - * @{ - */ - -/* Program operation functions ***********************************************/ -/** @addtogroup FLASH_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress); -/* FLASH IRQ handler method */ -void HAL_FLASH_IRQHandler(void); -/* Callbacks in non blocking modes */ -void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue); -void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup FLASH_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_Lock(void); -/* Option bytes control */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void); -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup FLASH_Exported_Functions_Group3 - * @{ - */ -uint32_t HAL_FLASH_GetError(void); -/** - * @} - */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -extern FLASH_ProcessTypeDef pFlash; -/** - * @} - */ - -/* Private constants --------------------------------------------------------*/ -/** @defgroup FLASH_Private_Constants FLASH Private Constants - * @{ - */ - -#define FLASH_TIMEOUT_VALUE 1000U /* 1 s */ - -#define FLASH_NON_SECURE_MASK 0x80000000U - -#define FLASH_NB_WORDS_IN_BURST 32 - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_PAGES_NS) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE_NS)) -#else -#define IS_FLASH_TYPEERASE(VALUE) (((VALUE) == FLASH_TYPEERASE_PAGES) || \ - ((VALUE) == FLASH_TYPEERASE_MASSERASE)) -#endif /* __ARM_FEATURE_CMSE */ - -#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2) || \ - ((BANK) == FLASH_BANK_BOTH)) - -#define IS_FLASH_BANK_EXCLUSIVE(BANK) (((BANK) == FLASH_BANK_1) || \ - ((BANK) == FLASH_BANK_2)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_QUADWORD_NS) || \ - ((VALUE) == FLASH_TYPEPROGRAM_BURST) || \ - ((VALUE) == FLASH_TYPEPROGRAM_BURST_NS)) -#else -#define IS_FLASH_TYPEPROGRAM(VALUE) (((VALUE) == FLASH_TYPEPROGRAM_QUADWORD) || \ - ((VALUE) == FLASH_TYPEPROGRAM_BURST)) -#endif /* __ARM_FEATURE_CMSE */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) ((((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) || \ - (((ADDRESS) >= FLASH_BASE_NS) && ((ADDRESS) < (FLASH_BASE_NS+FLASH_SIZE)))) -#else -#define IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) < (FLASH_BASE+FLASH_SIZE))) -#endif /* __ARM_FEATURE_CMSE */ - -#define IS_FLASH_OTP_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_OTP_BASE)\ - && ((ADDRESS) < (FLASH_OTP_BASE + FLASH_OTP_SIZE))) - -#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) ((IS_FLASH_MAIN_MEM_ADDRESS(ADDRESS)) || (IS_FLASH_OTP_ADDRESS(ADDRESS))) - -#define IS_FLASH_PAGE(PAGE) ((PAGE) < FLASH_PAGE_NB) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ - OPTIONBYTE_WMSEC | OPTIONBYTE_BOOT_LOCK | OPTIONBYTE_BOOTADDR | \ - OPTIONBYTE_RDPKEY))) -#else -#define IS_OPTIONBYTE(VALUE) (((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | \ - OPTIONBYTE_BOOTADDR | OPTIONBYTE_RDPKEY))) -#endif /* __ARM_FEATURE_CMSE */ - -#define IS_OB_WRPAREA(VALUE) (((VALUE) == OB_WRPAREA_BANK1_AREAA) || ((VALUE) == OB_WRPAREA_BANK1_AREAB) || \ - ((VALUE) == OB_WRPAREA_BANK2_AREAA) || ((VALUE) == OB_WRPAREA_BANK2_AREAB)) - -#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\ - ((LEVEL) == OB_RDP_LEVEL_0_5) ||\ - ((LEVEL) == OB_RDP_LEVEL_1) ||\ - ((LEVEL) == OB_RDP_LEVEL_2)) - -#define IS_OB_USER_TYPE(TYPE) (((TYPE) <= 0x1FFFFFU) && ((TYPE) != 0U)) - -#define IS_OB_USER_BOR_LEVEL(LEVEL) (((LEVEL) == OB_BOR_LEVEL_0) || ((LEVEL) == OB_BOR_LEVEL_1) || \ - ((LEVEL) == OB_BOR_LEVEL_2) || ((LEVEL) == OB_BOR_LEVEL_3) || \ - ((LEVEL) == OB_BOR_LEVEL_4)) - -#define IS_OB_USER_STOP(VALUE) (((VALUE) == OB_STOP_RST) || ((VALUE) == OB_STOP_NORST)) - -#define IS_OB_USER_STANDBY(VALUE) (((VALUE) == OB_STANDBY_RST) || ((VALUE) == OB_STANDBY_NORST)) - -#define IS_OB_USER_SHUTDOWN(VALUE) (((VALUE) == OB_SHUTDOWN_RST) || ((VALUE) == OB_SHUTDOWN_NORST)) - -#define IS_OB_USER_SRAM_RST(VALUE) (((VALUE) == OB_SRAM_RST_ERASE) || ((VALUE) == OB_SRAM_RST_NOT_ERASE)) - -#define IS_OB_USER_IWDG(VALUE) (((VALUE) == OB_IWDG_HW) || ((VALUE) == OB_IWDG_SW)) - -#define IS_OB_USER_IWDG_STOP(VALUE) (((VALUE) == OB_IWDG_STOP_FREEZE) || ((VALUE) == OB_IWDG_STOP_RUN)) - -#define IS_OB_USER_IWDG_STDBY(VALUE) (((VALUE) == OB_IWDG_STDBY_FREEZE) || ((VALUE) == OB_IWDG_STDBY_RUN)) - -#define IS_OB_USER_WWDG(VALUE) (((VALUE) == OB_WWDG_HW) || ((VALUE) == OB_WWDG_SW)) - -#define IS_OB_USER_SWAP_BANK(VALUE) (((VALUE) == OB_SWAP_BANK_DISABLE) || ((VALUE) == OB_SWAP_BANK_ENABLE)) - -#define IS_OB_USER_DUALBANK(VALUE) (((VALUE) == OB_DUALBANK_SINGLE) || ((VALUE) == OB_DUALBANK_DUAL)) - -#define IS_OB_USER_BKPRAM_ECC(VALUE) (((VALUE) == OB_BKPRAM_ECC_ENABLE) || ((VALUE) == OB_BKPRAM_ECC_DISABLE)) - -#define IS_OB_USER_SRAM3_ECC(VALUE) (((VALUE) == OB_SRAM3_ECC_ENABLE) || ((VALUE) == OB_SRAM3_ECC_DISABLE)) - -#define IS_OB_USER_SRAM2_ECC(VALUE) (((VALUE) == OB_SRAM2_ECC_ENABLE) || ((VALUE) == OB_SRAM2_ECC_DISABLE)) - -#define IS_OB_USER_SRAM2_RST(VALUE) (((VALUE) == OB_SRAM2_RST_ERASE) || ((VALUE) == OB_SRAM2_RST_NOT_ERASE)) - -#define IS_OB_USER_SWBOOT0(VALUE) (((VALUE) == OB_BOOT0_FROM_OB) || ((VALUE) == OB_BOOT0_FROM_PIN)) - -#define IS_OB_USER_BOOT0(VALUE) (((VALUE) == OB_NBOOT0_RESET) || ((VALUE) == OB_NBOOT0_SET)) - -#define IS_OB_USER_PA15_PUPEN(VALUE) (((VALUE) == OB_PA15_PUP_DISABLE) || ((VALUE) == OB_PA15_PUP_ENABLE)) - -#define IS_OB_USER_IO_VDD_HSLV(VALUE) (((VALUE) == OB_IO_VDD_HSLV_DISABLE) || ((VALUE) == OB_IO_VDD_HSLV_ENABLE)) - -#define IS_OB_USER_IO_VDDIO2_HSLV(VALUE) (((VALUE) == OB_IO_VDDIO2_HSLV_DISABLE)\ - || ((VALUE) == OB_IO_VDDIO2_HSLV_ENABLE)) - -#define IS_OB_USER_TZEN(VALUE) (((VALUE) == OB_TZEN_DISABLE) || ((VALUE) == OB_TZEN_ENABLE)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_OB_BOOT_LOCK(VALUE) (((VALUE) == OB_BOOT_LOCK_DISABLE) || ((VALUE) == OB_BOOT_LOCK_ENABLE)) - -#define IS_OB_WMSEC_CONFIG(CFG) ((((CFG) & 0x7F3U) != 0U) && \ - (((CFG) & 0x3U) != 0U) && (((CFG) & 0xFFFFF80CU) == 0U)) - -#define IS_OB_WMSEC_AREA_EXCLUSIVE(WMSEC) (((((WMSEC) & OB_WMSEC_AREA1) != 0U) && \ - (((WMSEC) & OB_WMSEC_AREA2) == 0U)) || \ - ((((WMSEC) & OB_WMSEC_AREA2) != 0U) && \ - (((WMSEC) & OB_WMSEC_AREA1) == 0U))) -#endif /* __ARM_FEATURE_CMSE */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1) || \ - ((CFG) == OB_BOOTADDR_SEC0)) -#else -#define IS_OB_BOOTADDR_CONFIG(CFG) (((CFG) == OB_BOOTADDR_NS0) || ((CFG) == OB_BOOTADDR_NS1)) -#endif /* __ARM_FEATURE_CMSE */ - -#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_LATENCY_0) || ((LATENCY) == FLASH_LATENCY_1) || \ - ((LATENCY) == FLASH_LATENCY_2) || ((LATENCY) == FLASH_LATENCY_3) || \ - ((LATENCY) == FLASH_LATENCY_4) || ((LATENCY) == FLASH_LATENCY_5) || \ - ((LATENCY) == FLASH_LATENCY_6) || ((LATENCY) == FLASH_LATENCY_7) || \ - ((LATENCY) == FLASH_LATENCY_8) || ((LATENCY) == FLASH_LATENCY_9) || \ - ((LATENCY) == FLASH_LATENCY_10) || ((LATENCY) == FLASH_LATENCY_11) || \ - ((LATENCY) == FLASH_LATENCY_12) || ((LATENCY) == FLASH_LATENCY_13) || \ - ((LATENCY) == FLASH_LATENCY_14) || ((LATENCY) == FLASH_LATENCY_15)) - -#define IS_OB_RDP_KEY_TYPE(TYPE) (((TYPE) == OB_RDP_KEY_OEM1) || \ - ((TYPE) == OB_RDP_KEY_OEM2)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_FLASH_SECURE_OPERATION() ((pFlash.ProcedureOnGoing & FLASH_NON_SECURE_MASK) == 0U) -#else -#define IS_FLASH_SECURE_OPERATION() (0U) -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_FLASH_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h deleted file mode 100644 index 6add95aca..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_flash_ex.h +++ /dev/null @@ -1,240 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_flash_ex.h - * @author MCD Application Team - * @brief Header file of FLASH HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_FLASH_EX_H -#define STM32U5xx_HAL_FLASH_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup FLASHEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Types FLASHEx Exported Types - * @{ - */ - -/** - * @brief FLASHEx Block-based attributes structure definition - */ - -typedef struct -{ - uint32_t Bank; /*!< Selection of the associated bank of Block-based Area. - This parameter must be a value of @ref FLASH_Banks */ - uint32_t BBAttributesType; /*!< Block-Based Attributes type. This parameter must - be a value of @ref FLASH_BB_Attributes */ - uint32_t BBAttributes_array[FLASH_BLOCKBASED_NB_REG]; /*!< Each bit specifies the block-based attribute configuration - of a page: 0 means page non-protected, 1 means page - protected. Protection (secure or privilege) depends - on BBAttributesType value */ -} FLASH_BBAttributesTypeDef; - - -/** - * @brief FLASHEx Operation structure definition - */ -typedef struct -{ - uint32_t OperationType; /*!< Flash operation Type. - This parameter must be a value of @ref FLASH_Operation_Type */ - uint32_t FlashArea; /*!< Flash operation memory area. - This parameter must be a value of @ref FLASH_Operation_Area */ - uint32_t Address; /*!< Flash operation Address offset. - This parameter is given by bank, and must be a value between 0x0 and 0xFFFF0 */ -} FLASH_OperationTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Constants - * @{ - */ -/** @defgroup PRIV_MODE_CFG FLASH privilege mode configuration - * @{ - */ -#define FLASH_NSPRIV_GRANTED 0x00000000U /*!< access to non-secure Flash registers is granted - to privileged or unprivileged access */ -#define FLASH_NSPRIV_DENIED FLASH_PRIVCFGR_NSPRIV /*!< access to non-secure Flash registers is denied - to non-privilege access */ -#define FLASH_SPRIV_GRANTED 0x00000000U /*!< access to secure Flash registers is granted to privileged - or unprivileged access */ -#define FLASH_SPRIV_DENIED FLASH_PRIVCFGR_SPRIV /*!< access to secure Flash registers is denied - to non-privilege access */ -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** @defgroup SEC_INVERSION_CFG FLASH security inversion configuration - * @{ - */ -#define FLASH_INV_DISABLE 0x00000000U /*!< Security state of Flash is not inverted */ -#define FLASH_INV_ENABLE FLASH_SECCR_INV /*!< Security state of Flash is inverted */ -/** - * @} - */ -#endif /* __ARM_FEATURE_CMSE */ - -/** @defgroup FLASH_LPM_CFG FLASH LPM configuration - * @{ - */ -#define FLASH_LPM_DISABLE 0x00000000U /*!< Flash is in normal read mode */ -#define FLASH_LPM_ENABLE FLASH_ACR_LPM /*!< Flash is in low-power read mode */ -/** - * @} - */ - -/** @defgroup FLASH_BB_Attributes FLASH Block-Base Attributes - * @{ - */ -#define FLASH_BB_SEC 0x01U /*!< Flash Block-Based Security Attributes */ -#define FLASH_BB_PRIV 0x02U /*!< Flash Block-Based Privilege Attributes */ -/** - * @} - */ - -/** @defgroup FLASH_Operation_Type FLASH Operation Type - * @{ - */ -#define FLASH_OPERATION_TYPE_NONE 00000000U /*!< No Flash operation */ -#define FLASH_OPERATION_TYPE_QUADWORD FLASH_OPSR_CODE_OP_0 /*!< Single write operation */ -#define FLASH_OPERATION_TYPE_BURST FLASH_OPSR_CODE_OP_1 /*!< Burst write operation */ -#define FLASH_OPERATION_TYPE_PAGEERASE (FLASH_OPSR_CODE_OP_1 | FLASH_OPSR_CODE_OP_0) /*!< Page erase operation */ -#define FLASH_OPERATION_TYPE_BANKERASE FLASH_OPSR_CODE_OP_2 /*!< Bank erase operation */ -#define FLASH_OPERATION_TYPE_MASSERASE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_0) /*!< Mass erase operation */ -#define FLASH_OPERATION_TYPE_OPTIONCHANGE (FLASH_OPSR_CODE_OP_2 | FLASH_OPSR_CODE_OP_1) /*!< Option change operation */ -/** - * @} - */ - -/** @defgroup FLASH_Operation_Area FLASH Operation Area - * @{ - */ -#define FLASH_OPERATION_AREA_BANK_1 00000000U /*!< Operation in Bank 1 */ -#define FLASH_OPERATION_AREA_BANK_2 FLASH_OPSR_BK_OP /*!< Operation in Bank 2 */ -#define FLASH_OPERATION_AREA_SYSF FLASH_OPSR_SYSF_OP /*!< Operation in System Flash memory */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup FLASHEx_Exported_Functions - * @{ - */ - -/* Extended Program operation functions *************************************/ -/** @addtogroup FLASHEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit); -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit); -HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); -void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks); -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group2 - * @{ - */ -void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode); -uint32_t HAL_FLASHEx_GetPrivMode(void); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState); -uint32_t HAL_FLASHEx_GetSecInversion(void); -#endif /* __ARM_FEATURE_CMSE */ -HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks); -HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM); -uint32_t HAL_FLASHEx_GetLowPowerRead(void); -void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation); -/** - * @} - */ - -/** - * @} - */ - -/* Private function ----------------------------------------------------------*/ -/** @addtogroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -void FLASH_PageErase(uint32_t Page, uint32_t Banks); -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup FLASHEx_Private_Macros FLASH Private Macros - * @{ - */ -#define IS_FLASH_BB_EXCLUSIVE(CFG) (((CFG) == FLASH_BB_SEC) || \ - ((CFG) == FLASH_BB_PRIV)) - -#define IS_FLASH_CFGPRIVMODE(CFG) (((CFG) & 0xFFFFFFFCU) == 0U) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_FLASH_CFGSECINV(CFG) (((CFG) == FLASH_INV_DISABLE) || \ - ((CFG) == FLASH_INV_ENABLE)) -#endif /* __ARM_FEATURE_CMSE */ - -#define IS_FLASH_CFGLPM(CFG) (((CFG) == FLASH_LPM_DISABLE) || \ - ((CFG) == FLASH_LPM_ENABLE)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_FLASH_EX_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h deleted file mode 100644 index 61cdc0e63..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio.h +++ /dev/null @@ -1,410 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_GPIO_H -#define STM32U5xx_HAL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIO GPIO - * @brief GPIO HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GPIO_Exported_Types GPIO Exported Types - * @{ - */ -/** - * @brief GPIO Init structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be a value of @ref GPIO_pins */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_mode */ - - uint32_t Pull; /*!< Specifies the Pull-up or Pull-Down activation for the selected pins. - This parameter can be a value of @ref GPIO_pull */ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_speed */ - - uint32_t Alternate; /*!< Peripheral to be connected to the selected pins - This parameter can be a value of @ref GPIOEx_Alternate_function_selection */ -} GPIO_InitTypeDef; - -/** - * @brief GPIO Bit SET and Bit RESET enumeration - */ -typedef enum -{ - GPIO_PIN_RESET = 0U, - GPIO_PIN_SET -} GPIO_PinState; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Constants GPIO Exported Constants - * @{ - */ -/** @defgroup GPIO_pins GPIO pins - * @{ - */ -#define GPIO_PIN_0 ((uint16_t)0x0001) -#define GPIO_PIN_1 ((uint16_t)0x0002) -#define GPIO_PIN_2 ((uint16_t)0x0004) -#define GPIO_PIN_3 ((uint16_t)0x0008) -#define GPIO_PIN_4 ((uint16_t)0x0010) -#define GPIO_PIN_5 ((uint16_t)0x0020) -#define GPIO_PIN_6 ((uint16_t)0x0040) -#define GPIO_PIN_7 ((uint16_t)0x0080) -#define GPIO_PIN_8 ((uint16_t)0x0100) -#define GPIO_PIN_9 ((uint16_t)0x0200) -#define GPIO_PIN_10 ((uint16_t)0x0400) -#define GPIO_PIN_11 ((uint16_t)0x0800) -#define GPIO_PIN_12 ((uint16_t)0x1000) -#define GPIO_PIN_13 ((uint16_t)0x2000) -#define GPIO_PIN_14 ((uint16_t)0x4000) -#define GPIO_PIN_15 ((uint16_t)0x8000) -#define GPIO_PIN_ALL ((uint16_t)0xFFFF) - -#define GPIO_PIN_MASK (0x0000FFFFU) -/** - * @} - */ - -/** @defgroup GPIO_mode GPIO mode - * @brief GPIO Configuration Mode - * Elements values convention: 0xX0yz00YZ - * - X : GPIO mode or EXTI Mode - * - y : External IT or Event trigger detection - * - z : IO configuration on External IT or Event - * - Y : Output type (Push Pull or Open Drain) - * - Z : IO Direction mode (Input, Output, (Alternate or Analog) not applicable in case of LPGPIO) - * @{ - */ -/*!< Input Floating Mode */ -#define GPIO_MODE_INPUT (0x00000000U) -/*!< Output Push Pull Mode */ -#define GPIO_MODE_OUTPUT_PP (0x00000001U) -/*!< Output Open Drain Mode */ -#define GPIO_MODE_OUTPUT_OD (0x00000011U) -/*!< Alternate Function Push Pull Mode */ -#define GPIO_MODE_AF_PP (0x00000002U) -/*!< Alternate Function Open Drain Mode */ -#define GPIO_MODE_AF_OD (0x00000012U) -/*!< Analog Mode */ -#define GPIO_MODE_ANALOG (0x00000003U) -/*!< External Interrupt Mode with Rising edge trigger detection */ -#define GPIO_MODE_IT_RISING (0x10110000U) -/*!< External Interrupt Mode with Falling edge trigger detection */ -#define GPIO_MODE_IT_FALLING (0x10210000U) -/*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_IT_RISING_FALLING (0x10310000U) -/*!< External Event Mode with Rising edge trigger detection */ -#define GPIO_MODE_EVT_RISING (0x10120000U) -/*!< External Event Mode with Falling edge trigger detection */ -#define GPIO_MODE_EVT_FALLING (0x10220000U) -/*!< External Event Mode with Rising/Falling edge trigger detection */ -#define GPIO_MODE_EVT_RISING_FALLING (0x10320000U) -/** - * @} - */ - -/** @defgroup GPIO_speed GPIO speed - * @brief GPIO Output Maximum frequency - * @{ - */ -#define GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Low speed */ -#define GPIO_SPEED_FREQ_MEDIUM (0x00000001U) /*!< Medium speed */ -#define GPIO_SPEED_FREQ_HIGH (0x00000002U) /*!< High speed */ -#define GPIO_SPEED_FREQ_VERY_HIGH (0x00000003U) /*!< Very-high speed */ -/** - * @} - */ - -/** @defgroup GPIO_pull GPIO pull - * @brief GPIO Pull-Up or Pull-Down Activation - * @{ - */ -#define GPIO_NOPULL (0x00000000U) /*!< No Pull-up or Pull-down activation */ -#define GPIO_PULLUP (0x00000001U) /*!< Pull-up activation */ -#define GPIO_PULLDOWN (0x00000002U) /*!< Pull-down activation */ -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @defgroup GPIO_attributes GPIO attributes - * @brief GPIO pin secure or non-secure attributes - * @{ - */ -#define GPIO_PIN_SEC (0x00000001U) /*!< Secure pin attribute */ -#define GPIO_PIN_NSEC (0x00000000U) /*!< Non-secure pin attribute */ -/** - * @} - */ - -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** - * @brief Check whether the specified EXTI line is rising edge asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line rising pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__) (EXTI->RPR1 = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line is falling edge asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 & (__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line falling pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__) (EXTI->FPR1 = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (__HAL_GPIO_EXTI_GET_RISING_IT(__EXTI_LINE__) || \ - __HAL_GPIO_EXTI_GET_FALLING_IT(__EXTI_LINE__)) - -/** - * @brief Clear the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) \ - do { \ - __HAL_GPIO_EXTI_CLEAR_RISING_IT(__EXTI_LINE__); \ - __HAL_GPIO_EXTI_CLEAR_FALLING_IT(__EXTI_LINE__); \ - } while(0) - - -/** - * @brief Generate a Software interrupt on selected EXTI line(s). - * @param __EXTI_LINE__: specifies the EXTI line to set. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER1 = (__EXTI_LINE__)) - -/** - * @brief Check whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__ specifies the EXTI line flag to check. - * This parameter can be GPIO_PIN_x where x can be(0..15) - * @retval The new state of __EXTI_LINE__ (SET or RESET). - */ -#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) - -/** - * @brief Clear the EXTI line pending flags. - * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. - * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) - * @retval None - */ -#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup GPIO_Private_Macros GPIO Private Macros - * @{ - */ -#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) - -#define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\ - (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00U)) - -#define IS_GPIO_SINGLE_PIN(__PIN__) (((__PIN__) == GPIO_PIN_0) ||\ - ((__PIN__) == GPIO_PIN_1) ||\ - ((__PIN__) == GPIO_PIN_2) ||\ - ((__PIN__) == GPIO_PIN_3) ||\ - ((__PIN__) == GPIO_PIN_4) ||\ - ((__PIN__) == GPIO_PIN_5) ||\ - ((__PIN__) == GPIO_PIN_6) ||\ - ((__PIN__) == GPIO_PIN_7) ||\ - ((__PIN__) == GPIO_PIN_8) ||\ - ((__PIN__) == GPIO_PIN_9) ||\ - ((__PIN__) == GPIO_PIN_10) ||\ - ((__PIN__) == GPIO_PIN_11) ||\ - ((__PIN__) == GPIO_PIN_12) ||\ - ((__PIN__) == GPIO_PIN_13) ||\ - ((__PIN__) == GPIO_PIN_14) ||\ - ((__PIN__) == GPIO_PIN_15)) - -#define IS_GPIO_COMMON_PIN(__RESETMASK__, __SETMASK__) \ - (((uint32_t)(__RESETMASK__) & (uint32_t)(__SETMASK__)) == 0x00u) - -#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ - ((__MODE__) == GPIO_MODE_OUTPUT_OD) ||\ - ((__MODE__) == GPIO_MODE_AF_PP) ||\ - ((__MODE__) == GPIO_MODE_AF_OD) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING) ||\ - ((__MODE__) == GPIO_MODE_IT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_IT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING) ||\ - ((__MODE__) == GPIO_MODE_EVT_FALLING) ||\ - ((__MODE__) == GPIO_MODE_EVT_RISING_FALLING) ||\ - ((__MODE__) == GPIO_MODE_ANALOG)) - -#define IS_GPIO_SPEED(__SPEED__) (((__SPEED__) == GPIO_SPEED_FREQ_LOW) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_HIGH) ||\ - ((__SPEED__) == GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_GPIO_PULL(__PULL__) (((__PULL__) == GPIO_NOPULL) ||\ - ((__PULL__) == GPIO_PULLUP) || \ - ((__PULL__) == GPIO_PULLDOWN)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -#define IS_GPIO_PIN_ATTRIBUTES(__ATTRIBUTES__) (((__ATTRIBUTES__) == GPIO_PIN_SEC) ||\ - ((__ATTRIBUTES__) == GPIO_PIN_NSEC)) - -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/* Include GPIO HAL Extended module */ -#include "stm32u5xx_hal_gpio_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_Exported_Functions GPIO Exported Functions - * @brief GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * @{ - */ - -/* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init); -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); - -/** - * @} - */ - -/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions - * @brief IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); -void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); -void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin); -void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); - -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions - * @{ - */ - -/* IO attributes management functions *****************************************/ -void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, - uint32_t *pPinAttributes); - -/** - * @} - */ - -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_GPIO_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h deleted file mode 100644 index c3710473c..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gpio_ex.h +++ /dev/null @@ -1,342 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_gpio_ex.h - * @author MCD Application Team - * @brief Header file of GPIO HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_GPIO_EX_H -#define STM32U5xx_HAL_GPIO_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup GPIOEx GPIOEx - * @brief GPIO Extended HAL module driver - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup LPGPIO_MapTypeDef GPIO/Ex Exported Types - * @{ - */ -typedef struct -{ - GPIO_TypeDef *GPIO_PORT; - uint32_t Pin_Pos; -} LPGPIO_MapTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants - * @{ - */ - -/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection - * @{ - */ - -/** - * @brief AF 0 selection - */ -#define GPIO_AF0_RTC_50HZ ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */ -#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */ -#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */ -#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */ -#define GPIO_AF0_LPTIM1 ((uint8_t)0x00) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */ -#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */ -#define GPIO_AF0_CRS ((uint8_t)0x00) /* CRS Alternate Function mapping */ -#define GPIO_AF0_SRDSTOP ((uint8_t)0x00) /* SRDSTOP Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */ -#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */ -#define GPIO_AF1_TIM5 ((uint8_t)0x01) /* TIM5 Alternate Function mapping */ -#define GPIO_AF1_TIM8 ((uint8_t)0x01) /* TIM8 Alternate Function mapping */ -#define GPIO_AF1_LPTIM1 ((uint8_t)0x01) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF1_IR ((uint8_t)0x01) /* IR Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define GPIO_AF2_TIM1 ((uint8_t)0x02) /* TIM1 Alternate Function mapping */ -#define GPIO_AF2_TIM2 ((uint8_t)0x02) /* TIM2 Alternate Function mapping */ -#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */ -#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */ -#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */ -#define GPIO_AF2_LPTIM1 ((uint8_t)0x02) /* LPTIM1 Alternate Function mapping */ -#define GPIO_AF2_LPTIM2 ((uint8_t)0x02) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF2_LPTIM3 ((uint8_t)0x02) /* LPTIM3 Alternate Function mapping */ -#if defined(I2C5) -#define GPIO_AF2_I2C5 ((uint8_t)0x02) /* I2C5 Alternate Function mapping */ -#endif /* I2C5 */ -#if defined(I2C6) -#define GPIO_AF2_I2C6 ((uint8_t)0x02) /* I2C6 Alternate Function mapping */ -#endif /* I2C6 */ -#if defined(GFXTIM) -#define GPIO_AF2_GFXTIM ((uint8_t)0x02) /* GFXTIM Alternate Function mapping */ -#endif /* GFXTIM */ - -/** - * @brief AF 3 selection - */ -#define GPIO_AF3_I2C4 ((uint8_t)0x03) /* I2C4 Alternate Function mapping */ -#define GPIO_AF3_OCTOSPI1 ((uint8_t)0x03) /* OCTOSPI1 Alternate Function mapping */ -#define GPIO_AF3_SAI1 ((uint8_t)0x03) /* SAI1 Alternate Function mapping */ -#define GPIO_AF3_SPI2 ((uint8_t)0x03) /* SPI2 Alternate Function mapping */ -#define GPIO_AF3_TIM1 ((uint8_t)0x03) /* TIM1 Alternate Function mapping */ -#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP1 ((uint8_t)0x03) /* TIM8/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM8_COMP2 ((uint8_t)0x03) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP1 ((uint8_t)0x03) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF3_TIM1_COMP2 ((uint8_t)0x03) /* TIM1/COMP2 Break in Alternate Function mapping */ -#if defined(USART2) -#define GPIO_AF3_USART2 ((uint8_t)0x03) /* USART2 Alternate Function mapping */ -#endif /* USART2 */ -#define GPIO_AF3_ADF1 ((uint8_t)0x03) /* ADF1 Alternate Function mapping */ -#if defined(USB_OTG_HS) -#define GPIO_AF3_USB_HS ((uint8_t)0x03) /* USB_HS Alternate Function mapping */ -#endif /* USB_OTG_HS */ - -/** - * @brief AF 4 selection - */ -#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */ -#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */ -#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */ -#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */ -#define GPIO_AF4_PSSI ((uint8_t)0x04) /* PSSI Alternate Function mapping */ -#define GPIO_AF4_DCMI ((uint8_t)0x04) /* DCMI Alternate Function mapping */ -#define GPIO_AF4_LPTIM3 ((uint8_t)0x04) /* LPTIM3 Alternate Function mapping */ -#if defined (I2C5) -#define GPIO_AF4_I2C5 ((uint8_t)0x04) /* I2C5 Alternate Function mapping */ -#endif /* I2C5 */ - -/** - * @brief AF 5 selection - */ -#define GPIO_AF5_I2C4 ((uint8_t)0x05) /* I2C4 Alternate Function mapping */ -#define GPIO_AF5_OCTOSPI1 ((uint8_t)0x05) /* OCTOSPI1 Alternate Function mapping */ -#if defined(OCTOSPI2) -#define GPIO_AF5_OCTOSPI2 ((uint8_t)0x05) /* OCTOSPI2 Alternate Function mapping */ -#endif /* OCTOSPI2 */ -#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ -#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2 Alternate Function mapping */ -#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ -#define GPIO_AF5_DCMI ((uint8_t)0x05) /* DCMI Alternate Function mapping */ -#define GPIO_AF5_MDF1 ((uint8_t)0x05) /* MDF1 Alternate Function mapping */ -#define GPIO_AF5_PSSI ((uint8_t)0x05) /* PSSI Alternate Function mapping */ -#if defined(GFXTIM) -#define GPIO_AF5_GFXTIM ((uint8_t)0x05) /* GFXTIM Alternate Function mapping */ -#endif /* GFXTIM */ - -/** - * @brief AF 6 selection - */ -#define GPIO_AF6_OCTOSPI1 ((uint8_t)0x06) /* OCTOSPI1 Alternate Function mapping */ -#if defined(OCTOSPI2) -#define GPIO_AF6_OCTOSPI2 ((uint8_t)0x06) /* OCTOSPI2 Alternate Function mapping */ -#endif /* OCTOPSI2 */ -#define GPIO_AF6_MDF1 ((uint8_t)0x06) /* MDF1 Alternate Function mapping */ -#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3 Alternate Function mapping */ -#define GPIO_AF6_I2C3 ((uint8_t)0x06) /* I2C3 Alternate Function mapping */ - -/** - * @brief AF 7 selection - */ -#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */ -#if defined(USART2) -#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */ -#endif /* USART2 */ -#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */ -#if defined(USART6) -#define GPIO_AF7_USART6 ((uint8_t)0x07) /* USART6 Alternate Function mapping */ -#endif /* USART6 */ -#if defined(LTDC) -#define GPIO_AF7_LTDC ((uint8_t)0x07) /* LTDC Alternate Function mapping */ -#endif /* LTDC */ - -/** - * @brief AF 8 selection - */ -#define GPIO_AF8_LPUART1 ((uint8_t)0x08) /* LPUART1 Alternate Function mapping */ -#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */ -#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */ -#define GPIO_AF8_SDMMC1 ((uint8_t)0x08) /* SDMMC1 Alternate Function mapping */ -#if defined(SDMMC2) -#define GPIO_AF8_SDMMC2 ((uint8_t)0x08) /* SDMMC2 Alternate Function mapping */ -#endif /* SDMMC2 */ -#if defined(LTDC) -#define GPIO_AF8_LTDC ((uint8_t)0x08) /* LTDC Alternate Function mapping */ -#endif /* LTDC */ -#if defined(HSPI1) -#define GPIO_AF8_HSPI1 ((uint8_t)0x08) /* HSPI1 Alternate Function mapping */ -#endif /* HSPI1 */ - -/** - * @brief AF 9 selection - */ -#define GPIO_AF9_FDCAN1 ((uint8_t)0x09) /* FDCAN1 Alternate Function mapping */ -#define GPIO_AF9_TSC ((uint8_t)0x09) /* TSC Alternate Function mapping */ - -/** - * @brief AF 10 selection - */ -#define GPIO_AF10_DCMI ((uint8_t)0x0A) /* DCMI Alternate Function mapping */ -#define GPIO_AF10_PSSI ((uint8_t)0x0A) /* PSSI Alternate Function mapping */ -#define GPIO_AF10_USB ((uint8_t)0x0A) /* USB Alternate Function mapping */ -#define GPIO_AF10_OCTOSPI1 ((uint8_t)0x0A) /* OCTOSPI1 Alternate Function mapping */ -#if defined(OCTOSPI2) -#define GPIO_AF10_OCTOSPI2 ((uint8_t)0x0A) /* OCTOSPI2 Alternate Function mapping */ -#endif /* OCTOSPI2 */ -#define GPIO_AF10_CRS ((uint8_t)0x0A) /* CRS Alternate Function mapping */ -#if defined(USB_OTG_HS) -#define GPIO_AF10_USB_HS ((uint8_t)0x0A) /* USB_HS Alternate Function mapping */ -#endif /* USB_OTG_HS */ -#if defined(DSI) -#define GPIO_AF10_DSI ((uint8_t)0x0A) /* DSI Alternate Function mapping */ -#endif /* DSI */ -#if defined(GFXTIM) -#define GPIO_AF10_GFXTIM ((uint8_t)0x0A) /* GFXTIM Alternate Function mapping */ -#endif /* GFXTIM */ - -/** - * @brief AF 11 selection - */ -#if defined(UCPD1) -#define GPIO_AF11_UCPD1 ((uint8_t)0x0B) /* UCPD1 Alternate Function mapping */ -#endif /* UCPD1 */ -#if defined(SDMMC2) -#define GPIO_AF11_SDMMC2 ((uint8_t)0x0B) /* SDMMC2 Alternate Function mapping */ -#endif /* SDMMC2 */ -#define GPIO_AF11_LPGPIO1 ((uint8_t)0x0B) /* LPGPIO1 Alternate Function mapping */ -#if defined(FMC_BASE) -#define GPIO_AF11_FMC ((uint8_t)0x0B) /* FMC Alternate Function mapping */ -#endif /* FMC_BASE */ -#if defined(DSI) -#define GPIO_AF11_DSI ((uint8_t)0x0B) /* DSI Alternate Function mapping */ -#endif /* DSI */ -#if defined(GFXTIM) -#define GPIO_AF11_GFXTIM ((uint8_t)0x0B) /* GFXTIM Alternate Function mapping */ -#endif /* GFXTIM */ - -/** - * @brief AF 12 selection - */ -#define GPIO_AF12_COMP1 ((uint8_t)0x0C) /* COMP1 Alternate Function mapping */ -#define GPIO_AF12_COMP2 ((uint8_t)0x0C) /* COMP2 Alternate Function mapping */ -#if defined(FMC_BASE) -#define GPIO_AF12_FMC ((uint8_t)0x0C) /* FMC Alternate Function mapping */ -#endif /* FMC_BASE */ -#define GPIO_AF12_TIM1_COMP1 ((uint8_t)0x0C) /* TIM1/COMP1 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM1_COMP2 ((uint8_t)0x0C) /* TIM1/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_TIM8_COMP2 ((uint8_t)0x0C) /* TIM8/COMP2 Break in Alternate Function mapping */ -#define GPIO_AF12_SDMMC1 ((uint8_t)0x0C) /* SDMMC1 Alternate Function mapping */ -#if defined(SDMMC2) -#define GPIO_AF12_SDMMC2 ((uint8_t)0x0C) /* SDMMC2 Alternate Function mapping */ -#endif /* SDMMC2 */ - -/** - * @brief AF 13 selection - */ -#define GPIO_AF13_SAI1 ((uint8_t)0x0D) /* SAI1 Alternate Function mapping */ -#if defined(SAI2) -#define GPIO_AF13_SAI2 ((uint8_t)0x0D) /* SAI2 Alternate Function mapping */ -#endif /* SAI2 */ -#define GPIO_AF13_LPTIM4 ((uint8_t)0x0D) /* LPTIM4 Alternate Function mapping */ -#define GPIO_AF13_LPTIM2 ((uint8_t)0x0D) /* LPTIM2 Alternate Function mapping */ -#if defined(GFXTIM) -#define GPIO_AF13_GFXTIM ((uint8_t)0x0D) /* GFXTIM Alternate Function mapping */ -#endif /* GFXTIM */ - -/** - * @brief AF 14 selection - */ -#define GPIO_AF14_LPTIM2 ((uint8_t)0x0E) /* LPTIM2 Alternate Function mapping */ -#define GPIO_AF14_LPTIM3 ((uint8_t)0x0E) /* LPTIM3 Alternate Function mapping */ -#define GPIO_AF14_TIM2 ((uint8_t)0x0E) /* TIM2 Alternate Function mapping */ -#define GPIO_AF14_TIM15 ((uint8_t)0x0E) /* TIM15 Alternate Function mapping */ -#define GPIO_AF14_TIM15_COMP1 ((uint8_t)0x0E) /* TIM15/COMP1 Alternate Function mapping */ -#define GPIO_AF14_TIM16 ((uint8_t)0x0E) /* TIM16 Alternate Function mapping */ -#define GPIO_AF14_TIM16_COMP1 ((uint8_t)0x0E) /* TIM16/COMP1 Alternate Function mapping */ -#define GPIO_AF14_TIM17 ((uint8_t)0x0E) /* TIM17 Alternate Function mapping */ -#define GPIO_AF14_TIM17_COMP1 ((uint8_t)0x0E) /* TIM17/COMP1 Alternate Function mapping */ -#if defined(FMC_BASE) -#define GPIO_AF14_FMC ((uint8_t)0x0E) /* FMC Alternate Function mapping */ -#endif /* FMC_BASE */ - -/** - * @brief AF 15 selection - */ -#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */ - -#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0F) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIOEx_Exported_Macros GPIOEx Exported Macros - * @{ - */ - -/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index - * @{ - */ - -/* GPIO_Peripheral_Memory_Mapping Peripheral Memory Mapping */ -#define GPIO_GET_INDEX(__GPIOx__) (((uint32_t )(__GPIOx__) & (~GPIOA_BASE)) >> 10) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_GPIO_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h deleted file mode 100644 index 10749e0a1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_gtzc.h +++ /dev/null @@ -1,675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_gtzc.h - * @author MCD Application Team - * @brief Header file of GTZC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_GTZC_H -#define STM32U5xx_HAL_GTZC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup GTZC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup GTZC_Exported_Types GTZC Exported Types - * @{ - */ - -/*!< Values needed for MPCBB_Attribute_ConfigTypeDef structure sizing */ -#if defined (SRAM5_BASE) -#define GTZC_MPCBB_NB_VCTR_REG_MAX (52U) /* Up to 52 super-blocks */ -#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (2U) /* More than one 32-bit needed */ -#else -#define GTZC_MPCBB_NB_VCTR_REG_MAX (32U) /* Up to 32 super-blocks */ -#define GTZC_MPCBB_NB_LCK_VCTR_REG_MAX (1U) /* One 32-bit needed */ -#endif /* SRAM5_BASE */ - -typedef struct -{ - uint32_t MPCBB_SecConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies secure access mode for - a super-block. Each bit corresponds to a block - inside the super-block. 0 means non-secure, - 1 means secure */ - uint32_t MPCBB_PrivConfig_array[GTZC_MPCBB_NB_VCTR_REG_MAX]; /*!< Each element specifies privilege access mode for - a super-block. Each bit corresponds to a block - inside the super-block. 0 means non-privilege, - 1 means privilege */ - uint32_t MPCBB_LockConfig_array[GTZC_MPCBB_NB_LCK_VCTR_REG_MAX]; /*!< Each bit specifies the lock configuration of - a super-block (32 blocks). 0 means unlocked, - 1 means locked */ -} MPCBB_Attribute_ConfigTypeDef; - -typedef struct -{ - uint32_t SecureRWIllegalMode; /*!< Secure read/write illegal access - field. It can be a value of @ref GTZC_MPCBB_SecureRWIllegalMode */ - uint32_t InvertSecureState; /*!< Default security state field (can be inverted or not). - It can be a value of @ref GTZC_MPCBB_InvertSecureState */ - MPCBB_Attribute_ConfigTypeDef AttributeConfig; /*!< MPCBB attribute configuration sub-structure */ -} MPCBB_ConfigTypeDef; - -typedef struct -{ - uint32_t AreaId; /*!< Area identifier field. It can be a value of @ref - GTZC_MPCWM_AreaId */ - uint32_t Offset; /*!< Offset of the watermark area, starting from the selected - memory base address. It must aligned on 128KB for FMC - and OCTOSPI memories, and on 32-byte for BKPSRAM */ - uint32_t Length; /*!< Length of the watermark area, starting from the selected - Offset. It must aligned on 128KB for FMC and OCTOSPI - memories, and on 32-byte for BKPSRAM */ - uint32_t Attribute; /*!< Attributes of the watermark area. It can be a value - of @ref GTZC_MPCWM_Attribute */ - uint32_t Lock; /*!< Lock of the watermark area. It can be a value - of @ref GTZC_MPCWM_Lock */ - uint32_t AreaStatus; /*!< Status of the watermark area. It can be set to - ENABLE or DISABLE */ -} MPCWM_ConfigTypeDef; - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ - -/** @defgroup GTZC_Private_Constants GTZC Private Constants - * @{ - */ - -/** @defgroup GTZC_Private_PeriphId_composition GTZC Peripheral identifier composition - * @{ - */ - -/* composition definition for Peripheral identifier parameter (PeriphId) used in - * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() - * functions and also in all HAL_GTZC_TZIC relative functions. - * Bitmap Definition - * bits[31:28] Field "register". Define the register index a peripheral belongs to. - * Each bit is dedicated to a single register. - * bit[5] Field "all peripherals". If this bit is set then the PeriphId targets - * all peripherals within all registers. - * bits[4:0] Field "bit position". Define the bit position within the - * register dedicated to the peripheral, value from 0 to 31. - */ -#define GTZC_PERIPH_REG_SHIFT (28U) -#define GTZC_PERIPH_REG (0xF0000000U) -#define GTZC1_PERIPH_REG1 (0x00000000U) -#define GTZC1_PERIPH_REG2 (0x10000000U) -#define GTZC1_PERIPH_REG3 (0x20000000U) -#define GTZC1_PERIPH_REG4 (0x30000000U) -#define GTZC2_PERIPH_REG1 (0x40000000U) -#define GTZC2_PERIPH_REG2 (0x50000000U) -#define GTZC_PERIPH_BIT_POSITION (0x0000001FU) - -/** - * @} - */ - -/** @defgroup GTZC_Private_Attributes_Msk GTZC Attributes Masks - * @{ - */ -#define GTZC_ATTR_SEC_MASK 0x100U -#define GTZC_ATTR_PRIV_MASK 0x200U - -/** - * @} - */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup GTZC_Exported_Constants GTZC Exported Constants - * @{ - */ - -/** @defgroup GTZC_MPCBB_SecureRWIllegalMode GTZC MPCBB SRWILADIS values - * @{ - */ - -#define GTZC_MPCBB_SRWILADIS_ENABLE (0U) -#define GTZC_MPCBB_SRWILADIS_DISABLE (GTZC_MPCBB_CR_SRWILADIS_Msk) - -/** - * @} - */ - -/** @defgroup GTZC_MPCBB_InvertSecureState GTZC MPCBB INVSECSTATE values - * @{ - */ - -#define GTZC_MPCBB_INVSECSTATE_NOT_INVERTED (0U) -#define GTZC_MPCBB_INVSECSTATE_INVERTED (GTZC_MPCBB_CR_INVSECSTATE_Msk) - -/** - * @} - */ - -/** @defgroup GTZC_MPCWM_AreaId GTZC MPCWM area identifier values - * @{ - */ - -#define GTZC_TZSC_MPCWM_ID1 (0U) -#define GTZC_TZSC_MPCWM_ID2 (1U) - -/** - * @} - */ - -/** @defgroup GTZC_TZSC_TZIC_PeriphId GTZC TZSC and TZIC Peripheral identifier values - * @{ - */ -/* GTZC1 */ -#define GTZC_PERIPH_TIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM2_Pos) -#define GTZC_PERIPH_TIM3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM3_Pos) -#define GTZC_PERIPH_TIM4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM4_Pos) -#define GTZC_PERIPH_TIM5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM5_Pos) -#define GTZC_PERIPH_TIM6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM6_Pos) -#define GTZC_PERIPH_TIM7 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_TIM7_Pos) -#define GTZC_PERIPH_WWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_WWDG_Pos) -#define GTZC_PERIPH_IWDG (GTZC1_PERIPH_REG1 | GTZC_CFGR1_IWDG_Pos) -#define GTZC_PERIPH_SPI2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_SPI2_Pos) -#if defined (USART2) -#define GTZC_PERIPH_USART2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART2_Pos) -#endif /* USART2 */ -#define GTZC_PERIPH_USART3 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART3_Pos) -#define GTZC_PERIPH_UART4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART4_Pos) -#define GTZC_PERIPH_UART5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UART5_Pos) -#define GTZC_PERIPH_I2C1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C1_Pos) -#define GTZC_PERIPH_I2C2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C2_Pos) -#define GTZC_PERIPH_CRS (GTZC1_PERIPH_REG1 | GTZC_CFGR1_CRS_Pos) -#define GTZC_PERIPH_I2C4 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C4_Pos) -#define GTZC_PERIPH_LPTIM2 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_LPTIM2_Pos) -#define GTZC_PERIPH_FDCAN1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_FDCAN1_Pos) -#if defined (UCPD1) -#define GTZC_PERIPH_UCPD1 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_UCPD1_Pos) -#endif /* UCPD1 */ -#if defined (USART6) -#define GTZC_PERIPH_USART6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_USART6_Pos) -#endif /* USART6 */ -#if defined (I2C5) -#define GTZC_PERIPH_I2C5 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C5_Pos) -#endif /* I2C5 */ -#if defined (I2C6) -#define GTZC_PERIPH_I2C6 (GTZC1_PERIPH_REG1 | GTZC_CFGR1_I2C6_Pos) -#endif /* I2C6 */ -#define GTZC_PERIPH_TIM1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM1_Pos) -#define GTZC_PERIPH_SPI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SPI1_Pos) -#define GTZC_PERIPH_TIM8 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM8_Pos) -#define GTZC_PERIPH_USART1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_USART1_Pos) -#define GTZC_PERIPH_TIM15 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM15_Pos) -#define GTZC_PERIPH_TIM16 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM16_Pos) -#define GTZC_PERIPH_TIM17 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_TIM17_Pos) -#define GTZC_PERIPH_SAI1 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI1_Pos) -#if defined (SAI2) -#define GTZC_PERIPH_SAI2 (GTZC1_PERIPH_REG2 | GTZC_CFGR2_SAI2_Pos) -#endif /* SAI2 */ -#if defined (LTDC) || defined (USB_DRD_FS) -#define GTZC_PERIPH_LTDCUSB (GTZC1_PERIPH_REG2 | GTZC_CFGR2_LTDCUSB_Pos) -#endif /* LTDC || USB_DRD_FS */ -#if defined (DSI) -#define GTZC_PERIPH_DSI (GTZC1_PERIPH_REG2 | GTZC_CFGR2_DSI_Pos) -#endif /* DSI */ -#if defined (GFXTIM) -#define GTZC_PERIPH_GFXTIM (GTZC1_PERIPH_REG2 | GTZC_CFGR2_GFXTIM_Pos) -#endif /* GFXTIM */ -#define GTZC_PERIPH_MDF1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_MDF1_Pos) -#define GTZC_PERIPH_CORDIC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CORDIC_Pos) -#define GTZC_PERIPH_FMAC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FMAC_Pos) -#define GTZC_PERIPH_CRC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_CRC_Pos) -#define GTZC_PERIPH_TSC (GTZC1_PERIPH_REG3 | GTZC_CFGR3_TSC_Pos) -#if defined (DMA2D) -#define GTZC_PERIPH_DMA2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DMA2D_Pos) -#endif /* DMA2D */ -#define GTZC_PERIPH_ICACHE_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ICACHE_REG_Pos) -#define GTZC_PERIPH_DCACHE1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE1_REG_Pos) -#define GTZC_PERIPH_ADC12 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_ADC12_Pos) -#define GTZC_PERIPH_DCMI_PSSI (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCMI_Pos) -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define GTZC_PERIPH_OTG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OTG_Pos) -#endif /* (USB_OTG_FS) || (USB_OTG_HS) */ -#if defined (AES) -#define GTZC_PERIPH_AES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_AES_Pos) -#endif /* AES */ -#define GTZC_PERIPH_HASH (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HASH_Pos) -#define GTZC_PERIPH_RNG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RNG_Pos) -#if defined (PKA) -#define GTZC_PERIPH_PKA (GTZC1_PERIPH_REG3 | GTZC_CFGR3_PKA_Pos) -#endif /* PKA */ -#if defined (SAES) -#define GTZC_PERIPH_SAES (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SAES_Pos) -#endif /* SAES */ -#if defined (OCTOSPIM) -#define GTZC_PERIPH_OCTOSPIM (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPIM_Pos) -#endif /* OCTOSPIM */ -#define GTZC_PERIPH_SDMMC1 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC1_Pos) -#if defined (SDMMC2) -#define GTZC_PERIPH_SDMMC2 (GTZC1_PERIPH_REG3 | GTZC_CFGR3_SDMMC2_Pos) -#endif /* SDMMC2 */ -#if defined (FMC_BASE) -#define GTZC_PERIPH_FSMC_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_FSMC_REG_Pos) -#endif /* FMC_BASE */ -#define GTZC_PERIPH_OCTOSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI1_REG_Pos) -#if defined (OCTOSPI2) -#define GTZC_PERIPH_OCTOSPI2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_OCTOSPI2_REG_Pos) -#endif /* OCTOSPI2 */ -#define GTZC_PERIPH_RAMCFG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_RAMCFG_Pos) -#if defined (GPU2D) -#define GTZC_PERIPH_GPU2D (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GPU2D_Pos) -#endif /* GPU2D */ -#if defined (GFXMMU) -#define GTZC_PERIPH_GFXMMU (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_Pos) -#define GTZC_PERIPH_GFXMMU_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_GFXMMU_REG_Pos) -#endif /* GFXMMU */ -#if defined (HSPI1) -#define GTZC_PERIPH_HSPI1_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_HSPI1_REG_Pos) -#endif /* HSPI1 */ -#if defined (DCACHE2) -#define GTZC_PERIPH_DCACHE2_REG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_DCACHE2_REG_Pos) -#endif /* DCACHE2 */ -#if defined (JPEG) -#define GTZC_PERIPH_JPEG (GTZC1_PERIPH_REG3 | GTZC_CFGR3_JPEG_Pos) -#endif /* JPEG */ -#define GTZC_PERIPH_GPDMA1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_GPDMA1_Pos) -#define GTZC_PERIPH_FLASH_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_REG_Pos) -#define GTZC_PERIPH_FLASH (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FLASH_Pos) -#if defined (OTFDEC2) -#define GTZC_PERIPH_OTFDEC2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC2_Pos) -#endif /* OTFDEC2 */ -#if defined (OTFDEC1) -#define GTZC_PERIPH_OTFDEC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OTFDEC1_Pos) -#endif /* OTFDEC1 */ -#define GTZC_PERIPH_TZSC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZSC1_Pos) -#define GTZC_PERIPH_TZIC1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_TZIC1_Pos) -#define GTZC_PERIPH_OCTOSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI1_MEM_Pos) -#if defined (FMC_BASE) -#define GTZC_PERIPH_FSMC_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_FSMC_MEM_Pos) -#endif /* FMC_BASE */ -#define GTZC_PERIPH_BKPSRAM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_BKPSRAM_Pos) -#if defined (OCTOSPI2) -#define GTZC_PERIPH_OCTOSPI2_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_OCTOSPI2_MEM_Pos) -#endif /* OCTOSPI2 */ -#if defined (HSPI1) -#define GTZC_PERIPH_HSPI1_MEM (GTZC1_PERIPH_REG4 | GTZC_CFGR4_HSPI1_MEM_Pos) -#endif /* HSPI1 */ -#if defined (SRAM6_BASE) -#define GTZC_PERIPH_SRAM6 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM6_Pos) -#define GTZC_PERIPH_MPCBB6_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB6_REG_Pos) -#endif /* SRAM6_BASE */ -#define GTZC_PERIPH_SRAM1 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM1_Pos) -#define GTZC_PERIPH_MPCBB1_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB1_REG_Pos) -#define GTZC_PERIPH_SRAM2 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM2_Pos) -#define GTZC_PERIPH_MPCBB2_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB2_REG_Pos) -#if defined (SRAM3_BASE) -#define GTZC_PERIPH_SRAM3 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM3_Pos) -#endif /* SRAM3_BASE */ -#define GTZC_PERIPH_MPCBB3_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB3_REG_Pos) -#if defined (SRAM5_BASE) -#define GTZC_PERIPH_SRAM5 (GTZC1_PERIPH_REG4 | GTZC_CFGR4_SRAM5_Pos) -#define GTZC_PERIPH_MPCBB5_REG (GTZC1_PERIPH_REG4 | GTZC_CFGR4_MPCBB5_REG_Pos) -#endif /* SRAM5_BASE */ - -/* GTZC2 */ -#define GTZC_PERIPH_SPI3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_SPI3_Pos) -#define GTZC_PERIPH_LPUART1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPUART1_Pos) -#define GTZC_PERIPH_I2C3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_I2C3_Pos) -#define GTZC_PERIPH_LPTIM1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM1_Pos) -#define GTZC_PERIPH_LPTIM3 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM3_Pos) -#define GTZC_PERIPH_LPTIM4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_LPTIM4_Pos) -#define GTZC_PERIPH_OPAMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_OPAMP_Pos) -#define GTZC_PERIPH_COMP (GTZC2_PERIPH_REG1 | GTZC_CFGR1_COMP_Pos) -#define GTZC_PERIPH_ADC4 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADC4_Pos) -#define GTZC_PERIPH_VREFBUF (GTZC2_PERIPH_REG1 | GTZC_CFGR1_VREFBUF_Pos) -#define GTZC_PERIPH_DAC1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_DAC1_Pos) -#define GTZC_PERIPH_ADF1 (GTZC2_PERIPH_REG1 | GTZC_CFGR1_ADF1_Pos) -#define GTZC_PERIPH_SYSCFG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SYSCFG_Pos) -#define GTZC_PERIPH_RTC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RTC_Pos) -#define GTZC_PERIPH_TAMP (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TAMP_Pos) -#define GTZC_PERIPH_PWR (GTZC2_PERIPH_REG2 | GTZC_CFGR2_PWR_Pos) -#define GTZC_PERIPH_RCC (GTZC2_PERIPH_REG2 | GTZC_CFGR2_RCC_Pos) -#define GTZC_PERIPH_LPDMA1 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_LPDMA1_Pos) -#define GTZC_PERIPH_EXTI (GTZC2_PERIPH_REG2 | GTZC_CFGR2_EXTI_Pos) -#define GTZC_PERIPH_TZSC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZSC2_Pos) -#define GTZC_PERIPH_TZIC2 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_TZIC2_Pos) -#define GTZC_PERIPH_SRAM4 (GTZC2_PERIPH_REG2 | GTZC_CFGR2_SRAM4_Pos) -#define GTZC_PERIPH_MPCBB4_REG (GTZC2_PERIPH_REG2 | GTZC_CFGR2_MPCBB4_REG_Pos) - -#define GTZC_PERIPH_ALL (0x00000020U) - -/* Note that two maximum values are also defined here: - * - max number of securable AHB/APB peripherals or masters - * (used in TZSC sub-block) - * - max number of securable and TrustZone-aware AHB/APB peripherals or masters - * (used in TZIC sub-block) - */ -#define GTZC_TZSC_PERIPH_NUMBER (HAL_GTZC_TZSC_GET_ARRAY_INDEX(GTZC_PERIPH_ADF1 + 1U)) -#define GTZC_TZIC_PERIPH_NUMBER (HAL_GTZC_TZIC_GET_ARRAY_INDEX(GTZC_PERIPH_MPCBB4_REG + 1U)) - -/** - * @} - */ - -/** @defgroup GTZC_TZSC_PeriphAttributes GTZC TZSC peripheral attribute values - * @{ - */ - -/* user-oriented definitions for attribute parameter (PeriphAttributes) used in - * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() - * functions - */ -#define GTZC_TZSC_PERIPH_SEC (GTZC_ATTR_SEC_MASK | 0x00000001U) /*!< Secure attribute */ -#define GTZC_TZSC_PERIPH_NSEC (GTZC_ATTR_SEC_MASK | 0x00000000U) /*!< Non-secure attribute */ -#define GTZC_TZSC_PERIPH_PRIV (GTZC_ATTR_PRIV_MASK | 0x00000002U) /*!< Privilege attribute */ -#define GTZC_TZSC_PERIPH_NPRIV (GTZC_ATTR_PRIV_MASK | 0x00000000U) /*!< Non-privilege attribute */ - -/** - * @} - */ - -/** @defgroup GTZC_TZSC_Lock GTZC TZSC lock values - * @{ - */ - -/* user-oriented definitions for HAL_GTZC_TZSC_GetLock() returned value */ -#define GTZC_TZSC_LOCK_OFF (0U) -#define GTZC_TZSC_LOCK_ON GTZC_TZSC_CR_LCK_Msk - -/** - * @} - */ - -/** @defgroup GTZC_MPCWM_Group GTZC MPCWM values - * @{ - */ - -/* user-oriented definitions for TZSC_MPCWM */ -#define GTZC_TZSC_MPCWM_GRANULARITY_1 0x00020000U /* OCTOSPI & FMC granularity: 128 kbytes */ -#define GTZC_TZSC_MPCWM_GRANULARITY_2 0x00000020U /* BKPSRAM granularity: 32 bytes */ - -/** - * @} - */ - -/** @defgroup GTZC_MPCWM_Lock GTZC MPCWM Lock values - * @{ - */ - -/* user-oriented definitions for TZSC_MPCWM */ -#define GTZC_TZSC_MPCWM_LOCK_OFF (0U) -#define GTZC_TZSC_MPCWM_LOCK_ON GTZC_TZSC_MPCWM_CFGR_SRLOCK_Msk - -/** - * @} - */ - -/** @defgroup GTZC_MPCWM_Attribute GTZC MPCWM Attribute values - * @{ - */ - -/* user-oriented definitions for TZSC_MPCWM */ -#define GTZC_TZSC_MPCWM_REGION_NSEC (0U) -#define GTZC_TZSC_MPCWM_REGION_SEC (1U) -#define GTZC_TZSC_MPCWM_REGION_NPRIV (0U) -#define GTZC_TZSC_MPCWM_REGION_PRIV (2U) - -/** - * @} - */ - -/** @defgroup GTZC_MPCBB_Group GTZC MPCBB values - * @{ - */ - -/* user-oriented definitions for MPCBB */ -#define GTZC_MPCBB_BLOCK_SIZE 0x200U /* 512 Bytes */ -#define GTZC_MPCBB_SUPERBLOCK_SIZE (GTZC_MPCBB_BLOCK_SIZE * 32U) /* 16 KBytes */ -#define GTZC_MPCBB_SUPERBLOCK_UNLOCKED (0U) -#define GTZC_MPCBB_SUPERBLOCK_LOCKED (1U) - -#define GTZC_MPCBB_BLOCK_NSEC (GTZC_ATTR_SEC_MASK | 0U) -#define GTZC_MPCBB_BLOCK_SEC (GTZC_ATTR_SEC_MASK | 1U) -#define GTZC_MPCBB_BLOCK_NPRIV (GTZC_ATTR_PRIV_MASK | 0U) -#define GTZC_MPCBB_BLOCK_PRIV (GTZC_ATTR_PRIV_MASK | 2U) - -/* user-oriented definitions for HAL_GTZC_MPCBB_GetLock() returned value */ -#define GTZC_MPCBB_LOCK_OFF (0U) -#define GTZC_MPCBB_LOCK_ON (1U) - -/** - * @} - */ - -/** @defgroup GTZC_TZIC_Flag GTZC TZIC flag values - * @{ - */ - -/* user-oriented definitions for HAL_GTZC_TZIC_GetFlag() flag parameter */ -#define GTZC_TZIC_NO_ILA_EVENT (0U) -#define GTZC_TZIC_ILA_EVENT_PENDING (1U) - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup GTZC_Private_Macros GTZC Private Macros - * @{ - */ - -/* retrieve information to access register for a specific PeriphId */ -#define GTZC_GET_REG_INDEX(periph_id)\ - (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) -#define GTZC_GET_REG_INDEX_IN_INSTANCE(periph_id)\ - ((((periph_id) & GTZC_PERIPH_REG) <= GTZC1_PERIPH_REG4) ? \ - (((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) : \ - ((((periph_id) & GTZC_PERIPH_REG) >> GTZC_PERIPH_REG_SHIFT) - 4U)) -#define GTZC_GET_PERIPH_POS(periph_id) ((periph_id) & GTZC_PERIPH_BIT_POSITION) - -#define IS_GTZC_BASE_ADDRESS(mem, address)\ - ( ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) || \ - ( (uint32_t)(address) == (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) ) - -#define GTZC_MEM_SIZE(mem)\ - ( mem ## _SIZE ) - -#define GTZC_BASE_ADDRESS_S(mem)\ - ( mem ## _BASE_S ) - -#define GTZC_BASE_ADDRESS_NS(mem)\ - ( mem ## _BASE_NS ) - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup GTZC_Exported_Macros GTZC Exported Macros - * @{ - */ - -/* user-oriented macro to get array index of a specific PeriphId - * in case of GTZC_PERIPH_ALL usage in the two following functions: - * HAL_GTZC_TZSC_ConfigPeriphAttributes() and HAL_GTZC_TZSC_GetConfigPeriphAttributes() - */ -#define HAL_GTZC_TZSC_GET_ARRAY_INDEX(periph_id) \ - (uint32_t)((HAL_GTZC_TZSC_GET_INSTANCE(periph_id) == GTZC_TZSC1)? \ - ((GTZC_GET_REG_INDEX(periph_id) * 32U) + GTZC_GET_PERIPH_POS(periph_id)) : \ - (((GTZC_GET_REG_INDEX(periph_id) - 1U) * 32U) + GTZC_GET_PERIPH_POS(periph_id) )) - -#define HAL_GTZC_TZIC_GET_ARRAY_INDEX(periph_id) \ - ( (GTZC_GET_REG_INDEX((periph_id)) * 32U) + GTZC_GET_PERIPH_POS((periph_id)) ) - -/* user-oriented macro to get TZSC instance of a specific PeriphId */ -#define HAL_GTZC_TZSC_GET_INSTANCE(periph_id) \ - ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4 >> GTZC_PERIPH_REG_SHIFT))? \ - GTZC_TZSC1 : GTZC_TZSC2) - -/* user-oriented macro to get TZIC instance of a specific PeriphId */ -#define HAL_GTZC_TZIC_GET_INSTANCE(periph_id) \ - ((GTZC_GET_REG_INDEX(periph_id) <= (GTZC1_PERIPH_REG4>> GTZC_PERIPH_REG_SHIFT))? \ - GTZC_TZIC1 : GTZC_TZIC2) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup GTZC_Exported_Functions - * @{ - */ - -/** @addtogroup GTZC_Exported_Functions_Group1 - * @brief TZSC Initialization and Configuration functions - * @{ - */ - -HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, - uint32_t PeriphAttributes); -HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, - uint32_t *PeriphAttributes); - -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @addtogroup GTZC_Exported_Functions_Group2 - * @brief MPCWM Initialization and Configuration functions - * @{ - */ - -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, - const MPCWM_ConfigTypeDef *pMPCWM_Desc); -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc); -/** - * @} - */ - -/** @addtogroup GTZC_Exported_Functions_Group3 - * @brief TZSC and TZSC-MPCWM Lock functions - * @{ - */ - -void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance); -uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance); - -/** - * @} - */ -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/** @addtogroup GTZC_Exported_Functions_Group4 - * @brief MPCBB Initialization and Configuration functions - * @{ - */ - -HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, - const MPCBB_ConfigTypeDef *pMPCBB_desc); -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, - MPCBB_ConfigTypeDef *pMPCBB_desc); -HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, - uint32_t NbBlocks, - const uint32_t *pMemAttributes); -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, - uint32_t NbBlocks, - uint32_t *pMemAttributes); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, - uint32_t NbSuperBlocks, - const uint32_t *pLockAttributes); -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - uint32_t NbSuperBlocks, - uint32_t *pLockAttributes); -HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress); -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, - uint32_t *pLockState); -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @addtogroup GTZC_Exported_Functions_Group5 - * @brief TZIC functions - * @{ - */ - -HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId); -HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId); -HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag); -HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId); - -/** - * @} - */ - -/** @addtogroup GTZC_Exported_Functions_Group6 - * @brief IRQ related Functions - * @{ - */ - -void HAL_GTZC_IRQHandler(void); -void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); - -/** - * @} - */ - -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_GTZC_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h deleted file mode 100644 index d37fb0e2a..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c.h +++ /dev/null @@ -1,846 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_i2c.h - * @author MCD Application Team - * @brief Header file of I2C HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_I2C_H -#define STM32U5xx_HAL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition - * @brief I2C Configuration Structure definition - * @{ - */ -typedef struct -{ - uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value. - This parameter calculated by referring to I2C initialization section - in Reference manual */ - - uint32_t OwnAddress1; /*!< Specifies the first device own address. - This parameter can be a 7-bit or 10-bit address. */ - - uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected. - This parameter can be a value of @ref I2C_ADDRESSING_MODE */ - - uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. - This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */ - - uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected - This parameter can be a 7-bit address. */ - - uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing - mode is selected. - This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */ - - uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. - This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */ - - uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. - This parameter can be a value of @ref I2C_NOSTRETCH_MODE */ - -} I2C_InitTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_state_structure_definition HAL state structure definition - * @brief HAL State structure definition - * @note HAL I2C State value coding follow below described bitmap :\n - * b7-b6 Error information\n - * 00 : No Error\n - * 01 : Abort (Abort user request on going)\n - * 10 : Timeout\n - * 11 : Error\n - * b5 Peripheral initialization status\n - * 0 : Reset (peripheral not initialized)\n - * 1 : Init done (peripheral initialized and ready to use. HAL I2C Init function called)\n - * b4 (not used)\n - * x : Should be set to 0\n - * b3\n - * 0 : Ready or Busy (No Listen mode ongoing)\n - * 1 : Listen (peripheral in Address Listen Mode)\n - * b2 Intrinsic process state\n - * 0 : Ready\n - * 1 : Busy (peripheral busy with some configuration or internal operations)\n - * b1 Rx state\n - * 0 : Ready (no Rx operation ongoing)\n - * 1 : Busy (Rx operation ongoing)\n - * b0 Tx state\n - * 0 : Ready (no Tx operation ongoing)\n - * 1 : Busy (Tx operation ongoing) - * @{ - */ -typedef enum -{ - HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */ - HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */ - HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */ - HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */ - HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ - HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */ - HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission - process is ongoing */ - HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception - process is ongoing */ - HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - -} HAL_I2C_StateTypeDef; - -/** - * @} - */ - -/** @defgroup HAL_mode_structure_definition HAL mode structure definition - * @brief HAL Mode structure definition - * @note HAL I2C Mode value coding follow below described bitmap :\n - * b7 (not used)\n - * x : Should be set to 0\n - * b6\n - * 0 : None\n - * 1 : Memory (HAL I2C communication is in Memory Mode)\n - * b5\n - * 0 : None\n - * 1 : Slave (HAL I2C communication is in Slave Mode)\n - * b4\n - * 0 : None\n - * 1 : Master (HAL I2C communication is in Master Mode)\n - * b3-b2-b1-b0 (not used)\n - * xxxx : Should be set to 0000 - * @{ - */ -typedef enum -{ - HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */ - HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */ - HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */ - HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */ - -} HAL_I2C_ModeTypeDef; - -/** - * @} - */ - -/** @defgroup I2C_Error_Code_definition I2C Error Code definition - * @brief I2C Error Code definition - * @{ - */ -#define HAL_I2C_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_I2C_ERROR_BERR (0x00000001U) /*!< BERR error */ -#define HAL_I2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */ -#define HAL_I2C_ERROR_AF (0x00000004U) /*!< ACKF error */ -#define HAL_I2C_ERROR_OVR (0x00000008U) /*!< OVR error */ -#define HAL_I2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#define HAL_I2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */ -#define HAL_I2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */ -#define HAL_I2C_ERROR_DMA_PARAM (0x00000080U) /*!< DMA Parameter Error */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define HAL_I2C_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -#define HAL_I2C_ERROR_INVALID_PARAM (0x00000200U) /*!< Invalid Parameters error */ -/** - * @} - */ - -/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition - * @brief I2C handle Structure definition - * @{ - */ -typedef struct __I2C_HandleTypeDef -{ - I2C_TypeDef *Instance; /*!< I2C registers base address */ - - I2C_InitTypeDef Init; /*!< I2C communication parameters */ - - uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */ - - uint16_t XferSize; /*!< I2C transfer size */ - - __IO uint16_t XferCount; /*!< I2C transfer counter */ - - __IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can - be a value of @ref I2C_XFEROPTIONS */ - - __IO uint32_t PreviousState; /*!< I2C communication Previous state */ - - HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); - /*!< I2C transfer IRQ handler function pointer */ - -#if defined(HAL_DMA_MODULE_ENABLED) - DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */ - -#endif /*HAL_DMA_MODULE_ENABLED*/ - - HAL_LockTypeDef Lock; /*!< I2C locking object */ - - __IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */ - - __IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */ - - __IO uint32_t ErrorCode; /*!< I2C Error code */ - - __IO uint32_t AddrEventCount; /*!< I2C Address Event counter */ - - __IO uint32_t Devaddress; /*!< I2C Target device address */ - - __IO uint32_t Memaddress; /*!< I2C Target memory address */ - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - void (* MasterTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Master Tx Transfer completed callback */ - void (* MasterRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Master Rx Transfer completed callback */ - void (* SlaveTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Slave Tx Transfer completed callback */ - void (* SlaveRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Slave Rx Transfer completed callback */ - void (* ListenCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Listen Complete callback */ - void (* MemTxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Memory Tx Transfer completed callback */ - void (* MemRxCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Memory Rx Transfer completed callback */ - void (* ErrorCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Error callback */ - void (* AbortCpltCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Abort callback */ - - void (* AddrCallback)(struct __I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); - /*!< I2C Slave Address Match callback */ - - void (* MspInitCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Msp Init callback */ - void (* MspDeInitCallback)(struct __I2C_HandleTypeDef *hi2c); - /*!< I2C Msp DeInit callback */ - -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -} I2C_HandleTypeDef; - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -/** - * @brief HAL I2C Callback ID enumeration definition - */ -typedef enum -{ - HAL_I2C_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< I2C Master Tx Transfer completed callback ID */ - HAL_I2C_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< I2C Master Rx Transfer completed callback ID */ - HAL_I2C_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< I2C Slave Tx Transfer completed callback ID */ - HAL_I2C_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< I2C Slave Rx Transfer completed callback ID */ - HAL_I2C_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< I2C Listen Complete callback ID */ - HAL_I2C_MEM_TX_COMPLETE_CB_ID = 0x05U, /*!< I2C Memory Tx Transfer callback ID */ - HAL_I2C_MEM_RX_COMPLETE_CB_ID = 0x06U, /*!< I2C Memory Rx Transfer completed callback ID */ - HAL_I2C_ERROR_CB_ID = 0x07U, /*!< I2C Error callback ID */ - HAL_I2C_ABORT_CB_ID = 0x08U, /*!< I2C Abort callback ID */ - - HAL_I2C_MSPINIT_CB_ID = 0x09U, /*!< I2C Msp Init callback ID */ - HAL_I2C_MSPDEINIT_CB_ID = 0x0AU /*!< I2C Msp DeInit callback ID */ - -} HAL_I2C_CallbackIDTypeDef; - -/** - * @brief HAL I2C Callback pointer definition - */ -typedef void (*pI2C_CallbackTypeDef)(I2C_HandleTypeDef *hi2c); -/*!< pointer to an I2C callback function */ -typedef void (*pI2C_AddrCallbackTypeDef)(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, - uint16_t AddrMatchCode); -/*!< pointer to an I2C Address Match callback function */ - -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** - * @} - */ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options - * @{ - */ -#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE) -#define I2C_FIRST_AND_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE)) -#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE) -#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE) - -/* List of XferOptions in usage of : - * 1- Restart condition in all use cases (direction change or not) - */ -#define I2C_OTHER_FRAME (0x000000AAU) -#define I2C_OTHER_AND_LAST_FRAME (0x0000AA00U) -/** - * @} - */ - -/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode - * @{ - */ -#define I2C_ADDRESSINGMODE_7BIT (0x00000001U) -#define I2C_ADDRESSINGMODE_10BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode - * @{ - */ -#define I2C_DUALADDRESS_DISABLE (0x00000000U) -#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN -/** - * @} - */ - -/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks - * @{ - */ -#define I2C_OA2_NOMASK ((uint8_t)0x00U) -#define I2C_OA2_MASK01 ((uint8_t)0x01U) -#define I2C_OA2_MASK02 ((uint8_t)0x02U) -#define I2C_OA2_MASK03 ((uint8_t)0x03U) -#define I2C_OA2_MASK04 ((uint8_t)0x04U) -#define I2C_OA2_MASK05 ((uint8_t)0x05U) -#define I2C_OA2_MASK06 ((uint8_t)0x06U) -#define I2C_OA2_MASK07 ((uint8_t)0x07U) -/** - * @} - */ - -/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode - * @{ - */ -#define I2C_GENERALCALL_DISABLE (0x00000000U) -#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN -/** - * @} - */ - -/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode - * @{ - */ -#define I2C_NOSTRETCH_DISABLE (0x00000000U) -#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH -/** - * @} - */ - -/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size - * @{ - */ -#define I2C_MEMADD_SIZE_8BIT (0x00000001U) -#define I2C_MEMADD_SIZE_16BIT (0x00000002U) -/** - * @} - */ - -/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View - * @{ - */ -#define I2C_DIRECTION_TRANSMIT (0x00000000U) -#define I2C_DIRECTION_RECEIVE (0x00000001U) -/** - * @} - */ - -/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode - * @{ - */ -#define I2C_RELOAD_MODE I2C_CR2_RELOAD -#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND -#define I2C_SOFTEND_MODE (0x00000000U) -/** - * @} - */ - -/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode - * @{ - */ -#define I2C_NO_STARTSTOP (0x00000000U) -#define I2C_GENERATE_NO_START_READ (uint32_t)(0x80000000U | I2C_CR2_RD_WRN) -#define I2C_GENERATE_NO_START_WRITE (uint32_t)(0x80000000U) -#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/** - * @} - */ - -/** @defgroup I2C_Interrupt_configuration_definition I2C Interrupt configuration definition - * @brief I2C Interrupt definition - * Elements values convention: 0xXXXXXXXX - * - XXXXXXXX : Interrupt control mask - * @{ - */ -#define I2C_IT_ERRI I2C_CR1_ERRIE -#define I2C_IT_TCI I2C_CR1_TCIE -#define I2C_IT_STOPI I2C_CR1_STOPIE -#define I2C_IT_NACKI I2C_CR1_NACKIE -#define I2C_IT_ADDRI I2C_CR1_ADDRIE -#define I2C_IT_RXI I2C_CR1_RXIE -#define I2C_IT_TXI I2C_CR1_TXIE -/** - * @} - */ - -/** @defgroup I2C_Flag_definition I2C Flag definition - * @{ - */ -#define I2C_FLAG_TXE I2C_ISR_TXE -#define I2C_FLAG_TXIS I2C_ISR_TXIS -#define I2C_FLAG_RXNE I2C_ISR_RXNE -#define I2C_FLAG_ADDR I2C_ISR_ADDR -#define I2C_FLAG_AF I2C_ISR_NACKF -#define I2C_FLAG_STOPF I2C_ISR_STOPF -#define I2C_FLAG_TC I2C_ISR_TC -#define I2C_FLAG_TCR I2C_ISR_TCR -#define I2C_FLAG_BERR I2C_ISR_BERR -#define I2C_FLAG_ARLO I2C_ISR_ARLO -#define I2C_FLAG_OVR I2C_ISR_OVR -#define I2C_FLAG_PECERR I2C_ISR_PECERR -#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT -#define I2C_FLAG_ALERT I2C_ISR_ALERT -#define I2C_FLAG_BUSY I2C_ISR_BUSY -#define I2C_FLAG_DIR I2C_ISR_DIR -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @brief Reset I2C handle state. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_I2C_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET) -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - -/** @brief Enable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) - -/** @brief Disable the specified I2C interrupt. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval None - */ -#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified I2C interrupt source is enabled or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __INTERRUPT__ specifies the I2C interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref I2C_IT_ERRI Errors interrupt enable - * @arg @ref I2C_IT_TCI Transfer complete interrupt enable - * @arg @ref I2C_IT_STOPI STOP detection interrupt enable - * @arg @ref I2C_IT_NACKI NACK received interrupt enable - * @arg @ref I2C_IT_ADDRI Address match interrupt enable - * @arg @ref I2C_IT_RXI RX interrupt enable - * @arg @ref I2C_IT_TXI TX interrupt enable - * - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified I2C flag is set or not. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_TXIS Transmit interrupt status - * @arg @ref I2C_FLAG_RXNE Receive data register not empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_TC Transfer complete (master mode) - * @arg @ref I2C_FLAG_TCR Transfer complete reload - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * @arg @ref I2C_FLAG_BUSY Bus busy - * @arg @ref I2C_FLAG_DIR Transfer direction (slave mode) - * - * @retval The new state of __FLAG__ (SET or RESET). - */ -#define I2C_FLAG_MASK (0x0001FFFFU) -#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & \ - (__FLAG__)) == (__FLAG__)) ? SET : RESET) - -/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit. - * @param __HANDLE__ specifies the I2C Handle. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be any combination of the following values: - * @arg @ref I2C_FLAG_TXE Transmit data register empty - * @arg @ref I2C_FLAG_ADDR Address matched (slave mode) - * @arg @ref I2C_FLAG_AF Acknowledge failure received flag - * @arg @ref I2C_FLAG_STOPF STOP detection flag - * @arg @ref I2C_FLAG_BERR Bus error - * @arg @ref I2C_FLAG_ARLO Arbitration lost - * @arg @ref I2C_FLAG_OVR Overrun/Underrun - * @arg @ref I2C_FLAG_PECERR PEC error in reception - * @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag - * @arg @ref I2C_FLAG_ALERT SMBus alert - * - * @retval None - */ -#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? \ - ((__HANDLE__)->Instance->ISR |= (__FLAG__)) : \ - ((__HANDLE__)->Instance->ICR = (__FLAG__))) - -/** @brief Enable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Disable the specified I2C peripheral. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) - -/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode. - * @param __HANDLE__ specifies the I2C Handle. - * @retval None - */ -#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) -/** - * @} - */ - -/* Include I2C HAL Extended module */ -#include "stm32u5xx_hal_i2c_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization and de-initialization functions******************************/ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, - pI2C_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* IO operation functions ****************************************************/ -/******* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout); - -/******* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress); - -#if defined(HAL_DMA_MODULE_ENABLED) -/******* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size); - -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions); -#endif /*HAL_DMA_MODULE_ENABLED*/ -/** - * @} - */ - -/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ -/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode); -void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c); -void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @{ - */ -/* Peripheral State, Mode and Error functions *********************************/ -HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c); -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c); -uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c); - -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Constants I2C Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_Private_Macro I2C Private Macros - * @{ - */ - -#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \ - ((MODE) == I2C_ADDRESSINGMODE_10BIT)) - -#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \ - ((ADDRESS) == I2C_DUALADDRESS_ENABLE)) - -#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \ - ((MASK) == I2C_OA2_MASK01) || \ - ((MASK) == I2C_OA2_MASK02) || \ - ((MASK) == I2C_OA2_MASK03) || \ - ((MASK) == I2C_OA2_MASK04) || \ - ((MASK) == I2C_OA2_MASK05) || \ - ((MASK) == I2C_OA2_MASK06) || \ - ((MASK) == I2C_OA2_MASK07)) - -#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \ - ((CALL) == I2C_GENERALCALL_ENABLE)) - -#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \ - ((STRETCH) == I2C_NOSTRETCH_ENABLE)) - -#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \ - ((SIZE) == I2C_MEMADD_SIZE_16BIT)) - -#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \ - ((MODE) == I2C_AUTOEND_MODE) || \ - ((MODE) == I2C_SOFTEND_MODE)) - -#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \ - ((REQUEST) == I2C_GENERATE_START_READ) || \ - ((REQUEST) == I2C_GENERATE_START_WRITE) || \ - ((REQUEST) == I2C_GENERATE_NO_START_READ) || \ - ((REQUEST) == I2C_GENERATE_NO_START_WRITE)|| \ - ((REQUEST) == I2C_NO_STARTSTOP)) - -#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \ - ((REQUEST) == I2C_NEXT_FRAME) || \ - ((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME) || \ - ((REQUEST) == I2C_LAST_FRAME_NO_STOP) || \ - IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) - -#define IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_OTHER_FRAME) || \ - ((REQUEST) == I2C_OTHER_AND_LAST_FRAME)) - -#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= \ - (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | \ - I2C_CR2_NBYTES | I2C_CR2_RELOAD | \ - I2C_CR2_RD_WRN))) - -#define I2C_GET_ADDR_MATCH(__HANDLE__) ((uint16_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) \ - >> 16U)) -#define I2C_GET_DIR(__HANDLE__) ((uint8_t)(((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) \ - >> 16U)) -#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) -#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)) -#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((uint16_t)((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)) - -#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) -#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) - -#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & \ - (uint16_t)(0xFF00U))) >> 8U))) -#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FFU)))) - -#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \ - (~I2C_CR2_RD_WRN)) : \ - (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \ - (I2C_CR2_ADD10) | (I2C_CR2_START) | \ - (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN))) - -#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \ - ((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET) -#define I2C_CHECK_IT_SOURCE(__CR1__, __IT__) ((((__CR1__) & (__IT__)) == (__IT__)) ? SET : RESET) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -/* Private functions are defined in stm32u5xx_hal_i2c.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32U5xx_HAL_I2C_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h deleted file mode 100644 index 4bd1ab8d9..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_i2c_ex.h +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_i2c_ex.h - * @author MCD Application Team - * @brief Header file of I2C HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_I2C_EX_H -#define STM32U5xx_HAL_I2C_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup I2CEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup I2C_Exported_Types I2C Exported Types - * @{ - */ - -/** @defgroup I2C_Autonomous_Mode_Configuration_Structure_definition Autonomous Mode Configuration Structure definition - * @brief I2C Autonomous Mode Configuration structure definition - * @{ - */ -typedef struct -{ - uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value - of @ref I2CEx_AutonomousMode_FunctionalState */ - - uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter - can be a value of @ref I2CEx_AutonomousMode_TriggerSelection */ - - uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter - can be a value of @ref I2CEx_AutonomousMode_TriggerPolarity */ - -} I2C_AutonomousModeConfTypeDef; -/** - * @} - */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Constants I2C Extended Exported Constants - * @{ - */ - -/** @defgroup I2CEx_Analog_Filter I2C Extended Analog Filter - * @{ - */ -#define I2C_ANALOGFILTER_ENABLE 0x00000000U -#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF -/** - * @} - */ - -/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus - * @{ - */ -#define I2C_FASTMODEPLUS_ENABLE 0x00000000U /*!< Enable Fast Mode Plus */ -#define I2C_FASTMODEPLUS_DISABLE 0x00000001U /*!< Disable Fast Mode Plus */ -/** - * @} - */ - -/** @defgroup I2CEx_AutonomousMode_FunctionalState I2C Extended Autonomous Mode State - * @{ - */ -#define I2C_AUTO_MODE_DISABLE (0x00000000U) /*!< Autonomous mode disable */ -#define I2C_AUTO_MODE_ENABLE I2C_AUTOCR_TRIGEN /*!< Autonomous mode enable */ -/** - * @} - */ - -/** @defgroup I2CEx_AutonomousMode_TriggerSelection I2C Extended Autonomous Mode Trigger Selection - * @{ - */ -#define I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ -#define I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ - -#define I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x00000000U)) -/*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define I2C_GRP1_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP1_EXTI9_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI9_TRG */ -#define I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM2_CH1_TRG */ -#define I2C_GRP1_COMP1_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ -#define I2C_GRP1_COMP2_TRG (uint32_t)(I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ -#define I2C_GRP1_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP1_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ - -#define I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x00000000U)) -/*!< HW Trigger signal is LPDMA_CH0_TRG */ -#define I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH1_TRG */ -#define I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH2_TRG */ -#define I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH3_TRG */ -#define I2C_GRP2_EXTI5_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI5_TRG */ -#define I2C_GRP2_EXTI8_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI8_TRG */ -#define I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM3_CH1_TRG */ -#define I2C_GRP2_COMP1_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ -#define I2C_GRP2_COMP2_TRG (uint32_t)(I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ -#define I2C_GRP2_RTC_ALRA_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ -#define I2C_GRP2_RTC_WUT_TRG (uint32_t)(I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ -/** - * @} - */ - -/** @defgroup I2CEx_AutonomousMode_TriggerPolarity Extended Autonomous Mode Trigger Polarity - * @{ - */ -#define I2C_TRIG_POLARITY_RISING (0x00000000U) /*!< I2C HW Trigger signal on rising edge */ -#define I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C HW Trigger signal on falling edge */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2CEx_Exported_Macros I2C Extended Exported Macros - * @{ - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @addtogroup I2CEx_Exported_Functions_Group1 Filter Mode Functions - * @{ - */ -/* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter); -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter); -/** - * @} - */ - -/** @addtogroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions - * @{ - */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c); -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** @addtogroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions - * @{ - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus); -/** - * @} - */ - -/** @addtogroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions - * @{ - */ -HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, - const I2C_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, - I2C_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Macro I2C Extended Private Macros - * @{ - */ -#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \ - ((FILTER) == I2C_ANALOGFILTER_DISABLE)) - -#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) - -#define IS_I2C_FASTMODEPLUS(__CONFIG__) (((__CONFIG__) == (I2C_FASTMODEPLUS_ENABLE)) || \ - ((__CONFIG__) == (I2C_FASTMODEPLUS_DISABLE))) - -#define IS_I2C_AUTO_MODE(__MODE__) (((__MODE__) == I2C_AUTO_MODE_DISABLE) || \ - ((__MODE__) == I2C_AUTO_MODE_ENABLE)) - -#define IS_I2C_TRIG_SOURCE(__INSTANCE__, __SOURCE__) (((__INSTANCE__) == I2C3) ? \ - IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) : \ - IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__)) - -#define IS_I2C_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP1_GPDMA_CH0_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_GPDMA_CH1_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_GPDMA_CH2_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_GPDMA_CH3_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_EXTI5_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_EXTI9_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_LPTIM1_CH1_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_LPTIM2_CH1_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_COMP1_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_COMP2_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_RTC_ALRA_TRG ) || \ - ((__SOURCE__) == I2C_GRP1_RTC_WUT_TRG )) - -#define IS_I2C_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == I2C_GRP2_LPDMA_CH0_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_LPDMA_CH1_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_LPDMA_CH2_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_LPDMA_CH3_TCF_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_EXTI5_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_EXTI8_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_LPTIM1_CH1_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_LPTIM3_CH1_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_COMP1_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_COMP2_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_RTC_ALRA_TRG ) || \ - ((__SOURCE__) == I2C_GRP2_RTC_WUT_TRG )) - -#define IS_I2C_TRIG_INPUT_INSTANCE(__INSTANCE__) (IS_I2C_GRP1_INSTANCE(__INSTANCE__) || \ - IS_I2C_GRP2_INSTANCE(__INSTANCE__)) - -#define IS_I2C_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == I2C_TRIG_POLARITY_RISING) || \ - ((__POLARITY__) == I2C_TRIG_POLARITY_FALLING)) -/** - * @} - */ - -/* Private Functions ---------------------------------------------------------*/ -/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions - * @{ - */ -/* Private functions are defined in stm32u5xx_hal_i2c_ex.c file */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_I2C_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h deleted file mode 100644 index 1f124b5a7..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_icache.h +++ /dev/null @@ -1,294 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_icache.h - * @author MCD Application Team - * @brief Header file of ICACHE HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion ------------------------------------*/ -#ifndef STM32U5xx_HAL_ICACHE_H -#define STM32U5xx_HAL_ICACHE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -----------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -#if defined(ICACHE) -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup ICACHE - * @{ - */ - -/* Exported types -----------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Types ICACHE Exported Types - * @{ - */ - -/** - * @brief HAL ICACHE region configuration structure definition - */ -typedef struct -{ - uint32_t BaseAddress; /*!< Configures the Base address of Region i to be remapped */ - - uint32_t RemapAddress; /*!< Configures the Remap address of Region i to be remapped */ - - uint32_t Size; /*!< Configures the Region size. - This parameter can be a value of @ref ICACHE_Region_Size */ - - uint32_t TrafficRoute; /*!< Selects the traffic route. - This parameter can be a value of @ref ICACHE_Traffic_Route */ - - uint32_t OutputBurstType; /*!< Selects the output burst type. - This parameter can be a value of @ref ICACHE_Output_Burst_Type */ -} ICACHE_RegionConfigTypeDef; -/** - * @} - */ - -/* Exported constants -------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Constants ICACHE Exported Constants - * @{ - */ - -/** @defgroup ICACHE_WaysSelection Ways selection - * @{ - */ -#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ -#define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ -/** - * @} - */ - -/** @defgroup ICACHE_Monitor_Type Monitor type - * @{ - */ -#define ICACHE_MONITOR_HIT_MISS (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< Hit & Miss monitoring */ -#define ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitoring */ -#define ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitoring */ -/** - * @} - */ - -/** @defgroup ICACHE_Region Remapped Region number - * @{ - */ -#define ICACHE_REGION_0 0U /*!< Region 0 */ -#define ICACHE_REGION_1 1U /*!< Region 1 */ -#define ICACHE_REGION_2 2U /*!< Region 2 */ -#define ICACHE_REGION_3 3U /*!< Region 3 */ -/** - * @} - */ - -/** @defgroup ICACHE_Region_Size Remapped Region size - * @{ - */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ -/** - * @} - */ - -/** @defgroup ICACHE_Traffic_Route Remapped Traffic route - * @{ - */ -#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */ -#define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ -/** - * @} - */ - -/** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type - * @{ - */ -#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ -#define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ -/** - * @} - */ - -/** @defgroup ICACHE_Interrupts Interrupts - * @{ - */ -#define ICACHE_IT_BUSYEND ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ -#define ICACHE_IT_ERROR ICACHE_IER_ERRIE /*!< Cache error interrupt */ -/** - * @} - */ - -/** @defgroup ICACHE_Flags Flags - * @{ - */ -#define ICACHE_FLAG_BUSY ICACHE_SR_BUSYF /*!< Busy flag */ -#define ICACHE_FLAG_BUSYEND ICACHE_SR_BSYENDF /*!< Busy end flag */ -#define ICACHE_FLAG_ERROR ICACHE_SR_ERRF /*!< Cache error flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros ----------------------------------------------------------*/ -/** @defgroup ICACHE_Exported_Macros ICACHE Exported Macros - * @{ - */ - -/** @defgroup ICACHE_Flags_Interrupts_Management Flags and Interrupts Management - * @brief macros to manage the specified ICACHE flags and interrupts. - * @{ - */ - -/** @brief Enable ICACHE interrupts. - * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - */ -#define __HAL_ICACHE_ENABLE_IT(__INTERRUPT__) SET_BIT(ICACHE->IER, (__INTERRUPT__)) - -/** @brief Disable ICACHE interrupts. - * @param __INTERRUPT__ specifies the ICACHE interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - */ -#define __HAL_ICACHE_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(ICACHE->IER, (__INTERRUPT__)) - -/** @brief Check whether the specified ICACHE interrupt source is enabled or not. - * @param __INTERRUPT__ specifies the ICACHE interrupt source to check. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_IT_BUSYEND Busy end interrupt - * @arg @ref ICACHE_IT_ERROR Cache error interrupt - * @retval The state of __INTERRUPT__ (0 or 1). - */ -#define __HAL_ICACHE_GET_IT_SOURCE(__INTERRUPT__) \ - ((READ_BIT(ICACHE->IER, (__INTERRUPT__)) == (__INTERRUPT__)) ? 1U : 0U) - -/** @brief Check whether the selected ICACHE flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref ICACHE_FLAG_BUSY Busy flag - * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag - * @arg @ref ICACHE_FLAG_ERROR Cache error flag - * @retval The state of __FLAG__ (0 or 1). - */ -#define __HAL_ICACHE_GET_FLAG(__FLAG__) ((READ_BIT(ICACHE->SR, (__FLAG__)) != 0U) ? 1U : 0U) - -/** @brief Clear the selected ICACHE flags. - * @param __FLAG__ specifies the ICACHE flags to clear. - * This parameter can be any combination of the following values: - * @arg @ref ICACHE_FLAG_BUSYEND Busy end flag - * @arg @ref ICACHE_FLAG_ERROR Cache error flag - */ -#define __HAL_ICACHE_CLEAR_FLAG(__FLAG__) WRITE_REG(ICACHE->FCR, (__FLAG__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions -------------------------------------------------------*/ -/** @addtogroup ICACHE_Exported_Functions - * @{ - */ - -/** @addtogroup ICACHE_Exported_Functions_Group1 - * @brief Initialization and control functions - * @{ - */ -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_ICACHE_Enable(void); -HAL_StatusTypeDef HAL_ICACHE_Disable(void); -uint32_t HAL_ICACHE_IsEnabled(void); -HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode); -HAL_StatusTypeDef HAL_ICACHE_DeInit(void); - -/******* Invalidate in blocking mode (Polling) */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate(void); -/******* Invalidate in non-blocking mode (Interrupt) */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void); -/******* Wait for Invalidate complete in blocking mode (Polling) */ -HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void); - -/******* Performance instruction cache monitoring functions */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType); -HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType); -HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType); -uint32_t HAL_ICACHE_Monitor_GetHitValue(void); -uint32_t HAL_ICACHE_Monitor_GetMissValue(void); - -/** - * @} - */ - -/** @addtogroup ICACHE_Exported_Functions_Group2 - * @brief IRQ and callback functions - * @{ - */ -/******* IRQHandler and Callbacks used in non-blocking mode (Interrupt) */ -void HAL_ICACHE_IRQHandler(void); -void HAL_ICACHE_InvalidateCompleteCallback(void); -void HAL_ICACHE_ErrorCallback(void); - -/** - * @} - */ - -/** @addtogroup ICACHE_Exported_Functions_Group3 - * @brief Memory remapped regions functions - * @{ - */ -/******* Memory remapped regions functions */ -HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig); -HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* ICACHE */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_ICACHE_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mdf.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mdf.h deleted file mode 100644 index 6ee766a52..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_mdf.h +++ /dev/null @@ -1,1182 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_mdf.h - * @author MCD Application Team - * @brief Header file of MDF HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_MDF_H -#define STM32U5xx_HAL_MDF_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup MDF - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup MDF_Exported_Types MDF Exported Types - * @{ - */ - -/** - * @brief HAL MDF states definition - */ -typedef enum -{ - HAL_MDF_STATE_RESET = 0x00U, /*!< MDF not initialized */ - HAL_MDF_STATE_READY = 0x01U, /*!< MDF initialized and ready for use */ - HAL_MDF_STATE_ACQUISITION = 0x02U, /*!< MDF acquisition in progress */ - HAL_MDF_STATE_ERROR = 0xFFU /*!< MDF state error */ -} HAL_MDF_StateTypeDef; - -/** - * @brief MDF clock trigger structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Output clock trigger enable/disable */ - uint32_t Source; /*!< Output clock trigger source. - This parameter can be a value of @ref MDF_ClockTriggerSource */ - uint32_t Edge; /*!< Output clock trigger edge. - This parameter can be a value of @ref MDF_ClockTriggerEdge */ -} MDF_ClockTriggerTypeDef; - -/** - * @brief MDF output clock structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Output clock enable/disable */ - uint32_t Pins; /*!< Output clock pins. - This parameter can be a value of @ref MDF_OuputClockPins */ - uint32_t Divider; /*!< Output clock divider. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ - MDF_ClockTriggerTypeDef Trigger; /*!< Output clock trigger parameters */ -} MDF_OutputClockTypeDef; - -/** - * @brief MDF common parameters structure definition - */ -typedef struct -{ - uint32_t InterleavedFilters; /*!< Number of filters in interleaved mode with filter 0. - This parameter must be a number between Min_Data = 0 - and Max_Data = 1 for STM32U535xx/STM32U545xx devices. - This parameter must be a number between Min_Data = 0 - and Max_Data = 5 for other devices. - @note This parameter is not used for ADF instance */ - uint32_t ProcClockDivider; /*!< Processing clock divider. - This parameter must be a number between Min_Data = 1 - and Max_Data = 128 */ - MDF_OutputClockTypeDef OutputClock; /*!< Output clock parameters */ -} MDF_CommonParamTypeDef; - -/** - * @brief MDF serial interface structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Serial interface enable/disable */ - uint32_t Mode; /*!< Serial interface mode. - This parameter can be a value of @ref MDF_SitfMode */ - uint32_t ClockSource; /*!< Serial interface clock source. - This parameter can be a value of @ref MDF_SitfClockSource */ - uint32_t Threshold; /*!< SPI threshold for clock absence detection or Manchester symbol threshold. - This parameter must be a number between Min_Data = 4 and Max_Data = 31 */ -} MDF_SerialInterfaceTypeDef; - -/** - * @brief MDF init structure definition - */ -typedef struct -{ - MDF_CommonParamTypeDef CommonParam; /*!< MDF common parameters */ - MDF_SerialInterfaceTypeDef SerialInterface; /*!< MDF serial interface parameters */ - uint32_t FilterBistream; /*!< MDF filter bitstream selection. - This parameter can be a value of @ref MDF_FilterBitstream */ -} MDF_InitTypeDef; - -/** - * @brief MDF handle structure definition - */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) -typedef struct __MDF_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -{ - MDF_Filter_TypeDef *Instance; /*!< MDF instance */ - MDF_InitTypeDef Init; /*!< MDF init parameters */ - DMA_HandleTypeDef *hdma; /*!< Pointer on DMA handler for acquisitions */ - __IO HAL_MDF_StateTypeDef State; /*!< MDF state */ - __IO uint32_t ErrorCode; /*!< MDF error code */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - void (*OldCallback)(struct __MDF_HandleTypeDef *hmdf, - uint32_t Threshold); /*!< MDF out-off limit detector callback. - @note Not used for ADF instance */ - void (*AcqCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition complete callback */ - void (*AcqHalfCpltCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF acquisition half complete callback */ - void (*SndLvCallback)(struct __MDF_HandleTypeDef *hmdf, - uint32_t SoundLevel, - uint32_t AmbientNoise); /*!< MDF sound level callback. - @note Not used for MDF instance */ - void (*SadCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF sound activity detector callback. - @note Not used for MDF instance */ - void (*ErrorCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF error callback */ - void (*MspInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP init callback */ - void (*MspDeInitCallback)(struct __MDF_HandleTypeDef *hmdf); /*!< MDF MSP de-init callback */ -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -} MDF_HandleTypeDef; - -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) -/** - * @brief MDF callback ID enumeration definition - */ -typedef enum -{ - HAL_MDF_OLD_CB_ID = 0x00U, /*!< MDF out-off limit detector callback ID. - @note Not used for ADF instance */ - HAL_MDF_ACQ_COMPLETE_CB_ID = 0x01U, /*!< MDF acquisition complete callback ID */ - HAL_MDF_ACQ_HALFCOMPLETE_CB_ID = 0x02U, /*!< MDF acquisition half complete callback ID */ - HAL_MDF_SNDLVL_CB_ID = 0x03U, /*!< MDF sound level callback ID. - @note Not used for MDF instance */ - HAL_MDF_SAD_CB_ID = 0x04U, /*!< MDF sound activity detector callback ID. - @note Not used for MDF instance */ - HAL_MDF_ERROR_CB_ID = 0x05U, /*!< MDF error callback ID */ - HAL_MDF_MSPINIT_CB_ID = 0x06U, /*!< MDF MSP init callback ID */ - HAL_MDF_MSPDEINIT_CB_ID = 0x07U /*!< MDF MSP de-init callback ID */ -} HAL_MDF_CallbackIDTypeDef; - -/** - * @brief MDF callback pointers definition - */ -typedef void (*pMDF_CallbackTypeDef)(MDF_HandleTypeDef *hmdf); -typedef void (*pMDF_OldCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t Threshold); -typedef void (*pMDF_SndLvlCallbackTypeDef)(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - -/** - * @brief MDF reshape filter structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Reshape filter enable/disable */ - uint32_t DecimationRatio; /*!< Reshape filter decimation ratio. - This parameter can be a value of @ref MDF_ReshapeDecimationRatio */ -} MDF_ReshapeFilterTypeDef; - -/** - * @brief MDF high pass filter structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< High pass filter enable/disable */ - uint32_t CutOffFrequency; /*!< High pass filter cut-off frequency. - This parameter can be a value of @ref MDF_HighPassCutOffFreq */ -} MDF_HighPassFilterTypeDef; - -/** - * @brief MDF integrator structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Integrator enable/disable */ - uint32_t Value; /*!< Integrator value. - This parameter must be a number between Min_Data = 2 and Max_Data = 128 */ - uint32_t OutputDivision; /*!< Integrator output division. - This parameter can be a value of @ref MDF_IntegratorOutputDiv */ -} MDF_IntegratorTypeDef; - -/** - * @brief MDF sound activity structure definition - */ -typedef struct -{ - FunctionalState Activation; /*!< Sound activity detector enable/disable */ - uint32_t Mode; /*!< Sound activity detector mode. - This parameter can be a value of @ref MDF_SadMode */ - uint32_t FrameSize; /*!< Size of one frame to compute short-term signal level. - This parameter can be a value of @ref MDF_SadFrameSize */ - FunctionalState Hysteresis; /*!< Hysteresis enable/disable. - @note This parameter is not used if Mode is set - to MDF_SAD_AMBIENT_NOISE_ESTIMATOR */ - uint32_t SoundTriggerEvent; /*!< Sound trigger event configuration. - This parameter can be a value of @ref MDF_SadSoundTriggerEvent */ - uint32_t DataMemoryTransfer; /*!< Data memory transfer mode. - This parameter can be a value of @ref MDF_SadDataMemoryTransfer */ - uint32_t MinNoiseLevel; /*!< Minimum noise level. - This parameter must be a number between Min_Data = 0 - and Max_Data = 8191 */ - uint32_t HangoverWindow; /*!< Hangover time window in frames. - This parameter can be a value of @ref MDF_SadHangoverWindow */ - uint32_t LearningFrames; /*!< Number of learning frames for the first estimation of noise level. - This parameter can be a value of @ref MDF_SadLearningFrames */ - uint32_t AmbientNoiseSlope; /*!< Ambient noise slope control. - This parameter must be a number between Min_Data = 0 and Max_Data = 7. - @note This parameter is not used if Mode is set - to MDF_SAD_SOUND_DETECTOR */ - uint32_t SignalNoiseThreshold; /*!< Signal to noise threshold. - This parameter can be a value of @ref MDF_SadSignalNoiseThreshold */ - FunctionalState SoundLevelInterrupt; /*!< Sound level interrupt enable/disable. - @note This interrupt is mainly used for debug purpose*/ - -} MDF_SoundActivityTypeDef; - -/** - * @brief MDF filter trigger structure definition - */ -typedef struct -{ - uint32_t Source; /*!< Filter trigger source. - This parameter can be a value of @ref MDF_FilterTriggerSource */ - uint32_t Edge; /*!< Filter trigger edge. - This parameter can be a value of @ref MDF_FilterTriggerEdge */ -} MDF_FilterTriggerTypeDef; - -/** - * @brief MDF filter configuration structure definition - */ -typedef struct -{ - uint32_t DataSource; /*!< Filter data source. - This parameter can be a value of @ref MDF_DataSource */ - uint32_t Delay; /*!< Delay to apply on data source in number of samples. - This parameter must be a number between Min_Data = 0 - and Max_Data = 127 */ - uint32_t CicMode; /*!< CIC filter mode. - This parameter can be a value of @ref MDF_CicMode */ - uint32_t DecimationRatio; /*!< Filter decimation ratio. - This parameter must be a number between Min_Data = 2 - and Max_Data = 512 */ - int32_t Offset; /*!< Filter offset error compensation. - This parameter must be a number between Min_Data = -33554432 - and Max_Data = 33554431. - @note This parameter is not used for ADF instance */ - int32_t Gain; /*!< Filter gain in step of around 3db (from -48db to 72dB). - This parameter must be a number between Min_Data = -16 - and Max_Data = 24 */ - MDF_ReshapeFilterTypeDef ReshapeFilter; /*!< Reshape filter configuration */ - MDF_HighPassFilterTypeDef HighPassFilter; /*!< High pass filter configuration */ - MDF_IntegratorTypeDef Integrator; /*!< Integrator configuration. - @note This parameter is not used for ADF instance */ - MDF_SoundActivityTypeDef SoundActivity; /*!< Sound activity detector configuration. - @note This parameter is not used for MDF instance */ - uint32_t AcquisitionMode; /*!< Filter acquisition mode. - This parameter can be a value of @ref MDF_AcquisitionMode */ - uint32_t FifoThreshold; /*!< Filter RXFIFO threshold. - This parameter can be a value of @ref MDF_FifoThreshold */ - uint32_t DiscardSamples; /*!< Number of samples to discard after filter enable. - This parameter must be a number between Min_Data = 0 - and Max_Data = 255 */ - MDF_FilterTriggerTypeDef Trigger; /*!< Filter trigger configuration. - @note This parameter is not used if AcquisitionMode is set - to MDF_MODE_ASYNC_CONT or MDF_MODE_ASYNC_SINGLE */ - uint32_t SnapshotFormat; /*!< Snapshot format. - This parameter can be a value of @ref MDF_SnapshotFormat. - @note This parameter is used only if AcquisitionMode is set - to MDF_MODE_SYNC_SNAPSHOT and for MDF instance */ -} MDF_FilterConfigTypeDef; - -/** - * @brief MDF snapshot parameters structure definition - */ -typedef struct -{ - int32_t Value; /*!< Snapshot acquisition value on 16 or 23 MSB depending on snapshot format */ - uint32_t DecimationCounter; /*!< Decimation counter value when snapshot trigger occurs */ - uint32_t IntegratorCounter; /*!< Integrator counter value when snapshot trigger occurs. - This value is available only if snapshot format is 16 bits resolution */ -} MDF_SnapshotParamTypeDef; - -/** - * @brief MDF DMA configuration structure definition - */ -typedef struct -{ - uint32_t Address; /*!< DMA destination address */ - uint32_t DataLength; /*!< Length of data to transfer in bytes */ - FunctionalState MsbOnly; /*!< Transfer only the 16MSB of the acquistion data */ -} MDF_DmaConfigTypeDef; - -/** - * @brief MDF short-circuit detector configuration structure definition - */ -typedef struct -{ - uint32_t Threshold; /*!< Short-circuit detector threshold. - This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ - uint32_t BreakSignal; /*!< Break signal assignment for short-circuit detector. - This parameter can be a values combination of @ref MDF_BreakSignals */ -} MDF_ScdConfigTypeDef; - -/** - * @brief MDF out-off limit detector configuration structure definition - */ -typedef struct -{ - uint32_t OldCicMode; /*!< Out-off limit detector CIC filter mode. - This parameter can be a value of @ref MDF_OldCicMode */ - uint32_t OldDecimationRatio; /*!< Out-off limit detector decimation ratio. - This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ - int32_t HighThreshold; /*!< Out-off limit detector high threshold. - This parameter must be a number between Min_Data = -33554432 - and Max_Data = 33554431 */ - int32_t LowThreshold; /*!< Out-off limit detector low threshold. - This parameter must be a number between Min_Data = -33554432 - and Max_Data = 33554431 */ - uint32_t OldEventConfig; /*!< Out-off limit event configuration. - This parameter can be a value of @ref MDF_OldEventConfig */ - uint32_t BreakSignal; /*!< Break signal assignment for out-off limit detector. - This parameter can be a values combination of @ref MDF_BreakSignals */ -} MDF_OldConfigTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup MDF_Exported_Constants MDF Exported Constants - * @{ - */ - -/** @defgroup MDF_ErrorCode MDF error code - * @{ - */ -#define MDF_ERROR_NONE 0x00000000U /*!< No error */ -#define MDF_ERROR_ACQUISITION_OVERFLOW 0x00000001U /*!< Overflow occurs during acquisition */ -#define MDF_ERROR_RSF_OVERRUN 0x00000002U /*!< Overrun occurs on reshape filter */ -#define MDF_ERROR_CLOCK_ABSENCE 0x00000004U /*!< Clock absence detection occurs */ -#define MDF_ERROR_SHORT_CIRCUIT 0x00000008U /*!< Short circuit detection occurs. - @note Not used for ADF instance */ -#define MDF_ERROR_SATURATION 0x00000010U /*!< Saturation detection occurs */ -#define MDF_ERROR_OUT_OFF_LIMIT 0x00000020U /*!< Out-off limit detection occurs. - @note Not used for ADF instance */ -#define MDF_ERROR_DMA 0x00000040U /*!< DMA error occurs */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) -#define MDF_ERROR_INVALID_CALLBACK 0x00000080U /*!< Invalid callback error occurs */ -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup MDF_ClockTriggerSource MDF output clock trigger source - * @{ - */ -#define MDF_CLOCK_TRIG_TRGO 0x00000000U -#define MDF_CLOCK_TRIG_TIM1_TRGO MDF_CKGCR_TRGSRC_1 /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM1_TRGO2 (MDF_CKGCR_TRGSRC_0 | \ - MDF_CKGCR_TRGSRC_1) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM8_TRGO MDF_CKGCR_TRGSRC_2 /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM8_TRGO2 (MDF_CKGCR_TRGSRC_0 | \ - MDF_CKGCR_TRGSRC_2) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM3_TRGO (MDF_CKGCR_TRGSRC_1 | \ - MDF_CKGCR_TRGSRC_2) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM4_TRGO (MDF_CKGCR_TRGSRC_0 | \ - MDF_CKGCR_TRGSRC_1 | \ - MDF_CKGCR_TRGSRC_2) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM16_OC1 MDF_CKGCR_TRGSRC_3 /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM6_TRGO (MDF_CKGCR_TRGSRC_0 | \ - MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_TIM7_TRGO (MDF_CKGCR_TRGSRC_1 | \ - MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_SAD_DET (MDF_CKGCR_TRGSRC_0 | \ - MDF_CKGCR_TRGSRC_1 | \ - MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_EXTI11 (MDF_CKGCR_TRGSRC_2 | \ - MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_EXTI15 (MDF_CKGCR_TRGSRC_0 | \ - MDF_CKGCR_TRGSRC_2 | \ - MDF_CKGCR_TRGSRC_3) -#define MDF_CLOCK_TRIG_LPTIM1_OUT (MDF_CKGCR_TRGSRC_1 | \ - MDF_CKGCR_TRGSRC_2 | \ - MDF_CKGCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_CLOCK_TRIG_SAD_TRGO MDF_CKGCR_TRGSRC /*!< @note Not available for ADF instance */ -/** - * @} - */ - -/** @defgroup MDF_ClockTriggerEdge MDF output clock trigger edge - * @{ - */ -#define MDF_CLOCK_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */ -#define MDF_CLOCK_TRIG_FALLING_EDGE MDF_CKGCR_TRGSENS /*!< Falling edge */ -/** - * @} - */ - -/** @defgroup MDF_OuputClockPins MDF output clock pins - * @{ - */ -#define MDF_OUTPUT_CLOCK_0 MDF_CKGCR_CCK0DIR /*!< MDF_CCK0 is used as output clock */ -#define MDF_OUTPUT_CLOCK_1 MDF_CKGCR_CCK1DIR /*!< MDF_CCK1 is used as output clock */ -#define MDF_OUTPUT_CLOCK_ALL (MDF_CKGCR_CCK0DIR | \ - MDF_CKGCR_CCK1DIR) /*!< MDF_CCK0 and MDF_CCK1 are used as output clock */ -/** - * @} - */ - -/** @defgroup MDF_SitfMode MDF serial interface mode - * @{ - */ -#define MDF_SITF_LF_MASTER_SPI_MODE 0x00000000U /*!< Low frequency master SPI mode */ -#define MDF_SITF_NORMAL_SPI_MODE MDF_SITFCR_SITFMOD_0 /*!< Normal SPI mode */ -#define MDF_SITF_MANCHESTER_FALLING_MODE MDF_SITFCR_SITFMOD_1 /*!< Manchester mode rising edge logic 0 - and falling edge logic 1 */ -#define MDF_SITF_MANCHESTER_RISING_MODE MDF_SITFCR_SITFMOD /*!< Manchester mode rising edge logic 1 - and falling edge logic 0 */ -/** - * @} - */ - -/** @defgroup MDF_SitfClockSource MDF serial interface clock source - * @{ - */ -#define MDF_SITF_CCK0_SOURCE 0x00000000U /*!< Common clock 0 source */ -#define MDF_SITF_CCK1_SOURCE MDF_SITFCR_SCKSRC_0 /*!< Common clock 1 source */ -#define MDF_SITF_CKI_SOURCE MDF_SITFCR_SCKSRC_1 /*!< Dedicated input clock source. - @note Not available for ADF instance */ -/** - * @} - */ - -/** @defgroup MDF_FilterBitstream MDF filter bitstream - * @{ - */ -#define MDF_BITSTREAM0_RISING 0x00000000U -#define MDF_BITSTREAM0_FALLING MDF_BSMXCR_BSSEL_0 -#define MDF_BITSTREAM1_RISING MDF_BSMXCR_BSSEL_1 /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM1_FALLING (MDF_BSMXCR_BSSEL_0 | \ - MDF_BSMXCR_BSSEL_1) /*!< @note Not available for ADF instance */ -#if !defined(STM32U535xx) && !defined(STM32U545xx) -#define MDF_BITSTREAM2_RISING MDF_BSMXCR_BSSEL_2 /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM2_FALLING (MDF_BSMXCR_BSSEL_0 | \ - MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM3_RISING (MDF_BSMXCR_BSSEL_1 | \ - MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM3_FALLING (MDF_BSMXCR_BSSEL_0 | \ - MDF_BSMXCR_BSSEL_1 | \ - MDF_BSMXCR_BSSEL_2) /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM4_RISING MDF_BSMXCR_BSSEL_3 /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM4_FALLING (MDF_BSMXCR_BSSEL_0 | \ - MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM5_RISING (MDF_BSMXCR_BSSEL_1 | \ - MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */ -#define MDF_BITSTREAM5_FALLING (MDF_BSMXCR_BSSEL_0 | \ - MDF_BSMXCR_BSSEL_1 | \ - MDF_BSMXCR_BSSEL_3) /*!< @note Not available for ADF instance */ -#endif /* !defined(STM32U535xx) && !defined(STM32U545xx) */ -/** - * @} - */ - -/** @defgroup MDF_ReshapeDecimationRatio MDF reshape filter decimation ratio - * @{ - */ -#define MDF_RSF_DECIMATION_RATIO_4 0x00000000U /*!< Reshape filter decimation ratio is 4 */ -#define MDF_RSF_DECIMATION_RATIO_1 MDF_DFLTRSFR_RSFLTD /*!< Reshape filter decimation ratio is 1 */ -/** - * @} - */ - -/** @defgroup MDF_HighPassCutOffFreq MDF high pass filter cut-off frequency - * @{ - */ -#define MDF_HPF_CUTOFF_0_000625FPCM 0x00000000U /*!< Cut-off frequency of 0.000625xFpcm */ -#define MDF_HPF_CUTOFF_0_00125FPCM MDF_DFLTRSFR_HPFC_0 /*!< Cut-off frequency of 0.00125xFpcm */ -#define MDF_HPF_CUTOFF_0_0025FPCM MDF_DFLTRSFR_HPFC_1 /*!< Cut-off frequency of 0.0025xFpcm */ -#define MDF_HPF_CUTOFF_0_0095FPCM MDF_DFLTRSFR_HPFC /*!< Cut-off frequency of 0.0095xFpcm */ -/** - * @} - */ - -/** @defgroup MDF_IntegratorOutputDiv MDF integrator output division - * @{ - */ -#define MDF_INTEGRATOR_OUTPUT_DIV_128 0x00000000U /*!< Integrator data outputs divided by 128 */ -#define MDF_INTEGRATOR_OUTPUT_DIV_32 MDF_DFLTINTR_INTDIV_0 /*!< Integrator data outputs divided by 32 */ -#define MDF_INTEGRATOR_OUTPUT_DIV_4 MDF_DFLTINTR_INTDIV_1 /*!< Integrator data outputs divided by 4 */ -#define MDF_INTEGRATOR_OUTPUT_NO_DIV MDF_DFLTINTR_INTDIV /*!< Integrator data outputs not divided */ -/** - * @} - */ - -/** @defgroup MDF_SadMode MDF sound activity detector mode - * @{ - */ -#define MDF_SAD_VOICE_ACTIVITY_DETECTOR 0x00000000U /*!< Voice activity detector */ -#define MDF_SAD_SOUND_DETECTOR MDF_SADCR_SADMOD_0 /*!< Sound detector */ -#define MDF_SAD_AMBIENT_NOISE_DETECTOR MDF_SADCR_SADMOD /*!< Ambient noise detector */ -/** - * @} - */ - -/** @defgroup MDF_SadFrameSize MDF sound activity detector frame size - * @{ - */ -#define MDF_SAD_8_PCM_SAMPLES 0x00000000U /*!< Frame size of 8 PCM samples */ -#define MDF_SAD_16_PCM_SAMPLES MDF_SADCR_FRSIZE_0 /*!< Frame size of 16 PCM samples */ -#define MDF_SAD_32_PCM_SAMPLES MDF_SADCR_FRSIZE_1 /*!< Frame size of 32 PCM samples */ -#define MDF_SAD_64_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_1) /*!< Frame size of 64 PCM samples */ -#define MDF_SAD_128_PCM_SAMPLES MDF_SADCR_FRSIZE_2 /*!< Frame size of 128 PCM samples */ -#define MDF_SAD_256_PCM_SAMPLES (MDF_SADCR_FRSIZE_0 | MDF_SADCR_FRSIZE_2) /*!< Frame size of 256 PCM samples */ -#define MDF_SAD_512_PCM_SAMPLES MDF_SADCR_FRSIZE /*!< Frame size of 512 PCM samples */ -/** - * @} - */ - -/** @defgroup MDF_SadSoundTriggerEvent MDF sound activity detector trigger event - * @{ - */ -#define MDF_SAD_ENTER_DETECT 0x00000000U /*!< Event when SAD enters in detect state */ -#define MDF_SAD_ENTER_EXIT_DETECT MDF_SADCR_DETCFG /*!< Event when SAD enters or exits from detect state */ -/** - * @} - */ - -/** @defgroup MDF_SadDataMemoryTransfer MDF sound activity detector data memory transfer mode - * @{ - */ -#define MDF_SAD_NO_MEMORY_TRANSFER 0x00000000U /*!< No memory transfer */ -#define MDF_SAD_MEMORY_TRANSFER_IN_DETECT MDF_SADCR_DATCAP_0 /*!< Memory transfer only in detect state */ -#define MDF_SAD_MEMORY_TRANSFER_ALWAYS MDF_SADCR_DATCAP /*!< Memory transfer always */ -/** - * @} - */ - -/** @defgroup MDF_SadHangoverWindow MDF sound activity detector data hangover time window - * @{ - */ -#define MDF_SAD_HANGOVER_4_FRAMES 0x00000000U /*!< Hangover window of 4 frames */ -#define MDF_SAD_HANGOVER_8_FRAMES MDF_SADCFGR_HGOVR_0 /*!< Hangover window of 8 frames */ -#define MDF_SAD_HANGOVER_16_FRAMES MDF_SADCFGR_HGOVR_1 /*!< Hangover window of 16 frames */ -#define MDF_SAD_HANGOVER_32_FRAMES (MDF_SADCFGR_HGOVR_0 | \ - MDF_SADCFGR_HGOVR_1) /*!< Hangover window of 32 frames */ -#define MDF_SAD_HANGOVER_64_FRAMES MDF_SADCFGR_HGOVR_2 /*!< Hangover window of 64 frames */ -#define MDF_SAD_HANGOVER_128_FRAMES (MDF_SADCFGR_HGOVR_0 | \ - MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 128 frames */ -#define MDF_SAD_HANGOVER_256_FRAMES (MDF_SADCFGR_HGOVR_1 | \ - MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 256 frames */ -#define MDF_SAD_HANGOVER_512_FRAMES (MDF_SADCFGR_HGOVR_0 | \ - MDF_SADCFGR_HGOVR_1 | \ - MDF_SADCFGR_HGOVR_2) /*!< Hangover window of 512 frames */ -/** - * @} - */ - -/** @defgroup MDF_SadLearningFrames MDF sound activity detector data learning frames - * @{ - */ -#define MDF_SAD_LEARNING_2_FRAMES 0x00000000U /*!< 2 learning frames */ -#define MDF_SAD_LEARNING_4_FRAMES MDF_SADCFGR_LFRNB_0 /*!< 4 learning frames */ -#define MDF_SAD_LEARNING_8_FRAMES MDF_SADCFGR_LFRNB_1 /*!< 8 learning frames */ -#define MDF_SAD_LEARNING_16_FRAMES (MDF_SADCFGR_LFRNB_0 | MDF_SADCFGR_LFRNB_1) /*!< 16 learning frames */ -#define MDF_SAD_LEARNING_32_FRAMES MDF_SADCFGR_LFRNB /*!< 32 learning frames */ -/** - * @} - */ - -/** @defgroup MDF_SadSignalNoiseThreshold MDF sound activity detector data signal to noise threshold - * @{ - */ -#define MDF_SAD_SIGNAL_NOISE_3_5DB 0x00000000U /*!< Signal to noise threshold is 3.5dB */ -#define MDF_SAD_SIGNAL_NOISE_6DB MDF_SADCFGR_SNTHR_0 /*!< Signal to noise threshold is 6dB */ -#define MDF_SAD_SIGNAL_NOISE_9_5DB MDF_SADCFGR_SNTHR_1 /*!< Signal to noise threshold is 9.5dB */ -#define MDF_SAD_SIGNAL_NOISE_12DB (MDF_SADCFGR_SNTHR_0 | \ - MDF_SADCFGR_SNTHR_1) /*!< Signal to noise threshold is 12dB */ -#define MDF_SAD_SIGNAL_NOISE_15_6DB MDF_SADCFGR_SNTHR_2 /*!< Signal to noise threshold is 15.6dB */ -#define MDF_SAD_SIGNAL_NOISE_18DB (MDF_SADCFGR_SNTHR_0 | \ - MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 18dB */ -#define MDF_SAD_SIGNAL_NOISE_21_6DB (MDF_SADCFGR_SNTHR_1 | \ - MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 21.6dB */ -#define MDF_SAD_SIGNAL_NOISE_24_1DB (MDF_SADCFGR_SNTHR_0 | \ - MDF_SADCFGR_SNTHR_1 | \ - MDF_SADCFGR_SNTHR_2) /*!< Signal to noise threshold is 24.1dB */ -#define MDF_SAD_SIGNAL_NOISE_27_6DB MDF_SADCFGR_SNTHR_3 /*!< Signal to noise threshold is 27.6dB */ -#define MDF_SAD_SIGNAL_NOISE_30_1DB (MDF_SADCFGR_SNTHR_0 | \ - MDF_SADCFGR_SNTHR_3) /*!< Signal to noise threshold is 30.1dB */ -/** - * @} - */ - -/** @defgroup MDF_FilterTriggerSource MDF filter trigger source - * @{ - */ -#define MDF_FILTER_TRIG_TRGO 0x00000000U -#define MDF_FILTER_TRIG_OLD_EVENT MDF_DFLTCR_TRGSRC_0 /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM1_TRGO MDF_DFLTCR_TRGSRC_1 /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM1_TRGO2 (MDF_DFLTCR_TRGSRC_0 | \ - MDF_DFLTCR_TRGSRC_1) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM8_TRGO MDF_DFLTCR_TRGSRC_2 /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM8_TRGO2 (MDF_DFLTCR_TRGSRC_0 | \ - MDF_DFLTCR_TRGSRC_2) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM3_TRGO (MDF_DFLTCR_TRGSRC_1 | \ - MDF_DFLTCR_TRGSRC_2) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM4_TRGO (MDF_DFLTCR_TRGSRC_0 | \ - MDF_DFLTCR_TRGSRC_1 | \ - MDF_DFLTCR_TRGSRC_2) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM16_OC1 MDF_DFLTCR_TRGSRC_3 /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM6_TRGO (MDF_DFLTCR_TRGSRC_0 | \ - MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_TIM7_TRGO (MDF_DFLTCR_TRGSRC_1 | \ - MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_ADF_SAD_DET (MDF_DFLTCR_TRGSRC_0 | \ - MDF_DFLTCR_TRGSRC_1 | \ - MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_EXTI11 (MDF_DFLTCR_TRGSRC_2 | \ - MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_EXTI15 (MDF_DFLTCR_TRGSRC_0 | \ - MDF_DFLTCR_TRGSRC_2 | \ - MDF_DFLTCR_TRGSRC_3) -#define MDF_FILTER_TRIG_LPTIM1_OUT (MDF_DFLTCR_TRGSRC_1 | \ - MDF_DFLTCR_TRGSRC_2 | \ - MDF_DFLTCR_TRGSRC_3) /*!< @note Not available for ADF instance */ -#define MDF_FILTER_TRIG_ADF_TRGO MDF_DFLTCR_TRGSRC /*!< @note Not available for ADF instance */ -/** - * @} - */ - -/** @defgroup MDF_FilterTriggerEdge MDF filter trigger edge - * @{ - */ -#define MDF_FILTER_TRIG_RISING_EDGE 0x00000000U /*!< Rising edge */ -#define MDF_FILTER_TRIG_FALLING_EDGE MDF_DFLTCR_TRGSENS /*!< Falling edge */ -/** - * @} - */ - -/** @defgroup MDF_DataSource MDF data source - * @{ - */ -#define MDF_DATA_SOURCE_BSMX 0x00000000U /*!< Data from bitstream matrix */ -#define MDF_DATA_SOURCE_ADCITF1 MDF_DFLTCICR_DATSRC_1 /*!< Data from ADC interface 1. - @note Not available for ADF instance */ -#if defined(ADC2) -#define MDF_DATA_SOURCE_ADCITF2 MDF_DFLTCICR_DATSRC /*!< Data from ADC interface 2. - @note Not available for ADF instance */ -#endif /* ADC2 */ -/** - * @} - */ - -/** @defgroup MDF_CicMode MDF CIC mode - * @{ - */ -#define MDF_TWO_FILTERS_MCIC_FASTSINC 0x00000000U /*!< Two filters, main filter in FastSinc order. - @note Not available for ADF instance */ -#define MDF_TWO_FILTERS_MCIC_SINC1 MDF_DFLTCICR_CICMOD_0 /*!< Two filters, main filter in Sinc1 order. - @note Not available for ADF instance */ -#define MDF_TWO_FILTERS_MCIC_SINC2 MDF_DFLTCICR_CICMOD_1 /*!< Two filters, main filter in Sinc2 order. - @note Not available for ADF instance */ -#define MDF_TWO_FILTERS_MCIC_SINC3 (MDF_DFLTCICR_CICMOD_0 | \ - MDF_DFLTCICR_CICMOD_1) /*!< Two filters, main filter in Sinc3 order. - @note Not available for ADF instance */ -#define MDF_ONE_FILTER_SINC4 MDF_DFLTCICR_CICMOD_2 /*!< One filter in Sinc4 order */ -#define MDF_ONE_FILTER_SINC5 (MDF_DFLTCICR_CICMOD_0 | \ - MDF_DFLTCICR_CICMOD_2) /*!< One filter in Sinc5 order */ -/** - * @} - */ - -/** @defgroup MDF_AcquisitionMode MDF acquisition mode - * @{ - */ -#define MDF_MODE_ASYNC_CONT 0x00000000U /*!< Asynchronous, continuous acquisition mode */ -#define MDF_MODE_ASYNC_SINGLE MDF_DFLTCR_ACQMOD_0 /*!< Asynchronous, single-shot acquisition mode. - @note Not available for ADF instance with SAD usage */ -#define MDF_MODE_SYNC_CONT MDF_DFLTCR_ACQMOD_1 /*!< Synchronous, continuous acquisition mode */ -#define MDF_MODE_SYNC_SINGLE (MDF_DFLTCR_ACQMOD_0 | \ - MDF_DFLTCR_ACQMOD_1) /*!< Synchronous, single-shot acquisition mode. - @note Not available for ADF instance with SAD usage*/ -#define MDF_MODE_WINDOW_CONT MDF_DFLTCR_ACQMOD_2 /*!< Window, continuous acquisition mode. - @note Not available for ADF instance with SAD usage*/ -#define MDF_MODE_SYNC_SNAPSHOT (MDF_DFLTCR_ACQMOD_0 | \ - MDF_DFLTCR_ACQMOD_2) /*!< Synchronous, snapshot acquisition mode. - @note Not available for ADF instance */ -/** - * @} - */ - -/** @defgroup MDF_FifoThreshold MDF RXFIFO threshold - * @{ - */ -#define MDF_FIFO_THRESHOLD_NOT_EMPTY 0x00000000U /*!< Event generated when RXFIFO is not empty */ -#define MDF_FIFO_THRESHOLD_HALF_FULL MDF_DFLTCR_FTH /*!< Event generated when RXFIFO is half_full */ -/** - * @} - */ - -/** @defgroup MDF_SnapshotFormat MDF snapshot format - * @{ - */ -#define MDF_SNAPSHOT_23BITS 0x00000000U /*!< Snapshot data resolution of 23 bits */ -#define MDF_SNAPSHOT_16BITS MDF_DFLTCR_SNPSFMT /*!< Snapshot data resolution of 16 bits */ -/** - * @} - */ - -/** @defgroup MDF_BreakSignals MDF break signals - * @{ - */ -#define MDF_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ -#define MDF_TIM1_BREAK_SIGNAL 0x00000001U /*!< TIM1_BREAK signal */ -#define MDF_TIM1_BREAK2_SIGNAL 0x00000002U /*!< TIM1_BREAK2 signal */ -#define MDF_TIM8_BREAK_SIGNAL 0x00000004U /*!< TIM8_BREAK signal */ -#define MDF_TIM8_BREAK2_SIGNAL 0x00000008U /*!< TIM8_BREAK2 signal */ -/** - * @} - */ - -/** @defgroup MDF_OldCicMode MDF out-off limit detector CIC mode - * @{ - */ -#define MDF_OLD_FILTER_FASTSINC 0x00000000U /*!< Out-off limit detector filter in FastSinc order */ -#define MDF_OLD_FILTER_SINC1 MDF_OLDCR_ACICN_0 /*!< Out-off limit detector filter in Sinc1 order */ -#define MDF_OLD_FILTER_SINC2 MDF_OLDCR_ACICN_1 /*!< Out-off limit detector filter in Sinc2 order */ -#define MDF_OLD_FILTER_SINC3 MDF_OLDCR_ACICN /*!< Out-off limit detector filter in Sinc3 order */ -/** - * @} - */ - -/** @defgroup MDF_OldEventConfig MDF out-off limit detector event configuration - * @{ - */ -#define MDF_OLD_SIGNAL_OUTSIDE_THRESHOLDS 0x00000000U /*!< Out-off limit detector event is generated - if signal is outside thresholds */ -#define MDF_OLD_SIGNAL_IN_THRESHOLDS MDF_OLDCR_THINB /*!< Out-off limit detector event is generated - if signal is in thresholds */ -/** - * @} - */ - -/** @defgroup MDF_OldThresholdInfo MDF out-off limit detector threshold information - * @{ - */ -#define MDF_OLD_IN_THRESHOLDS 0x00000000U /*!< The signal was in thresholds when out-off limit detection occurs */ -#define MDF_OLD_HIGH_THRESHOLD 0x00000001U /*!< The signal was higher than high threshold - when out-off limit detection occurs */ -#define MDF_OLD_LOW_THRESHOLD 0x00000002U /*!< The signal was lower than low threshold - when out-off limit detection occurs */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup MDF_Exported_Macros MDF Exported Macros - * @{ - */ - -/** @brief Reset MDF handle state. - * @param __HANDLE__ MDF handle. - * @retval None - */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) -#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_MDF_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ -#define __HAL_MDF_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDF_STATE_RESET) -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup MDF_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -/** @addtogroup MDF_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf); -void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf); -void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf); -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf, - HAL_MDF_CallbackIDTypeDef CallbackID, - pMDF_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf, - HAL_MDF_CallbackIDTypeDef CallbackID); -HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef *hmdf, - pMDF_OldCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf, - pMDF_SndLvlCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Acquisition functions *****************************************************/ -/** @addtogroup MDF_Exported_Functions_Group2 - * @{ - */ -HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig); -HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout); -HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout); -HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue); -HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam); -HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig); -HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig, - const MDF_DmaConfigTypeDef *pDmaConfig); -HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay); -HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay); -HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain); -HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain); -HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset); -HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset); -HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel, - uint32_t *pAmbientNoise); -HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout); -void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf); -void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf); -void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise); -void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf); -/** - * @} - */ - -/* Clock absence detection functions *****************************************/ -/** @addtogroup MDF_Exported_Functions_Group3 - * @{ - */ -HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout); -HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf); -/** - * @} - */ - -/* Short circuit detection functions *****************************************/ -/** @addtogroup MDF_Exported_Functions_Group4 - * @{ - */ -HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig); -HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout); -HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig); -HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf); -/** - * @} - */ - -/* Out-off limit detection functions *****************************************/ -/** @addtogroup MDF_Exported_Functions_Group5 - * @{ - */ -HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig); -HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo); -HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf); -HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig); -HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf); -void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo); -/** - * @} - */ - -/* Generic functions *********************************************************/ -/** @addtogroup MDF_Exported_Functions_Group6 - * @{ - */ -void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf); -void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf); -HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf); -uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup MDF_Private_Macros MDF Private Macros - * @{ - */ -#if defined(STM32U535xx) || defined(STM32U545xx) -#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ - ((PARAM) == MDF1_Filter1)) -#else /* defined(STM32U535xx) || defined(STM32U545xx) */ -#define IS_MDF_INSTANCE(PARAM) (((PARAM) == MDF1_Filter0) || \ - ((PARAM) == MDF1_Filter1) || \ - ((PARAM) == MDF1_Filter2) || \ - ((PARAM) == MDF1_Filter3) || \ - ((PARAM) == MDF1_Filter4) || \ - ((PARAM) == MDF1_Filter5)) -#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ - -#define IS_ADF_INSTANCE(PARAM) ((PARAM) == ADF1_Filter0) - -#if defined(STM32U535xx) || defined(STM32U545xx) -#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ - ((PARAM) == MDF_BITSTREAM0_FALLING) || \ - ((PARAM) == MDF_BITSTREAM1_RISING) || \ - ((PARAM) == MDF_BITSTREAM1_FALLING)) -#else /* defined(STM32U535xx) || defined(STM32U545xx) */ -#define IS_MDF_FILTER_BITSTREAM(PARAM) (((PARAM) == MDF_BITSTREAM0_RISING) || \ - ((PARAM) == MDF_BITSTREAM0_FALLING) || \ - ((PARAM) == MDF_BITSTREAM1_RISING) || \ - ((PARAM) == MDF_BITSTREAM1_FALLING) || \ - ((PARAM) == MDF_BITSTREAM2_RISING) || \ - ((PARAM) == MDF_BITSTREAM2_FALLING) || \ - ((PARAM) == MDF_BITSTREAM3_RISING) || \ - ((PARAM) == MDF_BITSTREAM3_FALLING) || \ - ((PARAM) == MDF_BITSTREAM4_RISING) || \ - ((PARAM) == MDF_BITSTREAM4_FALLING) || \ - ((PARAM) == MDF_BITSTREAM5_RISING) || \ - ((PARAM) == MDF_BITSTREAM5_FALLING)) -#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ - -#if defined(STM32U535xx) || defined(STM32U545xx) -#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 1U) -#else /* defined(STM32U535xx) || defined(STM32U545xx) */ -#define IS_MDF_INTERLEAVED_FILTERS(PARAM) ((PARAM) <= 5U) -#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ - -#define IS_MDF_PROC_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 128U)) - -#define IS_MDF_OUTPUT_CLOCK_PINS(PARAM) (((PARAM) == MDF_OUTPUT_CLOCK_0) || \ - ((PARAM) == MDF_OUTPUT_CLOCK_1) || \ - ((PARAM) == MDF_OUTPUT_CLOCK_ALL)) - -#define IS_MDF_OUTPUT_CLOCK_DIVIDER(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 16U)) - -#define IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM1_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM1_TRGO2) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM8_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM8_TRGO2) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM3_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM4_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM16_OC1) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM6_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_TIM7_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_SAD_DET) || \ - ((PARAM) == MDF_CLOCK_TRIG_EXTI11) || \ - ((PARAM) == MDF_CLOCK_TRIG_EXTI15) || \ - ((PARAM) == MDF_CLOCK_TRIG_LPTIM1_OUT) || \ - ((PARAM) == MDF_CLOCK_TRIG_SAD_TRGO)) - -#define IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_TRGO) || \ - ((PARAM) == MDF_CLOCK_TRIG_EXTI15)) - -#define IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_CLOCK_TRIG_RISING_EDGE) || \ - ((PARAM) == MDF_CLOCK_TRIG_FALLING_EDGE)) - -#define IS_MDF_SITF_MODE(PARAM) (((PARAM) == MDF_SITF_LF_MASTER_SPI_MODE) || \ - ((PARAM) == MDF_SITF_NORMAL_SPI_MODE) || \ - ((PARAM) == MDF_SITF_MANCHESTER_FALLING_MODE) || \ - ((PARAM) == MDF_SITF_MANCHESTER_RISING_MODE)) - -#define IS_MDF_SITF_CLOCK_SOURCE(PARAM) (((PARAM) == MDF_SITF_CCK0_SOURCE) || \ - ((PARAM) == MDF_SITF_CCK1_SOURCE) || \ - ((PARAM) == MDF_SITF_CKI_SOURCE)) - -#define IS_MDF_SITF_THRESHOLD(PARAM) ((4U <= (PARAM)) && ((PARAM) <= 31U)) - -#define IS_MDF_CIC_MODE(PARAM) (((PARAM) == MDF_TWO_FILTERS_MCIC_FASTSINC) || \ - ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC1) || \ - ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC2) || \ - ((PARAM) == MDF_TWO_FILTERS_MCIC_SINC3) || \ - ((PARAM) == MDF_ONE_FILTER_SINC4) || \ - ((PARAM) == MDF_ONE_FILTER_SINC5)) - -#define IS_ADF_CIC_MODE(PARAM) (((PARAM) == MDF_ONE_FILTER_SINC4) || \ - ((PARAM) == MDF_ONE_FILTER_SINC5)) - -#define IS_MDF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT) || \ - ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \ - ((PARAM) == MDF_MODE_SYNC_CONT) || \ - ((PARAM) == MDF_MODE_SYNC_SINGLE) || \ - ((PARAM) == MDF_MODE_WINDOW_CONT) || \ - ((PARAM) == MDF_MODE_SYNC_SNAPSHOT)) - -#define IS_ADF_ACQUISITION_MODE(PARAM) (((PARAM) == MDF_MODE_ASYNC_CONT) || \ - ((PARAM) == MDF_MODE_ASYNC_SINGLE) || \ - ((PARAM) == MDF_MODE_SYNC_CONT) || \ - ((PARAM) == MDF_MODE_SYNC_SINGLE) || \ - ((PARAM) == MDF_MODE_WINDOW_CONT)) - -#define IS_MDF_DISCARD_SAMPLES(PARAM) ((PARAM) <= 255U) - -#define IS_MDF_FIFO_THRESHOLD(PARAM) (((PARAM) == MDF_FIFO_THRESHOLD_NOT_EMPTY) || \ - ((PARAM) == MDF_FIFO_THRESHOLD_HALF_FULL)) - -#define IS_MDF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_OLD_EVENT) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM1_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM1_TRGO2) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM8_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM8_TRGO2) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM3_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM4_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM16_OC1) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM6_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_TIM7_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_ADF_SAD_DET) || \ - ((PARAM) == MDF_FILTER_TRIG_EXTI11) || \ - ((PARAM) == MDF_FILTER_TRIG_EXTI15) || \ - ((PARAM) == MDF_FILTER_TRIG_LPTIM1_OUT) || \ - ((PARAM) == MDF_FILTER_TRIG_ADF_TRGO)) - -#define IS_ADF_TRIGGER_SOURCE(PARAM) (((PARAM) == MDF_FILTER_TRIG_TRGO) || \ - ((PARAM) == MDF_FILTER_TRIG_EXTI15)) - -#define IS_MDF_TRIGGER_EDGE(PARAM) (((PARAM) == MDF_FILTER_TRIG_RISING_EDGE) || \ - ((PARAM) == MDF_FILTER_TRIG_FALLING_EDGE)) - -#define IS_MDF_SNAPSHOT_FORMAT(PARAM) (((PARAM) == MDF_SNAPSHOT_23BITS) || \ - ((PARAM) == MDF_SNAPSHOT_16BITS)) - -#if defined(ADC2) -#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \ - ((PARAM) == MDF_DATA_SOURCE_ADCITF1) || \ - ((PARAM) == MDF_DATA_SOURCE_ADCITF2)) -#else /* ADC2 */ -#define IS_MDF_DATA_SOURCE(PARAM) (((PARAM) == MDF_DATA_SOURCE_BSMX) || \ - ((PARAM) == MDF_DATA_SOURCE_ADCITF1)) -#endif /* ADC2 */ - -#define IS_ADF_DATA_SOURCE(PARAM) ((PARAM) == MDF_DATA_SOURCE_BSMX) - -#define IS_MDF_DECIMATION_RATIO(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 512U)) - -#define IS_MDF_GAIN(PARAM) ((-16 <= (PARAM)) && ((PARAM) <= 24)) - -#define IS_MDF_DELAY(PARAM) ((PARAM) <= 127U) - -#define IS_MDF_OFFSET(PARAM) ((-33554432 <= (PARAM)) && ((PARAM) <= 33554431)) - -#define IS_MDF_RSF_DECIMATION_RATIO(PARAM) (((PARAM) == MDF_RSF_DECIMATION_RATIO_4) || \ - ((PARAM) == MDF_RSF_DECIMATION_RATIO_1)) - -#define IS_MDF_HPF_CUTOFF_FREQ(PARAM) (((PARAM) == MDF_HPF_CUTOFF_0_000625FPCM) || \ - ((PARAM) == MDF_HPF_CUTOFF_0_00125FPCM) || \ - ((PARAM) == MDF_HPF_CUTOFF_0_0025FPCM) || \ - ((PARAM) == MDF_HPF_CUTOFF_0_0095FPCM)) - -#define IS_MDF_INTEGRATOR_VALUE(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 128U)) - -#define IS_MDF_INTEGRATOR_OUTPUT_DIV(PARAM) (((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_128) || \ - ((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_32) || \ - ((PARAM) == MDF_INTEGRATOR_OUTPUT_DIV_4) || \ - ((PARAM) == MDF_INTEGRATOR_OUTPUT_NO_DIV)) - -#define IS_MDF_SAD_MODE(PARAM) (((PARAM) == MDF_SAD_VOICE_ACTIVITY_DETECTOR) || \ - ((PARAM) == MDF_SAD_SOUND_DETECTOR) || \ - ((PARAM) == MDF_SAD_AMBIENT_NOISE_DETECTOR)) - -#define IS_MDF_SAD_FRAME_SIZE(PARAM) (((PARAM) == MDF_SAD_8_PCM_SAMPLES) || \ - ((PARAM) == MDF_SAD_16_PCM_SAMPLES) || \ - ((PARAM) == MDF_SAD_32_PCM_SAMPLES) || \ - ((PARAM) == MDF_SAD_64_PCM_SAMPLES) || \ - ((PARAM) == MDF_SAD_128_PCM_SAMPLES) || \ - ((PARAM) == MDF_SAD_256_PCM_SAMPLES) || \ - ((PARAM) == MDF_SAD_512_PCM_SAMPLES)) - -#define IS_MDF_SAD_SOUND_TRIGGER(PARAM) (((PARAM) == MDF_SAD_ENTER_DETECT) || \ - ((PARAM) == MDF_SAD_ENTER_EXIT_DETECT)) - -#define IS_MDF_SAD_DATA_MEMORY_TRANSFER(PARAM) (((PARAM) == MDF_SAD_NO_MEMORY_TRANSFER) || \ - ((PARAM) == MDF_SAD_MEMORY_TRANSFER_IN_DETECT) || \ - ((PARAM) == MDF_SAD_MEMORY_TRANSFER_ALWAYS)) - -#define IS_MDF_SAD_MIN_NOISE_LEVEL(PARAM) ((PARAM) <= 8191U) - -#define IS_MDF_SAD_HANGOVER_WINDOW(PARAM) (((PARAM) == MDF_SAD_HANGOVER_4_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_8_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_16_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_32_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_64_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_128_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_256_FRAMES) || \ - ((PARAM) == MDF_SAD_HANGOVER_512_FRAMES)) - -#define IS_MDF_SAD_LEARNING_FRAMES(PARAM) (((PARAM) == MDF_SAD_LEARNING_2_FRAMES) || \ - ((PARAM) == MDF_SAD_LEARNING_4_FRAMES) || \ - ((PARAM) == MDF_SAD_LEARNING_8_FRAMES) || \ - ((PARAM) == MDF_SAD_LEARNING_16_FRAMES) || \ - ((PARAM) == MDF_SAD_LEARNING_32_FRAMES)) - -#define IS_MDF_SAD_AMBIENT_NOISE_SLOPE(PARAM) ((PARAM) <= 7U) - -#define IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(PARAM) (((PARAM) == MDF_SAD_SIGNAL_NOISE_3_5DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_6DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_9_5DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_12DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_15_6DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_18DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_21_6DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_24_1DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_27_6DB) || \ - ((PARAM) == MDF_SAD_SIGNAL_NOISE_30_1DB)) - -#define IS_MDF_SCD_THRESHOLD(PARAM) ((2U <= (PARAM)) && ((PARAM) <= 256U)) - -#define IS_MDF_BREAK_SIGNAL(PARAM) ((PARAM) <= 15U) - -#define IS_MDF_OLD_CIC_MODE(PARAM) (((PARAM) == MDF_OLD_FILTER_FASTSINC) || \ - ((PARAM) == MDF_OLD_FILTER_SINC1) || \ - ((PARAM) == MDF_OLD_FILTER_SINC2) || \ - ((PARAM) == MDF_OLD_FILTER_SINC3)) - -#define IS_MDF_OLD_DECIMATION_RATIO(PARAM) ((1U <= (PARAM)) && ((PARAM) <= 32U)) - -#define IS_MDF_OLD_THRESHOLD(PARAM) ((-33554432 <= (PARAM)) && ((PARAM) <= 33554431)) - -#define IS_MDF_OLD_EVENT_CONFIG(PARAM) (((PARAM) == MDF_OLD_SIGNAL_OUTSIDE_THRESHOLDS) || \ - ((PARAM) == MDF_OLD_SIGNAL_IN_THRESHOLDS)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_MDF_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h deleted file mode 100644 index b63abb767..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_ospi.h +++ /dev/null @@ -1,1099 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_ospi.h - * @author MCD Application Team - * @brief Header file of OSPI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_OSPI_H -#define STM32U5xx_HAL_OSPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" -#include "stm32u5xx_ll_dlyb.h" - -#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup OSPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup OSPI_Exported_Types OSPI Exported Types - * @{ - */ -#define HAL_OSPI_DLYB_CfgTypeDef LL_DLYB_CfgTypeDef - -/** - * @brief OSPI Init structure definition - */ -typedef struct -{ - uint32_t FifoThreshold; /*!< This is the threshold used by the Peripheral to generate the interrupt - indicating that data are available in reception or free place - is available in transmission. - This parameter can be a value between 1 and 32 */ - uint32_t DualQuad; /*!< It enables or not the dual-quad mode which allow to access up to - quad mode on two different devices to increase the throughput. - This parameter can be a value of @ref OSPI_DualQuad */ - uint32_t MemoryType; /*!< It indicates the external device type connected to the OSPI. - This parameter can be a value of @ref OSPI_MemoryType */ - uint32_t DeviceSize; /*!< It defines the size of the external device connected to the OSPI, - it corresponds to the number of address bits required to access - the external device. - This parameter can be a value between 1 and 32 */ - uint32_t ChipSelectHighTime; /*!< It defines the minimum number of clocks which the chip select - must remain high between commands. - This parameter can be a value between 1 and 8 */ - uint32_t FreeRunningClock; /*!< It enables or not the free running clock. - This parameter can be a value of @ref OSPI_FreeRunningClock */ - uint32_t ClockMode; /*!< It indicates the level of clock when the chip select is released. - This parameter can be a value of @ref OSPI_ClockMode */ - uint32_t WrapSize; /*!< It indicates the wrap-size corresponding the external device configuration. - This parameter can be a value of @ref OSPI_WrapSize */ - uint32_t ClockPrescaler; /*!< It specifies the prescaler factor used for generating - the external clock based on the AHB clock. - This parameter can be a value between 1 and 256 */ - uint32_t SampleShifting; /*!< It allows to delay to 1/2 cycle the data sampling in order - to take in account external signal delays. - This parameter can be a value of @ref OSPI_SampleShifting */ - uint32_t DelayHoldQuarterCycle; /*!< It allows to hold to 1/4 cycle the data. - This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ - uint32_t ChipSelectBoundary; /*!< It enables the transaction boundary feature and - defines the boundary of bytes to release the chip select. - This parameter can be a value between 0 and 31 */ - uint32_t DelayBlockBypass; /*!< It enables the delay block bypass, so the sampling is not affected - by the delay block. - This parameter can be a value of @ref OSPI_DelayBlockBypass */ - uint32_t MaxTran; /*!< It enables the communication regulation feature. The chip select is - released every MaxTran+1 bytes when the other OctoSPI request the access - to the bus. - This parameter can be a value between 0 and 255 */ - uint32_t Refresh; /*!< It enables the refresh rate feature. The chip select is released every - Refresh+1 clock cycles. - This parameter can be a value between 0 and 0xFFFFFFFF */ -} OSPI_InitTypeDef; - -/** - * @brief HAL OSPI Handle Structure definition - */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) -typedef struct __OSPI_HandleTypeDef -#else -typedef struct -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ -{ - OCTOSPI_TypeDef *Instance; /*!< OSPI registers base address */ - OSPI_InitTypeDef Init; /*!< OSPI initialization parameters */ - uint8_t *pBuffPtr; /*!< Address of the OSPI buffer for transfer */ - __IO uint32_t XferSize; /*!< Number of data to transfer */ - __IO uint32_t XferCount; /*!< Counter of data transferred */ - DMA_HandleTypeDef *hdma; /*!< Handle of the DMA channel used for the transfer */ - __IO uint32_t State; /*!< Internal state of the OSPI HAL driver */ - __IO uint32_t ErrorCode; /*!< Error code in case of HAL driver internal error */ - uint32_t Timeout; /*!< Timeout used for the OSPI external device access */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - void (* ErrorCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* AbortCpltCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* CmdCpltCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* RxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* TxCpltCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* RxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* TxHalfCpltCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* StatusMatchCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* TimeOutCallback)(struct __OSPI_HandleTypeDef *hospi); - - void (* MspInitCallback)(struct __OSPI_HandleTypeDef *hospi); - void (* MspDeInitCallback)(struct __OSPI_HandleTypeDef *hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ -} OSPI_HandleTypeDef; - -/** - * @brief HAL OSPI Regular Command Structure definition - */ -typedef struct -{ - uint32_t OperationType; /*!< It indicates if the configuration applies to the common registers or - to the registers for the write operation (these registers are only - used for memory-mapped mode). - This parameter can be a value of @ref OSPI_OperationType */ - uint32_t FlashId; /*!< It indicates which external device is selected for this command (it - applies only if Dualquad is disabled in the initialization structure). - This parameter can be a value of @ref OSPI_FlashID */ - uint32_t Instruction; /*!< It contains the instruction to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t InstructionMode; /*!< It indicates the mode of the instruction. - This parameter can be a value of @ref OSPI_InstructionMode */ - uint32_t InstructionSize; /*!< It indicates the size of the instruction. - This parameter can be a value of @ref OSPI_InstructionSize */ - uint32_t InstructionDtrMode; /*!< It enables or not the DTR mode for the instruction phase. - This parameter can be a value of @ref OSPI_InstructionDtrMode */ - uint32_t Address; /*!< It contains the address to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AddressMode; /*!< It indicates the mode of the address. - This parameter can be a value of @ref OSPI_AddressMode */ - uint32_t AddressSize; /*!< It indicates the size of the address. - This parameter can be a value of @ref OSPI_AddressSize */ - uint32_t AddressDtrMode; /*!< It enables or not the DTR mode for the address phase. - This parameter can be a value of @ref OSPI_AddressDtrMode */ - uint32_t AlternateBytes; /*!< It contains the alternate bytes to be sent to the device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AlternateBytesMode; /*!< It indicates the mode of the alternate bytes. - This parameter can be a value of @ref OSPI_AlternateBytesMode */ - uint32_t AlternateBytesSize; /*!< It indicates the size of the alternate bytes. - This parameter can be a value of @ref OSPI_AlternateBytesSize */ - uint32_t AlternateBytesDtrMode; /*!< It enables or not the DTR mode for the alternate bytes phase. - This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ - uint32_t DataMode; /*!< It indicates the mode of the data. - This parameter can be a value of @ref OSPI_DataMode */ - uint32_t NbData; /*!< It indicates the number of data transferred with this command. - This field is only used for indirect mode. - This parameter can be a value between 1 and 0xFFFFFFFF */ - uint32_t DataDtrMode; /*!< It enables or not the DTR mode for the data phase. - This parameter can be a value of @ref OSPI_DataDtrMode */ - uint32_t DummyCycles; /*!< It indicates the number of dummy cycles inserted before data phase. - This parameter can be a value between 0 and 31 */ - uint32_t DQSMode; /*!< It enables or not the data strobe management. - This parameter can be a value of @ref OSPI_DQSMode */ - uint32_t SIOOMode; /*!< It enables or not the SIOO mode. - This parameter can be a value of @ref OSPI_SIOOMode */ -} OSPI_RegularCmdTypeDef; - -/** - * @brief HAL OSPI Hyperbus Configuration Structure definition - */ -typedef struct -{ - uint32_t RWRecoveryTime; /*!< It indicates the number of cycles for the device read write recovery time. - This parameter can be a value between 0 and 255 */ - uint32_t AccessTime; /*!< It indicates the number of cycles for the device access time. - This parameter can be a value between 0 and 255 */ - uint32_t WriteZeroLatency; /*!< It enables or not the latency for the write access. - This parameter can be a value of @ref OSPI_WriteZeroLatency */ - uint32_t LatencyMode; /*!< It configures the latency mode. - This parameter can be a value of @ref OSPI_LatencyMode */ -} OSPI_HyperbusCfgTypeDef; - -/** - * @brief HAL OSPI Hyperbus Command Structure definition - */ -typedef struct -{ - uint32_t AddressSpace; /*!< It indicates the address space accessed by the command. - This parameter can be a value of @ref OSPI_AddressSpace */ - uint32_t Address; /*!< It contains the address to be sent tot he device. - This parameter can be a value between 0 and 0xFFFFFFFF */ - uint32_t AddressSize; /*!< It indicates the size of the address. - This parameter can be a value of @ref OSPI_AddressSize */ - uint32_t NbData; /*!< It indicates the number of data transferred with this command. - This field is only used for indirect mode. - This parameter can be a value between 1 and 0xFFFFFFFF - In case of autopolling mode, this parameter can be any value between 1 and 4 */ - uint32_t DQSMode; /*!< It enables or not the data strobe management. - This parameter can be a value of @ref OSPI_DQSMode */ -} OSPI_HyperbusCmdTypeDef; - -/** - * @brief HAL OSPI Auto Polling mode configuration structure definition - */ -typedef struct -{ - uint32_t Match; /*!< Specifies the value to be compared with the masked status register to get a match. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t Mask; /*!< Specifies the mask to be applied to the status bytes received. - This parameter can be any value between 0 and 0xFFFFFFFF */ - uint32_t MatchMode; /*!< Specifies the method used for determining a match. - This parameter can be a value of @ref OSPI_MatchMode */ - uint32_t AutomaticStop; /*!< Specifies if automatic polling is stopped after a match. - This parameter can be a value of @ref OSPI_AutomaticStop */ - uint32_t Interval; /*!< Specifies the number of clock cycles between two read during automatic polling phases. - This parameter can be any value between 0 and 0xFFFF */ -} OSPI_AutoPollingTypeDef; - -/** - * @brief HAL OSPI Memory Mapped mode configuration structure definition - */ -typedef struct -{ - uint32_t TimeOutActivation; /*!< Specifies if the timeout counter is enabled to release the chip select. - This parameter can be a value of @ref OSPI_TimeOutActivation */ - uint32_t TimeOutPeriod; /*!< Specifies the number of clock to wait when the FIFO is full before to release the chip select. - This parameter can be any value between 0 and 0xFFFF */ -} OSPI_MemoryMappedTypeDef; - -#if defined (OCTOSPIM) -/** - * @brief HAL OSPI IO Manager Configuration structure definition - */ -typedef struct -{ - uint32_t ClkPort; /*!< It indicates which port of the OSPI IO Manager is used for the CLK pins. - This parameter can be a value between 1 and 8 */ - uint32_t DQSPort; /*!< It indicates which port of the OSPI IO Manager is used for the DQS pin. - This parameter can be a value between 0 and 8, 0 means that signal not used */ - uint32_t NCSPort; /*!< It indicates which port of the OSPI IO Manager is used for the NCS pin. - This parameter can be a value between 1 and 8 */ - uint32_t IOLowPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. - This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t IOHighPort; /*!< It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. - This parameter can be a value of @ref OSPIM_IOPort */ - uint32_t Req2AckTime; /*!< It indicates the minimum switching duration (in number of clock cycles) expected - if some signals are multiplexed in the OSPI IO Manager with the other OSPI. - This parameter can be a value between 1 and 256 */ -} OSPIM_CfgTypeDef; -#endif /*(OCTOSPIM)*/ - -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) -/** - * @brief HAL OSPI Callback ID enumeration definition - */ -typedef enum -{ - HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ - HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ - HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ - HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ - HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ - HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ - HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ - HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ - HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ - HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ - - HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ - HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ -} HAL_OSPI_CallbackIDTypeDef; - -/** - * @brief HAL OSPI Callback pointer definition - */ -typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup OSPI_Exported_Constants OSPI Exported Constants - * @{ - */ - -/** @defgroup OSPI_State OSPI State - * @{ - */ -#define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ -#define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ -#define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ -#define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ -#define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ -#define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ -#define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ -#define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ -#define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ -#define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ -#define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ -#define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ -#define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ -/** - * @} - */ - -/** @defgroup OSPI_ErrorCode OSPI Error Code - * @{ - */ -#define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ -#define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ -#define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ -#define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ -#define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) -#define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ -/** - * @} - */ - -/** @defgroup OSPI_DualQuad OSPI Dual-Quad - * @{ - */ -#define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ -#define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DMM) /*!< Dual-Quad mode enabled */ -/** - * @} - */ - -/** @defgroup OSPI_MemoryType OSPI Memory Type - * @{ - */ -#define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ -#define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ -#define HAL_OSPI_MEMTYPE_APMEMORY ((uint32_t)OCTOSPI_DCR1_MTYP_1) /*!< AP Memory mode */ -#define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ -#define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ -/** - * @} - */ - -/** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock - * @{ - */ -#define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ -#define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ -/** - * @} - */ - -/** @defgroup OSPI_ClockMode OSPI Clock Mode - * @{ - */ -#define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ -#define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ -/** - * @} - */ - -/** @defgroup OSPI_WrapSize OSPI Wrap-Size - * @{ - */ -#define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ -#define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ -#define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ -#define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ -#define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ -/** - * @} - */ - -/** @defgroup OSPI_SampleShifting OSPI Sample Shifting - * @{ - */ -#define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ -#define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ -/** - * @} - */ - -/** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle - * @{ - */ -#define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ -#define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ -/** - * @} - */ - -/** @defgroup OSPI_DelayBlockBypass OSPI Delay Block Bypaas - * @{ - */ -#define HAL_OSPI_DELAY_BLOCK_USED ((uint32_t)0x00000000U) /*!< Sampling clock is delayed by the delay block */ -#define HAL_OSPI_DELAY_BLOCK_BYPASSED ((uint32_t)OCTOSPI_DCR1_DLYBYP) /*!< Delay block is bypassed */ -/** - * @} - */ - -/** @defgroup OSPI_OperationType OSPI Operation Type - * @{ - */ -#define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ -#define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ -#define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ -#define HAL_OSPI_OPTYPE_WRAP_CFG ((uint32_t)0x00000003U) /*!< Wrap configuration (memory-mapped mode) */ -/** - * @} - */ - -/** @defgroup OSPI_FlashID OSPI Flash Id - * @{ - */ -#define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ -#define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_MSEL) /*!< FLASH 2 selected */ -/** - * @} - */ - -/** @defgroup OSPI_InstructionMode OSPI Instruction Mode - * @{ - */ -#define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ -#define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ -#define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ -#define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ -#define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ -/** - * @} - */ - -/** @defgroup OSPI_InstructionSize OSPI Instruction Size - * @{ - */ -#define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ -#define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ -#define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ -#define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ -/** - * @} - */ - -/** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode - * @{ - */ -#define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ -#define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ -/** - * @} - */ - -/** @defgroup OSPI_AddressMode OSPI Address Mode - * @{ - */ -#define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ -#define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ -#define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ -#define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ -#define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ -/** - * @} - */ - -/** @defgroup OSPI_AddressSize OSPI Address Size - * @{ - */ -#define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ -#define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ -#define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ -#define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ -/** - * @} - */ - -/** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode - * @{ - */ -#define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ -#define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ -/** - * @} - */ - -/** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode - * @{ - */ -#define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ -#define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ -#define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ -#define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ -#define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ -/** - * @} - */ - -/** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size - * @{ - */ -#define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ -#define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ -#define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ -#define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ -/** - * @} - */ - -/** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode - * @{ - */ -#define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ -#define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ -/** - * @} - */ - -/** @defgroup OSPI_DataMode OSPI Data Mode - * @{ - */ -#define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ -#define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ -#define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ -#define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ -#define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ -/** - * @} - */ - -/** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode - * @{ - */ -#define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ -#define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ -/** - * @} - */ - -/** @defgroup OSPI_DQSMode OSPI DQS Mode - * @{ - */ -#define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ -#define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ -/** - * @} - */ - -/** @defgroup OSPI_SIOOMode OSPI SIOO Mode - * @{ - */ -#define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ -#define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ -/** - * @} - */ - -/** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation - * @{ - */ -#define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ -#define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ -/** - * @} - */ - -/** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode - * @{ - */ -#define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ -#define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ -/** - * @} - */ - -/** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space - * @{ - */ -#define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ -#define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ -/** - * @} - */ - -/** @defgroup OSPI_MatchMode OSPI Match Mode - * @{ - */ -#define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ -#define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ -/** - * @} - */ - -/** @defgroup OSPI_AutomaticStop OSPI Automatic Stop - * @{ - */ -#define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ -#define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ -/** - * @} - */ - -/** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation - * @{ - */ -#define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ -#define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ -/** - * @} - */ - -/** @defgroup OSPI_Flags OSPI Flags - * @{ - */ -#define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ -#define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ -#define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ -#define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ -#define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ -#define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ -/** - * @} - */ - -/** @defgroup OSPI_Interrupts OSPI Interrupts - * @{ - */ -#define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ -#define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ -#define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ -#define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ -#define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ -/** - * @} - */ - -/** @defgroup OSPI_Timeout_definition OSPI Timeout definition - * @{ - */ -#define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ -/** - * @} - */ - -#if defined (OCTOSPIM) -/** @defgroup OSPI_IO_Manger_IOPort OSPI IO Manager IO Port - * @{ - */ -#define HAL_OSPIM_IOPORT_NONE ((uint32_t)0x00000000U) /*!< IOs not used */ -#define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1U)) /*!< Port 1 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1U)) /*!< Port 1 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2U)) /*!< Port 2 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2U)) /*!< Port 2 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_3_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x3U)) /*!< Port 3 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_3_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x3U)) /*!< Port 3 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_4_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x4U)) /*!< Port 4 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_4_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x4U)) /*!< Port 4 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_5_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x5U)) /*!< Port 5 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_5_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x5U)) /*!< Port 5 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_6_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x6U)) /*!< Port 6 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_6_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x6U)) /*!< Port 6 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_7_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x7U)) /*!< Port 7 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_7_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x7U)) /*!< Port 7 - IO[7:4] */ -#define HAL_OSPIM_IOPORT_8_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x8U)) /*!< Port 8 - IO[3:0] */ -#define HAL_OSPIM_IOPORT_8_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x8U)) /*!< Port 8 - IO[7:4] */ -/** - * @} - */ -#endif /*(OCTOSPIM)*/ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup OSPI_Exported_Macros OSPI Exported Macros - * @{ - */ -/** @brief Reset OSPI handle state. - * @param __HANDLE__ specifies the OSPI Handle. - * @retval None - */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) -#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - -/** @brief Enable the OSPI peripheral. - * @param __HANDLE__ specifies the OSPI Handle. - * @retval None - */ -#define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) - -/** @brief Disable the OSPI peripheral. - * @param __HANDLE__ specifies the OSPI Handle. - * @retval None - */ -#define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) - -/** @brief Enable the specified OSPI interrupt. - * @param __HANDLE__ specifies the OSPI Handle. - * @param __INTERRUPT__ specifies the OSPI interrupt source to enable. - * This parameter can be one of the following values: - * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt - * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt - * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt - * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt - * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt - * @retval None - */ -#define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) - - -/** @brief Disable the specified OSPI interrupt. - * @param __HANDLE__ specifies the OSPI Handle. - * @param __INTERRUPT__ specifies the OSPI interrupt source to disable. - * This parameter can be one of the following values: - * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt - * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt - * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt - * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt - * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt - * @retval None - */ -#define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) - -/** @brief Check whether the specified OSPI interrupt source is enabled or not. - * @param __HANDLE__ specifies the OSPI Handle. - * @param __INTERRUPT__ specifies the OSPI interrupt source to check. - * This parameter can be one of the following values: - * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt - * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt - * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt - * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt - * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__))\ - == (__INTERRUPT__)) - -/** - * @brief Check whether the selected OSPI flag is set or not. - * @param __HANDLE__ specifies the OSPI Handle. - * @param __FLAG__ specifies the OSPI flag to check. - * This parameter can be one of the following values: - * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag - * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag - * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag - * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag - * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag - * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag - * @retval None - */ -#define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) \ - != 0U) ? SET : RESET) - -/** @brief Clears the specified OSPI's flag status. - * @param __HANDLE__ specifies the OSPI Handle. - * @param __FLAG__ specifies the OSPI clear register flag that needs to be set - * This parameter can be one of the following values: - * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag - * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag - * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag - * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag - * @retval None - */ -#define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup OSPI_Exported_Functions OSPI Exported Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi); -HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi); - -/** - * @} - */ - -/* IO operation functions *****************************************************/ -/** @addtogroup OSPI_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -/* OSPI IRQ handler function */ -void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi); - -/* OSPI command configuration functions */ -HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); -HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); - -/* OSPI indirect mode functions */ -HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); -HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData); - -/* OSPI status flag polling mode functions */ -HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); -HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); - -/* OSPI memory-mapped mode functions */ -HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); - -/* Callback functions in non-blocking modes ***********************************/ -void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); - -/* OSPI indirect mode functions */ -void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi); -void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi); - -/* OSPI status flag polling mode functions */ -void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi); - -/* OSPI memory-mapped mode functions */ -void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi); - -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) -/* OSPI callback registering/unregistering */ -HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, - pOSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ -/** - * @} - */ - -/* Peripheral Control and State functions ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @{ - */ -HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi); -HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi); -HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold); -uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi); -HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout); -uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi); -uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); - -/** - * @} - */ - -#if defined (OCTOSPIM) -/* OSPI IO Manager configuration function ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group4 IO Manager configuration function - * @{ - */ -HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); - -/** - * @} - */ - -#endif /*(OCTOSPIM)*/ - -/* OSPI Delay Block function ************************************/ -/** @addtogroup OSPI_Exported_Functions_Group5 Delay Block function - * @{ - */ -HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); -HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); -HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg); - -/** - * @} - */ -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** - @cond 0 - */ -#define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) - -#define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ - ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) - -#define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ - ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ - ((TYPE) == HAL_OSPI_MEMTYPE_APMEMORY) || \ - ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX_RAM) || \ - ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) - -#define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) - -#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) - -#define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ - ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) - -#define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ - ((MODE) == HAL_OSPI_CLOCK_MODE_3)) - -#define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ - ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ - ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ - ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ - ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) - -#define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) - -#define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ - ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) - -#define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ - ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) - -#define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ - ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ - ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG) || \ - ((TYPE) == HAL_OSPI_OPTYPE_WRAP_CFG)) - -#define IS_OSPI_FLASH_ID(FLASHID) (((FLASHID) == HAL_OSPI_FLASH_ID_1) || \ - ((FLASHID) == HAL_OSPI_FLASH_ID_2)) - -#define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ - ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ - ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ - ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ - ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) - -#define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ - ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ - ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ - ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) - -#define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ - ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) - -#define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ - ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ - ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ - ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ - ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) - -#define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ - ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ - ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ - ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) - -#define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ - ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) - -#define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ - ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ - ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ - ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ - ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) - -#define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ - ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ - ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ - ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) - -#define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ - ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) - -#define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ - ((MODE) == HAL_OSPI_DATA_1_LINE) || \ - ((MODE) == HAL_OSPI_DATA_2_LINES) || \ - ((MODE) == HAL_OSPI_DATA_4_LINES) || \ - ((MODE) == HAL_OSPI_DATA_8_LINES)) - -#define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) - -#define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ - ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) - -#define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) - -#define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ - ((MODE) == HAL_OSPI_DQS_ENABLE)) - -#define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ - ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) - -#define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) - -#define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) - -#define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ - ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) - -#define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ - ((MODE) == HAL_OSPI_FIXED_LATENCY)) - -#define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ - ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) - -#define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ - ((MODE) == HAL_OSPI_MATCH_MODE_OR)) - -#define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ - ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) - -#define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) - -#define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) - -#define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ - ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) - -#define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) - -#define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) - -#define IS_OSPI_DLYBYP(MODE) (((MODE) == HAL_OSPI_DELAY_BLOCK_USED) || \ - ((MODE) == HAL_OSPI_DELAY_BLOCK_BYPASSED)) - -#define IS_OSPI_MAXTRAN(NB_BYTES) ((NB_BYTES) <= 255U) -#if defined(OCTOSPIM) - -#define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 8U)) - -#define IS_OSPIM_DQS_PORT(NUMBER) ((NUMBER) <= 8U) - -#define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_NONE) || \ - ((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_2_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_3_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_3_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_4_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_4_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_5_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_5_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_6_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_6_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_7_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_7_HIGH) || \ - ((PORT) == HAL_OSPIM_IOPORT_8_LOW) || \ - ((PORT) == HAL_OSPIM_IOPORT_8_HIGH)) - -#if defined (OCTOSPIM_CR_MUXEN) -#define IS_OSPIM_REQ2ACKTIME(TIME) (((TIME) >= 1U) && ((TIME) <= 256U)) -#endif /*(OCTOSPIM_CR_MUXEN)*/ -#endif /*(OCTOSPIM)*/ -/** - @endcond - */ - -/* End of private macros -----------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_OSPI_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h deleted file mode 100644 index 62741b5ec..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd.h +++ /dev/null @@ -1,675 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pcd.h - * @author MCD Application Team - * @brief Header file of PCD HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_PCD_H -#define STM32U5xx_HAL_PCD_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_usb.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCD - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup PCD_Exported_Types PCD Exported Types - * @{ - */ - -/** - * @brief PCD State structure definition - */ -typedef enum -{ - HAL_PCD_STATE_RESET = 0x00, - HAL_PCD_STATE_READY = 0x01, - HAL_PCD_STATE_ERROR = 0x02, - HAL_PCD_STATE_BUSY = 0x03, - HAL_PCD_STATE_TIMEOUT = 0x04 -} PCD_StateTypeDef; - -/* Device LPM suspend state */ -typedef enum -{ - LPM_L0 = 0x00, /* on */ - LPM_L1 = 0x01, /* LPM L1 sleep */ - LPM_L2 = 0x02, /* suspend */ - LPM_L3 = 0x03, /* off */ -} PCD_LPM_StateTypeDef; - -typedef enum -{ - PCD_LPM_L0_ACTIVE = 0x00, /* on */ - PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */ -} PCD_LPM_MsgTypeDef; - -typedef enum -{ - PCD_BCD_ERROR = 0xFF, - PCD_BCD_CONTACT_DETECTION = 0xFE, - PCD_BCD_STD_DOWNSTREAM_PORT = 0xFD, - PCD_BCD_CHARGING_DOWNSTREAM_PORT = 0xFC, - PCD_BCD_DEDICATED_CHARGING_PORT = 0xFB, - PCD_BCD_DISCOVERY_COMPLETED = 0x00, - -} PCD_BCD_MsgTypeDef; - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -typedef USB_OTG_GlobalTypeDef PCD_TypeDef; -typedef USB_OTG_CfgTypeDef PCD_InitTypeDef; -typedef USB_OTG_EPTypeDef PCD_EPTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined (USB_DRD_FS) -typedef USB_DRD_TypeDef PCD_TypeDef; -typedef USB_DRD_CfgTypeDef PCD_InitTypeDef; -typedef USB_DRD_EPTypeDef PCD_EPTypeDef; -#endif /* defined (USB_DRD_FS) */ - -/** - * @brief PCD Handle Structure definition - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -typedef struct __PCD_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -{ - PCD_TypeDef *Instance; /*!< Register base address */ - PCD_InitTypeDef Init; /*!< PCD required parameters */ - __IO uint8_t USB_Address; /*!< USB Address */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - PCD_EPTypeDef IN_ep[16]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[16]; /*!< OUT endpoint parameters */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined (USB_DRD_FS) - PCD_EPTypeDef IN_ep[8]; /*!< IN endpoint parameters */ - PCD_EPTypeDef OUT_ep[8]; /*!< OUT endpoint parameters */ -#endif /* defined (USB_DRD_FS) */ - HAL_LockTypeDef Lock; /*!< PCD peripheral status */ - __IO PCD_StateTypeDef State; /*!< PCD communication state */ - __IO uint32_t ErrorCode; /*!< PCD Error code */ - uint32_t Setup[12]; /*!< Setup packet buffer */ - PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */ - uint32_t BESL; - uint32_t FrameNumber; /*!< Store Current Frame number */ - - - uint32_t lpm_active; /*!< Enable or disable the Link Power Management . - This parameter can be set to ENABLE or DISABLE */ - - uint32_t battery_charging_active; /*!< Enable or disable Battery charging. - This parameter can be set to ENABLE or DISABLE */ - void *pData; /*!< Pointer to upper stack Handler */ - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - void (* SOFCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD SOF callback */ - void (* SetupStageCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Setup Stage callback */ - void (* ResetCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Reset callback */ - void (* SuspendCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Suspend callback */ - void (* ResumeCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Resume callback */ - void (* ConnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Connect callback */ - void (* DisconnectCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Disconnect callback */ - - void (* DataOutStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data OUT Stage callback */ - void (* DataInStageCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD Data IN Stage callback */ - void (* ISOOUTIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO OUT Incomplete callback */ - void (* ISOINIncompleteCallback)(struct __PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< USB OTG PCD ISO IN Incomplete callback */ - void (* BCDCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< USB OTG PCD BCD callback */ - void (* LPMCallback)(struct __PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< USB OTG PCD LPM callback */ - - void (* MspInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp Init callback */ - void (* MspDeInitCallback)(struct __PCD_HandleTypeDef *hpcd); /*!< USB OTG PCD Msp DeInit callback */ -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -} PCD_HandleTypeDef; - -/** - * @} - */ - -/* Include PCD HAL Extended module */ -#include "stm32u5xx_hal_pcd_ex.h" - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -/** @defgroup PCD_Speed PCD Speed - * @{ - */ -#define PCD_SPEED_HIGH USBD_HS_SPEED -#define PCD_SPEED_HIGH_IN_FULL USBD_HSINFS_SPEED -#define PCD_SPEED_FULL USBD_FS_SPEED -/** - * @} - */ - -/** @defgroup PCD_PHY_Module PCD PHY Module - * @{ - */ -#define PCD_PHY_ULPI 1U -#define PCD_PHY_EMBEDDED 2U -#define PCD_PHY_UTMI 3U -/** - * @} - */ - -/** @defgroup PCD_Error_Code_definition PCD Error Code definition - * @brief PCD Error Code definition - * @{ - */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -#define HAL_PCD_ERROR_INVALID_CALLBACK (0x00000010U) /*!< Invalid Callback error */ -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup PCD_Exported_Macros PCD Exported Macros - * @brief macros to handle interrupts and specific clock configurations - * @{ - */ -#define __HAL_PCD_ENABLE(__HANDLE__) (void)USB_EnableGlobalInt ((__HANDLE__)->Instance) -#define __HAL_PCD_DISABLE(__HANDLE__) (void)USB_DisableGlobalInt ((__HANDLE__)->Instance) - -#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__) \ - ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__)) - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) &= (__INTERRUPT__)) -#define __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U) - -#define __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__) \ - *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) &= ~(USB_OTG_PCGCCTL_STOPCLK) - -#define __HAL_PCD_GATE_PHYCLOCK(__HANDLE__) \ - *(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE) |= USB_OTG_PCGCCTL_STOPCLK - -#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) \ - ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE)) & 0x10U) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->ISTR)\ - &= (uint16_t)(~(__INTERRUPT__))) -#endif /* defined (USB_DRD_FS) */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/* Initialization/de-initialization functions ********************************/ -/** @addtogroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd); -void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd); - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -/** @defgroup HAL_PCD_Callback_ID_enumeration_definition HAL USB OTG PCD Callback ID enumeration definition - * @brief HAL USB OTG PCD Callback ID enumeration definition - * @{ - */ -typedef enum -{ - HAL_PCD_SOF_CB_ID = 0x01, /*!< USB PCD SOF callback ID */ - HAL_PCD_SETUPSTAGE_CB_ID = 0x02, /*!< USB PCD Setup Stage callback ID */ - HAL_PCD_RESET_CB_ID = 0x03, /*!< USB PCD Reset callback ID */ - HAL_PCD_SUSPEND_CB_ID = 0x04, /*!< USB PCD Suspend callback ID */ - HAL_PCD_RESUME_CB_ID = 0x05, /*!< USB PCD Resume callback ID */ - HAL_PCD_CONNECT_CB_ID = 0x06, /*!< USB PCD Connect callback ID */ - HAL_PCD_DISCONNECT_CB_ID = 0x07, /*!< USB PCD Disconnect callback ID */ - - HAL_PCD_MSPINIT_CB_ID = 0x08, /*!< USB PCD MspInit callback ID */ - HAL_PCD_MSPDEINIT_CB_ID = 0x09 /*!< USB PCD MspDeInit callback ID */ - -} HAL_PCD_CallbackIDTypeDef; -/** - * @} - */ - -/** @defgroup HAL_PCD_Callback_pointer_definition HAL USB OTG PCD Callback pointer definition - * @brief HAL USB OTG PCD Callback pointer definition - * @{ - */ - -typedef void (*pPCD_CallbackTypeDef)(PCD_HandleTypeDef *hpcd); /*!< pointer to a common USB OTG PCD callback function */ -typedef void (*pPCD_DataOutStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data OUT Stage callback */ -typedef void (*pPCD_DataInStageCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD Data IN Stage callback */ -typedef void (*pPCD_IsoOutIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO OUT Incomplete callback */ -typedef void (*pPCD_IsoInIncpltCallbackTypeDef)(PCD_HandleTypeDef *hpcd, uint8_t epnum); /*!< pointer to USB OTG PCD ISO IN Incomplete callback */ -typedef void (*pPCD_LpmCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); /*!< pointer to USB OTG PCD LPM callback */ -typedef void (*pPCD_BcdCallbackTypeDef)(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); /*!< pointer to USB OTG PCD BCD callback */ - -/** - * @} - */ - -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID, - pPCD_CallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataOutStageCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataInStageCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoOutIncpltCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoInIncpltCallbackTypeDef pCallback); - -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd); - -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* I/O operation functions ***************************************************/ -/* Non-Blocking mode: Interrupt */ -/** @addtogroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd); -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd); -void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd); - -void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum); -/** - * @} - */ - -/* Peripheral Control functions **********************************************/ -/** @addtogroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address); -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type); -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len); -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr); -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd); -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr); -/** - * @} - */ - -/* Peripheral State functions ************************************************/ -/** @addtogroup PCD_Exported_Functions_Group4 Peripheral State functions - * @{ - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); -/** - * @} - */ - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup PCD_Private_Constants PCD Private Constants - * @{ - */ -#if defined (USB_DRD_FS) -/** @defgroup PCD_EP0_MPS PCD EP0 MPS - * @{ - */ -#define PCD_EP0MPS_64 EP_MPS_64 -#define PCD_EP0MPS_32 EP_MPS_32 -#define PCD_EP0MPS_16 EP_MPS_16 -#define PCD_EP0MPS_08 EP_MPS_8 -/** - * @} - */ - -/** @defgroup PCD_ENDP PCD ENDP - * @{ - */ -#define PCD_ENDP0 0U -#define PCD_ENDP1 1U -#define PCD_ENDP2 2U -#define PCD_ENDP3 3U -#define PCD_ENDP4 4U -#define PCD_ENDP5 5U -#define PCD_ENDP6 6U -#define PCD_ENDP7 7U -/** - * @} - */ - -/** @defgroup PCD_ENDP_Kind PCD Endpoint Kind - * @{ - */ -#define PCD_SNG_BUF 0U -#define PCD_DBL_BUF 1U -/** - * @} - */ -#endif /* defined (USB_DRD_FS) */ -/** - * @} - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#ifndef USB_OTG_DOEPINT_OTEPSPR -#define USB_OTG_DOEPINT_OTEPSPR (0x1UL << 5) /*!< Status Phase Received interrupt */ -#endif /* defined USB_OTG_DOEPINT_OTEPSPR */ - -#ifndef USB_OTG_DOEPMSK_OTEPSPRM -#define USB_OTG_DOEPMSK_OTEPSPRM (0x1UL << 5) /*!< Setup Packet Received interrupt mask */ -#endif /* defined USB_OTG_DOEPMSK_OTEPSPRM */ - -#ifndef USB_OTG_DOEPINT_NAK -#define USB_OTG_DOEPINT_NAK (0x1UL << 13) /*!< NAK interrupt */ -#endif /* defined USB_OTG_DOEPINT_NAK */ - -#ifndef USB_OTG_DOEPMSK_NAKM -#define USB_OTG_DOEPMSK_NAKM (0x1UL << 13) /*!< OUT Packet NAK interrupt mask */ -#endif /* defined USB_OTG_DOEPMSK_NAKM */ - -#ifndef USB_OTG_DOEPINT_STPKTRX -#define USB_OTG_DOEPINT_STPKTRX (0x1UL << 15) /*!< Setup Packet Received interrupt */ -#endif /* defined USB_OTG_DOEPINT_STPKTRX */ - -#ifndef USB_OTG_DOEPMSK_NYETM -#define USB_OTG_DOEPMSK_NYETM (0x1UL << 14) /*!< Setup Packet Received interrupt mask */ -#endif /* defined USB_OTG_DOEPMSK_NYETM */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#if defined (USB_DRD_FS) -/* PMA RX counter */ -#ifndef PCD_RX_PMA_CNT -#define PCD_RX_PMA_CNT 10U -#endif /* PCD_RX_PMA_CNT */ - -/* SetENDPOINT */ -#define PCD_SET_ENDPOINT USB_DRD_SET_CHEP - -/* GetENDPOINT Register value*/ -#define PCD_GET_ENDPOINT USB_DRD_GET_CHEP - - -/** - * @brief free buffer used from the application realizing it to the line - * toggles bit SW_BUF in the double buffered endpoint register - * @param USBx USB device. - * @param bEpNum, bDir - * @retval None - */ -#define PCD_FREE_USER_BUFFER USB_DRD_FREE_USER_BUFFER - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wState new state - * @retval None - */ -#define PCD_SET_EP_TX_STATUS USB_DRD_SET_CHEP_TX_STATUS - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wState new state - * @retval None - */ -#define PCD_SET_EP_RX_STATUS USB_DRD_SET_CHEP_RX_STATUS - -/** - * @brief Sets/clears directly EP_KIND bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_SET_EP_KIND USB_DRD_SET_CHEP_KIND -#define PCD_CLEAR_EP_KIND USB_DRD_CLEAR_CHEP_KIND -#define PCD_SET_BULK_EP_DBUF PCD_SET_EP_KIND -#define PCD_CLEAR_BULK_EP_DBUF PCD_CLEAR_EP_KIND - - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_EP_CTR USB_DRD_CLEAR_RX_CHEP_CTR -#define PCD_CLEAR_TX_EP_CTR USB_DRD_CLEAR_TX_CHEP_CTR -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_RX_DTOG USB_DRD_RX_DTOG -#define PCD_TX_DTOG USB_DRD_TX_DTOG -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval None - */ -#define PCD_CLEAR_RX_DTOG USB_DRD_CLEAR_RX_DTOG -#define PCD_CLEAR_TX_DTOG USB_DRD_CLEAR_TX_DTOG - -/** - * @brief Sets address in an endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param bAddr Address. - * @retval None - */ -#define PCD_SET_EP_ADDRESS USB_DRD_SET_CHEP_ADDRESS - -/** - * @brief sets address of the tx/rx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wAddr address to be set (must be word aligned). - * @retval None - */ -#define PCD_SET_EP_TX_ADDRESS USB_DRD_SET_CHEP_TX_ADDRESS -#define PCD_SET_EP_RX_ADDRESS USB_DRD_SET_CHEP_RX_ADDRESS - -/** - * @brief sets counter for the tx/rx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wCount Counter value. - * @retval None - */ -#define PCD_SET_EP_TX_CNT USB_DRD_SET_CHEP_TX_CNT -#define PCD_SET_EP_RX_CNT USB_DRD_SET_CHEP_RX_CNT - -/** - * @brief gets counter of the tx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @retval Counter value - */ -#define PCD_GET_EP_TX_CNT USB_DRD_GET_CHEP_TX_CNT - -/** - * @brief gets counter of the rx buffer. - * @param Instance USB peripheral instance register address. - * @param bEpNum channel Number. - * @retval Counter value - */ -__STATIC_INLINE uint16_t PCD_GET_EP_RX_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) -{ - UNUSED(Instance); - __IO uint32_t count = PCD_RX_PMA_CNT; - - /* WA: few cycles for RX PMA descriptor to update */ - while (count > 0U) - { - count--; - } - - return (uint16_t)USB_DRD_GET_CHEP_RX_CNT((Instance), (bEpNum)); -} - -/** - * @brief Sets addresses in a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. - * @retval None - */ -#define PCD_SET_EP_DBUF_ADDR USB_DRD_SET_CHEP_DBUF_ADDR - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpNum Endpoint Number. - * @param bDir endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value - * @retval None - */ -#define PCD_SET_EP_DBUF0_CNT USB_DRD_SET_CHEP_DBUF0_CNT -#define PCD_SET_EP_DBUF1_CNT USB_DRD_SET_CHEP_DBUF1_CNT -#define PCD_SET_EP_DBUF_CNT USB_DRD_SET_CHEP_DBUF_CNT - -/** - * @brief gets counter of the rx buffer0. - * @param Instance USB peripheral instance register address. - * @param bEpNum channel Number. - * @retval Counter value - */ -__STATIC_INLINE uint16_t PCD_GET_EP_DBUF0_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) -{ - UNUSED(Instance); - __IO uint32_t count = PCD_RX_PMA_CNT; - - /* WA: few cycles for RX PMA descriptor to update */ - while (count > 0U) - { - count--; - } - - return (uint16_t)USB_DRD_GET_CHEP_DBUF0_CNT((Instance), (bEpNum)); -} - -/** - * @brief gets counter of the rx buffer1. - * @param Instance USB peripheral instance register address. - * @param bEpNum channel Number. - * @retval Counter value - */ -__STATIC_INLINE uint16_t PCD_GET_EP_DBUF1_CNT(const PCD_TypeDef *Instance, uint16_t bEpNum) -{ - UNUSED(Instance); - __IO uint32_t count = PCD_RX_PMA_CNT; - - /* WA: few cycles for RX PMA descriptor to update */ - while (count > 0U) - { - count--; - } - - return (uint16_t)USB_DRD_GET_CHEP_DBUF1_CNT((Instance), (bEpNum)); -} -#endif /* defined (USB_DRD_FS) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_PCD_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h deleted file mode 100644 index ab2bb878e..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pcd_ex.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pcd_ex.h - * @author MCD Application Team - * @brief Header file of PCD HAL Extension module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_PCD_EX_H -#define STM32U5xx_HAL_PCD_EX_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup PCDEx - * @{ - */ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ -/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @{ - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size); -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, - uint16_t ep_kind, uint32_t pmaadress); -#endif /* defined (USB_DRD_FS) */ - -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd); - - -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd); -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd); -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd); - -void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg); -void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* STM32U5xx_HAL_PCD_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h deleted file mode 100644 index c44722dc9..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr.h +++ /dev/null @@ -1,813 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pwr.h - * @author MCD Application Team - * @brief Header file of PWR HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_PWR_H -#define STM32U5xx_HAL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWR - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Types PWR Exported Types - * @{ - */ - -/** - * @brief PWR PVD configuration structure definition - */ -typedef struct -{ - uint32_t PVDLevel; /*!< Specifies the PVD detection level. - This parameter can be a value of - @ref PWR_PVD_Detection_Level. */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref PWR_PVD_Mode. */ -} PWR_PVDTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_PVD_Detection_Level Programmable Voltage Detection Level - * @{ - */ -#define PWR_PVDLEVEL_0 0x00000000UL /*!< PVD threshold around 2.0 V */ -#define PWR_PVDLEVEL_1 (PWR_SVMCR_PVDLS_0) /*!< PVD threshold around 2.2 V */ -#define PWR_PVDLEVEL_2 (PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.4 V */ -#define PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< PVD threshold around 2.5 V */ -#define PWR_PVDLEVEL_4 (PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.6 V */ -#define PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.8 V */ -#define PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< PVD threshold around 2.9 V */ -#define PWR_PVDLEVEL_7 (PWR_SVMCR_PVDLS) /*!< External input analog voltage - (compared internally to VREFINT) */ -/** - * @} - */ - -/** @defgroup PWR_PVD_Mode PWR PVD Mode - * @{ - */ -#define PWR_PVD_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ -#define PWR_PVD_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVD_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVD_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup PWR_Regulator_In_LowPower_Mode PWR Regulator State in Sleep/Stop Mode - * @{ - */ -#define PWR_MAINREGULATOR_ON (0x00U) /*!< Main Regulator ON in Run Mode */ -#define PWR_LOWPOWERREGULATOR_ON (0x00U) /*!< Main Regulator ON in Low Power Mode */ -/** - * @} - */ - -/** @defgroup PWR_Sleep_Mode_Entry PWR Sleep Mode Entry - * @{ - */ -#define PWR_SLEEPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Sleep mode */ -#define PWR_SLEEPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Sleep mode */ -#define PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR (0x03U) -/** - * @} - */ - -/** @defgroup PWR_Stop_Mode_Entry PWR Stop Mode Entry - * @{ - */ -#define PWR_STOPENTRY_WFI (0x01U) /*!< Wait For Interruption instruction to enter Stop mode */ -#define PWR_STOPENTRY_WFE (0x02U) /*!< Wait For Event instruction to enter Stop mode */ -#define PWR_STOPENTRY_WFE_NO_EVT_CLEAR (0x03U) -/** - * @} - */ - -/** @defgroup PWR_Flags PWR Flags - * @{ - */ -#define PWR_FLAG_VOSRDY (0x01U) /*!< Voltage scaling ready flag */ -#define PWR_FLAG_BOOSTRDY (0x02U) /*!< EPOD booster ready flag */ -#define PWR_FLAG_STOPF (0x03U) /*!< Stop flag */ -#define PWR_FLAG_SBF (0x04U) /*!< Standby flag */ -#define PWR_FLAG_VDDA2RDY (0x05U) /*!< VDDA ready flag (versus 1.8 V threshold) */ -#define PWR_FLAG_VDDA1RDY (0x06U) /*!< VDDA ready flag (versus 1.6 V threshold) */ -#define PWR_FLAG_VDDIO2RDY (0x07U) /*!< VDDIO2 ready flag */ -#define PWR_FLAG_VDDUSBRDY (0x08U) /*!< VDDUSB ready flag */ -#define PWR_FLAG_ACTVOSRDY (0x09U) /*!< Currently applied VOS ready flag */ -#define PWR_FLAG_PVDO (0x0AU) /*!< VDD voltage detector output flag */ -#define PWR_FLAG_REGS (0x0BU) /*!< Regulator selection flag */ -#define PWR_FLAG_TEMPH (0x0CU) /*!< Temperature level flag (versus high threshold) */ -#define PWR_FLAG_TEMPL (0x0DU) /*!< Temperature level flag (versus low threshold) */ -#define PWR_FLAG_VBATH (0x0EU) /*!< Backup domain voltage level flag (versus high threshold) */ -#if defined (PWR_VOSR_USBBOOSTRDY) -#define PWR_FLAG_USBBOOSTRDY (0x0FU) /*!< USB EPOD booster ready flag */ -#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Lines_Flags PWR Wakeup Lines Flags - * @{ - */ -#define PWR_WAKEUP_FLAG1 (0x10U) /*!< Wakeup flag 1 */ -#define PWR_WAKEUP_FLAG2 (0x20U) /*!< Wakeup flag 2 */ -#define PWR_WAKEUP_FLAG3 (0x30U) /*!< Wakeup flag 3 */ -#define PWR_WAKEUP_FLAG4 (0x40U) /*!< Wakeup flag 4 */ -#define PWR_WAKEUP_FLAG5 (0x50U) /*!< Wakeup flag 5 */ -#define PWR_WAKEUP_FLAG6 (0x60U) /*!< Wakeup flag 6 */ -#define PWR_WAKEUP_FLAG7 (0x70U) /*!< Wakeup flag 7 */ -#define PWR_WAKEUP_FLAG8 (0x80U) /*!< Wakeup flag 8 */ -#define PWR_WAKEUP_ALL_FLAG (0x90U) /*!< Wakeup flag all */ -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Pin_High_Polarity PWR Wake Up Pins High Polarity - * @{ - */ -#define PWR_WAKEUP_PIN1_HIGH_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (high polarity) */ -#define PWR_WAKEUP_PIN1_HIGH_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (high polarity) */ -#define PWR_WAKEUP_PIN1_HIGH_2 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_SOURCE_SELECTION_2) /*!< PE4 : Wakeup pin 1 (high polarity) */ - -#define PWR_WAKEUP_PIN2_HIGH_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (high polarity) */ -#define PWR_WAKEUP_PIN2_HIGH_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (high polarity) */ -#define PWR_WAKEUP_PIN2_HIGH_2 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_SOURCE_SELECTION_2) /*!< PE5 : Wakeup pin 2 (high polarity) */ - -#define PWR_WAKEUP_PIN3_HIGH_0 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_0) /*!< PE6 : Wakeup pin 3 (high polarity) */ -#define PWR_WAKEUP_PIN3_HIGH_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (high polarity) */ -#define PWR_WAKEUP_PIN3_HIGH_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (high polarity) */ - -#define PWR_WAKEUP_PIN4_HIGH_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (high polarity) */ -#define PWR_WAKEUP_PIN4_HIGH_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (high polarity) */ -#define PWR_WAKEUP_PIN4_HIGH_2 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 4 (high polarity) */ - -#define PWR_WAKEUP_PIN5_HIGH_0 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_0) /*!< PC5 : Wakeup pin 5 (high polarity) */ -#define PWR_WAKEUP_PIN5_HIGH_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (high polarity) */ -#define PWR_WAKEUP_PIN5_HIGH_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB8 : Wakeup pin 5 (high polarity) */ - -#define PWR_WAKEUP_PIN6_HIGH_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PB5 : Wakeup pin 6 (high polarity) */ -#define PWR_WAKEUP_PIN6_HIGH_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (high polarity) */ -#define PWR_WAKEUP_PIN6_HIGH_2 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_2) /*!< PE7 : Wakeup pin 6 (high polarity) */ -#define PWR_WAKEUP_PIN6_HIGH_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (high polarity) */ - -#define PWR_WAKEUP_PIN7_HIGH_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB15 : Wakeup pin 7 (high polarity) */ -#define PWR_WAKEUP_PIN7_HIGH_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (high polarity) */ -#define PWR_WAKEUP_PIN7_HIGH_2 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_2) /*!< PE8 : Wakeup pin 7 (high polarity) */ -#define PWR_WAKEUP_PIN7_HIGH_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (high polarity) */ - -#define PWR_WAKEUP_PIN8_HIGH_0 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_0) /*!< PF2 : Wakeup pin 8 (high polarity) */ -#define PWR_WAKEUP_PIN8_HIGH_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (high polarity) */ -#define PWR_WAKEUP_PIN8_HIGH_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB10 : Wakeup pin 8 (high polarity) */ -#define PWR_WAKEUP_PIN8_HIGH_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 8 (high polarity) */ -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Pin_Low_Polarity PWR Wake Up Pins Low Polarity - * @{ - */ -#define PWR_WAKEUP_PIN1_LOW_0 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_0) /*!< PA0 : Wakeup pin 1 (low polarity) */ -#define PWR_WAKEUP_PIN1_LOW_1 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_1) /*!< PB2 : Wakeup pin 1 (low polarity) */ -#define PWR_WAKEUP_PIN1_LOW_2 (PWR_WUCR1_WUPEN1 | PWR_WAKEUP1_POLARITY_LOW | PWR_WAKEUP1_SOURCE_SELECTION_2) /*!< PE4 : Wakeup pin 1 (low polarity) */ - -#define PWR_WAKEUP_PIN2_LOW_0 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_0) /*!< PA4 : Wakeup pin 2 (low polarity) */ -#define PWR_WAKEUP_PIN2_LOW_1 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_1) /*!< PC13 : Wakeup pin 2 (low polarity) */ -#define PWR_WAKEUP_PIN2_LOW_2 (PWR_WUCR1_WUPEN2 | PWR_WAKEUP2_POLARITY_LOW | PWR_WAKEUP2_SOURCE_SELECTION_2) /*!< PE5 : Wakeup pin 2 (low polarity) */ - -#define PWR_WAKEUP_PIN3_LOW_0 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_0) /*!< PE6 : Wakeup pin 3 (low polarity) */ -#define PWR_WAKEUP_PIN3_LOW_1 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_1) /*!< PA1 : Wakeup pin 3 (low polarity) */ -#define PWR_WAKEUP_PIN3_LOW_2 (PWR_WUCR1_WUPEN3 | PWR_WAKEUP3_POLARITY_LOW | PWR_WAKEUP3_SOURCE_SELECTION_2) /*!< PB6 : Wakeup pin 3 (low polarity) */ - -#define PWR_WAKEUP_PIN4_LOW_0 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_0) /*!< PA2 : Wakeup pin 4 (low polarity) */ -#define PWR_WAKEUP_PIN4_LOW_1 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_1) /*!< PB1 : Wakeup pin 4 (low polarity) */ -#define PWR_WAKEUP_PIN4_LOW_2 (PWR_WUCR1_WUPEN4 | PWR_WAKEUP4_POLARITY_LOW | PWR_WAKEUP4_SOURCE_SELECTION_2) /*!< PB7 : Wakeup pin 4 (low polarity) */ - -#define PWR_WAKEUP_PIN5_LOW_0 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_0) /*!< PC5 : Wakeup pin 5 (low polarity) */ -#define PWR_WAKEUP_PIN5_LOW_1 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_1) /*!< PA3 : Wakeup pin 5 (low polarity) */ -#define PWR_WAKEUP_PIN5_LOW_2 (PWR_WUCR1_WUPEN5 | PWR_WAKEUP5_POLARITY_LOW | PWR_WAKEUP5_SOURCE_SELECTION_2) /*!< PB8 : Wakeup pin 5 (low polarity) */ - -#define PWR_WAKEUP_PIN6_LOW_0 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_0) /*!< PB5 : Wakeup pin 6 (low polarity) */ -#define PWR_WAKEUP_PIN6_LOW_1 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_1) /*!< PA5 : Wakeup pin 6 (low polarity) */ -#define PWR_WAKEUP_PIN6_LOW_2 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_2) /*!< PE7 : Wakeup pin 6 (low polarity) */ -#define PWR_WAKEUP_PIN6_LOW_3 (PWR_WUCR1_WUPEN6 | PWR_WAKEUP6_POLARITY_LOW | PWR_WAKEUP6_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 6 (low polarity) */ - -#define PWR_WAKEUP_PIN7_LOW_0 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_0) /*!< PB15 : Wakeup pin 7 (low polarity) */ -#define PWR_WAKEUP_PIN7_LOW_1 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_1) /*!< PA6 : Wakeup pin 7 (low polarity) */ -#define PWR_WAKEUP_PIN7_LOW_2 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_2) /*!< PE8 : Wakeup pin 7 (low polarity) */ -#define PWR_WAKEUP_PIN7_LOW_3 (PWR_WUCR1_WUPEN7 | PWR_WAKEUP7_POLARITY_LOW | PWR_WAKEUP7_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 7 (low polarity) */ - -#define PWR_WAKEUP_PIN8_LOW_0 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_0) /*!< PF2 : Wakeup pin 8 (low polarity) */ -#define PWR_WAKEUP_PIN8_LOW_1 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_1) /*!< PA7 : Wakeup pin 8 (low polarity) */ -#define PWR_WAKEUP_PIN8_LOW_2 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_2) /*!< PB10 : Wakeup pin 8 (low polarity) */ -#define PWR_WAKEUP_PIN8_LOW_3 (PWR_WUCR1_WUPEN8 | PWR_WAKEUP8_POLARITY_LOW | PWR_WAKEUP8_SOURCE_SELECTION_3) /*!< RTC : Wakeup pin 8 (low polarity) */ -/** - * @} - */ - -/** @defgroup PWR_WakeUp_Pins PWR Wake Up Pins (Default polarity and default pin selection) - * @{ - */ -#define PWR_WAKEUP_PIN1 (PWR_WUCR1_WUPEN1) /*!< PA0 : Wakeup pin 1 (high polarity) */ -#define PWR_WAKEUP_PIN2 (PWR_WUCR1_WUPEN2) /*!< PA4 : Wakeup pin 2 (high polarity) */ -#define PWR_WAKEUP_PIN3 (PWR_WUCR1_WUPEN3) /*!< PE6 : Wakeup pin 3 (high polarity) */ -#define PWR_WAKEUP_PIN4 (PWR_WUCR1_WUPEN4) /*!< PA2 : Wakeup pin 4 (high polarity) */ -#define PWR_WAKEUP_PIN5 (PWR_WUCR1_WUPEN5) /*!< PC5 : Wakeup pin 5 (high polarity) */ -#define PWR_WAKEUP_PIN6 (PWR_WUCR1_WUPEN6) /*!< PB5 : Wakeup pin 6 (high polarity) */ -#define PWR_WAKEUP_PIN7 (PWR_WUCR1_WUPEN7) /*!< PB15 : Wakeup pin 7 (high polarity) */ -#define PWR_WAKEUP_PIN8 (PWR_WUCR1_WUPEN8) /*!< PF2 : Wakeup pin 8 (high polarity) */ -/** - * @} - */ - -/** @defgroup PWR_Items PWR Items - * @{ - */ -#define PWR_WKUP1 (PWR_SECCFGR_WUP1SEC) /*!< WUP1 secure protection */ -#define PWR_WKUP2 (PWR_SECCFGR_WUP2SEC) /*!< WUP2 secure protection */ -#define PWR_WKUP3 (PWR_SECCFGR_WUP3SEC) /*!< WUP3 secure protection */ -#define PWR_WKUP4 (PWR_SECCFGR_WUP4SEC) /*!< WUP4 secure protection */ -#define PWR_WKUP5 (PWR_SECCFGR_WUP5SEC) /*!< WUP5 secure protection */ -#define PWR_WKUP6 (PWR_SECCFGR_WUP6SEC) /*!< WUP6 secure protection */ -#define PWR_WKUP7 (PWR_SECCFGR_WUP7SEC) /*!< WUP7 secure protection */ -#define PWR_WKUP8 (PWR_SECCFGR_WUP8SEC) /*!< WUP8 secure protection */ -#define PWR_LPM (PWR_SECCFGR_LPMSEC) /*!< Low power modes secure protection */ -#define PWR_VDM (PWR_SECCFGR_VDMSEC) /*!< Voltage detection and monitoring secure protection */ -#define PWR_VB (PWR_SECCFGR_VBSEC) /*!< Backup domain secure protection */ -#define PWR_APC (PWR_SECCFGR_APCSEC) /*!< Pull-up/pull-down secure protection */ -#define PWR_ALL (PWR_WKUP1 | PWR_WKUP2 | PWR_WKUP3 | PWR_WKUP4 | \ - PWR_WKUP5 | PWR_WKUP7 | PWR_WKUP6 | PWR_WKUP8 | \ - PWR_LPM | PWR_VDM | PWR_VB | PWR_APC) -/** - * @} - */ - -/** @defgroup PWR_Attributes PWR Attributes - * @brief PWR Privilege/NPrivilege and Secure/NSecure Attributes - * @{ - */ -#define PWR_NSEC_PRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK | 0x01U) /*!< NSecure and Privileged attribute */ -#define PWR_NSEC_NPRIV (PWR_ITEM_ATTR_NSEC_PRIV_MASK) /*!< NSecure and NPrivileged attribute */ -#define PWR_SEC_PRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK | 0x02U) /*!< Secure and Privileged attribute */ -#define PWR_SEC_NPRIV (PWR_ITEM_ATTR_SEC_PRIV_MASK) /*!< Secure and NPrivileged attribute */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @brief Check PWR flags are set or not. - * @param __FLAG__ : Specifies the flag to check. - * This parameter can be one of the following values : - * @arg @ref PWR_FLAG_VOSRDY : Voltage scaling ready flag. - * Indicates that the Vcore level at or above VOS selected level. - * @arg @ref PWR_FLAG_BOOSTRDY : EPOD booster ready flag. - * Indicates that EPOD booster ready, - * frequency could be higher than 50 MHz. - * @arg @ref PWR_FLAG_USBBOOSTRDY : USB EPOD booster ready flag. - * Indicates that USB EPOD booster ready, - * frequency could be higher than 50 MHz. - * This flag is available only for STM32U59xxx and STM32U5Axxx - * devices. - * @arg @ref PWR_FLAG_STOPF : Stop flag. - * Indicates that the device was resumed from Stop mode. - * @arg @ref PWR_FLAG_SBF : Standby flag. - * Indicates that the device was resumed from Standby mode. - * @arg @ref PWR_FLAG_VDDA2RDY : VDDA2 ready flag (versus 1.8 V threshold). - * Indicates that VDDA is equal or above the threshold - * of the VDDA voltage monitor 2 (around 1.8 V). - * @arg @ref PWR_FLAG_VDDA1RDY : VDDA1 ready flag (versus 1.6 V threshold). - * Indicates that VDDA is equal or above the threshold - * of the VDDA voltage monitor 1 (around 1.6 V). - * @arg @ref PWR_FLAG_VDDIO2RDY : VDDIO2 ready flag (versus 0.9 V threshold). - * Indicates that VDDIO2 is equal or above the threshold - * of the VDDIO2 voltage monitor (around 0.9 V). - * @arg @ref PWR_FLAG_VDDUSBRDY : VDDUSB ready flag (versus 1.2 V threshold). - * Indicates that VDDUSB is equal or above the threshold - * of the VDDUSB voltage monitor (around 1.2 V). - * @arg @ref PWR_FLAG_ACTVOSRDY : Currently applied VOS ready flag. - * Indicates that Vcore is equal to the current - * voltage scaling provided by ACTVOS. - * @arg @ref PWR_FLAG_PVDO VDD : Voltage detector output flag. - * Indicates that Vdd is equal or above - * the PVD threshold selected by PVDLS. - * @arg @ref PWR_FLAG_REGS : Regulator selection flag. - * Indicates the regulator selected. - * @arg @ref PWR_FLAG_TEMPH : Temperature level flag (versus high threshold). - * Indicates the temperature is equal or above high threshold. - * @arg @ref PWR_FLAG_TEMPL : Temperature level flag (versus low threshold). - * Indicates the temperature is equal or above low threshold. - * @arg @ref PWR_FLAG_VBATH : Backup domain voltage level flag (versus high threshold). - * Indicates the backup domain voltage - * level is equal or above high threshold. - * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. - * Indicates that a wakeup event was received from the WKUP line 1. - * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. - * Indicates that a wakeup event was received from the WKUP line 2. - * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. - * Indicates that a wakeup event was received from the WKUP line 3. - * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. - * Indicates that a wakeup event was received from the WKUP line 4. - * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. - * Indicates that a wakeup event was received from the WKUP line 5. - * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. - * Indicates that a wakeup event was received from the WKUP line 6. - * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. - * Indicates that a wakeup event was received from the WKUP line 7. - * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. - * Indicates that a wakeup event was received from the WKUP line 8. - * @retval The state of __FLAG__ (TRUE or FALSE). - */ -#if defined (PWR_FLAG_USBBOOSTRDY) -#define __HAL_PWR_GET_FLAG(__FLAG__) \ - ( \ - ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ - ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ - ((__FLAG__) == PWR_FLAG_USBBOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == PWR_VOSR_USBBOOSTRDY) : \ - ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ - ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \ - ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \ - ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \ - ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \ - ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \ - ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \ - ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \ - ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \ - ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ - ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ - ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ - (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) -#else -#define __HAL_PWR_GET_FLAG(__FLAG__) \ - ( \ - ((__FLAG__) == PWR_FLAG_VOSRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == PWR_VOSR_VOSRDY) : \ - ((__FLAG__) == PWR_FLAG_BOOSTRDY) ? (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == PWR_VOSR_BOOSTRDY) : \ - ((__FLAG__) == PWR_FLAG_STOPF) ? (READ_BIT(PWR->SR, PWR_SR_STOPF) == PWR_SR_STOPF) : \ - ((__FLAG__) == PWR_FLAG_SBF) ? (READ_BIT(PWR->SR, PWR_SR_SBF) == PWR_SR_SBF) : \ - ((__FLAG__) == PWR_FLAG_VDDA2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == PWR_SVMSR_VDDA2RDY) : \ - ((__FLAG__) == PWR_FLAG_VDDA1RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == PWR_SVMSR_VDDA1RDY) : \ - ((__FLAG__) == PWR_FLAG_VDDIO2RDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == PWR_SVMSR_VDDIO2RDY) : \ - ((__FLAG__) == PWR_FLAG_VDDUSBRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == PWR_SVMSR_VDDUSBRDY) : \ - ((__FLAG__) == PWR_FLAG_ACTVOSRDY) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == PWR_SVMSR_ACTVOSRDY) : \ - ((__FLAG__) == PWR_FLAG_PVDO) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == PWR_SVMSR_PVDO) : \ - ((__FLAG__) == PWR_FLAG_REGS) ? (READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == PWR_SVMSR_REGS) : \ - ((__FLAG__) == PWR_FLAG_TEMPH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == PWR_BDSR_TEMPH) : \ - ((__FLAG__) == PWR_FLAG_TEMPL) ? (READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == PWR_BDSR_TEMPL) : \ - ((__FLAG__) == PWR_FLAG_VBATH) ? (READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == PWR_BDSR_VBATH) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == PWR_WUSR_WUF1) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == PWR_WUSR_WUF2) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == PWR_WUSR_WUF3) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == PWR_WUSR_WUF4) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == PWR_WUSR_WUF5) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == PWR_WUSR_WUF6) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == PWR_WUSR_WUF7) : \ - (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == PWR_WUSR_WUF8)) -#endif /* defined (PWR_FLAG_USBBOOSTRDY) */ - -/** @brief Clear PWR flags. - * @param __FLAG__ : Specifies the flag to clear. - * This parameter can be one of the following values : - * @arg @ref PWR_FLAG_STOPF : Stop flag. - * Indicates that the device was resumed from Stop mode. - * @arg @ref PWR_FLAG_SBF : Standby flag. - * Indicates that the device was resumed from Standby mode. - * @arg @ref PWR_WAKEUP_FLAG1 : Wakeup flag 1. - * Indicates that a wakeup event was received from the WKUP line 1. - * @arg @ref PWR_WAKEUP_FLAG2 : Wakeup flag 2. - * Indicates that a wakeup event was received from the WKUP line 2. - * @arg @ref PWR_WAKEUP_FLAG3 : Wakeup flag 3. - * Indicates that a wakeup event was received from the WKUP line 3. - * @arg @ref PWR_WAKEUP_FLAG4 : Wakeup flag 4. - * Indicates that a wakeup event was received from the WKUP line 4. - * @arg @ref PWR_WAKEUP_FLAG5 : Wakeup flag 5. - * Indicates that a wakeup event was received from the WKUP line 5. - * @arg @ref PWR_WAKEUP_FLAG6 : Wakeup flag 6. - * Indicates that a wakeup event was received from the WKUP line 6. - * @arg @ref PWR_WAKEUP_FLAG7 : Wakeup flag 7. - * Indicates that a wakeup event was received from the WKUP line 7. - * @arg @ref PWR_WAKEUP_FLAG8 : Wakeup flag 8. - * Indicates that a wakeup event was received from the WKUP line 8. - * @retval None. - */ -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) \ - ( \ - ((__FLAG__) == PWR_FLAG_STOPF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ - ((__FLAG__) == PWR_FLAG_SBF) ? (SET_BIT(PWR->SR, PWR_SR_CSSF)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG1) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG2) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG3) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG4) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG5) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG6) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG7) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7)) : \ - ((__FLAG__) == PWR_WAKEUP_FLAG8) ? (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8)) : \ - (SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF))) - -/** - * @brief Enable the PVD Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Event Line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Event Line. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Disable the PVD Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_PVD) - -/** - * @brief Enable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software Interrupt on selected EXTI line. - * @retval None - */ -#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_PVD) - -/** - * @brief Check whether or not the PVD EXTI Interrupt flag is set. - * @retval EXTI PVD Line Status. - */ -#define __HAL_PWR_PVD_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_PVD) - -/** - * @brief Clear the PVD EXTI Interrupt flag. - * @retval None. - */ -#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() \ - do \ - { \ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); \ - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); \ - } while(0) -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ - -/** @addtogroup PWR_Private_Constants PWR Private Constants - * @{ - */ -/* Define PVD extended interrupts and event line */ -#define PWR_EXTI_LINE_PVD (0x00010000UL) /*!< PVD EXTI Line */ - -/* Defines wake up lines shift */ -#define PWR_WUP_POLARITY_SHIFT (0x08U) /*!< Internal constant used to retrieve wakeup signal polarity */ -#define PWR_WUP_SELECT_SIGNAL_SHIFT (0x10U) /*!< Internal constant used to retrieve wakeup signal selection */ - -/* Defines wake up lines mask */ -#define PWR_EWUP_MASK (0x000000FFUL) /*!< Internal constant used to retrieve wakeup signal enable */ -#define PWR_WUP_POLARITY_MASK (0x0000FF00UL) /*!< Internal constant used to retrieve wakeup signal polarity */ -#define PWR_WUP_SELECT_MASK (0xFFFF0000UL) /*!< Internal constant used to retrieve wakeup signal selection */ - -/* Defines wake up lines selection */ -#define PWR_WAKEUP1_SOURCE_SELECTION_0 (0U) -#define PWR_WAKEUP1_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL1_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP1_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL1_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP2_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP2_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL2_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP2_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL2_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP3_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP3_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL3_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP3_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL3_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP4_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP4_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL4_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP4_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL4_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP5_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP5_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL5_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP5_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL5_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP6_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP6_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL6_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP6_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL6_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP6_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL6_0 | PWR_WUCR3_WUSEL6_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP7_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP7_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL7_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP7_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL7_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP7_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL7_0 | PWR_WUCR3_WUSEL7_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP8_SOURCE_SELECTION_0 (0U) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP8_SOURCE_SELECTION_1 (PWR_WUCR3_WUSEL8_0 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP8_SOURCE_SELECTION_2 (PWR_WUCR3_WUSEL8_1 << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP8_SOURCE_SELECTION_3 ((PWR_WUCR3_WUSEL8_0 | PWR_WUCR3_WUSEL8_1) << PWR_WUP_SELECT_SIGNAL_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ - -/* Defines wake up lines low polarity */ -#define PWR_WAKEUP1_POLARITY_LOW (PWR_WUCR2_WUPP1 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP2_POLARITY_LOW (PWR_WUCR2_WUPP2 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP3_POLARITY_LOW (PWR_WUCR2_WUPP3 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP4_POLARITY_LOW (PWR_WUCR2_WUPP4 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP5_POLARITY_LOW (PWR_WUCR2_WUPP5 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP6_POLARITY_LOW (PWR_WUCR2_WUPP6 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP7_POLARITY_LOW (PWR_WUCR2_WUPP7 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ -#define PWR_WAKEUP8_POLARITY_LOW (PWR_WUCR2_WUPP8 << PWR_WUP_POLARITY_SHIFT) /*!< Internal constant used to retrieve wakeup signal selection */ - -/* Defines attribute */ -#define PWR_ITEM_ATTR_NSEC_PRIV_MASK (0x10U) /*!< NSecure Privilege / NPrivilege attribute item mask */ -#define PWR_ITEM_ATTR_SEC_PRIV_MASK (0x20U) /*!< Secure Privilege / NPrivilege attribute item mask */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup PWR_Private_Macros PWR Private Macros - * @{ - */ -/* Wake up pins check macro */ -#define IS_PWR_WAKEUP_PIN(PIN) \ - (((PIN) == PWR_WAKEUP_PIN1_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN1_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN1_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN2_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN2_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN2_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN3_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN3_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN3_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN4_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN4_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN4_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN5_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN5_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN5_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN6_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN6_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN6_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN6_HIGH_3) ||\ - ((PIN) == PWR_WAKEUP_PIN7_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN7_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN7_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN7_HIGH_3) ||\ - ((PIN) == PWR_WAKEUP_PIN8_HIGH_0) ||\ - ((PIN) == PWR_WAKEUP_PIN8_HIGH_1) ||\ - ((PIN) == PWR_WAKEUP_PIN8_HIGH_2) ||\ - ((PIN) == PWR_WAKEUP_PIN8_HIGH_3) ||\ - ((PIN) == PWR_WAKEUP_PIN1_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN1_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN1_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN2_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN2_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN2_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN3_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN3_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN3_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN4_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN4_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN4_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN5_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN5_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN5_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN6_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN6_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN6_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN6_LOW_3) ||\ - ((PIN) == PWR_WAKEUP_PIN7_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN7_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN7_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN7_LOW_3) ||\ - ((PIN) == PWR_WAKEUP_PIN8_LOW_0) ||\ - ((PIN) == PWR_WAKEUP_PIN8_LOW_1) ||\ - ((PIN) == PWR_WAKEUP_PIN8_LOW_2) ||\ - ((PIN) == PWR_WAKEUP_PIN8_LOW_3) ||\ - ((PIN) == PWR_WAKEUP_PIN1) ||\ - ((PIN) == PWR_WAKEUP_PIN2) ||\ - ((PIN) == PWR_WAKEUP_PIN3) ||\ - ((PIN) == PWR_WAKEUP_PIN4) ||\ - ((PIN) == PWR_WAKEUP_PIN5) ||\ - ((PIN) == PWR_WAKEUP_PIN6) ||\ - ((PIN) == PWR_WAKEUP_PIN7) ||\ - ((PIN) == PWR_WAKEUP_PIN8)) - -/* PVD level check macro */ -#define IS_PWR_PVD_LEVEL(LEVEL) \ - (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1) ||\ - ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3) ||\ - ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5) ||\ - ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) - -/* PVD mode check macro */ -#define IS_PWR_PVD_MODE(MODE) \ - (((MODE) == PWR_PVD_MODE_NORMAL) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVD_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING)) - -/* Sleep mode entry check macro */ -#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) ||\ - ((ENTRY) == PWR_SLEEPENTRY_WFE) ||\ - ((ENTRY) == PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR)) - -/* Stop mode entry check macro */ -#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) ||\ - ((ENTRY) == PWR_STOPENTRY_WFE) ||\ - ((ENTRY) == PWR_STOPENTRY_WFE_NO_EVT_CLEAR)) - -/* PWR items check macro */ -#define IS_PWR_ITEMS_ATTRIBUTES(ITEM) \ - ((((ITEM) & (~PWR_ALL)) == 0U) && ((ITEM) != 0U)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/* PWR attribute check macro (Secure) */ -#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \ - ((((~(((ATTRIBUTES) & 0xF0U) >> 4U)) & ((ATTRIBUTES) & 0x0FU)) == 0U) && (((ATTRIBUTES) & 0xFFFFFFCCU) == 0U)) -#else -/* PWR attribute check macro (NSecure) */ -#define IS_PWR_ATTRIBUTES(ATTRIBUTES) \ - (((ATTRIBUTES) == PWR_NSEC_NPRIV) || ((ATTRIBUTES) == PWR_NSEC_PRIV)) -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/* Include PWR HAL Extended module */ -#include "stm32u5xx_hal_pwr_ex.h" - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @addtogroup PWR_Exported_Functions_Group1 - * @{ - */ -/* Initialization and de-initialization functions *****************************/ -void HAL_PWR_DeInit(void); -void HAL_PWR_EnableBkUpAccess(void); -void HAL_PWR_DisableBkUpAccess(void); -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group2 - * @{ - */ -/* Programmable voltage detector functions ************************************/ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD); -void HAL_PWR_EnablePVD(void); -void HAL_PWR_DisablePVD(void); - -/* Wake up pins configuration functions ***************************************/ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin); -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin); - -/* Low power modes configuration functions ************************************/ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry); -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry); -void HAL_PWR_EnterSTANDBYMode(void); - -/* Sleep on exit and sev on pending configuration functions *******************/ -void HAL_PWR_EnableSleepOnExit(void); -void HAL_PWR_DisableSleepOnExit(void); -void HAL_PWR_EnableSEVOnPend(void); -void HAL_PWR_DisableSEVOnPend(void); - -/* Interrupt handler functions ************************************************/ -void HAL_PWR_PVD_IRQHandler(void); -void HAL_PWR_PVDCallback(void); -/** - * @} - */ - -/** @addtogroup PWR_Exported_Functions_Group3 - * @{ - */ -/* Privileges and security configuration functions ****************************/ -void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes); -HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* STM32U5xx_HAL_PWR_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h deleted file mode 100644 index 8086e6a02..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_pwr_ex.h +++ /dev/null @@ -1,1109 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pwr_ex.h - * @author MCD Application Team - * @brief Header file of PWR HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_PWR_EX_H -#define STM32U5xx_HAL_PWR_EX_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup PWREx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Types PWR Extended Exported Types - * @{ - */ - -/** - * @brief PWR PVM configuration structure definition - */ -typedef struct -{ - uint32_t PVMType; /*!< Specifies which voltage is monitored. - This parameter can be a value of - @ref PWREx_PVM_Type. */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of - @ref PWREx_PVM_Mode. */ -} PWR_PVMTypeDef; -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Constants PWR Extended Exported Constants - * @{ - */ - -/** @defgroup PWREx_PVM_Type PWR Extended Voltage Monitoring Type - * @{ - */ -#define PWR_UVM PWR_SVMCR_UVMEN /*!< Independent USB voltage monitor (VDDUSB versus 1.2 V) */ -#define PWR_IO2VM PWR_SVMCR_IO2VMEN /*!< Independent VDDIO2 voltage monitor (VDDIO2 versus 0.9 V) */ -#define PWR_AVM1 PWR_SVMCR_AVM1EN /*!< Independent VDDA voltage monitor (VDDA versus 1.6 V) */ -#define PWR_AVM2 PWR_SVMCR_AVM2EN /*!< Independent VDDA voltage monitor (VDDA versus 1.8 V) */ -/** - * @} - */ - -/** @defgroup PWREx_PVM_Mode PWR Extended PVM Interrupt and Event Mode - * @{ - */ -#define PWR_PVM_MODE_NORMAL (0x00U) /*!< Basic Mode is used */ -#define PWR_PVM_MODE_IT_RISING (0x05U) /*!< External Interrupt Mode with Rising edge trigger detection */ -#define PWR_PVM_MODE_IT_FALLING (0x06U) /*!< External Interrupt Mode with Falling edge trigger detection */ -#define PWR_PVM_MODE_IT_RISING_FALLING (0x07U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ -#define PWR_PVM_MODE_EVENT_RISING (0x09U) /*!< Event Mode with Rising edge trigger detection */ -#define PWR_PVM_MODE_EVENT_FALLING (0x0AU) /*!< Event Mode with Falling edge trigger detection */ -#define PWR_PVM_MODE_EVENT_RISING_FALLING (0x0BU) /*!< Event Mode with Rising/Falling edge trigger detection */ -/** - * @} - */ - -/** @defgroup PWREx_SRD_State PWREx SRD Domain State - * @{ - */ -#define PWR_SRD_DOMAIN_STOP (0U) /*!< SRD in Stop mode when system goes to Stop 0/1/2 mode */ -#define PWR_SRD_DOMAIN_RUN PWR_CR2_SRDRUN /*!< SRD in Run mode when system goes to Stop 0/1/2 mode */ -/** - * @} - */ - -/** @defgroup PWREx_RAM_Contents_Stop_Retention PWR Extended RAM Contents Stop Retention - * @{ - */ -/* SRAM1 pages retention defines */ -#define PWR_SRAM1_PAGE1_STOP (SRAM1_ID | PAGE01_ID) /*!< SRAM1 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE2_STOP (SRAM1_ID | PAGE02_ID) /*!< SRAM1 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE3_STOP (SRAM1_ID | PAGE03_ID) /*!< SRAM1 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR4_SRAM1PDS4) -#define PWR_SRAM1_PAGE4_STOP (SRAM1_ID | PAGE04_ID) /*!< SRAM1 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE5_STOP (SRAM1_ID | PAGE05_ID) /*!< SRAM1 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE6_STOP (SRAM1_ID | PAGE06_ID) /*!< SRAM1 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE7_STOP (SRAM1_ID | PAGE07_ID) /*!< SRAM1 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE8_STOP (SRAM1_ID | PAGE08_ID) /*!< SRAM1 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE9_STOP (SRAM1_ID | PAGE09_ID) /*!< SRAM1 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE10_STOP (SRAM1_ID | PAGE10_ID) /*!< SRAM1 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE11_STOP (SRAM1_ID | PAGE11_ID) /*!< SRAM1 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_PAGE12_STOP (SRAM1_ID | PAGE12_ID) /*!< SRAM1 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x0FFFU) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#else -#define PWR_SRAM1_FULL_STOP (SRAM1_ID | 0x07U) /*!< SRAM1 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM1PDS4) */ - -/* SRAM2 pages retention defines */ -#define PWR_SRAM2_PAGE1_STOP (SRAM2_ID | PAGE01_ID) /*!< SRAM2 page 1 (8 KB) retention in Stop modes (Stop 0, 1, 2) */ -#define PWR_SRAM2_PAGE2_STOP (SRAM2_ID | PAGE02_ID) /*!< SRAM2 page 2 (54 KB) retention in Stop modes (Stop 0, 1, 2) */ -#define PWR_SRAM2_FULL_STOP (SRAM2_ID | 0x03U) /*!< SRAM2 all pages retention in Stop modes (Stop 0, 1, 2) */ - -#if defined (PWR_CR2_SRAM3PDS1) -/* SRAM3 pages retention defines */ -#define PWR_SRAM3_PAGE1_STOP (SRAM3_ID | PAGE01_ID) /*!< SRAM3 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE2_STOP (SRAM3_ID | PAGE02_ID) /*!< SRAM3 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE3_STOP (SRAM3_ID | PAGE03_ID) /*!< SRAM3 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE4_STOP (SRAM3_ID | PAGE04_ID) /*!< SRAM3 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE5_STOP (SRAM3_ID | PAGE05_ID) /*!< SRAM3 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE6_STOP (SRAM3_ID | PAGE06_ID) /*!< SRAM3 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE7_STOP (SRAM3_ID | PAGE07_ID) /*!< SRAM3 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE8_STOP (SRAM3_ID | PAGE08_ID) /*!< SRAM3 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR4_SRAM3PDS9) -#define PWR_SRAM3_PAGE9_STOP (SRAM3_ID | PAGE09_ID) /*!< SRAM3 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE10_STOP (SRAM3_ID | PAGE10_ID) /*!< SRAM3 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE11_STOP (SRAM3_ID | PAGE11_ID) /*!< SRAM3 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE12_STOP (SRAM3_ID | PAGE12_ID) /*!< SRAM3 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_PAGE13_STOP (SRAM3_ID | PAGE13_ID) /*!< SRAM3 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0x1FFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#else -#define PWR_SRAM3_FULL_STOP (SRAM3_ID | 0xFFU) /*!< SRAM3 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM3PDS9) */ -#endif /* PWR_CR2_SRAM3PDS1 */ - -/* SRAM4 page retention defines */ -#define PWR_SRAM4_FULL_STOP (SRAM4_ID | PAGE01_ID) /*!< SRAM4 retention in Stop modes (Stop 0, 1, 2, 3) */ - -#if defined (PWR_CR4_SRAM5PDS1) -/* SRAM5 pages retention defines */ -#define PWR_SRAM5_PAGE1_STOP (SRAM5_ID | PAGE01_ID) /*!< SRAM5 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE2_STOP (SRAM5_ID | PAGE02_ID) /*!< SRAM5 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE3_STOP (SRAM5_ID | PAGE03_ID) /*!< SRAM5 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE4_STOP (SRAM5_ID | PAGE04_ID) /*!< SRAM5 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE5_STOP (SRAM5_ID | PAGE05_ID) /*!< SRAM5 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE6_STOP (SRAM5_ID | PAGE06_ID) /*!< SRAM5 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE7_STOP (SRAM5_ID | PAGE07_ID) /*!< SRAM5 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE8_STOP (SRAM5_ID | PAGE08_ID) /*!< SRAM5 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE9_STOP (SRAM5_ID | PAGE09_ID) /*!< SRAM5 page 9 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE10_STOP (SRAM5_ID | PAGE10_ID) /*!< SRAM5 page 10 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE11_STOP (SRAM5_ID | PAGE11_ID) /*!< SRAM5 page 11 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE12_STOP (SRAM5_ID | PAGE12_ID) /*!< SRAM5 page 12 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_PAGE13_STOP (SRAM5_ID | PAGE13_ID) /*!< SRAM5 page 13 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM5_FULL_STOP (SRAM5_ID | 0x1FFFU) /*!< SRAM5 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM5PDS1) */ - -#if defined (PWR_CR5_SRAM6PDS1) -/* SRAM5 pages retention defines */ -#define PWR_SRAM6_PAGE1_STOP (SRAM6_ID | PAGE01_ID) /*!< SRAM6 page 1 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE2_STOP (SRAM6_ID | PAGE02_ID) /*!< SRAM6 page 2 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE3_STOP (SRAM6_ID | PAGE03_ID) /*!< SRAM6 page 3 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE4_STOP (SRAM6_ID | PAGE04_ID) /*!< SRAM6 page 4 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE5_STOP (SRAM6_ID | PAGE05_ID) /*!< SRAM6 page 5 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE6_STOP (SRAM6_ID | PAGE06_ID) /*!< SRAM6 page 6 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE7_STOP (SRAM6_ID | PAGE07_ID) /*!< SRAM6 page 7 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_PAGE8_STOP (SRAM6_ID | PAGE08_ID) /*!< SRAM6 page 8 (64 KB) retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_SRAM6_FULL_STOP (SRAM6_ID | 0xFFU) /*!< SRAM6 all pages retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR5_SRAM6PDS1) */ - -/* Cache RAMs retention defines */ -#define PWR_ICACHE_FULL_STOP (ICACHERAM_ID | PAGE01_ID) /*!< ICACHE page retention in Stop modes (Stop 0, 1, 2, 3) */ -#define PWR_DCACHE1_FULL_STOP (DCACHE1RAM_ID | PAGE01_ID) /*!< DCACHE1 page retention in Stop modes (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR2_DC2RAMPDS) -#define PWR_DCACHE2_FULL_STOP (DCACHE2RAM_ID | PAGE01_ID) /*!< DCACHE2 page retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR2_DC2RAMPDS) */ - -#if defined (PWR_CR2_DMA2DRAMPDS) -/* DMA2D RAM retention defines */ -#define PWR_DMA2DRAM_FULL_STOP (DMA2DRAM_ID | PAGE01_ID) /*!< DMA2D RAM retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* PWR_CR2_DMA2DRAMPDS */ - -/* FMAC, FDCAN and USB RAMs retention defines */ -#define PWR_PERIPHRAM_FULL_STOP (PERIPHRAM_ID | PAGE01_ID) /*!< FMAC, FDCAN and USB RAM retention in Stop modes (Stop 0, 1, 2, 3) */ - -/* PKA32 RAM retention defines */ -#define PWR_PKA32RAM_FULL_STOP (PKARAM_ID | PAGE01_ID) /*!< PKA32 RAM retention in Stop modes (Stop 0, 1, 2, 3) */ - -#if defined (PWR_CR2_GPRAMPDS) -/* Graphic peripherals RAM retention defines */ -#define PWR_GRAPHICPRAM_FULL_STOP (GRAPHIPRAM_ID | PAGE01_ID) /*!< LTDC, GFXMMU retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR2_GPRAMPDS) */ - -#if defined (PWR_CR2_DSIRAMPDS) -/* DSI RAM retention defines */ -#define PWR_DSIRAM_FULL_STOP (DSIRAM_ID | PAGE01_ID) /*!< DSI RAM retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR2_DSIRAMPDS) */ - -#if defined (PWR_CR2_JPEGRAMPDS) -/* JPEG RAM retention defines */ -#define PWR_JPEGRAM_FULL_STOP (JPEGRAM_ID | PAGE01_ID) /*!< JPEG RAM retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR2_JPEGRAMPDS) */ -/** - * @} - */ - -/** @defgroup PWREx_SRAM2_Contents_Standby_Retention PWR Extended SRAM2 Contents Standby Retention - * @note For some products of the U5 family (please see the Reference Manual), - * the SRAM2 content is preserved based on the same defines in Stop 3 mode. - * @{ - */ -#define PWR_SRAM2_PAGE1_STANDBY PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby modes */ -#define PWR_SRAM2_PAGE2_STANDBY PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby modes */ -#define PWR_SRAM2_FULL_STANDBY (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby modes */ -/** - * @} - */ - -/** @defgroup PWREx_SRAMx_Contents_Run_Retention PWR Extended SRAM Contents Run Retention - * @{ - */ -#define PWR_SRAM1_FULL_RUN PWR_CR1_SRAM1PD /*!< SRAM1 full retention in Run mode */ -#define PWR_SRAM2_FULL_RUN PWR_CR1_SRAM2PD /*!< SRAM2 full retention in Run mode */ -#if defined (PWR_CR1_SRAM3PD) -#define PWR_SRAM3_FULL_RUN PWR_CR1_SRAM3PD /*!< SRAM3 full retention in Run mode */ -#endif /* PWR_CR1_SRAM3PD */ -#define PWR_SRAM4_FULL_RUN PWR_CR1_SRAM4PD /*!< SRAM4 full retention in Run mode */ -#if defined (PWR_CR1_SRAM5PD) -#define PWR_SRAM5_FULL_RUN PWR_CR1_SRAM5PD /*!< SRAM5 full retention in Run mode */ -#endif /* defined (PWR_CR1_SRAM5PD) */ -#if defined (PWR_CR1_SRAM6PD) -#define PWR_SRAM6_FULL_RUN PWR_CR1_SRAM6PD /*!< SRAM6 full retention in Run mode */ -#endif /* defined (PWR_CR1_SRAM6PD) */ -/** - * @} - */ - -/** @defgroup PWREx_Supply_Configuration PWR Extended Supply Configuration - * @{ - */ -#define PWR_LDO_SUPPLY (0U) /*!< LDO supply */ -#define PWR_SMPS_SUPPLY (PWR_CR3_REGSEL) /*!< SMPS supply */ -/** - * @} - */ - -/** @defgroup PWREx_Regulator_Voltage_Scale PWR Extended Regulator Voltage Scale - * @{ - */ -#define PWR_REGULATOR_VOLTAGE_SCALE1 (PWR_VOSR_VOS_0 | PWR_VOSR_VOS_1) /*!< Voltage scaling range 1 */ -#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */ -#define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */ -#define PWR_REGULATOR_VOLTAGE_SCALE4 (0U) /*!< Voltage scaling range 4 */ -/** - * @} - */ - -/** @defgroup PWREx_VBAT_Battery_Charging_Selection PWR Extended Battery Charging Resistor Selection - * @{ - */ -#define PWR_BATTERY_CHARGING_RESISTOR_5 (0U) /*!< VBAT charging through a 5 kOhms resistor */ -#define PWR_BATTERY_CHARGING_RESISTOR_1_5 PWR_BDCR2_VBRS /*!< VBAT charging through a 1.5 kOhms resistor */ -/** - * @} - */ - -/** @defgroup PWREx_GPIO_Port PWR Extended GPIO Port - * @{ - */ -#define PWR_GPIO_A (0x00U) /*!< GPIO port A */ -#define PWR_GPIO_B (0x01U) /*!< GPIO port B */ -#define PWR_GPIO_C (0x02U) /*!< GPIO port C */ -#define PWR_GPIO_D (0x03U) /*!< GPIO port D */ -#define PWR_GPIO_E (0x04U) /*!< GPIO port E */ -#if defined (PWR_PUCRF_PU0) -#define PWR_GPIO_F (0x05U) /*!< GPIO port F */ -#endif /* PWR_PUCRF_PU0 */ -#define PWR_GPIO_G (0x06U) /*!< GPIO port G */ -#define PWR_GPIO_H (0x07U) /*!< GPIO port H */ -#if defined (PWR_PUCRI_PU0) -#define PWR_GPIO_I (0x08U) /*!< GPIO port I */ -#endif /* PWR_PUCRI_PU0 */ -#if defined (PWR_PUCRJ_PU0) -#define PWR_GPIO_J (0x09U) /*!< GPIO port J */ -#endif /* defined (PWR_PUCRJ_PU0) */ -/** - * @} - */ - -/** @defgroup PWREx_GPIO_Pin_Mask PWR Extended GPIO Pin Mask - * @{ - */ -#define PWR_GPIO_BIT_0 (0x0001U) /*!< GPIO port I/O pin 0 */ -#define PWR_GPIO_BIT_1 (0x0002U) /*!< GPIO port I/O pin 1 */ -#define PWR_GPIO_BIT_2 (0x0004U) /*!< GPIO port I/O pin 2 */ -#define PWR_GPIO_BIT_3 (0x0008U) /*!< GPIO port I/O pin 3 */ -#define PWR_GPIO_BIT_4 (0x0010U) /*!< GPIO port I/O pin 4 */ -#define PWR_GPIO_BIT_5 (0x0020U) /*!< GPIO port I/O pin 5 */ -#define PWR_GPIO_BIT_6 (0x0040U) /*!< GPIO port I/O pin 6 */ -#define PWR_GPIO_BIT_7 (0x0080U) /*!< GPIO port I/O pin 7 */ -#define PWR_GPIO_BIT_8 (0x0100U) /*!< GPIO port I/O pin 8 */ -#define PWR_GPIO_BIT_9 (0x0200U) /*!< GPIO port I/O pin 9 */ -#define PWR_GPIO_BIT_10 (0x0400U) /*!< GPIO port I/O pin 10 */ -#define PWR_GPIO_BIT_11 (0x0800U) /*!< GPIO port I/O pin 11 */ -#define PWR_GPIO_BIT_12 (0x1000U) /*!< GPIO port I/O pin 12 */ -#define PWR_GPIO_BIT_13 (0x2000U) /*!< GPIO port I/O pin 13 */ -#define PWR_GPIO_BIT_14 (0x4000U) /*!< GPIO port I/O pin 14 */ -#define PWR_GPIO_BIT_15 (0x8000U) /*!< GPIO port I/O pin 15 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros - * @{ - */ - -/** - * @brief Enable the UVM Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Disable the UVM Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Enable the UVM Event Line. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Disable the UVM Event Line. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Enable the UVM Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Disable the UVM Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Enable the UVM Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Disable the UVM Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_UVM) - -/** - * @brief Enable the UVM Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the UVM Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software Interrupt on UVM EXTI Line. - * @retval None - */ -#define __HAL_PWR_UVM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_UVM) - -/** - * @brief Check whether the specified UVM EXTI flag is set or not. - * @retval EXTI UVM Line Status. - */ -#define __HAL_PWR_UVM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_UVM) - -/** - * @brief Clear the UVM EXTI flag. - * @retval None. - */ -#define __HAL_PWR_UVM_EXTI_CLEAR_FLAG() \ - do \ - { \ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); \ - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); \ - } while(0) - -/** - * @brief Enable the IO2VM Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Disable the IO2VM Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Enable the IO2VM Event Line. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Disable the IO2VM Event Line. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Enable the IO2VM Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Disable the IO2VM Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Enable the IO2VM Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Disable the IO2VM Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Enable the IO2VM Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the IO2VM Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software Interrupt on IO2VM EXTI Line. - * @retval None - */ -#define __HAL_PWR_IO2VM_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_IO2VM) - -/** - * @brief Check whether the specified IO2VM EXTI flag is set or not. - * @retval EXTI IO2VM Line Status. - */ -#define __HAL_PWR_IO2VM_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_IO2VM) - -/** - * @brief Clear the IO2VM EXTI flag. - * @retval None. - */ -#define __HAL_PWR_IO2VM_EXTI_CLEAR_FLAG() \ - do \ - { \ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); \ - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); \ - } while(0) - -/** - * @brief Enable the AVM1 Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Disable the AVM1 Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Enable the AVM1 Event Line. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Disable the AVM1 Event Line. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Enable the AVM1 Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Disable the AVM1 Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Enable the AVM1 Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Disable the AVM1 Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Enable the AVM1 Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the AVM1 Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software Interrupt on AVM1 EXTI Line. - * @retval None - */ -#define __HAL_PWR_AVM1_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM1) - -/** - * @brief Check whether the specified AVM1 EXTI flag is set or not. - * @retval EXTI AVM1 Line Status. - */ -#define __HAL_PWR_AVM1_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM1) - -/** - * @brief Clear the AVM1 EXTI flag. - * @retval None. - */ -#define __HAL_PWR_AVM1_EXTI_CLEAR_FLAG() \ - do \ - { \ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); \ - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); \ - } while(0) - -/** - * @brief Enable the AVM2 Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Disable the AVM2 Extended Interrupt Line. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Enable the AVM2 Event Line. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Disable the AVM2 Event Line. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Enable the AVM2 Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Disable the AVM2 Extended Interrupt Rising Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Enable the AVM2 Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Disable the AVM2 Extended Interrupt Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Enable the AVM2 Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_ENABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); \ - __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Disable the AVM2 Extended Interrupt Rising & Falling Trigger. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_DISABLE_RISING_FALLING_EDGE() \ - do \ - { \ - __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); \ - __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); \ - } while(0) - -/** - * @brief Generate a Software Interrupt on AVM2 EXTI Line. - * @retval None - */ -#define __HAL_PWR_AVM2_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER1, PWR_EXTI_LINE_AVM2) - -/** - * @brief Check whether the specified AVM2 EXTI flag is set or not. - * @retval EXTI AVM2 Line Status. - */ -#define __HAL_PWR_AVM2_EXTI_GET_FLAG() ((EXTI->RPR1 | EXTI->FPR1) & PWR_EXTI_LINE_AVM2) - -/** - * @brief Clear the AVM2 EXTI flag. - * @retval None. - */ -#define __HAL_PWR_AVM2_EXTI_CLEAR_FLAG() \ - do \ - { \ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); \ - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); \ - } while(0) - -/** - * @brief Configure the main internal regulator output voltage. - * @note This macro is similar to HAL_PWREx_ControlVoltageScaling() API but - * doesn't check whether or not VOSREADY flag is set. User may resort - * to __HAL_PWR_GET_FLAG() macro to check VOSF bit state. - * @param __REGULATOR__ : Specifies the regulator output voltage to achieve a - * tradeoff between performance and power consumption. - * This parameter can be one of the following values : - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. - * Provides a typical output voltage at 1.2 V. - * Used when system clock frequency is up to 160 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. - * Provides a typical output voltage at 1.1 V. - * Used when system clock frequency is up to 100 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. - * Provides a typical output voltage at 1.0 V. - * Used when system clock frequency is up to 50 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4. - * Provides a typical output voltage at 0.9 V. - * Used when system clock frequency is up to 24 MHz. - * @retval None. - */ -#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) \ - do \ - { \ - __IO uint32_t tmpreg; \ - MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, (__REGULATOR__)); \ - tmpreg = READ_BIT(PWR->VOSR, PWR_VOSR_VOS); \ - UNUSED(tmpreg); \ - } while(0) -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ - -/** @addtogroup PWREx_Private_Constants PWR Extended Private Constants - * @{ - */ -/* PVM extended interrupts and event lines defines */ -#define PWR_EXTI_LINE_UVM (0x00080000UL) /* UVM EXTI Line */ -#define PWR_EXTI_LINE_IO2VM (0x00100000UL) /* IO2VM EXTI Line */ -#define PWR_EXTI_LINE_AVM1 (0x00200000UL) /* AVM1 EXTI Line */ -#define PWR_EXTI_LINE_AVM2 (0x00400000UL) /* AVM2 EXTI Line */ - -/* SRAM retention IDs */ -#define SRAM_ID_MASK (0xFFFFUL << 16U) -#define SRAM1_ID (0x01UL << 16U) -#define SRAM2_ID (0x01UL << 17U) -#if defined (PWR_CR2_SRAM3PDS1) -#define SRAM3_ID (0x01UL << 18U) -#endif /* PWR_CR2_SRAM3PDS1 */ -#define SRAM4_ID (0x01UL << 19U) -#define ICACHERAM_ID (0x01UL << 20U) -#define DCACHE1RAM_ID (0x01UL << 21U) -#if defined (PWR_CR2_DMA2DRAMPDS) -#define DMA2DRAM_ID (0x01UL << 22U) -#endif /* PWR_CR2_DMA2DRAMPDS */ -#define PERIPHRAM_ID (0x01UL << 23U) -#define PKARAM_ID (0x01UL << 24U) -#if defined (PWR_CR2_DC2RAMPDS) -#define DCACHE2RAM_ID (0x01UL << 25U) -#endif /* defined (PWR_CR2_DC2RAMPDS) */ -#if defined (PWR_CR2_GPRAMPDS) -#define GRAPHIPRAM_ID (0x01UL << 26U) -#endif /* defined (PWR_CR2_GPRAMPDS) */ -#if defined (PWR_CR2_DSIRAMPDS) -#define DSIRAM_ID (0x01UL << 27U) -#endif /* defined (PWR_CR2_DSIRAMPDS) */ -#if defined (PWR_CR4_SRAM5PDS1) -#define SRAM5_ID (0x01UL << 28U) -#endif /* defined (PWR_CR4_SRAM5PDS1) */ -#if defined (PWR_CR5_SRAM6PDS1) -#define SRAM6_ID (0x01UL << 29U) -#endif /* defined (PWR_CR5_SRAM6PDS1) */ -#if defined (PWR_CR2_JPEGRAMPDS) -#define JPEGRAM_ID (0x01UL << 30U) -#endif /* defined (PWR_CR2_JPEGRAMPDS)*/ - -/* SRAM page retention IDs */ -#define PAGE01_ID (0x01UL << 0U) -#define PAGE02_ID (0x01UL << 1U) -#define PAGE03_ID (0x01UL << 2U) -#define PAGE04_ID (0x01UL << 3U) -#define PAGE05_ID (0x01UL << 4U) -#define PAGE06_ID (0x01UL << 5U) -#define PAGE07_ID (0x01UL << 6U) -#define PAGE08_ID (0x01UL << 7U) -#define PAGE09_ID (0x01UL << 8U) -#define PAGE10_ID (0x01UL << 9U) -#define PAGE11_ID (0x01UL << 10U) -#define PAGE12_ID (0x01UL << 11U) -#define PAGE13_ID (0x01UL << 12U) - -/* All available RAM retention in Run mode define */ -#if defined (PWR_CR1_SRAM6PD) -#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ - PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ - PWR_SRAM5_FULL_RUN | PWR_SRAM6_FULL_RUN) -#elif defined (PWR_CR1_SRAM5PD) -#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ - PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN | \ - PWR_SRAM5_FULL_RUN) -#elif defined (PWR_CR2_SRAM3PDS1) -#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ - PWR_SRAM3_FULL_RUN | PWR_SRAM4_FULL_RUN) -#else -#define PWR_ALL_RAM_RUN_MASK (PWR_SRAM1_FULL_RUN | PWR_SRAM2_FULL_RUN | \ - PWR_SRAM4_FULL_RUN) -#endif /* defined (PWR_CR1_SRAM5PD) */ -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ - -/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros - * @{ - */ -/* PVM type check macro */ -#define IS_PWR_PVM_TYPE(TYPE) \ - (((TYPE) == PWR_UVM ) ||\ - ((TYPE) == PWR_IO2VM) ||\ - ((TYPE) == PWR_AVM1) ||\ - ((TYPE) == PWR_AVM2)) - -/* PVM mode check macro */ -#define IS_PWR_PVM_MODE(MODE) \ - (((MODE) == PWR_PVM_MODE_NORMAL) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_IT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_IT_RISING_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_FALLING) ||\ - ((MODE) == PWR_PVM_MODE_EVENT_RISING_FALLING)) - -/* SRD state check macro */ -#define IS_PWR_SRD_STATE(SRD_STATE) \ - (((SRD_STATE) == PWR_SRD_DOMAIN_STOP) ||\ - ((SRD_STATE) == PWR_SRD_DOMAIN_RUN)) - -/* Supply selection check macro */ -#define IS_PWR_SUPPLY(PWR_SOURCE) \ - (((PWR_SOURCE) == PWR_LDO_SUPPLY) ||\ - ((PWR_SOURCE) == PWR_SMPS_SUPPLY)) - -/* Voltage scaling range check macro */ -#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) \ - (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) ||\ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) ||\ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3) ||\ - ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE4)) - -/* Battery charging resistor selection check macro */ -#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) \ - (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ - ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) - -/* GPIO port check macro */ -#if defined (PWR_PUCRJ_PU0) -#define IS_PWR_GPIO_PORT(GPIO_PORT) \ - (((GPIO_PORT) == PWR_GPIO_A) ||\ - ((GPIO_PORT) == PWR_GPIO_B) ||\ - ((GPIO_PORT) == PWR_GPIO_C) ||\ - ((GPIO_PORT) == PWR_GPIO_D) ||\ - ((GPIO_PORT) == PWR_GPIO_E) ||\ - ((GPIO_PORT) == PWR_GPIO_F) ||\ - ((GPIO_PORT) == PWR_GPIO_G) ||\ - ((GPIO_PORT) == PWR_GPIO_H) ||\ - ((GPIO_PORT) == PWR_GPIO_I) ||\ - ((GPIO_PORT) == PWR_GPIO_J)) -#elif defined (PWR_PUCRF_PU0) && defined (PWR_PUCRI_PU0) -#define IS_PWR_GPIO_PORT(GPIO_PORT) \ - (((GPIO_PORT) == PWR_GPIO_A) ||\ - ((GPIO_PORT) == PWR_GPIO_B) ||\ - ((GPIO_PORT) == PWR_GPIO_C) ||\ - ((GPIO_PORT) == PWR_GPIO_D) ||\ - ((GPIO_PORT) == PWR_GPIO_E) ||\ - ((GPIO_PORT) == PWR_GPIO_F) ||\ - ((GPIO_PORT) == PWR_GPIO_G) ||\ - ((GPIO_PORT) == PWR_GPIO_H) ||\ - ((GPIO_PORT) == PWR_GPIO_I)) -#else -#define IS_PWR_GPIO_PORT(GPIO_PORT) \ - (((GPIO_PORT) == PWR_GPIO_A) ||\ - ((GPIO_PORT) == PWR_GPIO_B) ||\ - ((GPIO_PORT) == PWR_GPIO_C) ||\ - ((GPIO_PORT) == PWR_GPIO_D) ||\ - ((GPIO_PORT) == PWR_GPIO_E) ||\ - ((GPIO_PORT) == PWR_GPIO_G) ||\ - ((GPIO_PORT) == PWR_GPIO_H)) -#endif /* defined (PWR_PUCRJ_PU0) */ - -/* GPIO pin mask check macro */ -#define IS_PWR_GPIO_PIN_MASK(BIT_MASK) \ - ((((BIT_MASK) & GPIO_PIN_MASK) != 0U) && ((BIT_MASK) <= GPIO_PIN_MASK)) - -/* SRAM2 retention in Standby mode check macro */ -#define IS_PWR_SRAM2_STANDBY_RETENTION(CONTENT) \ - (((CONTENT) == PWR_SRAM2_PAGE1_STANDBY) ||\ - ((CONTENT) == PWR_SRAM2_PAGE2_STANDBY) ||\ - ((CONTENT) == PWR_SRAM2_FULL_STANDBY)) - -/* RAMs retention in Stop mode check macros */ -#define IS_PWR_SRAM1_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#define IS_PWR_SRAM2_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#if defined (PWR_CR2_SRAM3PDS1) -#define IS_PWR_SRAM3_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM3_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* PWR_CR2_SRAM3PDS1 */ - -#define IS_PWR_SRAM4_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM4_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#if defined (PWR_CR4_SRAM5PDS1) -#define IS_PWR_SRAM5_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM5_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* defined (PWR_CR4_SRAM5PDS1) */ - -#if defined (PWR_CR5_SRAM6PDS1) -#define IS_PWR_SRAM6_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_SRAM6_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* defined (PWR_CR5_SRAM6PDS1) */ - -#define IS_PWR_ICACHE_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_ICACHE_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#define IS_PWR_DCACHE1_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DCACHE1_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#if defined (PWR_CR2_DC2RAMPDS) -#define IS_PWR_DCACHE2_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DCACHE2_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* defined (PWR_CR2_DC2RAMPDS) */ - -#if defined (PWR_CR2_DMA2DRAMPDS) -#define IS_PWR_DMA2DRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DMA2DRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* PWR_CR2_DMA2DRAMPDS */ - -#define IS_PWR_PERIPHRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_PERIPHRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#define IS_PWR_PKA32RAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_PKA32RAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) - -#if defined (PWR_CR2_GPRAMPDS) -#define IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_GRAPHICPRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* defined (PWR_CR2_GPRAMPDS) */ - -#if defined (PWR_CR2_DSIRAMPDS) -#define IS_PWR_DSIRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_DSIRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* defined (PWR_CR2_DSIRAMPDS) */ - -#if defined (PWR_CR2_JPEGRAMPDS) -#define IS_PWR_JPEGRAM_STOP_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_JPEGRAM_FULL_STOP)) == 0U) && ((RAMCONTENT) != 0U)) -#endif /* defined (PWR_CR2_DSIRAMPDS) */ - -/* RAMs retention in Run mode check macro */ -#define IS_PWR_RAM_RUN_RETENTION(RAMCONTENT) \ - ((((RAMCONTENT) & (~PWR_ALL_RAM_RUN_MASK)) == 0U) && ((RAMCONTENT) != 0U)) -/** - * @} - */ - -/** @addtogroup PWREx_Exported_Functions PWR Extended Exported Functions - * @{ - */ - -/** @addtogroup PWREx_Exported_Functions_Group1 Power Supply Control Functions - * @{ - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); -uint32_t HAL_PWREx_GetVoltageRange(void); -HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource); -uint32_t HAL_PWREx_GetSupplyConfig(void); -void HAL_PWREx_EnableFastSoftStart(void); -void HAL_PWREx_DisableFastSoftStart(void); -/** - * @} - */ - -/** @addtogroup PWREx_Exported_Functions_Group2 Low Power Control Functions - * @{ - */ -void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry); -void HAL_PWREx_EnterSHUTDOWNMode(void); -void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState); -void HAL_PWREx_EnableUltraLowPowerMode(void); -void HAL_PWREx_DisableUltraLowPowerMode(void); -void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin); -void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin); -/** - * @} - */ - -/** @addtogroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions - * @{ - */ -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue); -void HAL_PWREx_DisableBatteryCharging(void); -void HAL_PWREx_EnableVddUSB(void); -void HAL_PWREx_DisableVddUSB(void); -void HAL_PWREx_EnableVddIO2(void); -void HAL_PWREx_DisableVddIO2(void); -void HAL_PWREx_EnableVddA(void); -void HAL_PWREx_DisableVddA(void); -void HAL_PWREx_EnableUVM(void); -void HAL_PWREx_DisableUVM(void); -void HAL_PWREx_EnableIO2VM(void); -void HAL_PWREx_DisableIO2VM(void); -void HAL_PWREx_EnableAVM1(void); -void HAL_PWREx_DisableAVM1(void); -void HAL_PWREx_EnableAVM2(void); -void HAL_PWREx_DisableAVM2(void); -#if defined (PWR_VOSR_USBPWREN) -HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void); -void HAL_PWREx_DisableUSBHSTranceiverSupply(void); -#endif /* defined (PWR_VOSR_USBPWREN) */ -#if defined (PWR_CR1_FORCE_USBPWR) -void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void); -void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void); -#endif /* defined (PWR_CR1_FORCE_USBPWR) */ -#if defined (PWR_VOSR_VDD11USBDIS) -void HAL_PWREx_EnableVDD11USB(void); -void HAL_PWREx_DisableVDD11USB(void); -#endif /* defined (PWR_VOSR_VDD11USBDIS) */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM); -void HAL_PWREx_EnableMonitoring(void); -void HAL_PWREx_DisableMonitoring(void); -void HAL_PWREx_EnableUCPDStandbyMode(void); -void HAL_PWREx_DisableUCPDStandbyMode(void); -void HAL_PWREx_EnableUCPDDeadBattery(void); -void HAL_PWREx_DisableUCPDDeadBattery(void); -void HAL_PWREx_PVD_PVM_IRQHandler(void); -void HAL_PWREx_UVMCallback(void); -void HAL_PWREx_IO2VMCallback(void); -void HAL_PWREx_AVM1Callback(void); -void HAL_PWREx_AVM2Callback(void); -/** - * @} - */ - -/** @addtogroup PWREx_Exported_Functions_Group4 Memories Retention Functions - * @{ - */ -void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); -void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages); -void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection); -void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection); -void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection); -void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection); -void HAL_PWREx_EnableFlashFastWakeUp(void); -void HAL_PWREx_DisableFlashFastWakeUp(void); -void HAL_PWREx_EnableSRAM4FastWakeUp(void); -void HAL_PWREx_DisableSRAM4FastWakeUp(void); -HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void); -void HAL_PWREx_DisableBkupRAMRetention(void); -/** - * @} - */ - -/** @addtogroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions - * @{ - */ -void HAL_PWREx_EnablePullUpPullDownConfig(void); -void HAL_PWREx_DisablePullUpPullDownConfig(void); -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin); -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* STM32U5xx_HAL_PWR_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h deleted file mode 100644 index 394d30d5f..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc.h +++ /dev/null @@ -1,4843 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_rcc.h - * @author MCD Application Team - * @brief Header file of RCC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_RCC_H -#define STM32U5xx_HAL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCC_Exported_Types RCC Exported Types - * @{ - */ - -/** - * @brief RCC PLL configuration structure definition - */ -typedef struct -{ - uint32_t PLLState; /*!< The new state of the PLL. - This parameter can be a value of @ref RCC_PLL_Config */ - - uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 16 */ - - uint32_t PLLMBOOST; /*!< PLLMBOOST: Prescaler for EPOD booster input clock. - This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider */ - - uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ - - uint32_t PLLP; /*!< PLLP: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLLQ; /*!< PLLQ: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLLR; /*!< PLLR: Division factor for system clock. - This parameter must be a number between Min_Data = 2 and Max_Data = 128 - Only division by 1 and even division factors are allowed */ - - uint32_t PLLRGE; /*!< PLLRGE: PLL1 clock Input range - This parameter must be a value of @ref RCC_PLL_VCI_Range */ - - uint32_t PLLFRACN; /*!< PLLFRACN: Specifies Fractional Part Of The Multiplication Factor for - PLL1 VCO It should be a value between 0 and 8191 */ - -} RCC_PLLInitTypeDef; - -/** - * @brief RCC Internal/External Oscillator (HSE, HSI, MSI, LSE and LSI) configuration structure definition - */ -typedef struct -{ - uint32_t OscillatorType; /*!< The oscillators to be configured. - This parameter can be a value of @ref RCC_Oscillator_Type */ - - uint32_t HSEState; /*!< The new state of the HSE. - This parameter can be a value of @ref RCC_HSE_Config */ - - uint32_t LSEState; /*!< The new state of the LSE. - This parameter can be a value of @ref RCC_LSE_Config */ - - uint32_t HSIState; /*!< The new state of the HSI. - This parameter can be a value of @ref RCC_HSI_Config */ - - uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F - on the other devices */ - - uint32_t LSIState; /*!< The new state of the LSI. - This parameter can be a value of @ref RCC_LSI_Config */ - - uint32_t LSIDiv; /*!< The division factor of the LSI. - This parameter can be a value of @ref RCC_LSI_Div */ - - uint32_t MSIState; /*!< The new state of the MSI. - This parameter can be a value of @ref RCC_MSI_Config */ - - uint32_t MSICalibrationValue; /*!< The calibration trimming value (default is RCC_MSICALIBRATION_DEFAULT). - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t MSIClockRange; /*!< The MSI frequency range. - This parameter can be a value of @ref RCC_MSI_Clock_Range */ - - uint32_t MSIKClockRange; /*!< The MSIK frequency range. - This parameter can be a value of @ref RCC_MSIK_Clock_Range */ - - uint32_t HSI48State; /*!< The new state of the HSI48. - This parameter can be a value of @ref RCC_HSI48_Config */ - - uint32_t SHSIState; /*!< The new state of the SHSI. - This parameter can be a value of @ref RCC_SHSI_Config */ - - uint32_t MSIKState; /*!< The new state of the MSIK. - This parameter can be a value of @ref RCC_MSIK_Config */ - - RCC_PLLInitTypeDef PLL; /*!< Main PLL structure parameters */ - -} RCC_OscInitTypeDef; - -/** - * @brief RCC System, AHB and APB busses clock configuration structure definition - */ -typedef struct -{ - uint32_t ClockType; /*!< The clock to be configured. - This parameter can be a value of @ref RCC_System_Clock_Type */ - - uint32_t SYSCLKSource; /*!< The clock source used as system clock (SYSCLK). - This parameter can be a value of @ref RCC_System_Clock_Source */ - - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock - (SYSCLK). - This parameter can be a value of @ref RCC_AHB_Clock_Source */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ - - uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_APB1_APB2_APB3_Clock_Source */ -} RCC_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_Exported_Constants RCC Exported Constants - * @{ - */ -#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT -#define HSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define MSI_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ - -/* Defines used for Flags */ -#define CR_REG_INDEX (1U) -#define BDCR_REG_INDEX (2U) -#define CSR_REG_INDEX (3U) -#define CRRCR_REG_INDEX (4U) - -#define RCC_FLAG_MASK (0x1FU) -/** - * @} - */ - -/** @defgroup RCC_Reset_Flag Reset Flag - * @{ - */ -#define RCC_RESET_FLAG_OBL RCC_CSR_OBLRSTF /*!< Option Byte Loader reset flag */ -#define RCC_RESET_FLAG_PIN RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define RCC_RESET_FLAG_PWR RCC_CSR_BORRSTF /*!< BOR or POR/PDR reset flag */ -#define RCC_RESET_FLAG_SW RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define RCC_RESET_FLAG_IWDG RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#define RCC_RESET_FLAG_WWDG RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#define RCC_RESET_FLAG_LPWR RCC_CSR_LPWRRSTF /*!< Low power reset flag */ -#define RCC_RESET_FLAG_ALL (RCC_RESET_FLAG_OBL | RCC_RESET_FLAG_PIN | RCC_RESET_FLAG_PWR | \ - RCC_RESET_FLAG_SW | RCC_RESET_FLAG_IWDG | RCC_RESET_FLAG_WWDG | \ - RCC_RESET_FLAG_LPWR) -/** - * @} - */ - -/** @defgroup RCC_Timeout_Value Timeout Values - * @{ - */ -#define RCC_DBP_TIMEOUT_VALUE (2U) /* 2 ms (minimum Tick + 1) */ -#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT -/** - * @} - */ - -/** @defgroup RCC_Oscillator_Type Oscillator Type - * @{ - */ -#define RCC_OSCILLATORTYPE_NONE 0x0UL /*!< Oscillator configuration unchanged */ -#define RCC_OSCILLATORTYPE_HSE 0x1UL /*!< HSE to configure */ -#define RCC_OSCILLATORTYPE_HSI 0x2UL /*!< HSI to configure */ -#define RCC_OSCILLATORTYPE_LSE 0x4UL /*!< LSE to configure */ -#define RCC_OSCILLATORTYPE_LSI 0x8UL /*!< LSI to configure */ -#define RCC_OSCILLATORTYPE_MSI 0x10UL /*!< MSI to configure */ -#define RCC_OSCILLATORTYPE_HSI48 0x20UL /*!< HSI48 to configure */ -#define RCC_OSCILLATORTYPE_MSIK 0x040U /*!< MSIK to configure */ -#define RCC_OSCILLATORTYPE_SHSI 0x80UL /*!< SHSI to configure */ -/* Defines Oscillator Masks */ -#define RCC_OSCILLATORTYPE_ALL (RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_MSIK | \ - RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_SHSI) /*!< All Oscillator to configure */ -/** - * @} - */ - -/** @defgroup RCC_HSE_Config HSE Config - * @{ - */ -#define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */ -#define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */ -#define RCC_HSE_BYPASS (RCC_CR_HSEBYP | RCC_CR_HSEON) /*!< External clock source for HSE clock */ -#define RCC_HSE_BYPASS_DIGITAL (RCC_CR_HSEEXT | RCC_CR_HSEBYP | RCC_CR_HSEON) -/** - * @} - */ - -/** @defgroup RCC_LSE_Config LSE Config - * @{ - */ -#define RCC_LSE_OFF 0U /*!< LSE clock deactivation */ -#define RCC_LSE_ON_RTC_ONLY RCC_BDCR_LSEON /*!< LSE clock activation for RTC only */ -#define RCC_LSE_ON (RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< LSE clock activation for RCC and peripherals */ -#define RCC_LSE_BYPASS_RTC_ONLY (RCC_BDCR_LSEBYP | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ -#define RCC_LSE_BYPASS (RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN | RCC_BDCR_LSEON) /*!< External clock source for LSE clock */ -/** - * @} - */ - -/** @defgroup RCC_HSI_Config HSI Config - * @{ - */ -#define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */ -#define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */ -#define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Config LSI Config - * @{ - */ -#define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */ -#define RCC_LSI_ON RCC_BDCR_LSION /*!< LSI clock activation */ -/** - * @} - */ - -/** @defgroup RCC_LSI_Div LSI Div - * @{ - */ -#define RCC_LSI_DIV1 0U /*!< LSI clock is not divided */ -#define RCC_LSI_DIV128 RCC_BDCR_LSIPREDIV /*!< LSI clock is divided by 128 */ -/** - * @} - */ - -/** @defgroup RCC_MSI_Config MSI Config - * @{ - */ -#define RCC_MSI_OFF 0x00000000U /*!< MSI clock deactivation */ -#define RCC_MSI_ON RCC_CR_MSISON /*!< MSI clock activation */ - -#define RCC_MSICALIBRATION_DEFAULT 0x10U /*!< Default MSI calibration trimming value */ -/** - * @} - */ - -/** @defgroup RCC_HSI48_Config HSI48 Config - * @{ - */ -#define RCC_HSI48_OFF 0x00000000U /*!< HSI48 clock deactivation */ -#define RCC_HSI48_ON RCC_CR_HSI48ON /*!< HSI48 clock activation */ -/** - * @} - */ - -/** @defgroup RCC_MSIK_Config MSIK Config - * @{ - */ -#define RCC_MSIK_OFF 0x00000000U /*!< MSIK clock deactivation */ -#define RCC_MSIK_ON RCC_CR_MSIKON /*!< MSIK clock activation */ -/** - * @} - */ - -/** @defgroup RCC_SHSI_Config SHSI Config - * @{ - */ -#define RCC_SHSI_OFF 0x00000000U /*!< SHSI clock deactivation */ -#define RCC_SHSI_ON RCC_CR_SHSION /*!< SHSI clock activation */ -/** - * @} - */ - -/** @defgroup RCC_PLL_Config RCC PLL Config - * @{ - */ -#define RCC_PLL_NONE 0x00000000U -#define RCC_PLL_OFF 0x00000001U -#define RCC_PLL_ON 0x00000002U -/** - * @} - */ - - -/** @defgroup RCC_PLL_Clock_Output RCC PLL Clock Output - * @{ - */ -#define RCC_PLL1_DIVP RCC_PLL1CFGR_PLL1PEN -#define RCC_PLL1_DIVQ RCC_PLL1CFGR_PLL1QEN -#define RCC_PLL1_DIVR RCC_PLL1CFGR_PLL1REN - -/** - * @} - */ - -/** @defgroup RCC_PLLMBOOST_EPOD_Clock_Divider PLLMBOOST EPOD Clock Divider - * @{ - */ -#define RCC_PLLMBOOST_DIV1 0x00000000U -#define RCC_PLLMBOOST_DIV2 RCC_PLL1CFGR_PLL1MBOOST_0 -#define RCC_PLLMBOOST_DIV4 RCC_PLL1CFGR_PLL1MBOOST_1 -#define RCC_PLLMBOOST_DIV6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) -#define RCC_PLLMBOOST_DIV8 RCC_PLL1CFGR_PLL1MBOOST_2 -#define RCC_PLLMBOOST_DIV10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) -#define RCC_PLLMBOOST_DIV12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) -#define RCC_PLLMBOOST_DIV14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1| RCC_PLL1CFGR_PLL1MBOOST_0) -#define RCC_PLLMBOOST_DIV16 RCC_PLL1CFGR_PLL1MBOOST_3 -/** - * @} - */ - -/** @defgroup RCC_PLL_VCI_Range RCC PLL1 VCI Range - * @{ - */ -#define RCC_PLLVCIRANGE_0 0x00000000U -#define RCC_PLLVCIRANGE_1 (RCC_PLL1CFGR_PLL1RGE_1 | RCC_PLL1CFGR_PLL1RGE_0) -/** - * @} - */ - -/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source - * @{ - */ -#define RCC_PLLSOURCE_NONE 0x00000000U -#define RCC_PLLSOURCE_MSI RCC_PLL1CFGR_PLL1SRC_0 -#define RCC_PLLSOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 -#define RCC_PLLSOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) - -/** - * @} - */ - - -/** @defgroup RCC_MSI_Clock_Range MSI Clock Range - * @{ - */ -#define RCC_MSIRANGE_0 0x00000000U /*!< MSI = 48 MHz */ -#define RCC_MSIRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSI = 24 MHz */ -#define RCC_MSIRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSI = 16 MHz */ -#define RCC_MSIRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSI = 12 MHz */ -#define RCC_MSIRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSI = 4 MHz */ -#define RCC_MSIRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 2 MHz */ -#define RCC_MSIRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1.33 MHz */ -#define RCC_MSIRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSI = 1 MHz */ -#define RCC_MSIRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSI = 3.072 MHz */ -#define RCC_MSIRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.536 MHz */ -#define RCC_MSIRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 1.024 MHz */ -#define RCC_MSIRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 768 KHz */ -#define RCC_MSIRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 400 KHz */ -#define RCC_MSIRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 200 KHz */ -#define RCC_MSIRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 133 KHz */ -#define RCC_MSIRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 |\ - RCC_ICSCR1_MSISRANGE_3) /*!< MSI = 100 KHz */ -/** - * @} - */ - -/** @defgroup RCC_MSIK_Clock_Range MSIK Clock Range - * @{ - */ -#define RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ -#define RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ -#define RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ -#define RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ -#define RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ -#define RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ -#define RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.33 MHz */ -#define RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ -#define RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ -#define RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ -#define RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ -#define RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ -#define RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ -#define RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ -#define RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 133 KHz */ -#define RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 |\ - RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Type System Clock Type - * @{ - */ -#define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */ -#define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */ -#define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */ -#define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */ -#define RCC_CLOCKTYPE_PCLK3 0x00000010U /*!< PCLK3 to configure */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source System Clock Source - * @{ - */ -#define RCC_SYSCLKSOURCE_MSI 0x00000000U /*!< MSI selection as system clock */ -#define RCC_SYSCLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI selection as system clock */ -#define RCC_SYSCLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ -#define RCC_SYSCLKSOURCE_PLLCLK (RCC_CFGR1_SW_0 | RCC_CFGR1_SW_1) /*!< PLL1 selection as system clock */ -/** - * @} - */ - -/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status - * @{ - */ -#define RCC_SYSCLKSOURCE_STATUS_MSI 0x00000000U /*!< MSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ -#define RCC_SYSCLKSOURCE_STATUS_PLLCLK (RCC_CFGR1_SWS_0 | RCC_CFGR1_SWS_1) /*!< PLL1 used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_AHB_Clock_Source AHB Clock Source - * @{ - */ -#define RCC_SYSCLK_DIV1 0x00000000U /*!< SYSCLK not divided */ -#define RCC_SYSCLK_DIV2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ -#define RCC_SYSCLK_DIV4 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 4 */ -#define RCC_SYSCLK_DIV8 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 8 */ -#define RCC_SYSCLK_DIV16 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 16 */ -#define RCC_SYSCLK_DIV64 (RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 64 */ -#define RCC_SYSCLK_DIV128 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 128 */ -#define RCC_SYSCLK_DIV256 (RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 256 */ -#define RCC_SYSCLK_DIV512 (RCC_CFGR2_HPRE_0 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_3) /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_APB1_APB2_APB3_Clock_Source APB1 APB2 APB3 Clock Source - * @{ - */ -#define RCC_HCLK_DIV1 (0x00000000U) /*!< HCLK not divided */ -#define RCC_HCLK_DIV2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ -#define RCC_HCLK_DIV4 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 4 */ -#define RCC_HCLK_DIV8 (RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 8 */ -#define RCC_HCLK_DIV16 (RCC_CFGR2_PPRE1_0 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_2) /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Source RTC Clock Source - * @{ - */ -#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_MCO_Index MCO Index - * @{ - */ -#define RCC_MCO1 0x00000000U -#define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/ -/** - * @} - */ - -/** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source - * @{ - */ -#define RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO1 output disabled, no clock on MCO1 */ -#define RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ -#define RCC_MCO1SOURCE_MSI RCC_CFGR1_MCOSEL_1 /*!< MSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ -#define RCC_MCO1SOURCE_PLL1CLK (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_2) /*!< PLL1CLK selection as MCO1 source */ -#define RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ -#define RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0|RCC_CFGR1_MCOSEL_1|RCC_CFGR1_MCOSEL_2) /*!< LSE selection as MCO1 source */ -#define RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ -#define RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0| RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ -/** - * @} - */ - -/** @defgroup RCC_MCOx_Clock_Prescaler MCO1 Clock Prescaler - * @{ - */ -#define RCC_MCODIV_1 0x00000000U /*!< MCO is divided by 1 */ -#define RCC_MCODIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO is divided by 2 */ -#define RCC_MCODIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO is divided by 4 */ -#define RCC_MCODIV_8 (RCC_CFGR1_MCOPRE_0 | RCC_CFGR1_MCOPRE_1)/*!< MCO is divided by 8 */ -#define RCC_MCODIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO is divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_Interrupt Interrupts - * @{ - */ -#define RCC_IT_LSIRDY RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define RCC_IT_LSERDY RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define RCC_IT_MSIRDY RCC_CIFR_MSISRDYF /*!< MSI Ready Interrupt flag */ -#define RCC_IT_HSIRDY RCC_CIFR_HSIRDYF /*!< HSI16 Ready Interrupt flag */ -#define RCC_IT_HSERDY RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ -#define RCC_IT_HSI48RDY RCC_CIFR_HSI48RDYF /*!< HSI48 Ready Interrupt flag */ -#define RCC_IT_PLLRDY RCC_CIFR_PLL1RDYF /*!< PLL1 Ready Interrupt flag */ -#define RCC_IT_PLL2RDY RCC_CIFR_PLL2RDYF /*!< PLL2 Ready Interrupt flag */ -#define RCC_IT_PLL3RDY RCC_CIFR_PLL3RDYF /*!< PLL3 Ready Interrupt flag */ -#define RCC_IT_CSS RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ -#define RCC_IT_MSIKRDY RCC_CIFR_MSIKRDYF /*!< MSIK Ready Interrupt flag */ -#define RCC_IT_SHSIRDY RCC_CIFR_SHSIRDYF /*!< SHSI Ready Interrupt flag */ -/** - * @} - */ - -/** @defgroup RCC_Flag Flags - * Elements values convention: XXXYYYYYb - * - YYYYY : Flag position in the register - * - XXX : Register index - * - 001: CR register - * - 010: BDCR register - * - 011: CSR register - * - 100: CRRCR register - * @{ - */ -/* Flags in the CR register */ -#define RCC_FLAG_MSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSISRDY_Pos)) /*!< MSI Ready flag */ -#define RCC_FLAG_MSIKRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_MSIKRDY_Pos)) /*!< MSI Ready flag */ -#define RCC_FLAG_HSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< HSI Ready flag */ -#define RCC_FLAG_HSERDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< HSE Ready flag */ -#define RCC_FLAG_PLL1RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL1RDY_Pos)) /*!< PLL Ready flag */ -#define RCC_FLAG_PLL2RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL2RDY_Pos)) /*!< PLL2 Ready flag */ -#define RCC_FLAG_PLL3RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_PLL3RDY_Pos)) /*!< PLL3 Ready flag */ -#define RCC_FLAG_SHSIRDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_SHSIRDY_Pos)) /*!< SHSI Ready flag */ -#define RCC_FLAG_HSI48RDY ((uint32_t)((CR_REG_INDEX << 5U) | RCC_CR_HSI48RDY_Pos)) /*!< HSI48 Ready flag */ - -/* Flags in the BDCR register */ -#define RCC_FLAG_LSERDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< LSE Ready flag */ -#define RCC_FLAG_LSESYSRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSESYSRDY_Pos)) /*!< LSESYS Ready flag */ -#define RCC_FLAG_LSECSSD ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSECSSD_Pos)) /*!< LSE Clock Security System Interrupt flag */ -#define RCC_FLAG_LSIRDY ((uint32_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSIRDY_Pos)) /*!< LSI Ready flag */ -/* Flags in the CSR register */ -#define RCC_FLAG_RMVF ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_RMVF_Pos)) /*!< Remove reset flag */ -#define RCC_FLAG_OBLRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_OBLRSTF_Pos)) /*!< Option Byte Loader reset flag */ -#define RCC_FLAG_PINRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */ -#define RCC_FLAG_BORRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_BORRSTF_Pos)) /*!< BOR reset flag */ -#define RCC_FLAG_SFTRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */ -#define RCC_FLAG_IWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */ -#define RCC_FLAG_WWDGRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */ -#define RCC_FLAG_LPWRRST ((uint32_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */ - -/** - * @} - */ - -/** @defgroup RCC_LSEDrive_Config LSE Drive Config - * @{ - */ -#define RCC_LSEDRIVE_LOW 0x00000000U /*!< LSE low drive capability */ -#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< LSE medium low drive capability */ -#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< LSE medium high drive capability */ -#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< LSE high drive capability */ -/** - * @} - */ - -/** @defgroup RCC_Stop_WakeUpClock Wake-Up from STOP Clock - * @{ - */ -#define RCC_STOP_WAKEUPCLOCK_MSI 0x00000000U /*!< MSI selection after wake-up from STOP */ -#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ -/** - * @} - */ - -/** @defgroup RCC_Stop_KernelWakeUpClock RCC Stop KernelWakeUpClock - * @{ - */ -#define RCC_STOP_KERWAKEUPCLOCK_MSI 0x00000000U /*!< MSI kernel clock selection after wake-up from STOP */ -#define RCC_STOP_KERWAKEUPCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI kernel clock selection after wake-up from STOP */ - -/** - * @} - */ - -/** @defgroup RCC_items RCC items - * @brief RCC items to configure attributes on - * @{ - */ -#define RCC_HSI RCC_SECCFGR_HSISEC -#define RCC_HSE RCC_SECCFGR_HSESEC -#define RCC_MSI RCC_SECCFGR_MSISEC -#define RCC_LSI RCC_SECCFGR_LSISEC -#define RCC_LSE RCC_SECCFGR_LSESEC -#define RCC_SYSCLK RCC_SECCFGR_SYSCLKSEC -#define RCC_PRESC RCC_SECCFGR_PRESCSEC -#define RCC_PLL1 RCC_SECCFGR_PLL1SEC -#define RCC_PLL2 RCC_SECCFGR_PLL2SEC -#define RCC_PLL3 RCC_SECCFGR_PLL3SEC -#define RCC_ICLK RCC_SECCFGR_ICLKSEC -#define RCC_HSI48 RCC_SECCFGR_HSI48SEC -#define RCC_RMVF RCC_SECCFGR_RMVFSEC -#define RCC_ALL (RCC_HSI|RCC_HSE|RCC_MSI|RCC_LSI|RCC_LSE|RCC_HSI48| \ - RCC_SYSCLK|RCC_PRESC|RCC_PLL1|RCC_PLL2| \ - RCC_PLL3|RCC_ICLK|RCC_RMVF) -/** - * @} - */ - -/** @defgroup RCC_attributes RCC attributes - * @brief RCC privilege/non-privilege and secure/non-secure attributes - * @{ - */ -#define RCC_NSEC_PRIV 0x00000001U /*!< Non-secure Privilege attribute item */ -#define RCC_NSEC_NPRIV 0x00000002U /*!< Non-secure Non-privilege attribute item */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define RCC_SEC_PRIV 0x00000010U /*!< Secure Privilege attribute item */ -#define RCC_SEC_NPRIV 0x00000020U /*!< Secure Non-privilege attribute item */ -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPDMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_CORDIC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_FMAC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_TSC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_CRC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* JPEG */ - -#define __HAL_RCC_RAMCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN); \ - UNUSED(tmpreg); \ - } while(0) -#define __HAL_RCC_FLASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_MDF1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPU2D */ - -#if defined(DCACHE2) -#define __HAL_RCC_DCACHE2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DCACHE2 */ - -#define __HAL_RCC_GTZC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DCACHE1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SRAM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) - -#define __HAL_RCC_CORDIC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) - -#define __HAL_RCC_FMAC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) - -#define __HAL_RCC_MDF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) - -#define __HAL_RCC_FLASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) - -#define __HAL_RCC_CRC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) - -#define __HAL_RCC_RAMCFG_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) -#endif /* GPU2D */ - -#if defined(DCACHE2) -#define __HAL_RCC_DCACHE2_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) -#endif /* DCACHE2 */ - -#define __HAL_RCC_GTZC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) - -#define __HAL_RCC_BKPSRAM_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) - -#define __HAL_RCC_DCACHE1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) - -#define __HAL_RCC_SRAM1_CLK_DISABLE() CLEAR_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable - * @brief Enable or disable the AHB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GPIOH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined (GPIOI) -#define __HAL_RCC_GPIOI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN); \ - UNUSED(tmpreg); \ - } while(0) - -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DCMI_PSSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN); \ - UNUSED(tmpreg); \ - } while(0) -#if defined (USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_CLK_ENABLE /*!< alias define for compatibility with legacy code */ -#endif /* defined (USB_OTG_FS) */ - -#if defined(RCC_AHB2ENR1_USBPHYCEN) -#define __HAL_RCC_USBPHYC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(PKA) -#define __HAL_RCC_PKA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SDMMC2 */ - -#define __HAL_RCC_SRAM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN); \ - UNUSED(tmpreg); \ - } while(0) -#if defined(SRAM3_BASE) -#define __HAL_RCC_SRAM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SRAM3_BASE */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* OCTOSPI2 */ - -#define __HAL_RCC_GPIOA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) - -#define __HAL_RCC_GPIOB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) - -#define __HAL_RCC_GPIOC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) - -#define __HAL_RCC_GPIOD_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) - -#define __HAL_RCC_GPIOE_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) - -#define __HAL_RCC_GPIOH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) - -#define __HAL_RCC_DCMI_PSSI_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) -#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_CLK_DISABLE /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(RCC_AHB2ENR1_USBPHYCEN) -#define __HAL_RCC_USBPHYC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_USBPHYCEN) -#endif /* defined (RCC_AHB2ENR1_USBPHYCEN) */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) - -#if defined(PKA) -#define __HAL_RCC_PKA_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) -#endif /* SDMMC2 */ - -#define __HAL_RCC_SRAM2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) - -#if defined(SRAM3_BASE) -#define __HAL_RCC_SRAM3_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) -#endif /* SRAM3_BASE */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* HSPI1 */ - -#if defined (SRAM6_BASE) -#define __HAL_RCC_SRAM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SRAM6_BASE */ - -#if defined (SRAM5_BASE) -#define __HAL_RCC_SRAM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SRAM5_BASE */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) -#endif /* HSPI1 */ - -#if defined (SRAM6_BASE) -#define __HAL_RCC_SRAM6_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) -#endif /* SRAM6_BASE */ - -#if defined (SRAM5_BASE) -#define __HAL_RCC_SRAM5_CLK_DISABLE() CLEAR_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) -#endif /* SRAM5_BASE */ -/** - * @} - */ - -/** @defgroup BUS AHB APB Peripheral Clock Enable Disable - * @{ - */ -#define __HAL_RCC_AHB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); - -#define __HAL_RCC_AHB2_1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); - -#define __HAL_RCC_AHB2_2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); - -#define __HAL_RCC_AHB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); - -#define __HAL_RCC_APB1_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); - -#define __HAL_RCC_APB2_CLK_DISABLE() SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); - -#define __HAL_RCC_APB3_CLK_DISABLE() SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); - -#define __HAL_RCC_AHB1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AHB2_1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_AHB2_2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_AHB3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_APB3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); \ - UNUSED(tmpreg); \ - } while(0) - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Enable_Disable AHB3ENR Peripheral Clock Enable Disable - * @brief Enable or disable the AHB3ENR peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_LPGPIO1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_PWR_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ADC4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_DAC1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPDMA1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_ADF1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_GTZC2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SRAM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPGPIO1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) - -#define __HAL_RCC_PWR_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) - -#define __HAL_RCC_ADC4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) - -#define __HAL_RCC_DAC1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) - -#define __HAL_RCC_LPDMA1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) - -#define __HAL_RCC_ADF1_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) - -#define __HAL_RCC_GTZC2_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) - -#define __HAL_RCC_SRAM4_CLK_DISABLE() CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable - * @brief Enable or disable the APB1 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM7_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_WWDG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(USART2) -#define __HAL_RCC_USART2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_UART5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_CRS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN); \ - UNUSED(tmpreg); \ - } while(0) - - -#if defined(USART6) -#define __HAL_RCC_USART6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* UCPD1 */ - -#define __HAL_RCC_TIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) - -#define __HAL_RCC_TIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) - -#define __HAL_RCC_TIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) - -#define __HAL_RCC_TIM5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) - -#define __HAL_RCC_TIM6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) - -#define __HAL_RCC_TIM7_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) - -#define __HAL_RCC_SPI2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) - -#if defined(USART2) -#define __HAL_RCC_USART2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) - -#define __HAL_RCC_UART4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) - -#define __HAL_RCC_UART5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) - -#define __HAL_RCC_I2C1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) - -#define __HAL_RCC_I2C2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) - -#define __HAL_RCC_CRS_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) - -#if defined(USART6) -#define __HAL_RCC_USART6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) - -#define __HAL_RCC_LPTIM2_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_CLK_DISABLE() CLEAR_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) -#endif /* UCPD1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable - * @brief Enable or disable the APB2 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM8_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN); \ - UNUSED(tmpreg); \ - } while(0) - - -#define __HAL_RCC_USART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM15_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM16_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_TIM17_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SAI1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#if defined (SAI2) -#define __HAL_RCC_SAI2_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* SAI2 */ - -#if defined(USB_DRD_FS) -#define __HAL_RCC_USB_FS_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN); \ - UNUSED(tmpreg); \ - } while(0) -#endif /* DSI */ - -#define __HAL_RCC_TIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) - -#define __HAL_RCC_SPI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) - -#define __HAL_RCC_TIM8_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) - -#define __HAL_RCC_USART1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) - -#define __HAL_RCC_TIM15_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) - -#define __HAL_RCC_TIM16_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) - -#define __HAL_RCC_TIM17_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) - -#define __HAL_RCC_SAI1_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) - -#if defined (SAI2) -#define __HAL_RCC_SAI2_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) -#endif /* SAI2 */ - -#if defined (USB_DRD_FS) -#define __HAL_RCC_USB_FS_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_DISABLE() CLEAR_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_APB3_Clock_Enable_Disable APB3 Peripheral Clock Enable Disable - * @brief Enable or disable the APB3 peripheral clock. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SPI3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPUART1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_I2C3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM3_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_LPTIM4_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_OPAMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_COMP_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_VREF_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_RTCAPB_CLK_ENABLE() do { \ - __IO uint32_t tmpreg; \ - SET_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN); \ - UNUSED(tmpreg); \ - } while(0) - -#define __HAL_RCC_SYSCFG_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) - -#define __HAL_RCC_SPI3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) - -#define __HAL_RCC_LPUART1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) - -#define __HAL_RCC_I2C3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) - -#define __HAL_RCC_LPTIM1_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) - -#define __HAL_RCC_LPTIM3_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) - -#define __HAL_RCC_LPTIM4_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) - -#define __HAL_RCC_OPAMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) - -#define __HAL_RCC_COMP_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) - -#define __HAL_RCC_VREF_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) - -#define __HAL_RCC_RTCAPB_CLK_DISABLE() CLEAR_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Enable_Disable_Status AHB1 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB1 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) != 0U) - -#define __HAL_RCC_CORDIC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) != 0U) - -#define __HAL_RCC_FMAC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) != 0U) - -#define __HAL_RCC_MDF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) != 0U) - -#define __HAL_RCC_FLASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) != 0U) - -#define __HAL_RCC_CRC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) != 0U) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) != 0U) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) != 0U) - -#define __HAL_RCC_RAMCFG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) != 0U) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) != 0U) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) != 0U) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) != 0U) -#endif /* GPU2D */ - -#if defined(DCACHE2) -#define __HAL_RCC_DCACHE2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) != 0U) -#endif /* DCACHE2 */ - -#define __HAL_RCC_GTZC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) != 0U) - -#define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) != 0U) - -#define __HAL_RCC_DCACHE1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) != 0U) - -#define __HAL_RCC_SRAM1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) != 0U) - -#define __HAL_RCC_GPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPDMA1EN) == 0U) - -#define __HAL_RCC_CORDIC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CORDICEN) == 0U) - -#define __HAL_RCC_FMAC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FMACEN) == 0U) - -#define __HAL_RCC_MDF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_MDF1EN) == 0U) - -#define __HAL_RCC_FLASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_FLASHEN) == 0U) - -#define __HAL_RCC_CRC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN) == 0U) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_JPEGEN) == 0U) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_TSCEN) == 0U) - -#define __HAL_RCC_RAMCFG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_RAMCFGEN) == 0U) - -#if defined (DMA2D) -#define __HAL_RCC_DMA2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN) == 0U) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GFXMMUEN) == 0U) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPU2DEN) == 0U) -#endif /* GPU2D */ - -#if defined(DCACHE2) -#define __HAL_RCC_DCACHE2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE2EN) == 0U) -#endif /* DCACHE2 */ - -#define __HAL_RCC_GTZC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GTZC1EN) == 0U) - -#define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN) == 0U) - -#define __HAL_RCC_DCACHE1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DCACHE1EN) == 0U) - -#define __HAL_RCC_SRAM1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_SRAM1EN) == 0U) -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripheral_Clock_Enable_Disable_Status AHB2 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB2 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) != 0U) - -#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) != 0U) - -#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) != 0U) - -#define __HAL_RCC_GPIOD_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) != 0U) - -#define __HAL_RCC_GPIOE_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) != 0U) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) != 0U) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) != 0U) - -#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) != 0U) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) != 0U) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) != 0U) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) != 0U) - -#define __HAL_RCC_DCMI_PSSI_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) != 0U) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) != 0U) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED __HAL_RCC_USB_IS_CLK_ENABLED /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) != 0U) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) != 0U) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) != 0U) - -#if defined(PKA) -#define __HAL_RCC_PKA_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) != 0U) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) != 0U) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) != 0U) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) != 0U) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) != 0U) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) != 0U) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) != 0U) -#endif /* SDMMC2 */ - -#define __HAL_RCC_SRAM2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) != 0U) - -#if defined (SRAM3_BASE) -#define __HAL_RCC_SRAM3_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) != 0U) -#endif /* SRAM3_BASE */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) != 0U) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) != 0U) - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) != 0U) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2,RCC_AHB2ENR2_HSPI1EN) != 0U) -#endif /* HSPI1 */ - -#if defined (SRAM6_BASE) -#define __HAL_RCC_SRAM6_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) != 0U) -#endif /* SRAM6_BASE */ - -#if defined (SRAM5_BASE) -#define __HAL_RCC_SRAM5_IS_CLK_ENABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) != 0U) -#endif /* SRAM5_BASE */ - -#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOAEN) == 0U) - -#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOBEN) == 0U) - -#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOCEN) == 0U) - -#define __HAL_RCC_GPIOD_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIODEN) == 0U) - -#define __HAL_RCC_GPIOE_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOEEN) == 0U) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOFEN) == 0U) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOGEN) == 0U) - -#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOHEN) == 0U) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOIEN) == 0U) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_GPIOJEN) == 0U) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_ADC12EN) == 0U) - -#define __HAL_RCC_DCMI_PSSI_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_DCMI_PSSIEN) == 0U) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTGEN) == 0U) -#define __HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED __HAL_RCC_USB_IS_CLK_DISABLED /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(AES) -#define __HAL_RCC_AES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_AESEN) == 0U) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_HASHEN) == 0U) -#endif /* HASH */ - -#define __HAL_RCC_RNG_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_RNGEN) == 0U) - -#if defined(PKA) -#define __HAL_RCC_PKA_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_PKAEN) == 0U) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SAESEN) == 0U) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OCTOSPIMEN) == 0U) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC1EN) == 0U) -#endif /* OTFDEC1 */ - -#if defined (OTFDEC2) -#define __HAL_RCC_OTFDEC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_OTFDEC2EN) == 0U) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC1EN) == 0U) - -#if defined (SDMMC2) -#define __HAL_RCC_SDMMC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SDMMC2EN) == 0U) -#endif /* SDMMC2 */ - -#define __HAL_RCC_SRAM2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM2EN) == 0U) - -#if defined (SRAM3_BASE) -#define __HAL_RCC_SRAM3_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR1, RCC_AHB2ENR1_SRAM3EN) == 0U) -#endif /* SRAM3_BASE */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_FSMCEN) == 0U) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI1EN) == 0U) - -#if defined (OCTOSPI2) -#define __HAL_RCC_OSPI2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_OCTOSPI2EN) == 0U) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_HSPI1EN) == 0U) -#endif /* HSPI1 */ - -#if defined (SRAM6_BASE) -#define __HAL_RCC_SRAM6_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM6EN) == 0U) -#endif /* SRAM6_BASE */ - -#if defined (SRAM5_BASE) -#define __HAL_RCC_SRAM5_IS_CLK_DISABLED() (READ_BIT(RCC->AHB2ENR2, RCC_AHB2ENR2_SRAM5EN) == 0U) -#endif /* SRAM5_BASE */ -/** - * @} - */ - -/** @defgroup RCC_AHB3_Peripheral_Clock_Enable_Disable_Status AHB3 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the AHB3 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_LPGPIO1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) != 0U) - -#define __HAL_RCC_PWR_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) != 0U) - -#define __HAL_RCC_ADC4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) != 0U) - -#define __HAL_RCC_DAC1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) != 0U) - -#define __HAL_RCC_LPDMA1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) != 0U) - -#define __HAL_RCC_ADF1_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) != 0U) - -#define __HAL_RCC_GTZC2_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) != 0U) - -#define __HAL_RCC_SRAM4_IS_CLK_ENABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) != 0U) - -#define __HAL_RCC_LPGPIO1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPGPIO1EN) == 0U) - -#define __HAL_RCC_PWR_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_PWREN) == 0U) - -#define __HAL_RCC_ADC4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADC4EN) == 0U) - -#define __HAL_RCC_DAC1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_DAC1EN) == 0U) - -#define __HAL_RCC_LPDMA1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_LPDMA1EN) == 0U) - -#define __HAL_RCC_ADF1_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_ADF1EN) == 0U) - -#define __HAL_RCC_GTZC2_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_GTZC2EN) == 0U) - -#define __HAL_RCC_SRAM4_IS_CLK_DISABLED() (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_SRAM4EN) == 0U) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB1 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_TIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) != 0U) - -#define __HAL_RCC_TIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) != 0U) - -#define __HAL_RCC_TIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) != 0U) - -#define __HAL_RCC_TIM5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) != 0U) - -#define __HAL_RCC_TIM6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) != 0U) - -#define __HAL_RCC_TIM7_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) != 0U) - -#define __HAL_RCC_WWDG_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_WWDGEN) != 0U) - -#define __HAL_RCC_SPI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) != 0U) - -#if defined(USART2) -#define __HAL_RCC_USART2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) != 0U) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) != 0U) - -#define __HAL_RCC_UART4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) != 0U) - -#define __HAL_RCC_UART5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) != 0U) - -#define __HAL_RCC_I2C1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) != 0U) - -#define __HAL_RCC_I2C2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) != 0U) - -#define __HAL_RCC_CRS_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) != 0U) - -#if defined(USART6) -#define __HAL_RCC_USART6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) != 0U) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) != 0U) - -#define __HAL_RCC_LPTIM2_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) != 0U) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) != 0U) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) != 0U) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) != 0U) - -#if defined (UCPD1) -#define __HAL_RCC_UCPD_IS_CLK_ENABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) != 0U) -#endif /* UCPD1 */ - -#define __HAL_RCC_TIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM2EN) == 0U) - -#define __HAL_RCC_TIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM3EN) == 0U) - -#define __HAL_RCC_TIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM4EN) == 0U) - -#define __HAL_RCC_TIM5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM5EN) == 0U) - -#define __HAL_RCC_TIM6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM6EN) == 0U) - -#define __HAL_RCC_TIM7_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_TIM7EN) == 0U) - -#define __HAL_RCC_SPI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_SPI2EN) == 0U) - -#if defined(USART2) -#define __HAL_RCC_USART2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART2EN) == 0U) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART3EN) == 0U) - -#define __HAL_RCC_UART4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART4EN) == 0U) - -#define __HAL_RCC_UART5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_UART5EN) == 0U) - -#define __HAL_RCC_I2C1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C1EN) == 0U) - -#define __HAL_RCC_I2C2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_I2C2EN) == 0U) - -#define __HAL_RCC_CRS_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_CRSEN) == 0U) - -#if defined(USART6) -#define __HAL_RCC_USART6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR1, RCC_APB1ENR1_USART6EN) == 0U) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C4EN) == 0U) - -#define __HAL_RCC_LPTIM2_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_LPTIM2EN) == 0U) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C5EN) == 0U) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_I2C6EN) == 0U) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_FDCAN1EN) == 0U) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_IS_CLK_DISABLED() (READ_BIT(RCC->APB1ENR2, RCC_APB1ENR2_UCPD1EN) == 0U) -#endif /* UCPD1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB2 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ - -#define __HAL_RCC_TIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) != 0U) - -#define __HAL_RCC_SPI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) != 0U) - -#define __HAL_RCC_TIM8_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) != 0U) - -#define __HAL_RCC_USART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) != 0U) - -#define __HAL_RCC_TIM15_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) != 0U) - -#define __HAL_RCC_TIM16_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) != 0U) - -#define __HAL_RCC_TIM17_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) != 0U) - -#define __HAL_RCC_SAI1_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) != 0U) - -#if defined (SAI2) -#define __HAL_RCC_SAI2_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) != 0U) -#endif /* SAI2 */ - -#if defined (USB_DRD_FS) -#define __HAL_RCC_USB_FS_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) != 0U) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) != 0U) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) != 0U) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_ENABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) != 0U) -#endif /* DSI */ - -#define __HAL_RCC_TIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN) == 0U) - -#define __HAL_RCC_SPI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN) == 0U) - -#define __HAL_RCC_TIM8_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN) == 0U) - -#define __HAL_RCC_USART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN) == 0U) - -#define __HAL_RCC_TIM15_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM15EN) == 0U) - -#define __HAL_RCC_TIM16_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM16EN) == 0U) - -#define __HAL_RCC_TIM17_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM17EN) == 0U) - -#define __HAL_RCC_SAI1_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN) == 0U) - -#if defined (SAI2) -#define __HAL_RCC_SAI2_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN) == 0U) -#endif /* SAI2 */ - -#if defined (USB_DRD_FS) -#define __HAL_RCC_USB_FS_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USBEN) == 0U) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_GFXTIMEN) == 0U) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN) == 0U) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_IS_CLK_DISABLED() (READ_BIT(RCC->APB2ENR, RCC_APB2ENR_DSIHOSTEN) == 0U) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_APB3_Peripheral_Clock_Enable_Disable_Status APB3 Peripheral Clock Enabled or Disabled Status - * @brief Check whether the APB3 peripheral clock is enabled or not. - * @note After reset, the peripheral clock (used for registers read/write access) - * is disabled and the application software has to enable this clock before - * using it. - * @{ - */ -#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) != 0U) - -#define __HAL_RCC_SPI3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) != 0U) - -#define __HAL_RCC_LPUART1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) != 0U) - -#define __HAL_RCC_I2C3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) != 0U) - -#define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) != 0U) - -#define __HAL_RCC_LPTIM3_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) != 0U) - -#define __HAL_RCC_LPTIM4_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) != 0U) - -#define __HAL_RCC_OPAMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) != 0U) - -#define __HAL_RCC_COMP_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) != 0U) - -#define __HAL_RCC_VREF_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) != 0U) - -#define __HAL_RCC_RTCAPB_IS_CLK_ENABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) != 0U) - -#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SYSCFGEN) == 0U) - -#define __HAL_RCC_SPI3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_SPI3EN) == 0U) - -#define __HAL_RCC_LPUART1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPUART1EN) == 0U) - -#define __HAL_RCC_I2C3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_I2C3EN) == 0U) - -#define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM1EN) == 0U) - -#define __HAL_RCC_LPTIM3_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM3EN) == 0U) - -#define __HAL_RCC_LPTIM4_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_LPTIM4EN) == 0U) - -#define __HAL_RCC_OPAMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_OPAMPEN) == 0U) - -#define __HAL_RCC_COMP_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_COMPEN) == 0U) - -#define __HAL_RCC_VREF_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_VREFEN) == 0U) - -#define __HAL_RCC_RTCAPB_IS_CLK_DISABLED() (READ_BIT(RCC->APB3ENR, RCC_APB3ENR_RTCAPBEN) == 0U) -/** - * @} - */ - -/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Peripheral Force Release Reset - * @brief Force or release AHB1 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB1_FORCE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x0007100FU) - -#define __HAL_RCC_GPDMA1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) - -#define __HAL_RCC_CORDIC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) - -#define __HAL_RCC_FMAC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) - -#define __HAL_RCC_MDF1_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) - -#define __HAL_RCC_CRC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) - -#define __HAL_RCC_RAMCFG_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_FORCE_RESET() SET_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) -#endif /* GPU2D */ - -#define __HAL_RCC_AHB1_RELEASE_RESET() WRITE_REG(RCC->AHB1RSTR, 0x00000000U) - -#define __HAL_RCC_GPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPDMA1RST) - -#define __HAL_RCC_CORDIC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CORDICRST) - -#define __HAL_RCC_FMAC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_FMACRST) - -#define __HAL_RCC_MDF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_MDF1RST) - -#define __HAL_RCC_CRC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_CRCRST) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_JPEGRST) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_TSCRST) - -#define __HAL_RCC_RAMCFG_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_RAMCFGRST) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_DMA2DRST) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GFXMMURST) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_RELEASE_RESET() CLEAR_BIT(RCC->AHB1RSTR, RCC_AHB1RSTR_GPU2DRST) -#endif /* GPU2D */ - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Peripheral Force Release Reset - * @brief Force or release AHB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB2_FORCE_RESET() do{\ - WRITE_REG(RCC->AHB2RSTR1, 0x19BF55FFU);\ - WRITE_REG(RCC->AHB2RSTR2, 0x00000111U);\ - }while(0) - -#define __HAL_RCC_GPIOA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) - -#define __HAL_RCC_GPIOB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) - -#define __HAL_RCC_GPIOC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) - -#define __HAL_RCC_GPIOD_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) - -#define __HAL_RCC_GPIOE_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) - -#define __HAL_RCC_GPIOH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) - -#define __HAL_RCC_DCMI_PSSI_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) -#define __HAL_RCC_USB_OTG_FS_FORCE_RESET __HAL_RCC_USB_FORCE_RESET /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(AES) -#define __HAL_RCC_AES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) -#endif /* AES */ - -#define __HAL_RCC_HASH_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) - -#define __HAL_RCC_RNG_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) - -#if defined(PKA) -#define __HAL_RCC_PKA_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) -#endif /* SDMMC2 */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) - -#if defined (OCTOSPI2) -#define __HAL_RCC_OSPI2_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_FORCE_RESET() SET_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) -#endif /* HSPI1 */ - -#define __HAL_RCC_AHB2_RELEASE_RESET() do{\ - WRITE_REG(RCC->AHB2RSTR1, 0x00000000U);\ - WRITE_REG(RCC->AHB2RSTR2, 0x00000000U);\ - }while(0) - -#define __HAL_RCC_GPIOA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOARST) - -#define __HAL_RCC_GPIOB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOBRST) - -#define __HAL_RCC_GPIOC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOCRST) - -#define __HAL_RCC_GPIOD_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIODRST) - -#define __HAL_RCC_GPIOE_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOERST) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOFRST) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOGRST) - -#define __HAL_RCC_GPIOH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOHRST) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOIRST) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_GPIOJRST) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_ADC12RST) - -#define __HAL_RCC_DCMI_PSSI_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_DCMI_PSSIRST) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTGRST) -#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(AES) -#define __HAL_RCC_AES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_AESRST) -#endif /* AES */ - -#define __HAL_RCC_HASH_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_HASHRST) - -#define __HAL_RCC_RNG_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_RNGRST) - -#if defined(PKA) -#define __HAL_RCC_PKA_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_PKARST) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SAESRST) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OSPIM_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OCTOSPIMRST) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC1RST) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_OTFDEC2RST) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC1RST) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR1, RCC_AHB2RSTR1_SDMMC2RST) -#endif /* SDMMC2 */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_FSMCRST) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI1RST) - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_OCTOSPI2RST) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_RELEASE_RESET() CLEAR_BIT(RCC->AHB2RSTR2, RCC_AHB2RSTR2_HSPI1RST) -#endif /* HSPI1 */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Peripheral Force Release Reset - * @brief Force or release AHB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_AHB3_FORCE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000661U) - -#define __HAL_RCC_LPGPIO1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) - -#define __HAL_RCC_ADC4_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) - -#define __HAL_RCC_DAC1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) - -#define __HAL_RCC_LPDMA1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) - -#define __HAL_RCC_ADF1_FORCE_RESET() SET_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) - -#define __HAL_RCC_AHB3_RELEASE_RESET() WRITE_REG(RCC->AHB3RSTR, 0x00000000U) - -#define __HAL_RCC_LPGPIO1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPGPIO1RST) - -#define __HAL_RCC_ADC4_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADC4RST) - -#define __HAL_RCC_DAC1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_DAC1RST) - -#define __HAL_RCC_LPDMA1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_LPDMA1RST) - -#define __HAL_RCC_ADF1_RELEASE_RESET() CLEAR_BIT(RCC->AHB3RSTR, RCC_AHB3RSTR_ADF1RST) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Force_Release_Reset APB1 Peripheral Force Release Reset - * @brief Force or release APB1 peripheral reset. - * @{ - */ - -#define __HAL_RCC_APB1_FORCE_RESET() do { \ - WRITE_REG(RCC->APB1RSTR1, 0x027E403FU); \ - WRITE_REG(RCC->APB1RSTR2, 0x00800222U); \ - } while(0) - -#define __HAL_RCC_TIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) - -#define __HAL_RCC_TIM3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) - -#define __HAL_RCC_TIM4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) - -#define __HAL_RCC_TIM5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) - -#define __HAL_RCC_TIM6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) - -#define __HAL_RCC_TIM7_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) - -#define __HAL_RCC_SPI2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) - -#if defined (USART2) -#define __HAL_RCC_USART2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) - -#define __HAL_RCC_UART4_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) - -#define __HAL_RCC_UART5_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) - -#define __HAL_RCC_I2C1_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) - -#define __HAL_RCC_I2C2_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) - -#define __HAL_RCC_CRS_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) - -#if defined(USART6) -#define __HAL_RCC_USART6_FORCE_RESET() SET_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) - -#define __HAL_RCC_LPTIM2_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_FORCE_RESET() SET_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) -#endif /* UCPD1 */ - -#define __HAL_RCC_APB1_RELEASE_RESET() do { \ - WRITE_REG(RCC->APB1RSTR1, 0x00000000U); \ - WRITE_REG(RCC->APB1RSTR2, 0x00000000U); \ - } while(0) - -#define __HAL_RCC_TIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM2RST) - -#define __HAL_RCC_TIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM3RST) - -#define __HAL_RCC_TIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM4RST) - -#define __HAL_RCC_TIM5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM5RST) - -#define __HAL_RCC_TIM6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM6RST) - -#define __HAL_RCC_TIM7_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_TIM7RST) - -#define __HAL_RCC_SPI2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_SPI2RST) - -#if defined(USART2) -#define __HAL_RCC_USART2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART2RST) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART3RST) - -#define __HAL_RCC_UART4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART4RST) - -#define __HAL_RCC_UART5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_UART5RST) - -#define __HAL_RCC_I2C1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C1RST) - -#define __HAL_RCC_I2C2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_I2C2RST) - -#define __HAL_RCC_CRS_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_CRSRST) - -#if defined(USART6) -#define __HAL_RCC_USART6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR1, RCC_APB1RSTR1_USART6RST) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C4RST) - -#define __HAL_RCC_LPTIM2_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_LPTIM2RST) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C5RST) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_I2C6RST) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_FDCAN1RST) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_RELEASE_RESET() CLEAR_BIT(RCC->APB1RSTR2, RCC_APB1RSTR2_UCPD1RST) -#endif /* UCPD1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB2_Force_Release_Reset APB2 Peripheral Force Release Reset - * @brief Force or release APB2 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB2_FORCE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00677800U) - -#define __HAL_RCC_TIM1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) - -#define __HAL_RCC_SPI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) - -#define __HAL_RCC_TIM8_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) - -#define __HAL_RCC_USART1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) - -#define __HAL_RCC_TIM15_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) - -#define __HAL_RCC_TIM16_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) - -#define __HAL_RCC_TIM17_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) - -#define __HAL_RCC_SAI1_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) -#endif /* SAI2 */ - -#if defined(USB_DRD_FS) -#define __HAL_RCC_USB_FS_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_FORCE_RESET() SET_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) -#endif /* DSI */ - -#define __HAL_RCC_APB2_RELEASE_RESET() WRITE_REG(RCC->APB2RSTR, 0x00000000U) - -#define __HAL_RCC_TIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM1RST) - -#define __HAL_RCC_SPI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SPI1RST) - -#define __HAL_RCC_TIM8_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM8RST) - -#define __HAL_RCC_USART1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USART1RST) - -#define __HAL_RCC_TIM15_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM15RST) - -#define __HAL_RCC_TIM16_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM16RST) - -#define __HAL_RCC_TIM17_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_TIM17RST) - -#define __HAL_RCC_SAI1_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI1RST) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_SAI2RST) -#endif /* SAI2 */ - -#if defined(USB_DRD_FS) -#define __HAL_RCC_USB_FS_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_USBRST) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_GFXTIMRST) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_LTDCRST) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_RELEASE_RESET() CLEAR_BIT(RCC->APB2RSTR, RCC_APB2RSTR_DSIHOSTRST) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_APB3_Force_Release_Reset APB3 Peripheral Force Release Reset - * @brief Force or release APB3 peripheral reset. - * @{ - */ -#define __HAL_RCC_APB3_FORCE_RESET() WRITE_REG(RCC->APB3RSTR, 0x0010F8E2U) - -#define __HAL_RCC_SYSCFG_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) - -#define __HAL_RCC_SPI3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) - -#define __HAL_RCC_LPUART1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) - -#define __HAL_RCC_I2C3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) - -#define __HAL_RCC_LPTIM1_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) - -#define __HAL_RCC_LPTIM3_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) - -#define __HAL_RCC_LPTIM4_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) - -#define __HAL_RCC_OPAMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) - -#define __HAL_RCC_COMP_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) - -#define __HAL_RCC_VREF_FORCE_RESET() SET_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) - -#define __HAL_RCC_APB3_RELEASE_RESET() WRITE_REG(RCC->APB3RSTR, 0x00000000U) - -#define __HAL_RCC_SYSCFG_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SYSCFGRST) - -#define __HAL_RCC_SPI3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_SPI3RST) - -#define __HAL_RCC_LPUART1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPUART1RST) - -#define __HAL_RCC_I2C3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_I2C3RST) - -#define __HAL_RCC_LPTIM1_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM1RST) - -#define __HAL_RCC_LPTIM3_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM3RST) - -#define __HAL_RCC_LPTIM4_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_LPTIM4RST) - -#define __HAL_RCC_OPAMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_OPAMPRST) - -#define __HAL_RCC_COMP_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_COMPRST) - -#define __HAL_RCC_VREF_RELEASE_RESET() CLEAR_BIT(RCC->APB3RSTR, RCC_APB3RSTR_VREFRST) - -/** - * @} - */ - -/** @defgroup RCC_AHB1_Peripheral_Clock_Sleep_Enable_Disable AHB1 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep and Stop) mode. - * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock - * is enabled only when a peripheral requests AHB clock. - * @{ - */ -#define __HAL_RCC_GPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) - -#define __HAL_RCC_CORDIC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) - -#define __HAL_RCC_FMAC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) - -#define __HAL_RCC_MDF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) - -#define __HAL_RCC_FLASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) - -#define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) - -#define __HAL_RCC_RAMCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) -#endif /* GPU2D */ - -#if defined(DCACHE2) -#define __HAL_RCC_DCACHE2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) -#endif /* DCACHE2 */ - -#define __HAL_RCC_GTZC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) - -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) - -#define __HAL_RCC_ICACHE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) - -#define __HAL_RCC_DCACHE1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) - -#define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) - -#define __HAL_RCC_GPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPDMA1SMEN) - -#define __HAL_RCC_CORDIC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CORDICSMEN) - -#define __HAL_RCC_FMAC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FMACSMEN) - -#define __HAL_RCC_MDF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_MDF1SMEN) - -#define __HAL_RCC_FLASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_FLASHSMEN) - -#define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_CRCSMEN) - -#if defined(JPEG) -#define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_JPEGSMEN) -#endif /* JPEG */ - -#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_TSCSMEN) - -#define __HAL_RCC_RAMCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_RAMCFGSMEN) - -#if defined(DMA2D) -#define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DMA2DSMEN) -#endif /* DMA2D */ - -#if defined(GFXMMU) -#define __HAL_RCC_GFXMMU_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GFXMMUSMEN) -#endif /* GFXMMU */ - -#if defined(GPU2D) -#define __HAL_RCC_GPU2D_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GPU2DSMEN) -#endif /* GPU2D */ - -#if defined(DCACHE2) -#define __HAL_RCC_DCACHE2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE2SMEN) -#endif /* DCACHE2 */ - -#define __HAL_RCC_GTZC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_GTZC1SMEN) - -#define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_BKPSRAMSMEN) - -#define __HAL_RCC_ICACHE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_ICACHESMEN) - -#define __HAL_RCC_DCACHE1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_DCACHE1SMEN) - -#define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB1SMENR, RCC_AHB1SMENR_SRAM1SMEN) - -/** - * @} - */ - -/** @defgroup RCC_AHB2_Peripheral_Clock_Sleep_Enable_Disable AHB2 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep and Stop) mode. - * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock - * is enabled only when a peripheral requests AHB clock. - * @{ - */ -#define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) - -#define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) - -#define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) - -#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) - -#define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) - -#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE __HAL_RCC_USB_CLK_SLEEP_ENABLE /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) -#define __HAL_RCC_USBPHYCCLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) -#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) - -#if defined(PKA) -#define __HAL_RCC_PKA_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) -#endif /* SDMMC2 */ - -#define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) - -#if defined(SRAM3_BASE) -#define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) -#endif /* SRAM3_BASE */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) -#endif /* HSPI1 */ - -#if defined(SRAM6_BASE) -#define __HAL_RCC_SRAM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) -#endif /* SRAM6_BASE */ - -#if defined(SRAM5_BASE) -#define __HAL_RCC_SRAM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) -#endif /* SRAM5_BASE */ - -#define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOASMEN) - -#define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOBSMEN) - -#define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOCSMEN) - -#define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIODSMEN) - -#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOESMEN) - -#if defined(GPIOF) -#define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOFSMEN) -#endif /* GPIOF */ - -#define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOGSMEN) - -#define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOHSMEN) - -#if defined(GPIOI) -#define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOISMEN) -#endif /* GPIOI */ - -#if defined(GPIOJ) -#define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_GPIOJSMEN) -#endif /* GPIOJ */ - -#define __HAL_RCC_ADC12_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_ADC12SMEN) - -#define __HAL_RCC_DCMI_PSSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_DCMI_PSSISMEN) - -#if defined(USB_OTG_HS) -#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) -#endif /* USB_OTG_HS */ - -#if defined(USB_OTG_FS) -#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTGSMEN) -#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE __HAL_RCC_USB_CLK_SLEEP_DISABLE /*!< alias define for compatibility with legacy code */ -#endif /* USB_OTG_FS */ - -#if defined(RCC_AHB2SMENR1_USBPHYCSMEN) -#define __HAL_RCC_USBPHYCCLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_USBPHYCSMEN) -#endif /* RCC_AHB2SMENR1_USBPHYCSMEN */ - -#if defined(AES) -#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_AESSMEN) -#endif /* AES */ - -#if defined(HASH) -#define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_HASHSMEN) -#endif /* HASH */ - -#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_RNGSMEN) - -#if defined(PKA) -#define __HAL_RCC_PKA_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_PKASMEN) -#endif /* PKA */ - -#if defined(SAES) -#define __HAL_RCC_SAES_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SAESSMEN) -#endif /* SAES */ - -#if defined(OCTOSPIM) -#define __HAL_RCC_OCTOSPIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OCTOSPIMSMEN) -#endif /* OCTOSPIM */ - -#if defined(OTFDEC1) -#define __HAL_RCC_OTFDEC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC1SMEN) -#endif /* OTFDEC1 */ - -#if defined(OTFDEC2) -#define __HAL_RCC_OTFDEC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_OTFDEC2SMEN) -#endif /* OTFDEC2 */ - -#define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC1SMEN) - -#if defined(SDMMC2) -#define __HAL_RCC_SDMMC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SDMMC2SMEN) -#endif /* SDMMC2 */ - -#define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM2SMEN) - -#if defined(SRAM3_BASE) -#define __HAL_RCC_SRAM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR1, RCC_AHB2SMENR1_SRAM3SMEN) -#endif /* SRAM3_BASE */ - -#if defined(FMC_BASE) -#define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_FSMCSMEN) -#endif /* FMC_BASE */ - -#define __HAL_RCC_OSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI1SMEN) - -#if defined(OCTOSPI2) -#define __HAL_RCC_OSPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_OCTOSPI2SMEN) -#endif /* OCTOSPI2 */ - -#if defined(HSPI1) -#define __HAL_RCC_HSPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_HSPI1SMEN) -#endif /* HSPI1 */ - -#if defined(SRAM6_BASE) -#define __HAL_RCC_SRAM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM6SMEN) -#endif /* SRAM6_BASE */ - -#if defined(SRAM5_BASE) -#define __HAL_RCC_SRAM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB2SMENR2, RCC_AHB2SMENR2_SRAM5SMEN) -#endif /* SRAM5_BASE */ - -/** - * @} - */ - -/** @defgroup RCC_AHB3_Clock_Sleep_Enable_Disable AHB3SMENR Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the AHB3SMENR peripheral clock during Low Power (Sleep and STOP ) mode. - * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock - * is enabled only when a peripheral requests AHB clock. - * @{ - */ -#define __HAL_RCC_LPGPIO1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) - -#define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) - -#define __HAL_RCC_ADC4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) - -#define __HAL_RCC_DAC1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) - -#define __HAL_RCC_LPDMA1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) - -#define __HAL_RCC_ADF1_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) - -#define __HAL_RCC_GTZC2_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) - -#define __HAL_RCC_SRAM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) - -#define __HAL_RCC_LPGPIO1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPGPIO1SMEN) - -#define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_PWRSMEN) - -#define __HAL_RCC_ADC4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADC4SMEN) - -#define __HAL_RCC_DAC1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_DAC1SMEN) - -#define __HAL_RCC_LPDMA1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_LPDMA1SMEN) - -#define __HAL_RCC_ADF1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_ADF1SMEN) - -#define __HAL_RCC_GTZC2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_GTZC2SMEN) - -#define __HAL_RCC_SRAM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->AHB3SMENR, RCC_AHB3SMENR_SRAM4SMEN) - -/** - * @} - */ - -/** @defgroup RCC_APB1_Clock_Sleep_Enable_Disable APB1 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep and Stop) mode. - * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock - * is enabled only when a peripheral requests APB clock. - * @{ - */ -#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) - -#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) - -#define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) - -#define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) - -#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) - -#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) - -#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) - -#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) - -#if defined(USART2) -#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) - -#define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) - -#define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) - -#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) - -#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) - -#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) - -#if defined(USART6) -#define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) -#endif /* UCPD1 */ - -#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM2SMEN) - -#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM3SMEN) - -#define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM4SMEN) - -#define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM5SMEN) - -#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM6SMEN) - -#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_TIM7SMEN) - -#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_WWDGSMEN) - -#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_SPI2SMEN) - -#if defined(USART2) -#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART2SMEN) -#endif /* USART2 */ - -#define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART3SMEN) - -#define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART4SMEN) - -#define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_UART5SMEN) - -#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C1SMEN) - -#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_I2C2SMEN) - -#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_CRSSMEN) - -#if defined(USART6) -#define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR1, RCC_APB1SMENR1_USART6SMEN) -#endif /* USART6 */ - -#define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C4SMEN) - -#define __HAL_RCC_LPTIM2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_LPTIM2SMEN) - -#if defined(I2C5) -#define __HAL_RCC_I2C5_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C5SMEN) -#endif /* I2C5 */ - -#if defined(I2C6) -#define __HAL_RCC_I2C6_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_I2C6SMEN) -#endif /* I2C6 */ - -#define __HAL_RCC_FDCAN1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_FDCAN1SMEN) - -#if defined(UCPD1) -#define __HAL_RCC_UCPD_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB1SMENR2, RCC_APB1SMENR2_UCPD1SMEN) -#endif /* UCPD1 */ - -/** - * @} - */ - -/** @defgroup RCC_APB2_Clock_Sleep_Enable_Disable APB2 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep and Stop) mode. - * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP or STOP mode, the pseripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock - * is enabled only when a peripheral requests APB clock. - * @{ - */ -#define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) - -#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) - -#define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) - -#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) - -#define __HAL_RCC_TIM15_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) - -#define __HAL_RCC_TIM16_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) - -#define __HAL_RCC_TIM17_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) - -#define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) -#endif /* SAI2 */ - -#if defined(USB_DRD_FS) -#define __HAL_RCC_USB_FS_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) -#endif /* DSI */ - -#define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM1SMEN) - -#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SPI1SMEN) - -#define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM8SMEN) - -#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USART1SMEN) - -#define __HAL_RCC_TIM15_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM15SMEN) - -#define __HAL_RCC_TIM16_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM16SMEN) - -#define __HAL_RCC_TIM17_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_TIM17SMEN) - -#define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI1SMEN) - -#if defined(SAI2) -#define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_SAI2SMEN) -#endif /* SAI2 */ - -#if defined(USB_DRD_FS) -#define __HAL_RCC_USB_FS_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_USBSMEN) -#endif /* USB_DRD_FS */ - -#if defined(GFXTIM) -#define __HAL_RCC_GFXTIM_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_GFXTIMSMEN) -#endif /* GFXTIM */ - -#if defined(LTDC) -#define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_LTDCSMEN) -#endif /* LTDC */ - -#if defined(DSI) -#define __HAL_RCC_DSI_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB2SMENR, RCC_APB2SMENR_DSIHOSTSMEN) -#endif /* DSI */ - -/** - * @} - */ - -/** @defgroup RCC_APB3_Clock_Sleep_Enable_Disable APB3 Peripheral Clock Sleep Enable Disable - * @brief Enable or disable the APB3 peripheral clock during Low Power (Sleep and Stop) mode. - * @note Peripheral clock gating in SLEEP and STOP modes can be used to further reduce - * power consumption. - * @note After wakeup from SLEEP or STOP modes, the peripheral clock is enabled again. - * @note By default, all peripheral clocks are enabled during SLEEP mode,in STOP mode peripheral clock - * is enabled only when a peripheral requests APB clock. - * @{ - */ -#define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) - -#define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) - -#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) - -#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) - -#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) - -#define __HAL_RCC_LPTIM3_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) - -#define __HAL_RCC_LPTIM4_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) - -#define __HAL_RCC_COMP_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) - -#define __HAL_RCC_VREF_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) - -#define __HAL_RCC_RTCAPB_CLK_SLEEP_ENABLE() SET_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) - -#define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SYSCFGSMEN) - -#define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_SPI3SMEN) - -#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPUART1SMEN) - -#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_I2C3SMEN) - -#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM1SMEN) - -#define __HAL_RCC_LPTIM3_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM3SMEN) - -#define __HAL_RCC_LPTIM4_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_LPTIM4SMEN) - -#define __HAL_RCC_OPAMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_OPAMPSMEN) - -#define __HAL_RCC_COMP_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_COMPSMEN) - -#define __HAL_RCC_VREF_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_VREFSMEN) - -#define __HAL_RCC_RTCAPB_CLK_SLEEP_DISABLE() CLEAR_BIT(RCC->APB3SMENR, RCC_APB3SMENR_RTCAPBSMEN) - -/** - * @} - */ - -/** @brief Enable or disable peripheral bus clock when SRD domain is in DRUN - * @note After reset, peripheral clock is disabled when CPUs are in CSTOP - * @{ - */ -#define __HAL_RCC_SPI3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) - -#define __HAL_RCC_LPUART1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) - -#define __HAL_RCC_I2C3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) - -#define __HAL_RCC_LPTIM1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) - -#define __HAL_RCC_LPTIM3_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) - -#define __HAL_RCC_LPTIM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) - -#define __HAL_RCC_OPAMP_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) - -#define __HAL_RCC_COMP12_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) - -#define __HAL_RCC_ADC4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) - -#define __HAL_RCC_VREF_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) - -#define __HAL_RCC_RTCAPB_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) - -#define __HAL_RCC_LPGPIO1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) - -#define __HAL_RCC_DAC1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) - -#define __HAL_RCC_LPDMA1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) - -#define __HAL_RCC_ADF1_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) - -#define __HAL_RCC_SRAM4_CLKAM_ENABLE() SET_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) - -#define __HAL_RCC_SPI3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SPI3AMEN) - -#define __HAL_RCC_LPUART1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPUART1AMEN) - -#define __HAL_RCC_I2C3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_I2C3AMEN) - -#define __HAL_RCC_LPTIM1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM1AMEN) - -#define __HAL_RCC_LPTIM3_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM3AMEN) - -#define __HAL_RCC_LPTIM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPTIM4AMEN) - -#define __HAL_RCC_OPAMP_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_OPAMPAMEN) - -#define __HAL_RCC_COMP12_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_COMPAMEN) - -#define __HAL_RCC_ADC4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADC4AMEN) - -#define __HAL_RCC_VREF_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_VREFAMEN) - -#define __HAL_RCC_RTCAPB_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_RTCAPBAMEN) - -#define __HAL_RCC_LPGPIO1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPGPIO1AMEN) - -#define __HAL_RCC_DAC1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_DAC1AMEN) - -#define __HAL_RCC_LPDMA1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_LPDMA1AMEN) - -#define __HAL_RCC_ADF1_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_ADF1AMEN) - -#define __HAL_RCC_SRAM4_CLKAM_DISABLE() CLEAR_BIT(RCC->SRDAMR , RCC_SRDAMR_SRAM4AMEN) - -/** - * @} - */ - - -/** @defgroup RCC_Backup_Domain_Reset RCC Backup Domain Reset - * @{ - */ - -/** @brief Macros to force or release the Backup domain reset. - * @note This function resets the RTC peripheral (including the backup registers) - * and the RTC clock source selection in RCC_CSR register. - * @note The BKPSRAM is not affected by this reset. - * @retval None - */ -#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST) - -/** - * @} - */ - -/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration - * @{ - */ - -/** @brief Macros to enable or disable the RTC clock. - * @note As the RTC is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the RTC - * (to be done once after reset). - * @note These macros must be used after the RTC clock source was selected. - * @retval None - */ -#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN) - -/** - * @} - */ - -/** @brief Macros to enable or disable the Internal High Speed 16MHz oscillator (HSI). - * @note The HSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after startup - * from Reset, wakeup from STOP and STANDBY mode, or in case of failure - * of the HSE used directly or indirectly as system clock (if the Clock - * Security System CSS is enabled). - * @note HSI can not be stopped if it is used as system clock source. In this case, - * you have to select another source of the system clock then stop the HSI. - * @note After enabling the HSI, the application software should wait on HSIRDY - * flag to be set indicating that HSI clock is stable and can be used as - * system clock source. - * This parameter can be: ENABLE or DISABLE. - * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION) - -#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION) - -/** @brief Macro to adjust the Internal High Speed 16MHz oscillator (HSI) calibration value. - * @note The calibration is used to compensate for the variations in voltage - * and temperature that influence the frequency of the internal HSI RC. - * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value - * (default is RCC_HSICALIBRATION_DEFAULT). - * This parameter must be a number between 0 and 0x20. - * @retval None - */ -#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) \ - MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_ICSCR3_HSITRIM_Pos) - -/** - * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI) - * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. - * @note Keeping the HSI ON in STOP mode allows to avoid slowing down the communication - * speed because of the HSI startup time. - * @note The enable of this function has not effect on the HSION bit. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON) - -#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON) - -/** - * @brief Macros to enable or disable the force of the Internal Multi Speed kernel oscillator (MSIK) - * in STOP mode to be quickly available as kernel clock for USARTs, LPUART and I2Cs. - * @note Keeping the MSIK ON in STOP mode allows to avoid slowing down the communication - * speed because of the MSIK startup time. - * @note The enable of this function has not effect on the MSIKON bit. - * @note The MSIKERON must be configured at 0 before entreing stop 3 mode. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_MSIKSTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKERON) - -#define __HAL_RCC_MSIKSTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON) - -/** - * @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI). - * @note The MSI is stopped by hardware when entering STOP and STANDBY modes. - * It is used (enabled by hardware) as system clock source after - * startup from Reset, wakeup from STOP and STANDBY mode, or in case - * of failure of the HSE used directly or indirectly as system clock - * (if the Clock Security System CSS is enabled). - * @note MSI can not be stopped if it is used as system clock source. - * In this case, you have to select another source of the system - * clock then stop the MSI. - * @note After enabling the MSI, the application software should wait on - * MSIRDY flag to be set indicating that MSI clock is stable and can - * be used as system clock source. - * @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_MSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSISON) - -#define __HAL_RCC_MSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSISON) - -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range in run mode - * @note After restart from Reset , the MSI clock is around 4 MHz. - * After stop the startup clock can be MSI (at any of its possible - * frequencies, the one that was used before entering stop mode) or HSI. - * After Standby its frequency can be selected between 4 possible values - * (1, 3.072, 4 or 8 MHz). - * @note MSIRANGE can be modified when MSI is OFF (MSION=0) or when MSI is ready - * (MSIRDY=1). - * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIRANGEVALUE__: specifies the MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz - * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz - * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz - * @retval None - */ -#define __HAL_RCC_MSI_RANGE_CONFIG(__MSIRANGEVALUE__) \ - do { \ - SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, (__MSIRANGEVALUE__)); \ - } while(0) - -/** - * @brief Macro configures the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode - * @note After restart from Reset , the MSIK clock is around 4 MHz. - * After stop the startup clock can be MSIK (at any of its possible - * frequencies, the one that was used before entering stop mode) or HSI. - * After Standby its frequency can be selected between 4 possible values - * (1, 3.072, 4 or 8 MHz). - * @note MSIKRANGE can be modified when MSIK is OFF (MSIKON=0) or when MSIK is ready - * (MSIKRDY=1). - * @note The MSI clock range after reset can be modified on the fly. - * @param __MSIKRANGEVALUE__: specifies the MSI clock range. - * @arg @ref RCC_MSIKRANGE_0 MSIK clock is around 48 MHz - * @arg @ref RCC_MSIKRANGE_1 MSIK clock is around 24 KHz - * @arg @ref RCC_MSIKRANGE_2 MSIK clock is around 16 MHz - * @arg @ref RCC_MSIKRANGE_3 MSIK clock is around 12 MHz - * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz - * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz - * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz - * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz - * @arg @ref RCC_MSIKRANGE_9 MSIK clock is around 1.536 MHz - * @arg @ref RCC_MSIKRANGE_10 MSIK clock is around 1.024 MHz - * @arg @ref RCC_MSIKRANGE_11 MSIK clock is around 768 KHz - * @arg @ref RCC_MSIKRANGE_12 MSIK clock is around 400 KHz - * @arg @ref RCC_MSIKRANGE_13 MSIK clock is around 200 KHz - * @arg @ref RCC_MSIKRANGE_14 MSIK clock is around 133 KHz - * @arg @ref RCC_MSIKRANGE_15 MSIK clock is around 100 KHz - * @retval None - */ -#define __HAL_RCC_MSIK_RANGE_CONFIG(__MSIKRANGEVALUE__) \ - do { \ - SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, (__MSIKRANGEVALUE__)); \ - } while(0) - -/** @brief Macros to enable or disable the MSI bias mode selection. - * @note By default the MSI bias is in continuous mode in order to maintain - * the output clocks accuracy. - * @note Setting this bit reduces the MSI consumption under range 4 but decrease its accuracy. - * @retval None - */ -#define __HAL_RCC_MSIBIAS_SELECTION_ENABLE() SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) - -#define __HAL_RCC_MSIBIAS_SELECTION_DISABLE() CLEAR_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS) - -/** @brief Macros to enable or disable LSE clock glitch filter . - * @note The glitches on LSE can be filtred by setting the LSEGFON. - * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). - * @retval None - */ - -#define __HAL_RCC_LSE_GLITCHFILTER_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) - -#define __HAL_RCC_LSE_GLITCHFILTER_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON ) - -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSI) clock range after Standby mode - * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). - * @param __MSIRANGEVALUE__: specifies the MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz - * @retval None - */ -#define __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(__MSIRANGEVALUE__) do {SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL);\ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE,\ - (__MSIRANGEVALUE__) >> (RCC_ICSCR1_MSISRANGE_Pos -\ - RCC_CSR_MSISSRANGE_Pos));\ - } while(0) -/** - * @brief Macro configures the Internal Multi Speed oscillator (MSIK) clock range after Standby mode - * After Standby its frequency can be selected between 5 possible values (4, 2, 1.33, 1, or 3.072 MHz). - * @param __MSIKRANGEVALUE__: specifies the MSIK clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIKRANGE_4 MSIK clock is around 4 MHz (default after Reset) - * @arg @ref RCC_MSIKRANGE_5 MSIK clock is around 2 MHz - * @arg @ref RCC_MSIKRANGE_6 MSIK clock is around 1.33 MHz - * @arg @ref RCC_MSIKRANGE_7 MSIK clock is around 1 MHz - * @arg @ref RCC_MSIKRANGE_8 MSIK clock is around 3.072 MHz - * @retval None - */ -#define __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(__MSIKRANGEVALUE__) \ - do { \ - SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); \ - MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, \ - (__MSIKRANGEVALUE__) >> (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos)); \ - } while(0) - -/** @brief Macro to get the Internal Multi Speed oscillator (MSI) clock range in run mode - * @retval MSI clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz - * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz - * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz - */ -#define __HAL_RCC_GET_MSI_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ - (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)) : \ - (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE) << \ - (RCC_ICSCR1_MSISRANGE_Pos - RCC_CSR_MSISSRANGE_Pos))) - -/** @brief Macro to get the Internal Multi Speed kernel oscillator (MSIK) clock range in run mode - * @retval MSIK clock range. - * This parameter must be one of the following values: - * @arg @ref RCC_MSIRANGE_0 MSI clock is around 48 MHz - * @arg @ref RCC_MSIRANGE_1 MSI clock is around 24 KHz - * @arg @ref RCC_MSIRANGE_2 MSI clock is around 16 MHz - * @arg @ref RCC_MSIRANGE_3 MSI clock is around 12 MHz - * @arg @ref RCC_MSIRANGE_4 MSI clock is around 4 MHz - * @arg @ref RCC_MSIRANGE_5 MSI clock is around 2 MHz - * @arg @ref RCC_MSIRANGE_6 MSI clock is around 1.33 MHz - * @arg @ref RCC_MSIRANGE_7 MSI clock is around 1 MHz - * @arg @ref RCC_MSIRANGE_8 MSI clock is around 3.072 MHz - * @arg @ref RCC_MSIRANGE_9 MSI clock is around 1.536 MHz - * @arg @ref RCC_MSIRANGE_10 MSI clock is around 1.024 MHz - * @arg @ref RCC_MSIRANGE_11 MSI clock is around 768 KHz - * @arg @ref RCC_MSIRANGE_12 MSI clock is around 400 KHz - * @arg @ref RCC_MSIRANGE_13 MSI clock is around 200 KHz - * @arg @ref RCC_MSIRANGE_14 MSI clock is around 133 KHz - * @arg @ref RCC_MSIRANGE_15 MSI clock is around 100 KHz - */ -#define __HAL_RCC_GET_MSIK_RANGE() ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) != 0U) ? \ - (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)) : \ - (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE) << \ - (RCC_ICSCR1_MSIKRANGE_Pos - RCC_CSR_MSIKSRANGE_Pos))) - -/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI). - * @note After enabling the LSI, the application software should wait on - * LSIRDY flag to be set indicating that LSI clock is stable and can - * be used to clock the IWDG and/or the RTC. - * @note LSI can not be disabled if the IWDG is running. - * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator - * clock cycles. - * @retval None - */ -#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_LSION) - -#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION|RCC_BDCR_LSIPREDIV) - -/** - * @brief Macro to configure the External High Speed oscillator (HSE). - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this macro. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application - * software should wait on HSERDY flag to be set indicating that HSE clock - * is stable and can be used to clock the PLL and/or system clock. - * @note HSE state can not be changed if it is used directly or through the - * PLL as system clock. In this case, you have to select another source - * of the system clock then change the HSE state (ex. disable it). - * @note The HSE is stopped by hardware when entering STOP and STANDBY or shutdown modes. - * @param __STATE__: specifies the new state of the HSE. - * This parameter can be one of the following values: - * @arg @ref RCC_HSE_OFF Turn OFF the HSE oscillator, HSERDY flag goes low after - * 6 HSE oscillator clock cycles. - * @arg @ref RCC_HSE_ON Turn ON the HSE oscillator. - * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock. - * @arg @ref RCC_HSE_BYPASS_DIGITAL HSE oscillator bypassed through I/O Schmitt trigger . - * @retval None - */ -#define __HAL_RCC_HSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_HSE_ON) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else if((__STATE__) == RCC_HSE_BYPASS_DIGITAL) \ - { \ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); \ - SET_BIT(RCC->CR, RCC_CR_HSEEXT); \ - SET_BIT(RCC->CR, RCC_CR_HSEON); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \ - CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT); \ - } \ - } while(0) - -/** @brief Macro to enable or disable the LSE system clock. - * @note This clock can be used by any peripheral when its source clock is the LSE or at system - * in case of one of the LSCOSEL, MCO, MSI PLL mode or CSS on LSE is needed. - * @note The LSESYS clock can be generated even if LSESYSEN= 0 if the LSE clock is requested by - * the CSS on LSE, by a peripheral or any other source clock using LSE. - * @retval None - */ -#define __HAL_RCC_LSESYS_ENABLE() SET_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) - -#define __HAL_RCC_LSESYS_DISABLE() CLEAR_BIT(RCC->BDCR,RCC_BDCR_LSESYSEN) - -/** @brief Macro to set Low-speed clock (LSI) divider. - * @note This bit can be written only when the LSI is disabled (LSION = 0 and LSIRDY = 0). - * The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC. - * - * @param __DIVIDER__ : specifies the divider value - * This parameter can be one of the following values - * @arg @ref RCC_LSI_DIV1 - * @arg @ref RCC_LSI_DIV128 - * @retval None - */ -#define __HAL_RCC_LSI_DIV_CONFIG(__DIVIDER__) \ - do { \ - if((__DIVIDER__) == RCC_LSI_DIV128) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV); \ - } \ - } while(0) - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE). - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this macro. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application - * software should wait on LSERDY flag to be set indicating that LSE clock - * is stable and can be used to clock the RTC. - * @param __STATE__: specifies the new state of the LSE. - * This parameter can be one of the following values: - * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after - * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. - * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. - * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral - * @retval None - */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) \ - do { \ - if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ - { \ - SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_ON) \ - { \ - SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ - } \ - else \ - { \ - CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ - } \ - } while(0) - -/** @brief Macros to enable or disable the Internal High Speed 48MHz oscillator (HSI48). - * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes. - * @note After enabling the HSI48, the application software should wait on HSI48RDY - * flag to be set indicating that HSI48 clock is stable. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSI48ON) - -#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON) - -/** @brief Macros to enable or disable the Internal multi-speed RC oscillator clock (MSIK). - * @note if the peripheral requests its kernel clock in Stop 0 or Stop 1 mode,MSIK is woken up - * @note After enabling the MSIK, the application software should wait on MSIKRDY - * flag to be set indicating that MSIK clock is stable. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_MSIK_ENABLE() SET_BIT(RCC->CR, RCC_CR_MSIKON) - -#define __HAL_RCC_MSIK_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_MSIKON) - -/** @brief Macros to enable or disable the secure Internal High Speed oscillator (SHSI). - * @note The SHSI is stopped by hardware when entering STOP and STANDBY modes. - * @note After enabling the SHSI, the application software should wait on SHSI - * flag to be set indicating that SHSI clock is stable. - * This parameter can be: ENABLE or DISABLE. - * @retval None - */ -#define __HAL_RCC_SHSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_SHSION) - -#define __HAL_RCC_SHSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_SHSION) - -/** @brief Macros to configure the RTC clock (RTCCLK). - * @note As the RTC clock configuration bits are in the Backup domain and write - * access is denied to this domain after reset, you have to enable write - * access using the Power Backup Access macro before to configure - * the RTC clock source (to be done once after reset). - * @note Once the RTC clock is configured it cannot be changed unless the - * Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by - * a Power On Reset (POR). - * - * @param __RTC_CLKSOURCE__: specifies the RTC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - * - * @note If the LSE or LSI is used as RTC clock source, the RTC continues to - * work in STOP and STANDBY modes, and can be used as wakeup source. - * However, when the HSE clock is used as RTC clock source, the RTC - * cannot be used in STOP and STANDBY modes. - * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as - * RTC clock source). - * @retval None - */ -#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) \ - MODIFY_REG( RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__)) - -/** @brief Macro to get the RTC clock source. - * @retval The returned value can be one of the following: - * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock. - * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV32 HSE clock divided by 32 selected - */ -#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))) - -/** @brief Macros to enable or disable the main PLL. - * @note After enabling the main PLL, the application software should wait on - * PLLRDY flag to be set indicating that PLL clock is stable and can - * be used as system clock source. - * @note The main PLL can not be disabled if it is used as system clock source - * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL1ON) -#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON) - -/** - * @brief Enables or disables each clock output (PLL_P_CLK, PLL_Q_CLK, PLL_R_CLK) - * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL, - * This is mainly used to save Power. - * @param __PLL1_CLOCKOUT__: specifies the PLL clock to be outputted - * This parameter can be one of the following values: - * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, - * high-quality audio performance on SAI interface. - * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), - * the random analog generator (<=48 MHz) and the OCTOSPI1/2. - * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) - * @retval None - * - */ -#define __HAL_RCC_PLLCLKOUT_ENABLE(__PLL1_CLOCKOUT__) SET_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) - -#define __HAL_RCC_PLLCLKOUT_DISABLE(__PLL1_CLOCKOUT__) CLEAR_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) - -/** - * @brief Macro to get the PLL clock output enable status. - * @param __PLL1_CLOCKOUT__ specifies the PLL1 clock to be output. - * This parameter can be one of the following values: - * @arg RCC_PLL1_DIVP: This clock is used to generate an accurate clock to achieve, - * high-quality audio performance on SAI interface. - * @arg RCC_PLL1_DIVQ: This Clock is used to generate the clock for the USB FS(48 MHz), - * the random analog generator (<=48 MHz) and the OCTOSPI1/2. - * @arg RCC_PLL1_DIVR: This Clock is used to generate the high speed system clock (up to 160MHz) - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLLCLKOUT_CONFIG(__PLL1_CLOCKOUT__) READ_BIT(RCC->PLL1CFGR, (__PLL1_CLOCKOUT__)) - -/** - * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL1 VCO - * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL1 - * @retval None - */ -#define __HAL_RCC_PLL_FRACN_ENABLE() SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) - -#define __HAL_RCC_PLL_FRACN_DISABLE() CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) - -/** - * @brief Macro to configure the main PLL clock source, multiplication and division factors. - * @note This function must be used only when the main PLL is disabled. - * - * @param __PLL1SOURCE__: specifies the PLL entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - * @note This clock source (__PLL1SOURCE__) is common for the main PLL1 (main PLL) and PLL2 & PLL3 . - * - * @param __PLL1MBOOST__: specifies the division factor for the EPOD clock - * This parameter must be a value of @ref RCC_PLLMBOOST_EPOD_Clock_Divider. - * - * @param __PLL1M__: specifies the division factor for PLL VCO input clock - * This parameter must be a number between 1 and 63. - * @note You have to set the PLLM parameter correctly to ensure that the VCO input - * frequency ranges from 1 to 16 MHz. - * - * @param __PLL1N__: specifies the multiplication factor for PLL VCO output clock - * This parameter must be a number between 4 and 512. - * @note You have to set the PLLN parameter correctly to ensure that the VCO - * output frequency is between 128 and 544 MHz(Voltage range 1 or 2) - * between 128 and 330 MHZ (Voltage range 3) and not allowed for Voltage range 4. - * - * @param __PLL1P__: specifies the division factor for peripheral kernel clocks. - * This parameter must be a number between 1 and 128 - * - * @param __PLL1Q__: specifies the division factor for peripheral kernel clocks. - * This parameter must be a number between 1 and 128 - * - * @param __PLL1R__: specifies the division factor for system clock. - * This parameter must be a number between 1 and 128 (Only division by 1 and even division are allowed) - * - * @retval None - */ -#define __HAL_RCC_PLL_CONFIG(__PLL1SOURCE__, __PLL1MBOOST__,__PLL1M__, __PLL1N__, __PLL1P__, __PLL1Q__, __PLL1R__) \ - do{ MODIFY_REG(RCC->PLL1CFGR,(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M|\ - RCC_PLL1CFGR_PLL1MBOOST), ((__PLL1SOURCE__) << RCC_PLL1CFGR_PLL1SRC_Pos) |\ - (((__PLL1M__) - 1U) << RCC_PLL1CFGR_PLL1M_Pos) | (__PLL1MBOOST__));\ - MODIFY_REG(RCC->PLL1DIVR ,(RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P | RCC_PLL1DIVR_PLL1Q |\ - RCC_PLL1DIVR_PLL1R), ( (((__PLL1N__) - 1U ) & RCC_PLL1DIVR_PLL1N) |\ - ((((__PLL1P__) -1U ) << RCC_PLL1DIVR_PLL1P_Pos) & \ - RCC_PLL1DIVR_PLL1P) | \ - ((((__PLL1Q__) -1U) << RCC_PLL1DIVR_PLL1Q_Pos) & \ - RCC_PLL1DIVR_PLL1Q) |\ - ((((__PLL1R__)- 1U) << RCC_PLL1DIVR_PLL1R_Pos) & \ - RCC_PLL1DIVR_PLL1R))); \ - } while(0) - -/** @brief Macro to configure the PLLs clock source. - * @note This function must be used only when all PLLs are disabled. - * @param __PLL1SOURCE__: specifies the PLLs entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry - */ -#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLL1SOURCE__) MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, (__PLL1SOURCE__)) - -/** - * @brief Macro to configure the main PLL clock Fractional Part Of The Multiplication Factor - * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL1 VCO - * @param __PLL1FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL1 VCO - * It should be a value between 0 and 8191 - * @note Warning: The software has to set correctly these bits to insure that the VCO - * output frequency is between its valid frequency range, which is: - * 192 to 836 MHz if PLL1VCOSEL = 0 - * 150 to 420 MHz if PLL1VCOSEL = 1. - * @retval None - */ -#define __HAL_RCC_PLL_FRACN_CONFIG(__PLL1FRACN__) WRITE_REG(RCC->PLL1FRACR, \ - (uint32_t)(__PLL1FRACN__) << \ - RCC_PLL1FRACR_PLL1FRACN_Pos) - -/** @brief Macro to select the PLL1 reference frequency range. - * @param __PLL1VCIRange__: specifies the PLL1 input frequency range - * This parameter can be one of the following values: - * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz - * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz - * @retval None - */ -#define __HAL_RCC_PLL_VCIRANGE(__PLL1VCIRange__) \ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, (__PLL1VCIRange__)) - -/** @brief Macro to get the oscillator used as PLL1 clock source. - * @retval The oscillator used as PLL1 clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC)) - -/** - * @brief Macro to configure the system clock source. - * @param __SYSCLKSOURCE__: specifies the system clock source. - * This parameter can be one of the following values: - * - RCC_SYSCLKSOURCE_MSI: MSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source. - * - RCC_SYSCLKSOURCE_PLL1CLK: PLL1 output is used as system clock source. - * @retval None - */ -#define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, (__SYSCLKSOURCE__)) - -/** @brief Macro to get the clock source used as system clock. - * @retval The clock source used as system clock. The returned value can be one - * of the following: - * - RCC_SYSCLKSOURCE_STATUS_MSI: MSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock. - * - RCC_SYSCLKSOURCE_STATUS_PLL1CLK: PLL1 used as system clock. - */ -#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR1 & RCC_CFGR1_SWS)) - -/** - * @brief Macro to configure the External Low Speed oscillator (LSE) drive capability. - * @note As the LSE is in the Backup domain and write access is denied to - * this domain after reset, you have to enable write access using - * HAL_PWR_EnableBkUpAccess() function before to configure the LSE - * (to be done once after reset). - * @note The LSE drive can be decreased to the lower drive capability (LSEDRV = 0) - * when the LSE is ON. However, once LSEDRV is selected, the drive - * capability can not be increased if LSEON = 1. - * @param __LSEDRIVE__: specifies the new state of the LSE drive capability. - * This parameter can be one of the following values: - * @arg @ref RCC_LSEDRIVE_LOW LSE oscillator low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMLOW LSE oscillator medium low drive capability. - * @arg @ref RCC_LSEDRIVE_MEDIUMHIGH LSE oscillator medium high drive capability. - * @arg @ref RCC_LSEDRIVE_HIGH LSE oscillator high drive capability. - * @retval None - */ -#define __HAL_RCC_LSEDRIVE_CONFIG(__LSEDRIVE__) \ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, (uint32_t)(__LSEDRIVE__)) - -/** - * @brief Macro to configure the wake up from stop clock. - * @note The selected clock is also used as emergency clock for the clock security system on HSE. - * @param __STOPWUCLK__: specifies the clock source used after wake up from stop. - * This parameter can be one of the following values: - * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI selected as system clock source and CSS backup clock - * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI selected as system clock source and CSS backup clock - * @retval None - */ -#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__STOPWUCLK__) \ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, (__STOPWUCLK__)) - -/** - * @brief Macro to configure the Kernel wake up from stop clock. - * @param __RCC_STOPKERWUCLK__: specifies the Kernel clock source used after wake up from stop - * This parameter can be one of the following values: - * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI selected as Kernel clock source - * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI selected as Kernel clock source - * @retval None - */ -#define __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(__RCC_STOPKERWUCLK__) \ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, (__RCC_STOPKERWUCLK__)) - -/** @brief Macro to configure the MCO clock. - * @param __MCOCLKSOURCE__ specifies the MCO clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled - * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL1CLK Main PLL clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - * @param __MCODIV__ specifies the MCO clock prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 MCO clock source is divided by 1 - * @arg @ref RCC_MCODIV_2 MCO clock source is divided by 2 - * @arg @ref RCC_MCODIV_4 MCO clock source is divided by 4 - * @arg @ref RCC_MCODIV_8 MCO clock source is divided by 8 - * @arg @ref RCC_MCODIV_16 MCO clock source is divided by 16 - */ -#define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \ - MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), ((__MCOCLKSOURCE__) | (__MCODIV__))) - -/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management - * @brief macros to manage the specified RCC Flags and interrupts. - * @{ - */ - -/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt - * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - * @retval None - */ -#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) SET_BIT(RCC->CIER, (__INTERRUPT__)) - -/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable - * the selected interrupts). - * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt - * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - * @retval None - */ -#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(RCC->CIER, (__INTERRUPT__)) - -/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16] - * bits to clear the selected interrupt pending bits. - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt - * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt - * @arg @ref RCC_IT_CSS HSE Clock security system interrupt - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt - * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt - * @retval None - */ -#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) WRITE_REG(RCC->CICR, (__INTERRUPT__)) - -/** @brief Check whether the RCC interrupt has occurred or not. - * @param __INTERRUPT__: specifies the RCC interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_IT_LSIRDY LSI ready interrupt - * @arg @ref RCC_IT_LSERDY LSE ready interrupt - * @arg @ref RCC_IT_MSIRDY MSI ready interrupt - * @arg @ref RCC_IT_HSIRDY HSI ready interrupt - * @arg @ref RCC_IT_HSERDY HSE ready interrupt - * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt - * @arg @ref RCC_IT_PLL2RDY PLL2 ready interrupt - * @arg @ref RCC_IT_PLL3RDY PLL3 ready interrupt - * @arg @ref RCC_IT_CSS HSE Clock security system interrupt - * @arg @ref RCC_IT_HSI48RDY HSI48 ready interrupt - * @arg @ref RCC_IT_MSIKRDY MSIK ready interrupt - * @arg @ref RCC_IT_SHSIRDY SHSI ready interrupt - * @retval The new state of __INTERRUPT__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIFR & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** @brief Set RMVF bit to clear the reset flags. - * The reset flags are: RCC_FLAG_FWRRST, RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_BORRST, - * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST. - * @retval None - */ -#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF) - -/** @brief Check whether the selected RCC flag is set or not. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_FLAG_MSIRDY MSI oscillator clock ready - * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready - * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready - * @arg @ref RCC_FLAG_PLL1RDY Main PLL1 clock ready - * @arg @ref RCC_FLAG_PLL2RDY PLL2 clock ready - * @arg @ref RCC_FLAG_PLL3RDY PLL3 clock ready - * @arg @ref RCC_FLAG_HSI48RDY HSI48 clock ready - * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready - * @arg @ref RCC_FLAG_LSECSSD Clock security system failure on LSE oscillator detection - * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready - * @arg @ref RCC_FLAG_BORRST BOR reset - * @arg @ref RCC_FLAG_OBLRST OBLRST reset - * @arg @ref RCC_FLAG_PINRST Pin reset - * @arg @ref RCC_FLAG_RMVF Remove reset Flag - * @arg @ref RCC_FLAG_SFTRST Software reset - * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset - * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset - * @arg @ref RCC_FLAG_LPWRRST Low Power reset - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_RCC_GET_FLAG(__FLAG__) ((((((((__FLAG__) >> 5U) == 1U) ? RCC->CR : \ - ((((__FLAG__) >> 5U) == 2U) ? RCC->BDCR : \ - ((((__FLAG__) >> 5U) == 3U) ? RCC->CSR : RCC->CIFR)))) & \ - (1U << ((__FLAG__) & RCC_FLAG_MASK))) != 0U) ? 1U : 0U) -/** - * @} - */ -#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_MSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSI) || \ - ((SOURCE) == RCC_PLLSOURCE_HSE)) - -#define IS_RCC_PLLM_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 16U)) -#define IS_RCC_PLLN_VALUE(VALUE) ((4U <= (VALUE)) && ((VALUE) <= 512U)) -#define IS_RCC_PLLP_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) -#define IS_RCC_PLLQ_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) -#define IS_RCC_PLLR_VALUE(VALUE) ((1U <= (VALUE)) && ((VALUE) <= 128U)) -#define IS_RCC_STOP_WAKEUPCLOCK(__SOURCE__) (((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_MSI) ||\ - ((__SOURCE__) == RCC_STOP_WAKEUPCLOCK_HSI)) - -#define IS_RCC_STOP_KERWAKEUPCLOCK(SOURCE) (((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_MSI) || \ - ((SOURCE) == RCC_STOP_KERWAKEUPCLOCK_HSI)) -#define IS_RCC_MSI_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) || \ - ((__RANGE__) == RCC_MSIRANGE_1) || \ - ((__RANGE__) == RCC_MSIRANGE_2) || \ - ((__RANGE__) == RCC_MSIRANGE_3) || \ - ((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6) || \ - ((__RANGE__) == RCC_MSIRANGE_7) || \ - ((__RANGE__) == RCC_MSIRANGE_8) || \ - ((__RANGE__) == RCC_MSIRANGE_9) || \ - ((__RANGE__) == RCC_MSIRANGE_10) || \ - ((__RANGE__) == RCC_MSIRANGE_11) || \ - ((__RANGE__) == RCC_MSIRANGE_12) || \ - ((__RANGE__) == RCC_MSIRANGE_13) || \ - ((__RANGE__) == RCC_MSIRANGE_14) || \ - ((__RANGE__) == RCC_MSIRANGE_15)) - -#define IS_RCC_MSI_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_4) || \ - ((__RANGE__) == RCC_MSIRANGE_5) || \ - ((__RANGE__) == RCC_MSIRANGE_6) || \ - ((__RANGE__) == RCC_MSIRANGE_7) || \ - ((__RANGE__) == RCC_MSIRANGE_8)) - -#define IS_RCC_MSIK_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_0) || \ - ((__RANGE__) == RCC_MSIKRANGE_1) || \ - ((__RANGE__) == RCC_MSIKRANGE_2) || \ - ((__RANGE__) == RCC_MSIKRANGE_3) || \ - ((__RANGE__) == RCC_MSIKRANGE_4) || \ - ((__RANGE__) == RCC_MSIKRANGE_5) || \ - ((__RANGE__) == RCC_MSIKRANGE_6) || \ - ((__RANGE__) == RCC_MSIKRANGE_7) || \ - ((__RANGE__) == RCC_MSIKRANGE_8) || \ - ((__RANGE__) == RCC_MSIKRANGE_9) || \ - ((__RANGE__) == RCC_MSIKRANGE_10) || \ - ((__RANGE__) == RCC_MSIKRANGE_11) || \ - ((__RANGE__) == RCC_MSIKRANGE_12) || \ - ((__RANGE__) == RCC_MSIKRANGE_13) || \ - ((__RANGE__) == RCC_MSIKRANGE_14) || \ - ((__RANGE__) == RCC_MSIKRANGE_15)) - -#define IS_RCC_MSIK_STANDBY_CLOCK_RANGE(__RANGE__) (((__RANGE__) == RCC_MSIKRANGE_4) || \ - ((__RANGE__) == RCC_MSIKRANGE_5) || \ - ((__RANGE__) == RCC_MSIKRANGE_6) || \ - ((__RANGE__) == RCC_MSIKRANGE_7) || \ - ((__RANGE__) == RCC_MSIKRANGE_8)) - -/** - * @} - */ - -/* Include RCC HAL Extended module */ -#include "stm32u5xx_hal_rcc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ******************************/ -HAL_StatusTypeDef HAL_RCC_DeInit(void); -HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency); - -/** - * @} - */ - -/** @addtogroup RCC_Exported_Functions_Group2 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv); -void HAL_RCC_EnableCSS(void); -uint32_t HAL_RCC_GetSysClockFreq(void); -uint32_t HAL_RCC_GetHCLKFreq(void); -uint32_t HAL_RCC_GetPCLK1Freq(void); -uint32_t HAL_RCC_GetPCLK2Freq(void); -uint32_t HAL_RCC_GetPCLK3Freq(void); -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct); -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency); -uint32_t HAL_RCC_GetResetSource(void); -/* CSS NMI IRQ handler */ -void HAL_RCC_NMI_IRQHandler(void); -/* User Callbacks in non blocking mode (IT mode) */ -void HAL_RCC_CSSCallback(void); - -/** - * @} - */ - -/* Attributes management functions ********************************************/ -void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes); -HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes); - -/** - * @} - */ - -/** - * @} - */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_RCC_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h deleted file mode 100644 index dc7bf097c..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_rcc_ex.h +++ /dev/null @@ -1,2448 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_rcc_ex.h - * @author MCD Application Team - * @brief Header file of RCC HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_RCC_EX_H -#define STM32U5xx_HAL_RCC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup RCCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Types RCCEx Exported Types - * @{ - */ - -/** - * @brief PLL2 Clock structure definition - */ -typedef struct -{ - uint32_t PLL2Source; /*!< RCC_PLL2Source: PLL2 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLL2M; /*!< PLL2M: Division factor for PLL2 VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ - - uint32_t PLL2N; /*!< PLL2N: Multiplication factor for PLL2 VCO output clock. - This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ - - uint32_t PLL2P; /*!< PLL2P: Division factor for system clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLL2Q; /*!< PLL2Q: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLL2R; /*!< PLL2R: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLL2RGE; /*!< PLL2RGE: PLL2 clock Input range - This parameter must be a value of @ref RCC_PLL_VCI_Range */ - - uint32_t PLL2FRACN; /*!< PLL2FRACN: Specifies Fractional Part Of The Multiplication Factor for - PLL2 VCO It should be a value between 0 and 8191 */ - - uint32_t PLL2ClockOut; /*!< PLL2ClockOut: specifies PLL2 output clock to be enabled. - This parameter must be a value of @ref RCC_PLL2_Clock_Output */ -} RCC_PLL2InitTypeDef; - - -/** - * @brief PLL3 Clock structure definition - */ -typedef struct -{ - uint32_t PLL3Source; /*!< RCC_PLL3Source: PLL3 entry clock source. - This parameter must be a value of @ref RCC_PLL_Clock_Source */ - - uint32_t PLL3M; /*!< PLL3M: Division factor for PLL3 VCO input clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 63 */ - - uint32_t PLL3N; /*!< PLL3N: Multiplication factor for PLL3 VCO output clock. - This parameter must be a number between Min_Data = 4 and Max_Data = 512 */ - - uint32_t PLL3P; /*!< PLL3P: Division factor for system clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLL3Q; /*!< PLL3Q: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLL3R; /*!< PLL3R: Division factor for peripheral clocks. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 */ - - uint32_t PLL3RGE; /*!< PLL3RGE: PLL3 clock Input range - This parameter must be a value of @ref RCC_PLL_VCI_Range */ - - uint32_t PLL3FRACN; /*!< PLL3FRACN: Specifies Fractional Part Of The Multiplication Factor for - PLL3 VCO It should be a value between 0 and 8191 */ - - uint32_t PLL3ClockOut; /*!< PLL3ClockOut: specifies PLL3 output clock to be enabled. - This parameter must be a value of @ref RCC_PLL3_Clock_Output */ -} RCC_PLL3InitTypeDef; - -/** - * @brief RCC PLL1 Clocks structure definition - */ -typedef struct -{ - uint32_t PLL1_P_Frequency; - uint32_t PLL1_Q_Frequency; - uint32_t PLL1_R_Frequency; -} PLL1_ClocksTypeDef; - -/** - * @brief RCC PLL2 Clocks structure definition - */ -typedef struct -{ - uint32_t PLL2_P_Frequency; - uint32_t PLL2_Q_Frequency; - uint32_t PLL2_R_Frequency; -} PLL2_ClocksTypeDef; - -/** - * @brief RCC PLL3 Clocks structure definition - */ -typedef struct -{ - uint32_t PLL3_P_Frequency; - uint32_t PLL3_Q_Frequency; - uint32_t PLL3_R_Frequency; -} PLL3_ClocksTypeDef; - - -/** - * @brief RCC extended clocks structure definition - */ -typedef struct -{ - uint64_t PeriphClockSelection; /*!< The Extended Clock to be configured. - This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ - - RCC_PLL2InitTypeDef PLL2; /*!< PLL2structure parameters. - This parameter will be used only when PLL2 is selected as kernel clock Source - for some peripherals */ - - RCC_PLL3InitTypeDef PLL3; /*!< PLL3 structure parameters. - This parameter will be used only when PLL2 is selected as kernel clock Source - for some peripherals */ - - uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. - This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ - -#if defined(USART2) - uint32_t Usart2ClockSelection; /*!< Specifies USART2 clock source. - This parameter can be a value of @ref RCCEx_USART2_Clock_Source */ -#endif /* USART2 */ - - uint32_t Usart3ClockSelection; /*!< Specifies USART3 clock source. - This parameter can be a value of @ref RCCEx_USART3_Clock_Source */ - - uint32_t Uart4ClockSelection; /*!< Specifies UART4 clock source. - This parameter can be a value of @ref RCCEx_UART4_Clock_Source */ - - uint32_t Uart5ClockSelection; /*!< Specifies UART5 clock source. - This parameter can be a value of @ref RCCEx_UART5_Clock_Source */ - -#if defined(USART6) - uint32_t Usart6ClockSelection; /*!< Specifies USART6 clock source. - This parameter can be a value of @ref RCCEx_USART6_Clock_Source */ -#endif /* USART6 */ - - uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. - This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ - - uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. - This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ - - uint32_t I2c2ClockSelection; /*!< Specifies I2C2 clock source. - This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */ - - uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. - This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ - - uint32_t I2c4ClockSelection; /*!< Specifies I2C4 clock source. - This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */ - -#if defined(I2C5) - uint32_t I2c5ClockSelection; /*!< Specifies I2C5 clock source. - This parameter can be a value of @ref RCCEx_I2C5_Clock_Source */ -#endif /* I2C5 */ - -#if defined(I2C6) - uint32_t I2c6ClockSelection; /*!< Specifies I2C6 clock source. - This parameter can be a value of @ref RCCEx_I2C6_Clock_Source */ -#endif /* I2C6 */ - - uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. - This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ - - uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. - This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ - - uint32_t Lptim34ClockSelection; /*!< Specifies LPTIM3 and LPTIM4 clock source. - This parameter can be a value of @ref RCCEx_LPTIM34_Clock_Source */ - - uint32_t Fdcan1ClockSelection; /*!< Specifies FDCAN1 kernel clock source. - This parameter can be a value of @ref RCCEx_FDCAN1_Clock_Source */ - - uint32_t Mdf1ClockSelection; /*!< Specifies MDF1 kernel clock source. - This parameter can be a value of @ref RCCEx_MDF1_Clock_Source */ - - uint32_t Adf1ClockSelection; /*!< Specifies Adf1 kernel clock source. - This parameter can be a value of @ref RCCEx_ADF1_Clock_Source */ - - uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. - This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ - -#if defined (SAI2) - uint32_t Sai2ClockSelection; /*!< Specifies SAI2 clock source. - This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */ -#endif /* SAI2 */ - - uint32_t RngClockSelection; /*!< Specifies RNG clock source - This parameter can be a value of @ref RCCEx_RNG_Clock_Source */ - -#if defined(SAES) - uint32_t SaesClockSelection; /*!< Specifies SAES clock source - This parameter can be a value of @ref RCCEx_SAES_Clock_Source */ -#endif /* SAES */ - - uint32_t IclkClockSelection; /*!< Specifies intermediate clock source used by USB, RNG and SDMMC1 - This parameter can be a value of @ref RCCEx_ICLK_Clock_Source */ - - uint32_t SdmmcClockSelection; /*!< Specifies SDMMC1/2 clock source. - This parameter can be a value of @ref RCCEx_SDMMC_Clock_Source */ - - uint32_t AdcDacClockSelection; /*!< Specifies ADC1, ADC4 and DAC interface clock source. - This parameter can be a value of @ref RCCEx_ADCDAC_Clock_Source */ - - uint32_t Dac1ClockSelection; /*!< Specifies DAC1 interface clock source. - This parameter can be a value of @ref RCCEx_DAC1_Clock_Source */ - - uint32_t OspiClockSelection; /*!< Specifies OctoSPI clock source. - This parameter can be a value of @ref RCCEx_OSPI_Clock_Source */ - -#if defined(HSPI1) - uint32_t HspiClockSelection; /*!< Specifies HexaSPI clock source. - This parameter can be a value of @ref RCCEx_HSPI_Clock_Source */ -#endif /* HSPI1 */ - - uint32_t Spi1ClockSelection; /*!< Specifies SPI1 clock source - This parameter can be a value of @ref RCCEx_SPI1_Clock_Source */ - - uint32_t Spi2ClockSelection; /*!< Specifies SPI2 clock source - This parameter can be a value of @ref RCCEx_SPI2_Clock_Source */ - - uint32_t Spi3ClockSelection; /*!< Specifies SPI3 clock source - This parameter can be a value of @ref RCCEx_SPI3_Clock_Source */ - - uint32_t RTCClockSelection; /*!< Specifies RTC clock source. - This parameter can be a value of @ref RCC_RTC_Clock_Source */ - -#if defined(LTDC) - uint32_t LtdcClockSelection; /*!< Specifies LTDC clock source. - This parameter can be a value of @ref RCCEx_LTDC_Clock_Source */ -#endif /* LTDC */ - -#if defined(DSI) - uint32_t DsiClockSelection; /*!< Specifies DSI clock source. - This parameter can be a value of @ref RCCEx_DSI_Clock_Source */ -#endif /* DSI */ - -#if defined(USB_OTG_HS) - uint32_t UsbPhyClockSelection; /*!< Specifies USB PHY clock source. - This parameter can be a value of @ref RCCEx_USBPHY_Clock_Source */ -#endif /* USB_OTG_HS */ - -} RCC_PeriphCLKInitTypeDef; - -#if defined(CRS) - -/** - * @brief RCC_CRS Init structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal. - This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */ - - uint32_t Source; /*!< Specifies the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroSource */ - - uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source. - This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */ - - uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC - event. It can be calculated in using macro - __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) - This parameter must be a number between 0 and 0xFFFF or a value of - @ref RCCEx_CRS_ReloadValueDefault .*/ - - uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value. - This parameter must be a number between 0 and 0xFF or a value of - @ref RCCEx_CRS_ErrorLimitDefault */ - - uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator. - This parameter must be a number between 0 and 0x7F or a value of - @ref RCCEx_CRS_HSI48CalibrationDefault */ - -} RCC_CRSInitTypeDef; - -/** - * @brief RCC_CRS Synchronization structure definition - */ -typedef struct -{ - uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value. - This parameter must be a number between 0 and 0xFFFF */ - - uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming. - This parameter must be a number between 0 and 0x3F */ - - uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter - value latched in the time of the last SYNC event. - This parameter must be a number between 0 and 0xFFFF */ - - uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the - frequency error counter latched in the time of the last SYNC event. - It shows whether the actual frequency is below or above the target. - This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ - -} RCC_CRSSynchroInfoTypeDef; - -#endif /* CRS */ -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants - * @{ - */ - -/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source - * @{ - */ -#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */ -#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */ -/** - * @} - */ - -/** @defgroup RCCEx_MSI_Pll_Mode_Selection MSI Pll Mode Selection - * @{ - */ -#define RCC_MSIKPLL_MODE_SEL 0x00000000U /*!< PLL mode applied to MSIK (MSI kernel) clock output */ -#define RCC_MSISPLL_MODE_SEL RCC_CR_MSIPLLSEL /*!< PLL mode applied to MSIS (MSI system) clock output */ -/** - * @} - */ - -/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection - * @{ - */ -#define RCC_PERIPHCLK_USART1 ((uint64_t)0x00000001U) -#if defined(USART2) -#define RCC_PERIPHCLK_USART2 ((uint64_t)0x00000002U) -#endif /* USART2 */ -#define RCC_PERIPHCLK_USART3 ((uint64_t)0x00000004U) -#define RCC_PERIPHCLK_UART4 ((uint64_t)0x00000008U) -#define RCC_PERIPHCLK_UART5 ((uint64_t)0x00000010U) -#define RCC_PERIPHCLK_LPUART1 ((uint64_t)0x00000020U) -#define RCC_PERIPHCLK_I2C1 ((uint64_t)0x00000040U) -#define RCC_PERIPHCLK_I2C2 ((uint64_t)0x00000080U) -#define RCC_PERIPHCLK_I2C3 ((uint64_t)0x00000100U) -#define RCC_PERIPHCLK_LPTIM1 ((uint64_t)0x00000200U) -#define RCC_PERIPHCLK_LPTIM2 ((uint64_t)0x00000400U) -#define RCC_PERIPHCLK_LPTIM34 ((uint64_t)0x00000800U) -#if defined(SAES) -#define RCC_PERIPHCLK_SAES ((uint64_t)0x00001000U) -#endif /* SAES */ -#define RCC_PERIPHCLK_SAI1 ((uint64_t)0x00002000U) -#if defined(SAI2) -#define RCC_PERIPHCLK_SAI2 ((uint64_t)0x00004000U) -#endif /* SAI2 */ -#define RCC_PERIPHCLK_ADCDAC ((uint64_t)0x00008000U) -#define RCC_PERIPHCLK_MDF1 ((uint64_t)0x00010000U) -#define RCC_PERIPHCLK_ADF1 ((uint64_t)0x00020000U) -#define RCC_PERIPHCLK_RTC ((uint64_t)0x00040000U) -#define RCC_PERIPHCLK_RNG ((uint64_t)0x00080000U) -#define RCC_PERIPHCLK_ICLK ((uint64_t)0x00100000U) -#define RCC_PERIPHCLK_SDMMC ((uint64_t)0x00200000U) -#define RCC_PERIPHCLK_I2C4 ((uint64_t)0x00400000U) -#define RCC_PERIPHCLK_SPI1 ((uint64_t)0x00800000U) -#define RCC_PERIPHCLK_SPI2 ((uint64_t)0x01000000U) -#define RCC_PERIPHCLK_SPI3 ((uint64_t)0x02000000U) -#define RCC_PERIPHCLK_OSPI ((uint64_t)0x04000000U) -#define RCC_PERIPHCLK_FDCAN1 ((uint64_t)0x08000000U) -#define RCC_PERIPHCLK_DAC1 ((uint64_t)0x10000000U) -#if defined(USART6) -#define RCC_PERIPHCLK_USART6 ((uint64_t)0x20000000U) -#endif /* USART6 */ -#if defined(I2C5) -#define RCC_PERIPHCLK_I2C5 ((uint64_t)0x40000000U) -#endif /* I2C5 */ -#if defined(I2C6) -#define RCC_PERIPHCLK_I2C6 ((uint64_t)0x80000000U) -#endif /* I2C6 */ -#if defined(HSPI1) -#define RCC_PERIPHCLK_HSPI ((uint64_t)0x100000000U) -#endif /* HSPI1 */ -#if defined(LTDC) -#define RCC_PERIPHCLK_LTDC ((uint64_t)0x200000000U) -#endif /* LTDC */ -#if defined(DSI) -#define RCC_PERIPHCLK_DSI ((uint64_t)0x400000000U) -#endif /* DSI */ -#if defined(USB_OTG_HS) -#define RCC_PERIPHCLK_USBPHY ((uint64_t)0x800000000U) -#endif /* USB_OTG_HS */ -#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ - RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ - RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ - RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY) -#elif defined (STM32U5G7xx) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ - RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ - RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ - RCC_PERIPHCLK_USBPHY | RCC_PERIPHCLK_SAES) -#elif defined (STM32U5F7xx) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ - RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ - RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ - RCC_PERIPHCLK_USBPHY) -#elif (defined(STM32U595xx) || defined(STM32U5A5xx)) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ - RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ - RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY) -#elif defined(STM32U585xx) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ - RCC_PERIPHCLK_SAES | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ - RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \ - RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ - RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ - RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) -#elif defined(STM32U575xx) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 |RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ - RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_ICLK | \ - RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ - RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 |RCC_PERIPHCLK_OSPI | \ - RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) -#elif defined(STM32U535xx) -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ - RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ - RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ - RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) -#else -#define RCC_PERIPHCLOCK_ALL (RCC_PERIPHCLK_USART1 |RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 |RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ - RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_SAES | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ - RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ - RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1) -#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ -/** - * @} - */ - - -/** @defgroup RCC_PLL2_Clock_Output RCC PLL2 Clock Output - * @{ - */ -#define RCC_PLL2_DIVP RCC_PLL2CFGR_PLL2PEN -#define RCC_PLL2_DIVQ RCC_PLL2CFGR_PLL2QEN -#define RCC_PLL2_DIVR RCC_PLL2CFGR_PLL2REN -/** - * @} - */ - -/** @defgroup RCC_PLL3_Clock_Output RCC PLL3 Clock Output - * @{ - */ -#define RCC_PLL3_DIVP RCC_PLL3CFGR_PLL3PEN -#define RCC_PLL3_DIVQ RCC_PLL3CFGR_PLL3QEN -#define RCC_PLL3_DIVR RCC_PLL3CFGR_PLL3REN -/** - * @} - */ - -/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source - * @{ - */ -#define RCC_USART1CLKSOURCE_PCLK2 0x00000000U -#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR1_USART1SEL_0 -#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR1_USART1SEL_1 -#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR1_USART1SEL_0 | RCC_CCIPR1_USART1SEL_1) -/** - * @} - */ - -#if defined(USART2) -/** @defgroup RCCEx_USART2_Clock_Source USART2 Clock Source - * @{ - */ -#define RCC_USART2CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR1_USART2SEL_0 -#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR1_USART2SEL_1 -#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR1_USART2SEL_0 | RCC_CCIPR1_USART2SEL_1) -/** - * @} - */ -#endif /* USART2 */ - -/** @defgroup RCCEx_USART3_Clock_Source USART3 Clock Source - * @{ - */ -#define RCC_USART3CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART3CLKSOURCE_SYSCLK RCC_CCIPR1_USART3SEL_0 -#define RCC_USART3CLKSOURCE_HSI RCC_CCIPR1_USART3SEL_1 -#define RCC_USART3CLKSOURCE_LSE (RCC_CCIPR1_USART3SEL_0 | RCC_CCIPR1_USART3SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_UART4_Clock_Source UART4 Clock Source - * @{ - */ -#define RCC_UART4CLKSOURCE_PCLK1 0x00000000U -#define RCC_UART4CLKSOURCE_SYSCLK RCC_CCIPR1_UART4SEL_0 -#define RCC_UART4CLKSOURCE_HSI RCC_CCIPR1_UART4SEL_1 -#define RCC_UART4CLKSOURCE_LSE (RCC_CCIPR1_UART4SEL_0 | RCC_CCIPR1_UART4SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_UART5_Clock_Source UART5 Clock Source - * @{ - */ -#define RCC_UART5CLKSOURCE_PCLK1 0x00000000U -#define RCC_UART5CLKSOURCE_SYSCLK RCC_CCIPR1_UART5SEL_0 -#define RCC_UART5CLKSOURCE_HSI RCC_CCIPR1_UART5SEL_1 -#define RCC_UART5CLKSOURCE_LSE (RCC_CCIPR1_UART5SEL_0 | RCC_CCIPR1_UART5SEL_1) -/** - * @} - */ - -#if defined(USART6) -/** @defgroup RCCEx_USART6_Clock_Source USART6 Clock Source - * @{ - */ -#define RCC_USART6CLKSOURCE_PCLK1 0x00000000U -#define RCC_USART6CLKSOURCE_SYSCLK RCC_CCIPR2_USART6SEL_0 -#define RCC_USART6CLKSOURCE_HSI RCC_CCIPR2_USART6SEL_1 -#define RCC_USART6CLKSOURCE_LSE (RCC_CCIPR2_USART6SEL_0 | RCC_CCIPR2_USART6SEL_1) -/** - * @} - */ -#endif /* USART6 */ - -/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source - * @{ - */ -#define RCC_LPUART1CLKSOURCE_PCLK3 0x00000000U -#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 -#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 -#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) -#define RCC_LPUART1CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 -/** - * @} - */ - -/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source - * @{ - */ -#define RCC_I2C1CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR1_I2C1SEL_0 -#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR1_I2C1SEL_1 -#define RCC_I2C1CLKSOURCE_MSIK (RCC_CCIPR1_I2C1SEL_1 | RCC_CCIPR1_I2C1SEL_0) -/** - * @} - */ - -/** @defgroup RCCEx_I2C2_Clock_Source I2C2 Clock Source - * @{ - */ -#define RCC_I2C2CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CCIPR1_I2C2SEL_0 -#define RCC_I2C2CLKSOURCE_HSI RCC_CCIPR1_I2C2SEL_1 -#define RCC_I2C2CLKSOURCE_MSIK (RCC_CCIPR1_I2C2SEL_1 | RCC_CCIPR1_I2C2SEL_0) -/** - * @} - */ - -/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source - * @{ - */ -#define RCC_I2C3CLKSOURCE_PCLK3 0x00000000U -#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR3_I2C3SEL_0 -#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR3_I2C3SEL_1 -#define RCC_I2C3CLKSOURCE_MSIK (RCC_CCIPR3_I2C3SEL_0 | RCC_CCIPR3_I2C3SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_I2C4_Clock_Source I2C4 Clock Source - * @{ - */ -#define RCC_I2C4CLKSOURCE_PCLK1 0x00000000U -#define RCC_I2C4CLKSOURCE_SYSCLK RCC_CCIPR1_I2C4SEL_0 -#define RCC_I2C4CLKSOURCE_HSI RCC_CCIPR1_I2C4SEL_1 -#define RCC_I2C4CLKSOURCE_MSIK (RCC_CCIPR1_I2C4SEL_1 | RCC_CCIPR1_I2C4SEL_0) -/** - * @} - */ - -#if defined(I2C5) -/** @defgroup RCCEx_I2C5_Clock_Source I2C5 Clock Source - * @{ - */ -#define RCC_I2C5CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C5CLKSOURCE_SYSCLK RCC_CCIPR2_I2C5SEL_0 -#define RCC_I2C5CLKSOURCE_HSI RCC_CCIPR2_I2C5SEL_1 -#define RCC_I2C5CLKSOURCE_MSIK (RCC_CCIPR2_I2C5SEL_1 | RCC_CCIPR2_I2C5SEL_0) -/** - * @} - */ -#endif /* I2C5 */ - -#if defined(I2C6) -/** @defgroup RCCEx_I2C6_Clock_Source I2C6 Clock Source - * @{ - */ -#define RCC_I2C6CLKSOURCE_PCLK1 ((uint32_t)0x00000000U) -#define RCC_I2C6CLKSOURCE_SYSCLK RCC_CCIPR2_I2C6SEL_0 -#define RCC_I2C6CLKSOURCE_HSI RCC_CCIPR2_I2C6SEL_1 -#define RCC_I2C6CLKSOURCE_MSIK (RCC_CCIPR2_I2C6SEL_1 | RCC_CCIPR2_I2C6SEL_0) -/** - * @} - */ -#endif /* I2C6 */ - -/** @defgroup RCCEx_RNG_Clock_Source RCCEx RNG Clock Source - * @{ - */ -#define RCC_RNGCLKSOURCE_HSI48 0x00000000U -#define RCC_RNGCLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 -#define RCC_RNGCLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 -/** - * @} - */ - -#if defined(SAES) -/** @defgroup RCCEx_SAES_Clock_Source RCCEx SAES Clock Source - * @{ - */ -#define RCC_SAESCLKSOURCE_SHSI 0x00000000U -#define RCC_SAESCLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL -/** - * @} - */ -#endif /* SAES */ - -/** @defgroup RCCEx_SPI1_Clock_Source SPI1 Clock Source - * @{ - */ -#define RCC_SPI1CLKSOURCE_PCLK2 0x00000000U -#define RCC_SPI1CLKSOURCE_SYSCLK RCC_CCIPR1_SPI1SEL_0 -#define RCC_SPI1CLKSOURCE_HSI RCC_CCIPR1_SPI1SEL_1 -#define RCC_SPI1CLKSOURCE_MSIK (RCC_CCIPR1_SPI1SEL_0 | RCC_CCIPR1_SPI1SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_SPI2_Clock_Source SPI2 Clock Source - * @{ - */ -#define RCC_SPI2CLKSOURCE_PCLK1 0x00000000U -#define RCC_SPI2CLKSOURCE_SYSCLK RCC_CCIPR1_SPI2SEL_0 -#define RCC_SPI2CLKSOURCE_HSI RCC_CCIPR1_SPI2SEL_1 -#define RCC_SPI2CLKSOURCE_MSIK (RCC_CCIPR1_SPI2SEL_0 | RCC_CCIPR1_SPI2SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_SPI3_Clock_Source SPI3 Clock Source - * @{ - */ -#define RCC_SPI3CLKSOURCE_PCLK3 0x00000000U -#define RCC_SPI3CLKSOURCE_SYSCLK RCC_CCIPR3_SPI3SEL_0 -#define RCC_SPI3CLKSOURCE_HSI RCC_CCIPR3_SPI3SEL_1 -#define RCC_SPI3CLKSOURCE_MSIK (RCC_CCIPR3_SPI3SEL_0 | RCC_CCIPR3_SPI3SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM34_Clock_Source LPTIM34 Clock Source - * @{ - */ -#define RCC_LPTIM34CLKSOURCE_MSIK 0x00000000U -#define RCC_LPTIM34CLKSOURCE_LSI RCC_CCIPR3_LPTIM34SEL_0 -#define RCC_LPTIM34CLKSOURCE_HSI RCC_CCIPR3_LPTIM34SEL_1 -#define RCC_LPTIM34CLKSOURCE_LSE (RCC_CCIPR3_LPTIM34SEL_0 | RCC_CCIPR3_LPTIM34SEL_1) -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source - * @{ - */ -#define RCC_LPTIM1CLKSOURCE_MSIK 0x00000000U -#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR3_LPTIM1SEL_0 -#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR3_LPTIM1SEL_1 -#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR3_LPTIM1SEL -/** - * @} - */ - -/** @defgroup RCCEx_LPTIM2_Clock_Source LPTIM2 Clock Source - * @{ - */ -#define RCC_LPTIM2CLKSOURCE_PCLK1 0x00000000U -#define RCC_LPTIM2CLKSOURCE_LSI RCC_CCIPR1_LPTIM2SEL_0 -#define RCC_LPTIM2CLKSOURCE_HSI RCC_CCIPR1_LPTIM2SEL_1 -#define RCC_LPTIM2CLKSOURCE_LSE RCC_CCIPR1_LPTIM2SEL -/** - * @} - */ - -/** @defgroup RCCEx_FDCAN1_Clock_Source FDCAN1 Kernel Clock Source - * @{ - */ -#define RCC_FDCAN1CLKSOURCE_HSE 0x00000000U -#define RCC_FDCAN1CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 -#define RCC_FDCAN1CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 -/** - * @} - */ - -/** @defgroup RCCEx_ICLK_Clock_Source ICLK Clock Source - * @{ - */ -#define RCC_ICLK_CLKSOURCE_HSI48 0x00000000U -#define RCC_ICLK_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 -#define RCC_ICLK_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 -#define RCC_ICLK_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL -/** - * @} - */ - -/** @defgroup RCCEx_ADCDAC_Clock_Source ADC1 Clock Source - * @{ - */ -#define RCC_ADCDACCLKSOURCE_HCLK 0x00000000U -#define RCC_ADCDACCLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 -#define RCC_ADCDACCLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 -#define RCC_ADCDACCLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_1) -#define RCC_ADCDACCLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 -#define RCC_ADCDACCLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_0 | RCC_CCIPR3_ADCDACSEL_2) -/** - * @} - */ - -/** @defgroup RCCEx_MDF1_Clock_Source MDF1 Clock Source - * @{ - */ -#define RCC_MDF1CLKSOURCE_HCLK 0x00000000U -#define RCC_MDF1CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 -#define RCC_MDF1CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 -#define RCC_MDF1CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_0 | RCC_CCIPR2_MDF1SEL_1) -#define RCC_MDF1CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 -/** - * @} - */ - -/** @defgroup RCCEx_ADF1_Clock_Source ADF1 Clock Source - * @{ - */ -#define RCC_ADF1CLKSOURCE_HCLK 0x00000000U -#define RCC_ADF1CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 -#define RCC_ADF1CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 -#define RCC_ADF1CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_0 | RCC_CCIPR3_ADF1SEL_1) -#define RCC_ADF1CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 -/** - * @} - */ - -/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source - * @{ - */ -#define RCC_SAI1CLKSOURCE_PLL2 0x00000000U -#define RCC_SAI1CLKSOURCE_PLL3 RCC_CCIPR2_SAI1SEL_0 -#define RCC_SAI1CLKSOURCE_PLL1 RCC_CCIPR2_SAI1SEL_1 -#define RCC_SAI1CLKSOURCE_PIN (RCC_CCIPR2_SAI1SEL_1 | RCC_CCIPR2_SAI1SEL_0) -#define RCC_SAI1CLKSOURCE_HSI RCC_CCIPR2_SAI1SEL_2 -/** - * @} - */ - -#if defined(SAI2) -/** @defgroup RCCEx_SAI2_Clock_Source SAI2 Clock Source - * @{ - */ -#define RCC_SAI2CLKSOURCE_PLL2 0x00000000U -#define RCC_SAI2CLKSOURCE_PLL3 RCC_CCIPR2_SAI2SEL_0 -#define RCC_SAI2CLKSOURCE_PLL1 RCC_CCIPR2_SAI2SEL_1 -#define RCC_SAI2CLKSOURCE_PIN (RCC_CCIPR2_SAI2SEL_1 | RCC_CCIPR2_SAI2SEL_0) -#define RCC_SAI2CLKSOURCE_HSI RCC_CCIPR2_SAI2SEL_2 -/** - * @} - */ -#endif /* SAI2 */ - -/** @defgroup RCCEx_SDMMC_Clock_Source SDMMC1/2 Clock Source - * @{ - */ -#define RCC_SDMMCCLKSOURCE_CLK48 0x00000000U -#define RCC_SDMMCCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL -/** - * @} - */ - -/** @defgroup RCCEx_OSPI_Clock_Source OctoSPI Clock Source - * @{ - */ -#define RCC_OSPICLKSOURCE_SYSCLK 0x00000000U -#define RCC_OSPICLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 -#define RCC_OSPICLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 -#define RCC_OSPICLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) -/** - * @} - */ - -#if defined(HSPI1) -/** @defgroup RCCEx_HSPI_Clock_Source HexaSPI Clock Source - * @{ - */ -#define RCC_HSPICLKSOURCE_SYSCLK ((uint32_t)0x00000000U) -#define RCC_HSPICLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 -#define RCC_HSPICLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 -#define RCC_HSPICLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL -/** - * @} - */ -#endif /* HSPI1 */ - -/** @defgroup RCCEx_DAC1_Clock_Source DAC1 Clock Source - * @{ - */ -#define RCC_DAC1CLKSOURCE_LSE 0x00000000U -#define RCC_DAC1CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL -/** - * @} - */ - -/** @defgroup RCC_Timicsel_items RCC timicsel items - * @brief RCC Timicsel items to configure timicsel - * @{ - */ -#define RCC_TIMIC_HSI_256 RCC_CCIPR1_TIMICSEL_2 /*!= RCC_MSIRANGE_12) \ - {\ - MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM3), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ - RCC_ICSCR2_MSITRIM3_Pos));\ - }\ - else if(__MSIRANGE__ >= RCC_MSIRANGE_8)\ - {\ - MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM2), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ - RCC_ICSCR2_MSITRIM2_Pos));\ - }\ - else if(__MSIRANGE__ >= RCC_MSIRANGE_4)\ - {\ - MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM1), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ - RCC_ICSCR2_MSITRIM1_Pos));\ - } \ - else /* if(__MSIRANGE__ >= RCC_MSIRANGE_0) */\ - { \ - MODIFY_REG((RCC->ICSCR2), (RCC_ICSCR2_MSITRIM0), ((uint32_t)(__MSICALIBRATIONVALUE__)<<\ - RCC_ICSCR2_MSITRIM0_Pos));\ - } \ - } while(0) - -/** @brief Macro to configure timer input capture clock source. - * @param __TIMICSOURCE__ : specifies the TIMIC clock source - * This parameter can be one or a combination of the following values: - * @arg RCC_TIMIC_HSI_256: HSI/256 selected for Timer16/17 and LPTimer2 - * @arg RCC_TIMIC_MSI_1024: MSIS/1024 selected for Timer16/17 and LPTimer2 - * @arg RCC_TIMIC_MSI_4: MSIS/4 selected for Timer16/17 and LPTimer2 - * @arg RCC_TIMIC_MSIK_1024: MSIK/1024 selected for Timer16/17 and LPTimer2 - * @arg RCC_TIMIC_MSIK_4 : MSIK/4 selected for Timer16/17 and LPTimer2 - * @note combination to be avoid : - * RCC_TIMIC_MSI_1024 and RCC_TIMIC_MSIK_1024 - * RCC_TIMIC_MSI_4 and RCC_TIMIC_MSIK_4 - * @retval None - */ -#define __HAL_RCC_TIMIC_CLK_CONFIG(__TIMICSOURCE__) \ - do \ - { \ - /*Disable All TIMIC SOURCE*/ \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)); \ - /*Select TIMIC clock SOURCE*/ \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(uint32_t)(__TIMICSOURCE__));\ - } while(0) - -/** @brief Macro to disable timer input capture clock source. - * @retval None - */ -#define __HAL_RCC_TIMIC_CLK_DISABLE() MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL,(0x00000000)) - -/** @brief Macros to enable or disable the PLL2. - * @note After enabling PLL2, the application software should wait on - * PLL2RDY flag to be set indicating that PLL2 clock is stable and can - * be used as kernel clock source. - * @note The PLL2 is disabled by hardware when entering STOP and STANDBY modes. - * @retval None - */ -#define __HAL_RCC_PLL2_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL2ON) -#define __HAL_RCC_PLL2_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON) - -/** @brief Macro to configure the PLL2 clock source. - * @note This function must be used only when all PLL2 is disabled. - * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL2 clock entry - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL2 clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL2 clock entry - */ -#define __HAL_RCC_PLL2_PLLSOURCE_CONFIG(__PLL2SOURCE__) MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC,\ - (__PLL2SOURCE__)) - -/** @brief Macro to get the oscillator used as PLL2 clock source. - * @retval The oscillator used as PLL2 clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL2_OSCSOURCE() ((uint32_t)(RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC)) - -/** @brief Macro to configures the PLL2 source, multiplication and division factors. - * @note This function must be used only when PLL2 is disabled. - * @param __PLL2SOURCE__: specifies the PLL2 entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL2 clock entry - * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL2 clock entry - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL2 clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL2 clock entry - * @param __PLL2M__ specifies the division factor of PLL2 input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16 - * @param __PLL2N__: specifies the multiplication factor for PLL2 VCO output clock - * This parameter must be a number between 4 and 512. - * @note You have to set the PLL2N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * PLL2 clock frequency = f(PLL2) multiplied by PLL2N - * @param __PLL2P__: specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 - * @param __PLL2Q__: specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 - * @param __PLL2R__: specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 - * @retval None - */ -#define __HAL_RCC_PLL2_CONFIG(__PLL2SOURCE__, __PLL2M__, __PLL2N__, __PLL2P__, __PLL2Q__, __PLL2R__) \ - do \ - { \ - MODIFY_REG(RCC->PLL2CFGR,(RCC_PLL2CFGR_PLL2SRC|RCC_PLL2CFGR_PLL2M), ((__PLL2SOURCE__)<< RCC_PLL2CFGR_PLL2SRC_Pos) |\ - (((__PLL2M__) - 1U) << RCC_PLL2CFGR_PLL2M_Pos));\ - MODIFY_REG(RCC->PLL2DIVR ,(RCC_PLL2DIVR_PLL2N|RCC_PLL2DIVR_PLL2P|RCC_PLL2DIVR_PLL2Q|\ - RCC_PLL2DIVR_PLL2R), ((((__PLL2N__) - 1U) & RCC_PLL2DIVR_PLL2N) | ((((__PLL2P__) -1U)<< \ - RCC_PLL2DIVR_PLL2P_Pos) & RCC_PLL2DIVR_PLL2P) |\ - ((((__PLL2Q__) -1U) << RCC_PLL2DIVR_PLL2Q_Pos)& \ - RCC_PLL2DIVR_PLL2Q) | ((((__PLL2R__)- 1U) << \ - RCC_PLL2DIVR_PLL2R_Pos) & \ - RCC_PLL2DIVR_PLL2R))); \ - } while(0) - -/** - * @brief Enables or disables each clock output (PLL2_P_CLK, PLL2_Q_CLK, PLL2_R_CLK) - * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL2, - * This is mainly used to save Power. - * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock outputted. - * This parameter can be one or a combination of the following values: - * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface. - * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), - * the random number generator (<=48 MHz). - * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. - * @retval None - */ -#define __HAL_RCC_PLL2CLKOUT_ENABLE(__PLL2_CLOCKOUT__) SET_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) -#define __HAL_RCC_PLL2CLKOUT_DISABLE(__PLL2_CLOCKOUT__) CLEAR_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) - -/** - * @brief Macro to get the PLL2 clock output enable status. - * @param __PLL2_CLOCKOUT__ specifies the PLL2 clock to be outputted. - * This parameter can be one of the following values: - * This parameter can be one or a combination of the following values: - * @arg RCC_PLL2_DIVP: This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface. - * @arg RCC_PLL2_DIVQ: This clock is used to generate the clock for the USB FS (48 MHz), - * the random number generator (<=48 MHz). - * @arg RCC_PLL2_DIVR: Clock used to clock ADC peripheral. - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG(__PLL2_CLOCKOUT__) READ_BIT(RCC->PLL2CFGR, (__PLL2_CLOCKOUT__)) - -/** - * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL2 VCO - * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL2 - * @retval None - */ -#define __HAL_RCC_PLL2FRACN_ENABLE() SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) -#define __HAL_RCC_PLL2FRACN_DISABLE() CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) - -/** - * @brief Macro to configures PLL2 clock Fractional Part Of The Multiplication Factor - * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL2 VCO - * @param __PLL2FRACN__: Specifies Fractional Part Of The Multiplication factor for PLL2 VCO - * It should be a value between 0 and 8191 - * @note Warning: the software has to set correctly these bits to insure that the VCO - * output frequency is between its valid frequency range, which is: - * 192 to 836 MHz if PLL2VCOSEL = 0 - * 150 to 420 MHz if PLL2VCOSEL = 1 - * @retval None - */ -#define __HAL_RCC_PLL2FRACN_CONFIG(__PLL2FRACN__) MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN,\ - (uint32_t)(__PLL2FRACN__) << RCC_PLL2FRACR_PLL2FRACN_Pos) - -/** @brief Macro to select the PLL2 reference frequency range. - * @param __PLL2VCIRange__: specifies the PLL2 input frequency range - * This parameter can be one of the following values: - * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz - * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz - * @retval None - */ -#define __HAL_RCC_PLL2_VCIRANGE(__PLL2VCIRange__) \ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, (__PLL2VCIRange__)) - -/** @brief Macros to enable or disable the main PLL3. - * @note After enabling PLL3, the application software should wait on - * PLL3RDY flag to be set indicating that PLL3 clock is stable and can - * be used as kernel clock source. - * @note PLL3 is disabled by hardware when entering STOP and STANDBY modes. - */ -#define __HAL_RCC_PLL3_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLL3ON) -#define __HAL_RCC_PLL3_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON) - -/** @brief Macro to configure the PLL3 clock source. - * @note This function must be used only when all PLL3 is disabled. - * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. - * This parameter can be one of the following values: - * @arg RCC_PLLSOURCE_MSI: MSI oscillator clock selected as PLL3 clock entry - * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL3 clock entry - * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL3 clock entry - * - */ -#define __HAL_RCC_PLL3_PLLSOURCE_CONFIG(__PLL3SOURCE__) MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, \ - (__PLL3SOURCE__)) - -/** @brief Macro to get the oscillator used as PLL3 clock source. - * @retval The oscillator used as PLL3 clock source. The returned value can be one - * of the following: - * - RCC_PLLSOURCE_NONE: No oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_MSI: MSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source. - * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source. - */ -#define __HAL_RCC_GET_PLL3_OSCSOURCE() ((uint32_t)(RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC)) - -/** @brief Macro to configures the PLL3 source, multiplication and division factors. - * @note This function must be used only when PLL3 is disabled. - * - * @param __PLL3SOURCE__: specifies the PLL3 entry clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_PLLSOURCE_NONE No clock selected as PLL3 clock entry - * @arg @ref RCC_PLLSOURCE_MSI MSI oscillator clock selected as PLL3 clock entry - * @arg @ref RCC_PLLSOURCE_HSI HSI oscillator clock selected as PLL3 clock entry - * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL3 clock entry - * @param __PLL3M__ specifies the division factor of PLL3 input clock. - * This parameter must be a number between Min_Data = 1 and Max_Data = 16 - * @param __PLL3N__: specifies the multiplication factor for PLL3 VCO output clock - * This parameter must be a number between 4 and 512. - * @note You have to set the PLL3N parameter correctly to ensure that the VCO - * output frequency is between 64 and 344 MHz. - * PLL3 clock frequency = f(PLL3) multiplied by PLL3N - * @param __PLL3P__: specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 - * @param __PLL3Q__: specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 - * @param __PLL3R__: specifies the division factor for peripheral kernel clocks - * This parameter must be a number between 1 and 128 - * @retval None - */ -#define __HAL_RCC_PLL3_CONFIG(__PLL3SOURCE__, __PLL3M__, __PLL3N__, __PLL3P__, __PLL3Q__, __PLL3R__) \ - do\ - {\ - MODIFY_REG(RCC->PLL3CFGR,(RCC_PLL3CFGR_PLL3SRC|RCC_PLL3CFGR_PLL3M), ((__PLL3SOURCE__) << RCC_PLL3CFGR_PLL3SRC_Pos)|\ - (((__PLL3M__) - 1U) << RCC_PLL3CFGR_PLL3M_Pos));\ - MODIFY_REG(RCC->PLL3DIVR ,(RCC_PLL3DIVR_PLL3N|RCC_PLL3DIVR_PLL3P|RCC_PLL3DIVR_PLL3Q|RCC_PLL3DIVR_PLL3R),\ - ((((__PLL3N__) - 1U) & RCC_PLL3DIVR_PLL3N) | ((((__PLL3P__) -1U) << RCC_PLL3DIVR_PLL3P_Pos) &\ - RCC_PLL3DIVR_PLL3P) | ((((__PLL3Q__) -1U) << \ - RCC_PLL3DIVR_PLL3Q_Pos) & \ - RCC_PLL3DIVR_PLL3Q) | \ - ((((__PLL3R__)- 1U) << RCC_PLL3DIVR_PLL3R_Pos) & RCC_PLL3DIVR_PLL3R))); \ - } while(0) - -/** - * @brief Macro to configures PLL3 clock Fractional Part of The Multiplication Factor - * @note These bits can be written at any time, allowing dynamic fine-tuning of the PLL3 VCO - * @param __PLL3FRACN__: specifies Fractional Part Of The Multiplication Factor for PLL3 VCO - * It should be a value between 0 and 8191 - * @note Warning: the software has to set correctly these bits to insure that the VCO - * output frequency is between its valid frequency range, which is: - * 192 to 836 MHz if PLL3VCOSEL = 0 - * 150 to 420 MHz if PLL3VCOSEL = 1 - * @retval None - */ -#define __HAL_RCC_PLL3FRACN_CONFIG(__PLL3FRACN__) MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, \ - (uint32_t)(__PLL3FRACN__) << RCC_PLL3FRACR_PLL3FRACN_Pos) - -/** @brief Macro to select the PLL3 reference frequency range. - * @param __PLL3VCIRange__: specifies the PLL1 input frequency range - * This parameter can be one of the following values: - * @arg RCC_PLLVCIRANGE_0: Range frequency is between 4 and 8 MHz - * @arg RCC_PLLVCIRANGE_1: Range frequency is between 8 and 16 MHz - * @retval None - */ -#define __HAL_RCC_PLL3_VCIRANGE(__PLL3VCIRange__) \ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, (__PLL3VCIRange__)) - -/** - * @brief Enables or disables Fractional Part Of The Multiplication Factor of PLL3 VCO - * @note Enabling/disabling Fractional Part can be any time without the need to stop the PLL3 - * @retval None - */ -#define __HAL_RCC_PLL3FRACN_ENABLE() SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) -#define __HAL_RCC_PLL3FRACN_DISABLE() CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) - -/** - * @brief Enables or disables each clock output (PLL3_P_CLK, PLL3_Q_CLK, PLL3_R_CLK) - * @note Enabling/disabling Those Clocks can be any time without the need to stop the PLL3, - * This is mainly used to save Power. - * @param __PLL3_CLOCKOUT__: specifies the PLL3 clock to be outputted - * This parameter can be one of the following values: - * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface. - * @retval None - */ -#define __HAL_RCC_PLL3CLKOUT_ENABLE(__PLL3_CLOCKOUT__) SET_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) -#define __HAL_RCC_PLL3CLKOUT_DISABLE(__PLL3_CLOCKOUT__) CLEAR_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) - -/** - * @brief Macro to get clock output enable status (PLL3_SAI2). - * @param __PLL3_CLOCKOUT__ specifies the PLL3 clock to be outputted. - * This parameter can be one of the following values: - * @arg RCC_PLL3_DIVP: This clock is used to generate an accurate clock to achieve - * high-quality audio performance on SAI interface. - * @retval SET / RESET - */ -#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG(__PLL3_CLOCKOUT__) READ_BIT(RCC->PLL3CFGR, (__PLL3_CLOCKOUT__)) - -/** @brief Macro to configure the ADC1, ADC2, ADC4 and DAC interface clock. - * @param __ADCDAC_CLKSOURCE__ specifies the ADC1, ADC4 and DAC digital interface clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock selected as ADC1, ADC2, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock selected as ADC1, ADC2 ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock selected as ADC1, ADC2 ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock selected as ADC1, ADC2 ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock selected as ADC1, ADC2 ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock selected as ADC1, ADC2 ADC4 and DAC clock - * @retval None - */ -#define __HAL_RCC_ADCDAC_CONFIG(__ADCDAC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, (uint32_t)(__ADCDAC_CLKSOURCE__)) - -/** @brief Macro to get the ADCDAC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADCDACCLKSOURCE_HCLK clock used as ADC1, ADC2, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_SYSCLK clock used as ADC1, ADC2, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_PLL2 clock used as ADC1, ADC2, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSE clock used as ADC1, ADC2, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_HSI clock used as ADC1, ADC2, ADC4 and DAC clock - * @arg @ref RCC_ADCDACCLKSOURCE_MSIK clock used as ADC1, ADC2, ADC4 and DAC clock - */ -#define __HAL_RCC_GET_ADCDAC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL))) - -/** @brief Macro to configure the CLK48 source (CLK48CLK). - * @param __CLK48_SOURCE__: specifies the CLK48 clock source. - * This parameter can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 selected as CLK48 source - * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 selected as CLK48 source - * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 selected as CLK48 source - * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK selected as CLK48 source - */ -#define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, (uint32_t)(__CLK48_SOURCE__)) - -/** @brief macro to get the CLK48 source. - * @retval The clock source can be one of the following values: - * @arg RCC_CLK48CLKSOURCE_HSI48: HSI48 used as CLK48 source - * @arg RCC_CLK48CLKSOURCE_PLL2 : PLL2 used as CLK48 source - * @arg RCC_CLK48CLKSOURCE_PLL1 : PLL1 used as CLK48 source - * @arg RCC_CLK48CLKSOURCE_MSIK : MSIK used as CLK48 source - */ -#define __HAL_RCC_GET_ICLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL))) - -/** @brief Macro to configure the FDCAN1 kernel clock (FDCAN1CLK). - * @param __FDCAN1_CLKSOURCE__ specifies the FDCAN1 kernel clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock - * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock - * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock - * @retval None - */ -#define __HAL_RCC_FDCAN1_CONFIG(__FDCAN1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, (uint32_t)(__FDCAN1_CLKSOURCE__)) - -/** @brief Macro to get the FDCAN1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_FDCAN1CLKSOURCE_HSE HSE selected as FDCAN1 kernel clock - * @arg @ref RCC_FDCAN1CLKSOURCE_PLL1 PLL1 Clock selected as FDCAN1 kernel clock - * @arg @ref RCC_FDCAN1CLKSOURCE_PLL2 PLL2 Clock selected as FDCAN1 kernel clock - */ -#define __HAL_RCC_GET_FDCAN1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL))) - -/** @brief Macro to configure the LPTIM34 clock (LPTIM34CLK). - * @param __LPTIM34_CLKSOURCE__ specifies the LPTIM34 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock - * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock - * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock - * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock - * @retval None - */ -#define __HAL_RCC_LPTIM34_CONFIG(__LPTIM34_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL, (uint32_t)(__LPTIM34_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM34 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM34CLKSOURCE_MSIK MSIK selected as LPTIM34 clock - * @arg @ref RCC_LPTIM34CLKSOURCE_LSI LSI selected as LPTIM34 clock - * @arg @ref RCC_LPTIM34CLKSOURCE_HSI HSI selected as LPTIM34 clock - * @arg @ref RCC_LPTIM34CLKSOURCE_LSE LSE selected as LPTIM34 clock - */ -#define __HAL_RCC_GET_LPTIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM34SEL))) - -/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). - * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSI LSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock - * @retval None - */ -#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM1CLKSOURCE_MSIK MSIK selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_HSI HSI selected as LPTIM1 clock - * @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock - */ -#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPTIM1SEL))) - -/** @brief Macro to configure the LPTIM2 clock (LPTIM2CLK). - * @param __LPTIM2_CLKSOURCE__ specifies the LPTIM2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSI LSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock - * @retval None - */ -#define __HAL_RCC_LPTIM2_CONFIG(__LPTIM2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL, (uint32_t)(__LPTIM2_CLKSOURCE__)) - -/** @brief Macro to get the LPTIM2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPTIM2CLKSOURCE_PCLK1 PCLK1 selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSI HSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_HSI HSI selected as LPTIM2 clock - * @arg @ref RCC_LPTIM2CLKSOURCE_LSE LSE selected as LPTIM2 clock - */ -#define __HAL_RCC_GET_LPTIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_LPTIM2SEL))) - -/** @brief macro to configure the SPI1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock selected as SPI1 clock - * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI1 clock - * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock selected as SPI1 clock - * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock selected as SPI1 clock - */ - -#define __HAL_RCC_SPI1_CONFIG(__SPI1CLKSource__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL, (uint32_t)(__SPI1CLKSource__)) - -/** @brief macro to get the SPI1 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SPI1CLKSOURCE_PCLK2 : PCLK2 Clock used as SPI1 clock - * @arg RCC_SPI1CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI1 clock - * @arg RCC_SPI1CLKSOURCE_HSI : HSI Clock used as SPI1 clock - * @arg RCC_SPI1CLKSOURCE_MSIK : MSIK Clock used as SPI1 clock - */ -#define __HAL_RCC_GET_SPI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI1SEL))) - -/** @brief macro to configure the SPI2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SPI2CLKSOURCE_PCLK3 : PCLK3 selected as SPI2 clock - * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI2 clock - * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock selected as SPI2 clock - * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock selected as SPI2 clock - */ - -#define __HAL_RCC_SPI2_CONFIG(__SPI2CLKSource__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL, (uint32_t)(__SPI2CLKSource__)) - -/** @brief macro to get the SPI2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SPI2CLKSOURCE_PCLK1 : PCLK1 Clock used as SPI2 clock - * @arg RCC_SPI2CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI2 clock - * @arg RCC_SPI2CLKSOURCE_HSI : HSI Clock used as SPI2 clock - * @arg RCC_SPI2CLKSOURCE_MSIK : MSIK Clock used as SPI2 clock - */ -#define __HAL_RCC_GET_SPI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SPI2SEL))) - -/** @brief macro to configure the SPI3 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 selected as SPI3 clock - * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock selected as SPI3 clock - * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock selected as SPI3 clock - * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock selected as SPI3 clock - */ -#define __HAL_RCC_SPI3_CONFIG(__SPI3CLKSource__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL, (uint32_t)(__SPI3CLKSource__)) - -/** @brief macro to get the SPI3 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SPI3CLKSOURCE_PCLK3 : PCLK3 used as SPI3 clock - * @arg RCC_SPI3CLKSOURCE_SYSCLK : SYSCLK Clock used as SPI3 clock - * @arg RCC_SPI3CLKSOURCE_HSI : HSI Clock used as SPI3 clock - * @arg RCC_SPI3CLKSOURCE_MSIK : MSIK Clock used as SPI3 clock - */ -#define __HAL_RCC_GET_SPI3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_SPI3SEL))) - - -/** @brief Macro to configure the I2C1 clock (I2C1CLK). - * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock - * @retval None - */ -#define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__)) - -/** @brief Macro to get the I2C1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C1CLKSOURCE_PCLK1 PCLK1 selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_SYSCLK System Clock selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_HSI HSI selected as I2C1 clock - * @arg @ref RCC_I2C1CLKSOURCE_MSIK MSIK selected as I2C1 clock - */ -#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C1SEL))) - -/** @brief Macro to configure the I2C2 clock (I2C2CLK). - * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock - * @retval None - */ -#define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__)) - -/** @brief Macro to get the I2C2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C2CLKSOURCE_PCLK1 PCLK1 selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_SYSCLK System Clock selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_HSI HSI selected as I2C2 clock - * @arg @ref RCC_I2C2CLKSOURCE_MSIK MSIK selected as I2C2 clock - */ -#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C2SEL))) - -/** @brief Macro to configure the I2C3 clock (I2C3CLK). - * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK selected as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock selected as I2C3 clock - * @retval None - */ -#define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__)) - -/** @brief Macro to get the I2C3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C3CLKSOURCE_PCLK3 : PCLK3 used as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_HSI : HSI used as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_MSIK : MSIK used as I2C3 clock - * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK : System Clock used as I2C3 clock - */ -#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_I2C3SEL))) - -/** @brief Macro to configure the I2C4 clock (I2C4CLK). - * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock - * @retval None - */ -#define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__)) - -/** @brief Macro to get the I2C4 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C4CLKSOURCE_PCLK1 PCLK1 selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_SYSCLK System Clock selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_HSI HSI selected as I2C4 clock - * @arg @ref RCC_I2C4CLKSOURCE_MSIK MSIK selected as I2C4 clock - */ -#define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_I2C4SEL))) - -#if defined(I2C5) -/** @brief Macro to configure the I2C5 clock (I2C5CLK). - * - * @param __I2C5_CLKSOURCE__ specifies the I2C5 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock - * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock - * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock - * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock - * @retval None - */ -#define __HAL_RCC_I2C5_CONFIG(__I2C5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL, (uint32_t)(__I2C5_CLKSOURCE__)) - -/** @brief Macro to get the I2C5 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C5CLKSOURCE_PCLK1 PCLK1 selected as I2C5 clock - * @arg @ref RCC_I2C5CLKSOURCE_SYSCLK System Clock selected as I2C5 clock - * @arg @ref RCC_I2C5CLKSOURCE_HSI HSI selected as I2C5 clock - * @arg @ref RCC_I2C5CLKSOURCE_MSIK MSIK selected as I2C5 clock - */ -#define __HAL_RCC_GET_I2C5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C5SEL))) -#endif /* I2C5 */ - -#if defined(I2C6) -/** @brief Macro to configure the I2C6 clock (I2C6CLK). - * - * @param __I2C6_CLKSOURCE__ specifies the I2C6 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock - * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock - * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock - * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock - * @retval None - */ -#define __HAL_RCC_I2C6_CONFIG(__I2C6_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL, (uint32_t)(__I2C6_CLKSOURCE__)) - -/** @brief Macro to get the I2C6 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_I2C6CLKSOURCE_PCLK1 PCLK1 selected as I2C6 clock - * @arg @ref RCC_I2C6CLKSOURCE_SYSCLK System Clock selected as I2C6 clock - * @arg @ref RCC_I2C6CLKSOURCE_HSI HSI selected as I2C6 clock - * @arg @ref RCC_I2C6CLKSOURCE_MSIK MSIK selected as I2C6 clock - */ -#define __HAL_RCC_GET_I2C6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_I2C6SEL))) -#endif /* I2C6 */ - -/** @brief Macro to configure the USART1 clock (USART1CLK). - * @param __USART1_CLKSOURCE__ specifies the USART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE SE selected as USART1 clock - * @retval None - */ -#define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__)) - -/** @brief Macro to get the USART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART1CLKSOURCE_PCLK2 PCLK1 selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_HSI HSI selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_SYSCLK System Clock selected as USART1 clock - * @arg @ref RCC_USART1CLKSOURCE_LSE LSE selected as USART1 clock - */ -#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART1SEL))) - -#if defined(USART2) -/** @brief Macro to configure the USART2 clock (USART2CLK). - * @param __USART2_CLKSOURCE__ specifies the USART2 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - * @retval None - */ -#define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__)) - -/** @brief Macro to get the USART2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART2CLKSOURCE_PCLK1 PCLK1 selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_HSI HSI selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_SYSCLK System Clock selected as USART2 clock - * @arg @ref RCC_USART2CLKSOURCE_LSE LSE selected as USART2 clock - */ -#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART2SEL))) -#endif /* USART2 */ - -/** @brief Macro to configure the USART3 clock (USART3CLK). - * - * @param __USART3_CLKSOURCE__ specifies the USART3 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - * @retval None - */ -#define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__)) - -/** @brief Macro to get the USART3 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART3CLKSOURCE_PCLK1 PCLK1 selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_HSI HSI selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_SYSCLK System Clock selected as USART3 clock - * @arg @ref RCC_USART3CLKSOURCE_LSE LSE selected as USART3 clock - */ -#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_USART3SEL))) - -/** @brief Macro to configure the UART4 clock (UART4CLK). - * - * @param __UART4_CLKSOURCE__ specifies the UART4 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock - * @retval None - */ -#define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__)) - -/** @brief Macro to get the UART4 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_UART4CLKSOURCE_PCLK1 PCLK1 selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_HSI HSI selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_SYSCLK System Clock selected as UART4 clock - * @arg @ref RCC_UART4CLKSOURCE_LSE LSE selected as UART4 clock - */ -#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART4SEL))) - -/** @brief Macro to configure the UART5 clock (UART5CLK). - * @param __UART5_CLKSOURCE__ specifies the UART5 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock - * @retval None - */ -#define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__)) - -/** @brief Macro to get the UART5 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_UART5CLKSOURCE_PCLK1 PCLK1 selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_HSI HSI selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_SYSCLK System Clock selected as UART5 clock - * @arg @ref RCC_UART5CLKSOURCE_LSE LSE selected as UART5 clock - */ -#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_UART5SEL))) - -#if defined(USART6) -/** @brief Macro to configure the USART6 clock (USART6CLK). - * - * @param __USART6_CLKSOURCE__ specifies the USART6 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock - * @retval None - */ -#define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__)) - -/** @brief Macro to get the USART6 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USART6CLKSOURCE_PCLK1 PCLK1 selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_HSI HSI selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_SYSCLK System Clock selected as USART6 clock - * @arg @ref RCC_USART6CLKSOURCE_LSE LSE selected as USART6 clock - */ -#define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USART6SEL))) -#endif /* USART6 */ - -/** @brief Macro to configure the LPUART1 clock (LPUART1CLK). - * - * @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock - * @retval None - */ -#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__)) - -/** @brief Macro to get the LPUART1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LPUART1CLKSOURCE_PCLK3 PCLK3 selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_MSIK MSIK selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock - * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock - */ -#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL))) - -/** @brief Macro to configure the OctoSPI clock. - * @param __OSPI_CLKSOURCE__ specifies the OctoSPI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock - * @retval None - */ -#define __HAL_RCC_OSPI_CONFIG(__OSPI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, (uint32_t)(__OSPI_CLKSOURCE__)) - -/** @brief Macro to get the OctoSPI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_OSPICLKSOURCE_SYSCLK System Clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_MSIK MSIK clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as OctoSPI clock - * @arg @ref RCC_OSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as OctoSPI clock - */ -#define __HAL_RCC_GET_OSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL))) - -#if defined(HSPI1) -/** @brief Macro to configure the HexaSPI clock. - * @param __HSPI_CLKSOURCE__ specifies the HexaSPI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock - * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock - * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock - * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock - * @retval None - */ -#define __HAL_RCC_HSPI_CONFIG(__HSPI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, (uint32_t)(__HSPI_CLKSOURCE__)) - -/** @brief Macro to get the HexaSPI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_HSPICLKSOURCE_SYSCLK System Clock selected as HexaSPI clock - * @arg @ref RCC_HSPICLKSOURCE_PLL1 PLL1 Q divider clock selected as HexaSPI clock - * @arg @ref RCC_HSPICLKSOURCE_PLL2 PLL2 Q divider clock selected as HexaSPI clock - * @arg @ref RCC_HSPICLKSOURCE_PLL3 PLL3 R divider clock selected as HexaSPI clock - */ -#define __HAL_RCC_GET_HSPI_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_HSPISEL))) -#endif /* HSPI1 */ - -/** @brief Macro to configure the SDMMC1/2 clock (SDMMCCLK). - * @param __SDMMC_CLKSOURCE__: specifies the SDMMC1/2 clock source. - * This parameter can be one of the following values: - * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock - * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock - */ -#define __HAL_RCC_SDMMC_CONFIG(__SDMMC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, (uint32_t)(__SDMMC_CLKSOURCE__)) - -/** @brief macro to get the SDMMC1/2 clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SDMMCCLKSOURCE_CLK48: CLK48 selected as SDMMC1/2 clock - * @arg RCC_SDMMCCLKSOURCE_PLL1: PLL1 P selected as SDMMC1/2 clock - */ -#define __HAL_RCC_GET_SDMMC_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL))) - -/** @brief macro to configure the RNG clock (RNGCLK). - * @param __RNG_CLKSource__: specifies the RNG clock source. - * This parameter can be one of the following values: - * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock - * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock - * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock - */ -#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSource__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, (uint32_t)(__RNG_CLKSource__)) - -/** @brief macro to get the RNG clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock - * @arg RCC_RNGCLKSOURCE_HSI48_DIV2: HSI48/2 selected as RNG clock - * @arg RCC_RNGCLKSOURCE_HSI: HSI selected as RNG clock - */ -#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_RNGSEL))) - -#if defined(SAES) -/** @brief macro to configure the SAES clock (SAESCLK). - * @param __SAES_CLKSource__: specifies the SAES clock source. - * This parameter can be one of the following values: - * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock - * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock - */ -#define __HAL_RCC_SAES_CONFIG(__SAES_CLKSource__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, (uint32_t)(__SAES_CLKSource__)) - -/** @brief macro to get the SAES clock source. - * @retval The clock source can be one of the following values: - * @arg RCC_SAESCLKSOURCE_SHSI: SHSI selected as SAES clock - * @arg RCC_SAESCLKSOURCE_SHSI_DIV2: SHSI/2 selected as SAES clock - */ -#define __HAL_RCC_GET_SAES_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAESSEL))) -#endif /* SAES */ - -/** - * @brief Macro to configure the SAI1 clock source. - * @param __SAI1_CLKSOURCE__ defines the SAI1 clock source. This clock is derived - * from the PLL2, system PLL or external clock (through a dedicated pin). - * This parameter can be one of the following values: - * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL1 "P" clock (PLL1CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) - * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 - * - * @note HSI16 is automatically set as SAI1 clock source when PLL are disabled for devices without PLL3. - * @retval None - */ -#define __HAL_RCC_SAI1_CONFIG(__SAI1_CLKSOURCE__)\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL, (uint32_t)(__SAI1_CLKSOURCE__)) - -/** @brief Macro to get the SAI1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SAI1CLKSOURCE_PLL2 SAI1 clock = PLL2 "P" clock (PLL2CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PLL3 SAI1 clock = PLL3 "P" clock (PLL3CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PLL1 SAI1 clock = PLL "P" clock (PLL1CLK) - * @arg @ref RCC_SAI1CLKSOURCE_PIN SAI1 clock = External Clock (SAI1_EXTCLK) - * @arg @ref RCC_SAI1CLKSOURCE_HSI SAI1 clock = HSI16 - * @note Despite returned values RCC_SAI1CLKSOURCE_PLL2 or RCC_SAI1CLKSOURCE_PLL, HSI16 is automatically set as SAI1 - * clock source when PLLs are disabled for devices without PLL3. - */ -#define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI1SEL))) - -#if defined(SAI2) -/** - * @brief Macro to configure the SAI2 clock source. - * @param __SAI2_CLKSOURCE__ defines the SAI2 clock source. This clock is derived - * from the PLL3, system PLL or external clock (through a dedicated pin). - * This parameter can be one of the following values: - * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) - * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 - * @retval None - */ -#define __HAL_RCC_SAI2_CONFIG(__SAI2_CLKSOURCE__ )\ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL, (uint32_t)(__SAI2_CLKSOURCE__)) - -/** @brief Macro to get the SAI2 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_SAI2CLKSOURCE_PLL2 SAI2 clock = PLL2 "P" clock (PLL2CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL3 SAI2 clock = PLL3 "P" clock (PLL3CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PLL1 SAI2 clock = PLL1 "P" clock (PLL1CLK) - * @arg @ref RCC_SAI2CLKSOURCE_PIN SAI2 clock = External Clock (SAI2_EXTCLK) - * @arg @ref RCC_SAI2CLKSOURCE_HSI SAI2 clock = HSI16 - */ -#define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_SAI2SEL))) -#endif /* SAI2 */ - -/** @brief Macro to configure the MDF1 clock. - * @param __MDF1_CLKSOURCE__ specifies the MDF1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock selected as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 P Clock selected as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Q Clock selected as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock selected as MDF1 clock - * @retval None - */ -#define __HAL_RCC_MDF1_CONFIG(__MDF1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, (uint32_t)(__MDF1_CLKSOURCE__)) - -/** @brief Macro to get the MDF1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_MDF1CLKSOURCE_HCLK HCLK Clock used as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_PLL1 PLL1 Clock used as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_PLL3 PLL3 Clock used as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as MDF1 clock - * @arg @ref RCC_MDF1CLKSOURCE_MSIK MSIK Clock used as MDF1 clock - */ -#define __HAL_RCC_GET_MDF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL))) - -/** @brief Macro to configure the ADF1 clock. - * @param __ADF1_CLKSOURCE__ specifies the ADF1 clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock selected as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock selected as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock selected as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) selected as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock selected as ADF1 clock - * @retval None - */ -#define __HAL_RCC_ADF1_CONFIG(__ADF1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, (uint32_t)(__ADF1_CLKSOURCE__)) - -/** @brief Macro to get the ADF1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_ADF1CLKSOURCE_HCLK HCLK Clock used as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_PLL1 PLL1 P Clock used as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_PLL3 PLL3 Q Clock used as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_PIN External Clock (SAI1_EXTCLK) used as ADF1 clock - * @arg @ref RCC_ADF1CLKSOURCE_MSIK MSI Clock used as ADF1 clock - */ -#define __HAL_RCC_GET_ADF1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL))) - -/** @brief Macro to configure the DAC1 interface clock. - * @param __DAC1_CLKSOURCE__ specifies the DAC1 digital interface clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock - * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock - * @retval None - */ -#define __HAL_RCC_DAC1_CONFIG(__DAC1_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, (uint32_t)(__DAC1_CLKSOURCE__)) - -/** @brief Macro to get the DAC1 clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DAC1CLKSOURCE_LSE LSE clock selected as DAC1 clock - * @arg @ref RCC_DAC1CLKSOURCE_LSI LSI clock selected as DAC1 clock - */ -#define __HAL_RCC_GET_DAC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL))) - -#if defined(LTDC) - -/** @brief Macro to configure the LTDC clock. - * @param __LTDC_CLKSOURCE__ specifies the LTDC clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock - * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock - * @retval None - */ -#define __HAL_RCC_LTDC_CONFIG(__LTDC_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, (__LTDC_CLKSOURCE__)) - -/** @brief Macro to get the LTDC clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_LTDCCLKSOURCE_PLL3 PLL3 divider R clock selected as LTDC kernel clock - * @arg @ref RCC_LTDCCLKSOURCE_PLL2 PLL2 divider R clock selected as LTDC kernel clock - */ -#define __HAL_RCC_GET_LTDC_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL)) - -#endif /* LTDC */ - -#if defined(DSI) - -/** @brief Macro to configure the DSI clock. - * @param __DSI_CLKSOURCE__ specifies the DSI clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock - * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) - * @retval None - */ -#define __HAL_RCC_DSI_CONFIG(__DSI_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, (__DSI_CLKSOURCE__)) - -/** @brief Macro to get the DSI clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_DSICLKSOURCE_DSIPHY DSI-PHY clock selected as DSI clock - * @arg @ref RCC_DSICLKSOURCE_PLL3 PLL3 divider P clock selected as DSI clock (low power case) - */ -#define __HAL_RCC_GET_DSI_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL)) - -#endif /* DSI */ - -#if defined(USB_OTG_HS) - -/** @brief Macro to configure the USB PHY clock. - * @param __USBPHY_CLKSOURCE__ specifies the USB PHY clock source. - * This parameter can be one of the following values: - * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock - * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock - * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock - * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock - * @retval None - */ -#define __HAL_RCC_USBPHY_CONFIG(__USBPHY_CLKSOURCE__) \ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, (__USBPHY_CLKSOURCE__)) - -/** @brief Macro to get the USB PHY clock source. - * @retval The clock source can be one of the following values: - * @arg @ref RCC_USBPHYCLKSOURCE_HSE HSE clock selected as USB PHY clock - * @arg @ref RCC_USBPHYCLKSOURCE_HSE_DIV2 HSE clock div by 2 selected as USB PHY clock - * @arg @ref RCC_USBPHYCLKSOURCE_PLL1 PLL1 P divider clock selected as USB PHY clock - * @arg @ref RCC_USBPHYCLKSOURCE_PLL1_DIV2 PLL1 P divider clock div by 2 selected as USB PHY clock - */ -#define __HAL_RCC_GET_USBPHY_SOURCE() (READ_BIT(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL)) - -#endif /* USB_OTG_HS */ - -#if defined(RCC_CFGR2_PPRE_DPHY) - -/** @brief Macro to configure the DPHY clock. - * @param __PRESCALER__ specifies the DPHY clock source prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock - * @retval None - */ -#define __HAL_RCC_DPHY_CONFIG(__PRESCALER__) \ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, (__PRESCALER__) << 8UL) - -/** @brief Macro to get the DPHY clock prescaler configuration. - * @retval The clock source prescaler can be one of the following values: - * @arg @ref RCC_HCLK_DIV1 HCLK divided by 1 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV2 HCLK divided by 2 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV4 HCLK divided by 4 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV8 HCLK divided by 8 selected as DPHY clock - * @arg @ref RCC_HCLK_DIV16 HCLK divided by 16 selected as DPHY clock - * @retval None - */ -#define __HAL_RCC_GET_DPHY_CONFIG() (READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY) >> 8UL) - -#endif /* defined(RCC_CFGR2_PPRE_DPHY) */ - -#if defined(CRS) - -/** - * @brief Enable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) SET_BIT(CRS->CR, (__INTERRUPT__)) - -/** - * @brief Disable the specified CRS interrupts. - * @param __INTERRUPT__ specifies the CRS interrupt sources to be disabled. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval None - */ -#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) CLEAR_BIT(CRS->CR, (__INTERRUPT__)) - -/** @brief Check whether the CRS interrupt has occurred or not. - * @param __INTERRUPT__ specifies the CRS interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((READ_BIT(CRS->CR, (__INTERRUPT__)) != RESET) ? SET : RESET) - -/** @brief Clear the CRS interrupt pending bits - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be any combination of the following values: - * @arg @ref RCC_CRS_IT_SYNCOK SYNC event OK interrupt - * @arg @ref RCC_CRS_IT_SYNCWARN SYNC warning interrupt - * @arg @ref RCC_CRS_IT_ERR Synchronization or trimming error interrupt - * @arg @ref RCC_CRS_IT_ESYNC Expected SYNC interrupt - * @arg @ref RCC_CRS_IT_TRIMOVF Trimming overflow or underflow interrupt - * @arg @ref RCC_CRS_IT_SYNCERR SYNC error interrupt - * @arg @ref RCC_CRS_IT_SYNCMISS SYNC missed interrupt - */ -#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS)) - -#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) do { \ - if(((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK) != 0U) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC |\ - ((__INTERRUPT__) & ~RCC_CRS_IT_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__INTERRUPT__)); \ - } \ - } while(0) - -/** - * @brief Check whether the specified CRS flag is set or not. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @retval The new state of _FLAG_ (TRUE or FALSE). - */ -#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) (READ_BIT(CRS->ISR, (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the CRS specified FLAG. - * @param __FLAG__ specifies the flag to clear. - * This parameter can be one of the following values: - * @arg @ref RCC_CRS_FLAG_SYNCOK SYNC event OK - * @arg @ref RCC_CRS_FLAG_SYNCWARN SYNC warning - * @arg @ref RCC_CRS_FLAG_ERR Error - * @arg @ref RCC_CRS_FLAG_ESYNC Expected SYNC - * @arg @ref RCC_CRS_FLAG_TRIMOVF Trimming overflow or underflow - * @arg @ref RCC_CRS_FLAG_SYNCERR SYNC error - * @arg @ref RCC_CRS_FLAG_SYNCMISS SYNC missed - * @note RCC_CRS_FLAG_ERR clears RCC_CRS_FLAG_TRIMOVF, RCC_CRS_FLAG_SYNCERR, RCC_CRS_FLAG_SYNCMISS and consequently - * RCC_CRS_FLAG_ERR - * @retval None - */ -#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | \ - RCC_CRS_FLAG_SYNCMISS)) - -#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) do { \ - if(((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK) != 0U) \ - { \ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC | \ - ((__FLAG__) & ~RCC_CRS_FLAG_ERROR_MASK)); \ - } \ - else \ - { \ - WRITE_REG(CRS->ICR, (__FLAG__)); \ - } \ - } while(0) - -/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features - * @{ - */ -/** - * @brief Enable the oscillator clock for frequency error counter. - * @note when the CEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_ENABLE() SET_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Disable the oscillator clock for frequency error counter. - * @retval None - */ -#define __HAL_RCC_CRS_FREQ_ERROR_COUNTER_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_CEN) - -/** - * @brief Enable the automatic hardware adjustment of TRIM bits. - * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_ENABLE() SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Enable or disable the automatic hardware adjustment of TRIM bits. - * @retval None - */ -#define __HAL_RCC_CRS_AUTOMATIC_CALIB_DISABLE() CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency - * of the synchronization source after prescaling. It is then decreased by one in order to - * reach the expected synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval None - */ -#define __HAL_RCC_CRS_RELOADVALUE_CALCULATE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCCEx_Exported_Functions - * @{ - */ - -/** @addtogroup RCCEx_Exported_Functions_Group1 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit); -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit); -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk); -void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks); -void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks); -void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks); -/** - * @} - */ - -/** @addtogroup RCCEx_Exported_Functions_Group2 - * @{ - */ - -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void); -HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init); -HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void); -HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void); -HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void); -HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection); -void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); -void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk); -void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange); -void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange); -void HAL_RCCEx_EnableLSECSS(void); -void HAL_RCCEx_DisableLSECSS(void); -void HAL_RCCEx_EnableLSECSS_IT(void); -void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void); -void HAL_RCCEx_LSECSS_IRQHandler(void); -void HAL_RCCEx_LSECSS_Callback(void); -void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void); -void HAL_RCCEx_MSIPLLUNLCK_Callback(void); -void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource); -void HAL_RCCEx_DisableLSCO(void); -void HAL_RCCEx_EnableMSIPLLMode(void); -void HAL_RCCEx_DisableMSIPLLMode(void); -/** - * @} - */ - -#if defined(CRS) - -/** @addtogroup RCCEx_Exported_Functions_Group3 - * @{ - */ -void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit); -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); -void HAL_RCCEx_CRS_IRQHandler(void); -void HAL_RCCEx_CRS_SyncOkCallback(void); -void HAL_RCCEx_CRS_SyncWarnCallback(void); -void HAL_RCCEx_CRS_ExpectedSyncCallback(void); -void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error); -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_RCC_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h deleted file mode 100644 index bbc186528..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi.h +++ /dev/null @@ -1,1128 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_spi.h - * @author MCD Application Team - * @brief Header file of SPI HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_SPI_H -#define STM32U5xx_HAL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SPI_Exported_Types SPI Exported Types - * @{ - */ - -/** - * @brief SPI Configuration Structure definition - */ -typedef struct -{ - uint32_t Mode; /*!< Specifies the SPI operating mode. - This parameter can be a value of @ref SPI_Mode */ - - uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. - This parameter can be a value of @ref SPI_Direction */ - - uint32_t DataSize; /*!< Specifies the SPI data size. - This parameter can be a value of @ref SPI_Data_Size */ - - uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_Clock_Polarity */ - - uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_Clock_Phase */ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by - hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of - @ref SPI_Slave_Select_Management */ - - uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be - used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_BaudRate_Prescaler - @note The communication clock is derived from the master - clock. The slave clock does not need to be set. */ - - uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_MSB_LSB_Transmission */ - - uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. - This parameter can be a value of @ref SPI_TI_Mode */ - - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. - This parameter can be a value of @ref SPI_CRC_Calculation */ - - uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be an odd number between - Min_Data = 0 and Max_Data = 65535 */ - - uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. - This parameter can be a value of @ref SPI_CRC_length */ - - uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . - This parameter can be a value of @ref SPI_NSSP_Mode - This mode is activated by the SSOM bit in the SPIx_CR2 register - and it takes effect only if the SPI interface is configured - as Motorola SPI master (FRF=0). */ - - uint32_t NSSPolarity; /*!< Specifies which level of SS input/output external signal - (present on SS pin) is considered as active one. - This parameter can be a value of @ref SPI_NSS_Polarity */ - - uint32_t FifoThreshold; /*!< Specifies the FIFO threshold level. - This parameter can be a value of @ref SPI_Fifo_Threshold */ - - uint32_t TxCRCInitializationPattern; /*!< Specifies the transmitter CRC initialization Pattern used for - the CRC calculation. This parameter can be a value of - @ref SPI_CRC_Calculation_Initialization_Pattern */ - - uint32_t RxCRCInitializationPattern; /*!< Specifies the receiver CRC initialization Pattern used for - the CRC calculation. This parameter can be a value of - @ref SPI_CRC_Calculation_Initialization_Pattern */ - - uint32_t MasterSSIdleness; /*!< Specifies an extra delay, expressed in number of SPI clock cycle - periods, inserted additionally between active edge of SS - and first data transaction start in master mode. - This parameter can be a value of @ref SPI_Master_SS_Idleness */ - - uint32_t MasterInterDataIdleness; /*!< Specifies minimum time delay (expressed in SPI clock cycles periods) - inserted between two consecutive data frames in master mode. - This parameter can be a value of - @ref SPI_Master_InterData_Idleness */ - - uint32_t MasterReceiverAutoSusp; /*!< Control continuous SPI transfer in master receiver mode - and automatic management in order to avoid overrun condition. - This parameter can be a value of @ref SPI_Master_RX_AutoSuspend*/ - - uint32_t MasterKeepIOState; /*!< Control of Alternate function GPIOs state - This parameter can be a value of @ref SPI_Master_Keep_IO_State */ - - uint32_t IOSwap; /*!< Invert MISO/MOSI alternate functions - This parameter can be a value of @ref SPI_IO_Swap */ - - uint32_t ReadyMasterManagement; /*!< Specifies if RDY Signal is managed internally or not. - This parameter can be a value of @ref SPI_RDY_Master_Management */ - - uint32_t ReadyPolarity; /*!< Specifies which level of RDY Signal input (present on RDY pin) - is considered as active one. - This parameter can be a value of @ref SPI_RDY_Polarity */ -} SPI_InitTypeDef; - -/** - * @brief HAL SPI State structure definition - */ -typedef enum -{ - HAL_SPI_STATE_RESET = 0x00UL, /*!< Peripheral not Initialized */ - HAL_SPI_STATE_READY = 0x01UL, /*!< Peripheral Initialized and ready for use */ - HAL_SPI_STATE_BUSY = 0x02UL, /*!< an internal process is ongoing */ - HAL_SPI_STATE_BUSY_TX = 0x03UL, /*!< Data Transmission process is ongoing */ - HAL_SPI_STATE_BUSY_RX = 0x04UL, /*!< Data Reception process is ongoing */ - HAL_SPI_STATE_BUSY_TX_RX = 0x05UL, /*!< Data Transmission and Reception process is ongoing */ - HAL_SPI_STATE_ERROR = 0x06UL, /*!< SPI error state */ - HAL_SPI_STATE_ABORT = 0x07UL /*!< SPI abort is ongoing */ -} HAL_SPI_StateTypeDef; - - -/** - * @brief SPI handle Structure definition - */ -typedef struct __SPI_HandleTypeDef -{ - SPI_TypeDef *Instance; /*!< SPI registers base address */ - - SPI_InitTypeDef Init; /*!< SPI communication parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< SPI Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< SPI Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ - - uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ - - void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ - - void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ - - DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ - - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ - - __IO uint32_t ErrorCode; /*!< SPI Error code */ - - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ - void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ - void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ - void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ - void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ - void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ - void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ - void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ - void (* SuspendCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Suspend callback */ - void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ - void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ - -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} SPI_HandleTypeDef; - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) -/** - * @brief HAL SPI Callback ID enumeration definition - */ -typedef enum -{ - HAL_SPI_TX_COMPLETE_CB_ID = 0x00UL, /*!< SPI Tx Completed callback ID */ - HAL_SPI_RX_COMPLETE_CB_ID = 0x01UL, /*!< SPI Rx Completed callback ID */ - HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02UL, /*!< SPI TxRx Completed callback ID */ - HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03UL, /*!< SPI Tx Half Completed callback ID */ - HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04UL, /*!< SPI Rx Half Completed callback ID */ - HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05UL, /*!< SPI TxRx Half Completed callback ID */ - HAL_SPI_ERROR_CB_ID = 0x06UL, /*!< SPI Error callback ID */ - HAL_SPI_ABORT_CB_ID = 0x07UL, /*!< SPI Abort callback ID */ - HAL_SPI_SUSPEND_CB_ID = 0x08UL, /*!< SPI Suspend callback ID */ - HAL_SPI_MSPINIT_CB_ID = 0x09UL, /*!< SPI Msp Init callback ID */ - HAL_SPI_MSPDEINIT_CB_ID = 0x0AUL /*!< SPI Msp DeInit callback ID */ - -} HAL_SPI_CallbackIDTypeDef; - -/** - * @brief HAL SPI Callback pointer definition - */ -typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ - -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup SPI_Exported_Constants SPI Exported Constants - * @{ - */ - -/** @defgroup SPI_FIFO_Type SPI FIFO Type - * @{ - */ -#define SPI_LOWEND_FIFO_SIZE 8UL -#define SPI_HIGHEND_FIFO_SIZE 16UL -/** - * @} - */ - -/** @defgroup SPI_Error_Code SPI Error Codes - * @{ - */ -#define HAL_SPI_ERROR_NONE (0x00000000UL) /*!< No error */ -#define HAL_SPI_ERROR_MODF (0x00000001UL) /*!< MODF error */ -#define HAL_SPI_ERROR_CRC (0x00000002UL) /*!< CRC error */ -#define HAL_SPI_ERROR_OVR (0x00000004UL) /*!< OVR error */ -#define HAL_SPI_ERROR_FRE (0x00000008UL) /*!< FRE error */ -#define HAL_SPI_ERROR_DMA (0x00000010UL) /*!< DMA transfer error */ -#define HAL_SPI_ERROR_FLAG (0x00000020UL) /*!< Error on RXP/TXP/DXP/FTLVL/FRLVL Flag */ -#define HAL_SPI_ERROR_ABORT (0x00000040UL) /*!< Error during SPI Abort procedure */ -#define HAL_SPI_ERROR_UDR (0x00000080UL) /*!< Underrun error */ -#define HAL_SPI_ERROR_TIMEOUT (0x00000100UL) /*!< Timeout error */ -#define HAL_SPI_ERROR_UNKNOW (0x00000200UL) /*!< Unknown error */ -#define HAL_SPI_ERROR_NOT_SUPPORTED (0x00000400UL) /*!< Requested operation not supported */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) -#define HAL_SPI_ERROR_INVALID_CALLBACK (0x00001000UL) /*!< Invalid Callback error */ -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SPI_Mode SPI Mode - * @{ - */ -#define SPI_MODE_SLAVE (0x00000000UL) -#define SPI_MODE_MASTER SPI_CFG2_MASTER -/** - * @} - */ - -/** @defgroup SPI_Direction SPI Direction Mode - * @{ - */ -#define SPI_DIRECTION_2LINES (0x00000000UL) -#define SPI_DIRECTION_2LINES_TXONLY SPI_CFG2_COMM_0 -#define SPI_DIRECTION_2LINES_RXONLY SPI_CFG2_COMM_1 -#define SPI_DIRECTION_1LINE SPI_CFG2_COMM -/** - * @} - */ - -/** @defgroup SPI_Data_Size SPI Data Size - * @{ - */ -#define SPI_DATASIZE_4BIT (0x00000003UL) -#define SPI_DATASIZE_5BIT (0x00000004UL) -#define SPI_DATASIZE_6BIT (0x00000005UL) -#define SPI_DATASIZE_7BIT (0x00000006UL) -#define SPI_DATASIZE_8BIT (0x00000007UL) -#define SPI_DATASIZE_9BIT (0x00000008UL) -#define SPI_DATASIZE_10BIT (0x00000009UL) -#define SPI_DATASIZE_11BIT (0x0000000AUL) -#define SPI_DATASIZE_12BIT (0x0000000BUL) -#define SPI_DATASIZE_13BIT (0x0000000CUL) -#define SPI_DATASIZE_14BIT (0x0000000DUL) -#define SPI_DATASIZE_15BIT (0x0000000EUL) -#define SPI_DATASIZE_16BIT (0x0000000FUL) -#define SPI_DATASIZE_17BIT (0x00000010UL) -#define SPI_DATASIZE_18BIT (0x00000011UL) -#define SPI_DATASIZE_19BIT (0x00000012UL) -#define SPI_DATASIZE_20BIT (0x00000013UL) -#define SPI_DATASIZE_21BIT (0x00000014UL) -#define SPI_DATASIZE_22BIT (0x00000015UL) -#define SPI_DATASIZE_23BIT (0x00000016UL) -#define SPI_DATASIZE_24BIT (0x00000017UL) -#define SPI_DATASIZE_25BIT (0x00000018UL) -#define SPI_DATASIZE_26BIT (0x00000019UL) -#define SPI_DATASIZE_27BIT (0x0000001AUL) -#define SPI_DATASIZE_28BIT (0x0000001BUL) -#define SPI_DATASIZE_29BIT (0x0000001CUL) -#define SPI_DATASIZE_30BIT (0x0000001DUL) -#define SPI_DATASIZE_31BIT (0x0000001EUL) -#define SPI_DATASIZE_32BIT (0x0000001FUL) -/** - * @} - */ - -/** @defgroup SPI_Clock_Polarity SPI Clock Polarity - * @{ - */ -#define SPI_POLARITY_LOW (0x00000000UL) -#define SPI_POLARITY_HIGH SPI_CFG2_CPOL -/** - * @} - */ - -/** @defgroup SPI_Clock_Phase SPI Clock Phase - * @{ - */ -#define SPI_PHASE_1EDGE (0x00000000UL) -#define SPI_PHASE_2EDGE SPI_CFG2_CPHA -/** - * @} - */ - -/** @defgroup SPI_Slave_Select_Management SPI Slave Select Management - * @{ - */ -#define SPI_NSS_SOFT SPI_CFG2_SSM -#define SPI_NSS_HARD_INPUT (0x00000000UL) -#define SPI_NSS_HARD_OUTPUT SPI_CFG2_SSOE -/** - * @} - */ - -/** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode - * @{ - */ -#define SPI_NSS_PULSE_DISABLE (0x00000000UL) -#define SPI_NSS_PULSE_ENABLE SPI_CFG2_SSOM -/** - * @} - */ - -/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler - * @{ - */ -#define SPI_BAUDRATEPRESCALER_BYPASS (0x80000000UL) -#define SPI_BAUDRATEPRESCALER_2 (0x00000000UL) -#define SPI_BAUDRATEPRESCALER_4 (0x10000000UL) -#define SPI_BAUDRATEPRESCALER_8 (0x20000000UL) -#define SPI_BAUDRATEPRESCALER_16 (0x30000000UL) -#define SPI_BAUDRATEPRESCALER_32 (0x40000000UL) -#define SPI_BAUDRATEPRESCALER_64 (0x50000000UL) -#define SPI_BAUDRATEPRESCALER_128 (0x60000000UL) -#define SPI_BAUDRATEPRESCALER_256 (0x70000000UL) -/** - * @} - */ - -/** @defgroup SPI_MSB_LSB_Transmission SPI MSB LSB Transmission - * @{ - */ -#define SPI_FIRSTBIT_MSB (0x00000000UL) -#define SPI_FIRSTBIT_LSB SPI_CFG2_LSBFRST -/** - * @} - */ - -/** @defgroup SPI_TI_Mode SPI TI Mode - * @{ - */ -#define SPI_TIMODE_DISABLE (0x00000000UL) -#define SPI_TIMODE_ENABLE SPI_CFG2_SP_0 -/** - * @} - */ - -/** @defgroup SPI_CRC_Calculation SPI CRC Calculation - * @{ - */ -#define SPI_CRCCALCULATION_DISABLE (0x00000000UL) -#define SPI_CRCCALCULATION_ENABLE SPI_CFG1_CRCEN -/** - * @} - */ - -/** @defgroup SPI_CRC_length SPI CRC Length - * @{ - */ -#define SPI_CRC_LENGTH_DATASIZE (0x00000000UL) -#define SPI_CRC_LENGTH_4BIT (0x00030000UL) -#define SPI_CRC_LENGTH_5BIT (0x00040000UL) -#define SPI_CRC_LENGTH_6BIT (0x00050000UL) -#define SPI_CRC_LENGTH_7BIT (0x00060000UL) -#define SPI_CRC_LENGTH_8BIT (0x00070000UL) -#define SPI_CRC_LENGTH_9BIT (0x00080000UL) -#define SPI_CRC_LENGTH_10BIT (0x00090000UL) -#define SPI_CRC_LENGTH_11BIT (0x000A0000UL) -#define SPI_CRC_LENGTH_12BIT (0x000B0000UL) -#define SPI_CRC_LENGTH_13BIT (0x000C0000UL) -#define SPI_CRC_LENGTH_14BIT (0x000D0000UL) -#define SPI_CRC_LENGTH_15BIT (0x000E0000UL) -#define SPI_CRC_LENGTH_16BIT (0x000F0000UL) -#define SPI_CRC_LENGTH_17BIT (0x00100000UL) -#define SPI_CRC_LENGTH_18BIT (0x00110000UL) -#define SPI_CRC_LENGTH_19BIT (0x00120000UL) -#define SPI_CRC_LENGTH_20BIT (0x00130000UL) -#define SPI_CRC_LENGTH_21BIT (0x00140000UL) -#define SPI_CRC_LENGTH_22BIT (0x00150000UL) -#define SPI_CRC_LENGTH_23BIT (0x00160000UL) -#define SPI_CRC_LENGTH_24BIT (0x00170000UL) -#define SPI_CRC_LENGTH_25BIT (0x00180000UL) -#define SPI_CRC_LENGTH_26BIT (0x00190000UL) -#define SPI_CRC_LENGTH_27BIT (0x001A0000UL) -#define SPI_CRC_LENGTH_28BIT (0x001B0000UL) -#define SPI_CRC_LENGTH_29BIT (0x001C0000UL) -#define SPI_CRC_LENGTH_30BIT (0x001D0000UL) -#define SPI_CRC_LENGTH_31BIT (0x001E0000UL) -#define SPI_CRC_LENGTH_32BIT (0x001F0000UL) -/** - * @} - */ - -/** @defgroup SPI_Fifo_Threshold SPI Fifo Threshold - * @{ - */ -#define SPI_FIFO_THRESHOLD_01DATA (0x00000000UL) -#define SPI_FIFO_THRESHOLD_02DATA (0x00000020UL) -#define SPI_FIFO_THRESHOLD_03DATA (0x00000040UL) -#define SPI_FIFO_THRESHOLD_04DATA (0x00000060UL) -#define SPI_FIFO_THRESHOLD_05DATA (0x00000080UL) -#define SPI_FIFO_THRESHOLD_06DATA (0x000000A0UL) -#define SPI_FIFO_THRESHOLD_07DATA (0x000000C0UL) -#define SPI_FIFO_THRESHOLD_08DATA (0x000000E0UL) -#define SPI_FIFO_THRESHOLD_09DATA (0x00000100UL) -#define SPI_FIFO_THRESHOLD_10DATA (0x00000120UL) -#define SPI_FIFO_THRESHOLD_11DATA (0x00000140UL) -#define SPI_FIFO_THRESHOLD_12DATA (0x00000160UL) -#define SPI_FIFO_THRESHOLD_13DATA (0x00000180UL) -#define SPI_FIFO_THRESHOLD_14DATA (0x000001A0UL) -#define SPI_FIFO_THRESHOLD_15DATA (0x000001C0UL) -#define SPI_FIFO_THRESHOLD_16DATA (0x000001E0UL) -/** - * @} - */ - -/** @defgroup SPI_CRC_Calculation_Initialization_Pattern SPI CRC Calculation Initialization Pattern - * @{ - */ -#define SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN (0x00000000UL) -#define SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN (0x00000001UL) -/** - * @} - */ - -/** @defgroup SPI_NSS_Polarity SPI NSS Polarity - * @{ - */ -#define SPI_NSS_POLARITY_LOW (0x00000000UL) -#define SPI_NSS_POLARITY_HIGH SPI_CFG2_SSIOP -/** - * @} - */ - -/** @defgroup SPI_Master_Keep_IO_State Keep IO State - * @{ - */ -#define SPI_MASTER_KEEP_IO_STATE_DISABLE (0x00000000UL) -#define SPI_MASTER_KEEP_IO_STATE_ENABLE SPI_CFG2_AFCNTR -/** - * @} - */ - -/** @defgroup SPI_IO_Swap Control SPI IO Swap - * @{ - */ -#define SPI_IO_SWAP_DISABLE (0x00000000UL) -#define SPI_IO_SWAP_ENABLE SPI_CFG2_IOSWP -/** - * @} - */ - -/** @defgroup SPI_Master_SS_Idleness SPI Master SS Idleness - * @{ - */ -#define SPI_MASTER_SS_IDLENESS_00CYCLE (0x00000000UL) -#define SPI_MASTER_SS_IDLENESS_01CYCLE (0x00000001UL) -#define SPI_MASTER_SS_IDLENESS_02CYCLE (0x00000002UL) -#define SPI_MASTER_SS_IDLENESS_03CYCLE (0x00000003UL) -#define SPI_MASTER_SS_IDLENESS_04CYCLE (0x00000004UL) -#define SPI_MASTER_SS_IDLENESS_05CYCLE (0x00000005UL) -#define SPI_MASTER_SS_IDLENESS_06CYCLE (0x00000006UL) -#define SPI_MASTER_SS_IDLENESS_07CYCLE (0x00000007UL) -#define SPI_MASTER_SS_IDLENESS_08CYCLE (0x00000008UL) -#define SPI_MASTER_SS_IDLENESS_09CYCLE (0x00000009UL) -#define SPI_MASTER_SS_IDLENESS_10CYCLE (0x0000000AUL) -#define SPI_MASTER_SS_IDLENESS_11CYCLE (0x0000000BUL) -#define SPI_MASTER_SS_IDLENESS_12CYCLE (0x0000000CUL) -#define SPI_MASTER_SS_IDLENESS_13CYCLE (0x0000000DUL) -#define SPI_MASTER_SS_IDLENESS_14CYCLE (0x0000000EUL) -#define SPI_MASTER_SS_IDLENESS_15CYCLE (0x0000000FUL) -/** - * @} - */ - -/** @defgroup SPI_Master_InterData_Idleness SPI Master Inter-Data Idleness - * @{ - */ -#define SPI_MASTER_INTERDATA_IDLENESS_00CYCLE (0x00000000UL) -#define SPI_MASTER_INTERDATA_IDLENESS_01CYCLE (0x00000010UL) -#define SPI_MASTER_INTERDATA_IDLENESS_02CYCLE (0x00000020UL) -#define SPI_MASTER_INTERDATA_IDLENESS_03CYCLE (0x00000030UL) -#define SPI_MASTER_INTERDATA_IDLENESS_04CYCLE (0x00000040UL) -#define SPI_MASTER_INTERDATA_IDLENESS_05CYCLE (0x00000050UL) -#define SPI_MASTER_INTERDATA_IDLENESS_06CYCLE (0x00000060UL) -#define SPI_MASTER_INTERDATA_IDLENESS_07CYCLE (0x00000070UL) -#define SPI_MASTER_INTERDATA_IDLENESS_08CYCLE (0x00000080UL) -#define SPI_MASTER_INTERDATA_IDLENESS_09CYCLE (0x00000090UL) -#define SPI_MASTER_INTERDATA_IDLENESS_10CYCLE (0x000000A0UL) -#define SPI_MASTER_INTERDATA_IDLENESS_11CYCLE (0x000000B0UL) -#define SPI_MASTER_INTERDATA_IDLENESS_12CYCLE (0x000000C0UL) -#define SPI_MASTER_INTERDATA_IDLENESS_13CYCLE (0x000000D0UL) -#define SPI_MASTER_INTERDATA_IDLENESS_14CYCLE (0x000000E0UL) -#define SPI_MASTER_INTERDATA_IDLENESS_15CYCLE (0x000000F0UL) -/** - * @} - */ - -/** @defgroup SPI_Master_RX_AutoSuspend SPI Master Receiver AutoSuspend - * @{ - */ -#define SPI_MASTER_RX_AUTOSUSP_DISABLE (0x00000000UL) -#define SPI_MASTER_RX_AUTOSUSP_ENABLE SPI_CR1_MASRX -/** - * @} - */ - -/** @defgroup SPI_Underrun_Behaviour SPI Underrun Behavior - * @{ - */ -#define SPI_UNDERRUN_BEHAV_REGISTER_PATTERN (0x00000000UL) -#define SPI_UNDERRUN_BEHAV_LAST_RECEIVED SPI_CFG1_UDRCFG -/** - * @} - */ - -/** @defgroup SPI_RDY_Master_Management SPI RDY Signal Input Master Management - * @{ - */ -#define SPI_RDY_MASTER_MANAGEMENT_INTERNALLY (0x00000000UL) -#define SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY SPI_CFG2_RDIMM -/** - * @} - */ - -/** @defgroup SPI_RDY_Polarity SPI RDY Signal Input/Output Polarity - * @{ - */ -#define SPI_RDY_POLARITY_HIGH (0x00000000UL) -#define SPI_RDY_POLARITY_LOW SPI_CFG2_RDIOP -/** - * @} - */ - -/** @defgroup SPI_Interrupt_definition SPI Interrupt Definition - * @{ - */ -#define SPI_IT_RXP SPI_IER_RXPIE -#define SPI_IT_TXP SPI_IER_TXPIE -#define SPI_IT_DXP SPI_IER_DXPIE -#define SPI_IT_EOT SPI_IER_EOTIE -#define SPI_IT_TXTF SPI_IER_TXTFIE -#define SPI_IT_UDR SPI_IER_UDRIE -#define SPI_IT_OVR SPI_IER_OVRIE -#define SPI_IT_CRCERR SPI_IER_CRCEIE -#define SPI_IT_FRE SPI_IER_TIFREIE -#define SPI_IT_MODF SPI_IER_MODFIE -#define SPI_IT_ERR (SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF | SPI_IT_CRCERR) -/** - * @} - */ - -/** @defgroup SPI_Flags_definition SPI Flags Definition - * @{ - */ -#define SPI_FLAG_RXP SPI_SR_RXP /* SPI status flag : Rx-Packet available flag */ -#define SPI_FLAG_TXP SPI_SR_TXP /* SPI status flag : Tx-Packet space available flag */ -#define SPI_FLAG_DXP SPI_SR_DXP /* SPI status flag : Duplex Packet flag */ -#define SPI_FLAG_EOT SPI_SR_EOT /* SPI status flag : End of transfer flag */ -#define SPI_FLAG_TXTF SPI_SR_TXTF /* SPI status flag : Transmission Transfer Filled flag */ -#define SPI_FLAG_UDR SPI_SR_UDR /* SPI Error flag : Underrun flag */ -#define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag : Overrun flag */ -#define SPI_FLAG_CRCERR SPI_SR_CRCE /* SPI Error flag : CRC error flag */ -#define SPI_FLAG_FRE SPI_SR_TIFRE /* SPI Error flag : TI mode frame format error flag */ -#define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag : Mode fault flag */ -#define SPI_FLAG_SUSP SPI_SR_SUSP /* SPI status flag : Transfer suspend complete flag */ -#define SPI_FLAG_TXC SPI_SR_TXC /* SPI status flag : TxFIFO transmission complete flag */ -#define SPI_FLAG_FRLVL SPI_SR_RXPLVL /* SPI status flag : Fifo reception level flag */ -#define SPI_FLAG_RXWNE SPI_SR_RXWNE /* SPI status flag : RxFIFO word not empty flag */ -/** - * @} - */ - -/** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level - * @{ - */ -#define SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packets available in the RxFIFO */ -#define SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) -#define SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) -#define SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup SPI_Exported_Macros SPI Exported Macros - * @{ - */ - -/** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @retval None - */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - -/** @brief Enable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg SPI_IT_RXP : Rx-Packet available interrupt - * @arg SPI_IT_TXP : Tx-Packet space available interrupt - * @arg SPI_IT_DXP : Duplex Packet interrupt - * @arg SPI_IT_EOT : End of transfer interrupt - * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt - * @arg SPI_IT_UDR : Underrun interrupt - * @arg SPI_IT_OVR : Overrun interrupt - * @arg SPI_IT_CRCERR : CRC error interrupt - * @arg SPI_IT_FRE : TI mode frame format error interrupt - * @arg SPI_IT_MODF : Mode fault interrupt - * @arg SPI_IT_ERR : Error interrupt - * @retval None - */ -#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) - -/** @brief Disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. - * This parameter can be one of the following values: - * @arg SPI_IT_RXP : Rx-Packet available interrupt - * @arg SPI_IT_TXP : Tx-Packet space available interrupt - * @arg SPI_IT_DXP : Duplex Packet interrupt - * @arg SPI_IT_EOT : End of transfer interrupt - * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt - * @arg SPI_IT_UDR : Underrun interrupt - * @arg SPI_IT_OVR : Overrun interrupt - * @arg SPI_IT_CRCERR : CRC error interrupt - * @arg SPI_IT_FRE : TI mode frame format error interrupt - * @arg SPI_IT_MODF : Mode fault interrupt - * @arg SPI_IT_ERR : Error interrupt - * @retval None - */ -#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) - -/** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. - * This parameter can be one of the following values: - * @arg SPI_IT_RXP : Rx-Packet available interrupt - * @arg SPI_IT_TXP : Tx-Packet space available interrupt - * @arg SPI_IT_DXP : Duplex Packet interrupt - * @arg SPI_IT_EOT : End of transfer interrupt - * @arg SPI_IT_TXTF : Transmission Transfer Filled interrupt - * @arg SPI_IT_UDR : Underrun interrupt - * @arg SPI_IT_OVR : Overrun interrupt - * @arg SPI_IT_CRCERR : CRC error interrupt - * @arg SPI_IT_FRE : TI mode frame format error interrupt - * @arg SPI_IT_MODF : Mode fault interrupt - * @arg SPI_IT_ERR : Error interrupt - * @retval The new state of __IT__ (TRUE or FALSE). - */ -#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & \ - (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, 3, 4, 5 or 6 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. - * This parameter can be one of the following values: - * @arg SPI_FLAG_RXP : Rx-Packet available flag - * @arg SPI_FLAG_TXP : Tx-Packet space available flag - * @arg SPI_FLAG_DXP : Duplex Packet flag - * @arg SPI_FLAG_EOT : End of transfer flag - * @arg SPI_FLAG_TXTF : Transmission Transfer Filled flag - * @arg SPI_FLAG_UDR : Underrun flag - * @arg SPI_FLAG_OVR : Overrun flag - * @arg SPI_FLAG_CRCERR : CRC error flag - * @arg SPI_FLAG_FRE : TI mode frame format error flag - * @arg SPI_FLAG_MODF : Mode fault flag - * @arg SPI_FLAG_SUSP : Transfer suspend complete flag - * @arg SPI_FLAG_TXC : TxFIFO transmission complete flag - * @arg SPI_FLAG_FRLVL : Fifo reception level flag - * @arg SPI_FLAG_RXWNE : RxFIFO word not empty flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) - -/** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_CRCEC) - -/** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , (uint32_t)(SPI_IFCR_MODFC)); - -/** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_OVRC) - -/** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TIFREC) - -/** @brief Clear the SPI UDR pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_UDRFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_UDRC) - -/** @brief Clear the SPI EOT pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_EOTFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_EOTC) - -/** @brief Clear the SPI UDR pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_TXTFFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_TXTFC) - -/** @brief Clear the SPI SUSP pending flag. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_CLEAR_SUSPFLAG(__HANDLE__) SET_BIT((__HANDLE__)->Instance->IFCR , SPI_IFCR_SUSPC) - -/** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) - -/** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. - * @retval None - */ -#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1 , SPI_CR1_SPE) -/** - * @} - */ - - -/* Include SPI HAL Extension module */ -#include "stm32u5xx_hal_spi_ex.h" - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPI_Exported_Functions - * @{ - */ - -/** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ -/* Initialization/de-initialization functions ********************************/ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); -void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); -void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, - pSPI_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup SPI_Exported_Functions_Group2 IO operation functions - * @{ - */ -/* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size); - -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size); - - -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); - -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); - -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); -void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi); -/** - * @} - */ - -/** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @{ - */ - -/* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SPI_Private_Macros SPI Private Macros - * @{ - */ - -/** @brief Set the SPI transmit-only mode in 1Line configuration. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) - -/** @brief Set the SPI receive-only mode in 1Line configuration. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_HDDIR) - -/** @brief Set the SPI transmit-only mode in 2Lines configuration. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_2LINES_TX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_0) - -/** @brief Set the SPI receive-only mode in 2Lines configuration. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_2LINES_RX(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, SPI_CFG2_COMM_1) - -/** @brief Set the SPI Transmit-Receive mode in 2Lines configuration. - * @param __HANDLE__: specifies the SPI Handle. - * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @retval None - */ -#define SPI_2LINES(__HANDLE__) MODIFY_REG((__HANDLE__)->Instance->CFG2, SPI_CFG2_COMM, 0x00000000UL) - -#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \ - ((MODE) == SPI_MODE_MASTER)) - -#define IS_SPI_DIRECTION(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) - -#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES) - -#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_TXONLY)) - -#define IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(MODE) (((MODE) == SPI_DIRECTION_2LINES)|| \ - ((MODE) == SPI_DIRECTION_1LINE) || \ - ((MODE) == SPI_DIRECTION_2LINES_RXONLY)) - -#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_32BIT) || \ - ((DATASIZE) == SPI_DATASIZE_31BIT) || \ - ((DATASIZE) == SPI_DATASIZE_30BIT) || \ - ((DATASIZE) == SPI_DATASIZE_29BIT) || \ - ((DATASIZE) == SPI_DATASIZE_28BIT) || \ - ((DATASIZE) == SPI_DATASIZE_27BIT) || \ - ((DATASIZE) == SPI_DATASIZE_26BIT) || \ - ((DATASIZE) == SPI_DATASIZE_25BIT) || \ - ((DATASIZE) == SPI_DATASIZE_24BIT) || \ - ((DATASIZE) == SPI_DATASIZE_23BIT) || \ - ((DATASIZE) == SPI_DATASIZE_22BIT) || \ - ((DATASIZE) == SPI_DATASIZE_21BIT) || \ - ((DATASIZE) == SPI_DATASIZE_20BIT) || \ - ((DATASIZE) == SPI_DATASIZE_22BIT) || \ - ((DATASIZE) == SPI_DATASIZE_19BIT) || \ - ((DATASIZE) == SPI_DATASIZE_18BIT) || \ - ((DATASIZE) == SPI_DATASIZE_17BIT) || \ - ((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_15BIT) || \ - ((DATASIZE) == SPI_DATASIZE_14BIT) || \ - ((DATASIZE) == SPI_DATASIZE_13BIT) || \ - ((DATASIZE) == SPI_DATASIZE_12BIT) || \ - ((DATASIZE) == SPI_DATASIZE_11BIT) || \ - ((DATASIZE) == SPI_DATASIZE_10BIT) || \ - ((DATASIZE) == SPI_DATASIZE_9BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT) || \ - ((DATASIZE) == SPI_DATASIZE_7BIT) || \ - ((DATASIZE) == SPI_DATASIZE_6BIT) || \ - ((DATASIZE) == SPI_DATASIZE_5BIT) || \ - ((DATASIZE) == SPI_DATASIZE_4BIT)) - -/** - * @brief DataSize for limited instance - */ -#define IS_SPI_LIMITED_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \ - ((DATASIZE) == SPI_DATASIZE_8BIT)) - -#define IS_SPI_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_09DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_10DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_11DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_12DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_13DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_14DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_15DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_16DATA)) - -/** - * @brief FifoThreshold for limited instance - */ -#define IS_SPI_LIMITED_FIFOTHRESHOLD(THRESHOLD) (((THRESHOLD) == SPI_FIFO_THRESHOLD_01DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_02DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_03DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_04DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_05DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_06DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_07DATA) || \ - ((THRESHOLD) == SPI_FIFO_THRESHOLD_08DATA)) - -#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \ - ((CPOL) == SPI_POLARITY_HIGH)) - -#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \ - ((CPHA) == SPI_PHASE_2EDGE)) - -#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \ - ((NSS) == SPI_NSS_HARD_INPUT) || \ - ((NSS) == SPI_NSS_HARD_OUTPUT)) - -#define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \ - ((NSSP) == SPI_NSS_PULSE_DISABLE)) - -#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_BYPASS) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \ - ((PRESCALER) == SPI_BAUDRATEPRESCALER_256)) - -#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \ - ((BIT) == SPI_FIRSTBIT_LSB)) - -#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \ - ((MODE) == SPI_TIMODE_ENABLE)) - -#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \ - ((CALCULATION) == SPI_CRCCALCULATION_ENABLE)) - -#define IS_SPI_CRC_INITIALIZATION_PATTERN(PATTERN) (((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ZERO_PATTERN) || \ - ((PATTERN) == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN)) - -#define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) || \ - ((LENGTH) == SPI_CRC_LENGTH_32BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_31BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_30BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_29BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_28BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_27BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_26BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_25BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_24BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_23BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_22BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_21BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_20BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_19BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_18BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_17BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_16BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_15BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_14BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_13BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_12BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_11BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_10BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_9BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_7BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_6BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_5BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_4BIT)) - -/** - * @brief CRC Length for limited instance - */ -#define IS_SPI_LIMITED_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_8BIT) || \ - ((LENGTH) == SPI_CRC_LENGTH_16BIT)) - - -#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) > 0x0UL) - - - -#define IS_SPI_UNDERRUN_BEHAVIOUR(MODE) (((MODE) == SPI_UNDERRUN_BEHAV_REGISTER_PATTERN) || \ - ((MODE) == SPI_UNDERRUN_BEHAV_LAST_RECEIVED)) - -#define IS_SPI_RDY_MASTER_MANAGEMENT(MANAGEMENT) (((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_INTERNALLY) || \ - ((MANAGEMENT) == SPI_RDY_MASTER_MANAGEMENT_EXTERNALLY)) - -#define IS_SPI_RDY_POLARITY(POLARITY) (((POLARITY) == SPI_RDY_POLARITY_HIGH) || \ - ((POLARITY) == SPI_RDY_POLARITY_LOW)) - -#define IS_SPI_MASTER_RX_AUTOSUSP(MODE) (((MODE) == SPI_MASTER_RX_AUTOSUSP_DISABLE) || \ - ((MODE) == SPI_MASTER_RX_AUTOSUSP_ENABLE)) -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_SPI_H */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h deleted file mode 100644 index 707bb0749..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_spi_ex.h +++ /dev/null @@ -1,254 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_spi_ex.h - * @author MCD Application Team - * @brief Header file of SPI HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_SPI_EX_H -#define STM32U5xx_HAL_SPI_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup SPIEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup SPIEx_Exported_Types SPIEx Exported Types - * @{ - */ - -/** - * @brief SPI Autonomous Mode Configuration structure definition - */ -typedef struct -{ - uint32_t TriggerState; /*!< Specifies the trigger state. This parameter can be a value - of @ref FunctionalState */ - - uint32_t TriggerSelection; /*!< Specifies the autonomous mode trigger signal selection. This parameter - can be a value of @ref SPI_AutonomousMode_TriggerSelection */ - - uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity sensitivity. This parameter - can be a value of @ref SPI_AutonomousMode_TriggerPolarity */ - -} SPI_AutonomousModeConfTypeDef; - - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SPIEx_Exported_Constants SPIEx Exported Constants - * @{ - */ - -/** @defgroup FunctionalState SPI Autonomous Mode State - * @{ - */ -#define SPI_AUTO_MODE_DISABLE (0x00000000UL) -#define SPI_AUTO_MODE_ENABLE SPI_AUTOCR_TRIGEN -/** - * @} - */ - -/** @defgroup SPI_AutonomousMode_TriggerSelection Autonomous Mode Trigger Selection - * @{ - */ -#define SPI_TRIG_GRP1 (0x10000000U) /* Trigger Group for SPI1 and SPI2 */ -#if defined(SPI3) -#define SPI_TRIG_GRP2 (0x20000000U) /* Trigger Group for SPI3 */ -#endif /* GRP2_AVAILABILITY */ - -/* HW Trigger signal is GPDMA_CH0_TRG */ -#define SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x00000000U)) -/* HW Trigger signal is GPDMA_CH1_TRG */ -#define SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is GPDMA_CH2_TRG */ -#define SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is GPDMA_CH3_TRG */ -#define SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP1_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI9_TRG */ -#define SPI_GRP1_EXTI9_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM2_CH1_TRG */ -#define SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP1_COMP1_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP2_TRG */ -#define SPI_GRP1_COMP2_TRG (uint32_t)(SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP1_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP1_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) - -#if defined(SPI3) -/* HW Trigger signal is LPDMA_CH0_TRG */ -#define SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x00000000U)) -/* HW Trigger signal is LPDMA_CH1_TRG */ -#define SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPDMA_CH2_TRG */ -#define SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPDMA_CH3_TRG */ -#define SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI4_TRG */ -#define SPI_GRP2_EXTI4_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is EXTI8_TRG */ -#define SPI_GRP2_EXTI8_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM1_CH1_TRG */ -#define SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is LPTIM3_CH1_TRG */ -#define SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP1_TRG */ -#define SPI_GRP2_COMP1_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is COMP2_TRG */ -#define SPI_GRP2_COMP2_TRG (uint32_t)(SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_ALRA_TRG */ -#define SPI_GRP2_RTC_ALRA_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) -/* HW Trigger signal is RTC_WUT_TRG */ -#define SPI_GRP2_RTC_WUT_TRG (uint32_t)(SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) -#endif /* GRP2_AVAILABILITY */ -/** - * @} - */ - -/** @defgroup SPI_AutonomousMode_TriggerPolarity Autonomous Mode Trigger Polarity - * @{ - */ -#define SPI_TRIG_POLARITY_RISING (0x00000000UL) /* SPI HW Trigger signal on rising edge */ -#define SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /* SPI HW Trigger signal on falling edge */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup SPIEx_Exported_Macros SPIEx Extended Exported Macros - * @{ - */ - -#define IS_SPI_AUTO_MODE(__MODE__) (((__MODE__) == SPI_AUTO_MODE_DISABLE) || \ - ((__MODE__) == SPI_AUTO_MODE_ENABLE)) - -#if defined(SPI_TRIG_GRP2) -#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) (IS_SPI_GRP1_INSTANCE(__INSTANCE__) || \ - IS_SPI_GRP2_INSTANCE(__INSTANCE__)) -#else -#define IS_SPI_AUTONOMOUS_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) -#endif /* SPI_TRIG_GRP2 */ - -#if defined(SPI_TRIG_GRP2) -#define IS_SPI_TRIG_SOURCE(__INSTANCE__, __SOURCE__) ((IS_SPI_GRP2_INSTANCE(__INSTANCE__)) ? \ - IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) : \ - IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__)) -#endif /* SPI_TRIG_GRP2 */ - -#define IS_SPI_GRP1_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP1_GPDMA_CH0_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_GPDMA_CH1_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_GPDMA_CH2_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_GPDMA_CH3_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_EXTI4_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_EXTI9_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_LPTIM1_CH1_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_LPTIM2_CH1_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_COMP1_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_COMP2_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_RTC_ALRA_TRG ) || \ - ((__SOURCE__) == SPI_GRP1_RTC_WUT_TRG )) - -#define IS_SPI_GRP2_TRIG_SOURCE(__SOURCE__) (((__SOURCE__) == SPI_GRP2_LPDMA_CH0_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_LPDMA_CH1_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_LPDMA_CH2_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_LPDMA_CH3_TCF_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_EXTI4_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_EXTI8_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_LPTIM1_CH1_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_LPTIM3_CH1_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_COMP1_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_COMP2_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_RTC_ALRA_TRG ) || \ - ((__SOURCE__) == SPI_GRP2_RTC_WUT_TRG )) - -#define IS_SPI_AUTO_MODE_TRG_POL(__POLARITY__) (((__POLARITY__) == SPI_TRIG_POLARITY_RISING) || \ - ((__POLARITY__) == SPI_TRIG_POLARITY_FALLING)) - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPIEx_Exported_Functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -/* IO operation functions *****************************************************/ -/** @addtogroup SPIEx_Exported_Functions_Group1 - * @{ - */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi); -HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, - uint32_t UnderrunBehaviour); -/** - * @} - */ - -/** @addtogroup SPI_Autonomous_Mode_Functions Autonomous Mode Functions - * @{ - */ -HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, - const SPI_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, - SPI_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi); -/** - * @} - */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_SPI_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h deleted file mode 100644 index e5919c183..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim.h +++ /dev/null @@ -1,2531 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_tim.h - * @author MCD Application Team - * @brief Header file of TIM HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_TIM_H -#define STM32U5xx_HAL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIM - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIM_Exported_Types TIM Exported Types - * @{ - */ - -/** - * @brief TIM Time base Configuration Structure definition - */ -typedef struct -{ - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF - Macro __HAL_TIM_CALC_PSC() can be used to calculate prescaler value */ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_Counter_Mode */ - - uint32_t Period; /*!< Specifies the period value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF - (or 0xFFEF if dithering is activated)Macros __HAL_TIM_CALC_PERIOD(), - __HAL_TIM_CALC_PERIOD_DITHER(),__HAL_TIM_CALC_PERIOD_BY_DELAY(), - __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY()can be used to calculate Period value */ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_ClockDivision */ - - uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - GP timers: this parameter must be a number between Min_Data = 0x00 and - Max_Data = 0xFF. - Advanced timers: this parameter must be a number between Min_Data = 0x0000 and - Max_Data = 0xFFFF. */ - - uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload. - This parameter can be a value of @ref TIM_AutoReloadPreload */ -} TIM_Base_InitTypeDef; - -/** - * @brief TIM Output Compare Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF - (or 0xFFEF if dithering is activated) - Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate - Pulse value */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCFastMode; /*!< Specifies the Fast mode state. - This parameter can be a value of @ref TIM_Output_Fast_State - @note This parameter is valid only in PWM1 and PWM2 mode. */ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ -} TIM_OC_InitTypeDef; - -/** - * @brief TIM One Pulse Mode Configuration Structure definition - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the TIM mode. - This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ - - uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF - (or 0xFFEF if dithering is activated) - Macros __HAL_TIM_CALC_PULSE(), __HAL_TIM_CALC_PULSE_DITHER() can be used to calculate - Pulse value */ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_Output_Compare_Polarity */ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_Output_Compare_N_Polarity - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State - @note This parameter is valid only for timer instances supporting break feature. */ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_OnePulse_InitTypeDef; - -/** - * @brief TIM Input Capture Configuration Structure definition - */ -typedef struct -{ - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t ICSelection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_IC_InitTypeDef; - -/** - * @brief TIM Encoder Configuration Structure definition - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Mode */ - - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC1Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Encoder_Input_Polarity */ - - uint32_t IC2Selection; /*!< Specifies the input. - This parameter can be a value of @ref TIM_Input_Capture_Selection */ - - uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC2Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_Encoder_InitTypeDef; - -/** - * @brief Clock Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClockSource; /*!< TIM clock sources - This parameter can be a value of @ref TIM_Clock_Source */ - uint32_t ClockPolarity; /*!< TIM clock polarity - This parameter can be a value of @ref TIM_Clock_Polarity */ - uint32_t ClockPrescaler; /*!< TIM clock prescaler - This parameter can be a value of @ref TIM_Clock_Prescaler */ - uint32_t ClockFilter; /*!< TIM clock filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClockConfigTypeDef; - -/** - * @brief TIM Clear Input Configuration Handle Structure definition - */ -typedef struct -{ - uint32_t ClearInputState; /*!< TIM clear Input state - This parameter can be ENABLE or DISABLE */ - uint32_t ClearInputSource; /*!< TIM clear Input sources - This parameter can be a value of @ref TIM_ClearInput_Source */ - uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity - This parameter can be a value of @ref TIM_ClearInput_Polarity */ - uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler - This parameter must be 0: When OCRef clear feature is used with ETR source, - ETR prescaler must be off */ - uint32_t ClearInputFilter; /*!< TIM Clear Input filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ -} TIM_ClearInputConfigTypeDef; - -/** - * @brief TIM Master configuration Structure definition - * @note Advanced timers provide TRGO2 internal line which is redirected - * to the ADC - */ -typedef struct -{ - uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection */ - uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection - This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ - uint32_t MasterSlaveMode; /*!< Master/slave mode selection - This parameter can be a value of @ref TIM_Master_Slave_Mode - @note When the Master/slave mode is enabled, the effect of - an event on the trigger input (TRGI) is delayed to allow a - perfect synchronization between the current timer and its - slaves (through TRGO). It is not mandatory in case of timer - synchronization mode. */ -} TIM_MasterConfigTypeDef; - -/** - * @brief TIM Slave configuration Structure definition - */ -typedef struct -{ - uint32_t SlaveMode; /*!< Slave mode selection - This parameter can be a value of @ref TIM_Slave_Mode */ - uint32_t InputTrigger; /*!< Input Trigger source - This parameter can be a value of @ref TIM_Trigger_Selection */ - uint32_t TriggerPolarity; /*!< Input Trigger polarity - This parameter can be a value of @ref TIM_Trigger_Polarity */ - uint32_t TriggerPrescaler; /*!< Input trigger prescaler - This parameter can be a value of @ref TIM_Trigger_Prescaler */ - uint32_t TriggerFilter; /*!< Input trigger filter - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - -} TIM_SlaveConfigTypeDef; - -/** - * @brief TIM Break input(s) and Dead time configuration Structure definition - * @note 2 break inputs can be configured (BKIN and BKIN2) with configurable - * filter and polarity. - */ -typedef struct -{ - uint32_t OffStateRunMode; /*!< TIM off state in run mode, This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */ - - uint32_t OffStateIDLEMode; /*!< TIM off state in IDLE mode, This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */ - - uint32_t LockLevel; /*!< TIM Lock level, This parameter can be a value of @ref TIM_Lock_level */ - - uint32_t DeadTime; /*!< TIM dead Time, This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF */ - - uint32_t BreakState; /*!< TIM Break State, This parameter can be a value of @ref TIM_Break_Input_enable_disable */ - - uint32_t BreakPolarity; /*!< TIM Break input polarity, This parameter can be a value of @ref TIM_Break_Polarity */ - - uint32_t BreakFilter; /*!< Specifies the break input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t BreakAFMode; /*!< Specifies the alternate function mode of the break input.This parameter can be a value of @ref TIM_Break_Input_AF_Mode */ - - uint32_t Break2State; /*!< TIM Break2 State, This parameter can be a value of @ref TIM_Break2_Input_enable_disable */ - - uint32_t Break2Polarity; /*!< TIM Break2 input polarity, This parameter can be a value of @ref TIM_Break2_Polarity */ - - uint32_t Break2Filter; /*!< TIM break2 input filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Break2AFMode; /*!< Specifies the alternate function mode of the break2 input.This parameter can be a value of @ref TIM_Break2_Input_AF_Mode */ - - uint32_t AutomaticOutput; /*!< TIM Automatic Output Enable state, This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ - -} TIM_BreakDeadTimeConfigTypeDef; - -/** - * @brief HAL State structures definition - */ -typedef enum -{ - HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ - HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ - HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ - HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ - HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ -} HAL_TIM_StateTypeDef; - -/** - * @brief TIM Channel States definition - */ -typedef enum -{ - HAL_TIM_CHANNEL_STATE_RESET = 0x00U, /*!< TIM Channel initial state */ - HAL_TIM_CHANNEL_STATE_READY = 0x01U, /*!< TIM Channel ready for use */ - HAL_TIM_CHANNEL_STATE_BUSY = 0x02U, /*!< An internal process is ongoing on the TIM channel */ -} HAL_TIM_ChannelStateTypeDef; - -/** - * @brief DMA Burst States definition - */ -typedef enum -{ - HAL_DMA_BURST_STATE_RESET = 0x00U, /*!< DMA Burst initial state */ - HAL_DMA_BURST_STATE_READY = 0x01U, /*!< DMA Burst ready for use */ - HAL_DMA_BURST_STATE_BUSY = 0x02U, /*!< Ongoing DMA Burst */ -} HAL_TIM_DMABurstStateTypeDef; - -/** - * @brief HAL Active channel structures definition - */ -typedef enum -{ - HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ - HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ - HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ - HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ - HAL_TIM_ACTIVE_CHANNEL_5 = 0x10U, /*!< The active channel is 5 */ - HAL_TIM_ACTIVE_CHANNEL_6 = 0x20U, /*!< The active channel is 6 */ - HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ -} HAL_TIM_ActiveChannel; - -/** - * @brief TIM Time Base Handle Structure definition - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -typedef struct __TIM_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -{ - TIM_TypeDef *Instance; /*!< Register base address */ - TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ - HAL_TIM_ActiveChannel Channel; /*!< Active channel */ - DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array - This array is accessed by a @ref DMA_Handle_index */ - HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelState[6]; /*!< TIM channel operation state */ - __IO HAL_TIM_ChannelStateTypeDef ChannelNState[4]; /*!< TIM complementary channel operation state */ - __IO HAL_TIM_DMABurstStateTypeDef DMABurstState; /*!< DMA burst operation state */ - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - void (* Base_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */ - void (* Base_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */ - void (* IC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */ - void (* IC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */ - void (* OC_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */ - void (* OC_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */ - void (* PWM_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */ - void (* PWM_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */ - void (* OnePulse_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */ - void (* OnePulse_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */ - void (* Encoder_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */ - void (* Encoder_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */ - void (* HallSensor_MspInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */ - void (* HallSensor_MspDeInitCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */ - void (* PeriodElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */ - void (* PeriodElapsedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed half complete Callback */ - void (* TriggerCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */ - void (* TriggerHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger half complete Callback */ - void (* IC_CaptureCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */ - void (* IC_CaptureHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture half complete Callback */ - void (* OC_DelayElapsedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */ - void (* PWM_PulseFinishedCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */ - void (* PWM_PulseFinishedHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished half complete Callback */ - void (* ErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */ - void (* CommutationCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */ - void (* CommutationHalfCpltCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation half complete Callback */ - void (* BreakCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */ - void (* Break2Callback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Break2 Callback */ - void (* EncoderIndexCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Index Callback */ - void (* DirectionChangeCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Direction Change Callback */ - void (* IndexErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Index Error Callback */ - void (* TransitionErrorCallback)(struct __TIM_HandleTypeDef *htim); /*!< TIM Transition Error Callback */ -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} TIM_HandleTypeDef; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief HAL TIM Callback ID enumeration definition - */ -typedef enum -{ - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ - , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ - , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ - , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ - , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ - , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ - , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ - , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ - , HAL_TIM_COMMUTATION_HALF_CB_ID = 0x19U /*!< TIM Commutation half complete Callback ID */ - , HAL_TIM_BREAK_CB_ID = 0x1AU /*!< TIM Break Callback ID */ - , HAL_TIM_BREAK2_CB_ID = 0x1BU /*!< TIM Break2 Callback ID */ - , HAL_TIM_ENCODER_INDEX_CB_ID = 0x1CU /*!< TIM Encoder Index Callback ID */ - , HAL_TIM_DIRECTION_CHANGE_CB_ID = 0x1DU /*!< TIM Direction Change Callback ID */ - , HAL_TIM_INDEX_ERROR_CB_ID = 0x1EU /*!< TIM Index Error Callback ID */ - , HAL_TIM_TRANSITION_ERROR_CB_ID = 0x1FU /*!< TIM Transition Error Callback ID */ -} HAL_TIM_CallbackIDTypeDef; - -/** - * @brief HAL TIM Callback pointer definition - */ -typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to the TIM callback function */ - -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_ClearInput_Source TIM Clear Input Source - * @{ - */ -#define TIM_CLEARINPUTSOURCE_NONE 0xFFFFFFFFU /*!< OCREF_CLR is disabled */ -#define TIM_CLEARINPUTSOURCE_ETR 0x00000001U /*!< OCREF_CLR is connected to ETRF input */ -#define TIM_CLEARINPUTSOURCE_COMP1 0x00000000U /*!< OCREF_CLR_INT is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_CLEARINPUTSOURCE_COMP2 TIM1_AF2_OCRSEL_0 /*!< OCREF_CLR_INT is connected to COMP2 output */ -#endif /* COMP2 */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Base_address TIM DMA Base Address - * @{ - */ -#define TIM_DMABASE_CR1 0x00000000U -#define TIM_DMABASE_CR2 0x00000001U -#define TIM_DMABASE_SMCR 0x00000002U -#define TIM_DMABASE_DIER 0x00000003U -#define TIM_DMABASE_SR 0x00000004U -#define TIM_DMABASE_EGR 0x00000005U -#define TIM_DMABASE_CCMR1 0x00000006U -#define TIM_DMABASE_CCMR2 0x00000007U -#define TIM_DMABASE_CCER 0x00000008U -#define TIM_DMABASE_CNT 0x00000009U -#define TIM_DMABASE_PSC 0x0000000AU -#define TIM_DMABASE_ARR 0x0000000BU -#define TIM_DMABASE_RCR 0x0000000CU -#define TIM_DMABASE_CCR1 0x0000000DU -#define TIM_DMABASE_CCR2 0x0000000EU -#define TIM_DMABASE_CCR3 0x0000000FU -#define TIM_DMABASE_CCR4 0x00000010U -#define TIM_DMABASE_BDTR 0x00000011U -#define TIM_DMABASE_CCR5 0x00000012U -#define TIM_DMABASE_CCR6 0x00000013U -#define TIM_DMABASE_CCMR3 0x00000014U -#define TIM_DMABASE_DTR2 0x00000015U -#define TIM_DMABASE_ECR 0x00000016U -#define TIM_DMABASE_TISEL 0x00000017U -#define TIM_DMABASE_AF1 0x00000018U -#define TIM_DMABASE_AF2 0x00000019U -#define TIM_DMABASE_OR1 0x0000001AU -/** - * @} - */ - -/** @defgroup TIM_Event_Source TIM Event Source - * @{ - */ -#define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG /*!< Reinitialize the counter and generates an update of the registers */ -#define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G /*!< A capture/compare event is generated on channel 1 */ -#define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G /*!< A capture/compare event is generated on channel 2 */ -#define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G /*!< A capture/compare event is generated on channel 3 */ -#define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G /*!< A capture/compare event is generated on channel 4 */ -#define TIM_EVENTSOURCE_COM TIM_EGR_COMG /*!< A commutation event is generated */ -#define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG /*!< A trigger event is generated */ -#define TIM_EVENTSOURCE_BREAK TIM_EGR_BG /*!< A break event is generated */ -#define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G /*!< A break 2 event is generated */ -/** - * @} - */ - -/** @defgroup TIM_Input_Channel_Polarity TIM Input Channel polarity - * @{ - */ -#define TIM_INPUTCHANNELPOLARITY_RISING 0x00000000U /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_FALLING TIM_CCER_CC1P /*!< Polarity for TIx source */ -#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Polarity TIM ETR Polarity - * @{ - */ -#define TIM_ETRPOLARITY_INVERTED TIM_SMCR_ETP /*!< Polarity for ETR source */ -#define TIM_ETRPOLARITY_NONINVERTED 0x00000000U /*!< Polarity for ETR source */ -/** - * @} - */ - -/** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler - * @{ - */ -#define TIM_ETRPRESCALER_DIV1 0x00000000U /*!< No prescaler is used */ -#define TIM_ETRPRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR input source is divided by 2 */ -#define TIM_ETRPRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR input source is divided by 4 */ -#define TIM_ETRPRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR input source is divided by 8 */ -/** - * @} - */ - -/** @defgroup TIM_Counter_Mode TIM Counter Mode - * @{ - */ -#define TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as up-counter */ -#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as down-counter */ -#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 /*!< Center-aligned mode 1 */ -#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 /*!< Center-aligned mode 2 */ -#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS /*!< Center-aligned mode 3 */ -/** - * @} - */ - -/** @defgroup TIM_Update_Interrupt_Flag_Remap TIM Update Interrupt Flag Remap - * @{ - */ -#define TIM_UIFREMAP_DISABLE 0x00000000U /*!< Update interrupt flag remap disabled */ -#define TIM_UIFREMAP_ENABLE TIM_CR1_UIFREMAP /*!< Update interrupt flag remap enabled */ -/** - * @} - */ - -/** @defgroup TIM_ClockDivision TIM Clock Division - * @{ - */ -#define TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< Clock division: tDTS=tCK_INT */ -#define TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< Clock division: tDTS=2*tCK_INT */ -#define TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< Clock division: tDTS=4*tCK_INT */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_State TIM Output Compare State - * @{ - */ -#define TIM_OUTPUTSTATE_DISABLE 0x00000000U /*!< Capture/Compare 1 output disabled */ -#define TIM_OUTPUTSTATE_ENABLE TIM_CCER_CC1E /*!< Capture/Compare 1 output enabled */ -/** - * @} - */ - -/** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload - * @{ - */ -#define TIM_AUTORELOAD_PRELOAD_DISABLE 0x00000000U /*!< TIMx_ARR register is not buffered */ -#define TIM_AUTORELOAD_PRELOAD_ENABLE TIM_CR1_ARPE /*!< TIMx_ARR register is buffered */ - -/** - * @} - */ - -/** @defgroup TIM_Output_Fast_State TIM Output Fast State - * @{ - */ -#define TIM_OCFAST_DISABLE 0x00000000U /*!< Output Compare fast disable */ -#define TIM_OCFAST_ENABLE TIM_CCMR1_OC1FE /*!< Output Compare fast enable */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State - * @{ - */ -#define TIM_OUTPUTNSTATE_DISABLE 0x00000000U /*!< OCxN is disabled */ -#define TIM_OUTPUTNSTATE_ENABLE TIM_CCER_CC1NE /*!< OCxN is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity - * @{ - */ -#define TIM_OCPOLARITY_HIGH 0x00000000U /*!< Capture/Compare output polarity */ -#define TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< Capture/Compare output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity - * @{ - */ -#define TIM_OCNPOLARITY_HIGH 0x00000000U /*!< Capture/Compare complementary output polarity */ -#define TIM_OCNPOLARITY_LOW TIM_CCER_CC1NP /*!< Capture/Compare complementary output polarity */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State - * @{ - */ -#define TIM_OCIDLESTATE_SET TIM_CR2_OIS1 /*!< Output Idle state: OCx=1 when MOE=0 */ -#define TIM_OCIDLESTATE_RESET 0x00000000U /*!< Output Idle state: OCx=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_N_Idle_State TIM Complementary Output Compare Idle State - * @{ - */ -#define TIM_OCNIDLESTATE_SET TIM_CR2_OIS1N /*!< Complementary output Idle state: OCxN=1 when MOE=0 */ -#define TIM_OCNIDLESTATE_RESET 0x00000000U /*!< Complementary output Idle state: OCxN=0 when MOE=0 */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity - * @{ - */ -#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Capture triggered by rising edge on timer input */ -#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Capture triggered by falling edge on timer input */ -#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Capture triggered by both rising and falling edges on timer input*/ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity - * @{ - */ -#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */ -#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection - * @{ - */ -#define TIM_ICSELECTION_DIRECTTI TIM_CCMR1_CC1S_0 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC1, IC2, IC3 or IC4, respectively */ -#define TIM_ICSELECTION_INDIRECTTI TIM_CCMR1_CC1S_1 /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to IC2, IC1, IC4 or IC3, respectively */ -#define TIM_ICSELECTION_TRC TIM_CCMR1_CC1S /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ -/** - * @} - */ - -/** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler - * @{ - */ -#define TIM_ICPSC_DIV1 0x00000000U /*!< Capture performed each time an edge is detected on the capture input */ -#define TIM_ICPSC_DIV2 TIM_CCMR1_IC1PSC_0 /*!< Capture performed once every 2 events */ -#define TIM_ICPSC_DIV4 TIM_CCMR1_IC1PSC_1 /*!< Capture performed once every 4 events */ -#define TIM_ICPSC_DIV8 TIM_CCMR1_IC1PSC /*!< Capture performed once every 8 events */ -/** - * @} - */ - -/** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode - * @{ - */ -#define TIM_OPMODE_SINGLE TIM_CR1_OPM /*!< Counter stops counting at the next update event */ -#define TIM_OPMODE_REPETITIVE 0x00000000U /*!< Counter is not stopped at update event */ -/** - * @} - */ - -/** @defgroup TIM_Encoder_Mode TIM Encoder Mode - * @{ - */ -#define TIM_ENCODERMODE_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode, counts up/down on TI1FP1 edge depending on TI2FP2 level */ -#define TIM_ENCODERMODE_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode, counts up/down on TI2FP2 edge depending on TI1FP1 level. */ -#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode, counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. */ -#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1) /*!< Encoder mode: Clock plus direction, x2 mode */ -#define TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode: Clock plus direction, x1 mode, TI2FP2 edge sensitivity is set by CC2P */ -#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2) /*!< Encoder mode: Directional Clock, x2 mode */ -#define TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Encoder mode: Directional Clock, x1 mode, TI1FP1 and TI2FP2 edge sensitivity is set by CC1P and CC2P */ -#define TIM_ENCODERMODE_X1_TI1 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Quadrature encoder mode: x1 mode, counting on TI1FP1 edges only, edge sensitivity is set by CC1P */ -#define TIM_ENCODERMODE_X1_TI2 (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode: x1 mode, counting on TI2FP2 edges only, edge sensitivity is set by CC1P */ -/** - * @} - */ - -/** @defgroup TIM_Interrupt_definition TIM interrupt Definition - * @{ - */ -#define TIM_IT_UPDATE TIM_DIER_UIE /*!< Update interrupt */ -#define TIM_IT_CC1 TIM_DIER_CC1IE /*!< Capture/Compare 1 interrupt */ -#define TIM_IT_CC2 TIM_DIER_CC2IE /*!< Capture/Compare 2 interrupt */ -#define TIM_IT_CC3 TIM_DIER_CC3IE /*!< Capture/Compare 3 interrupt */ -#define TIM_IT_CC4 TIM_DIER_CC4IE /*!< Capture/Compare 4 interrupt */ -#define TIM_IT_COM TIM_DIER_COMIE /*!< Commutation interrupt */ -#define TIM_IT_TRIGGER TIM_DIER_TIE /*!< Trigger interrupt */ -#define TIM_IT_BREAK TIM_DIER_BIE /*!< Break interrupt */ -#define TIM_IT_IDX TIM_DIER_IDXIE /*!< Index interrupt */ -#define TIM_IT_DIR TIM_DIER_DIRIE /*!< Direction change interrupt */ -#define TIM_IT_IERR TIM_DIER_IERRIE /*!< Index error interrupt */ -#define TIM_IT_TERR TIM_DIER_TERRIE /*!< Transition error interrupt */ -/** - * @} - */ - -/** @defgroup TIM_Commutation_Source TIM Commutation Source - * @{ - */ -#define TIM_COMMUTATION_TRGI TIM_CR2_CCUS /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit or when an rising edge occurs on trigger input */ -#define TIM_COMMUTATION_SOFTWARE 0x00000000U /*!< When Capture/compare control bits are preloaded, they are updated by setting the COMG bit */ -/** - * @} - */ - -/** @defgroup TIM_DMA_sources TIM DMA Sources - * @{ - */ -#define TIM_DMA_UPDATE TIM_DIER_UDE /*!< DMA request is triggered by the update event */ -#define TIM_DMA_CC1 TIM_DIER_CC1DE /*!< DMA request is triggered by the capture/compare macth 1 event */ -#define TIM_DMA_CC2 TIM_DIER_CC2DE /*!< DMA request is triggered by the capture/compare macth 2 event event */ -#define TIM_DMA_CC3 TIM_DIER_CC3DE /*!< DMA request is triggered by the capture/compare macth 3 event event */ -#define TIM_DMA_CC4 TIM_DIER_CC4DE /*!< DMA request is triggered by the capture/compare macth 4 event event */ -#define TIM_DMA_COM TIM_DIER_COMDE /*!< DMA request is triggered by the commutation event */ -#define TIM_DMA_TRIGGER TIM_DIER_TDE /*!< DMA request is triggered by the trigger event */ -/** - * @} - */ - -/** @defgroup TIM_CC_DMA_Request CCx DMA request selection - * @{ - */ -#define TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when capture or compare match event occurs */ -#define TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ -/** - * @} - */ - -/** @defgroup TIM_Flag_definition TIM Flag Definition - * @{ - */ -#define TIM_FLAG_UPDATE TIM_SR_UIF /*!< Update interrupt flag */ -#define TIM_FLAG_CC1 TIM_SR_CC1IF /*!< Capture/Compare 1 interrupt flag */ -#define TIM_FLAG_CC2 TIM_SR_CC2IF /*!< Capture/Compare 2 interrupt flag */ -#define TIM_FLAG_CC3 TIM_SR_CC3IF /*!< Capture/Compare 3 interrupt flag */ -#define TIM_FLAG_CC4 TIM_SR_CC4IF /*!< Capture/Compare 4 interrupt flag */ -#define TIM_FLAG_CC5 TIM_SR_CC5IF /*!< Capture/Compare 5 interrupt flag */ -#define TIM_FLAG_CC6 TIM_SR_CC6IF /*!< Capture/Compare 6 interrupt flag */ -#define TIM_FLAG_COM TIM_SR_COMIF /*!< Commutation interrupt flag */ -#define TIM_FLAG_TRIGGER TIM_SR_TIF /*!< Trigger interrupt flag */ -#define TIM_FLAG_BREAK TIM_SR_BIF /*!< Break interrupt flag */ -#define TIM_FLAG_BREAK2 TIM_SR_B2IF /*!< Break 2 interrupt flag */ -#define TIM_FLAG_SYSTEM_BREAK TIM_SR_SBIF /*!< System Break interrupt flag */ -#define TIM_FLAG_CC1OF TIM_SR_CC1OF /*!< Capture 1 overcapture flag */ -#define TIM_FLAG_CC2OF TIM_SR_CC2OF /*!< Capture 2 overcapture flag */ -#define TIM_FLAG_CC3OF TIM_SR_CC3OF /*!< Capture 3 overcapture flag */ -#define TIM_FLAG_CC4OF TIM_SR_CC4OF /*!< Capture 4 overcapture flag */ -#define TIM_FLAG_IDX TIM_SR_IDXF /*!< Encoder index flag */ -#define TIM_FLAG_DIR TIM_SR_DIRF /*!< Direction change flag */ -#define TIM_FLAG_IERR TIM_SR_IERRF /*!< Index error flag */ -#define TIM_FLAG_TERR TIM_SR_TERRF /*!< Transition error flag */ -/** - * @} - */ - -/** @defgroup TIM_Channel TIM Channel - * @{ - */ -#define TIM_CHANNEL_1 0x00000000U /*!< Capture/compare channel 1 identifier */ -#define TIM_CHANNEL_2 0x00000004U /*!< Capture/compare channel 2 identifier */ -#define TIM_CHANNEL_3 0x00000008U /*!< Capture/compare channel 3 identifier */ -#define TIM_CHANNEL_4 0x0000000CU /*!< Capture/compare channel 4 identifier */ -#define TIM_CHANNEL_5 0x00000010U /*!< Compare channel 5 identifier */ -#define TIM_CHANNEL_6 0x00000014U /*!< Compare channel 6 identifier */ -#define TIM_CHANNEL_ALL 0x0000003CU /*!< Global Capture/compare channel identifier */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Source TIM Clock Source - * @{ - */ -#define TIM_CLOCKSOURCE_INTERNAL TIM_SMCR_ETPS_0 /*!< Internal clock source */ -#define TIM_CLOCKSOURCE_ETRMODE1 TIM_TS_ETRF /*!< External clock source mode 1 (ETRF) */ -#define TIM_CLOCKSOURCE_ETRMODE2 TIM_SMCR_ETPS_1 /*!< External clock source mode 2 */ -#define TIM_CLOCKSOURCE_TI1ED TIM_TS_TI1F_ED /*!< External clock source mode 1 (TTI1FP1 + edge detect.) */ -#define TIM_CLOCKSOURCE_TI1 TIM_TS_TI1FP1 /*!< External clock source mode 1 (TTI1FP1) */ -#define TIM_CLOCKSOURCE_TI2 TIM_TS_TI2FP2 /*!< External clock source mode 1 (TTI2FP2) */ -#define TIM_CLOCKSOURCE_ITR0 TIM_TS_ITR0 /*!< External clock source mode 1 (ITR0) */ -#define TIM_CLOCKSOURCE_ITR1 TIM_TS_ITR1 /*!< External clock source mode 1 (ITR1) */ -#define TIM_CLOCKSOURCE_ITR2 TIM_TS_ITR2 /*!< External clock source mode 1 (ITR2) */ -#define TIM_CLOCKSOURCE_ITR3 TIM_TS_ITR3 /*!< External clock source mode 1 (ITR3) */ -#define TIM_CLOCKSOURCE_ITR4 TIM_TS_ITR4 /*!< External clock source mode 1 (ITR4) */ -#define TIM_CLOCKSOURCE_ITR5 TIM_TS_ITR5 /*!< External clock source mode 1 (ITR5) */ -#define TIM_CLOCKSOURCE_ITR6 TIM_TS_ITR6 /*!< External clock source mode 1 (ITR6) */ -#define TIM_CLOCKSOURCE_ITR7 TIM_TS_ITR7 /*!< External clock source mode 1 (ITR7) */ -#define TIM_CLOCKSOURCE_ITR8 TIM_TS_ITR8 /*!< External clock source mode 1 (ITR8) */ -#define TIM_CLOCKSOURCE_ITR11 TIM_TS_ITR11 /*!< External clock source mode 1 (ITR11) */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Polarity TIM Clock Polarity - * @{ - */ -#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ -#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ -#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ -/** - * @} - */ - -/** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler - * @{ - */ -#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ -#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ -#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity - * @{ - */ -#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler - * @{ - */ -#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state - * @{ - */ -#define TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ - -/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state - * @{ - */ -#define TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OC/OCN outputs are enabled (still controlled by the timer) */ -#define TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OC/OCN outputs are disabled (not controlled any longer by the timer) */ -/** - * @} - */ -/** @defgroup TIM_Lock_level TIM Lock level - * @{ - */ -#define TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF */ -#define TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ -#define TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ -#define TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ -/** - * @} - */ - -/** @defgroup TIM_Break_Input_enable_disable TIM Break Input Enable - * @{ - */ -#define TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break input BRK is enabled */ -#define TIM_BREAK_DISABLE 0x00000000U /*!< Break input BRK is disabled */ -/** - * @} - */ - -/** @defgroup TIM_Break_Polarity TIM Break Input Polarity - * @{ - */ -#define TIM_BREAKPOLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ -#define TIM_BREAKPOLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ -/** - * @} - */ - -/** @defgroup TIM_Break_Input_AF_Mode TIM Break Input Alternate Function Mode - * @{ - */ -#define TIM_BREAK_AFMODE_INPUT 0x00000000U /*!< Break input BRK in input mode */ -#define TIM_BREAK_AFMODE_BIDIRECTIONAL TIM_BDTR_BKBID /*!< Break input BRK in bidirectional mode */ -/** - * @} - */ - -/** @defgroup TIM_Break2_Input_enable_disable TIM Break input 2 Enable - * @{ - */ -#define TIM_BREAK2_DISABLE 0x00000000U /*!< Break input BRK2 is disabled */ -#define TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break input BRK2 is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Break2_Polarity TIM Break Input 2 Polarity - * @{ - */ -#define TIM_BREAK2POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ -#define TIM_BREAK2POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ -/** - * @} - */ - -/** @defgroup TIM_Break2_Input_AF_Mode TIM Break2 Input Alternate Function Mode - * @{ - */ -#define TIM_BREAK2_AFMODE_INPUT 0x00000000U /*!< Break2 input BRK2 in input mode */ -#define TIM_BREAK2_AFMODE_BIDIRECTIONAL TIM_BDTR_BK2BID /*!< Break2 input BRK2 in bidirectional mode */ -/** - * @} - */ - -/** @defgroup TIM_AOE_Bit_Set_Reset TIM Automatic Output Enable - * @{ - */ -#define TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event (if none of the break inputs BRK and BRK2 is active) */ -/** - * @} - */ - -/** @defgroup TIM_Group_Channel5 TIM Group Channel 5 and Channel 1, 2 or 3 - * @{ - */ -#define TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ -#define TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ -#define TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ -#define TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection - * @{ - */ -#define TIM_TRGO_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO) */ -#define TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO) */ -#define TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1 (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO) */ -#define TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output (TRGO) */ -#define TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output(TRGO) */ -#define TIM_TRGO_ENCODER_CLK TIM_CR2_MMS_3 /*!< Encoder clock is used as trigger output(TRGO) */ -/** - * @} - */ - -/** @defgroup TIM_Master_Mode_Selection_2 TIM Master Mode Selection 2 (TRGO2) - * @{ - */ -#define TIM_TRGO2_RESET 0x00000000U /*!< TIMx_EGR.UG bit is used as trigger output (TRGO2) */ -#define TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< TIMx_CR1.CEN bit is used as trigger output (TRGO2) */ -#define TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC1 (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< Capture or a compare match 1 is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC1REF TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC2REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC3REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC4REF (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC5REF TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC6REF (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output (TRGO2) */ -#define TIM_TRGO2_OC4REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC6REF_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC4REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC5REF_RISING_OC6REF_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ -#define TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF or OC6REF rising edges generate pulses on TRGO2 */ -/** - * @} - */ - -/** @defgroup TIM_Master_Slave_Mode TIM Master/Slave Mode - * @{ - */ -#define TIM_MASTERSLAVEMODE_ENABLE TIM_SMCR_MSM /*!< No action */ -#define TIM_MASTERSLAVEMODE_DISABLE 0x00000000U /*!< Master/slave mode is selected */ -/** - * @} - */ - -/** @defgroup TIM_Slave_Mode TIM Slave mode - * @{ - */ -#define TIM_SLAVEMODE_DISABLE 0x00000000U /*!< Slave mode disabled */ -#define TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode */ -#define TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode */ -#define TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode */ -#define TIM_SLAVEMODE_EXTERNAL1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< External Clock Mode 1 */ -#define TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode */ -#define TIM_SLAVEMODE_COMBINED_GATEDRESET (TIM_SMCR_SMS_3 | TIM_SMCR_SMS_0) /*!< Combined gated + reset mode */ -/** - * @} - */ - -/** @defgroup TIM_Output_Compare_and_PWM_modes TIM Output Compare and PWM Modes - * @{ - */ -#define TIM_OCMODE_TIMING 0x00000000U /*!< Frozen */ -#define TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!< Set channel to active level on match */ -#define TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!< Set channel to inactive level on match */ -#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< Toggle */ -#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!< PWM mode 1 */ -#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!< PWM mode 2 */ -#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!< Force active level */ -#define TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!< Force inactive level */ -#define TIM_OCMODE_RETRIGERRABLE_OPM1 TIM_CCMR1_OC1M_3 /*!< Retrigerrable OPM mode 1 */ -#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ -#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ -#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ -#define TIM_OCMODE_PULSE_ON_COMPARE (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1) /*!< Pulse on compare (CH3&CH4 only) */ -#define TIM_OCMODE_DIRECTION_OUTPUT (TIM_CCMR2_OC3M_3 | TIM_CCMR2_OC3M_1 | TIM_CCMR2_OC3M_0) /*!< Direction output (CH3&CH4 only) */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Selection TIM Trigger Selection - * @{ - */ -#define TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) */ -#define TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) */ -#define TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) */ -#define TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) */ -#define TIM_TS_ITR4 (TIM_SMCR_TS_3) /*!< Internal Trigger 4 (ITR4) */ -#define TIM_TS_ITR5 (TIM_SMCR_TS_0 | TIM_SMCR_TS_3) /*!< Internal Trigger 5 (ITR5) */ -#define TIM_TS_ITR6 (TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 6 (ITR6) */ -#define TIM_TS_ITR7 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_3) /*!< Internal Trigger 7 (ITR7) */ -#define TIM_TS_ITR8 (TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 8 (ITR8) */ -#define TIM_TS_ITR11 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2 | TIM_SMCR_TS_3) /*!< Internal Trigger 11 (ITR11) */ -#define TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) */ -#define TIM_TS_TI1FP1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 1 (TI1FP1) */ -#define TIM_TS_TI2FP2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered Timer Input 2 (TI2FP2) */ -#define TIM_TS_ETRF (TIM_SMCR_TS_0 | TIM_SMCR_TS_1 | TIM_SMCR_TS_2) /*!< Filtered External Trigger input (ETRF) */ -#define TIM_TS_NONE 0x0000FFFFU /*!< No trigger selected */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity - * @{ - */ -#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ -#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ -/** - * @} - */ - -/** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler - * @{ - */ -#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ -#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ -#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ -/** - * @} - */ - -/** @defgroup TIM_TI1_Selection TIM TI1 Input Selection - * @{ - */ -#define TIM_TI1SELECTION_CH1 0x00000000U /*!< The TIMx_CH1 pin is connected to TI1 input */ -#define TIM_TI1SELECTION_XORCOMBINATION TIM_CR2_TI1S /*!< The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) */ -/** - * @} - */ - -/** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length - * @{ - */ -#define TIM_DMABURSTLENGTH_1TRANSFER 0x00000000U /*!< The transfer is done to 1 register starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_2TRANSFERS 0x00000100U /*!< The transfer is done to 2 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_3TRANSFERS 0x00000200U /*!< The transfer is done to 3 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_4TRANSFERS 0x00000300U /*!< The transfer is done to 4 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_5TRANSFERS 0x00000400U /*!< The transfer is done to 5 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_6TRANSFERS 0x00000500U /*!< The transfer is done to 6 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_7TRANSFERS 0x00000600U /*!< The transfer is done to 7 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_8TRANSFERS 0x00000700U /*!< The transfer is done to 8 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_9TRANSFERS 0x00000800U /*!< The transfer is done to 9 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_10TRANSFERS 0x00000900U /*!< The transfer is done to 10 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_11TRANSFERS 0x00000A00U /*!< The transfer is done to 11 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_12TRANSFERS 0x00000B00U /*!< The transfer is done to 12 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_13TRANSFERS 0x00000C00U /*!< The transfer is done to 13 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_14TRANSFERS 0x00000D00U /*!< The transfer is done to 14 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_15TRANSFERS 0x00000E00U /*!< The transfer is done to 15 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_16TRANSFERS 0x00000F00U /*!< The transfer is done to 16 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_17TRANSFERS 0x00001000U /*!< The transfer is done to 17 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_18TRANSFERS 0x00001100U /*!< The transfer is done to 18 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_19TRANSFERS 0x00001200U /*!< The transfer is done to 19 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_20TRANSFERS 0x00001300U /*!< The transfer is done to 20 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_21TRANSFERS 0x00001400U /*!< The transfer is done to 21 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_22TRANSFERS 0x00001500U /*!< The transfer is done to 22 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_23TRANSFERS 0x00001600U /*!< The transfer is done to 23 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_24TRANSFERS 0x00001700U /*!< The transfer is done to 24 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_25TRANSFERS 0x00001800U /*!< The transfer is done to 25 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -#define TIM_DMABURSTLENGTH_26TRANSFERS 0x00001900U /*!< The transfer is done to 26 registers starting from TIMx_CR1 + TIMx_DCR.DBA */ -/** - * @} - */ - -/** @defgroup DMA_Handle_index TIM DMA Handle Index - * @{ - */ -#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0000) /*!< Index of the DMA handle used for Update DMA requests */ -#define TIM_DMA_ID_CC1 ((uint16_t) 0x0001) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ -#define TIM_DMA_ID_CC2 ((uint16_t) 0x0002) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ -#define TIM_DMA_ID_CC3 ((uint16_t) 0x0003) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ -#define TIM_DMA_ID_CC4 ((uint16_t) 0x0004) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ -#define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x0005) /*!< Index of the DMA handle used for Commutation DMA requests */ -#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x0006) /*!< Index of the DMA handle used for Trigger DMA requests */ -/** - * @} - */ - -/** @defgroup Channel_CC_State TIM Capture/Compare Channel State - * @{ - */ -#define TIM_CCx_ENABLE 0x00000001U /*!< Input or output channel is enabled */ -#define TIM_CCx_DISABLE 0x00000000U /*!< Input or output channel is disabled */ -#define TIM_CCxN_ENABLE 0x00000004U /*!< Complementary output channel is enabled */ -#define TIM_CCxN_DISABLE 0x00000000U /*!< Complementary output channel is enabled */ -/** - * @} - */ - -/** @defgroup TIM_Break_System TIM Break System - * @{ - */ -#define TIM_BREAK_SYSTEM_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal with Break Input of TIM1/8/15/16/17/20 */ -#define TIM_BREAK_SYSTEM_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection with TIM1/8/15/16/17/20 Break Input and also the PVDE and PLS bits of the Power Control Interface */ -#define TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIM1/8/15/16/17/20 */ -#define TIM_BREAK_SYSTEM_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM4 with Break Input of TIM1/8/15/16/17/20 */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup TIM_Exported_Macros TIM Exported Macros - * @{ - */ - -/** @brief Reset TIM handle state. - * @param __HANDLE__ TIM handle. - * @retval None - */ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - (__HANDLE__)->Base_MspInitCallback = NULL; \ - (__HANDLE__)->Base_MspDeInitCallback = NULL; \ - (__HANDLE__)->IC_MspInitCallback = NULL; \ - (__HANDLE__)->IC_MspDeInitCallback = NULL; \ - (__HANDLE__)->OC_MspInitCallback = NULL; \ - (__HANDLE__)->OC_MspDeInitCallback = NULL; \ - (__HANDLE__)->PWM_MspInitCallback = NULL; \ - (__HANDLE__)->PWM_MspDeInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspInitCallback = NULL; \ - (__HANDLE__)->OnePulse_MspDeInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspInitCallback = NULL; \ - (__HANDLE__)->Encoder_MspDeInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspInitCallback = NULL; \ - (__HANDLE__)->HallSensor_MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) do { \ - (__HANDLE__)->State = HAL_TIM_STATE_RESET; \ - (__HANDLE__)->ChannelState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[4] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelState[5] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[0] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[1] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[2] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->ChannelNState[3] = HAL_TIM_CHANNEL_STATE_RESET; \ - (__HANDLE__)->DMABurstState = HAL_DMA_BURST_STATE_RESET; \ - } while(0) -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @brief Enable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) - -/** - * @brief Enable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE)) - -/** - * @brief Disable the TIM peripheral. - * @param __HANDLE__ TIM handle - * @retval None - */ -#define __HAL_TIM_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been - * disabled - */ -#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ - do { \ - if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ - { \ - if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ - { \ - (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ - } \ - } \ - } while(0) - -/** - * @brief Disable the TIM main Output. - * @param __HANDLE__ TIM handle - * @retval None - * @note The Main Output Enable of a timer instance is disabled unconditionally - */ -#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE) - -/** @brief Enable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to enable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @arg TIM_IT_IDX: Index interrupt - * @arg TIM_IT_DIR: Direction change interrupt - * @arg TIM_IT_IERR: Index error interrupt - * @arg TIM_IT_TERR: Transition error interrupt - * @retval None - */ -#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) - -/** @brief Disable the specified TIM interrupt. - * @param __HANDLE__ specifies the TIM Handle. - * @param __INTERRUPT__ specifies the TIM interrupt source to disable. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @arg TIM_IT_IDX: Index interrupt - * @arg TIM_IT_DIR: Direction change interrupt - * @arg TIM_IT_IERR: Index error interrupt - * @arg TIM_IT_TERR: Transition error interrupt - * @retval None - */ -#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) - -/** @brief Enable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to enable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) - -/** @brief Disable the specified DMA request. - * @param __HANDLE__ specifies the TIM Handle. - * @param __DMA__ specifies the TIM DMA request to disable. - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: Update DMA request - * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request - * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request - * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request - * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request - * @arg TIM_DMA_COM: Commutation DMA request - * @arg TIM_DMA_TRIGGER: Trigger DMA request - * @retval None - */ -#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) - -/** @brief Check whether the specified TIM interrupt flag is set or not. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to check. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @arg TIM_FLAG_IDX: Index interrupt flag - * @arg TIM_FLAG_DIR: Direction change interrupt flag - * @arg TIM_FLAG_IERR: Index error interrupt flag - * @arg TIM_FLAG_TERR: Transition error interrupt flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) - -/** @brief Clear the specified TIM interrupt flag. - * @param __HANDLE__ specifies the TIM Handle. - * @param __FLAG__ specifies the TIM interrupt flag to clear. - * This parameter can be one of the following values: - * @arg TIM_FLAG_UPDATE: Update interrupt flag - * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag - * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag - * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag - * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag - * @arg TIM_FLAG_CC5: Compare 5 interrupt flag - * @arg TIM_FLAG_CC6: Compare 6 interrupt flag - * @arg TIM_FLAG_COM: Commutation interrupt flag - * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag - * @arg TIM_FLAG_BREAK: Break interrupt flag - * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag - * @arg TIM_FLAG_SYSTEM_BREAK: System Break interrupt flag - * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag - * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag - * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag - * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag - * @arg TIM_FLAG_IDX: Index interrupt flag - * @arg TIM_FLAG_DIR: Direction change interrupt flag - * @arg TIM_FLAG_IERR: Index error interrupt flag - * @arg TIM_FLAG_TERR: Transition error interrupt flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) - -/** - * @brief Check whether the specified TIM interrupt source is enabled or not. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the TIM interrupt source to check. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @arg TIM_IT_IDX: Index interrupt - * @arg TIM_IT_DIR: Direction change interrupt - * @arg TIM_IT_IERR: Index error interrupt - * @arg TIM_IT_TERR: Transition error interrupt - * @retval The state of TIM_IT (SET or RESET). - */ -#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \ - == (__INTERRUPT__)) ? SET : RESET) - -/** @brief Clear the TIM interrupt pending bits. - * @param __HANDLE__ TIM handle - * @param __INTERRUPT__ specifies the interrupt pending bit to clear. - * This parameter can be one of the following values: - * @arg TIM_IT_UPDATE: Update interrupt - * @arg TIM_IT_CC1: Capture/Compare 1 interrupt - * @arg TIM_IT_CC2: Capture/Compare 2 interrupt - * @arg TIM_IT_CC3: Capture/Compare 3 interrupt - * @arg TIM_IT_CC4: Capture/Compare 4 interrupt - * @arg TIM_IT_COM: Commutation interrupt - * @arg TIM_IT_TRIGGER: Trigger interrupt - * @arg TIM_IT_BREAK: Break interrupt - * @arg TIM_IT_IDX: Index interrupt - * @arg TIM_IT_DIR: Direction change interrupt - * @arg TIM_IT_IERR: Index error interrupt - * @arg TIM_IT_TERR: Transition error interrupt - * @retval None - */ -#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) - -/** - * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). - * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read - * in an atomic way. - * @param __HANDLE__ TIM handle. - * @retval None -mode. - */ -#define __HAL_TIM_UIFREMAP_ENABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 |= TIM_CR1_UIFREMAP)) - -/** - * @brief Disable update interrupt flag (UIF) remapping. - * @param __HANDLE__ TIM handle. - * @retval None -mode. - */ -#define __HAL_TIM_UIFREMAP_DISABLE(__HANDLE__) (((__HANDLE__)->Instance->CR1 &= ~TIM_CR1_UIFREMAP)) - -/** - * @brief Get update interrupt flag (UIF) copy status. - * @param __COUNTER__ Counter value. - * @retval The state of UIFCPY (TRUE or FALSE). -mode. - */ -#define __HAL_TIM_GET_UIFCPY(__COUNTER__) (((__COUNTER__) & (TIM_CNT_UIFCPY)) == (TIM_CNT_UIFCPY)) - -/** - * @brief Indicates whether or not the TIM Counter is used as downcounter. - * @param __HANDLE__ TIM handle. - * @retval False (Counter used as upcounter) or True (Counter used as downcounter) - * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode - * or Encoder mode. - */ -#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) - -/** - * @brief Set the TIM Prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __PRESC__ specifies the Prescaler new value. - * @retval None - */ -#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) - -/** - * @brief Set the TIM Counter Register value on runtime. - * Note Please check if the bit 31 of CNT register is used as UIF copy or not, this may affect the counter range in - * case of 32 bits counter TIM instance. - * Bit 31 of CNT can be enabled/disabled using __HAL_TIM_UIFREMAP_ENABLE()/__HAL_TIM_UIFREMAP_DISABLE() macros. - * @param __HANDLE__ TIM handle. - * @param __COUNTER__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) - -/** - * @brief Get the TIM Counter Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) - */ -#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) - -/** - * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __AUTORELOAD__ specifies the Counter register new value. - * @retval None - */ -#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ - do{ \ - (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ - (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ - } while(0) - -/** - * @brief Get the TIM Autoreload Register value on runtime. - * @param __HANDLE__ TIM handle. - * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) - */ -#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) - -/** - * @brief Set the TIM Clock Division value on runtime without calling another time any Init function. - * @param __HANDLE__ TIM handle. - * @param __CKD__ specifies the clock division value. - * This parameter can be one of the following value: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - * @retval None - */ -#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ - do{ \ - (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ - (__HANDLE__)->Instance->CR1 |= (__CKD__); \ - (__HANDLE__)->Init.ClockDivision = (__CKD__); \ - } while(0) - -/** - * @brief Get the TIM Clock Division value on runtime. - * @param __HANDLE__ TIM handle. - * @retval The clock division can be one of the following values: - * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT - * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT - * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT - */ -#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) - -/** - * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() - * function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __ICPSC__ specifies the Input Capture4 prescaler new value. - * This parameter can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - * @retval None - */ -#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ - do{ \ - TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ - } while(0) - -/** - * @brief Get the TIM Input Capture prescaler on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get input capture 1 prescaler value - * @arg TIM_CHANNEL_2: get input capture 2 prescaler value - * @arg TIM_CHANNEL_3: get input capture 3 prescaler value - * @arg TIM_CHANNEL_4: get input capture 4 prescaler value - * @retval The input capture prescaler can be one of the following values: - * @arg TIM_ICPSC_DIV1: no prescaler - * @arg TIM_ICPSC_DIV2: capture is done once every 2 events - * @arg TIM_ICPSC_DIV4: capture is done once every 4 events - * @arg TIM_ICPSC_DIV8: capture is done once every 8 events - */ -#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8U) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ - (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) - -/** - * @brief Set the TIM Capture Compare Register value on runtime without calling another time ConfigChannel function. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param __COMPARE__ specifies the Capture Compare register new value. - * @retval None - */ -#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ - ((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) - -/** - * @brief Get the TIM Capture Compare Register value on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channel associated with the capture compare register - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: get capture/compare 1 register value - * @arg TIM_CHANNEL_2: get capture/compare 2 register value - * @arg TIM_CHANNEL_3: get capture/compare 3 register value - * @arg TIM_CHANNEL_4: get capture/compare 4 register value - * @arg TIM_CHANNEL_5: get capture/compare 5 register value - * @arg TIM_CHANNEL_6: get capture/compare 6 register value - * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) - */ -#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ - ((__HANDLE__)->Instance->CCR6)) - -/** - * @brief Set the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) - -/** - * @brief Reset the TIM Output compare preload. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\ - ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE)) - -/** - * @brief Enable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @note When fast mode is enabled an active edge on the trigger input acts - * like a compare match on CCx output. Delay to sample the trigger - * input and to activate CCx output is reduced to 3 clock cycles. - * @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode. - * @retval None - */ -#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\ - ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE)) - -/** - * @brief Disable fast mode for a given channel. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @note When fast mode is disabled CCx output behaves normally depending - * on counter and CCRx values even when the trigger is ON. The minimum - * delay to activate CCx output when an active edge occurs on the - * trigger input is 5 clock cycles. - * @retval None - */ -#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\ - ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE)) - -/** - * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is set, only counter - * overflow/underflow generates an update interrupt or DMA request (if - * enabled) - * @retval None - */ -#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS) - -/** - * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. - * @param __HANDLE__ TIM handle. - * @note When the URS bit of the TIMx_CR1 register is reset, any of the - * following events generate an update interrupt or DMA request (if - * enabled): - * _ Counter overflow underflow - * _ Setting the UG bit - * _ Update generation through the slave mode controller - * @retval None - */ -#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS) - -/** - * @brief Set the TIM Capture x input polarity on runtime. - * @param __HANDLE__ TIM handle. - * @param __CHANNEL__ TIM Channels to be configured. - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param __POLARITY__ Polarity for TIx source - * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge - * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge - * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge - * @retval None - */ -#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - do{ \ - TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ - TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ - }while(0) - -/** @brief Select the Capture/compare DMA request source. - * @param __HANDLE__ specifies the TIM Handle. - * @param __CCDMA__ specifies Capture/compare DMA request source - * This parameter can be one of the following values: - * @arg TIM_CCDMAREQUEST_CC: CCx DMA request generated on Capture/Compare event - * @arg TIM_CCDMAREQUEST_UPDATE: CCx DMA request generated on Update event - * @retval None - */ -#define __HAL_TIM_SELECT_CCDMAREQUEST(__HANDLE__, __CCDMA__) \ - MODIFY_REG((__HANDLE__)->Instance->CR2, TIM_CR2_CCDS, (__CCDMA__)) - -/** - * @} - */ -/* End of exported macros ----------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_Private_Constants TIM Private Constants - * @{ - */ -/* The counter of a timer instance is disabled only if all the CCx and CCxN - channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) -#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_Private_Macros TIM Private Macros - * @{ - */ -#if defined(COMP2) -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP2) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) -#else -#define IS_TIM_CLEARINPUT_SOURCE(__MODE__) (((__MODE__) == TIM_CLEARINPUTSOURCE_ETR) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_COMP1) || \ - ((__MODE__) == TIM_CLEARINPUTSOURCE_NONE)) -#endif /* COMP2 */ - -#define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ - ((__BASE__) == TIM_DMABASE_CR2) || \ - ((__BASE__) == TIM_DMABASE_SMCR) || \ - ((__BASE__) == TIM_DMABASE_DIER) || \ - ((__BASE__) == TIM_DMABASE_SR) || \ - ((__BASE__) == TIM_DMABASE_EGR) || \ - ((__BASE__) == TIM_DMABASE_CCMR1) || \ - ((__BASE__) == TIM_DMABASE_CCMR2) || \ - ((__BASE__) == TIM_DMABASE_CCER) || \ - ((__BASE__) == TIM_DMABASE_CNT) || \ - ((__BASE__) == TIM_DMABASE_PSC) || \ - ((__BASE__) == TIM_DMABASE_ARR) || \ - ((__BASE__) == TIM_DMABASE_RCR) || \ - ((__BASE__) == TIM_DMABASE_CCR1) || \ - ((__BASE__) == TIM_DMABASE_CCR2) || \ - ((__BASE__) == TIM_DMABASE_CCR3) || \ - ((__BASE__) == TIM_DMABASE_CCR4) || \ - ((__BASE__) == TIM_DMABASE_BDTR) || \ - ((__BASE__) == TIM_DMABASE_CCMR3) || \ - ((__BASE__) == TIM_DMABASE_CCR5) || \ - ((__BASE__) == TIM_DMABASE_CCR6) || \ - ((__BASE__) == TIM_DMABASE_AF1) || \ - ((__BASE__) == TIM_DMABASE_AF2) || \ - ((__BASE__) == TIM_DMABASE_TISEL) || \ - ((__BASE__) == TIM_DMABASE_DTR2) || \ - ((__BASE__) == TIM_DMABASE_ECR) || \ - ((__BASE__) == TIM_DMABASE_OR1)) - -#define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ - ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ - ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) - -#define IS_TIM_UIFREMAP_MODE(__MODE__) (((__MODE__) == TIM_UIFREMAP_DISABLE) || \ - ((__MODE__) == TIM_UIFREMAP_ENABLE)) - -#define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ - ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) - -#define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \ - ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE)) - -#define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ - ((__STATE__) == TIM_OCFAST_ENABLE)) - -#define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCPOLARITY_LOW)) - -#define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \ - ((__POLARITY__) == TIM_OCNPOLARITY_LOW)) - -#define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCIDLESTATE_RESET)) - -#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ - ((__STATE__) == TIM_OCNIDLESTATE_RESET)) - -#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING)) - -#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) - -#define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ - ((__SELECTION__) == TIM_ICSELECTION_TRC)) - -#define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ - ((__PRESCALER__) == TIM_ICPSC_DIV8)) - -#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ - ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ - ((__CHANNEL__) != (TIM_CHANNEL_6))) - -#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ - ((__MODE__) == TIM_OPMODE_REPETITIVE)) - -#define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_TI2) || \ - ((__MODE__) == TIM_ENCODERMODE_TI12) || \ - ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2) || \ - ((__MODE__) == TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1) || \ - ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X2) || \ - ((__MODE__) == TIM_ENCODERMODE_DIRECTIONALCLOCK_X1_TI12) || \ - ((__MODE__) == TIM_ENCODERMODE_X1_TI1) || \ - ((__MODE__) == TIM_ENCODERMODE_X1_TI2)) - -#define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) - -#define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4) || \ - ((__CHANNEL__) == TIM_CHANNEL_5) || \ - ((__CHANNEL__) == TIM_CHANNEL_6) || \ - ((__CHANNEL__) == TIM_CHANNEL_ALL)) - -#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2)) - -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ - (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ - ((__PERIOD__) > 0U)) - -#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ - ((__CHANNEL__) == TIM_CHANNEL_2) || \ - ((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4)) - -#define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11)) - -#define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ - ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) - -#define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) - -#define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) - -#define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) - -#define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \ - ((__STATE__) == TIM_OSSR_DISABLE)) - -#define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \ - ((__STATE__) == TIM_OSSI_DISABLE)) - -#define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_1) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_2) || \ - ((__LEVEL__) == TIM_LOCKLEVEL_3)) - -#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - - -#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ - ((__STATE__) == TIM_BREAK_DISABLE)) - -#define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH)) - -#define IS_TIM_BREAK_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK_AFMODE_INPUT) || \ - ((__AFMODE__) == TIM_BREAK_AFMODE_BIDIRECTIONAL)) - - -#define IS_TIM_BREAK2_STATE(__STATE__) (((__STATE__) == TIM_BREAK2_ENABLE) || \ - ((__STATE__) == TIM_BREAK2_DISABLE)) - -#define IS_TIM_BREAK2_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAK2POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAK2POLARITY_HIGH)) - -#define IS_TIM_BREAK2_AFMODE(__AFMODE__) (((__AFMODE__) == TIM_BREAK2_AFMODE_INPUT) || \ - ((__AFMODE__) == TIM_BREAK2_AFMODE_BIDIRECTIONAL)) - - -#define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \ - ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE)) - -#define IS_TIM_GROUPCH5(__OCREF__) ((((__OCREF__) & 0x1FFFFFFFU) == 0x00000000U)) - -#define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ - ((__SOURCE__) == TIM_TRGO_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO_OC1) || \ - ((__SOURCE__) == TIM_TRGO_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO_OC4REF) || \ - ((__SOURCE__) == TIM_TRGO_ENCODER_CLK)) - -#define IS_TIM_TRGO2_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO2_RESET) || \ - ((__SOURCE__) == TIM_TRGO2_ENABLE) || \ - ((__SOURCE__) == TIM_TRGO2_UPDATE) || \ - ((__SOURCE__) == TIM_TRGO2_OC1) || \ - ((__SOURCE__) == TIM_TRGO2_OC1REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC2REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC3REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC6REF_RISINGFALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC4REF_RISING_OC6REF_FALLING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_RISING) || \ - ((__SOURCE__) == TIM_TRGO2_OC5REF_RISING_OC6REF_FALLING)) - -#define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ - ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) - -#define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ - ((__MODE__) == TIM_SLAVEMODE_RESET) || \ - ((__MODE__) == TIM_SLAVEMODE_GATED) || \ - ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1) || \ - ((__MODE__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER) || \ - ((__MODE__) == TIM_SLAVEMODE_COMBINED_GATEDRESET)) - -#define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ - ((__MODE__) == TIM_OCMODE_PWM2) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ - ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) - -#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ - ((__MODE__) == TIM_OCMODE_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_TOGGLE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ - ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM1) || \ - ((__MODE__) == TIM_OCMODE_RETRIGERRABLE_OPM2) || \ - ((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || \ - ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) - -#define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ - ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) - -#define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) - -#define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ - ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) - -#define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_19TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_20TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_21TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_22TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_23TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_24TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_25TRANSFERS) || \ - ((__LENGTH__) == TIM_DMABURSTLENGTH_26TRANSFERS)) - -#define IS_TIM_DMA_DATA_LENGTH(LENGTH) (((LENGTH) >= 0x1U) && ((LENGTH) < 0x10000U)) - -#define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) - -#define IS_TIM_DEADTIME(__DEADTIME__) ((__DEADTIME__) <= 0xFFU) - -#define IS_TIM_BREAK_SYSTEM(__CONFIG__) (((__CONFIG__) == TIM_BREAK_SYSTEM_ECC) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_PVD) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_SRAM_PARITY_ERROR) || \ - ((__CONFIG__) == TIM_BREAK_SYSTEM_LOCKUP)) - -#define IS_TIM_SLAVEMODE_TRIGGER_ENABLED(__TRIGGER__) (((__TRIGGER__) == TIM_SLAVEMODE_TRIGGER) || \ - ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) - -#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ - ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) - -#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\ - ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC)) - -#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ - ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) - -#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ - ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) - -#define TIM_CHANNEL_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelState[2] :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? (__HANDLE__)->ChannelState[3] :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? (__HANDLE__)->ChannelState[4] :\ - (__HANDLE__)->ChannelState[5]) - -#define TIM_CHANNEL_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) - -#define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ - (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? (__HANDLE__)->ChannelNState[1] :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? (__HANDLE__)->ChannelNState[2] :\ - (__HANDLE__)->ChannelNState[3]) - -#define TIM_CHANNEL_N_STATE_SET(__HANDLE__, __CHANNEL__, __CHANNEL_STATE__) \ - (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__)) :\ - ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ - ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) - -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) - -/** - * @} - */ -/* End of private macros -----------------------------------------------------*/ - -/* Include TIM HAL Extended module */ -#include "stm32u5xx_hal_tim_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @addtogroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * @{ - */ -/* Time Base functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * @{ - */ -/* Timer Output Compare functions *********************************************/ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * @{ - */ -/* Timer PWM functions ********************************************************/ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * @{ - */ -/* Timer Input Capture functions **********************************************/ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * @{ - */ -/* Timer One Pulse functions **************************************************/ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * @{ - */ -/* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length); -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief IRQ handler management - * @{ - */ -/* Interrupt Handler functions ***********************************************/ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Control functions *********************************************************/ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel); -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - const TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel); -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig); -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength); -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); -uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * @{ - */ -/* Callback in non blocking modes (Interrupt and DMA) *************************/ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief Peripheral State functions - * @{ - */ -/* Peripheral State functions ************************************************/ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim); - -/* Peripheral Channel state functions ************************************************/ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure); -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter); - -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_DMAError(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma); -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState); -HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, - uint32_t length); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -void TIM_ResetCallback(TIM_HandleTypeDef *htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_TIM_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h deleted file mode 100644 index b800440ac..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_tim_ex.h +++ /dev/null @@ -1,1123 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_tim_ex.h - * @author MCD Application Team - * @brief Header file of TIM HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_TIM_EX_H -#define STM32U5xx_HAL_TIM_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup TIMEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Types TIM Extended Exported Types - * @{ - */ - -/** - * @brief TIM Hall sensor Configuration Structure definition - */ - -typedef struct -{ - uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_Input_Capture_Polarity */ - - uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ - - uint32_t IC1Filter; /*!< Specifies the input capture filter. - This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Commutation_Delay; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ -} TIM_HallSensor_InitTypeDef; - -/** - * @brief TIM Break/Break2 input configuration - */ -typedef struct -{ - uint32_t Source; /*!< Specifies the source of the timer break input. - This parameter can be a value of @ref TIMEx_Break_Input_Source */ - uint32_t Enable; /*!< Specifies whether or not the break input source is enabled. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */ - uint32_t Polarity; /*!< Specifies the break input source polarity. - This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity */ -} TIMEx_BreakInputConfigTypeDef; - -/** - * @brief TIM Encoder index configuration - */ -typedef struct -{ - uint32_t Polarity; /*!< TIM Encoder index polarity.This parameter can be a value of @ref TIMEx_Encoder_Index_Polarity */ - - uint32_t Prescaler; /*!< TIM Encoder index prescaler.This parameter can be a value of @ref TIMEx_Encoder_Index_Prescaler */ - - uint32_t Filter; /*!< TIM Encoder index filter.This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ - - uint32_t Blanking; /*!< Specifies whether or not the encoder index event is conditioned by TI3 or TI4 input.This parameter can be a value of @ref TIMEx_Encoder_Index_Blanking */ - - FunctionalState FirstIndexEnable; /*!< Specifies whether or not the encoder first index is enabled.This parameter value can be ENABLE or DISABLE. */ - - uint32_t Position; /*!< Specifies in which AB input configuration the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Position */ - - uint32_t Direction; /*!< Specifies in which counter direction the index event resets the counter.This parameter can be a value of @ref TIMEx_Encoder_Index_Direction */ - -} TIMEx_EncoderIndexConfigTypeDef; - -/** - * @} - */ -/* End of exported types -----------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Constants TIM Extended Exported Constants - * @{ - */ - -/** @defgroup TIMEx_Remap TIM Extended Remapping - * @{ - */ -#define TIM_TIM1_ETR_GPIO 0x00000000UL /*!< TIM1_ETR is not connected to I/O */ -#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM1_ETR is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM1_ETR is connected to COMP2 output */ -#endif /* COMP2 */ -#define TIM_TIM1_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSIK */ -#define TIM_TIM1_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM1_ETR is connected to HSI */ -#define TIM_TIM1_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to MSI */ -#if defined(ADC2) -#define TIM_TIM1_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM1_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC2 AWD3 */ -#endif /* ADC2 */ -#define TIM_TIM1_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3) /*!< TIM1_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM1_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM1_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD1 */ -#define TIM_TIM1_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM1_ETR is connected to ADC4 AWD2 */ -#define TIM_TIM1_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM1_ETR is connected to ADC4 AWD3 */ -#if defined(ADC2) -#define TIM_TIM1_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM1_ETR is connected to ADC2 AWD1 */ -#endif /* ADC2 */ - -#define TIM_TIM2_ETR_GPIO 0x00000000UL /*!< TIM2_ETR is not connected to I/O */ -#define TIM_TIM2_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM2_ETR is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_TIM2_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM2_ETR is connected to COMP2 output */ -#endif /* COMP2 */ -#define TIM_TIM2_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIK */ -#define TIM_TIM2_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM2_ETR is connected to HSI */ -#define TIM_TIM2_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to MSIS */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM2_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DCMI VSYNC */ -#define TIM_TIM2_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LTDC_VSYNC */ -#endif /* DCMI && LTDC */ -#define TIM_TIM2_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM2_ETR is connected to TIM3 ETR */ -#define TIM_TIM2_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to TIM4 ETR */ -#define TIM_TIM2_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to TIM5 ETR */ -#define TIM_TIM2_ETR_LSE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LSE */ -#if defined(DSI) -#define TIM_TIM2_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to DSI_TE */ -#endif /* DSI */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM2_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DCMI HSYNC */ -#define TIM_TIM2_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM2_ETR is connected to LTDC HSYNC */ -#endif /* DCMI && LTDC */ - -#define TIM_TIM3_ETR_GPIO 0x00000000UL /*!< TIM3_ETR is not connected to I/O */ -#define TIM_TIM3_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM3_ETR is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_TIM3_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM3_ETR is connected to COMP2 output */ -#endif /* COMP2 */ -#define TIM_TIM3_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIK */ -#define TIM_TIM3_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM3_ETR is connected to HSI */ -#define TIM_TIM3_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to MSIS */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM3_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DCMI VSYNC */ -#define TIM_TIM3_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to LTDC_VSYNC */ -#endif /* DCMI && LTDC */ -#define TIM_TIM3_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM3_ETR is connected to TIM2 ETR */ -#define TIM_TIM3_ETR_TIM4_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to TIM4 ETR */ -#if defined(DSI) -#define TIM_TIM3_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DSI_TE */ -#endif /* DSI */ -#define TIM_TIM3_ETR_ADC1_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM3_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM3_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM3_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to ADC1 AWD3 */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM3_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM3_ETR is connected to DCMI HSYNC */ -#define TIM_TIM3_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM3_ETR is connected to LTDC HSYNC */ -#endif /* DCMI && LTDC */ - -#define TIM_TIM4_ETR_GPIO 0x00000000UL /*!< TIM4_ETR is not connected to I/O */ -#define TIM_TIM4_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM4_ETR is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_TIM4_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM4_ETR is connected to COMP2 output */ -#endif /* COMP2 */ -#define TIM_TIM4_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIK */ -#define TIM_TIM4_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM4_ETR is connected to HSI */ -#define TIM_TIM4_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to MSIS */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM4_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to DCMI VSYNC */ -#define TIM_TIM4_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to LTDC_VSYNC */ -#endif /* DCMI && LTDC */ -#define TIM_TIM4_ETR_TIM3_ETR TIM1_AF1_ETRSEL_3 /*!< TIM4_ETR is connected to TIM3 ETR */ -#define TIM_TIM4_ETR_TIM5_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to TIM5 ETR */ -#if defined(DSI) -#define TIM_TIM4_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM2_ETR is connected to DSI_TE */ -#endif /* DSI */ -#if defined(ADC2) -#define TIM_TIM4_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to ADC2 AWD1 */ -#define TIM_TIM4_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM4_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM4_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to ADC2 AWD3 */ -#endif /* ADC2 */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM4_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM4_ETR is connected to DCMI HSYNC */ -#define TIM_TIM4_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM4_ETR is connected to LTDC HSYNC */ -#endif /* DCMI && LTDC */ - -#define TIM_TIM5_ETR_GPIO 0x00000000UL /*!< TIM5_ETR is not connected to I/O */ -#define TIM_TIM5_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM5_ETR is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_TIM5_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM5_ETR is connected to COMP2 output */ -#endif /* COMP2 */ -#define TIM_TIM5_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIK */ -#define TIM_TIM5_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM5_ETR is connected to HSI */ -#define TIM_TIM5_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to MSIS */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM5_ETR_DCMI_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DCMI VSYNC */ -#define TIM_TIM5_ETR_LTDC_VSYNC (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to LTDC_VSYNC */ -#endif /* DCMI && LTDC */ -#define TIM_TIM5_ETR_TIM2_ETR TIM1_AF1_ETRSEL_3 /*!< TIM5_ETR is connected to TIM2 ETR */ -#define TIM_TIM5_ETR_TIM3_ETR (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to TIM3 ETR */ -#if defined(DSI) -#define TIM_TIM5_ETR_DSI_TE (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DSI_TE */ -#endif /* DSI */ -#if defined(DCMI) && defined(LTDC) -#define TIM_TIM5_ETR_DCMI_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM5_ETR is connected to DCMI HSYNC */ -#define TIM_TIM5_ETR_LTDC_HSYNC (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM5_ETR is connected to LTDC HSYNC */ -#endif /* DCMI && LTDC */ - -#define TIM_TIM8_ETR_GPIO 0x00000000UL /*!< TIM8_ETR is not connected to I/O */ -#define TIM_TIM8_ETR_COMP1 TIM1_AF1_ETRSEL_0 /*!< TIM8_ETR is connected to COMP1 output */ -#if defined(COMP2) -#define TIM_TIM8_ETR_COMP2 TIM1_AF1_ETRSEL_1 /*!< TIM8_ETR is connected to COMP2 output */ -#endif /* COMP2 */ -#define TIM_TIM8_ETR_MSIK (TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIK */ -#define TIM_TIM8_ETR_HSI TIM1_AF1_ETRSEL_2 /*!< TIM8_ETR is connected to HSI */ -#define TIM_TIM8_ETR_MSIS (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to MSIS */ -#if defined(ADC2) -#define TIM_TIM8_ETR_ADC2_AWD2 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC2 AWD2 */ -#define TIM_TIM8_ETR_ADC2_AWD3 (TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1| TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC2 AWD3 */ -#endif /* ADC2 */ -#define TIM_TIM8_ETR_ADC1_AWD1 TIM1_AF1_ETRSEL_3 /*!< TIM8_ETR is connected to ADC1 AWD1 */ -#define TIM_TIM8_ETR_ADC1_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC1 AWD2 */ -#define TIM_TIM8_ETR_ADC1_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC1 AWD3 */ -#define TIM_TIM8_ETR_ADC4_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_1 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD1 */ -#define TIM_TIM8_ETR_ADC4_AWD2 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2) /*!< TIM8_ETR is connected to ADC4 AWD2 */ -#define TIM_TIM8_ETR_ADC4_AWD3 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_0) /*!< TIM8_ETR is connected to ADC4 AWD3 */ -#if defined(ADC2) -#define TIM_TIM8_ETR_ADC2_AWD1 (TIM1_AF1_ETRSEL_3 | TIM1_AF1_ETRSEL_2 | TIM1_AF1_ETRSEL_1) /*!< TIM8_ETR is connected to ADC2 AWD1 */ -#endif /* ADC2 */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input TIM Extended Break input - * @{ - */ -#define TIM_BREAKINPUT_BRK 0x00000001U /*!< Timer break input */ -#define TIM_BREAKINPUT_BRK2 0x00000002U /*!< Timer break2 input */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source TIM Extended Break input source - * @{ - */ -#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /*!< An external source (GPIO) is connected to the BKIN pin */ -#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /*!< The COMP1 output is connected to the break input */ -#if defined(COMP2) -#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /*!< The COMP2 output is connected to the break input */ -#endif /* COMP2 */ -#define TIM_BREAKINPUTSOURCE_MDF1 0x00000008U /*!< The analog watchdog output of the MDF1 peripheral is connected to the break input */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Enable TIM Extended Break input source enabling - * @{ - */ -#define TIM_BREAKINPUTSOURCE_DISABLE 0x00000000U /*!< Break input source is disabled */ -#define TIM_BREAKINPUTSOURCE_ENABLE 0x00000001U /*!< Break input source is enabled */ -/** - * @} - */ - -/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity - * @{ - */ -#define TIM_BREAKINPUTSOURCE_POLARITY_LOW 0x00000001U /*!< Break input source is active low */ -#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH 0x00000000U /*!< Break input source is active_high */ -/** - * @} - */ - -/** @defgroup TIMEx_Timer_Input_Selection TIM Extended Timer input selection - * @{ - */ -#define TIM_TIM1_TI1_GPIO 0x00000000UL /*!< TIM1_TI1 is connected to GPIO */ -#define TIM_TIM1_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM1_TI1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM1_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM1_TI1 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM2_TI1_GPIO 0x00000000UL /*!< TIM2_TI1 is connected to GPIO */ -#define TIM_TIM2_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM2_TI1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM2_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM2_TI1 is connected to COMP2 OUT */ -#endif /* COMP2 */ -#define TIM_TIM2_TI2_GPIO 0x00000000UL /*!< TIM2_TI2 is connected to GPIO */ -#define TIM_TIM2_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM2_TI2 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM2_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM2_TI2 is connected to COMP2 OUT */ -#endif /* COMP2 */ -#define TIM_TIM2_TI4_GPIO 0x00000000UL /*!< TIM2_TI4 is connected to GPIO */ -#define TIM_TIM2_TI4_COMP1 TIM_TISEL_TI4SEL_0 /*!< TIM2_TI4 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM2_TI4_COMP2 TIM_TISEL_TI4SEL_1 /*!< TIM2_TI4 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM3_TI1_GPIO 0x00000000UL /*!< TIM3_TI1 is connected to GPIO */ -#define TIM_TIM3_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM3_TI1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM3_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM3_TI1 is connected to COMP2 OUT */ -#endif /* COMP2 */ -#define TIM_TIM3_TI2_GPIO 0x00000000UL /*!< TIM3_TI2 is connected to GPIO */ -#define TIM_TIM3_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM3_TI2 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM3_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM3_TI2 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM4_TI1_GPIO 0x00000000UL /*!< TIM4_TI1 is connected to GPIO */ -#define TIM_TIM4_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM4_TI1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM4_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM4_TI1 is connected to COMP2 OUT */ -#endif /* COMP2 */ -#define TIM_TIM4_TI2_GPIO 0x00000000UL /*!< TIM4_TI2 is connected to GPIO */ -#define TIM_TIM4_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM4_TI2 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM4_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM4_TI2 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM5_TI1_GPIO 0x00000000UL /*!< TIM5_TI1 is connected to GPIO */ -#define TIM_TIM5_TI1_LSI TIM_TISEL_TI1SEL_0 /*!< TIM5_TI1 is connected to LSI */ -#define TIM_TIM5_TI1_LSE TIM_TISEL_TI1SEL_1 /*!< TIM5_TI1 is connected to LSE */ -#define TIM_TIM5_TI1_RTC_WKUP (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM5_TI1 is connected to RTC Wakeup */ -#define TIM_TIM5_TI1_COMP1 TIM_TISEL_TI1SEL_2 /*!< TIM5_COMP1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM5_TI1_COMP2 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM5_COMP2 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM5_TI2_GPIO 0x00000000UL /*!< TIM5_TI2 is connected to GPIO */ -#define TIM_TIM5_TI2_COMP1 TIM_TISEL_TI2SEL_0 /*!< TIM5_TI2 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM5_TI2_COMP2 TIM_TISEL_TI2SEL_1 /*!< TIM5_TI2 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM8_TI1_GPIO 0x00000000UL /*!< TIM8_TI1 is connected to GPIO */ -#define TIM_TIM8_TI1_COMP1 TIM_TISEL_TI1SEL_0 /*!< TIM8_TI1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM8_TI1_COMP2 TIM_TISEL_TI1SEL_1 /*!< TIM8_TI1 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM15_TI1_GPIO 0x00000000UL /*!< TIM15_TI1 is connected to GPIO */ -#define TIM_TIM15_TI1_LSE TIM_TISEL_TI1SEL_0 /*!< TIM15_TI1 is connected to LSE */ -#define TIM_TIM15_TI1_COMP1 TIM_TISEL_TI1SEL_1 /*!< TIM15_TI1 is connected to COMP1 OUT */ -#if defined(COMP2) -#define TIM_TIM15_TI1_COMP2 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM15_TI1 is connected to COMP2 OUT */ -#endif /* COMP2 */ -#define TIM_TIM15_TI2_GPIO 0x00000000UL /*!< TIM15_TI2 is connected to GPIO */ -#if defined(COMP2) -#define TIM_TIM15_TI2_COMP2 TIM_TISEL_TI2SEL_0 /*!< TIM15_TI2 is connected to COMP2 OUT */ -#endif /* COMP2 */ - -#define TIM_TIM16_TI1_GPIO 0x00000000UL /*!< TIM16_TI1 is connected to GPIO */ -#define TIM_TIM16_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM16_TI1 is connected to MCO */ -#define TIM_TIM16_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSE/32 */ -#define TIM_TIM16_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM16_TI1 is connected to RTC Wakeup */ -#define TIM_TIM16_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to LSE */ -#define TIM_TIM16_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM16_TI1 is connected to LSI */ -#define TIM_TIM16_TI1_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to MSIS/1024 */ -#define TIM_TIM16_TI1_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM16_TI1 is connected to MSIS/4 */ -#define TIM_TIM16_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM16_TI1 is connected to HSI/256 */ - -#define TIM_TIM17_TI1_GPIO 0x00000000UL /*!< TIM17_TI1 is connected to GPIO */ -#define TIM_TIM17_TI1_MCO TIM_TISEL_TI1SEL_1 /*!< TIM17_TI1 is connected to MCO */ -#define TIM_TIM17_TI1_HSE_DIV32 (TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSE/32 */ -#define TIM_TIM17_TI1_RTC_WKUP TIM_TISEL_TI1SEL_2 /*!< TIM17_TI1 is connected to RTC Wakeup */ -#define TIM_TIM17_TI1_LSE (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to LSE */ -#define TIM_TIM17_TI1_LSI (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1) /*!< TIM17_TI1 is connected to LSI */ -#define TIM_TIM17_TI1_MSIS_1024 (TIM_TISEL_TI1SEL_2 | TIM_TISEL_TI1SEL_1 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to MSIS/1024 */ -#define TIM_TIM17_TI1_MSIS_4 TIM_TISEL_TI1SEL_3 /*!< TIM17_TI1 is connected to MSIS/4 */ -#define TIM_TIM17_TI1_HSI_256 (TIM_TISEL_TI1SEL_3 | TIM_TISEL_TI1SEL_0) /*!< TIM17_TI1 is connected to HSI/256 */ -/** - * @} - */ - -/** @defgroup TIMEx_SMS_Preload_Enable TIM Extended Bitfield SMS preload enabling - * @{ - */ -#define TIM_SMS_PRELOAD_SOURCE_UPDATE 0x00000000U /*!< Prelaod of SMS bitfield is disabled */ -#define TIM_SMS_PRELOAD_SOURCE_INDEX TIM_SMCR_SMSPS /*!< Preload of SMS bitfield is enabled */ -/** - * @} - */ - -/** @defgroup TIMEx_Encoder_Index_Blanking TIM Extended Encoder index blanking - * @{ - */ -#define TIM_ENCODERINDEX_BLANKING_DISABLE 0x00000000U /*!< Encoder index blanking is disabled */ -#define TIM_ENCODERINDEX_BLANKING_TI3 TIM_ECR_IBLK_0 /*!< Encoder index blanking is enabled on TI3 */ -#define TIM_ENCODERINDEX_BLANKING_TI4 TIM_ECR_IBLK_1 /*!< Encoder index blanking is enabled on TI4 */ - -/** - * @} - */ - -/** @defgroup TIMEx_Encoder_Index_Position TIM Extended Encoder index position - * @{ - */ -#define TIM_ENCODERINDEX_POSITION_00 0x00000000U /*!< Encoder index position is AB=00 */ -#define TIM_ENCODERINDEX_POSITION_01 TIM_ECR_IPOS_0 /*!< Encoder index position is AB=01 */ -#define TIM_ENCODERINDEX_POSITION_10 TIM_ECR_IPOS_1 /*!< Encoder index position is AB=10 */ -#define TIM_ENCODERINDEX_POSITION_11 (TIM_ECR_IPOS_1 | TIM_ECR_IPOS_0) /*!< Encoder index position is AB=11 */ -#define TIM_ENCODERINDEX_POSITION_0 0x00000000U /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 0 */ -#define TIM_ENCODERINDEX_POSITION_1 TIM_ECR_IPOS_0 /*!< In directional clock mode or clock plus direction mode, index resets the counter when clock is 1 */ -/** - * @} - */ - -/** @defgroup TIMEx_Encoder_Index_Direction TIM Extended Encoder index direction - * @{ - */ -#define TIM_ENCODERINDEX_DIRECTION_UP_DOWN 0x00000000U /*!< Index resets the counter whatever the direction */ -#define TIM_ENCODERINDEX_DIRECTION_UP TIM_ECR_IDIR_0 /*!< Index resets the counter when up-counting only */ -#define TIM_ENCODERINDEX_DIRECTION_DOWN TIM_ECR_IDIR_1 /*!< Index resets the counter when down-counting only */ -/** - * @} - */ - -/** @defgroup TIMEx_Encoder_Index_Polarity TIM Extended Encoder index polarity - * @{ - */ -#define TIM_ENCODERINDEX_POLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ -#define TIM_ENCODERINDEX_POLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ -/** - * @} - */ - -/** @defgroup TIMEx_Encoder_Index_Prescaler TIM Extended Encodder index prescaler - * @{ - */ -#define TIM_ENCODERINDEX_PRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ -#define TIM_ENCODERINDEX_PRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ -#define TIM_ENCODERINDEX_PRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ -#define TIM_ENCODERINDEX_PRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ -/** - * @} - */ - -/** - * @} - */ -/* End of exported constants -------------------------------------------------*/ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Macros TIM Extended Exported Macros - * @{ - */ - -/** - * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. - * @note ex: @ref __HAL_TIM_CALC_PSC(80000000, 1000000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CNTCLK__ counter clock frequency (in Hz) - * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) - */ -#define __HAL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. - * @note ex: @ref __HAL_TIM_CALC_PERIOD(1000000, 0, 10000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __FREQ__ output signal frequency (in Hz) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __HAL_TIM_CALC_PERIOD(__TIMCLK__, __PSC__, __FREQ__) \ - (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U - -/** - * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required - * output signal frequency. - * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER(1000000, 0, 10000); - * @note This macro should be used only if dithering is already enabled - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __FREQ__ output signal frequency (in Hz) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) - */ -#define __HAL_TIM_CALC_PERIOD_DITHER(__TIMCLK__, __PSC__, __FREQ__) \ - (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? \ - (uint32_t)(((uint64_t)(__TIMCLK__)*16/((__FREQ__) * ((__PSC__) + 1U)) - 16U)) : 0U - -/** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare - * active/inactive delay. - * @note ex: @ref __HAL_TIM_CALC_PULSE(1000000, 0, 10); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @retval Compare value (between Min_Data=0 and Max_Data=65535) - */ -#define __HAL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__) \ - ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) - -/** - * @brief HELPER macro calculating the compare value, with dithering feature enabled, to achieve the required timer - * output compare active/inactive delay. - * @note ex: @ref __HAL_TIM_CALC_PULSE_DITHER(1000000, 0, 10); - * @note This macro should be used only if dithering is already enabled - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @retval Compare value (between Min_Data=0 and Max_Data=65519) - */ -#define __HAL_TIM_CALC_PULSE_DITHER(__TIMCLK__, __PSC__, __DELAY__) \ - ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__) * 16U) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration - * (when the timer operates in one pulse mode). - * @note ex: @ref __HAL_TIM_CALC_PERIOD_BY_DELAY(1000000, 0, 10, 20); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @param __PULSE__ pulse duration (in us) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __HAL_TIM_CALC_PERIOD_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __HAL_TIM_CALC_PULSE((__TIMCLK__), (__PSC__), (__DELAY__)))) - -/** - * @brief HELPER macro calculating the auto-reload value, with dithering feature enabled, to achieve the required - * pulse duration (when the timer operates in one pulse mode). - * @note ex: @ref __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(1000000, 0, 10, 20); - * @note This macro should be used only if dithering is already enabled - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @param __PULSE__ pulse duration (in us) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65519) - */ -#define __HAL_TIM_CALC_PERIOD_DITHER_BY_DELAY(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __HAL_TIM_CALC_PULSE_DITHER((__TIMCLK__), (__PSC__), (__DELAY__)))) - -/** - * @} - */ -/* End of exported macro -----------------------------------------------------*/ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Macros TIM Extended Private Macros - * @{ - */ -#define IS_TIM_REMAP(__REMAP__) ((((__REMAP__) & 0xFFFC3FFFU) == 0x00000000U)) -#define IS_TIM_BREAKINPUT(__BREAKINPUT__) (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ - ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) - -#if defined(COMP2) -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) -#else -#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ - ((__SOURCE__) == TIM_BREAKINPUTSOURCE_MDF1)) -#endif /* COMP2 */ - -#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ - ((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE)) - -#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \ - ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH)) - -#define IS_TIM_TISEL(__TISEL__) ((((__TISEL__) & 0xF0F0F0F0U) == 0x00000000U)) - -#define IS_TIM_TISEL_TIX_INSTANCE(INSTANCE, CHANNEL) \ - (IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) && ((CHANNEL) < TIM_CHANNEL_5)) - -#define IS_TIM_CLOCKSOURCE_INSTANCE(INSTANCE, __CLOCK__) \ - ((((INSTANCE) == TIM1) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ - || \ - (((INSTANCE) == TIM2) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR11))) \ - || \ - (((INSTANCE) == TIM3) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ - || \ - (((INSTANCE) == TIM4) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ - || \ - (((INSTANCE) == TIM5) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ - || \ - (((INSTANCE) == TIM8) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR6) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8))) \ - || \ - (((INSTANCE) == TIM15) && \ - (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR4) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR5) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR7) || \ - ((__CLOCK__) == TIM_CLOCKSOURCE_ITR8)))) - -#define IS_TIM_TRIGGER_INSTANCE(INSTANCE, __SELECTION__) \ - ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8))) \ - || \ - (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8))) \ - || \ - (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8))) \ - || \ - (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8))) \ - || \ - (((INSTANCE) == TIM5) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8))) \ - || \ - (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ETRF) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8))) \ - || \ - (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_TI1F_ED) || \ - ((__SELECTION__) == TIM_TS_TI1FP1) || \ - ((__SELECTION__) == TIM_TS_TI2FP2) || \ - ((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8)))) - -#define IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(INSTANCE, __SELECTION__) \ - ((((INSTANCE) == TIM1) && \ - (((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_NONE))) \ - || \ - (((INSTANCE) == TIM2) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_ITR11)|| \ - ((__SELECTION__) == TIM_TS_NONE))) \ - || \ - (((INSTANCE) == TIM3) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_NONE))) \ - || \ - (((INSTANCE) == TIM4) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_NONE))) \ - || \ - (((INSTANCE) == TIM5) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_NONE))) \ - || \ - (((INSTANCE) == TIM8) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR6) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_NONE))) \ - || \ - (((INSTANCE) == TIM15) && \ - (((__SELECTION__) == TIM_TS_ITR0) || \ - ((__SELECTION__) == TIM_TS_ITR1) || \ - ((__SELECTION__) == TIM_TS_ITR2) || \ - ((__SELECTION__) == TIM_TS_ITR3) || \ - ((__SELECTION__) == TIM_TS_ITR4) || \ - ((__SELECTION__) == TIM_TS_ITR5) || \ - ((__SELECTION__) == TIM_TS_ITR7) || \ - ((__SELECTION__) == TIM_TS_ITR8) || \ - ((__SELECTION__) == TIM_TS_NONE)))) - -#define IS_TIM_OC_CHANNEL_MODE(__MODE__, __CHANNEL__) \ - (IS_TIM_OC_MODE(__MODE__) \ - && ((((__MODE__) == TIM_OCMODE_DIRECTION_OUTPUT) || ((__MODE__) == TIM_OCMODE_PULSE_ON_COMPARE)) \ - ? (((__CHANNEL__) == TIM_CHANNEL_3) || ((__CHANNEL__) == TIM_CHANNEL_4)) : (1 == 1))) - -#define IS_TIM_PULSEONCOMPARE_CHANNEL(__CHANNEL__) \ - (((__CHANNEL__) == TIM_CHANNEL_3) || \ - ((__CHANNEL__) == TIM_CHANNEL_4)) - -#define IS_TIM_PULSEONCOMPARE_INSTANCE(INSTANCE) IS_TIM_CC3_INSTANCE(INSTANCE) - -#define IS_TIM_PULSEONCOMPARE_WIDTH(__WIDTH__) ((__WIDTH__) <= 0xFFU) - -#define IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0x7U) - -#define IS_TIM_SLAVE_PRELOAD_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_UPDATE) \ - || ((__SOURCE__) == TIM_SMS_PRELOAD_SOURCE_INDEX)) - -#define IS_TIM_ENCODERINDEX_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_INVERTED) || \ - ((__POLARITY__) == TIM_ENCODERINDEX_POLARITY_NONINVERTED)) - -#define IS_TIM_ENCODERINDEX_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV1) || \ - ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV2) || \ - ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV4) || \ - ((__PRESCALER__) == TIM_ENCODERINDEX_PRESCALER_DIV8)) - -#define IS_TIM_ENCODERINDEX_FILTER(__FILTER__) ((__FILTER__) <= 0xFUL) - -#define IS_TIM_ENCODERINDEX_POSITION(__POSITION__) (((__POSITION__) == TIM_ENCODERINDEX_POSITION_00) || \ - ((__POSITION__) == TIM_ENCODERINDEX_POSITION_01) || \ - ((__POSITION__) == TIM_ENCODERINDEX_POSITION_10) || \ - ((__POSITION__) == TIM_ENCODERINDEX_POSITION_11) || \ - ((__POSITION__) == TIM_ENCODERINDEX_POSITION_0) || \ - ((__POSITION__) == TIM_ENCODERINDEX_POSITION_1)) - -#define IS_TIM_ENCODERINDEX_DIRECTION(__DIRECTION__) (((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP_DOWN) || \ - ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_UP) || \ - ((__DIRECTION__) == TIM_ENCODERINDEX_DIRECTION_DOWN)) - -#define IS_TIM_ENCODERINDEX_BLANKING(__BLANKING__) (((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_DISABLE) || \ - ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI3) || \ - ((__BLANKING__) == TIM_ENCODERINDEX_BLANKING_TI4)) - -/** - * @} - */ -/* End of private macro ------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * @{ - */ -/* Timer Hall Sensor functions **********************************************/ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); - -void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim); -void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim); - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * @{ - */ -/* Timer Complementary Output Compare functions *****************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * @{ - */ -/* Timer Complementary PWM functions ****************************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); -/* Non-Blocking mode: DMA */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length); -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * @{ - */ -/* Timer Complementary One Pulse functions **********************************/ -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); - -/* Non-Blocking mode: Interrupt */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Extended Control functions ************************************************/ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource); -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - const TIM_MasterConfigTypeDef *sMasterConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, - const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); -HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel); -HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim); - -HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, uint32_t PulseWidthPrescaler, - uint32_t PulseWidth); -HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source); -HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime); -HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime); -HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, - TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig); -HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim); -HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * @{ - */ -/* Extended Callback **********************************************************/ -void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim); -void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim); -/** - * @} - */ - -/** @addtogroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * @{ - */ -/* Extended Peripheral State functions ***************************************/ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim); -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN); -/** - * @} - */ - -/** - * @} - */ -/* End of exported functions -------------------------------------------------*/ - -/* Private functions----------------------------------------------------------*/ -/** @addtogroup TIMEx_Private_Functions TIM Extended Private Functions - * @{ - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma); -/** - * @} - */ -/* End of private functions --------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32U5xx_HAL_TIM_EX_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h deleted file mode 100644 index 988f5be2b..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart.h +++ /dev/null @@ -1,1751 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_uart.h - * @author MCD Application Team - * @brief Header file of UART HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_UART_H -#define STM32U5xx_HAL_UART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UART_Exported_Types UART Exported Types - * @{ - */ - -/** - * @brief UART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - LPUART: - ======= - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - where uart_ker_ck_pres is the UART input clock divided by a prescaler */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ - -} UART_InitTypeDef; - -/** - * @brief UART Advanced Features initialization structure definition - */ -typedef struct -{ - uint32_t AdvFeatureInit; /*!< Specifies which advanced UART features is initialized. Several - Advanced Features may be initialized at the same time . - This parameter can be a value of - @ref UART_Advanced_Features_Initialization_Type. */ - - uint32_t TxPinLevelInvert; /*!< Specifies whether the TX pin active level is inverted. - This parameter can be a value of @ref UART_Tx_Inv. */ - - uint32_t RxPinLevelInvert; /*!< Specifies whether the RX pin active level is inverted. - This parameter can be a value of @ref UART_Rx_Inv. */ - - uint32_t DataInvert; /*!< Specifies whether data are inverted (positive/direct logic - vs negative/inverted logic). - This parameter can be a value of @ref UART_Data_Inv. */ - - uint32_t Swap; /*!< Specifies whether TX and RX pins are swapped. - This parameter can be a value of @ref UART_Rx_Tx_Swap. */ - - uint32_t OverrunDisable; /*!< Specifies whether the reception overrun detection is disabled. - This parameter can be a value of @ref UART_Overrun_Disable. */ - -#if defined(HAL_DMA_MODULE_ENABLED) - uint32_t DMADisableonRxError; /*!< Specifies whether the DMA is disabled in case of reception error. - This parameter can be a value of @ref UART_DMA_Disable_on_Rx_Error. */ - -#endif /* HAL_DMA_MODULE_ENABLED */ - uint32_t AutoBaudRateEnable; /*!< Specifies whether auto Baud rate detection is enabled. - This parameter can be a value of @ref UART_AutoBaudRate_Enable. */ - - uint32_t AutoBaudRateMode; /*!< If auto Baud rate detection is enabled, specifies how the rate - detection is carried out. - This parameter can be a value of @ref UART_AutoBaud_Rate_Mode. */ - - uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. - This parameter can be a value of @ref UART_MSB_First. */ -} UART_AdvFeatureInitTypeDef; - -/** - * @brief HAL UART State definition - * @note HAL UART State value is a combination of 2 different substates: - * gState and RxState (see @ref UART_State_Definition). - * - gState contains UART state information related to global Handle management - * and also information related to Tx operations. - * gState value coding follow below described bitmap : - * b7-b6 Error information - * 00 : No Error - * 01 : (Not Used) - * 10 : Timeout - * 11 : Error - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized. HAL UART Init function already called) - * b4-b3 (not used) - * xx : Should be set to 00 - * b2 Intrinsic process state - * 0 : Ready - * 1 : Busy (Peripheral busy with some configuration or internal operations) - * b1 (not used) - * x : Should be set to 0 - * b0 Tx state - * 0 : Ready (no Tx operation ongoing) - * 1 : Busy (Tx operation ongoing) - * - RxState contains information related to Rx operations. - * RxState value coding follow below described bitmap : - * b7-b6 (not used) - * xx : Should be set to 00 - * b5 Peripheral initialization status - * 0 : Reset (Peripheral not initialized) - * 1 : Init done (Peripheral initialized) - * b4-b2 (not used) - * xxx : Should be set to 000 - * b1 Rx state - * 0 : Ready (no Rx operation ongoing) - * 1 : Busy (Rx operation ongoing) - * b0 (not used) - * x : Should be set to 0. - */ -typedef uint32_t HAL_UART_StateTypeDef; - -/** - * @brief HAL UART Reception type definition - * @note HAL UART Reception type value aims to identify which type of Reception is ongoing. - * This parameter can be a value of @ref UART_Reception_Type_Values : - * HAL_UART_RECEPTION_STANDARD = 0x00U, - * HAL_UART_RECEPTION_TOIDLE = 0x01U, - * HAL_UART_RECEPTION_TORTO = 0x02U, - * HAL_UART_RECEPTION_TOCHARMATCH = 0x03U, - */ -typedef uint32_t HAL_UART_RxTypeTypeDef; - -/** - * @brief HAL UART Rx Event type definition - * @note HAL UART Rx Event type value aims to identify which type of Event has occurred - * leading to call of the RxEvent callback. - * This parameter can be a value of @ref UART_RxEvent_Type_Values : - * HAL_UART_RXEVENT_TC = 0x00U, - * HAL_UART_RXEVENT_HT = 0x01U, - * HAL_UART_RXEVENT_IDLE = 0x02U, - */ -typedef uint32_t HAL_UART_RxEventTypeTypeDef; - -/** - * @brief UART handle Structure definition - */ -typedef struct __UART_HandleTypeDef -{ - USART_TypeDef *Instance; /*!< UART registers base address */ - - UART_InitTypeDef Init; /*!< UART communication parameters */ - - UART_AdvFeatureInitTypeDef AdvancedInit; /*!< UART Advanced Features initialization parameters */ - - const uint8_t *pTxBuffPtr; /*!< Pointer to UART Tx transfer Buffer */ - - uint16_t TxXferSize; /*!< UART Tx Transfer size */ - - __IO uint16_t TxXferCount; /*!< UART Tx Transfer Counter */ - - uint8_t *pRxBuffPtr; /*!< Pointer to UART Rx transfer Buffer */ - - uint16_t RxXferSize; /*!< UART Rx Transfer size */ - - __IO uint16_t RxXferCount; /*!< UART Rx Transfer Counter */ - - uint16_t Mask; /*!< UART Rx RDR register mask */ - - uint32_t FifoMode; /*!< Specifies if the FIFO mode is being used. - This parameter can be a value of @ref UARTEx_FIFO_mode. */ - - uint16_t NbRxDataToProcess; /*!< Number of data to process during RX ISR execution */ - - uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - - __IO HAL_UART_RxTypeTypeDef ReceptionType; /*!< Type of ongoing reception */ - - __IO HAL_UART_RxEventTypeTypeDef RxEventType; /*!< Type of Rx Event */ - - void (*RxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ - - void (*TxISR)(struct __UART_HandleTypeDef *huart); /*!< Function pointer on Tx IRQ handler */ - -#if defined(HAL_DMA_MODULE_ENABLED) - DMA_HandleTypeDef *hdmatx; /*!< UART Tx DMA Handle parameters */ - - DMA_HandleTypeDef *hdmarx; /*!< UART Rx DMA Handle parameters */ - -#endif /* HAL_DMA_MODULE_ENABLED */ - HAL_LockTypeDef Lock; /*!< Locking object */ - - __IO HAL_UART_StateTypeDef gState; /*!< UART state information related to global Handle management - and also related to Tx operations. This parameter - can be a value of @ref HAL_UART_StateTypeDef */ - - __IO HAL_UART_StateTypeDef RxState; /*!< UART state information related to Rx operations. This - parameter can be a value of @ref HAL_UART_StateTypeDef */ - - __IO uint32_t ErrorCode; /*!< UART Error code */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - void (* TxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Half Complete Callback */ - void (* TxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Complete Callback */ - void (* RxHalfCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Half Complete Callback */ - void (* RxCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Complete Callback */ - void (* ErrorCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Error Callback */ - void (* AbortCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Complete Callback */ - void (* AbortTransmitCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Transmit Complete Callback */ - void (* AbortReceiveCpltCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Abort Receive Complete Callback */ - void (* RxFifoFullCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Rx Fifo Full Callback */ - void (* TxFifoEmptyCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Tx Fifo Empty Callback */ - void (* RxEventCallback)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< UART Reception Event Callback */ - - void (* MspInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp Init callback */ - void (* MspDeInitCallback)(struct __UART_HandleTypeDef *huart); /*!< UART Msp DeInit callback */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -} UART_HandleTypeDef; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief HAL UART Callback ID enumeration definition - */ -typedef enum -{ - HAL_UART_TX_HALFCOMPLETE_CB_ID = 0x00U, /*!< UART Tx Half Complete Callback ID */ - HAL_UART_TX_COMPLETE_CB_ID = 0x01U, /*!< UART Tx Complete Callback ID */ - HAL_UART_RX_HALFCOMPLETE_CB_ID = 0x02U, /*!< UART Rx Half Complete Callback ID */ - HAL_UART_RX_COMPLETE_CB_ID = 0x03U, /*!< UART Rx Complete Callback ID */ - HAL_UART_ERROR_CB_ID = 0x04U, /*!< UART Error Callback ID */ - HAL_UART_ABORT_COMPLETE_CB_ID = 0x05U, /*!< UART Abort Complete Callback ID */ - HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID = 0x06U, /*!< UART Abort Transmit Complete Callback ID */ - HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID = 0x07U, /*!< UART Abort Receive Complete Callback ID */ - HAL_UART_WAKEUP_CB_ID = 0x08U, /*!< UART Wakeup Callback ID */ - HAL_UART_RX_FIFO_FULL_CB_ID = 0x09U, /*!< UART Rx Fifo Full Callback ID */ - HAL_UART_TX_FIFO_EMPTY_CB_ID = 0x0AU, /*!< UART Tx Fifo Empty Callback ID */ - - HAL_UART_MSPINIT_CB_ID = 0x0BU, /*!< UART MspInit callback ID */ - HAL_UART_MSPDEINIT_CB_ID = 0x0CU /*!< UART MspDeInit callback ID */ - -} HAL_UART_CallbackIDTypeDef; - -/** - * @brief HAL UART Callback pointer definition - */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef) -(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UART_Exported_Constants UART Exported Constants - * @{ - */ - -/** @defgroup UART_State_Definition UART State Code Definition - * @{ - */ -#define HAL_UART_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_UART_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ -#define HAL_UART_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ -#define HAL_UART_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ -#define HAL_UART_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing - Value is allowed for RxState only */ -#define HAL_UART_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState.Value is result - of combination (Or) between gState and RxState values */ -#define HAL_UART_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ -#define HAL_UART_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ -/** - * @} - */ - -/** @defgroup UART_Error_Definition UART Error Definition - * @{ - */ -#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ -#if defined(HAL_DMA_MODULE_ENABLED) -#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ -#endif /* HAL_DMA_MODULE_ENABLED */ -#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup UART_Stop_Bits UART Number of Stop Bits - * @{ - */ -#define UART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< UART frame with 0.5 stop bit */ -#define UART_STOPBITS_1 0x00000000U /*!< UART frame with 1 stop bit */ -#define UART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< UART frame with 1.5 stop bits */ -#define UART_STOPBITS_2 USART_CR2_STOP_1 /*!< UART frame with 2 stop bits */ -/** - * @} - */ - -/** @defgroup UART_Parity UART Parity - * @{ - */ -#define UART_PARITY_NONE 0x00000000U /*!< No parity */ -#define UART_PARITY_EVEN USART_CR1_PCE /*!< Even parity */ -#define UART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Odd parity */ -/** - * @} - */ - -/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control - * @{ - */ -#define UART_HWCONTROL_NONE 0x00000000U /*!< No hardware control */ -#define UART_HWCONTROL_RTS USART_CR3_RTSE /*!< Request To Send */ -#define UART_HWCONTROL_CTS USART_CR3_CTSE /*!< Clear To Send */ -#define UART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< Request and Clear To Send */ -/** - * @} - */ - -/** @defgroup UART_Mode UART Transfer Mode - * @{ - */ -#define UART_MODE_RX USART_CR1_RE /*!< RX mode */ -#define UART_MODE_TX USART_CR1_TE /*!< TX mode */ -#define UART_MODE_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< RX and TX mode */ -/** - * @} - */ - -/** @defgroup UART_State UART State - * @{ - */ -#define UART_STATE_DISABLE 0x00000000U /*!< UART disabled */ -#define UART_STATE_ENABLE USART_CR1_UE /*!< UART enabled */ -/** - * @} - */ - -/** @defgroup UART_Over_Sampling UART Over Sampling - * @{ - */ -#define UART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define UART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -/** @defgroup UART_OneBit_Sampling UART One Bit Sampling Method - * @{ - */ -#define UART_ONE_BIT_SAMPLE_DISABLE 0x00000000U /*!< One-bit sampling disable */ -#define UART_ONE_BIT_SAMPLE_ENABLE USART_CR3_ONEBIT /*!< One-bit sampling enable */ -/** - * @} - */ - -/** @defgroup UART_ClockPrescaler UART Clock Prescaler - * @{ - */ -#define UART_PRESCALER_DIV1 0x00000000U /*!< fclk_pres = fclk */ -#define UART_PRESCALER_DIV2 0x00000001U /*!< fclk_pres = fclk/2 */ -#define UART_PRESCALER_DIV4 0x00000002U /*!< fclk_pres = fclk/4 */ -#define UART_PRESCALER_DIV6 0x00000003U /*!< fclk_pres = fclk/6 */ -#define UART_PRESCALER_DIV8 0x00000004U /*!< fclk_pres = fclk/8 */ -#define UART_PRESCALER_DIV10 0x00000005U /*!< fclk_pres = fclk/10 */ -#define UART_PRESCALER_DIV12 0x00000006U /*!< fclk_pres = fclk/12 */ -#define UART_PRESCALER_DIV16 0x00000007U /*!< fclk_pres = fclk/16 */ -#define UART_PRESCALER_DIV32 0x00000008U /*!< fclk_pres = fclk/32 */ -#define UART_PRESCALER_DIV64 0x00000009U /*!< fclk_pres = fclk/64 */ -#define UART_PRESCALER_DIV128 0x0000000AU /*!< fclk_pres = fclk/128 */ -#define UART_PRESCALER_DIV256 0x0000000BU /*!< fclk_pres = fclk/256 */ -/** - * @} - */ - -/** @defgroup UART_AutoBaud_Rate_Mode UART Advanced Feature AutoBaud Rate Mode - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection - on start bit */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE USART_CR2_ABRMODE_0 /*!< Auto Baud rate detection - on falling edge */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME USART_CR2_ABRMODE_1 /*!< Auto Baud rate detection - on 0x7F frame detection */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME USART_CR2_ABRMODE /*!< Auto Baud rate detection - on 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup UART_Receiver_Timeout UART Receiver Timeout - * @{ - */ -#define UART_RECEIVER_TIMEOUT_DISABLE 0x00000000U /*!< UART Receiver Timeout disable */ -#define UART_RECEIVER_TIMEOUT_ENABLE USART_CR2_RTOEN /*!< UART Receiver Timeout enable */ -/** - * @} - */ - -/** @defgroup UART_LIN UART Local Interconnection Network mode - * @{ - */ -#define UART_LIN_DISABLE 0x00000000U /*!< Local Interconnect Network disable */ -#define UART_LIN_ENABLE USART_CR2_LINEN /*!< Local Interconnect Network enable */ -/** - * @} - */ - -/** @defgroup UART_LIN_Break_Detection UART LIN Break Detection - * @{ - */ -#define UART_LINBREAKDETECTLENGTH_10B 0x00000000U /*!< LIN 10-bit break detection length */ -#define UART_LINBREAKDETECTLENGTH_11B USART_CR2_LBDL /*!< LIN 11-bit break detection length */ -/** - * @} - */ - -#if defined(HAL_DMA_MODULE_ENABLED) -/** @defgroup UART_DMA_Tx UART DMA Tx - * @{ - */ -#define UART_DMA_TX_DISABLE 0x00000000U /*!< UART DMA TX disabled */ -#define UART_DMA_TX_ENABLE USART_CR3_DMAT /*!< UART DMA TX enabled */ -/** - * @} - */ - -/** @defgroup UART_DMA_Rx UART DMA Rx - * @{ - */ -#define UART_DMA_RX_DISABLE 0x00000000U /*!< UART DMA RX disabled */ -#define UART_DMA_RX_ENABLE USART_CR3_DMAR /*!< UART DMA RX enabled */ -/** - * @} - */ -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** @defgroup UART_Half_Duplex_Selection UART Half Duplex Selection - * @{ - */ -#define UART_HALF_DUPLEX_DISABLE 0x00000000U /*!< UART half-duplex disabled */ -#define UART_HALF_DUPLEX_ENABLE USART_CR3_HDSEL /*!< UART half-duplex enabled */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_Methods UART WakeUp Methods - * @{ - */ -#define UART_WAKEUPMETHOD_IDLELINE 0x00000000U /*!< UART wake-up on idle line */ -#define UART_WAKEUPMETHOD_ADDRESSMARK USART_CR1_WAKE /*!< UART wake-up on address mark */ -/** - * @} - */ - -/** @defgroup UART_Request_Parameters UART Request Parameters - * @{ - */ -#define UART_AUTOBAUD_REQUEST USART_RQR_ABRRQ /*!< Auto-Baud Rate Request */ -#define UART_SENDBREAK_REQUEST USART_RQR_SBKRQ /*!< Send Break Request */ -#define UART_MUTE_MODE_REQUEST USART_RQR_MMRQ /*!< Mute Mode Request */ -#define UART_RXDATA_FLUSH_REQUEST USART_RQR_RXFRQ /*!< Receive Data flush Request */ -#define UART_TXDATA_FLUSH_REQUEST USART_RQR_TXFRQ /*!< Transmit data flush Request */ -/** - * @} - */ - -/** @defgroup UART_Advanced_Features_Initialization_Type UART Advanced Feature Initialization Type - * @{ - */ -#define UART_ADVFEATURE_NO_INIT 0x00000000U /*!< No advanced feature initialization */ -#define UART_ADVFEATURE_TXINVERT_INIT 0x00000001U /*!< TX pin active level inversion */ -#define UART_ADVFEATURE_RXINVERT_INIT 0x00000002U /*!< RX pin active level inversion */ -#define UART_ADVFEATURE_DATAINVERT_INIT 0x00000004U /*!< Binary data inversion */ -#define UART_ADVFEATURE_SWAP_INIT 0x00000008U /*!< TX/RX pins swap */ -#define UART_ADVFEATURE_RXOVERRUNDISABLE_INIT 0x00000010U /*!< RX overrun disable */ -#if defined(HAL_DMA_MODULE_ENABLED) -#define UART_ADVFEATURE_DMADISABLEONERROR_INIT 0x00000020U /*!< DMA disable on Reception Error */ -#endif /* HAL_DMA_MODULE_ENABLED */ -#define UART_ADVFEATURE_AUTOBAUDRATE_INIT 0x00000040U /*!< Auto Baud rate detection initialization */ -#define UART_ADVFEATURE_MSBFIRST_INIT 0x00000080U /*!< Most significant bit sent/received first */ -/** - * @} - */ - -/** @defgroup UART_Tx_Inv UART Advanced Feature TX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_TXINV_DISABLE 0x00000000U /*!< TX pin active level inversion disable */ -#define UART_ADVFEATURE_TXINV_ENABLE USART_CR2_TXINV /*!< TX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Inv UART Advanced Feature RX Pin Active Level Inversion - * @{ - */ -#define UART_ADVFEATURE_RXINV_DISABLE 0x00000000U /*!< RX pin active level inversion disable */ -#define UART_ADVFEATURE_RXINV_ENABLE USART_CR2_RXINV /*!< RX pin active level inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Data_Inv UART Advanced Feature Binary Data Inversion - * @{ - */ -#define UART_ADVFEATURE_DATAINV_DISABLE 0x00000000U /*!< Binary data inversion disable */ -#define UART_ADVFEATURE_DATAINV_ENABLE USART_CR2_DATAINV /*!< Binary data inversion enable */ -/** - * @} - */ - -/** @defgroup UART_Rx_Tx_Swap UART Advanced Feature RX TX Pins Swap - * @{ - */ -#define UART_ADVFEATURE_SWAP_DISABLE 0x00000000U /*!< TX/RX pins swap disable */ -#define UART_ADVFEATURE_SWAP_ENABLE USART_CR2_SWAP /*!< TX/RX pins swap enable */ -/** - * @} - */ - -/** @defgroup UART_Overrun_Disable UART Advanced Feature Overrun Disable - * @{ - */ -#define UART_ADVFEATURE_OVERRUN_ENABLE 0x00000000U /*!< RX overrun enable */ -#define UART_ADVFEATURE_OVERRUN_DISABLE USART_CR3_OVRDIS /*!< RX overrun disable */ -/** - * @} - */ - -/** @defgroup UART_AutoBaudRate_Enable UART Advanced Feature Auto BaudRate Enable - * @{ - */ -#define UART_ADVFEATURE_AUTOBAUDRATE_DISABLE 0x00000000U /*!< RX Auto Baud rate detection enable */ -#define UART_ADVFEATURE_AUTOBAUDRATE_ENABLE USART_CR2_ABREN /*!< RX Auto Baud rate detection disable */ -/** - * @} - */ - -#if defined(HAL_DMA_MODULE_ENABLED) -/** @defgroup UART_DMA_Disable_on_Rx_Error UART Advanced Feature DMA Disable On Rx Error - * @{ - */ -#define UART_ADVFEATURE_DMA_ENABLEONRXERROR 0x00000000U /*!< DMA enable on Reception Error */ -#define UART_ADVFEATURE_DMA_DISABLEONRXERROR USART_CR3_DDRE /*!< DMA disable on Reception Error */ -/** - * @} - */ -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** @defgroup UART_MSB_First UART Advanced Feature MSB First - * @{ - */ -#define UART_ADVFEATURE_MSBFIRST_DISABLE 0x00000000U /*!< Most significant bit sent/received - first disable */ -#define UART_ADVFEATURE_MSBFIRST_ENABLE USART_CR2_MSBFIRST /*!< Most significant bit sent/received - first enable */ -/** - * @} - */ - -/** @defgroup UART_Stop_Mode_Enable UART Advanced Feature Stop Mode Enable - * @{ - */ -#define UART_ADVFEATURE_STOPMODE_DISABLE 0x00000000U /*!< UART stop mode disable */ -#define UART_ADVFEATURE_STOPMODE_ENABLE USART_CR1_UESM /*!< UART stop mode enable */ -/** - * @} - */ - -/** @defgroup UART_Mute_Mode UART Advanced Feature Mute Mode Enable - * @{ - */ -#define UART_ADVFEATURE_MUTEMODE_DISABLE 0x00000000U /*!< UART mute mode disable */ -#define UART_ADVFEATURE_MUTEMODE_ENABLE USART_CR1_MME /*!< UART mute mode enable */ -/** - * @} - */ - -/** @defgroup UART_CR2_ADDRESS_LSB_POS UART Address-matching LSB Position In CR2 Register - * @{ - */ -#define UART_CR2_ADDRESS_LSB_POS 24U /*!< UART address-matching LSB position in CR2 register */ -/** - * @} - */ - -/** @defgroup UART_WakeUp_from_Stop_Selection UART WakeUp From Stop Selection - * @{ - */ -#define UART_WAKEUP_ON_ADDRESS 0x00000000U /*!< UART wake-up on address */ -#define UART_WAKEUP_ON_READDATA_NONEMPTY 0x00000001U /*!< UART wake-up on receive data register - not empty or RXFIFO is not empty */ -/** - * @} - */ - -/** @defgroup UART_DriverEnable_Polarity UART DriverEnable Polarity - * @{ - */ -#define UART_DE_POLARITY_HIGH 0x00000000U /*!< Driver enable signal is active high */ -#define UART_DE_POLARITY_LOW USART_CR3_DEP /*!< Driver enable signal is active low */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEAT_ADDRESS_LSB_POS UART Driver Enable Assertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEAT_ADDRESS_LSB_POS 21U /*!< UART Driver Enable assertion time LSB - position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_CR1_DEDT_ADDRESS_LSB_POS UART Driver Enable DeAssertion Time LSB Position In CR1 Register - * @{ - */ -#define UART_CR1_DEDT_ADDRESS_LSB_POS 16U /*!< UART Driver Enable de-assertion time LSB - position in CR1 register */ -/** - * @} - */ - -/** @defgroup UART_Interruption_Mask UART Interruptions Flag Mask - * @{ - */ -#define UART_IT_MASK 0x001FU /*!< UART interruptions flags mask */ -/** - * @} - */ - -/** @defgroup UART_TimeOut_Value UART polling-based communications time-out value - * @{ - */ -#define HAL_UART_TIMEOUT_VALUE 0x1FFFFFFU /*!< UART polling-based communications time-out value */ -/** - * @} - */ - -/** @defgroup UART_Flags UART Status Flags - * Elements values convention: 0xXXXX - * - 0xXXXX : Flag mask in the ISR register - * @{ - */ -#define UART_FLAG_TXFT USART_ISR_TXFT /*!< UART TXFIFO threshold flag */ -#define UART_FLAG_RXFT USART_ISR_RXFT /*!< UART RXFIFO threshold flag */ -#define UART_FLAG_RXFF USART_ISR_RXFF /*!< UART RXFIFO Full flag */ -#define UART_FLAG_TXFE USART_ISR_TXFE /*!< UART TXFIFO Empty flag */ -#define UART_FLAG_REACK USART_ISR_REACK /*!< UART receive enable acknowledge flag */ -#define UART_FLAG_TEACK USART_ISR_TEACK /*!< UART transmit enable acknowledge flag */ -#define UART_FLAG_RWU USART_ISR_RWU /*!< UART receiver wake-up from mute mode flag */ -#define UART_FLAG_SBKF USART_ISR_SBKF /*!< UART send break flag */ -#define UART_FLAG_CMF USART_ISR_CMF /*!< UART character match flag */ -#define UART_FLAG_BUSY USART_ISR_BUSY /*!< UART busy flag */ -#define UART_FLAG_ABRF USART_ISR_ABRF /*!< UART auto Baud rate flag */ -#define UART_FLAG_ABRE USART_ISR_ABRE /*!< UART auto Baud rate error */ -#define UART_FLAG_RTOF USART_ISR_RTOF /*!< UART receiver timeout flag */ -#define UART_FLAG_CTS USART_ISR_CTS /*!< UART clear to send flag */ -#define UART_FLAG_CTSIF USART_ISR_CTSIF /*!< UART clear to send interrupt flag */ -#define UART_FLAG_LBDF USART_ISR_LBDF /*!< UART LIN break detection flag */ -#define UART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< UART transmit data register empty */ -#define UART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< UART TXFIFO not full */ -#define UART_FLAG_TC USART_ISR_TC /*!< UART transmission complete */ -#define UART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< UART read data register not empty */ -#define UART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< UART RXFIFO not empty */ -#define UART_FLAG_IDLE USART_ISR_IDLE /*!< UART idle flag */ -#define UART_FLAG_ORE USART_ISR_ORE /*!< UART overrun error */ -#define UART_FLAG_NE USART_ISR_NE /*!< UART noise error */ -#define UART_FLAG_FE USART_ISR_FE /*!< UART frame error */ -#define UART_FLAG_PE USART_ISR_PE /*!< UART parity error */ -/** - * @} - */ - -/** @defgroup UART_Interrupt_definition UART Interrupts Definition - * Elements values convention: 000ZZZZZ0XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * - ZZZZZ : Flag position in the ISR register(5bits) - * Elements values convention: 000000000XXYYYYYb - * - YYYYY : Interrupt source position in the XX register (5bits) - * - XX : Interrupt source register (2bits) - * - 01: CR1 register - * - 10: CR2 register - * - 11: CR3 register - * Elements values convention: 0000ZZZZ00000000b - * - ZZZZ : Flag position in the ISR register(4bits) - * @{ - */ -#define UART_IT_PE 0x0028U /*!< UART parity error interruption */ -#define UART_IT_TXE 0x0727U /*!< UART transmit data register empty interruption */ -#define UART_IT_TXFNF 0x0727U /*!< UART TX FIFO not full interruption */ -#define UART_IT_TC 0x0626U /*!< UART transmission complete interruption */ -#define UART_IT_RXNE 0x0525U /*!< UART read data register not empty interruption */ -#define UART_IT_RXFNE 0x0525U /*!< UART RXFIFO not empty interruption */ -#define UART_IT_IDLE 0x0424U /*!< UART idle interruption */ -#define UART_IT_LBD 0x0846U /*!< UART LIN break detection interruption */ -#define UART_IT_CTS 0x096AU /*!< UART CTS interruption */ -#define UART_IT_CM 0x112EU /*!< UART character match interruption */ -#define UART_IT_RXFF 0x183FU /*!< UART RXFIFO full interruption */ -#define UART_IT_TXFE 0x173EU /*!< UART TXFIFO empty interruption */ -#define UART_IT_RXFT 0x1A7CU /*!< UART RXFIFO threshold reached interruption */ -#define UART_IT_TXFT 0x1B77U /*!< UART TXFIFO threshold reached interruption */ -#define UART_IT_RTO 0x0B3AU /*!< UART receiver timeout interruption */ - -#define UART_IT_ERR 0x0060U /*!< UART error interruption */ - -#define UART_IT_ORE 0x0300U /*!< UART overrun error interruption */ -#define UART_IT_NE 0x0200U /*!< UART noise error interruption */ -#define UART_IT_FE 0x0100U /*!< UART frame error interruption */ -/** - * @} - */ - -/** @defgroup UART_IT_CLEAR_Flags UART Interruption Clear Flags - * @{ - */ -#define UART_CLEAR_PEF USART_ICR_PECF /*!< Parity Error Clear Flag */ -#define UART_CLEAR_FEF USART_ICR_FECF /*!< Framing Error Clear Flag */ -#define UART_CLEAR_NEF USART_ICR_NECF /*!< Noise Error detected Clear Flag */ -#define UART_CLEAR_OREF USART_ICR_ORECF /*!< Overrun Error Clear Flag */ -#define UART_CLEAR_IDLEF USART_ICR_IDLECF /*!< IDLE line detected Clear Flag */ -#define UART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO empty clear flag */ -#define UART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ -#define UART_CLEAR_LBDF USART_ICR_LBDCF /*!< LIN Break Detection Clear Flag */ -#define UART_CLEAR_CTSF USART_ICR_CTSCF /*!< CTS Interrupt Clear Flag */ -#define UART_CLEAR_CMF USART_ICR_CMCF /*!< Character Match Clear Flag */ -#define UART_CLEAR_RTOF USART_ICR_RTOCF /*!< UART receiver timeout clear flag */ -/** - * @} - */ - -/** @defgroup UART_Reception_Type_Values UART Reception type values - * @{ - */ -#define HAL_UART_RECEPTION_STANDARD (0x00000000U) /*!< Standard reception */ -#define HAL_UART_RECEPTION_TOIDLE (0x00000001U) /*!< Reception till completion or IDLE event */ -#define HAL_UART_RECEPTION_TORTO (0x00000002U) /*!< Reception till completion or RTO event */ -#define HAL_UART_RECEPTION_TOCHARMATCH (0x00000003U) /*!< Reception till completion or CM event */ -/** - * @} - */ - -/** @defgroup UART_RxEvent_Type_Values UART RxEvent type values - * @{ - */ -#define HAL_UART_RXEVENT_TC (0x00000000U) /*!< RxEvent linked to Transfer Complete event */ -#define HAL_UART_RXEVENT_HT (0x00000001U) /*!< RxEvent linked to Half Transfer event */ -#define HAL_UART_RXEVENT_IDLE (0x00000002U) /*!< RxEvent linked to IDLE event */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/** @defgroup UART_Exported_Macros UART Exported Macros - * @{ - */ - -/** @brief Reset UART handle states. - * @param __HANDLE__ UART handle. - * @retval None - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0U) -#else -#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->gState = HAL_UART_STATE_RESET; \ - (__HANDLE__)->RxState = HAL_UART_STATE_RESET; \ - } while(0U) -#endif /*USE_HAL_UART_REGISTER_CALLBACKS */ - -/** @brief Flush the UART Data registers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \ - do{ \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_RXDATA_FLUSH_REQUEST); \ - SET_BIT((__HANDLE__)->Instance->RQR, UART_TXDATA_FLUSH_REQUEST); \ - } while(0U) - -/** @brief Clear the specified UART pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be any combination of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver Timeout clear flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) - -/** @brief Clear the UART PE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_PEF) - -/** @brief Clear the UART FE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_FEF) - -/** @brief Clear the UART NE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_NEF) - -/** @brief Clear the UART ORE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_OREF) - -/** @brief Clear the UART IDLE pending flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_IDLEF) - -/** @brief Clear the UART TX FIFO empty clear flag. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_CLEAR_TXFECF(__HANDLE__) __HAL_UART_CLEAR_FLAG((__HANDLE__), UART_CLEAR_TXFECF) - -/** @brief Check whether the specified UART flag is set or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __FLAG__ specifies the flag to check. - * This parameter can be one of the following values: - * @arg @ref UART_FLAG_TXFT TXFIFO threshold flag - * @arg @ref UART_FLAG_RXFT RXFIFO threshold flag - * @arg @ref UART_FLAG_RXFF RXFIFO Full flag - * @arg @ref UART_FLAG_TXFE TXFIFO Empty flag - * @arg @ref UART_FLAG_REACK Receive enable acknowledge flag - * @arg @ref UART_FLAG_TEACK Transmit enable acknowledge flag - * @arg @ref UART_FLAG_RWU Receiver wake up flag (if the UART in mute mode) - * @arg @ref UART_FLAG_SBKF Send Break flag - * @arg @ref UART_FLAG_CMF Character match flag - * @arg @ref UART_FLAG_BUSY Busy flag - * @arg @ref UART_FLAG_ABRF Auto Baud rate detection flag - * @arg @ref UART_FLAG_ABRE Auto Baud rate detection error flag - * @arg @ref UART_FLAG_CTS CTS Change flag - * @arg @ref UART_FLAG_LBDF LIN Break detection flag - * @arg @ref UART_FLAG_TXE Transmit data register empty flag - * @arg @ref UART_FLAG_TXFNF UART TXFIFO not full flag - * @arg @ref UART_FLAG_TC Transmission Complete flag - * @arg @ref UART_FLAG_RXNE Receive data register not empty flag - * @arg @ref UART_FLAG_RXFNE UART RXFIFO not empty flag - * @arg @ref UART_FLAG_RTOF Receiver Timeout flag - * @arg @ref UART_FLAG_IDLE Idle Line detection flag - * @arg @ref UART_FLAG_ORE Overrun Error flag - * @arg @ref UART_FLAG_NE Noise Error flag - * @arg @ref UART_FLAG_FE Framing Error flag - * @arg @ref UART_FLAG_PE Parity Error flag - * @retval The new state of __FLAG__ (TRUE or FALSE). - */ -#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__)) - -/** @brief Enable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to enable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (\ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Disable the specified UART interrupt. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to disable. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval None - */ -#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (\ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ - ((__INTERRUPT__) & UART_IT_MASK)))) - -/** @brief Check whether the specified UART interrupt has occurred or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (1U << ((__INTERRUPT__)>> 8U))) != RESET) ? SET : RESET) - -/** @brief Check whether the specified UART interrupt source is enabled or not. - * @param __HANDLE__ specifies the UART Handle. - * @param __INTERRUPT__ specifies the UART interrupt source to check. - * This parameter can be one of the following values: - * @arg @ref UART_IT_RXFF RXFIFO Full interrupt - * @arg @ref UART_IT_TXFE TXFIFO Empty interrupt - * @arg @ref UART_IT_RXFT RXFIFO threshold interrupt - * @arg @ref UART_IT_TXFT TXFIFO threshold interrupt - * @arg @ref UART_IT_CM Character match interrupt - * @arg @ref UART_IT_CTS CTS change interrupt - * @arg @ref UART_IT_LBD LIN Break detection interrupt - * @arg @ref UART_IT_TXE Transmit Data Register empty interrupt - * @arg @ref UART_IT_TXFNF TX FIFO not full interrupt - * @arg @ref UART_IT_TC Transmission complete interrupt - * @arg @ref UART_IT_RXNE Receive Data register not empty interrupt - * @arg @ref UART_IT_RXFNE RXFIFO not empty interrupt - * @arg @ref UART_IT_RTO Receive Timeout interrupt - * @arg @ref UART_IT_IDLE Idle line detection interrupt - * @arg @ref UART_IT_PE Parity Error interrupt - * @arg @ref UART_IT_ERR Error interrupt (Frame error, noise error, overrun error) - * @retval The new state of __INTERRUPT__ (SET or RESET). - */ -#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 5U) == 1U) ?\ - (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U) ?\ - (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (1U <<\ - (((uint16_t)(__INTERRUPT__)) &\ - UART_IT_MASK))) != RESET) ? SET : RESET) - -/** @brief Clear the specified UART ISR flag, in setting the proper ICR register flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set - * to clear the corresponding interrupt - * This parameter can be one of the following values: - * @arg @ref UART_CLEAR_PEF Parity Error Clear Flag - * @arg @ref UART_CLEAR_FEF Framing Error Clear Flag - * @arg @ref UART_CLEAR_NEF Noise detected Clear Flag - * @arg @ref UART_CLEAR_OREF Overrun Error Clear Flag - * @arg @ref UART_CLEAR_IDLEF IDLE line detected Clear Flag - * @arg @ref UART_CLEAR_RTOF Receiver timeout clear flag - * @arg @ref UART_CLEAR_TXFECF TXFIFO empty Clear Flag - * @arg @ref UART_CLEAR_TCF Transmission Complete Clear Flag - * @arg @ref UART_CLEAR_LBDF LIN Break Detection Clear Flag - * @arg @ref UART_CLEAR_CTSF CTS Interrupt Clear Flag - * @arg @ref UART_CLEAR_CMF Character Match Clear Flag - * @retval None - */ -#define __HAL_UART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__)) - -/** @brief Set a specific UART request flag. - * @param __HANDLE__ specifies the UART Handle. - * @param __REQ__ specifies the request flag to set - * This parameter can be one of the following values: - * @arg @ref UART_AUTOBAUD_REQUEST Auto-Baud Rate Request - * @arg @ref UART_SENDBREAK_REQUEST Send Break Request - * @arg @ref UART_MUTE_MODE_REQUEST Mute Mode Request - * @arg @ref UART_RXDATA_FLUSH_REQUEST Receive Data flush Request - * @arg @ref UART_TXDATA_FLUSH_REQUEST Transmit data flush Request - * @retval None - */ -#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__)) - -/** @brief Enable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT) - -/** @brief Disable the UART one bit sample method. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= ~USART_CR3_ONEBIT) - -/** @brief Enable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE) - -/** @brief Disable UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE) - -/** @brief Enable CTS flow control. - * @note This macro allows to enable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_ENABLE(__HANDLE__) \ - do{ \ - ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_CTSE; \ - } while(0U) - -/** @brief Disable CTS flow control. - * @note This macro allows to disable CTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying CTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_CTS_DISABLE(__HANDLE__) \ - do{ \ - ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_CTSE); \ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_CTSE); \ - } while(0U) - -/** @brief Enable RTS flow control. - * @note This macro allows to enable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_ENABLE(__HANDLE__) \ - do{ \ - ATOMIC_SET_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE); \ - (__HANDLE__)->Init.HwFlowCtl |= USART_CR3_RTSE; \ - } while(0U) - -/** @brief Disable RTS flow control. - * @note This macro allows to disable RTS hardware flow control for a given UART instance, - * without need to call HAL_UART_Init() function. - * As involving direct access to UART registers, usage of this macro should be fully endorsed by user. - * @note As macro is expected to be used for modifying RTS Hw flow control feature activation, without need - * for USART instance Deinit/Init, following conditions for macro call should be fulfilled : - * - UART instance should have already been initialised (through call of HAL_UART_Init() ) - * - macro could only be called when corresponding UART instance is disabled - * (i.e. __HAL_UART_DISABLE(__HANDLE__)) and should be followed by an Enable - * macro (i.e. __HAL_UART_ENABLE(__HANDLE__)). - * @param __HANDLE__ specifies the UART Handle. - * @retval None - */ -#define __HAL_UART_HWCONTROL_RTS_DISABLE(__HANDLE__) \ - do{ \ - ATOMIC_CLEAR_BIT((__HANDLE__)->Instance->CR3, USART_CR3_RTSE);\ - (__HANDLE__)->Init.HwFlowCtl &= ~(USART_CR3_RTSE); \ - } while(0U) -/** - * @} - */ - -/* Private macros --------------------------------------------------------*/ -/** @defgroup UART_Private_Macros UART Private Macros - * @{ - */ -/** @brief Get UART clok division factor from clock prescaler value. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval UART clock division factor - */ -#define UART_GET_DIV_FACTOR(__CLOCKPRESCALER__) \ - (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) ? 1U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) ? 2U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) ? 4U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) ? 6U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) ? 8U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) ? 10U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) ? 12U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) - -/** @brief BRR division operation to set BRR register with LPUART. - * @param __PCLK__ LPUART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_LPUART(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ - ((uint32_t)((((((uint64_t)(__PCLK__))/(UARTPrescTable[(__CLOCKPRESCALER__)]))*256U)+ \ - (uint32_t)((__BAUD__)/2U)) / (__BAUD__)) \ - ) - -/** @brief BRR division operation to set BRR register in 8-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ - (((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)])*2U) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief BRR division operation to set BRR register in 16-bit oversampling mode. - * @param __PCLK__ UART clock. - * @param __BAUD__ Baud rate set by the user. - * @param __CLOCKPRESCALER__ UART prescaler value. - * @retval Division result - */ -#define UART_DIV_SAMPLING16(__PCLK__, __BAUD__, __CLOCKPRESCALER__) \ - ((((__PCLK__)/UARTPrescTable[(__CLOCKPRESCALER__)]) + ((__BAUD__)/2U)) / (__BAUD__)) - -/** @brief Check whether or not UART instance is Low Power UART. - * @param __HANDLE__ specifies the UART Handle. - * @retval SET (instance is LPUART) or RESET (instance isn't LPUART) - */ -#define UART_INSTANCE_LOWPOWER(__HANDLE__) (IS_LPUART_INSTANCE((__HANDLE__)->Instance)) - -/** @brief Check UART Baud rate. - * @param __BAUDRATE__ Baudrate specified by the user. - * The maximum Baud Rate is derived from the maximum clock on U5 (i.e. 160 MHz) - * divided by the smallest oversampling used on the USART (i.e. 8) - * @retval SET (__BAUDRATE__ is valid) or RESET (__BAUDRATE__ is invalid) - */ -#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 20000000U) - -/** @brief Check UART assertion time. - * @param __TIME__ 5-bit value assertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_ASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** @brief Check UART deassertion time. - * @param __TIME__ 5-bit value deassertion time. - * @retval Test result (TRUE or FALSE). - */ -#define IS_UART_DEASSERTIONTIME(__TIME__) ((__TIME__) <= 0x1FU) - -/** - * @brief Ensure that UART frame number of stop bits is valid. - * @param __STOPBITS__ UART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_UART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_0_5) || \ - ((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_1_5) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that LPUART frame number of stop bits is valid. - * @param __STOPBITS__ LPUART frame number of stop bits. - * @retval SET (__STOPBITS__ is valid) or RESET (__STOPBITS__ is invalid) - */ -#define IS_LPUART_STOPBITS(__STOPBITS__) (((__STOPBITS__) == UART_STOPBITS_1) || \ - ((__STOPBITS__) == UART_STOPBITS_2)) - -/** - * @brief Ensure that UART frame parity is valid. - * @param __PARITY__ UART frame parity. - * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid) - */ -#define IS_UART_PARITY(__PARITY__) (((__PARITY__) == UART_PARITY_NONE) || \ - ((__PARITY__) == UART_PARITY_EVEN) || \ - ((__PARITY__) == UART_PARITY_ODD)) - -/** - * @brief Ensure that UART hardware flow control is valid. - * @param __CONTROL__ UART hardware flow control. - * @retval SET (__CONTROL__ is valid) or RESET (__CONTROL__ is invalid) - */ -#define IS_UART_HARDWARE_FLOW_CONTROL(__CONTROL__)\ - (((__CONTROL__) == UART_HWCONTROL_NONE) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS) || \ - ((__CONTROL__) == UART_HWCONTROL_CTS) || \ - ((__CONTROL__) == UART_HWCONTROL_RTS_CTS)) - -/** - * @brief Ensure that UART communication mode is valid. - * @param __MODE__ UART communication mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(UART_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U)) - -/** - * @brief Ensure that UART state is valid. - * @param __STATE__ UART state. - * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid) - */ -#define IS_UART_STATE(__STATE__) (((__STATE__) == UART_STATE_DISABLE) || \ - ((__STATE__) == UART_STATE_ENABLE)) - -/** - * @brief Ensure that UART oversampling is valid. - * @param __SAMPLING__ UART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_UART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == UART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == UART_OVERSAMPLING_8)) - -/** - * @brief Ensure that UART frame sampling is valid. - * @param __ONEBIT__ UART frame sampling. - * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid) - */ -#define IS_UART_ONE_BIT_SAMPLE(__ONEBIT__) (((__ONEBIT__) == UART_ONE_BIT_SAMPLE_DISABLE) || \ - ((__ONEBIT__) == UART_ONE_BIT_SAMPLE_ENABLE)) - -/** - * @brief Ensure that UART auto Baud rate detection mode is valid. - * @param __MODE__ UART auto Baud rate detection mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(__MODE__) (((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONSTARTBIT) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ONFALLINGEDGE) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X7FFRAME) || \ - ((__MODE__) == UART_ADVFEATURE_AUTOBAUDRATE_ON0X55FRAME)) - -/** - * @brief Ensure that UART receiver timeout setting is valid. - * @param __TIMEOUT__ UART receiver timeout setting. - * @retval SET (__TIMEOUT__ is valid) or RESET (__TIMEOUT__ is invalid) - */ -#define IS_UART_RECEIVER_TIMEOUT(__TIMEOUT__) (((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_DISABLE) || \ - ((__TIMEOUT__) == UART_RECEIVER_TIMEOUT_ENABLE)) - -/** @brief Check the receiver timeout value. - * @note The maximum UART receiver timeout value is 0xFFFFFF. - * @param __TIMEOUTVALUE__ receiver timeout value. - * @retval Test result (TRUE or FALSE) - */ -#define IS_UART_RECEIVER_TIMEOUT_VALUE(__TIMEOUTVALUE__) ((__TIMEOUTVALUE__) <= 0xFFFFFFU) - -/** - * @brief Ensure that UART LIN state is valid. - * @param __LIN__ UART LIN state. - * @retval SET (__LIN__ is valid) or RESET (__LIN__ is invalid) - */ -#define IS_UART_LIN(__LIN__) (((__LIN__) == UART_LIN_DISABLE) || \ - ((__LIN__) == UART_LIN_ENABLE)) - -/** - * @brief Ensure that UART LIN break detection length is valid. - * @param __LENGTH__ UART LIN break detection length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_LIN_BREAK_DETECT_LENGTH(__LENGTH__) (((__LENGTH__) == UART_LINBREAKDETECTLENGTH_10B) || \ - ((__LENGTH__) == UART_LINBREAKDETECTLENGTH_11B)) - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Ensure that UART DMA TX state is valid. - * @param __DMATX__ UART DMA TX state. - * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid) - */ -#define IS_UART_DMA_TX(__DMATX__) (((__DMATX__) == UART_DMA_TX_DISABLE) || \ - ((__DMATX__) == UART_DMA_TX_ENABLE)) - -/** - * @brief Ensure that UART DMA RX state is valid. - * @param __DMARX__ UART DMA RX state. - * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid) - */ -#define IS_UART_DMA_RX(__DMARX__) (((__DMARX__) == UART_DMA_RX_DISABLE) || \ - ((__DMARX__) == UART_DMA_RX_ENABLE)) - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @brief Ensure that UART half-duplex state is valid. - * @param __HDSEL__ UART half-duplex state. - * @retval SET (__HDSEL__ is valid) or RESET (__HDSEL__ is invalid) - */ -#define IS_UART_HALF_DUPLEX(__HDSEL__) (((__HDSEL__) == UART_HALF_DUPLEX_DISABLE) || \ - ((__HDSEL__) == UART_HALF_DUPLEX_ENABLE)) - -/** - * @brief Ensure that UART wake-up method is valid. - * @param __WAKEUP__ UART wake-up method . - * @retval SET (__WAKEUP__ is valid) or RESET (__WAKEUP__ is invalid) - */ -#define IS_UART_WAKEUPMETHOD(__WAKEUP__) (((__WAKEUP__) == UART_WAKEUPMETHOD_IDLELINE) || \ - ((__WAKEUP__) == UART_WAKEUPMETHOD_ADDRESSMARK)) - -/** - * @brief Ensure that UART request parameter is valid. - * @param __PARAM__ UART request parameter. - * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid) - */ -#define IS_UART_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == UART_AUTOBAUD_REQUEST) || \ - ((__PARAM__) == UART_SENDBREAK_REQUEST) || \ - ((__PARAM__) == UART_MUTE_MODE_REQUEST) || \ - ((__PARAM__) == UART_RXDATA_FLUSH_REQUEST) || \ - ((__PARAM__) == UART_TXDATA_FLUSH_REQUEST)) - -/** - * @brief Ensure that UART advanced features initialization is valid. - * @param __INIT__ UART advanced features initialization. - * @retval SET (__INIT__ is valid) or RESET (__INIT__ is invalid) - */ -#if defined(HAL_DMA_MODULE_ENABLED) -#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_DMADISABLEONERROR_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) -#else -#define IS_UART_ADVFEATURE_INIT(__INIT__) ((__INIT__) <= (UART_ADVFEATURE_NO_INIT | \ - UART_ADVFEATURE_TXINVERT_INIT | \ - UART_ADVFEATURE_RXINVERT_INIT | \ - UART_ADVFEATURE_DATAINVERT_INIT | \ - UART_ADVFEATURE_SWAP_INIT | \ - UART_ADVFEATURE_RXOVERRUNDISABLE_INIT | \ - UART_ADVFEATURE_AUTOBAUDRATE_INIT | \ - UART_ADVFEATURE_MSBFIRST_INIT)) -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Ensure that UART frame TX inversion setting is valid. - * @param __TXINV__ UART frame TX inversion setting. - * @retval SET (__TXINV__ is valid) or RESET (__TXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_TXINV(__TXINV__) (((__TXINV__) == UART_ADVFEATURE_TXINV_DISABLE) || \ - ((__TXINV__) == UART_ADVFEATURE_TXINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX inversion setting is valid. - * @param __RXINV__ UART frame RX inversion setting. - * @retval SET (__RXINV__ is valid) or RESET (__RXINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_RXINV(__RXINV__) (((__RXINV__) == UART_ADVFEATURE_RXINV_DISABLE) || \ - ((__RXINV__) == UART_ADVFEATURE_RXINV_ENABLE)) - -/** - * @brief Ensure that UART frame data inversion setting is valid. - * @param __DATAINV__ UART frame data inversion setting. - * @retval SET (__DATAINV__ is valid) or RESET (__DATAINV__ is invalid) - */ -#define IS_UART_ADVFEATURE_DATAINV(__DATAINV__) (((__DATAINV__) == UART_ADVFEATURE_DATAINV_DISABLE) || \ - ((__DATAINV__) == UART_ADVFEATURE_DATAINV_ENABLE)) - -/** - * @brief Ensure that UART frame RX/TX pins swap setting is valid. - * @param __SWAP__ UART frame RX/TX pins swap setting. - * @retval SET (__SWAP__ is valid) or RESET (__SWAP__ is invalid) - */ -#define IS_UART_ADVFEATURE_SWAP(__SWAP__) (((__SWAP__) == UART_ADVFEATURE_SWAP_DISABLE) || \ - ((__SWAP__) == UART_ADVFEATURE_SWAP_ENABLE)) - -/** - * @brief Ensure that UART frame overrun setting is valid. - * @param __OVERRUN__ UART frame overrun setting. - * @retval SET (__OVERRUN__ is valid) or RESET (__OVERRUN__ is invalid) - */ -#define IS_UART_OVERRUN(__OVERRUN__) (((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_ENABLE) || \ - ((__OVERRUN__) == UART_ADVFEATURE_OVERRUN_DISABLE)) - -/** - * @brief Ensure that UART auto Baud rate state is valid. - * @param __AUTOBAUDRATE__ UART auto Baud rate state. - * @retval SET (__AUTOBAUDRATE__ is valid) or RESET (__AUTOBAUDRATE__ is invalid) - */ -#define IS_UART_ADVFEATURE_AUTOBAUDRATE(__AUTOBAUDRATE__) (((__AUTOBAUDRATE__) == \ - UART_ADVFEATURE_AUTOBAUDRATE_DISABLE) || \ - ((__AUTOBAUDRATE__) == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE)) - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Ensure that UART DMA enabling or disabling on error setting is valid. - * @param __DMA__ UART DMA enabling or disabling on error setting. - * @retval SET (__DMA__ is valid) or RESET (__DMA__ is invalid) - */ -#define IS_UART_ADVFEATURE_DMAONRXERROR(__DMA__) (((__DMA__) == UART_ADVFEATURE_DMA_ENABLEONRXERROR) || \ - ((__DMA__) == UART_ADVFEATURE_DMA_DISABLEONRXERROR)) -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Ensure that UART frame MSB first setting is valid. - * @param __MSBFIRST__ UART frame MSB first setting. - * @retval SET (__MSBFIRST__ is valid) or RESET (__MSBFIRST__ is invalid) - */ -#define IS_UART_ADVFEATURE_MSBFIRST(__MSBFIRST__) (((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_DISABLE) || \ - ((__MSBFIRST__) == UART_ADVFEATURE_MSBFIRST_ENABLE)) - -/** - * @brief Ensure that UART stop mode state is valid. - * @param __STOPMODE__ UART stop mode state. - * @retval SET (__STOPMODE__ is valid) or RESET (__STOPMODE__ is invalid) - */ -#define IS_UART_ADVFEATURE_STOPMODE(__STOPMODE__) (((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_DISABLE) || \ - ((__STOPMODE__) == UART_ADVFEATURE_STOPMODE_ENABLE)) - -/** - * @brief Ensure that UART mute mode state is valid. - * @param __MUTE__ UART mute mode state. - * @retval SET (__MUTE__ is valid) or RESET (__MUTE__ is invalid) - */ -#define IS_UART_MUTE_MODE(__MUTE__) (((__MUTE__) == UART_ADVFEATURE_MUTEMODE_DISABLE) || \ - ((__MUTE__) == UART_ADVFEATURE_MUTEMODE_ENABLE)) - -/** - * @brief Ensure that UART wake-up selection is valid. - * @param __WAKE__ UART wake-up selection. - * @retval SET (__WAKE__ is valid) or RESET (__WAKE__ is invalid) - */ -#define IS_UART_WAKEUP_SELECTION(__WAKE__) (((__WAKE__) == UART_WAKEUP_ON_ADDRESS) || \ - ((__WAKE__) == UART_WAKEUP_ON_READDATA_NONEMPTY)) - -/** - * @brief Ensure that UART driver enable polarity is valid. - * @param __POLARITY__ UART driver enable polarity. - * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) - */ -#define IS_UART_DE_POLARITY(__POLARITY__) (((__POLARITY__) == UART_DE_POLARITY_HIGH) || \ - ((__POLARITY__) == UART_DE_POLARITY_LOW)) - -/** - * @brief Ensure that UART Prescaler is valid. - * @param __CLOCKPRESCALER__ UART Prescaler value. - * @retval SET (__CLOCKPRESCALER__ is valid) or RESET (__CLOCKPRESCALER__ is invalid) - */ -#define IS_UART_PRESCALER(__CLOCKPRESCALER__) (((__CLOCKPRESCALER__) == UART_PRESCALER_DIV1) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV2) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV4) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV6) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV8) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV10) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV12) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) || \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256)) - -/** - * @} - */ - -/* Include UART HAL Extended module */ -#include "stm32u5xx_hal_uart_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength); -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod); -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart); -void HAL_UART_MspInit(UART_HandleTypeDef *huart); -void HAL_UART_MspDeInit(UART_HandleTypeDef *huart); - -/* Callbacks Register/UnRegister functions ***********************************/ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, - pUART_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID); - -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group2 IO operation functions - * @{ - */ - -/* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -#if defined(HAL_DMA_MODULE_ENABLED) -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart); -#endif /* HAL_DMA_MODULE_ENABLED */ -/* Transfer Abort functions */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart); - -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart); -void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart); -void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart); - -void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions - * @{ - */ - -/* Peripheral Control functions ************************************************/ -void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue); -HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart); -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @{ - */ - -/* Peripheral State and Errors functions **************************************************/ -HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart); -uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -----------------------------------------------------------*/ -/** @addtogroup UART_Private_Functions UART Private Functions - * @{ - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout); -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -#if defined(HAL_DMA_MODULE_ENABLED) -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @} - */ - -/* Private variables -----------------------------------------------------------*/ -/** @defgroup UART_Private_variables UART Private variables - * @{ - */ -/* Prescaler Table used in BRR computation macros. - Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ -extern const uint16_t UARTPrescTable[12]; -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_UART_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h deleted file mode 100644 index c6ac80c31..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_hal_uart_ex.h +++ /dev/null @@ -1,547 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_uart_ex.h - * @author MCD Application Team - * @brief Header file of UART HAL Extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_UART_EX_H -#define STM32U5xx_HAL_UART_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup UARTEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Types UARTEx Exported Types - * @{ - */ - -/** - * @brief UART wake up from stop mode parameters - */ -typedef struct -{ - uint32_t WakeUpEvent; /*!< Specifies which event will activate the Wakeup from Stop mode flag (WUF). - This parameter can be a value of @ref UART_WakeUp_from_Stop_Selection. - If set to UART_WAKEUP_ON_ADDRESS, the two other fields below must - be filled up. */ - - uint16_t AddressLength; /*!< Specifies whether the address is 4 or 7-bit long. - This parameter can be a value of @ref UARTEx_WakeUp_Address_Length. */ - - uint8_t Address; /*!< UART/USART node address (7-bit long max). */ -} UART_WakeUpTypeDef; - -/** - * @brief UART Autonomous mode parameters - */ -typedef struct -{ - uint32_t AutonomousModeState; /*!< Specifies the autonomous mode state.This parameter can be a value of - @ref UARTEx_Autonomous_mode.*/ - - uint32_t TriggerSelection; /*!< Specifies which trigger will activate the Transmission automatically. - This parameter can be a value of @ref UARTEx_Autonomous_Trigger_selection - or @ref UARTEx_Low_Power_Autonomous_Trigger_selection.*/ - - uint32_t TriggerPolarity; /*!< Specifies the autonomous mode trigger signal polarity. - This parameter can be a value of @ref UARTEx_Autonomous_Trigger_Polarity */ - - uint32_t DataSize; /*!< Specifies the transmitted data size in byte */ - - uint32_t IdleFrame; /*!< Specifies whether the IDLE frame transmission is enabled or disabled. - This parameter can be a value of @ref UARTEx_Autonomous_IDLE_FRAME. */ -} UART_AutonomousModeConfTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UARTEx_Exported_Constants UARTEx Exported Constants - * @{ - */ - -/** @defgroup UARTEx_Word_Length UARTEx Word Length - * @{ - */ -#define UART_WORDLENGTH_7B USART_CR1_M1 /*!< 7-bit long UART frame */ -#define UART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long UART frame */ -#define UART_WORDLENGTH_9B USART_CR1_M0 /*!< 9-bit long UART frame */ -/** - * @} - */ - -/** @defgroup UARTEx_WakeUp_Address_Length UARTEx WakeUp Address Length - * @{ - */ -#define UART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit long wake-up address */ -#define UART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit long wake-up address */ -/** - * @} - */ - -/** @defgroup UARTEx_FIFO_mode UARTEx FIFO mode - * @brief UART FIFO mode - * @{ - */ -#define UART_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */ -#define UART_FIFOMODE_ENABLE USART_CR1_FIFOEN /*!< FIFO mode enable */ -/** - * @} - */ - -/** @defgroup UARTEx_TXFIFO_threshold_level UARTEx TXFIFO threshold level - * @brief UART TXFIFO threshold level - * @{ - */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ -/** - * @} - */ - -/** @defgroup UARTEx_RXFIFO_threshold_level UARTEx RXFIFO threshold level - * @brief UART RXFIFO threshold level - * @{ - */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ -/** - * @} - */ - -/** @defgroup UARTEx_Autonomous_mode UARTEx Autonomous Mode - * @brief UART Autonomous mode - * @{ - */ -#define UART_AUTONOMOUS_MODE_DISABLE 0x00000000U /*!< Autonomous mode disable */ -#define UART_AUTONOMOUS_MODE_ENABLE USART_AUTOCR_TRIGEN /*!< Autonomous mode enable */ -/** - * @} - */ - -/** @defgroup UARTEx_Autonomous_Trigger_Polarity UARTEx Autonomous Trigger Polarity - * @brief UART Trigger polarity edge selection - * @{ - */ -#define UART_TRIG_POLARITY_RISING 0x00000000U /*!< UART triggered on rising edge */ -#define UART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< UART triggered on falling edge */ -/** - * @} - */ - -/** @defgroup UARTEx_Autonomous_IDLE_FRAME UARTEx Autonomous IDLE Frame - * @brief UART IDLE frame transmission - * @{ - */ -#define UART_IDLE_FRAME_ENABLE 0x00000000U /*!< IDLE Frame sent after enabling the transmitter */ -#define UART_IDLE_FRAME_DISABLE USART_AUTOCR_IDLEDIS /*!< IDLE Frame not sent after enabling the transmitter */ -/** - * @} - */ - -/** @defgroup UARTEx_Autonomous_Trigger_selection UARTEx Autonomous trigger selection - * @brief UART Autonomous Trigger selection - * @{ - */ -#define UART_GPDMA1_CH0_TCF_TRG 0U /*!< UART GPDMA1 channel0 Internal Trigger */ -#define UART_GPDMA1_CH1_TCF_TRG 1U /*!< UART GPDMA1 channel1 Internal Trigger */ -#define UART_GPDMA1_CH2_TCF_TRG 2U /*!< UART GPDMA1 channel2 Internal Trigger */ -#define UART_GPDMA1_CH3_TCF_TRG 3U /*!< UART GPDMA1 channel3 Internal Trigger */ -#define UART_EXTI_LINE6_TRG 4U /*!< UART EXTI line 6 Internal Trigger */ -#define UART_EXTI_LINE9_TRG 5U /*!< UART EXTI line 9 Internal Trigger */ -#define UART_LPTIM1_OUT_TRG 6U /*!< UART LPTIM1 out Internal Trigger */ -#define UART_LPTIM2_OUT_TRG 7U /*!< UART LPTIM2 out Internal Trigger */ -#define UART_COMP1_OUT_TRG 8U /*!< UART COMP1 out Internal Trigger */ -#define UART_COMP2_OUT_TRG 9U /*!< UART COMP2 out Internal Trigger */ -#define UART_RTC_ALRA_TRG 10U /*!< UART RTC alarm Internal Trigger */ -#define UART_RTC_WUT_TRG 11U /*!< UART RTC wakeup Internal Trigger */ -/** - * @} - */ - -/** @defgroup UARTEx_Low_Power_Autonomous_Trigger_selection UARTEx Low Power Autonomous trigger selection - * @brief LPUART Autonomous Trigger selection - * @{ - */ -#define LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */ -#define LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */ -#define LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */ -#define LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */ -#define LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ -#define LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ -#define LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */ -#define LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */ -#define LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ -#define LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ -#define LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ -#define LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UARTEx_Exported_Functions - * @{ - */ - -/** @addtogroup UARTEx_Exported_Functions_Group1 - * @{ - */ - -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, - uint32_t DeassertionTime); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group2 - * @{ - */ - -void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart); - -void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart); -void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart); - -/** - * @} - */ - -/** @addtogroup UARTEx_Exported_Functions_Group3 - * @{ - */ - -/* Peripheral Control functions **********************************************/ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart); - -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength); - -HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); - -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, - uint32_t Timeout); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -#if defined(HAL_DMA_MODULE_ENABLED) -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -#endif /* HAL_DMA_MODULE_ENABLED */ - -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); - -/* Autonomous Mode Control functions **********************************************/ -HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, - const UART_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, - UART_AutonomousModeConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart); - - -/** - * @} - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UARTEx_Private_Macros UARTEx Private Macros - * @{ - */ - -/** @brief Report the UART clock source. - * @param __HANDLE__ specifies the UART Handle. - * @param __CLOCKSOURCE__ output variable. - * @retval UART clocking source, written in __CLOCKSOURCE__. - */ -#if defined(USART6) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == USART6) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART6; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ - } while(0U) -#elif defined(USART2) -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART2) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART2; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ - } while(0U) -#else -#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \ - do { \ - if((__HANDLE__)->Instance == USART1) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART1; \ - } \ - else if((__HANDLE__)->Instance == USART3) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_USART3; \ - } \ - else if((__HANDLE__)->Instance == UART4) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART4; \ - } \ - else if((__HANDLE__)->Instance == UART5) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_UART5; \ - } \ - else if((__HANDLE__)->Instance == LPUART1) \ - { \ - (__CLOCKSOURCE__) = (uint32_t)RCC_PERIPHCLK_LPUART1; \ - } \ - else \ - { \ - (__CLOCKSOURCE__) = 0U; \ - } \ - } while(0U) -#endif /* USART6 */ - -/** @brief Report the UART mask to apply to retrieve the received data - * according to the word length and to the parity bits activation. - * @note If PCE = 1, the parity bit is not included in the data extracted - * by the reception API(). - * This masking operation is not carried out in the case of - * DMA transfers. - * @param __HANDLE__ specifies the UART Handle. - * @retval None, the mask to apply to UART RDR register is stored in (__HANDLE__)->Mask field. - */ -#define UART_MASK_COMPUTATION(__HANDLE__) \ - do { \ - if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_9B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x01FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_8B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x00FFU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - } \ - else if ((__HANDLE__)->Init.WordLength == UART_WORDLENGTH_7B) \ - { \ - if ((__HANDLE__)->Init.Parity == UART_PARITY_NONE) \ - { \ - (__HANDLE__)->Mask = 0x007FU ; \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x003FU ; \ - } \ - } \ - else \ - { \ - (__HANDLE__)->Mask = 0x0000U; \ - } \ - } while(0U) - -/** - * @brief Ensure that UART frame length is valid. - * @param __LENGTH__ UART frame length. - * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid) - */ -#define IS_UART_WORD_LENGTH(__LENGTH__) (((__LENGTH__) == UART_WORDLENGTH_7B) || \ - ((__LENGTH__) == UART_WORDLENGTH_8B) || \ - ((__LENGTH__) == UART_WORDLENGTH_9B)) - -/** - * @brief Ensure that UART wake-up address length is valid. - * @param __ADDRESS__ UART wake-up address length. - * @retval SET (__ADDRESS__ is valid) or RESET (__ADDRESS__ is invalid) - */ -#define IS_UART_ADDRESSLENGTH_DETECT(__ADDRESS__) (((__ADDRESS__) == UART_ADDRESS_DETECT_4B) || \ - ((__ADDRESS__) == UART_ADDRESS_DETECT_7B)) - -/** - * @brief Ensure that UART TXFIFO threshold level is valid. - * @param __THRESHOLD__ UART TXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_TXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_TXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that UART RXFIFO threshold level is valid. - * @param __THRESHOLD__ UART RXFIFO threshold level. - * @retval SET (__THRESHOLD__ is valid) or RESET (__THRESHOLD__ is invalid) - */ -#define IS_UART_RXFIFO_THRESHOLD(__THRESHOLD__) (((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_1_2) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_3_4) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_7_8) || \ - ((__THRESHOLD__) == UART_RXFIFO_THRESHOLD_8_8)) - -/** - * @brief Ensure that UART Trigger polarity state is valid. - * @param __POLARITY__ UART Trigger polarity. - * @retval SET (__POLARITY__ is valid) or RESET (__POLARITY__ is invalid) - */ -#define IS_UART_TRIGGER_POLARITY(__POLARITY__) (((__POLARITY__) == UART_TRIG_POLARITY_RISING) ||\ - ((__POLARITY__) == UART_TRIG_POLARITY_FALLING)) - -/** - * @brief Ensure that UART IDLE Frame Transmit state is valid. - * @param __IDLE__ UART IDLE Frame Transmit state. - * @retval SET (__IDLE__ is valid) or RESET (__IDLE__ is invalid) - */ -#define IS_UART_IDLE_FRAME_TRANSMIT(__IDLE__) (((__IDLE__) == UART_IDLE_FRAME_ENABLE) ||\ - ((__IDLE__) == UART_IDLE_FRAME_DISABLE)) - -/** - * @brief Ensure that UART Trigger source selection is valid. - * @param __SOURCE__ UART Trigger source selection. - * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) - */ -#define IS_UART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) - -/** - * @brief Ensure that LPUART Trigger source selection is valid. - * @param __SOURCE__ LPUART Trigger source selection. - * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) - */ -#define IS_LPUART_TRIGGER_SELECTION(__SOURCE__) ((__SOURCE__) <= 11U) - -/** - * @brief Ensure that the number of transferred data is valid. - * @param __SOURCE__ UART TX data size. - * @retval SET (__SOURCE__ is valid) or RESET (__SOURCE__ is invalid) - */ -#define IS_UART_TX_DATA_SIZE(__SOURCE__) ((__SOURCE__) <= 0xFFFFU) - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_UART_EX_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h deleted file mode 100644 index 957512d07..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_bus.h +++ /dev/null @@ -1,3223 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_bus.h - * @author MCD Application Team - * @brief Header file of BUS LL module. - - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB , APB peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB , APB peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_BUS_H -#define STM32U5xx_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_AHB1_GRP1_PERIPH_GPDMA1 RCC_AHB1ENR_GPDMA1EN -#define LL_AHB1_GRP1_PERIPH_CORDIC RCC_AHB1ENR_CORDICEN -#define LL_AHB1_GRP1_PERIPH_FMAC RCC_AHB1ENR_FMACEN -#define LL_AHB1_GRP1_PERIPH_MDF1 RCC_AHB1ENR_MDF1EN -#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN -#if defined(JPEG) -#define LL_AHB1_GRP1_PERIPH_JPEG RCC_AHB1ENR_JPEGEN -#endif /* defined(JPEG) */ -#define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN -#define LL_AHB1_GRP1_PERIPH_RAMCFG RCC_AHB1ENR_RAMCFGEN -#if defined(DMA2D) -#define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN -#endif /* DMA2D */ -#if defined(GFXMMU) -#define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN -#endif /* defined(GFXMMU) */ -#if defined(GPU2D) -#define LL_AHB1_GRP1_PERIPH_GPU2D RCC_AHB1ENR_GPU2DEN -#endif /* defined(GPU2D) */ -#if defined(DCACHE2) -#define LL_AHB1_GRP1_PERIPH_DCACHE2 RCC_AHB1ENR_DCACHE2EN -#endif /* defined(DCACHE2) */ -#define LL_AHB1_GRP1_PERIPH_GTZC1 RCC_AHB1ENR_GTZC1EN -#define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN -#define LL_AHB1_GRP1_PERIPH_ICACHE1 RCC_AHB1SMENR_ICACHESMEN -#define LL_AHB1_GRP1_PERIPH_DCACHE1 RCC_AHB1ENR_DCACHE1EN -#define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1ENR_SRAM1EN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH - * @{ - */ -#define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR1_GPIOAEN -#define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR1_GPIOBEN -#define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR1_GPIOCEN -#define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR1_GPIODEN -#define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR1_GPIOEEN -#if defined(GPIOF) -#define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR1_GPIOFEN -#endif /* GPIOF */ -#define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR1_GPIOGEN -#define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR1_GPIOHEN -#if defined (GPIOI) -#define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR1_GPIOIEN -#endif /* GPIOI */ -#if defined (GPIOJ) -#define LL_AHB2_GRP1_PERIPH_GPIOJ RCC_AHB2ENR1_GPIOJEN -#endif /* defined (GPIOJ) */ -#define LL_AHB2_GRP1_PERIPH_ADC12 RCC_AHB2ENR1_ADC12EN -#define LL_AHB2_GRP1_PERIPH_DCMI_PSSI RCC_AHB2ENR1_DCMI_PSSIEN -#if defined(USB_OTG_FS) -#define LL_AHB2_GRP1_PERIPH_OTG_FS RCC_AHB2ENR1_OTGEN -/* Legacy define */ -#define LL_AHB2_GRP1_PERIPH_USBFS LL_AHB2_GRP1_PERIPH_OTG_FS -#elif defined(USB_OTG_HS) -#define LL_AHB2_GRP1_PERIPH_OTG_HS RCC_AHB2ENR1_OTGEN -/* Legacy define */ -#define LL_AHB2_GRP1_PERIPH_USBHS LL_AHB2_GRP1_PERIPH_OTG_HS -#endif /* defined(USB_OTG_HS) */ -#if defined(RCC_AHB2ENR1_USBPHYCEN) -#define LL_AHB2_GRP1_PERIPH_USBPHY RCC_AHB2ENR1_USBPHYCEN -#endif /* defined(RCC_AHB2ENR1_USBPHYCEN) */ -#if defined(AES) -#define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR1_AESEN -#endif /* AES */ -#if defined(HASH) -#define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR1_HASHEN -#endif /* HASH */ -#define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR1_RNGEN -#define LL_AHB2_GRP1_PERIPH_PKA RCC_AHB2ENR1_PKAEN -#if defined(SAES) -#define LL_AHB2_GRP1_PERIPH_SAES RCC_AHB2ENR1_SAESEN -#endif /* SAES */ -#if defined(OCTOSPIM) -#define LL_AHB2_GRP1_PERIPH_OCTOSPIM RCC_AHB2ENR1_OCTOSPIMEN -#endif /* OCTOSPIM */ -#define LL_AHB2_GRP1_PERIPH_OTFDEC1 RCC_AHB2ENR1_OTFDEC1EN -#if defined (OTFDEC2) -#define LL_AHB2_GRP1_PERIPH_OTFDEC2 RCC_AHB2ENR1_OTFDEC2EN -#endif /* OTFDEC2 */ -#define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR1_SDMMC1EN -#if defined(SDMMC2) -#define LL_AHB2_GRP1_PERIPH_SDMMC2 RCC_AHB2ENR1_SDMMC2EN -#endif /* SDMMC2 */ -#define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2ENR1_SRAM2EN -#if defined(SRAM3_BASE) -#define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2ENR1_SRAM3EN -#endif /* SRAM3_BASE */ - -/** - * @} - */ - -/** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH - * @{ - */ -#define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_AHB3_GRP1_PERIPH_LPGPIO1 RCC_AHB3ENR_LPGPIO1EN -#define LL_AHB3_GRP1_PERIPH_PWR RCC_AHB3ENR_PWREN -#define LL_AHB3_GRP1_PERIPH_ADC4 RCC_AHB3ENR_ADC4EN -#define LL_AHB3_GRP1_PERIPH_DAC1 RCC_AHB3ENR_DAC1EN -#define LL_AHB3_GRP1_PERIPH_LPDMA1 RCC_AHB3ENR_LPDMA1EN -#define LL_AHB3_GRP1_PERIPH_ADF1 RCC_AHB3ENR_ADF1EN -#define LL_AHB3_GRP1_PERIPH_GTZC2 RCC_AHB3ENR_GTZC2EN -#define LL_AHB3_GRP1_PERIPH_SRAM4 RCC_AHB3ENR_SRAM4EN - -/** - * @} - */ - -/** @defgroup BUS_LL_EC_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH - * @{ - */ -#define LL_AHB2_GRP2_PERIPH_ALL 0xFFFFFFFFU -#if defined(FMC_BASE) -#define LL_AHB2_GRP2_PERIPH_FSMC RCC_AHB2ENR2_FSMCEN -#endif /* FMC_BASE */ -#define LL_AHB2_GRP2_PERIPH_OCTOSPI1 RCC_AHB2ENR2_OCTOSPI1EN -#if defined(OCTOSPI2) -#define LL_AHB2_GRP2_PERIPH_OCTOSPI2 RCC_AHB2ENR2_OCTOSPI2EN -#endif /* OCTOSPI2 */ -#if defined(HSPI1) -#define LL_AHB2_GRP2_PERIPH_HSPI1 RCC_AHB2ENR2_HSPI1EN -#endif /* defined(HSPI1) */ -#if defined(SRAM6_BASE) -#define LL_AHB2_GRP2_PERIPH_SRAM6 RCC_AHB2ENR2_SRAM6EN -#endif /* SRAM6_BASE */ -#if defined(SRAM5_BASE) -#define LL_AHB2_GRP2_PERIPH_SRAM5 RCC_AHB2ENR2_SRAM5EN -#endif /* SRAM5_BASE */ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN -#define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN -#define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN -#define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN -#define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN -#if defined(USART2) -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN -#endif /* USART2 */ -#define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN -#define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN -#define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN -#define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN -#define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN -#if defined(USART6) -#define LL_APB1_GRP1_PERIPH_USART6 RCC_APB1ENR1_USART6EN -#endif /* defined(USART6) */ -/** - * @} - */ - - -/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH - * @{ - */ -#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN -#define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN -#define LL_APB1_GRP2_PERIPH_FDCAN1 RCC_APB1ENR2_FDCAN1EN -#if defined(UCPD1) -#define LL_APB1_GRP2_PERIPH_UCPD1 RCC_APB1ENR2_UCPD1EN -#endif /* UCPD1 */ -#if defined(I2C5) -#define LL_APB1_GRP2_PERIPH_I2C5 RCC_APB1ENR2_I2C5EN -#endif /* defined(I2C5) */ -#if defined(I2C6) -#define LL_APB1_GRP2_PERIPH_I2C6 RCC_APB1ENR2_I2C6EN -#endif /* defined(I2C6) */ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH - * @{ - */ -#define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN -#define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN -#define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN -#define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN -#define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN -#define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN -#define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN -#define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN -#if defined(SAI2) -#define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN -#endif /* SAI2 */ -#if defined(USB_DRD_FS) -#define LL_APB2_GRP1_PERIPH_USB_FS RCC_APB2ENR_USBEN -#endif /* USB_DRD_FS */ -#if defined(GFXTIM) -#define LL_APB2_GRP1_PERIPH_GFXTIM RCC_APB2ENR_GFXTIMEN -#endif /* GFXTIM */ -#if defined(LTDC) -#define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN -#endif /* defined(LTDC) */ -#if defined(DSI) -#define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIHOSTEN -#endif /* defined(DSI) */ -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB3_GRP1_PERIPH APB3 GRP1 PERIPH - * @{ - */ -#define LL_APB3_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB3_GRP1_PERIPH_SYSCFG RCC_APB3ENR_SYSCFGEN -#define LL_APB3_GRP1_PERIPH_SPI3 RCC_APB3ENR_SPI3EN -#define LL_APB3_GRP1_PERIPH_LPUART1 RCC_APB3ENR_LPUART1EN -#define LL_APB3_GRP1_PERIPH_I2C3 RCC_APB3ENR_I2C3EN -#define LL_APB3_GRP1_PERIPH_LPTIM1 RCC_APB3ENR_LPTIM1EN -#define LL_APB3_GRP1_PERIPH_LPTIM3 RCC_APB3ENR_LPTIM3EN -#define LL_APB3_GRP1_PERIPH_LPTIM4 RCC_APB3ENR_LPTIM4EN -#define LL_APB3_GRP1_PERIPH_OPAMP RCC_APB3ENR_OPAMPEN -#define LL_APB3_GRP1_PERIPH_COMP RCC_APB3ENR_COMPEN -#define LL_APB3_GRP1_PERIPH_VREF RCC_APB3ENR_VREFEN -#define LL_APB3_GRP1_PERIPH_RTCAPB RCC_APB3ENR_RTCAPBEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_SRDAMR_GRP1_PERIPH SRDAMR GRP1 PERIPH - * @{ - */ -#define LL_SRDAMR_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_SRDAMR_GRP1_PERIPH_SPI3 RCC_SRDAMR_SPI3AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPUART1 RCC_SRDAMR_LPUART1AMEN -#define LL_SRDAMR_GRP1_PERIPH_I2C3 RCC_SRDAMR_I2C3AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPTIM1 RCC_SRDAMR_LPTIM1AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPTIM3 RCC_SRDAMR_LPTIM3AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPTIM4 RCC_SRDAMR_LPTIM4AMEN -#define LL_SRDAMR_GRP1_PERIPH_OPAMP RCC_SRDAMR_OPAMPAMEN -#define LL_SRDAMR_GRP1_PERIPH_COMP RCC_SRDAMR_COMPAMEN -#define LL_SRDAMR_GRP1_PERIPH_VREF RCC_SRDAMR_VREFAMEN -#define LL_SRDAMR_GRP1_PERIPH_RTCAPB RCC_SRDAMR_RTCAPBAMEN -#define LL_SRDAMR_GRP1_PERIPH_ADC4 RCC_SRDAMR_ADC4AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1 RCC_SRDAMR_LPGPIO1AMEN -#define LL_SRDAMR_GRP1_PERIPH_DAC1 RCC_SRDAMR_DAC1AMEN -#define LL_SRDAMR_GRP1_PERIPH_LPDMA1 RCC_SRDAMR_LPDMA1AMEN -#define LL_SRDAMR_GRP1_PERIPH_ADF1 RCC_SRDAMR_ADF1AMEN -#define LL_SRDAMR_GRP1_PERIPH_SRAM4 RCC_SRDAMR_SRAM4AMEN -/** - * @} - */ -/** @defgroup LL_RCC_Aliased_Constants LL RCC Aliased Constants maintained for legacy purpose - * @{ - */ -#define LL_AHB2_GRP1_PERIPH_ADC1 LL_AHB2_GRP1_PERIPH_ADC12 -#define LL_SRDAMR_GRP1_PERIPH_SPI3AMEN LL_SRDAMR_GRP1_PERIPH_SPI3 -#define LL_SRDAMR_GRP1_PERIPH_LPUART1AMEN LL_SRDAMR_GRP1_PERIPH_LPUART1 -#define LL_SRDAMR_GRP1_PERIPH_I2C3AMEN LL_SRDAMR_GRP1_PERIPH_I2C3 -#define LL_SRDAMR_GRP1_PERIPH_LPTIM1AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM1 -#define LL_SRDAMR_GRP1_PERIPH_LPTIM3AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM3 -#define LL_SRDAMR_GRP1_PERIPH_LPTIM4AMEN LL_SRDAMR_GRP1_PERIPH_LPTIM4 -#define LL_SRDAMR_GRP1_PERIPH_OPAMPAMEN LL_SRDAMR_GRP1_PERIPH_OPAMP -#define LL_SRDAMR_GRP1_PERIPH_COMPAMEN LL_SRDAMR_GRP1_PERIPH_COMP -#define LL_SRDAMR_GRP1_PERIPH_VREFAMEN LL_SRDAMR_GRP1_PERIPH_VREF -#define LL_SRDAMR_GRP1_PERIPH_RTCAPBAMEN LL_SRDAMR_GRP1_PERIPH_RTCAPB -#define LL_SRDAMR_GRP1_PERIPH_ADC4AMEN LL_SRDAMR_GRP1_PERIPH_ADC4 -#define LL_SRDAMR_GRP1_PERIPH_LPGPIO1AMEN LL_SRDAMR_GRP1_PERIPH_LPGPIO1 -#define LL_SRDAMR_GRP1_PERIPH_DAC1AMEN LL_SRDAMR_GRP1_PERIPH_DAC1 -#define LL_SRDAMR_GRP1_PERIPH_LPDMA1AMEN LL_SRDAMR_GRP1_PERIPH_LPDMA1 -#define LL_SRDAMR_GRP1_PERIPH_ADF1AMEN LL_SRDAMR_GRP1_PERIPH_ADF1 -#define LL_SRDAMR_GRP1_PERIPH_SRAM4AMEN LL_SRDAMR_GRP1_PERIPH_SRAM4 -/** - * @} - */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 bus clock. - * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); - (void)(tmpreg); -} - -/** - * @brief Enable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR CORDICEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR FMACEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR MDF1EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR JPEGEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR RAMCFGEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GPU2DEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DCACHE2EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR GTZC1EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR DCACHE1EN LL_AHB1_GRP1_EnableClock\n - * AHB1ENR SRAM1EN LL_AHB1_GRP1_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB1ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR CORDICEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR FMACEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR MDF1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR JPEGEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR RAMCFGEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GPU2DEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DCACHE2EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR GTZC1EN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR DCACHEEN LL_AHB1_GRP1_IsEnabledClock\n - * AHB1ENR SRAM1EN LL_AHB1_GRP1_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB1ENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB1 bus clock. - * @note except for FLASH, BKPSRAM, ICACHE, DCACHE1 and SRAM1. - * @rmtoll CFGR2 AHB1DIS LL_AHB1_GRP1_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB1DIS); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @rmtoll AHB1ENR GPDMA1EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR CORDICEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR FMACEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR MDF1EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR JPEGEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR RAMCFGEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GPU2DEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DCACHE2EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR GTZC1EN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR DCACHEEN LL_AHB1_GRP1_DisableClock\n - * AHB1ENR SRAM1EN LL_AHB1_GRP1_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1ENR, Periphs); -} - -/** - * @brief Force AHB1 peripherals reset. - * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR JPEGRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ForceReset\n - * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB1RSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @rmtoll AHB1RSTR GPDMA1RSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR CORDICRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR FMACRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR MDF1RSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR CRCRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR JPEGRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR TSCRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR RAMCFGRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DMA2DRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GFXMMURSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR GPU2DRSTR LL_AHB1_GRP1_ReleaseReset\n - * AHB1RSTR DCACHE2RSTR LL_AHB1_GRP1_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1RSTR, Periphs); -} - -/** - * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR FMACSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB1SMENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR FMACSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR CRCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR TSCSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB1SMENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB1SMENR GPDMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR CORDICSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR FMACSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR MDF1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR JPEGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR RAMCFGSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR GPU2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR DCACHE2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR GTZC1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR BKPSRAMSMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR ICACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR DCACHESMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_GPDMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CORDIC - * @arg @ref LL_AHB1_GRP1_PERIPH_FMAC - * @arg @ref LL_AHB1_GRP1_PERIPH_MDF1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @arg @ref LL_AHB1_GRP1_PERIPH_JPEG (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_TSC - * @arg @ref LL_AHB1_GRP1_PERIPH_RAMCFG - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GPU2D (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE2 (*) - * @arg @ref LL_AHB1_GRP1_PERIPH_GTZC1 - * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_ICACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_DCACHE1 - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB1SMENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH - * @{ - */ - -/** - * @brief Enable AHB2_1 bus clock. - * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); - (void)(tmpreg); -} - -/** - * @brief Enable AHB2 peripherals clock. - * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIODEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 ADC12EN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 OTGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 AESEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 HASHEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 RNGEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 PKAEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 SAESEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_EnableClock\n - * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2ENR1, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2ENR1, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB2 peripheral clock is enabled or not - * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIODEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 ADC12EN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 OTGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 AESEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 HASHEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 RNGEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 PKAEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 SAESEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 OCTOSPIMEN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_IsEnabledClock\n - * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB2ENR1, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB2_1 bus clock. - * @note except for SRAM2 and SRAM3. - * @rmtoll CFGR2 AHB2DIS1 LL_AHB2_GRP1_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS1); -} - -/** - * @brief Disable AHB2 peripherals clock. - * @rmtoll AHB2ENR1 GPIOAEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOBEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOCEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIODEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOEEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOFEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOHEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOIEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 GPIOJEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 ADC12EN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 DCMI_PSSIEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 OTGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 AESEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 HASHEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 RNGEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 PKAEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 SAESEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 OSPIMEN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 OTFDEC1EN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 OTFDEC2EN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 SDMMC1EN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 SDMMC2EN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 SRAM2EN LL_AHB2_GRP1_DisableClock\n - * AHB2ENR1 SRAM3EN LL_AHB2_GRP1_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2ENR1, Periphs); -} - -/** - * @brief Force AHB2 peripherals reset. - * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 AESRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 PKARST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ForceReset\n - * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB2RSTR1, Periphs); -} - -/** - * @brief Release AHB2 peripherals reset. - * @rmtoll AHB2RSTR1 GPIOARST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOBRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOCRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIODRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOERST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOFRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOHRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOIRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 GPIOJRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 ADC12RST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 DCMI_PSSIRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 OTGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 USBPHYCRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 AESRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 HASHRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 RNGRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 PKARST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 SAESRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 OCTOSPIMRST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 OTFDEC1RST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 OTFDEC2RST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 SDMMC1RST LL_AHB2_GRP1_ReleaseReset\n - * AHB2RSTR1 SDMMC2RST LL_AHB2_GRP1_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2RSTR1, Periphs); -} - -/** - * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2ENR1 USBPHYCEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2SMENR1, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2SMENR1, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 USBPHYCMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB2SMENR1, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB2SMENR1 GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 GPIOJSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 ADC12SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 DCMI_PSSISMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 OTGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 USBPHYCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 PKASMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 SAESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 OTFDEC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 OTFDEC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 SDMMC2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * AHB2SMENR1 SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP1_PERIPH_ALL - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOJ (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_ADC12 - * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI_PSSI - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_FS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTG_HS (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_USBPHY (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_AES - * @arg @ref LL_AHB2_GRP1_PERIPH_HASH - * @arg @ref LL_AHB2_GRP1_PERIPH_RNG - * @arg @ref LL_AHB2_GRP1_PERIPH_PKA - * @arg @ref LL_AHB2_GRP1_PERIPH_SAES (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OCTOSPIM (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC1 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_OTFDEC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 - * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC2 (*) - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 - * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2SMENR1, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_AHB3 AHB3 - * @{ - */ - -/** - * @brief Enable AHB3 bus clock. - * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); - (void)(tmpreg); -} - -/** - * @brief Enable AHB3 peripherals clock. - * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR PWREN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR ADC4EN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR DAC1EN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR LPDMA1EN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR ADF1EN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR GTZC2EN LL_AHB3_GRP1_EnableClock\n - * AHB3ENR SRAM4EN LL_AHB3_GRP1_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB3ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB3 peripheral clock is enabled or not - * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR PWREN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR ADC4EN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR DAC1EN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR LPDMA1EN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR ADF1EN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR GTZC2EN LL_AHB3_GRP1_IsEnabledClock\n - * AHB3ENR SRAM4EN LL_AHB3_GRP1_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB3ENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB3 bus clock. - * @rmtoll CFGR2 AHB3DIS LL_AHB3_GRP1_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR3, RCC_CFGR3_AHB3DIS); -} - -/** - * @brief Disable AHB3 peripherals clock. - * @rmtoll AHB3ENR LPGPIO1EN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR PWREN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR ADC4EN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR DAC1EN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR LPDMA1EN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR ADF1EN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR GTZC2EN LL_AHB3_GRP1_DisableClock\n - * AHB3ENR SRAM4EN LL_AHB3_GRP1_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3ENR, Periphs); -} - -/** - * @brief Force AHB3 peripherals reset. - * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR PWRRST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR ADC4RST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR DAC1RST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR ADF1RST LL_AHB3_GRP1_ForceReset\n - * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB3RSTR, Periphs); -} - -/** - * @brief Release AHB3 peripherals reset. - * @rmtoll AHB3RSTR LPGPIO1RST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR PWRRST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR ADC4RST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR DAC1RST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR LPDMA1RST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR ADF1RST LL_AHB3_GRP1_ReleaseReset\n - * AHB3RSTR GTZC2RST LL_AHB3_GRP1_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3RSTR, Periphs); -} - -/** - * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR PWRSMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB3SMENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB3 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR PWRSMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB3SMENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB3SMENR LPGPIO1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR PWRSMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR ADC4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR DAC1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR LPDMA1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR ADF1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR GTZC2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * AHB3SMENR SRAM4SMEN LL_AHB3_GRP1_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB3_GRP1_PERIPH_ALL - * @arg @ref LL_AHB3_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_AHB3_GRP1_PERIPH_PWR - * @arg @ref LL_AHB3_GRP1_PERIPH_ADC4 - * @arg @ref LL_AHB3_GRP1_PERIPH_DAC1 - * @arg @ref LL_AHB3_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_AHB3_GRP1_PERIPH_ADF1 - * @arg @ref LL_AHB3_GRP1_PERIPH_GTZC2 - * @arg @ref LL_AHB3_GRP1_PERIPH_SRAM4 - * @retval None - */ -__STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB3SMENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_AHB2_GRP2_PERIPH AHB2 GRP2 PERIPH - * @{ - */ - -/** - * @brief Enable AHB2_2 bus clock. - * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); - (void)(tmpreg); -} - -/** - * @brief Enable AHB2 peripherals clock. - * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_EnableClock\n - * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_EnableClock\n - * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_EnableClock\n - * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_EnableClock\n - * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_EnableClock\n - * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) - * - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2ENR2, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2ENR2, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB2 peripheral clock is enabled or not - * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_IsEnabledClock\n - * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_IsEnabledClock\n - * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_IsEnabledClock\n - * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_IsEnabledClock\n - * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n - * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) - * - * (*) value not defined in all devices. - * @retval None - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB2ENR2, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB2_2 bus clock. - * @rmtoll CFGR2 AHB2DIS2 LL_AHB2_GRP2_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR2, RCC_CFGR2_AHB2DIS2); -} - -/** - * @brief Disable AHB2 peripherals clock. - * @rmtoll AHB2ENR2 FSMCEN LL_AHB2_GRP2_DisableClock\n - * AHB2ENR2 OCTOSPI1EN LL_AHB2_GRP2_DisableClock\n - * AHB2ENR2 OCTOSPI2EN LL_AHB2_GRP2_DisableClock\n - * AHB2ENR2 HSPI1EN LL_AHB2_GRP2_DisableClock\n - * AHB2ENR2 SRAM6EN LL_AHB2_GRP2_DisableClock\n - * AHB2ENR2 SRAM5EN LL_AHB2_GRP2_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2ENR2, Periphs); -} - -/** - * @brief Force AHB2 peripherals reset. - * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ForceReset\n - * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ForceReset\n - * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ForceReset\n - * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHB2RSTR2, Periphs); -} - -/** - * @brief Release AHB2 peripherals reset. - * @rmtoll AHB2RSTR2 FSMCRST LL_AHB2_GRP2_ReleaseReset\n - * AHB2RSTR2 OCTOSPI1RST LL_AHB2_GRP2_ReleaseReset\n - * AHB2RSTR2 OCTOSPI2RST LL_AHB2_GRP2_ReleaseReset\n - * AHB2RSTR2 HSPI1RST LL_AHB2_GRP2_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2RSTR2, Periphs); -} - -/** - * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_EnableClockStopSleep\n - * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n - * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_EnableClockStopSleep\n - * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_EnableClockStopSleep\n - * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHB2SMENR2, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHB2SMENR2, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB2 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB2_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHB2SMENR2, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes - * @rmtoll AHB2SMENR2 FSMCSMEN LL_AHB2_GRP2_DisableClockStopSleep\n - * AHB2SMENR2 OCTOSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n - * AHB2SMENR2 OCTOSPI2SMEN LL_AHB2_GRP2_DisableClockStopSleep\n - * AHB2SMENR2 HSPI1SMEN LL_AHB2_GRP2_DisableClockStopSleep\n - * AHB2SMENR2 SRAM6SMEN LL_AHB2_GRP2_DisableClockStopSleep\n - * AHB2SMENR2 SRAM5SMEN LL_AHB2_GRP2_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB2_GRP2_PERIPH_ALL - * @arg @ref LL_AHB2_GRP2_PERIPH_FSMC (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI1 - * @arg @ref LL_AHB2_GRP2_PERIPH_OCTOSPI2 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_HSPI1 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM6 (*) - * @arg @ref LL_AHB2_GRP2_PERIPH_SRAM5 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_AHB2_GRP2_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHB2SMENR2, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1 APB1 - * @{ - */ - -/** - * @brief Enable APB1 bus clock. - * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); - (void)(tmpreg); -} - -/** - * @brief Enable APB1 peripherals clock. - * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n - * APB1ENR1 USART6N LL_APB1_GRP1_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR1, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); - (void)tmpreg; -} - -/** - * @brief Enable APB1 peripherals clock. - * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n - * APB1ENR2 I2C5EN LL_APB1_GRP2_EnableClock\n - * APB1ENR2 I2C6EN LL_APB1_GRP2_EnableClock\n - * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock\n - * APB1ENR2 FDCAN1EN LL_APB1_GRP2_EnableClock\n - * APB1ENR2 UCPD1EN LL_APB1_GRP2_EnableClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1ENR2, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not - * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n - * APB1ENR1 USART6EN LL_APB1_GRP1_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB1ENR1, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Check if APB1 peripheral clock is enabled or not - * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n - * APB1ENR2 I2C5EN LL_APB1_GRP2_IsEnabledClock\n - * APB1ENR2 I2C6EN LL_APB1_GRP2_IsEnabledClock\n - * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock\n - * APB1ENR2 FDCAN1EN LL_APB1_GRP2_IsEnabledClock\n - * APB1ENR2 UCPD1EN LL_APB1_GRP2_IsEnabledClock - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB1ENR2, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB1 bus clock. - * @note except for IWDG. - * @rmtoll CFGR2 APB1DIS LL_APB1_GRP1_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR2, RCC_CFGR2_APB1DIS); -} - -/** - * @brief Disable APB1 peripherals clock. - * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n - * APB1ENR1 USART6EN LL_APB1_GRP1_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR1, Periphs); -} - -/** - * @brief Disable APB1 peripherals clock. - * @rmtoll APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n - * APB1ENR2 I2C5EN LL_APB1_GRP2_DisableClock\n - * APB1ENR2 I2C6EN LL_APB1_GRP2_DisableClock\n - * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock\n - * APB1ENR2 FDCAN1EN LL_APB1_GRP2_DisableClock\n - * APB1ENR2 UCPD1EN LL_APB1_GRP2_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1ENR2, Periphs); -} - -/** - * @brief Force APB1 peripherals reset. - * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n - * APB1RSTR1 USART6RST LL_APB1_GRP1_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR1, Periphs); -} - -/** - * @brief Force APB1 peripherals reset. - * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_DisableClock\n - * APB1RSTR2 I2C5RST LL_APB1_GRP2_DisableClock\n - * APB1RSTR2 I2C6RST LL_APB1_GRP2_DisableClock\n - * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_DisableClock\n - * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_DisableClock\n - * APB1RSTR2 UCPDRST LL_APB1_GRP2_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB1RSTR2, Periphs); -} - -/** - * @brief Release APB1 peripherals reset. - * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n - * APB1RSTR1 USART6RST LL_APB1_GRP1_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR1, Periphs); -} - -/** - * @brief Release APB1 peripherals reset. - * @rmtoll APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n - * APB1RSTR2 I2C5RST LL_APB1_GRP2_ReleaseReset\n - * APB1RSTR2 I2C6RST LL_APB1_GRP2_ReleaseReset\n - * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset\n - * APB1RSTR2 FDCAN1RST LL_APB1_GRP2_ReleaseReset\n - * APB1RSTR2 UCPD1RST LL_APB1_GRP2_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1RSTR2, Periphs); -} - -/** - * @brief Enable APB1 peripheral clocks in Sleep and Stop modes - * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n - * APB1SMENR1 USART6SMEN LL_APB1_GRP1_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1SMENR1, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 USART2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 USART3SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 UART4SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 UART5SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 CRSSMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * APB1SMENR1 USART6SMEN LL_APB1_GRP1_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB1SMENR1, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB1 peripheral clocks in Sleep and Stop modes - * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n - * APB1SMENR1 USART6SMEN LL_APB1_GRP1_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_ALL - * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 - * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 (*) - * @arg @ref LL_APB1_GRP1_PERIPH_USART3 - * @arg @ref LL_APB1_GRP1_PERIPH_UART4 - * @arg @ref LL_APB1_GRP1_PERIPH_UART5 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 - * @arg @ref LL_APB1_GRP1_PERIPH_CRS - * @arg @ref LL_APB1_GRP1_PERIPH_USART6 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1SMENR1, Periphs); -} - -/** - * @brief Enable APB1 peripheral clocks in Sleep and Stop modes - * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB1SMENR2, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n - * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n - * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n - * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n - * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep\n - * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_IsEnabledClockStopSleep - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB1SMENR2, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB1 peripheral clocks in Sleep and Stop modes - * @rmtoll APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n - * APB1SMENR2 I2C5SMEN LL_APB1_GRP2_DisableClockStopSleep\n - * APB1SMENR2 I2C6SMEN LL_APB1_GRP2_DisableClockStopSleep\n - * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep\n - * APB1SMENR2 FDCAN1SMEN LL_APB1_GRP2_DisableClockStopSleep\n - * APB1SMENR2 UCPD1SMEN LL_APB1_GRP2_DisableClockStopSleep - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 - * @arg @ref LL_APB1_GRP2_PERIPH_I2C5 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_I2C6 (*) - * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 - * @arg @ref LL_APB1_GRP2_PERIPH_FDCAN1 - * @arg @ref LL_APB1_GRP2_PERIPH_UCPD1 (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB1SMENR2, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB2 APB2 - * @{ - */ - -/** - * @brief Enable APB2 bus clock. - * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); - tmpreg = READ_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); - (void)(tmpreg); -} - -/** - * @brief Enable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n - * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n - * APB2ENR USBEN LL_APB2_GRP1_EnableClock\n - * APB2ENR GFXTIMEN LL_APB2_GRP1_EnableClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n - * APB2ENR DSIHOSTEN LL_APB2_GRP1_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB2 peripheral clock is enabled or not - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR USBEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR GFXTIMEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n - * APB2ENR DSIHOSTEN LL_APB2_GRP1_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB2ENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB2 bus clock. - * @rmtoll CFGR2 APB2DIS LL_APB2_GRP1_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR2, RCC_CFGR2_APB2DIS); -} - -/** - * @brief Disable APB2 peripherals clock. - * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n - * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n - * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n - * APB2ENR USBEN LL_APB2_GRP1_DisableClock\n - * APB2ENR GFXTIMEN LL_APB2_GRP1_DisableClock\n - * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n - * APB2ENR DSIHOSTEN LL_APB2_GRP1_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2ENR, Periphs); -} - -/** - * @brief Force APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n - * APB2RSTR USBRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR GFXTIMRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n - * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Release APB2 peripherals reset. - * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR USBRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR GFXTIMRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n - * APB2RSTR DSIHOSTRST LL_APB2_GRP1_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2RSTR, Periphs); -} - -/** - * @brief Enable APB2 peripheral clocks in Sleep and Stop modes - * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR USBSMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n - * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM(*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB2SMENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); - (void)tmpreg; -} - - -/** - * @brief Check if APB2 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR SPI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR TIM8SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR USART1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR TIM15SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR TIM16SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR TIM17SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR SAI1SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR USBSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR LTDCSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * (*) value not defined in all devices. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB2SMENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB2 peripheral clocks in Sleep and Stop modes - * @rmtoll APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR USBSMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR GFXTIMSMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n - * APB2SMENR DSIHOSTSMEN LL_APB2_GRP1_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB2_GRP1_PERIPH_ALL - * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 - * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 - * @arg @ref LL_APB2_GRP1_PERIPH_USART1 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 - * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 - * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) - * @arg @ref LL_APB2_GRP1_PERIPH_USB_FS (*) - * @arg @ref LL_APB2_GRP1_PERIPH_GFXTIM (*) - * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) - * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) - * - * (*) value not defined in all devices. - * @retval None - */ -__STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB2SMENR, Periphs); -} - -/** - * @} - */ - - -/** @defgroup BUS_LL_EF_APB3 APB3 - * @{ - */ - -/** - * @brief Enable APB3 bus clock. - * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_EnableBusClock - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_EnableBusClock(void) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); - tmpreg = READ_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); - (void)(tmpreg); -} - -/** - * @brief Enable APB3 peripherals clock. - * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_EnableClock\n - * APB3ENR SPI3EN LL_APB3_GRP1_EnableClock\n - * APB3ENR LPUART1EN LL_APB3_GRP1_EnableClock\n - * APB3ENR I2C3EN LL_APB3_GRP1_EnableClock\n - * APB3ENR LPTIM1EN LL_APB3_GRP1_EnableClock\n - * APB3ENR LPTIM3EN LL_APB3_GRP1_EnableClock\n - * APB3ENR LPTIM4EN LL_APB3_GRP1_EnableClock\n - * APB3ENR OPAMPEN LL_APB3_GRP1_EnableClock\n - * APB3ENR COMPEN LL_APB3_GRP1_EnableClock\n - * APB3ENR VREFEN LL_APB3_GRP1_EnableClock\n - * APB3ENR RTCAPBEN LL_APB3_GRP1_EnableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB3ENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB3ENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB3 peripheral clock is enabled or not - * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR SPI3EN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR LPUART1EN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR I2C3EN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR LPTIM1EN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR LPTIM3EN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR LPTIM4EN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR OPAMPEN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR COMPEN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR VREFEN LL_APB3_GRP1_IsEnabledClock\n - * APB3ENR RTCAPBEN LL_APB3_GRP1_IsEnabledClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB3ENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB3 bus clock. - * @rmtoll CFGR2 APB3DIS LL_APB3_GRP1_DisableBusClock - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_DisableBusClock(void) -{ - SET_BIT(RCC->CFGR3, RCC_CFGR3_APB3DIS); -} - -/** - * @brief Disable APB2 peripherals clock. - * @rmtoll APB3ENR SYSCFGEN LL_APB3_GRP1_DisableClock\n - * APB3ENR SPI3EN LL_APB3_GRP1_DisableClock\n - * APB3ENR LPUART1EN LL_APB3_GRP1_DisableClock\n - * APB3ENR I2C3EN LL_APB3_GRP1_DisableClock\n - * APB3ENR LPTIM1EN LL_APB3_GRP1_DisableClock\n - * APB3ENR LPTIM3EN LL_APB3_GRP1_DisableClock\n - * APB3ENR LPTIM4EN LL_APB3_GRP1_DisableClock\n - * APB3ENR OPAMPEN LL_APB3_GRP1_DisableClock\n - * APB3ENR COMPEN LL_APB3_GRP1_DisableClock\n - * APB3ENR VREFEN LL_APB3_GRP1_DisableClock\n - * APB3ENR RTCAPBEN LL_APB3_GRP1_DisableClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB3ENR, Periphs); -} - -/** - * @brief Force APB3 peripherals reset. - * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ForceReset\n - * APB3RSTR SPI3RST LL_APB3_GRP1_ForceReset\n - * APB3RSTR LPUART1RST LL_APB3_GRP1_ForceReset\n - * APB3RSTR I2C3RST LL_APB3_GRP1_ForceReset\n - * APB3RSTR LPTIM1RST LL_APB3_GRP1_ForceReset\n - * APB3RSTR LPTIM3RST LL_APB3_GRP1_ForceReset\n - * APB3RSTR LPTIM4RST LL_APB3_GRP1_ForceReset\n - * APB3RSTR OPAMPRST LL_APB3_GRP1_ForceReset\n - * APB3RSTR COMPRST LL_APB3_GRP1_ForceReset\n - * APB3RSTR VREFRST LL_APB3_GRP1_ForceReset\n - * APB3RSTR RTCAPBRST LL_APB3_GRP1_ForceReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APB3RSTR, Periphs); -} - -/** - * @brief Release APB3 peripherals reset. - * @rmtoll APB3RSTR SYSCFGRST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR SPI3RST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR LPUART1RST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR I2C3RST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR LPTIM1RST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR LPTIM3RST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR LPTIM4RST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR OPAMPRST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR COMPRST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR VREFRST LL_APB3_GRP1_ReleaseReset\n - * APB3RSTR RTCAPBRST LL_APB3_GRP1_ReleaseReset\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB3RSTR, Periphs); -} - -/** - * @brief Enable APB3 peripheral clocks in Sleep and Stop modes - * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR SPI3SMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR LPUART1SMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR I2C3SMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR OPAMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR COMPSMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR VREFSMEN LL_APB3_GRP1_EnableClockStopSleep\n - * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_EnableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_EnableClockStopSleep(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APB3SMENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APB3SMENR, Periphs); - (void)tmpreg; -} - - -/** - * @brief Check if APB3 peripheral clocks in Sleep and Stop modes is enabled or not - * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR SPI3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR LPUART1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR I2C3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR OPAMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR COMPSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR VREFSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_IsEnabledClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB3_GRP1_IsEnabledClockStopSleep(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APB3SMENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable APB3 peripheral clocks in Sleep and Stop modes - * @rmtoll APB3SMENR SYSCFGSMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR SPI3SMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR LPUART1SMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR I2C3SMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR LPTIM1SMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR LPTIM3SMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR LPTIM4SMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR OPAMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR COMPSMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR VREFSMEN LL_APB3_GRP1_DisableClockStopSleep\n - * APB3SMENR RTCAPBSMEN LL_APB3_GRP1_DisableClockStopSleep\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB3_GRP1_PERIPH_ALL - * @arg @ref LL_APB3_GRP1_PERIPH_SYSCFG - * @arg @ref LL_APB3_GRP1_PERIPH_SPI3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPUART1 - * @arg @ref LL_APB3_GRP1_PERIPH_I2C3 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_APB3_GRP1_PERIPH_OPAMP - * @arg @ref LL_APB3_GRP1_PERIPH_COMP - * @arg @ref LL_APB3_GRP1_PERIPH_VREF - * @arg @ref LL_APB3_GRP1_PERIPH_RTCAPB - * @retval None - */ -__STATIC_INLINE void LL_APB3_GRP1_DisableClockStopSleep(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APB3SMENR, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_SRDAMR SRDAMR - * @{ - */ - -/** - * @brief Enable SRDAMR peripheral clocks in autonomous mode - * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR COMPAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR VREFAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR VREFRST LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_EnableAutonomousClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP - * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP - * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF - * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 - * @retval None - */ -__STATIC_INLINE void LL_SRDAMR_GRP1_EnableAutonomousClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->SRDAMR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->SRDAMR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if SRDAMR peripheral clock is enabled or not - * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR COMPAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR VREFAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR VREFRST LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_IsEnabledAutonomousClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP - * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP - * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF - * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SRDAMR_GRP1_IsEnabledAutonomousClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->SRDAMR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable SRDAMR peripheral clocks in Sleep and Stop modes - * @rmtoll SRDAMR SPI3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR LPUART1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR I2C3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR LPTIM1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR LPTIM3AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR LPTIM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR OPAMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR COMPAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR VREFAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR VREFRST LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR RTCAPBAMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR ADC4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR LPGPIO1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR DAC1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR LPDMA1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR ADF1AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * SRDAMR SRAM4AMEN LL_SRDAMR_GRP1_DisableAutonomousClock\n - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ALL - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SPI3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPUART1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_I2C3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM3 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPTIM4 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_OPAMP - * @arg @ref LL_SRDAMR_GRP1_PERIPH_COMP - * @arg @ref LL_SRDAMR_GRP1_PERIPH_VREF - * @arg @ref LL_SRDAMR_GRP1_PERIPH_RTCAPB - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADC4 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPGPIO1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_DAC1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_LPDMA1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_ADF1 - * @arg @ref LL_SRDAMR_GRP1_PERIPH_SRAM4 - * @retval None - */ -__STATIC_INLINE void LL_SRDAMR_GRP1_DisableAutonomousClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->SRDAMR, Periphs); -} -/** - * @} - */ - -/** - * @} - */ -#endif /* defined(RCC) */ - -/** - * @} - */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_BUS_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h deleted file mode 100644 index 103ab54cb..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_cortex.h +++ /dev/null @@ -1,1314 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_cortex.h - * @author MCD Application Team - * @brief Header file of CORTEX LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL CORTEX driver contains a set of generic APIs that can be - used by user: - (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick with - HCLK source or @ref LL_Init1msTick_HCLK_Div8, @ref LL_Init1msTick_LSI or - @ref LL_Init1msTick_LSE with external source - (+) Low power mode configuration (SCB register of Cortex-MCU) - (+) API to access to MCU info (CPUID register) - (+) API to enable fault handler (SHCSR accesses) - (+) API to enable and disable the MPU secure and non-secure - (+) API to configure the region of MPU secure and non-secure - (+) API to configure the attributes region of MPU secure and non-secure - - @endverbatim - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_CORTEX_H -#define STM32U5xx_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CORTEX_LL_EC_REGION_ACCESS CORTEX LL MPU Region Access Attributes - * @{ - */ -/* Register MPU_RBAR (Cortex-M33) : bits [4:0] */ -#define MPU_ACCESS_MSK (MPU_RBAR_SH_Msk|MPU_RBAR_AP_Msk|MPU_RBAR_XN_Msk) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX LL Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_EXTERNAL 0x00000000U /*!< External clock source selected as SysTick - clock source */ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick - clock source */ -/** Legacy definitions for backward compatibility purpose - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 LL_SYSTICK_CLKSOURCE_EXTERNAL -/** - */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_EC_FAULT Handler Fault type - * @{ - */ -#define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ -#define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ -#define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ -#define LL_HANDLER_FAULT_SECURE SCB_SHCSR_SECUREFAULTENA_Msk /*!< Secure fault */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control CORTEX LL MPU HFNMI and PRIVILEGED Access control - * @{ - */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Attributes CORTEX LL MPU Attributes - * @{ - */ -#define LL_MPU_DEVICE_NGNRNE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_NGNRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_NGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ - -#define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ -#define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - -#define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ -#define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - -#define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ -#define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ -#define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ -#define LL_MPU_RW_ALLOCATE 0x3U /* Normal memory, read/write allocate. */ -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Region_Enable CORTEX LL MPU Region Enable - * @{ - */ -#define LL_MPU_REGION_ENABLE 1U -#define LL_MPU_REGION_DISABLE 0U -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Instruction_Access CORTEX LL MPU Instruction Access - * @{ - */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Access_Shareable CORTEX LL MPU Instruction Access Shareable - * @{ - */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes CORTEX LL MPU Region Permission Attributes - * @{ - */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Region_Index CORTEX LL MPU Region Index - * @{ - */ -#define LL_MPU_REGION_NUMBER0 0U -#define LL_MPU_REGION_NUMBER1 1U -#define LL_MPU_REGION_NUMBER2 2U -#define LL_MPU_REGION_NUMBER3 3U -#define LL_MPU_REGION_NUMBER4 4U -#define LL_MPU_REGION_NUMBER5 5U -#define LL_MPU_REGION_NUMBER6 6U -#define LL_MPU_REGION_NUMBER7 7U -/** - * @} - */ - -/** @defgroup CORTEX_LL_MPU_Attributes_Index CORTEX LL MPU Memory Attributes Index - * @{ - */ -#define LL_MPU_ATTRIBUTES_NUMBER0 0U -#define LL_MPU_ATTRIBUTES_NUMBER1 1U -#define LL_MPU_ATTRIBUTES_NUMBER2 2U -#define LL_MPU_ATTRIBUTES_NUMBER3 3U -#define LL_MPU_ATTRIBUTES_NUMBER4 4U -#define LL_MPU_ATTRIBUTES_NUMBER5 5U -#define LL_MPU_ATTRIBUTES_NUMBER6 6U -#define LL_MPU_ATTRIBUTES_NUMBER7 7U -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX LL Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @brief CORTEX SYSTICK LL module driver - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_EXTERNAL - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE CORTEX LL LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_HANDLER CORTEX LL HANDLER - * @{ - */ - -/** - * @brief Enable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_EnableFault\n - * SCB_SHCSR BUSFAULTENA LL_HANDLER_EnableFault\n - * SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault\n - * SCB_SHCSR SECUREFAULTENA LL_HANDLER_EnableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @arg @ref LL_HANDLER_FAULT_SECURE (*) - * - * (*) value applicable in secure when the system implements the security. - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) -{ - /* Enable the system handler fault */ - SET_BIT(SCB->SHCSR, Fault); -} - -/** - * @brief Disable a fault in System handler control register (SHCSR) - * @rmtoll SCB_SHCSR USGFAULTENA LL_HANDLER_DisableFault\n - * SCB_SHCSR BUSFAULTENA LL_HANDLER_DisableFault\n - * SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault\n - * SCB_SHCSR SECUREFAULTENA LL_HANDLER_DisableFault - * @param Fault This parameter can be a combination of the following values: - * @arg @ref LL_HANDLER_FAULT_USG - * @arg @ref LL_HANDLER_FAULT_BUS - * @arg @ref LL_HANDLER_FAULT_MEM - * @arg @ref LL_HANDLER_FAULT_SECURE (*) - * - * (*) value applicable in secure when the system implements the security. - * @retval None - */ -__STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) -{ - /* Disable the system handler fault */ - CLEAR_BIT(SCB->SHCSR, Fault); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO CORTEX LL MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x0: revision 0) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Architecture version - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture - * @retval Value should be equal to 0xF for Cortex-M33 ("ARMv8-M with Main Extension") - */ -__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xD21 for Cortex-M33 - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MPU CORTEX LL MPU - * @{ - */ - -/** - * @brief Enable MPU with input options - * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable - * @param MPU_Control This parameter can be one of the following values: - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE - * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI - * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void LL_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ - - /* Enable the MPU*/ - MPU->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable non-secure MPU with input options - * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable - * @param MPU_Control This parameter can be one of the following values: - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE - * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI - * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT - * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF - * @retval None - */ -__STATIC_INLINE void LL_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ - - /* Enable the MPU*/ - MPU_NS->CTRL = MPU_CTRL_ENABLE_Msk | MPU_Control; - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Disable MPU - * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable - * @retval None - */ -__STATIC_INLINE void LL_MPU_Disable(void) -{ - __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ - - /* Disable MPU */ - WRITE_REG(MPU->CTRL, 0U); - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Disable the non-secure MPU - * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable_NS - * @retval None - */ -__STATIC_INLINE void LL_MPU_Disable_NS(void) -{ - __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before disabling the MPU */ - - /* Disable MPU*/ - WRITE_REG(MPU_NS->CTRL, 0U); - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} -#endif /* __ARM_FEATURE_CMSE */ - - -/** - * @brief Check if MPU is enabled or not - * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) -{ - return ((READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Check if non-secure MPU is enabled or not - * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled_NS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled_NS(void) -{ - return ((READ_BIT(MPU_NS->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)) ? 1UL : 0UL); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Enable a MPU region - * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - /* Enable the MPU region */ - SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); -} - -/** - * @brief Check if MPU region is enabled or not - * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region(uint32_t Region) -{ - /* Set region index */ - WRITE_REG(MPU->RNR, Region); - - /* Return MPU region status */ - return ((READ_BIT(MPU->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable a non-secure MPU region - * @rmtoll MPU_RLAR ENABLE LL_MPU_EnableRegion_NS - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_EnableRegion_NS(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Enable the MPU region */ - SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); -} - -/** - * @brief Check if non-secure MPU region is enabled or not - * @rmtoll MPU_RNR ENABLE LL_MPU_IsEnabled_Region_NS - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_MPU_IsEnabled_Region_NS(uint32_t Region) -{ - /* Set region index */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Return non-secure MPU region status */ - return ((READ_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk) == (MPU_RLAR_EN_Msk)) ? 1UL : 0UL); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Disable a MPU region - * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n - * MPU_RLAR ENABLE LL_MPU_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - /* Disable the MPU region */ - CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Disable a non-secure MPU region - * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion_NS\n - * MPU_RLAR ENABLE LL_MPU_DisableRegion_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_DisableRegion_NS(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Disable the MPU region */ - CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Configure and enable a MPU region - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n - * MPU_RBAR ADDR LL_MPU_ConfigRegion\n - * MPU_RLAR ADDR LL_MPU_ConfigRegion\n - * MPU_RBAR XN LL_MPU_ConfigRegion\n - * MPU_RBAR AP LL_MPU_ConfigRegion\n - * MPU_RBAR SH LL_MPU_ConfigRegion\n - * MPU_RLAR EN LL_MPU_ConfigRegion\n - * MPU_RLAR AttrIndx LL_MPU_ConfigRegion\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE - * or @ref LL_MPU_ACCESS_INNER_SHAREABLE - * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO - * or @ref LL_MPU_REGION_ALL_RO - * @param AttrIndx This parameter can be one of the following values: - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 - * @param BaseAddress Value of region base address - * @param LimitAddress Value of region limit address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, uint32_t BaseAddress, - uint32_t LimitAddress) -{ - /* Set region index */ - WRITE_REG(MPU->RNR, Region); - - /* Set region base address and region access attributes */ - WRITE_REG(MPU->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); - - /* Set region limit address, memory attributes index and enable region */ - WRITE_REG(MPU->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure and enable a non-secure MPU region - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion_NS\n - * MPU_RBAR ADDR LL_MPU_ConfigRegion_NS\n - * MPU_RLAR ADDR LL_MPU_ConfigRegion_NS\n - * MPU_RBAR XN LL_MPU_ConfigRegion_NS\n - * MPU_RBAR AP LL_MPU_ConfigRegion_NS\n - * MPU_RBAR SH LL_MPU_ConfigRegion_NS\n - * MPU_RLAR EN LL_MPU_ConfigRegion_NS\n - * MPU_RLAR AttrIndx LL_MPU_ConfigRegion_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE - * or @ref LL_MPU_ACCESS_INNER_SHAREABLE - * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO - * or @ref LL_MPU_REGION_ALL_RO - * @param AttrIndx This parameter can be one of the following values: - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 - * @param BaseAddress Value of region base address - * @param LimitAddress Value of region limit address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegion_NS(uint32_t Region, uint32_t Attributes, uint32_t AttrIndx, - uint32_t BaseAddress, uint32_t LimitAddress) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Set region base address and region access attributes */ - WRITE_REG(MPU_NS->RBAR, ((BaseAddress & MPU_RBAR_BASE_Msk) | Attributes)); - - /* Set region limit address, memory attributes index and enable region */ - WRITE_REG(MPU_NS->RLAR, ((LimitAddress & MPU_RLAR_LIMIT_Msk) | AttrIndx | MPU_RLAR_EN_Msk)); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Configure a MPU region address range - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress\n - * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress\n - * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param BaseAddress Value of region base address - * @param LimitAddress Value of region limit address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegionAddress(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - /* Modify region base address */ - MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); - - /* Modify region limit address */ - MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure a non-secure MPU region address range - * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegionAddress_NS\n - * MPU_RBAR ADDR LL_MPU_ConfigRegionAddress_NS\n - * MPU_RLAR ADDR LL_MPU_ConfigRegionAddress_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param BaseAddress Value of region base address - * @param LimitAddress Value of region limit address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigRegionAddress_NS(uint32_t Region, uint32_t BaseAddress, uint32_t LimitAddress) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Set base address */ - MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); - - /* Set limit address */ - MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Configure a MPU attributes index - * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes\n - * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes\n - * @param AttIndex This parameter can be one of the following values: - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 - * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigAttributes(uint32_t AttIndex, uint32_t Attributes) -{ - /* When selected index is in range [0;3] */ - if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) - { - /* Modify Attr field of MPU_MAIR0 accordingly */ - MODIFY_REG(MPU->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); - } - /* When selected index is in range [4;7] */ - else - { - /* Modify Attr field of MPU_MAIR1 accordingly */ - MODIFY_REG(MPU->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure a non-secure MPU attributes index - * @rmtoll MPU_MAIR0 Attribute LL_MPU_ConfigAttributes_NS\n - * MPU_MAIR1 Attribute LL_MPU_ConfigAttributes_NS\n - * @param AttIndex This parameter can be one of the following values: - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER0 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER1 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER2 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER3 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER4 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER5 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER6 - * @arg @ref LL_MPU_ATTRIBUTES_NUMBER7 - * @param Attributes This parameter can be a combination of @ref CORTEX_LL_MPU_Attributes - * @retval None - */ -__STATIC_INLINE void LL_MPU_ConfigAttributes_NS(uint32_t AttIndex, uint32_t Attributes) -{ - /* When selected index is in range [0;3] */ - if (AttIndex < LL_MPU_ATTRIBUTES_NUMBER4) - { - /* Modify Attr field of MPU_MAIR0_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR0, (0xFFU << (AttIndex * 8U)), (Attributes << (AttIndex * 8U))); - } - /* When selected index is in range [4;7] */ - else - { - /* Modify Attr field of MPU_MAIR1_NS accordingly */ - MODIFY_REG(MPU_NS->MAIR1, (0xFFU << ((AttIndex - 4U) * 8U)), (Attributes << ((AttIndex - 4U) * 8U))); - } -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Configure a MPU region limit address - * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress\n - * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param LimitAddress Value of region limit address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_SetRegionLimitAddress(uint32_t Region, uint32_t LimitAddress) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - /* Set limit address */ - MODIFY_REG(MPU->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); -} - -/** - * @brief Get a MPU region limit address - * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - return (READ_REG(MPU->RLAR & MPU_RLAR_LIMIT_Msk)); -} - -/** - * @brief Configure a MPU region base address - * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress\n - * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param BaseAddress Value of region base address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_SetRegionBaseAddress(uint32_t Region, uint32_t BaseAddress) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - /* Set base address */ - MODIFY_REG(MPU->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); -} - -/** - * @brief Get a MPU region base address - * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - return (READ_REG(MPU->RBAR & MPU_RBAR_BASE_Msk)); -} - -/** - * @brief Configure a MPU region access attributes and enable a region - * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess\n - * MPU_RBAR XN LL_MPU_SetRegionAccess\n - * MPU_RBAR AP LL_MPU_SetRegionAccess\n - * MPU_RBAR SH LL_MPU_SetRegionAccess\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE - * or @ref LL_MPU_ACCESS_INNER_SHAREABLE - * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO - * or @ref LL_MPU_REGION_ALL_RO - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_SetRegionAccess(uint32_t Region, uint32_t Attributes) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - /* Set base address */ - MODIFY_REG(MPU->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); -} - -/** - * @brief Get a MPU region access attributes - * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess\n - * MPU_RBAR XN LL_MPU_GetRegionAccess\n - * MPU_RBAR AP LL_MPU_GetRegionAccess\n - * MPU_RBAR SH LL_MPU_GetRegionAccess\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU->RNR, Region); - - return (READ_REG(MPU->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure a non-secure MPU region limit address - * @rmtoll MPU_RNR REGION LL_MPU_SetRegionLimitAddress_NS\n - * MPU_RLAR ADDR LL_MPU_SetRegionLimitAddress_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param LimitAddress Value of region limit address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_SetRegionLimitAddress_NS(uint32_t Region, uint32_t LimitAddress) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Set limit address */ - MODIFY_REG(MPU_NS->RLAR, MPU_RLAR_LIMIT_Msk, (LimitAddress & MPU_RLAR_LIMIT_Msk)); -} - -/** - * @brief Get a non-secure MPU region limit address - * @rmtoll MPU_RNR REGION LL_MPU_GetRegionLimitAddress_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_MPU_GetRegionLimitAddress_NS(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - return (READ_REG(MPU_NS->RLAR & MPU_RLAR_LIMIT_Msk)); -} - -/** - * @brief Configure a non-secure MPU region base address - * @rmtoll MPU_RNR REGION LL_MPU_SetRegionBaseAddress_NS\n - * MPU_RBAR ADDR LL_MPU_SetRegionBaseAddress_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param BaseAddress Value of region base address - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_SetRegionBaseAddress_NS(uint32_t Region, uint32_t BaseAddress) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Set base address */ - MODIFY_REG(MPU_NS->RBAR, MPU_RBAR_BASE_Msk, (BaseAddress & MPU_RBAR_BASE_Msk)); -} - -/** - * @brief Get a non-secure MPU region base address - * @rmtoll MPU_RNR REGION LL_MPU_GetRegionBaseAddress_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_MPU_GetRegionBaseAddress_NS(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - return (READ_REG(MPU_NS->RBAR & MPU_RBAR_BASE_Msk)); -} - -/** - * @brief Configure a non-secure MPU region access attributes and enable a region - * @rmtoll MPU_RNR REGION LL_MPU_SetRegionAccess_NS\n - * MPU_RBAR XN LL_MPU_SetRegionAccess_NS\n - * MPU_RBAR AP LL_MPU_SetRegionAccess_NS\n - * MPU_RBAR SH LL_MPU_SetRegionAccess_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @param Attributes This parameter can be a combination of the following values: - * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE - * @arg @ref LL_MPU_ACCESS_NOT_SHAREABLE or @ref LL_MPU_ACCESS_OUTER_SHAREABLE - * or @ref LL_MPU_ACCESS_INNER_SHAREABLE - * @arg @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_ALL_RW or @ref LL_MPU_REGION_PRIV_RO - * or @ref LL_MPU_REGION_ALL_RO - * @note cortex-M33 supports 8 secure and 8 non secure regions. - * @retval None - */ -__STATIC_INLINE void LL_MPU_SetRegionAccess_NS(uint32_t Region, uint32_t Attributes) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - /* Set base address Attributes */ - MODIFY_REG(MPU_NS->RBAR, MPU_ACCESS_MSK, (Attributes & MPU_ACCESS_MSK)); -} - -/** - * @brief Get a non-secure MPU region access attributes - * @rmtoll MPU_RNR REGION LL_MPU_GetRegionAccess_NS\n - * MPU_RBAR XN LL_MPU_GetRegionAccess_NS\n - * MPU_RBAR AP LL_MPU_GetRegionAccess_NS\n - * MPU_RBAR SH LL_MPU_GetRegionAccess_NS\n - * @param Region This parameter can be one of the following values: - * @arg @ref LL_MPU_REGION_NUMBER0 - * @arg @ref LL_MPU_REGION_NUMBER1 - * @arg @ref LL_MPU_REGION_NUMBER2 - * @arg @ref LL_MPU_REGION_NUMBER3 - * @arg @ref LL_MPU_REGION_NUMBER4 - * @arg @ref LL_MPU_REGION_NUMBER5 - * @arg @ref LL_MPU_REGION_NUMBER6 - * @arg @ref LL_MPU_REGION_NUMBER7 - * @retval None - */ -__STATIC_INLINE uint32_t LL_MPU_GetRegionAccess_NS(uint32_t Region) -{ - /* Set Region number */ - WRITE_REG(MPU_NS->RNR, Region); - - return (READ_REG(MPU_NS->RBAR & (MPU_RBAR_XN_Msk | MPU_RBAR_AP_Msk | MPU_RBAR_SH_Msk))); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_CORTEX_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h deleted file mode 100644 index 678c2e799..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_crs.h +++ /dev/null @@ -1,796 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_crs.h - * @author MCD Application Team - * @brief Header file of CRS LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_CRS_H -#define STM32U5xx_LL_CRS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(CRS) - -/** @defgroup CRS_LL CRS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup CRS_LL_Private_Constants CRS Private Constants - * @{ - */ - -/* Defines used for the bit position in the register and perform offsets*/ -#define CRS_POSITION_TRIM (CRS_CR_TRIM_Pos) /* bit position in CR reg */ -#define CRS_POSITION_FECAP (CRS_ISR_FECAP_Pos) /* bit position in ISR reg */ -#define CRS_POSITION_FELIM (CRS_CFGR_FELIM_Pos) /* bit position in CFGR reg */ - - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Constants CRS Exported Constants - * @{ - */ - -/** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_CRS_ReadReg function - * @{ - */ -#define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF -#define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF -#define LL_CRS_ISR_ERRF CRS_ISR_ERRF -#define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF -#define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR -#define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS -#define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF -/** - * @} - */ - -/** @defgroup CRS_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions - * @{ - */ -#define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE -#define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE -#define LL_CRS_CR_ERRIE CRS_CR_ERRIE -#define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider - * @{ - */ -#define LL_CRS_SYNC_DIV_1 0x00000000U /*!< Synchro Signal not divided (default) */ -#define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ -#define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ -#define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ -#define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ -#define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ -#define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ -#define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source - * @{ - */ -#define LL_CRS_SYNC_SOURCE_GPIO 0x00000000U /*!< Synchro Signal source GPIO */ -#define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ -#define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity - * @{ - */ -#define LL_CRS_SYNC_POLARITY_RISING 0x00000000U /*!< Synchro Active on rising edge (default) */ -#define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction - * @{ - */ -#define LL_CRS_FREQ_ERROR_DIR_UP 0x00000000U /*!< Upcounting direction, the actual frequency is above the target */ -#define LL_CRS_FREQ_ERROR_DIR_DOWN CRS_ISR_FEDIR /*!< Downcounting direction, the actual frequency is below the target */ -/** - * @} - */ - -/** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values - * @{ - */ -/** - * @brief Reset value of the RELOAD field - * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz - * and a synchronization signal frequency of 1 kHz (SOF signal from USB) - */ -#define LL_CRS_RELOADVALUE_DEFAULT 0x0000BB7FU - -/** - * @brief Reset value of Frequency error limit. - */ -#define LL_CRS_ERRORLIMIT_DEFAULT 0x00000022U - -/** - * @brief Reset value of the HSI48 Calibration field - * @note The default value is 64, which corresponds to the middle of the trimming interval. - * The trimming step is specified in the product datasheet. - * A higher TRIM value corresponds to a higher output frequency. - */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Macros CRS Exported Macros - * @{ - */ - -/** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in CRS register - * @param __INSTANCE__ CRS Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in CRS register - * @param __INSTANCE__ CRS Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload - * @{ - */ - -/** - * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies - * @note The RELOAD value should be selected according to the ratio between - * the target frequency and the frequency of the synchronization source after - * prescaling. It is then decreased by one in order to reach the expected - * synchronization on the zero value. The formula is the following: - * RELOAD = (fTARGET / fSYNC) -1 - * @param __FTARGET__ Target frequency (value in Hz) - * @param __FSYNC__ Synchronization signal frequency (value in Hz) - * @retval Reload value (in Hz) - */ -#define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRS_LL_Exported_Functions CRS Exported Functions - * @{ - */ - -/** @defgroup CRS_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable Frequency error counter - * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified - * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) -{ - SET_BIT(CRS->CR, CRS_CR_CEN); -} - -/** - * @brief Disable Frequency error counter - * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_CEN); -} - -/** - * @brief Check if Frequency error counter is enabled or not - * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) -{ - return ((READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable Automatic trimming counter - * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) -{ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); -} - -/** - * @brief Disable Automatic trimming counter - * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); -} - -/** - * @brief Check if Automatic trimming is enabled or not - * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) -{ - return ((READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)) ? 1UL : 0UL); -} - -/** - * @brief Set HSI48 oscillator smooth trimming - * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only - * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming - * @param Value a number between Min_Data = 0 and Max_Data = 127 - * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) -{ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_POSITION_TRIM); -} - -/** - * @brief Get HSI48 oscillator smooth trimming - * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming - * @retval a number between Min_Data = 0 and Max_Data = 127 - */ -__STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) -{ - return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_POSITION_TRIM); -} - -/** - * @brief Set counter reload value - * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter - * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF - * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT - * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); -} - -/** - * @brief Get counter reload value - * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter - * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); -} - -/** - * @brief Set frequency error limit - * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit - * @param Value a number between Min_Data = 0 and Max_Data = 255 - * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_POSITION_FELIM); -} - -/** - * @brief Get frequency error limit - * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit - * @retval A number between Min_Data = 0 and Max_Data = 255 - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_POSITION_FELIM); -} - -/** - * @brief Set division factor for SYNC signal - * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider - * @param Divider This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 - * @arg @ref LL_CRS_SYNC_DIV_2 - * @arg @ref LL_CRS_SYNC_DIV_4 - * @arg @ref LL_CRS_SYNC_DIV_8 - * @arg @ref LL_CRS_SYNC_DIV_16 - * @arg @ref LL_CRS_SYNC_DIV_32 - * @arg @ref LL_CRS_SYNC_DIV_64 - * @arg @ref LL_CRS_SYNC_DIV_128 - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); -} - -/** - * @brief Get division factor for SYNC signal - * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 - * @arg @ref LL_CRS_SYNC_DIV_2 - * @arg @ref LL_CRS_SYNC_DIV_4 - * @arg @ref LL_CRS_SYNC_DIV_8 - * @arg @ref LL_CRS_SYNC_DIV_16 - * @arg @ref LL_CRS_SYNC_DIV_32 - * @arg @ref LL_CRS_SYNC_DIV_64 - * @arg @ref LL_CRS_SYNC_DIV_128 - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); -} - -/** - * @brief Set SYNC signal source - * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO - * @arg @ref LL_CRS_SYNC_SOURCE_LSE - * @arg @ref LL_CRS_SYNC_SOURCE_USB - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); -} - -/** - * @brief Get SYNC signal source - * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO - * @arg @ref LL_CRS_SYNC_SOURCE_LSE - * @arg @ref LL_CRS_SYNC_SOURCE_USB - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); -} - -/** - * @brief Set input polarity for the SYNC signal source - * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_CRS_SYNC_POLARITY_RISING - * @arg @ref LL_CRS_SYNC_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) -{ - MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); -} - -/** - * @brief Get input polarity for the SYNC signal source - * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_SYNC_POLARITY_RISING - * @arg @ref LL_CRS_SYNC_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) -{ - return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); -} - -/** - * @brief Configure CRS for the synchronization - * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n - * CFGR RELOAD LL_CRS_ConfigSynchronization\n - * CFGR FELIM LL_CRS_ConfigSynchronization\n - * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n - * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n - * CFGR SYNCPOL LL_CRS_ConfigSynchronization - * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 - * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF - * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 - * @param Settings This parameter can be a combination of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 - * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 - * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 - * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB - * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, - uint32_t ReloadValue, uint32_t Settings) -{ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); - MODIFY_REG(CRS->CFGR, - CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, - ReloadValue | (ErrorLimitValue << CRS_POSITION_FELIM) | Settings); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_CRS_Management CRS_Management - * @{ - */ - -/** - * @brief Generate software SYNC event - * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Get the frequency error direction latched in the time of the last - * SYNC event - * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection - * @retval Returned value can be one of the following values: - * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP - * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) -{ - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** - * @brief Get the frequency error counter value latched in the time of the last SYNC event - * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture - * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF - */ -__STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) -{ - return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_POSITION_FECAP); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if SYNC event OK signal occurred or not - * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)) ? 1UL : 0UL); -} - -/** - * @brief Check if SYNC warning signal occurred or not - * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)) ? 1UL : 0UL); -} - -/** - * @brief Check if Synchronization or trimming error signal occurred or not - * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)) ? 1UL : 0UL); -} - -/** - * @brief Check if Expected SYNC signal occurred or not - * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)) ? 1UL : 0UL); -} - -/** - * @brief Check if SYNC error signal occurred or not - * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)) ? 1UL : 0UL); -} - -/** - * @brief Check if SYNC missed error signal occurred or not - * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)) ? 1UL : 0UL); -} - -/** - * @brief Check if Trimming overflow or underflow occurred or not - * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) -{ - return ((READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the SYNC event OK flag - * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); -} - -/** - * @brief Clear the SYNC warning flag - * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); -} - -/** - * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also - * the ERR flag - * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); -} - -/** - * @brief Clear Expected SYNC flag - * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) -{ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); -} - -/** - * @} - */ - -/** @defgroup CRS_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable SYNC event OK interrupt - * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) -{ - SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); -} - -/** - * @brief Disable SYNC event OK interrupt - * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); -} - -/** - * @brief Check if SYNC event OK interrupt is enabled or not - * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) -{ - return ((READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable SYNC warning interrupt - * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) -{ - SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); -} - -/** - * @brief Disable SYNC warning interrupt - * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); -} - -/** - * @brief Check if SYNC warning interrupt is enabled or not - * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) -{ - return ((READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Synchronization or trimming error interrupt - * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_ERR(void) -{ - SET_BIT(CRS->CR, CRS_CR_ERRIE); -} - -/** - * @brief Disable Synchronization or trimming error interrupt - * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_ERR(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); -} - -/** - * @brief Check if Synchronization or trimming error interrupt is enabled or not - * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) -{ - return ((READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Expected SYNC interrupt - * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) -{ - SET_BIT(CRS->CR, CRS_CR_ESYNCIE); -} - -/** - * @brief Disable Expected SYNC interrupt - * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC - * @retval None - */ -__STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) -{ - CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); -} - -/** - * @brief Check if Expected SYNC interrupt is enabled or not - * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) -{ - return ((READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_CRS_DeInit(void); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(CRS) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_CRS_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h deleted file mode 100644 index cb98f2fd4..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dlyb.h +++ /dev/null @@ -1,143 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_dlyb.h - * @author MCD Application Team - * @brief Header file of DelayBlock module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_DLYB_H -#define STM32U5xx_LL_DLYB_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) -#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup DLYB_LL DLYB - * @{ - */ - -/** - * @brief DLYB Configuration Structure definition - */ - -typedef struct -{ - uint32_t Units; /*!< Specifies the Delay of a unit delay cell. - This parameter can be a value between 0 and DLYB_MAX_UNIT */ - - uint32_t PhaseSel; /*!< Specifies the Phase for the output clock. - This parameter can be a value between 0 and DLYB_MAX_SELECT */ -} LL_DLYB_CfgTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DLYB_Exported_Constants DLYB Exported Constants - * @{ - */ - -#define DLYB_MAX_UNIT ((uint32_t)0x00000080U) /*!< Max UNIT value (128) */ -#define DLYB_MAX_SELECT ((uint32_t)0x0000000CU) /*!< Max SELECT value (12) */ - -/** - * @} - */ - -/** @defgroup DLYB_LL_Flags DLYB Flags - * @{ - */ - -#define DLYB_FLAG_LNGF DLYB_CFGR_LNGF - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DLYB_LL_Exported_Functions DLYB Exported Functions - * @{ - */ - -/** @defgroup DLYB_LL_Configuration Configuration functions - * @{ - */ - -/** - * @brief DLYB Enable - * @param DLYBx DLYB Instance - * @retval None - */ - -__STATIC_INLINE void LL_DLYB_Enable(DLYB_TypeDef *DLYBx) -{ - SET_BIT(DLYBx->CR, DLYB_CR_DEN); -} - -/** @brief Disable the DLYB. - * @param DLYBx DLYB Instance. - * @retval None - */ - -__STATIC_INLINE void LL_DLYB_Disable(DLYB_TypeDef *DLYBx) -{ - CLEAR_BIT(DLYBx->CR, DLYB_CR_DEN); -} - -/** - * @} - */ - -/** @defgroup DLYB_Control_Functions DLYB Control functions - * @{ - */ - -void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); -void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); -uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_DLYB_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h deleted file mode 100644 index 26178cc1b..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_dma.h +++ /dev/null @@ -1,6978 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_dma.h - * @author MCD Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### LL DMA driver acronyms ##### - ============================================================================== - [..] Acronyms table : - ========================================= - || Acronym || || - ========================================= - || SRC || Source || - || DEST || Destination || - || ADDR || Address || - || ADDRS || Addresses || - || INC || Increment / Incremented || - || DEC || Decrement / Decremented || - || BLK || Block || - || RPT || Repeat / Repeated || - || TRIG || Trigger || - ========================================= - @endverbatim - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_DMA_H -#define STM32U5xx_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if (defined (GPDMA1) || defined (LPDMA1)) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -#define DMA_CHANNEL0_OFFSET (0x00000050UL) -#define DMA_CHANNEL1_OFFSET (0x000000D0UL) -#define DMA_CHANNEL2_OFFSET (0x00000150UL) -#define DMA_CHANNEL3_OFFSET (0x000001D0UL) -#define DMA_CHANNEL4_OFFSET (0x00000250UL) -#define DMA_CHANNEL5_OFFSET (0x000002D0UL) -#define DMA_CHANNEL6_OFFSET (0x00000350UL) -#define DMA_CHANNEL7_OFFSET (0x000003D0UL) -#define DMA_CHANNEL8_OFFSET (0x00000450UL) -#define DMA_CHANNEL9_OFFSET (0x000004D0UL) -#define DMA_CHANNEL10_OFFSET (0x00000550UL) -#define DMA_CHANNEL11_OFFSET (0x000005D0UL) -#define DMA_CHANNEL12_OFFSET (0x00000650UL) -#define DMA_CHANNEL13_OFFSET (0x000006D0UL) -#define DMA_CHANNEL14_OFFSET (0x00000750UL) -#define DMA_CHANNEL15_OFFSET (0x000007D0UL) - -/* Array used to get the DMA Channel register offset versus Channel index LL_DMA_CHANNEL_x */ -static const uint32_t LL_DMA_CH_OFFSET_TAB[] = -{ - DMA_CHANNEL0_OFFSET, DMA_CHANNEL1_OFFSET, DMA_CHANNEL2_OFFSET, DMA_CHANNEL3_OFFSET, - DMA_CHANNEL4_OFFSET, DMA_CHANNEL5_OFFSET, DMA_CHANNEL6_OFFSET, DMA_CHANNEL7_OFFSET, - DMA_CHANNEL8_OFFSET, DMA_CHANNEL9_OFFSET, DMA_CHANNEL10_OFFSET, DMA_CHANNEL11_OFFSET, - DMA_CHANNEL12_OFFSET, DMA_CHANNEL13_OFFSET, DMA_CHANNEL14_OFFSET, DMA_CHANNEL15_OFFSET, -}; - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ - -#if defined (USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ - -/** - * @brief LL DMA init structure definition. - */ -typedef struct -{ - uint32_t SrcAddress; /*!< This field specify the data transfer source address. - Programming this field is mandatory for all available DMA channels. - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcAddress(). */ - - uint32_t DestAddress; /*!< This field specify the data transfer destination address. - Programming this field is mandatory for all available DMA channels. - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestAddress(). */ - - uint32_t Direction; /*!< This field specify the data transfer direction. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkHWRequest(). */ - - uint32_t DataAlignment; /*!< This field specify the transfer data alignment. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDataAlignment(). */ - - uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. - Programming this field is not mandatory for LPDMA channels. - This parameter must be a value between Min_Data = 1 and Max_Data = 64. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcBurstLength(). */ - - uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. - Programming this field is not mandatory for LPDMA channels. - This parameter must be a value between Min_Data = 1 and Max_Data = 64. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestBurstLength(). */ - - uint32_t SrcDataWidth; /*!< This field specify the source data width. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcDataWidth(). */ - - uint32_t DestDataWidth; /*!< This field specify the destination data width. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestDataWidth(). */ - - uint32_t SrcIncMode; /*!< This field specify the source burst increment mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcIncMode(). */ - - uint32_t DestIncMode; /*!< This field specify the destination burst increment mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestIncMode(). */ - - uint32_t Priority; /*!< This field specify the channel priority level. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetChannelPriorityLevel(). */ - - uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. - Programming this field is mandatory for all available DMA channels. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkDataLength(). */ - - uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value between 1 and 2048 Min_Data = 0 - and Max_Data = 0x000007FF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkRptCount(). */ - - uint32_t TriggerMode; /*!< This field specify the trigger mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetTriggerMode(). */ - - uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetTriggerPolarity(). */ - - uint32_t TriggerSelection; /*!< This field specify the trigger event selection. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetHWTrigger(). */ - - uint32_t Request; /*!< This field specify the peripheral request selection. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetPeriphRequest(). */ - - uint32_t TransferEventMode; /*!< This field specify the transfer event mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetTransferEventMode(). */ - - uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestHWordExchange(). */ - - uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestByteExchange(). */ - - uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcByteExchange(). */ - - uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcAllocatedPort(). */ - - uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestAllocatedPort(). */ - - uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetLinkAllocatedPort(). */ - - uint32_t LinkStepMode; /*!< This field specify the link step mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetLinkStepMode(). */ - - uint32_t SrcAddrUpdateMode; /*!< This field specify the source address update mode. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcAddrUpdate(). */ - - uint32_t DestAddrUpdateMode; /*!< This field specify the destination address update mode. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestAddrUpdate(). */ - - uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value Between 0 to 0x00001FFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetSrcAddrUpdateValue(). */ - - uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value Between 0 to 0x00001FFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetDestAddrUpdateValue(). */ - - uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkRptSrcAddrUpdate(). */ - - uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value of @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkRptDestAddrUpdate(). */ - - uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value Between 0 to 0x0000FFFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkRptSrcAddrUpdateValue(). */ - - uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. - Programming this field is mandatory only for 2D addressing channels. - This parameter can be a value Between 0 to 0x0000FFFF. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetBlkRptDestAddrUpdateValue(). */ - - uint32_t LinkedListBaseAddr; /*!< This field specify the linked list base address. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value Between 0 to 0xFFFF0000 (where the 4 first - bytes are always forced to 0). - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetLinkedListBaseAddr(). */ - - uint32_t LinkedListAddrOffset; /*!< Specifies the linked list address offset. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value Between 0 to 0x0000FFFC. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetLinkedListAddrOffset(). */ - -} LL_DMA_InitTypeDef; - - -/** - * @brief LL DMA init linked list structure definition. - */ -typedef struct -{ - uint32_t Priority; /*!< This field specify the channel priority level. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY_LEVEL. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetChannelPriorityLevel(). */ - - uint32_t LinkStepMode; /*!< This field specify the link step mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_LINK_STEP_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetLinkStepMode(). */ - - uint32_t LinkAllocatedPort; /*!< This field specify the linked-list allocated port. - Programming this field is not mandatory for LPDMA channels. - This parameter can be a value of @ref DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetLinkAllocatedPort(). */ - - uint32_t TransferEventMode; /*!< This field specify the transfer event mode. - Programming this field is mandatory for all available DMA channels. - This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. - This feature can be modified afterwards using unitary function - @ref LL_DMA_SetTransferEventMode(). */ -} LL_DMA_InitLinkedListTypeDef; - - -/** - * @brief LL DMA node init structure definition. - */ -typedef struct -{ - /* CTR1 register fields ****************************************************** - If any CTR1 fields need to be updated comparing to previous node, it is - mandatory to update the new value in CTR1 register fields and enable update - CTR1 register in UpdateRegisters fields if it is not enabled in the - previous node. - - If the node to be created is for LPDMA channels, there is no need to fill - the following fields for CTR1 register : - - DestAllocatedPort. - - DestHWordExchange. - - DestByteExchange. - - DestBurstLength. - - SrcAllocatedPort. - - SrcByteExchange. - - SrcBurstLength. - - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t DestSecure; /*!< This field specify the destination secure. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE. */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - uint32_t DestAllocatedPort; /*!< This field specify the destination allocated port. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_ALLOCATED_PORT. */ - - uint32_t DestHWordExchange; /*!< This field specify the destination half word exchange. - This parameter can be a value of @ref DMA_LL_EC_DEST_HALFWORD_EXCHANGE. */ - - uint32_t DestByteExchange; /*!< This field specify the destination byte exchange. - This parameter can be a value of @ref DMA_LL_EC_DEST_BYTE_EXCHANGE. */ - - uint32_t DestBurstLength; /*!< This field specify the destination burst length of transfer in bytes. - This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ - - uint32_t DestIncMode; /*!< This field specify the destination increment mode. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_INCREMENT_MODE. */ - - uint32_t DestDataWidth; /*!< This field specify the destination data width. - This parameter can be a value of @ref DMA_LL_EC_DESTINATION_DATA_WIDTH. */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t SrcSecure; /*!< This field specify the source secure. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE. */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - uint32_t SrcAllocatedPort; /*!< This field specify the source allocated port. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_ALLOCATED_PORT. */ - - uint32_t SrcByteExchange; /*!< This field specify the source byte exchange. - This parameter can be a value of @ref DMA_LL_EC_SRC_BYTE_EXCHANGE. */ - - uint32_t DataAlignment; /*!< This field specify the transfer data alignment. - This parameter can be a value of @ref DMA_LL_EC_DATA_ALIGNMENT. */ - - uint32_t SrcBurstLength; /*!< This field specify the source burst length of transfer in bytes. - This parameter must be a value between Min_Data = 1 and Max_Data = 64. */ - - uint32_t SrcIncMode; /*!< This field specify the source increment mode. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_INCREMENT_MODE. */ - - uint32_t SrcDataWidth; /*!< This field specify the source data width. - This parameter can be a value of @ref DMA_LL_EC_SOURCE_DATA_WIDTH. */ - - - /* CTR2 register fields ****************************************************** - If any CTR2 fields need to be updated comparing to previous node, it is - mandatory to update the new value in CTR2 register fields and enable update - CTR2 register in UpdateRegisters fields if it is not enabled in the - previous node. - - For all node created, filling all fields is mandatory. - */ - uint32_t TransferEventMode; /*!< This field specify the transfer event mode. - This parameter can be a value of @ref DMA_LL_EC_TRANSFER_EVENT_MODE. */ - - uint32_t TriggerPolarity; /*!< This field specify the trigger event polarity. - This parameter can be a value of @ref DMA_LL_EC_TRIGGER_POLARITY. */ - - uint32_t TriggerSelection; /*!< This field specify the trigger event selection. - This parameter can be a value of @ref DMA_LL_EC_TRIGGER_SELECTION. */ - - uint32_t TriggerMode; /*!< This field specify the trigger mode. - This parameter can be a value of @ref DMA_LL_EC_TRIGGER_MODE. */ - - uint32_t BlkHWRequest; /*!< This field specify the hardware request unity. - This parameter can be a value of @ref DMA_LL_EC_BLKHW_REQUEST. */ - - uint32_t Direction; /*!< This field specify the transfer direction. - This parameter can be a value of @ref DMA_LL_EC_TRANSFER_DIRECTION. */ - - uint32_t Request; /*!< This field specify the peripheral request selection. - This parameter can be a value of @ref DMA_LL_EC_REQUEST_SELECTION. */ - - - /* CBR1 register fields ****************************************************** - If any CBR1 fields need to be updated comparing to previous node, it is - mandatory to update the new value in CBR1 register fields and enable update - CBR1 register in UpdateRegisters fields if it is not enabled in the - previous node. - - If the node to be created is not for 2D addressing channels, there is no - need to fill the following fields for CBR1 register : - - BlkReptDestAddrUpdate. - - BlkRptSrcAddrUpdate. - - DestAddrUpdate. - - SrcAddrUpdate. - - BlkRptCount. - */ - uint32_t BlkRptDestAddrUpdateMode; /*!< This field specifies the block repeat destination address update mode. - This parameter can be a value of - @ref DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE. */ - - uint32_t BlkRptSrcAddrUpdateMode; /*!< This field specifies the block repeat source address update mode. - This parameter can be a value of - @ref DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE. */ - - uint32_t DestAddrUpdateMode; /*!< This field specify the Destination address update mode. - This parameter can be a value of @ref DMA_LL_EC_DEST_ADDR_UPDATE_MODE. */ - - uint32_t SrcAddrUpdateMode; /*!< This field specify the Source address update mode. - This parameter can be a value of @ref DMA_LL_EC_SRC_ADDR_UPDATE_MODE. */ - - uint32_t BlkRptCount; /*!< This field specify the number of repetitions of the current block. - This parameter can be a value between 1 and 2048 Min_Data = 0 - and Max_Data = 0x000007FF. */ - - uint32_t BlkDataLength; /*!< This field specify the length of a block transfer in bytes. - This parameter must be a value between Min_Data = 0 - and Max_Data = 0x0000FFFF. */ - - /* CSAR register fields ****************************************************** - If any CSAR fields need to be updated comparing to previous node, it is - mandatory to update the new value in CSAR register fields and enable update - CSAR register in UpdateRegisters fields if it is not enabled in the - previous node. - - For all node created, filling all fields is mandatory. - */ - uint32_t SrcAddress; /*!< This field specify the transfer source address. - This parameter must be a value between Min_Data = 0 - and Max_Data = 0xFFFFFFFF. */ - - - /* CDAR register fields ****************************************************** - If any CDAR fields need to be updated comparing to previous node, it is - mandatory to update the new value in CDAR register fields and enable update - CDAR register in UpdateRegisters fields if it is not enabled in the - previous node. - - For all node created, filling all fields is mandatory. - */ - uint32_t DestAddress; /*!< This field specify the transfer destination address. - This parameter must be a value between Min_Data = 0 - and Max_Data = 0xFFFFFFFF. */ - - /* CTR3 register fields ****************************************************** - If any CTR3 fields need to be updated comparing to previous node, it is - mandatory to update the new value in CTR3 register fields and enable update - CTR3 register in UpdateRegisters fields if it is not enabled in the - previous node. - - This register is used only for 2D addressing channels. - If used channel is linear addressing, this register will be overwritten by - CLLR register in memory. - When this register is enabled on UpdateRegisters and the selected channel - is linear addressing, LL APIs will discard this register update in memory. - */ - uint32_t DestAddrOffset; /*!< This field specifies the destination address offset. - This parameter can be a value Between 0 to 0x00001FFF. */ - - uint32_t SrcAddrOffset; /*!< This field specifies the source address offset. - This parameter can be a value Between 0 to 0x00001FFF. */ - - - /* CBR2 register fields ****************************************************** - If any CBR2 fields need to be updated comparing to previous node, it is - mandatory to update the new value in CBR2 register fields and enable update - CBR2 register in UpdateRegisters fields if it is not enabled in the - previous node. - - This register is used only for 2D addressing channels. - If used channel is linear addressing, this register will be discarded in - memory. When this register is enabled on UpdateRegisters and the selected - channel is linear addressing, LL APIs will discard this register update in - memory. - */ - uint32_t BlkRptDestAddrOffset; /*!< This field specifies the block repeat destination address offset. - This parameter can be a value Between 0 to 0x0000FFFF. */ - - uint32_t BlkRptSrcAddrOffset; /*!< This field specifies the block repeat source address offset. - This parameter can be a value Between 0 to 0x0000FFFF. */ - - /* CLLR register fields ****************************************************** - If any CLLR fields need to be updated comparing to previous node, it is - mandatory to update the new value in CLLR register fields and enable update - CLLR register in UpdateRegisters fields if it is not enabled in the - previous node. - - If used channel is linear addressing, there is no need to enable/disable - CTR3 and CBR2 register in UpdateRegisters fields as they will be discarded - by LL APIs. - */ - uint32_t UpdateRegisters; /*!< Specifies the linked list register update. - This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE. */ - - /* DMA Node type field ******************************************************* - This parameter defines node types as node size and node content varies - between channels. - Thanks to this fields, linked list queue could be created independently - from channel selection. So, one queue could be executed by all DMA channels. - */ - uint32_t NodeType; /*!< Specifies the node type to be created. - This parameter can be a value of @ref DMA_LL_EC_LINKEDLIST_NODE_TYPE. */ -} LL_DMA_InitNodeTypeDef; - -/** - * @brief LL DMA linked list node structure definition. - * @note For 2D addressing channels, the maximum node size is : - * (4 Bytes * 8 registers = 32 Bytes). - * For GPDMA linear addressing channels, the maximum node size is : - * (4 Bytes * 6 registers = 24 Bytes). - * For LPDMA linear addressing channels, the maximum node size is : - * (4 Bytes * 6 registers = 24 Bytes). - */ -typedef struct -{ - __IO uint32_t LinkRegisters[8U]; - -} LL_DMA_LinkNodeTypeDef; -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ - -/** @defgroup DMA_LL_EC_CHANNEL Channel - * @{ - */ -#define LL_DMA_CHANNEL_0 (0x00U) -#define LL_DMA_CHANNEL_1 (0x01U) -#define LL_DMA_CHANNEL_2 (0x02U) -#define LL_DMA_CHANNEL_3 (0x03U) -#define LL_DMA_CHANNEL_4 (0x04U) -#define LL_DMA_CHANNEL_5 (0x05U) -#define LL_DMA_CHANNEL_6 (0x06U) -#define LL_DMA_CHANNEL_7 (0x07U) -#define LL_DMA_CHANNEL_8 (0x08U) -#define LL_DMA_CHANNEL_9 (0x09U) -#define LL_DMA_CHANNEL_10 (0x0AU) -#define LL_DMA_CHANNEL_11 (0x0BU) -#define LL_DMA_CHANNEL_12 (0x0CU) -#define LL_DMA_CHANNEL_13 (0x0DU) -#define LL_DMA_CHANNEL_14 (0x0EU) -#define LL_DMA_CHANNEL_15 (0x0FU) -#if defined (USE_FULL_LL_DRIVER) -#define LL_DMA_CHANNEL_ALL (0x10U) -#endif /* USE_FULL_LL_DRIVER */ -/** - * @} - */ - -#if defined (USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EC_CLLR_OFFSET CLLR offset - * @{ - */ -#define LL_DMA_CLLR_OFFSET0 (0x00U) -#define LL_DMA_CLLR_OFFSET1 (0x01U) -#define LL_DMA_CLLR_OFFSET2 (0x02U) -#define LL_DMA_CLLR_OFFSET3 (0x03U) -#define LL_DMA_CLLR_OFFSET4 (0x04U) -#define LL_DMA_CLLR_OFFSET5 (0x05U) -#define LL_DMA_CLLR_OFFSET6 (0x06U) -#define LL_DMA_CLLR_OFFSET7 (0x07U) -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup DMA_LL_EC_PRIORITY_LEVEL Priority Level - * @{ - */ -#define LL_DMA_LOW_PRIORITY_LOW_WEIGHT 0x00000000U /*!< Priority level : Low Priority, Low Weight */ -#define LL_DMA_LOW_PRIORITY_MID_WEIGHT DMA_CCR_PRIO_0 /*!< Priority level : Low Priority, Mid Weight */ -#define LL_DMA_LOW_PRIORITY_HIGH_WEIGHT DMA_CCR_PRIO_1 /*!< Priority level : Low Priority, High Weight */ -#define LL_DMA_HIGH_PRIORITY DMA_CCR_PRIO /*!< Priority level : High Priority */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_LINKED_LIST_ALLOCATED_PORT Linked List Allocated Port - * @{ - */ -#define LL_DMA_LINK_ALLOCATED_PORT0 0x00000000U /*!< Linked List Allocated Port 0 */ -#define LL_DMA_LINK_ALLOCATED_PORT1 DMA_CCR_LAP /*!< Linked List Allocated Port 1 */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_LINK_STEP_MODE Link Step Mode - * @{ - */ -#define LL_DMA_LSM_FULL_EXECUTION 0x00000000U /*!< Channel execute the full linked list */ -#define LL_DMA_LSM_1LINK_EXECUTION DMA_CCR_LSM /*!< Channel execute one node of the linked list */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DEST_HALFWORD_EXCHANGE Destination Half-Word Exchange - * @{ - */ -#define LL_DMA_DEST_HALFWORD_PRESERVE 0x00000000U /*!< No destination Half-Word exchange when destination data width - is word */ -#define LL_DMA_DEST_HALFWORD_EXCHANGE DMA_CTR1_DHX /*!< Destination Half-Word exchange when destination data width - is word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DEST_BYTE_EXCHANGE Destination Byte Exchange - * @{ - */ -#define LL_DMA_DEST_BYTE_PRESERVE 0x00000000U /*!< No destination Byte exchange when destination data width > Byte */ -#define LL_DMA_DEST_BYTE_EXCHANGE DMA_CTR1_DBX /*!< Destination Byte exchange when destination data width > Byte */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_SRC_BYTE_EXCHANGE Source Byte Exchange - * @{ - */ -#define LL_DMA_SRC_BYTE_PRESERVE 0x00000000U /*!< No source Byte exchange when source data width is word */ -#define LL_DMA_SRC_BYTE_EXCHANGE DMA_CTR1_SBX /*!< Source Byte exchange when source data width is word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_SOURCE_ALLOCATED_PORT Source Allocated Port - * @{ - */ -#define LL_DMA_SRC_ALLOCATED_PORT0 0x00000000U /*!< Source Allocated Port 0 */ -#define LL_DMA_SRC_ALLOCATED_PORT1 DMA_CTR1_SAP /*!< Source Allocated Port 1 */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DESTINATION_ALLOCATED_PORT Destination Allocated Port - * @{ - */ -#define LL_DMA_DEST_ALLOCATED_PORT0 0x00000000U /*!< Destination Allocated Port 0 */ -#define LL_DMA_DEST_ALLOCATED_PORT1 DMA_CTR1_DAP /*!< Destination Allocated Port 1 */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DESTINATION_INCREMENT_MODE Destination Increment Mode - * @{ - */ -#define LL_DMA_DEST_FIXED 0x00000000U /*!< Destination fixed single/burst */ -#define LL_DMA_DEST_INCREMENT DMA_CTR1_DINC /*!< Destination incremented single/burst */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DESTINATION_DATA_WIDTH Destination Data Width - * @{ - */ -#define LL_DMA_DEST_DATAWIDTH_BYTE 0x00000000U /*!< Destination Data Width : Byte */ -#define LL_DMA_DEST_DATAWIDTH_HALFWORD DMA_CTR1_DDW_LOG2_0 /*!< Destination Data Width : HalfWord */ -#define LL_DMA_DEST_DATAWIDTH_WORD DMA_CTR1_DDW_LOG2_1 /*!< Destination Data Width : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DATA_ALIGNMENT Data Alignment - * @{ - */ -#define LL_DMA_DATA_ALIGN_ZEROPADD 0x00000000U /*!< If src data width < dest data width : - => Right Aligned padded with 0 up to destination - data width. - If src data width > dest data width : - => Right Aligned Left Truncated down to destination - data width. */ -#define LL_DMA_DATA_ALIGN_SIGNEXTPADD DMA_CTR1_PAM_0 /*!< If src data width < dest data width : - => Right Aligned padded with sign extended up to destination - data width. - If src data width > dest data width : - => Left Aligned Right Truncated down to the destination - data width */ -#define LL_DMA_DATA_PACK_UNPACK DMA_CTR1_PAM_1 /*!< If src data width < dest data width : - => Packed at the destination data width (Not Available - for LPDMA) - If src data width > dest data width : - => Unpacked at the destination data width (Not Available - for LPDMA) */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_SOURCE_INCREMENT_MODE Source Increment Mode - * @{ - */ -#define LL_DMA_SRC_FIXED 0x00000000U /*!< Source fixed single/burst */ -#define LL_DMA_SRC_INCREMENT DMA_CTR1_SINC /*!< Source incremented single/burst */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_SOURCE_DATA_WIDTH Source Data Width - * @{ - */ -#define LL_DMA_SRC_DATAWIDTH_BYTE 0x00000000U /*!< Source Data Width : Byte */ -#define LL_DMA_SRC_DATAWIDTH_HALFWORD DMA_CTR1_SDW_LOG2_0 /*!< Source Data Width : HalfWord */ -#define LL_DMA_SRC_DATAWIDTH_WORD DMA_CTR1_SDW_LOG2_1 /*!< Source Data Width : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_BLKHW_REQUEST Block Hardware Request - * @{ - */ -#define LL_DMA_HWREQUEST_SINGLEBURST 0x00000000U /*!< Hardware request is driven by a peripheral with a hardware - request/acknowledge protocol at a burst level */ -#define LL_DMA_HWREQUEST_BLK DMA_CTR2_BREQ /*!< Hardware request is driven by a peripheral with a hardware - request/acknowledge protocol at a block level */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_TRANSFER_EVENT_MODE Transfer Event Mode - * @{ - */ -#define LL_DMA_TCEM_BLK_TRANSFER 0x00000000U /*!< The TC (and the HT) event is generated at the - (respectively half) end of each block */ -#define LL_DMA_TCEM_RPT_BLK_TRANSFER DMA_CTR2_TCEM_0 /*!< The TC (and the HT) event is generated at the - (respectively half) end of the repeated block */ -#define LL_DMA_TCEM_EACH_LLITEM_TRANSFER DMA_CTR2_TCEM_1 /*!< The TC (and the HT) event is generated at the - (respectively half) end of each linked-list item */ -#define LL_DMA_TCEM_LAST_LLITEM_TRANSFER DMA_CTR2_TCEM /*!< The TC (and the HT) event is generated at the - (respectively half) end of the last linked-list item */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_TRIGGER_POLARITY Trigger Polarity - * @{ - */ -#define LL_DMA_TRIG_POLARITY_MASKED 0x00000000U /*!< No trigger of the selected DMA request. - Masked trigger event */ -#define LL_DMA_TRIG_POLARITY_RISING DMA_CTR2_TRIGPOL_0 /*!< Trigger of the selected DMA request on the rising - edge of the selected trigger event input */ -#define LL_DMA_TRIG_POLARITY_FALLING DMA_CTR2_TRIGPOL_1 /*!< Trigger of the selected DMA request on the falling - edge of the selected trigger event input */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_TRIGGER_MODE Transfer Trigger Mode - * @{ - */ -#define LL_DMA_TRIGM_BLK_TRANSFER 0x00000000U /*!< A block transfer is conditioned by (at least) - one hit trigger */ -#define LL_DMA_TRIGM_RPT_BLK_TRANSFER DMA_CTR2_TRIGM_0 /*!< A repeated block transfer is conditioned by (at least) - one hit trigger */ -#define LL_DMA_TRIGM_LLI_LINK_TRANSFER DMA_CTR2_TRIGM_1 /*!< A LLI link transfer is conditioned by (at least) - one hit trigger */ -#define LL_DMA_TRIGM_SINGLBURST_TRANSFER DMA_CTR2_TRIGM /*!< A Single/Burst transfer is conditioned by (at least) - one hit trigger */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_TRANSFER_DIRECTION Transfer Direction - * @{ - */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CTR2_SWREQ /*!< Memory to memory direction */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CTR2_DREQ /*!< Memory to peripheral direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_BLK_RPT_SRC_ADDR_UPDATE_MODE Block Repeat Source Address Update Mode - * @{ - */ -#define LL_DMA_BLKRPT_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each block - transfer by source update value */ -#define LL_DMA_BLKRPT_SRC_ADDR_DECREMENT DMA_CBR1_BRSDEC /*!< Source address pointer is decremented after each block - transfer by source update value */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_BLK_RPT_DEST_ADDR_UPDATE_MODE Block Repeat Destination Address Update Mode - * @{ - */ -#define LL_DMA_BLKRPT_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address is incremented after each block - transfer by destination update value */ -#define LL_DMA_BLKRPT_DEST_ADDR_DECREMENT DMA_CBR1_BRDDEC /*!< Destination address is decremented after each block - transfer by destination update value */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_SRC_ADDR_UPDATE_MODE Burst Source Address Update Mode - * @{ - */ -#define LL_DMA_BURST_SRC_ADDR_INCREMENT 0x00000000U /*!< Source address pointer is incremented after each burst - transfer by source update value */ -#define LL_DMA_BURST_SRC_ADDR_DECREMENT DMA_CBR1_SDEC /*!< Source address pointer is decremented after each burst - transfer by source update value */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DEST_ADDR_UPDATE_MODE Burst Destination Address Update Mode - * @{ - */ -#define LL_DMA_BURST_DEST_ADDR_INCREMENT 0x00000000U /*!< Destination address pointer is incremented after each - burst transfer by destination update value */ -#define LL_DMA_BURST_DEST_ADDR_DECREMENT DMA_CBR1_DDEC /*!< Destination address pointer is decremented after each - burst transfer by destination update value */ -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute - * @{ - */ -#define LL_DMA_CHANNEL_NSEC 0x00000000U /*!< NSecure channel */ -#define LL_DMA_CHANNEL_SEC 0x00000001U /*!< Secure channel */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_SOURCE_SECURITY_ATTRIBUTE Source Security Attribute - * @{ - */ -#define LL_DMA_CHANNEL_SRC_NSEC 0x00000000U /*!< NSecure transfer from the source */ -#define LL_DMA_CHANNEL_SRC_SEC DMA_CTR1_SSEC /*!< Secure transfer from the source */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DESTINATION_SECURITY_ATTRIBUTE Destination Security Attribute - * @{ - */ -#define LL_DMA_CHANNEL_DEST_NSEC 0x00000000U /*!< NSecure transfer from the destination */ -#define LL_DMA_CHANNEL_DEST_SEC DMA_CTR1_DSEC /*!< Secure transfer from the destination */ -/** - * @} - */ -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** @defgroup DMA_LL_EC_LINKEDLIST_NODE_TYPE Linked list node type - * @{ - */ -#define LL_DMA_LPDMA_LINEAR_NODE 0x00U /*!< LPDMA node : linear addressing node */ -#define LL_DMA_GPDMA_LINEAR_NODE 0x01U /*!< GPDMA node : linear addressing node */ -#define LL_DMA_GPDMA_2D_NODE 0x02U /*!< GPDMA node : 2 dimension addressing node */ - -/** - * @} - */ - -/** @defgroup DMA_LL_EC_LINKEDLIST_REGISTER_UPDATE Linked list register update - * @{ - */ -#define LL_DMA_UPDATE_CTR1 DMA_CLLR_UT1 /*!< Update CTR1 register from memory : - available for all DMA channels */ -#define LL_DMA_UPDATE_CTR2 DMA_CLLR_UT2 /*!< Update CTR2 register from memory : - available for all DMA channels */ -#define LL_DMA_UPDATE_CBR1 DMA_CLLR_UB1 /*!< Update CBR1 register from memory : - available for all DMA channels */ -#define LL_DMA_UPDATE_CSAR DMA_CLLR_USA /*!< Update CSAR register from memory : - available for all DMA channels */ -#define LL_DMA_UPDATE_CDAR DMA_CLLR_UDA /*!< Update CDAR register from memory : - available for all DMA channels */ -#define LL_DMA_UPDATE_CTR3 DMA_CLLR_UT3 /*!< Update CTR3 register from memory : - available only for 2D addressing DMA channels */ -#define LL_DMA_UPDATE_CBR2 DMA_CLLR_UB2 /*!< Update CBR2 register from memory : - available only for 2D addressing DMA channels */ -#define LL_DMA_UPDATE_CLLR DMA_CLLR_ULL /*!< Update CLLR register from memory : - available for all DMA channels */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_REQUEST_SELECTION Request Selection - * @{ - */ -/* GPDMA1 Hardware Requests */ -#define LL_GPDMA1_REQUEST_ADC1 0U /*!< GPDMA1 HW Request is ADC1 */ -#define LL_GPDMA1_REQUEST_ADC4 1U /*!< GPDMA1 HW Request is ADC4 */ -#define LL_GPDMA1_REQUEST_DAC1_CH1 2U /*!< GPDMA1 HW Request is DAC1_CH1 */ -#define LL_GPDMA1_REQUEST_DAC1_CH2 3U /*!< GPDMA1 HW Request is DAC1_CH2 */ -#define LL_GPDMA1_REQUEST_TIM6_UP 4U /*!< GPDMA1 HW Request is TIM6_UP */ -#define LL_GPDMA1_REQUEST_TIM7_UP 5U /*!< GPDMA1 HW Request is TIM7_UP */ -#define LL_GPDMA1_REQUEST_SPI1_RX 6U /*!< GPDMA1 HW Request is SPI1_RX */ -#define LL_GPDMA1_REQUEST_SPI1_TX 7U /*!< GPDMA1 HW Request is SPI1_TX */ -#define LL_GPDMA1_REQUEST_SPI2_RX 8U /*!< GPDMA1 HW Request is SPI2_RX */ -#define LL_GPDMA1_REQUEST_SPI2_TX 9U /*!< GPDMA1 HW Request is SPI2_TX */ -#define LL_GPDMA1_REQUEST_SPI3_RX 10U /*!< GPDMA1 HW Request is SPI3_RX */ -#define LL_GPDMA1_REQUEST_SPI3_TX 11U /*!< GPDMA1 HW Request is SPI3_TX */ -#define LL_GPDMA1_REQUEST_I2C1_RX 12U /*!< GPDMA1 HW Request is I2C1_RX */ -#define LL_GPDMA1_REQUEST_I2C1_TX 13U /*!< GPDMA1 HW Request is I2C1_TX */ -#define LL_GPDMA1_REQUEST_I2C1_EVC 14U /*!< GPDMA1 HW Request is I2C1_EVC */ -#define LL_GPDMA1_REQUEST_I2C2_RX 15U /*!< GPDMA1 HW Request is I2C2_RX */ -#define LL_GPDMA1_REQUEST_I2C2_TX 16U /*!< GPDMA1 HW Request is I2C2_TX */ -#define LL_GPDMA1_REQUEST_I2C2_EVC 17U /*!< GPDMA1 HW Request is I2C2_EVC */ -#define LL_GPDMA1_REQUEST_I2C3_RX 18U /*!< GPDMA1 HW Request is I2C3_RX */ -#define LL_GPDMA1_REQUEST_I2C3_TX 19U /*!< GPDMA1 HW Request is I2C3_TX */ -#define LL_GPDMA1_REQUEST_I2C3_EVC 20U /*!< GPDMA1 HW Request is I2C3_EVC */ -#define LL_GPDMA1_REQUEST_I2C4_RX 21U /*!< GPDMA1 HW Request is I2C4_RX */ -#define LL_GPDMA1_REQUEST_I2C4_TX 22U /*!< GPDMA1 HW Request is I2C4_TX */ -#define LL_GPDMA1_REQUEST_I2C4_EVC 23U /*!< GPDMA1 HW Request is I2C4_EVC */ -#define LL_GPDMA1_REQUEST_USART1_RX 24U /*!< GPDMA1 HW Request is USART1_RX */ -#define LL_GPDMA1_REQUEST_USART1_TX 25U /*!< GPDMA1 HW Request is USART1_TX */ -#if defined(USART2) -#define LL_GPDMA1_REQUEST_USART2_RX 26U /*!< GPDMA1 HW Request is USART2_RX */ -#define LL_GPDMA1_REQUEST_USART2_TX 27U /*!< GPDMA1 HW Request is USART2_TX */ -#endif /* USART2 */ -#define LL_GPDMA1_REQUEST_USART3_RX 28U /*!< GPDMA1 HW Request is USART3_RX */ -#define LL_GPDMA1_REQUEST_USART3_TX 29U /*!< GPDMA1 HW Request is USART3_TX */ -#define LL_GPDMA1_REQUEST_UART4_RX 30U /*!< GPDMA1 HW Request is UART4_RX */ -#define LL_GPDMA1_REQUEST_UART4_TX 31U /*!< GPDMA1 HW Request is UART4_TX */ -#define LL_GPDMA1_REQUEST_UART5_RX 32U /*!< GPDMA1 HW Request is UART5_RX */ -#define LL_GPDMA1_REQUEST_UART5_TX 33U /*!< GPDMA1 HW Request is UART5_TX */ -#define LL_GPDMA1_REQUEST_LPUART1_RX 34U /*!< GPDMA1 HW Request is LPUART1_RX */ -#define LL_GPDMA1_REQUEST_LPUART1_TX 35U /*!< GPDMA1 HW Request is LPUART1_TX */ -#define LL_GPDMA1_REQUEST_SAI1_A 36U /*!< GPDMA1 HW Request is SAI1_A */ -#define LL_GPDMA1_REQUEST_SAI1_B 37U /*!< GPDMA1 HW Request is SAI1_B */ -#if defined(SAI2) -#define LL_GPDMA1_REQUEST_SAI2_A 38U /*!< GPDMA1 HW Request is SAI2_A */ -#define LL_GPDMA1_REQUEST_SAI2_B 39U /*!< GPDMA1 HW Request is SAI2_B */ -#endif /* SAI2 */ -#define LL_GPDMA1_REQUEST_OCTOSPI1 40U /*!< GPDMA1 HW Request is OCTOSPI1 */ -#if defined(OCTOSPI2) -#define LL_GPDMA1_REQUEST_OCTOSPI2 41U /*!< GPDMA1 HW Request is OCTOSPI2 */ -#endif /* OCTOSPI2 */ -#define LL_GPDMA1_REQUEST_TIM1_CH1 42U /*!< GPDMA1 HW Request is TIM1_CH1 */ -#define LL_GPDMA1_REQUEST_TIM1_CH2 43U /*!< GPDMA1 HW Request is TIM1_CH2 */ -#define LL_GPDMA1_REQUEST_TIM1_CH3 44U /*!< GPDMA1 HW Request is TIM1_CH3 */ -#define LL_GPDMA1_REQUEST_TIM1_CH4 45U /*!< GPDMA1 HW Request is TIM1_CH4 */ -#define LL_GPDMA1_REQUEST_TIM1_UP 46U /*!< GPDMA1 HW Request is TIM1_UP */ -#define LL_GPDMA1_REQUEST_TIM1_TRIG 47U /*!< GPDMA1 HW Request is TIM1_TRIG */ -#define LL_GPDMA1_REQUEST_TIM1_COM 48U /*!< GPDMA1 HW Request is TIM1_COM */ -#define LL_GPDMA1_REQUEST_TIM8_CH1 49U /*!< GPDMA1 HW Request is TIM8_CH1 */ -#define LL_GPDMA1_REQUEST_TIM8_CH2 50U /*!< GPDMA1 HW Request is TIM8_CH2 */ -#define LL_GPDMA1_REQUEST_TIM8_CH3 51U /*!< GPDMA1 HW Request is TIM8_CH3 */ -#define LL_GPDMA1_REQUEST_TIM8_CH4 52U /*!< GPDMA1 HW Request is TIM8_CH4 */ -#define LL_GPDMA1_REQUEST_TIM8_UP 53U /*!< GPDMA1 HW Request is TIM8_UP */ -#define LL_GPDMA1_REQUEST_TIM8_TRIG 54U /*!< GPDMA1 HW Request is TIM8_TRIG */ -#define LL_GPDMA1_REQUEST_TIM8_COM 55U /*!< GPDMA1 HW Request is TIM8_COM */ -#define LL_GPDMA1_REQUEST_TIM2_CH1 56U /*!< GPDMA1 HW Request is TIM2_CH1 */ -#define LL_GPDMA1_REQUEST_TIM2_CH2 57U /*!< GPDMA1 HW Request is TIM2_CH2 */ -#define LL_GPDMA1_REQUEST_TIM2_CH3 58U /*!< GPDMA1 HW Request is TIM2_CH3 */ -#define LL_GPDMA1_REQUEST_TIM2_CH4 59U /*!< GPDMA1 HW Request is TIM2_CH4 */ -#define LL_GPDMA1_REQUEST_TIM2_UP 60U /*!< GPDMA1 HW Request is TIM2_UP */ -#define LL_GPDMA1_REQUEST_TIM3_CH1 61U /*!< GPDMA1 HW Request is TIM3_CH1 */ -#define LL_GPDMA1_REQUEST_TIM3_CH2 62U /*!< GPDMA1 HW Request is TIM3_CH2 */ -#define LL_GPDMA1_REQUEST_TIM3_CH3 63U /*!< GPDMA1 HW Request is TIM3_CH3 */ -#define LL_GPDMA1_REQUEST_TIM3_CH4 64U /*!< GPDMA1 HW Request is TIM3_CH4 */ -#define LL_GPDMA1_REQUEST_TIM3_UP 65U /*!< GPDMA1 HW Request is TIM3_UP */ -#define LL_GPDMA1_REQUEST_TIM3_TRIG 66U /*!< GPDMA1 HW Request is TIM3_TRIG */ -#define LL_GPDMA1_REQUEST_TIM4_CH1 67U /*!< GPDMA1 HW Request is TIM4_CH1 */ -#define LL_GPDMA1_REQUEST_TIM4_CH2 68U /*!< GPDMA1 HW Request is TIM4_CH2 */ -#define LL_GPDMA1_REQUEST_TIM4_CH3 69U /*!< GPDMA1 HW Request is TIM4_CH3 */ -#define LL_GPDMA1_REQUEST_TIM4_CH4 70U /*!< GPDMA1 HW Request is TIM4_CH4 */ -#define LL_GPDMA1_REQUEST_TIM4_UP 71U /*!< GPDMA1 HW Request is TIM4_UP */ -#define LL_GPDMA1_REQUEST_TIM5_CH1 72U /*!< GPDMA1 HW Request is TIM5_CH1 */ -#define LL_GPDMA1_REQUEST_TIM5_CH2 73U /*!< GPDMA1 HW Request is TIM5_CH2 */ -#define LL_GPDMA1_REQUEST_TIM5_CH3 74U /*!< GPDMA1 HW Request is TIM5_CH3 */ -#define LL_GPDMA1_REQUEST_TIM5_CH4 75U /*!< GPDMA1 HW Request is TIM5_CH4 */ -#define LL_GPDMA1_REQUEST_TIM5_UP 76U /*!< GPDMA1 HW Request is TIM5_UP */ -#define LL_GPDMA1_REQUEST_TIM5_TRIG 77U /*!< GPDMA1 HW Request is TIM5_TRIG */ -#define LL_GPDMA1_REQUEST_TIM15_CH1 78U /*!< GPDMA1 HW Request is TIM15_CH1 */ -#define LL_GPDMA1_REQUEST_TIM15_UP 79U /*!< GPDMA1 HW Request is TIM15_UP */ -#define LL_GPDMA1_REQUEST_TIM15_TRIG 80U /*!< GPDMA1 HW Request is TIM15_TRIG */ -#define LL_GPDMA1_REQUEST_TIM15_COM 81U /*!< GPDMA1 HW Request is TIM15_COM */ -#define LL_GPDMA1_REQUEST_TIM16_CH1 82U /*!< GPDMA1 HW Request is TIM16_CH1 */ -#define LL_GPDMA1_REQUEST_TIM16_UP 83U /*!< GPDMA1 HW Request is TIM16_UP */ -#define LL_GPDMA1_REQUEST_TIM17_CH1 84U /*!< GPDMA1 HW Request is TIM17_CH1 */ -#define LL_GPDMA1_REQUEST_TIM17_UP 85U /*!< GPDMA1 HW Request is TIM17_UP */ -#define LL_GPDMA1_REQUEST_DCMI_PSSI 86U /*!< GPDMA1 HW Request is DCMI_PSSI */ -#define LL_GPDMA1_REQUEST_AES_IN 87U /*!< GPDMA1 HW Request is AES_IN */ -#define LL_GPDMA1_REQUEST_AES_OUT 88U /*!< GPDMA1 HW Request is AES_OUT */ -#define LL_GPDMA1_REQUEST_HASH_IN 89U /*!< GPDMA1 HW Request is HASH_IN */ -#if defined(UCPD1) -#define LL_GPDMA1_REQUEST_UCPD1_TX 90U /*!< GPDMA1 HW Request is UCPD1_TX */ -#define LL_GPDMA1_REQUEST_UCPD1_RX 91U /*!< GPDMA1 HW Request is UCPD1_RX */ -#endif /* UCPD1 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT0 92U /*!< GPDMA1 HW Request is MDF1_FLT0 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT1 93U /*!< GPDMA1 HW Request is MDF1_FLT1 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT2 94U /*!< GPDMA1 HW Request is MDF1_FLT2 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT3 95U /*!< GPDMA1 HW Request is MDF1_FLT3 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT4 96U /*!< GPDMA1 HW Request is MDF1_FLT4 */ -#define LL_GPDMA1_REQUEST_MDF1_FLT5 97U /*!< GPDMA1 HW Request is MDF1_FLT5 */ -#define LL_GPDMA1_REQUEST_ADF1_FLT0 98U /*!< GPDMA1 HW Request is ADF1_FLT0 */ -#define LL_GPDMA1_REQUEST_FMAC_READ 99U /*!< GPDMA1 HW Request is FMAC_READ */ -#define LL_GPDMA1_REQUEST_FMAC_WRITE 100U /*!< GPDMA1 HW Request is FMAC_WRITE */ -#define LL_GPDMA1_REQUEST_CORDIC_READ 101U /*!< GPDMA1 HW Request is CORDIC_READ */ -#define LL_GPDMA1_REQUEST_CORDIC_WRITE 102U /*!< GPDMA1 HW Request is CORDIC_WRITE */ -#define LL_GPDMA1_REQUEST_SAES_IN 103U /*!< GPDMA1 HW Request is SAES_IN */ -#define LL_GPDMA1_REQUEST_SAES_OUT 104U /*!< GPDMA1 HW Request is SAES_OUT */ -#define LL_GPDMA1_REQUEST_LPTIM1_IC1 105U /*!< GPDMA1 HW Request is LPTIM1_IC1 */ -#define LL_GPDMA1_REQUEST_LPTIM1_IC2 106U /*!< GPDMA1 HW Request is LPTIM1_IC2 */ -#define LL_GPDMA1_REQUEST_LPTIM1_UE 107U /*!< GPDMA1 HW Request is LPTIM1_UE */ -#define LL_GPDMA1_REQUEST_LPTIM2_IC1 108U /*!< GPDMA1 HW Request is LPTIM2_IC1 */ -#define LL_GPDMA1_REQUEST_LPTIM2_IC2 109U /*!< GPDMA1 HW Request is LPTIM2_IC2 */ -#define LL_GPDMA1_REQUEST_LPTIM2_UE 110U /*!< GPDMA1 HW Request is LPTIM2_UE */ -#define LL_GPDMA1_REQUEST_LPTIM3_IC1 111U /*!< GPDMA1 HW Request is LPTIM3_IC1 */ -#define LL_GPDMA1_REQUEST_LPTIM3_IC2 112U /*!< GPDMA1 HW Request is LPTIM3_IC2 */ -#define LL_GPDMA1_REQUEST_LPTIM3_UE 113U /*!< GPDMA1 HW Request is LPTIM3_UE */ -#if defined (HSPI1_BASE) -#define LL_GPDMA1_REQUEST_HSPI1 114U /*!< GPDMA1 HW request is HSPI1 */ -#endif /* HSPI1_BASE */ -#if defined (I2C5) -#define LL_GPDMA1_REQUEST_I2C5_RX 115U /*!< GPDMA1 HW request is I2C5_RX */ -#define LL_GPDMA1_REQUEST_I2C5_TX 116U /*!< GPDMA1 HW request is I2C5_TX */ -#define LL_GPDMA1_REQUEST_I2C5_EVC 117U /*!< GPDMA1 HW request is I2C5_EVC */ -#endif /* I2C5 */ -#if defined (I2C6) -#define LL_GPDMA1_REQUEST_I2C6_RX 118U /*!< GPDMA1 HW request is I2C6_RX */ -#define LL_GPDMA1_REQUEST_I2C6_TX 119U /*!< GPDMA1 HW request is I2C6_TX */ -#define LL_GPDMA1_REQUEST_I2C6_EVC 120U /*!< GPDMA1 HW request is I2C6_EVC */ -#endif /* I2C6 */ -#if defined (USART6) -#define LL_GPDMA1_REQUEST_USART6_RX 121U /*!< GPDMA1 HW request is USART6_RX */ -#define LL_GPDMA1_REQUEST_USART6_TX 122U /*!< GPDMA1 HW request is USART6_TX */ -#endif /* USART6 */ -#if defined (ADC2) -#define LL_GPDMA1_REQUEST_ADC2 123U /*!< GPDMA1 HW request is ADC2 */ -#endif /* ADC2 */ -#if defined (JPEG) -#define LL_GPDMA1_REQUEST_JPEG_RX 124U /*!< GPDMA1 HW request is JPEG_TX */ -#define LL_GPDMA1_REQUEST_JPEG_TX 125U /*!< GPDMA1 HW request is JPEG_RX */ -#endif /* JPEG */ - -/* GPDMA1 Hardware Requests aliases */ -#define LL_GPDMA1_REQUEST_DCMI LL_GPDMA1_REQUEST_DCMI_PSSI - -/* LPDMA1 Hardware Requests */ -#define LL_LPDMA1_REQUEST_LPUART1_RX 0U /*!< LPDMA1 HW Request is LPUART1_RX */ -#define LL_LPDMA1_REQUEST_LPUART1_TX 1U /*!< LPDMA1 HW Request is LPUART1_TX */ -#define LL_LPDMA1_REQUEST_SPI3_RX 2U /*!< LPDMA1 HW Request is SPI3_RX */ -#define LL_LPDMA1_REQUEST_SPI3_TX 3U /*!< LPDMA1 HW Request is SPI3_TX */ -#define LL_LPDMA1_REQUEST_I2C3_RX 4U /*!< LPDMA1 HW Request is I2C3_RX */ -#define LL_LPDMA1_REQUEST_I2C3_TX 5U /*!< LPDMA1 HW Request is I2C3_TX */ -#define LL_LPDMA1_REQUEST_I2C3_EVC 6U /*!< LPDMA1 HW Request is I2C3_EVC */ -#define LL_LPDMA1_REQUEST_ADC4 7U /*!< LPDMA1 HW Request is ADC4 */ -#define LL_LPDMA1_REQUEST_DAC1_CH1 8U /*!< LPDMA1 HW Request is DAC1_CH1 */ -#define LL_LPDMA1_REQUEST_DAC1_CH2 9U /*!< LPDMA1 HW Request is DAC1_CH2 */ -#define LL_LPDMA1_REQUEST_ADF1_FLT0 10U /*!< LPDMA1 HW Request is ADF1_FLT0 */ -#define LL_LPDMA1_REQUEST_LPTIM1_IC1 11U /*!< LPDMA1 HW Request is LPTIM1_IC1 */ -#define LL_LPDMA1_REQUEST_LPTIM1_IC2 12U /*!< LPDMA1 HW Request is LPTIM1_IC2 */ -#define LL_LPDMA1_REQUEST_LPTIM1_UE 13U /*!< LPDMA1 HW Request is LPTIM1_UE */ -#define LL_LPDMA1_REQUEST_LPTIM3_IC1 14U /*!< LPDMA1 HW Request is LPTIM3_IC1 */ -#define LL_LPDMA1_REQUEST_LPTIM3_IC2 15U /*!< LPDMA1 HW Request is LPTIM3_IC2 */ -#define LL_LPDMA1_REQUEST_LPTIM3_UE 16U /*!< LPDMA1 HW Request is LPTIM3_UE */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_TRIGGER_SELECTION Trigger Selection - * @{ - */ -/* GPDMA1 Hardware Triggers */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE0 0U /*!< GPDMA1 HW Trigger is EXTI_LINE0 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE1 1U /*!< GPDMA1 HW Trigger is EXTI_LINE1 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE2 2U /*!< GPDMA1 HW Trigger is EXTI_LINE2 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE3 3U /*!< GPDMA1 HW Trigger is EXTI_LINE3 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE4 4U /*!< GPDMA1 HW Trigger is EXTI_LINE4 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE5 5U /*!< GPDMA1 HW Trigger is EXTI_LINE5 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE6 6U /*!< GPDMA1 HW Trigger is EXTI_LINE6 */ -#define LL_GPDMA1_TRIGGER_EXTI_LINE7 7U /*!< GPDMA1 HW Trigger is EXTI_LINE7 */ -#define LL_GPDMA1_TRIGGER_TAMP_TRG1 8U /*!< GPDMA1 HW Trigger is TAMP_TRG1 */ -#define LL_GPDMA1_TRIGGER_TAMP_TRG2 9U /*!< GPDMA1 HW Trigger is TAMP_TRG2 */ -#define LL_GPDMA1_TRIGGER_TAMP_TRG3 10U /*!< GPDMA1 HW Trigger is TAMP_TRG3 */ -#define LL_GPDMA1_TRIGGER_LPTIM1_CH1 11U /*!< GPDMA1 HW Trigger is LPTIM1_CH1 */ -#define LL_GPDMA1_TRIGGER_LPTIM1_CH2 12U /*!< GPDMA1 HW Trigger is LPTIM1_CH2 */ -#define LL_GPDMA1_TRIGGER_LPTIM2_CH1 13U /*!< GPDMA1 HW Trigger is LPTIM2_CH1 */ -#define LL_GPDMA1_TRIGGER_LPTIM2_CH2 14U /*!< GPDMA1 HW Trigger is LPTIM2_CH2 */ -#define LL_GPDMA1_TRIGGER_LPTIM4_OUT 15U /*!< GPDMA1 HW Trigger is LPTIM4_OUT */ -#define LL_GPDMA1_TRIGGER_COMP1_OUT 16U /*!< GPDMA1 HW Trigger is COMP1_OUT */ -#if defined(COMP2) -#define LL_GPDMA1_TRIGGER_COMP2_OUT 17U /*!< GPDMA1 HW Trigger is COMP2_OUT */ -#endif /* COMP2 */ -#define LL_GPDMA1_TRIGGER_RTC_ALRA_TRG 18U /*!< GPDMA1 HW Trigger is RTC_ALRA_TRG */ -#define LL_GPDMA1_TRIGGER_RTC_ALRB_TRG 19U /*!< GPDMA1 HW Trigger is RTC_ALRB_TRG */ -#define LL_GPDMA1_TRIGGER_RTC_WUT_TRG 20U /*!< GPDMA1 HW Trigger is RTC_WUT_TRG */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< GPDMA1 HW Trigger is GPDMA1_CH0_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< GPDMA1 HW Trigger is GPDMA1_CH1_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF 24U /*!< GPDMA1 HW Trigger is GPDMA1_CH2_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF 25U /*!< GPDMA1 HW Trigger is GPDMA1_CH3_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF 26U /*!< GPDMA1 HW Trigger is GPDMA1_CH4_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF 27U /*!< GPDMA1 HW Trigger is GPDMA1_CH5_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF 28U /*!< GPDMA1 HW Trigger is GPDMA1_CH6_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF 29U /*!< GPDMA1 HW Trigger is GPDMA1_CH7_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF 30U /*!< GPDMA1 HW Trigger is GPDMA1_CH8_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF 31U /*!< GPDMA1 HW Trigger is GPDMA1_CH9_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF 32U /*!< GPDMA1 HW Trigger is GPDMA1_CH10_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF 33U /*!< GPDMA1 HW Trigger is GPDMA1_CH11_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF 34U /*!< GPDMA1 HW Trigger is GPDMA1_CH12_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF 35U /*!< GPDMA1 HW Trigger is GPDMA1_CH13_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF 36U /*!< GPDMA1 HW Trigger is GPDMA1_CH14_TCF */ -#define LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF 37U /*!< GPDMA1 HW Trigger is GPDMA1_CH15_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF 38U /*!< GPDMA1 HW Trigger is LPDMA1_CH0_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF 39U /*!< GPDMA1 HW Trigger is LPDMA1_CH1_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF 40U /*!< GPDMA1 HW Trigger is LPDMA1_CH2_TCF */ -#define LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF 41U /*!< GPDMA1 HW Trigger is LPDMA1_CH3_TCF */ -#define LL_GPDMA1_TRIGGER_TIM2_TRGO 42U /*!< GPDMA1 HW Trigger is TIM2_TRGO */ -#define LL_GPDMA1_TRIGGER_TIM15_TRGO 43U /*!< GPDMA1 HW Trigger is TIM15_TRGO */ -#define LL_GPDMA1_TRIGGER_ADC4_AWD1 57U /*!< GPDMA1 HW Trigger is ADC4_AWD1 */ -#define LL_GPDMA1_TRIGGER_ADC1_AWD1 58U /*!< GPDMA1 HW Trigger is ADC1_AWD1 */ -#if defined (TIM3_TRGO_TRIGGER_SUPPORT) -#define LL_GPDMA1_TRIGGER_TIM3_TRGO 44U /*!< GPDMA1 HW Trigger signal is TIM3_TRGO */ -#endif /* TIM3_TRGO_TRIGGER_SUPPORT */ -#if defined (TIM4_TRGO_TRIGGER_SUPPORT) -#define LL_GPDMA1_TRIGGER_TIM4_TRGO 45U /*!< GPDMA1 HW Trigger signal is TIM4_TRGO */ -#endif /* TIM4_TRGO_TRIGGER_SUPPORT */ -#if defined (TIM5_TRGO_TRIGGER_SUPPORT) -#define LL_GPDMA1_TRIGGER_TIM5_TRGO 46U /*!< GPDMA1 HW Trigger signal is TIM5_TRGO */ -#endif /* TIM5_TRGO_TRIGGER_SUPPORT */ -#if defined (LTDC) -#define LL_GPDMA1_TRIGGER_LTDC_LI 47U /*!< GPDMA1 HW Trigger signal is LTDC_LI */ -#endif /* LTDC */ -#if defined (DSI) -#define LL_GPDMA1_TRIGGER_DSI_TE 48U /*!< GPDMA1 HW Trigger signal is DSI_TE */ -#define LL_GPDMA1_TRIGGER_DSI_ER 49U /*!< GPDMA1 HW Trigger signal is DSI_ER */ -#endif /* DSI */ -#if defined (DMA2D) -#define LL_GPDMA1_TRIGGER_DMA2D_TC 50U /*!< GPDMA1 HW Trigger signal is DMA2D_TC */ -#define LL_GPDMA1_TRIGGER_DMA2D_CTC 51U /*!< GPDMA1 HW Trigger signal is DMA2D_CTC */ -#define LL_GPDMA1_TRIGGER_DMA2D_TW 52U /*!< GPDMA1 HW Trigger signal is DMA2D_TW */ -#endif /* DMA2D */ -#if defined (GPU2D) -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG0 53U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG0 */ -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG1 54U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG1 */ -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG2 55U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG2 */ -#define LL_GPDMA1_TRIGGER_GPU2D_FLAG3 56U /*!< GPDMA1 HW Trigger signal is GPU2D_FLAG3 */ -#endif /* GPU2D */ -#if defined (GFXTIM) -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT3 59U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT3 */ -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT2 60U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT2 */ -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT1 61U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT1 */ -#define LL_GPDMA1_TRIGGER_GFXTIM_EVT0 62U /*!< GPDMA1 HW Trigger signal is GFXTIM_EVT0 */ -#endif /* GFXTIM */ -#if defined (JPEG) -#define LL_GPDMA1_TRIGGER_JPEG_EOC 63U /*!< GPDMA1 HW Trigger signal is JPEG_EOC */ -#define LL_GPDMA1_TRIGGER_JPEG_IFNF 64U /*!< GPDMA1 HW Trigger signal is JPEG_IFNF */ -#define LL_GPDMA1_TRIGGER_JPEG_IFT 65U /*!< GPDMA1 HW Trigger signal is JPEG_IFT */ -#define LL_GPDMA1_TRIGGER_JPEG_OFNE 66U /*!< GPDMA1 HW Trigger signal is JPEG_OFNE */ -#define LL_GPDMA1_TRIGGER_JPEG_OFT 67U /*!< GPDMA1 HW Trigger signal is JPEG_OFT */ -#endif /* JPEG */ - -/* LPDMA1 triggers */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE0 0U /*!< LPDMA1 HW Trigger is EXTI_LINE0 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE1 1U /*!< LPDMA1 HW Trigger is EXTI_LINE1 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE2 2U /*!< LPDMA1 HW Trigger is EXTI_LINE2 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE3 3U /*!< LPDMA1 HW Trigger is EXTI_LINE3 */ -#define LL_LPDMA1_TRIGGER_EXTI_LINE4 4U /*!< LPDMA1 HW Trigger is EXTI_LINE4 */ -#define LL_LPDMA1_TRIGGER_TAMP_TRG1 5U /*!< LPDMA1 HW Trigger is TAMP_TRG1 */ -#define LL_LPDMA1_TRIGGER_TAMP_TRG2 6U /*!< LPDMA1 HW Trigger is TAMP_TRG2 */ -#define LL_LPDMA1_TRIGGER_TAMP_TRG3 7U /*!< LPDMA1 HW Trigger is TAMP_TRG3 */ -#define LL_LPDMA1_TRIGGER_LPTIM1_CH1 8U /*!< LPDMA1 HW Trigger is LPTIM1_CH1 */ -#define LL_LPDMA1_TRIGGER_LPTIM1_CH2 9U /*!< LPDMA1 HW Trigger is LPTIM1_CH2 */ -#define LL_LPDMA1_TRIGGER_LPTIM3_CH1 10U /*!< LPDMA1 HW Trigger is LPTIM3_CH1 */ -#define LL_LPDMA1_TRIGGER_LPTIM4_OUT 11U /*!< LPDMA1 HW Trigger is LPTIM4_OUT */ -#define LL_LPDMA1_TRIGGER_COMP1_OUT 12U /*!< LPDMA1 HW Trigger is COMP1_OUT */ -#if defined(COMP2) -#define LL_LPDMA1_TRIGGER_COMP2_OUT 13U /*!< LPDMA1 HW Trigger is COMP2_OUT */ -#endif /* COMP2 */ -#define LL_LPDMA1_TRIGGER_RTC_ALRA_TRG 14U /*!< LPDMA1 HW Trigger is RTC_ALRA_TRG */ -#define LL_LPDMA1_TRIGGER_RTC_ALRB_TRG 15U /*!< LPDMA1 HW Trigger is RTC_ALRB_TRG */ -#define LL_LPDMA1_TRIGGER_RTC_WUT_TRG 16U /*!< LPDMA1 HW Trigger is RTC_WUT_TRG */ -#define LL_LPDMA1_TRIGGER_ADC4_AWD1 17U /*!< LPDMA1 HW Trigger is ADC4_AWD1 */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF 18U /*!< LPDMA1 HW Trigger is LPDMA1_CH0_TCF */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF 19U /*!< LPDMA1 HW Trigger is LPDMA1_CH1_TCF */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF 20U /*!< LPDMA1 HW Trigger is LPDMA1_CH2_TCF */ -#define LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF 21U /*!< LPDMA1 HW Trigger is LPDMA1_CH3_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF 22U /*!< LPDMA1 HW Trigger is GPDMA1_CH0_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF 23U /*!< LPDMA1 HW Trigger is GPDMA1_CH1_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF 24U /*!< LPDMA1 HW Trigger is GPDMA1_CH4_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF 25U /*!< LPDMA1 HW Trigger is GPDMA1_CH5_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF 26U /*!< LPDMA1 HW Trigger is GPDMA1_CH6_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF 27U /*!< LPDMA1 HW Trigger is GPDMA1_CH7_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF 28U /*!< LPDMA1 HW Trigger is GPDMA1_CH12_TCF */ -#define LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF 29U /*!< LPDMA1 HW Trigger is GPDMA1_CH13_TCF */ -#define LL_LPDMA1_TRIGGER_TIM2_TRGO 30U /*!< LPDMA1 HW Trigger is TIM2_TRGO */ -#define LL_LPDMA1_TRIGGER_TIM15_TRGO 31U /*!< LPDMA1 HW Trigger is TIM15_TRGO */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_COMMON_WRITE_READ_REGISTERS Common Write and Read Registers macros - * @{ - */ -/** - * @brief Write a value in DMA register. - * @param __INSTANCE__ DMA Instance. - * @param __REG__ Register to be written. - * @param __VALUE__ Value to be written in the register. - * @retval None. - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register. - * @param __INSTANCE__ DMA Instance. - * @param __REG__ Register to be read. - * @retval Register value. - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely - * @{ - */ -/** - * @brief Convert DMAx_Channely into DMAx. - * @param __CHANNEL_INSTANCE__ DMAx_Channely. - * @retval DMAx. - */ -#define LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ - (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)GPDMA1_Channel15)) ? LPDMA1 : GPDMA1) - -/** - * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y. - * @param __CHANNEL_INSTANCE__ DMAx_Channely. - * @retval LL_DMA_CHANNEL_y. - */ -#define LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ - (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel0)) ? LL_DMA_CHANNEL_0 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)LPDMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel8)) ? LL_DMA_CHANNEL_8 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel9)) ? LL_DMA_CHANNEL_9 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel10)) ? LL_DMA_CHANNEL_10 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel11)) ? LL_DMA_CHANNEL_11 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel12)) ? LL_DMA_CHANNEL_12 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel13)) ? LL_DMA_CHANNEL_13 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)GPDMA1_Channel14)) ? LL_DMA_CHANNEL_14 : \ - LL_DMA_CHANNEL_15) - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely. - * @param __DMA_INSTANCE__ DMAx. - * @param __CHANNEL__ LL_DMA_CHANNEL_y. - * @retval DMAx_Channely. - */ -#define LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ - ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ - ? GPDMA1_Channel0 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_0))) \ - ? LPDMA1_Channel0 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ - ? GPDMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) \ - ? LPDMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ - ? GPDMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) \ - ? LPDMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ - ? GPDMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)LPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) \ - ? LPDMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) \ - ? GPDMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) \ - ? GPDMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) \ - ? GPDMA1_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) \ - ? GPDMA1_Channel7 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) \ - ? GPDMA1_Channel8 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_9))) \ - ? GPDMA1_Channel9 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_10)))\ - ? GPDMA1_Channel10 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_11)))\ - ? GPDMA1_Channel11 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_12)))\ - ? GPDMA1_Channel12 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_13)))\ - ? GPDMA1_Channel13 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)GPDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_14)))\ - ? GPDMA1_Channel14 : GPDMA1_Channel15) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable channel. - * @note This API is used for all available DMA channels. - * @rmtoll CCR EN LL_DMA_EnableChannel - * @param DMAx DMAx Instance. - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); -} - -/** - * @brief Disable channel. - * @note This API is used for all available DMA channels. - * @rmtoll CCR EN LL_DMA_DisableChannel - * @param DMAx DMAx Instance. - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, - (DMA_CCR_SUSP | DMA_CCR_RESET)); -} - -/** - * @brief Check if channel is enabled or disabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR EN LL_DMA_IsEnabledChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN) - == (DMA_CCR_EN)) ? 1UL : 0UL); -} - -/** - * @brief Reset channel. - * @note This API is used for all available DMA channels. - * @rmtoll CCR RESET LL_DMA_ResetChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ResetChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_RESET); -} - -/** - * @brief Suspend channel. - * @note This API is used for all available DMA channels. - * @rmtoll CCR SUSP LL_DMA_SuspendChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SuspendChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); -} - -/** - * @brief Resume channel. - * @note This API is used for all available DMA channels. - * @rmtoll CCR SUSP LL_DMA_ResumeChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ResumeChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP); -} - -/** - * @brief Check if channel is suspended. - * @note This API is used for all available DMA channels. - * @rmtoll CCR SUSP LL_DMA_IsSuspendedChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsSuspendedChannel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSP) - == (DMA_CCR_SUSP)) ? 1UL : 0UL); -} - -/** - * @brief Set linked-list base address. - * @note This API is used for all available DMA channels. - * @rmtoll CLBAR LBA LL_DMA_SetLinkedListBaseAddr - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param LinkedListBaseAddr Between 0 to 0xFFFF0000 (where the 4 LSB bytes - * are always 0) - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t LinkedListBaseAddr) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA, - (LinkedListBaseAddr & DMA_CLBAR_LBA)); -} - -/** - * @brief Get linked-list base address. - * @note This API is used for all available DMA channels. - * @rmtoll CLBAR LBA LL_DMA_GetLinkedListBaseAddr - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Value between 0 to 0xFFFF0000 (where the 4 LSB bytes are always 0) - */ -__STATIC_INLINE uint32_t LL_DMA_GetLinkedListBaseAddr(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLBAR, DMA_CLBAR_LBA)); -} - -/** - * @brief Configure all parameters linked to channel control. - * @note This API is used for all available DMA channels. - * For LPDMA channels, LAP field programming is discarded. - * @rmtoll CCR PRIO LL_DMA_ConfigControl\n - * CCR LAP LL_DMA_ConfigControl\n - * CCR LSM LL_DMA_ConfigControl - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT or @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT or - * @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT or @ref LL_DMA_HIGH_PRIORITY - * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 or @ref LL_DMA_LINK_ALLOCATED_PORT1 - * @arg @ref LL_DMA_LSM_FULL_EXECUTION or @ref LL_DMA_LSM_1LINK_EXECUTION - *@retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigControl(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, - (DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM), Configuration); -} - -/** - * @brief Set priority level. - * @note This API is used for all available DMA channels. - * @rmtoll CCR PRIO LL_DMA_SetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT - * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT - * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT - * @arg @ref LL_DMA_HIGH_PRIORITY - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO, Priority); -} - -/** - * @brief Get Channel priority level. - * @note This API is used for all available DMA channels. - * @rmtoll CCR PRIO LL_DMA_GetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_LOW_PRIORITY_LOW_WEIGHT - * @arg @ref LL_DMA_LOW_PRIORITY_MID_WEIGHT - * @arg @ref LL_DMA_LOW_PRIORITY_HIGH_WEIGHT - * @arg @ref LL_DMA_HIGH_PRIORITY - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIO)); -} - -/** - * @brief Set linked-list allocated port. - * @note This API is not used for LPDMA channels. - * @rmtoll CCR LAP LL_DMA_SetLinkAllocatedPort - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param LinkAllocatedPort This parameter can be one of the following values: - * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 - * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkAllocatedPort) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, - DMA_CCR_LAP, LinkAllocatedPort); -} - -/** - * @brief Get linked-list allocated port. - * @note This API is not used for LPDMA channels. - * @rmtoll CCR LAP LL_DMA_GetLinkAllocatedPort - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_LINK_ALLOCATED_PORT0 - * @arg @ref LL_DMA_LINK_ALLOCATED_PORT1 - */ -__STATIC_INLINE uint32_t LL_DMA_GetLinkAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LAP)); -} - -/** - * @brief Set link step mode. - * @note This API is used for all available DMA channels. - * @rmtoll CCR LSM LL_DMA_SetLinkStepMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param LinkStepMode This parameter can be one of the following values: - * @arg @ref LL_DMA_LSM_FULL_EXECUTION - * @arg @ref LL_DMA_LSM_1LINK_EXECUTION - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t LinkStepMode) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM, LinkStepMode); -} - -/** - * @brief Get Link step mode. - * @note This API is used for all available DMA channels. - * @rmtoll CCR LSM LL_DMA_GetLinkStepMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_LSM_FULL_EXECUTION - * @arg @ref LL_DMA_LSM_1LINK_EXECUTION - */ -__STATIC_INLINE uint32_t LL_DMA_GetLinkStepMode(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_LSM)); -} - -/** - * @brief Configure data transfer. - * @note This API is used for all available DMA channels. - * For LPDMA channels DAP, DHX, DBX, SAP, SBX fields programming is - * discarded. - * @rmtoll CTR1 DAP LL_DMA_ConfigTransfer\n - * CTR1 DHX LL_DMA_ConfigTransfer\n - * CTR1 DBX LL_DMA_ConfigTransfer\n - * CTR1 DINC LL_DMA_ConfigTransfer\n - * CTR1 SAP LL_DMA_ConfigTransfer\n - * CTR1 SBX LL_DMA_ConfigTransfer\n - * CTR1 PAM LL_DMA_ConfigTransfer\n - * CTR1 SINC LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 or @ref LL_DMA_DEST_ALLOCATED_PORT1 - * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE or @ref LL_DMA_DEST_HALFWORD_EXCHANGE - * @arg @ref LL_DMA_DEST_BYTE_PRESERVE or @ref LL_DMA_DEST_BYTE_EXCHANGE - * @arg @ref LL_DMA_SRC_BYTE_PRESERVE or @ref LL_DMA_SRC_BYTE_EXCHANGE - * @arg @ref LL_DMA_DEST_FIXED or @ref LL_DMA_DEST_INCREMENT - * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE or @ref LL_DMA_DEST_DATAWIDTH_HALFWORD or - * @ref LL_DMA_DEST_DATAWIDTH_WORD - * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 or @ref LL_DMA_SRC_ALLOCATED_PORT1 - * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD or @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD or - * @ref LL_DMA_DATA_PACK_UNPACK - * @arg @ref LL_DMA_SRC_FIXED or @ref LL_DMA_SRC_INCREMENT - * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE or @ref LL_DMA_SRC_DATAWIDTH_HALFWORD or - * @ref LL_DMA_SRC_DATAWIDTH_WORD - *@retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - DMA_CTR1_DAP | DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_DINC | DMA_CTR1_SINC | \ - DMA_CTR1_SAP | DMA_CTR1_PAM | DMA_CTR1_DDW_LOG2 | DMA_CTR1_SDW_LOG2, Configuration); -} - -/** - * @brief Configure source and destination burst length. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength\n - * @rmtoll CTR1 SBL_1 LL_DMA_SetDestBurstLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcBurstLength Between 1 to 64 - * @param DestBurstLength Between 1 to 64 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength, - uint32_t DestBurstLength) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - (DMA_CTR1_SBL_1 | DMA_CTR1_DBL_1), (((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1) | \ - (((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1)); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure all secure parameters linked to DMA channel. - * @note This API is used for all available DMA channels. - * @rmtoll SECCFGR SEC LL_DMA_ConfigChannelSecure\n - * @rmtoll CTR1 SSEC LL_DMA_ConfigChannelSecure\n - * @rmtoll CTR1 DSEC LL_DMA_ConfigChannelSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_CHANNEL_NSEC or @ref LL_DMA_CHANNEL_SEC - * @arg @ref LL_DMA_CHANNEL_SRC_NSEC or @ref LL_DMA_CHANNEL_SRC_SEC - * @arg @ref LL_DMA_CHANNEL_DEST_NSEC or @ref LL_DMA_CHANNEL_DEST_SEC - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << Channel), ((Configuration & LL_DMA_CHANNEL_SEC) << Channel)); - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - (DMA_CTR1_SSEC | DMA_CTR1_DSEC), (Configuration & (~LL_DMA_CHANNEL_SEC))); -} - -/** - * @brief Enable security attribute of the DMA transfer to the destination. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DSEC LL_DMA_EnableChannelDestSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); -} - -/** - * @brief Disable security attribute of the DMA transfer to the destination. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DSEC LL_DMA_DisableChannelDestSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC); -} -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Check security attribute of the DMA transfer to the destination. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DSEC LL_DMA_IsEnabledChannelDestSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DSEC) - == (DMA_CTR1_DSEC)) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable security attribute of the DMA transfer from the source. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SSEC LL_DMA_EnableChannelSrcSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); -} - -/** - * @brief Disable security attribute of the DMA transfer from the source. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SSEC LL_DMA_DisableChannelSrcSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC); -} -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Check security attribute of the DMA transfer from the source. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SSEC LL_DMA_IsEnabledChannelSrcSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SSEC) - == (DMA_CTR1_SSEC)) ? 1UL : 0UL); -} - -/** - * @brief Set destination allocated port. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DAP LL_DMA_SetDestAllocatedPort - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestAllocatedPort This parameter can be one of the following values: - * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 - * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAllocatedPort) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP, - DestAllocatedPort); -} - -/** - * @brief Get destination allocated port. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DAP LL_DMA_GetDestAllocatedPort - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DEST_ALLOCATED_PORT0 - * @arg @ref LL_DMA_DEST_ALLOCATED_PORT1 - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DAP)); -} - -/** - * @brief Set destination half-word exchange. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DHX LL_DMA_SetDestHWordExchange - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestHWordExchange This parameter can be one of the following values: - * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE - * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestHWordExchange) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX, - DestHWordExchange); -} - -/** - * @brief Get destination half-word exchange. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DHX LL_DMA_GetDestHWordExchange - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DEST_HALFWORD_PRESERVE - * @arg @ref LL_DMA_DEST_HALFWORD_EXCHANGE - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestHWordExchange(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DHX)); -} - -/** - * @brief Set destination byte exchange. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DBX LL_DMA_SetDestByteExchange - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestByteExchange This parameter can be one of the following values: - * @arg @ref LL_DMA_DEST_BYTE_PRESERVE - * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestByteExchange) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX, - DestByteExchange); -} - -/** - * @brief Get destination byte exchange. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DBX LL_DMA_GetDestByteExchange - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DEST_BYTE_PRESERVE - * @arg @ref LL_DMA_DEST_BYTE_EXCHANGE - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBX)); -} - -/** - * @brief Set source byte exchange. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 SBX LL_DMA_SetSrcByteExchange - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcByteExchange This parameter can be one of the following values: - * @arg @ref LL_DMA_SRC_BYTE_PRESERVE - * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcByteExchange) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX, - SrcByteExchange); -} - -/** - * @brief Get source byte exchange. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 SBX LL_DMA_GetSrcByteExchange - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_SRC_BYTE_PRESERVE - * @arg @ref LL_DMA_SRC_BYTE_EXCHANGE - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcByteExchange(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBX)); -} - -/** - * @brief Set destination burst length. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DBL_1 LL_DMA_SetDestBurstLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestBurstLength Between 1 to 64 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestBurstLength) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DBL_1, - ((DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1); -} - -/** - * @brief Get destination burst length. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DBL_1 LL_DMA_GetDestBurstLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 1 to 64. - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U); -} - -/** - * @brief Set destination increment mode. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 DINC LL_DMA_SetDestIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestInc This parameter can be one of the following values: - * @arg @ref LL_DMA_DEST_FIXED - * @arg @ref LL_DMA_DEST_INCREMENT - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestInc) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC, DestInc); -} - -/** - * @brief Get destination increment mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DINC LL_DMA_GetDestIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DEST_FIXED - * @arg @ref LL_DMA_DEST_INCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DINC)); -} - -/** - * @brief Set destination data width. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DDW_LOG2 LL_DMA_SetDestDataWidth - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestDataWidth This parameter can be one of the following values: - * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE - * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD - * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestDataWidth) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2, - DestDataWidth); -} - -/** - * @brief Get destination data width. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 DDW_LOG2 LL_DMA_GetDestDataWidth - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DEST_DATAWIDTH_BYTE - * @arg @ref LL_DMA_DEST_DATAWIDTH_HALFWORD - * @arg @ref LL_DMA_DEST_DATAWIDTH_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_DDW_LOG2)); -} - -/** - * @brief Set source allocated port. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 SAP LL_DMA_SetSrcAllocatedPort - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcAllocatedPort This parameter can be one of the following values: - * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 - * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAllocatedPort) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP, - SrcAllocatedPort); -} - -/** - * @brief Get source allocated port. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 SAP LL_DMA_GetSrcAllocatedPort - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_SRC_ALLOCATED_PORT0 - * @arg @ref LL_DMA_SRC_ALLOCATED_PORT1 - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcAllocatedPort(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SAP)); -} - -/** - * @brief Set data alignment mode. - * @note This API is used for all available DMA channels. - * For LPDMA channels, PAM field is reduced to one bit. - * @rmtoll CTR1 PAM LL_DMA_SetDataAlignment - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DataAlignment This parameter can be one of the following values: - * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD - * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD - * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels) - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DataAlignment) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM, - DataAlignment); -} - -/** - * @brief Get data alignment mode. - * @note This API is used for all available DMA channels. - * For LPDMA channels, PAM field is reduced to one bit. - * @rmtoll CTR1 PAM LL_DMA_GetDataAlignment - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DATA_ALIGN_ZEROPADD - * @arg @ref LL_DMA_DATA_ALIGN_SIGNEXTPADD - * @arg @ref LL_DMA_DATA_PACK_UNPACK (This value is not allowed for LPDMA channels) - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataAlignment(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_PAM)); -} - -/** - * @brief Set source burst length. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 SBL_1 LL_DMA_SetSrcBurstLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcBurstLength Between 1 to 64 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcBurstLength) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SBL_1, - ((SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1); -} - -/** - * @brief Get source burst length. - * @note This API is not used for LPDMA channels. - * @rmtoll CTR1 SBL_1 LL_DMA_GetSrcBurstLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 1 to 64 - * @retval None. - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcBurstLength(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, - DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U); -} - -/** - * @brief Set source increment mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SINC LL_DMA_SetSrcIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcInc This parameter can be one of the following values: - * @arg @ref LL_DMA_SRC_FIXED - * @arg @ref LL_DMA_SRC_INCREMENT - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcInc) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC, SrcInc); -} - -/** - * @brief Get source increment mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SINC LL_DMA_GetSrcIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_SRC_FIXED - * @arg @ref LL_DMA_SRC_INCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SINC)); -} - -/** - * @brief Set source data width. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SDW_LOG2 LL_DMA_SetSrcDataWidth - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcDataWidth This parameter can be one of the following values: - * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE - * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD - * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcDataWidth) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2, - SrcDataWidth); -} - -/** - * @brief Get Source Data width. - * @note This API is used for all available DMA channels. - * @rmtoll CTR1 SDW_LOG2 LL_DMA_GetSrcDataWidth - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_SRC_DATAWIDTH_BYTE - * @arg @ref LL_DMA_SRC_DATAWIDTH_HALFWORD - * @arg @ref LL_DMA_SRC_DATAWIDTH_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcDataWidth(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR1, DMA_CTR1_SDW_LOG2)); -} - -/** - * @brief Configure channel transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TCEM LL_DMA_ConfigChannelTransfer\n - * CTR2 TRIGPOL LL_DMA_ConfigChannelTransfer\n - * CTR2 TRIGM LL_DMA_ConfigChannelTransfer\n - * CTR2 BREQ LL_DMA_ConfigChannelTransfer\n - * CTR2 DREQ LL_DMA_ConfigChannelTransfer\n - * CTR2 SWREQ LL_DMA_ConfigChannelTransfer - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_TCEM_BLK_TRANSFER or @ref LL_DMA_TCEM_RPT_BLK_TRANSFER or - * @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER or @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER - * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST or @ref LL_DMA_HWREQUEST_BLK - * @arg @ref LL_DMA_TRIG_POLARITY_MASKED or @ref LL_DMA_TRIG_POLARITY_RISING or - * @ref LL_DMA_TRIG_POLARITY_FALLING - * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER or @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER or - * @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER or @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or - * @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - *@retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigChannelTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, - (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGM | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_BREQ), - Configuration); -} - -/** - * @brief Set transfer event mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TCEM LL_DMA_SetTransferEventMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param TransferEventMode This parameter can be one of the following values: - * @arg @ref LL_DMA_TCEM_BLK_TRANSFER - * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER - * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER - * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TransferEventMode) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM, - TransferEventMode); -} - -/** - * @brief Get transfer event mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TCEM LL_DMA_GetTransferEventMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_TCEM_BLK_TRANSFER - * @arg @ref LL_DMA_TCEM_RPT_BLK_TRANSFER - * @arg @ref LL_DMA_TCEM_EACH_LLITEM_TRANSFER - * @arg @ref LL_DMA_TCEM_LAST_LLITEM_TRANSFER - */ -__STATIC_INLINE uint32_t LL_DMA_GetTransferEventMode(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TCEM)); -} - -/** - * @brief Set trigger polarity. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TRIGPOL LL_DMA_SetTriggerPolarity - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param TriggerPolarity This parameter can be one of the following values: - * @arg @ref LL_DMA_TRIG_POLARITY_MASKED - * @arg @ref LL_DMA_TRIG_POLARITY_RISING - * @arg @ref LL_DMA_TRIG_POLARITY_FALLING - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerPolarity) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL, - TriggerPolarity); -} - -/** - * @brief Get trigger polarity. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TRIGPOL LL_DMA_GetTriggerPolarity - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_TRIG_POLARITY_MASKED - * @arg @ref LL_DMA_TRIG_POLARITY_RISING - * @arg @ref LL_DMA_TRIG_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_DMA_GetTriggerPolarity(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGPOL)); -} - -/** - * @brief Set trigger Mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TRIGM LL_DMA_SetTriggerMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param TriggerMode This parameter can be one of the following values: - * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER - * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) - * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER - * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t TriggerMode) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM, - TriggerMode); -} - -/** - * @brief Get trigger Mode. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 TRIGM LL_DMA_GetTriggerMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_TRIGM_BLK_TRANSFER - * @arg @ref LL_DMA_TRIGM_RPT_BLK_TRANSFER (This value is allowed only for 2D addressing channels) - * @arg @ref LL_DMA_TRIGM_LLI_LINK_TRANSFER - * @arg @ref LL_DMA_TRIGM_SINGLBURST_TRANSFER - */ -__STATIC_INLINE uint32_t LL_DMA_GetTriggerMode(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGM)); -} - -/** - * @brief Set destination hardware and software transfer request. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 DREQ LL_DMA_SetDataTransferDirection\n - * @rmtoll CTR2 SWREQ LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels) - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels) - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, - DMA_CTR2_DREQ | DMA_CTR2_SWREQ, Direction); -} - -/** - * @brief Get destination hardware and software transfer request. - * @note This API is used for all available DMA channels. - * For LPDMA channels, DREQ fields programming is discarded. - * @rmtoll CTR2 DREQ LL_DMA_GetDataTransferDirection\n - * @rmtoll CTR2 SWREQ LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH (This value is not allowed for LPDMA channels) - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY (This value is not allowed for LPDMA channels) - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, - DMA_CTR2_DREQ | DMA_CTR2_SWREQ)); -} - -/** - * @brief Set block hardware request. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 BREQ LL_DMA_SetBlkHWRequest\n - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkHWRequest This parameter can be one of the following values: - * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST - * @arg @ref LL_DMA_HWREQUEST_BLK - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkHWRequest) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ, - BlkHWRequest); -} - -/** - * @brief Get block hardware request. - * @note This API is used for all available DMA channels. - * @rmtoll CTR2 BREQ LL_DMA_GetBlkHWRequest\n - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_HWREQUEST_SINGLEBURST - * @arg @ref LL_DMA_HWREQUEST_BLK - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkHWRequest(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_BREQ)); -} - -/** - * @brief Set hardware request. - * @note This API is used for all available DMA channels. - * For LPDMA channels, REQSEL fields is reduced to 5 bits. - * @rmtoll CTR2 REQSEL LL_DMA_SetPeriphRequest - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Request This parameter can be one of the following values: - * @arg @ref LL_GPDMA1_REQUEST_ADC1 - * @arg @ref LL_GPDMA1_REQUEST_ADC4 - * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1 - * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP - * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX - * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX - * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX - * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX - * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX - * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC - * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC - * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC - * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC - * @arg @ref LL_GPDMA1_REQUEST_USART1_RX - * @arg @ref LL_GPDMA1_REQUEST_USART1_TX - * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_USART3_RX - * @arg @ref LL_GPDMA1_REQUEST_USART3_TX - * @arg @ref LL_GPDMA1_REQUEST_UART4_RX - * @arg @ref LL_GPDMA1_REQUEST_UART4_TX - * @arg @ref LL_GPDMA1_REQUEST_UART5_RX - * @arg @ref LL_GPDMA1_REQUEST_UART5_TX - * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX - * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX - * @arg @ref LL_GPDMA1_REQUEST_SAI1_A - * @arg @ref LL_GPDMA1_REQUEST_SAI1_B - * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) - * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) - * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 - * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM - * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP - * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI - * @arg @ref LL_GPDMA1_REQUEST_AES_IN - * @arg @ref LL_GPDMA1_REQUEST_AES_OUT - * @arg @ref LL_GPDMA1_REQUEST_HASH_IN - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 - * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 - * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ - * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE - * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ - * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE - * @arg @ref LL_GPDMA1_REQUEST_SAES_IN - * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT - * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE - * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE - * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE - * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*) - * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) - * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX (*) - * - * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX - * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX - * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX - * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX - * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX - * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX - * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC - * @arg @ref LL_LPDMA1_REQUEST_ADC4 - * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1 - * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2 - * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE - * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE - * - * @note (*) Availability depends on devices. - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL, Request); -} - -/** - * @brief Get hardware request. - * @note This API is used for all available DMA channels. - * For LPDMA channels, REQSEL fields is reduced to 5 bits. - * @rmtoll CTR2 REQSEL LL_DMA_GetPeriphRequest - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPDMA1_REQUEST_ADC1 - * @arg @ref LL_GPDMA1_REQUEST_ADC4 - * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH1 - * @arg @ref LL_GPDMA1_REQUEST_DAC1_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM6_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM7_UP - * @arg @ref LL_GPDMA1_REQUEST_SPI1_RX - * @arg @ref LL_GPDMA1_REQUEST_SPI1_TX - * @arg @ref LL_GPDMA1_REQUEST_SPI2_RX - * @arg @ref LL_GPDMA1_REQUEST_SPI2_TX - * @arg @ref LL_GPDMA1_REQUEST_SPI3_RX - * @arg @ref LL_GPDMA1_REQUEST_SPI3_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C1_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C1_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C1_EVC - * @arg @ref LL_GPDMA1_REQUEST_I2C2_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C2_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C2_EVC - * @arg @ref LL_GPDMA1_REQUEST_I2C3_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C3_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C3_EVC - * @arg @ref LL_GPDMA1_REQUEST_I2C4_RX - * @arg @ref LL_GPDMA1_REQUEST_I2C4_TX - * @arg @ref LL_GPDMA1_REQUEST_I2C4_EVC - * @arg @ref LL_GPDMA1_REQUEST_USART1_RX - * @arg @ref LL_GPDMA1_REQUEST_USART1_TX - * @arg @ref LL_GPDMA1_REQUEST_USART2_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_USART2_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_USART3_RX - * @arg @ref LL_GPDMA1_REQUEST_USART3_TX - * @arg @ref LL_GPDMA1_REQUEST_UART4_RX - * @arg @ref LL_GPDMA1_REQUEST_UART4_TX - * @arg @ref LL_GPDMA1_REQUEST_UART5_RX - * @arg @ref LL_GPDMA1_REQUEST_UART5_TX - * @arg @ref LL_GPDMA1_REQUEST_LPUART1_RX - * @arg @ref LL_GPDMA1_REQUEST_LPUART1_TX - * @arg @ref LL_GPDMA1_REQUEST_SAI1_A - * @arg @ref LL_GPDMA1_REQUEST_SAI1_B - * @arg @ref LL_GPDMA1_REQUEST_SAI2_A (*) - * @arg @ref LL_GPDMA1_REQUEST_SAI2_B (*) - * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI1 - * @arg @ref LL_GPDMA1_REQUEST_OCTOSPI2 (*) - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM1_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM1_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM1_COM - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM8_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM8_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM8_COM - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM2_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM3_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM3_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM4_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH2 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH3 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_CH4 - * @arg @ref LL_GPDMA1_REQUEST_TIM5_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM5_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM15_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM15_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM15_TRIG - * @arg @ref LL_GPDMA1_REQUEST_TIM15_COM - * @arg @ref LL_GPDMA1_REQUEST_TIM16_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM16_UP - * @arg @ref LL_GPDMA1_REQUEST_TIM17_CH1 - * @arg @ref LL_GPDMA1_REQUEST_TIM17_UP - * @arg @ref LL_GPDMA1_REQUEST_DCMI_PSSI - * @arg @ref LL_GPDMA1_REQUEST_AES_IN - * @arg @ref LL_GPDMA1_REQUEST_AES_OUT - * @arg @ref LL_GPDMA1_REQUEST_HASH_IN - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_UCPD1_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT0 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT1 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT2 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT3 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT4 - * @arg @ref LL_GPDMA1_REQUEST_MDF1_FLT5 - * @arg @ref LL_GPDMA1_REQUEST_ADF1_FLT0 - * @arg @ref LL_GPDMA1_REQUEST_FMAC_READ - * @arg @ref LL_GPDMA1_REQUEST_FMAC_WRITE - * @arg @ref LL_GPDMA1_REQUEST_CORDIC_READ - * @arg @ref LL_GPDMA1_REQUEST_CORDIC_WRITE - * @arg @ref LL_GPDMA1_REQUEST_SAES_IN - * @arg @ref LL_GPDMA1_REQUEST_SAES_OUT - * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC1 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_IC2 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM1_UE - * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC1 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_IC2 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM2_UE - * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC1 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_IC2 - * @arg @ref LL_GPDMA1_REQUEST_LPTIM3_UE - * @arg @ref LL_GPDMA1_REQUEST_HSPI1 (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C5_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C5_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C5_EVC (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C6_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C6_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_I2C6_EVC (*) - * @arg @ref LL_GPDMA1_REQUEST_USART6_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_USART6_TX (*) - * @arg @ref LL_GPDMA1_REQUEST_ADC2 (*) - * @arg @ref LL_GPDMA1_REQUEST_JPEG_RX (*) - * @arg @ref LL_GPDMA1_REQUEST_JPEG_TX (*) - * - * @arg @ref LL_LPDMA1_REQUEST_LPUART1_RX - * @arg @ref LL_LPDMA1_REQUEST_LPUART1_TX - * @arg @ref LL_LPDMA1_REQUEST_SPI3_RX - * @arg @ref LL_LPDMA1_REQUEST_SPI3_TX - * @arg @ref LL_LPDMA1_REQUEST_I2C3_RX - * @arg @ref LL_LPDMA1_REQUEST_I2C3_TX - * @arg @ref LL_LPDMA1_REQUEST_I2C3_EVC - * @arg @ref LL_LPDMA1_REQUEST_ADC4 - * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH1 - * @arg @ref LL_LPDMA1_REQUEST_DAC1_CH2 - * @arg @ref LL_LPDMA1_REQUEST_ADF1_FLT0 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC1 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_IC2 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM1_UE - * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC1 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_IC2 - * @arg @ref LL_LPDMA1_REQUEST_LPTIM3_UE - * - * @note (*) Availability depends on devices. - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_REQSEL)); -} - -/** - * @brief Set hardware trigger. - * @note This API is used for all available DMA channels. - * For LPDMA channels, TRIGSEL fields is reduced to 5 bits. - * @rmtoll CTR2 TRIGSEL LL_DMA_SetHWTrigger - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Trigger This parameter can be one of the following values: - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 - * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 - * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 - * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT - * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT - * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) - * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG - * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG - * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF - * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO - * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO - * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) - * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*) - * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*) - * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*) - * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*) - * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*) - * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*) - * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*) - * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*) - * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 - * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1 - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT0 (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT (*) - * - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4 - * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 - * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 - * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT - * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT - * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT (*) - * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG - * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG - * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG - * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF - * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO - * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO - * @note (*) Availability depends on devices. - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Trigger) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, DMA_CTR2_TRIGSEL, - (Trigger << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); -} - -/** - * @brief Get hardware triggers. - * @note This API is used for all available DMA channels. - * For LPDMA channels, TRIGSEL fields is reduced to 5 bits. - * @rmtoll CTR2 TRIGSEL LL_DMA_GetHWTrigger - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE0 - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE1 - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE2 - * @arg @ref LL_GPDMA1_TRIGGER_EXTI_LINE3 - * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG1 - * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG2 - * @arg @ref LL_GPDMA1_TRIGGER_TAMP_TRG3 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH1 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM1_CH2 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH1 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM2_CH2 - * @arg @ref LL_GPDMA1_TRIGGER_LPTIM4_OUT - * @arg @ref LL_GPDMA1_TRIGGER_COMP1_OUT - * @arg @ref LL_GPDMA1_TRIGGER_COMP2_OUT (*) - * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRA_TRG - * @arg @ref LL_GPDMA1_TRIGGER_RTC_ALRB_TRG - * @arg @ref LL_GPDMA1_TRIGGER_RTC_WUT_TRG - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH0_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH1_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH2_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH3_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH4_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH5_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH6_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH7_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH8_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH9_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH10_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH11_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH12_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH13_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH14_TCF - * @arg @ref LL_GPDMA1_TRIGGER_GPDMA1_CH15_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH0_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH1_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH2_TCF - * @arg @ref LL_GPDMA1_TRIGGER_LPDMA1_CH3_TCF - * @arg @ref LL_GPDMA1_TRIGGER_TIM2_TRGO - * @arg @ref LL_GPDMA1_TRIGGER_TIM15_TRGO - * @arg @ref LL_GPDMA1_TRIGGER_TIM3_TRGO (*) - * @arg @ref LL_GPDMA1_TRIGGER_TIM4_TRGO (*) - * @arg @ref LL_GPDMA1_TRIGGER_TIM5_TRGO (*) - * @arg @ref LL_GPDMA1_TRIGGER_LTDC_LI (*) - * @arg @ref LL_GPDMA1_TRIGGER_DSI_TE (*) - * @arg @ref LL_GPDMA1_TRIGGER_DSI_ER (*) - * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TC (*) - * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_CTC (*) - * @arg @ref LL_GPDMA1_TRIGGER_DMA2D_TW (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG0 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG1 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG2 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GPU2D_FLAG3 (*) - * @arg @ref LL_GPDMA1_TRIGGER_ADC4_AWD1 - * @arg @ref LL_GPDMA1_TRIGGER_ADC1_AWD1 - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT3 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT2 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT1 (*) - * @arg @ref LL_GPDMA1_TRIGGER_GFXTIM_EVT0 (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_EOC (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFNF (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_IFT (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFNE (*) - * @arg @ref LL_GPDMA1_TRIGGER_JPEG_OFT (*) - * - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE0 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE1 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE2 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE3 - * @arg @ref LL_LPDMA1_TRIGGER_EXTI_LINE4 - * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG1 - * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG2 - * @arg @ref LL_LPDMA1_TRIGGER_TAMP_TRG3 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH1 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM1_CH2 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM3_CH1 - * @arg @ref LL_LPDMA1_TRIGGER_LPTIM4_OUT - * @arg @ref LL_LPDMA1_TRIGGER_COMP1_OUT - * @arg @ref LL_LPDMA1_TRIGGER_COMP2_OUT (*) - * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRA_TRG - * @arg @ref LL_LPDMA1_TRIGGER_RTC_ALRB_TRG - * @arg @ref LL_LPDMA1_TRIGGER_RTC_WUT_TRG - * @arg @ref LL_LPDMA1_TRIGGER_ADC4_AWD1 - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH0_TCF - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH1_TCF - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH2_TCF - * @arg @ref LL_LPDMA1_TRIGGER_LPDMA1_CH3_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH0_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH1_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH4_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH5_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH6_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH7_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH12_TCF - * @arg @ref LL_LPDMA1_TRIGGER_GPDMA1_CH13_TCF - * @arg @ref LL_LPDMA1_TRIGGER_TIM2_TRGO - * @arg @ref LL_LPDMA1_TRIGGER_TIM15_TRGO - * @note (*) Availability depends on devices. - */ -__STATIC_INLINE uint32_t LL_DMA_GetHWTrigger(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR2, - DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos); -} - -/** - * @brief Configure addresses update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRDDEC LL_DMA_ConfigBlkRptAddrUpdate\n - * CBR1 BRSDEC LL_DMA_ConfigBlkRptAddrUpdate\n - * CBR1 DDEC LL_DMA_ConfigBlkRptAddrUpdate\n - * CBR1 SDEC LL_DMA_ConfigBlkRptAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT - * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT or @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT - * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT or @ref LL_DMA_BURST_DEST_ADDR_DECREMENT - * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT or @ref LL_DMA_BURST_SRC_ADDR_DECREMENT - *@retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, - DMA_CBR1_BRDDEC | DMA_CBR1_BRSDEC | DMA_CBR1_DDEC | DMA_CBR1_SDEC, Configuration); -} - -/** - * @brief Configure DMA Block number of data and repeat Count. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BNDT LL_DMA_ConfigBlkCounters\n - * CBR1 BRC LL_DMA_ConfigBlkCounters - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkDataLength Block transfer length - Value between 0 to 0x0000FFFF - * @param BlkRptCount Block repeat counter - * Value between 0 to 0x000007FF - *@retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigBlkCounters(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength, - uint32_t BlkRptCount) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, - (DMA_CBR1_BNDT | DMA_CBR1_BRC), (BlkDataLength | (BlkRptCount << DMA_CBR1_BRC_Pos))); -} - -/** - * @brief Set block repeat destination address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRDDEC LL_DMA_SetBlkRptDestAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkRptDestAddrUpdate This parameter can be one of the following values: - * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT - * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t BlkRptDestAddrUpdate) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC, - BlkRptDestAddrUpdate); -} - -/** - * @brief Get block repeat destination address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRDDEC LL_DMA_GetBlkRptDestAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_INCREMENT - * @arg @ref LL_DMA_BLKRPT_DEST_ADDR_DECREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRDDEC)); -} - -/** - * @brief Set block repeat source address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRSDEC LL_DMA_SetBlkRptSrcAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkRptSrcAddrUpdate This parameter can be one of the following values: - * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT - * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t BlkRptSrcAddrUpdate) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC, - BlkRptSrcAddrUpdate); -} - -/** - * @brief Get block repeat source address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRSDEC LL_DMA_GetBlkRptSrcAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_INCREMENT - * @arg @ref LL_DMA_BLKRPT_SRC_ADDR_DECREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRSDEC)); -} - -/** - * @brief Set destination address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 DDEC LL_DMA_SetDestAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestAddrUpdate This parameter can be one of the following values: - * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT - * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrUpdate) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC, - DestAddrUpdate); -} - -/** - * @brief Get destination address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 DDEC LL_DMA_GetDestAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_BURST_DEST_ADDR_INCREMENT - * @arg @ref LL_DMA_BURST_DEST_ADDR_DECREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_DDEC)); -} - -/** - * @brief Set source address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 SDEC LL_DMA_SetSrcAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcAddrUpdate This parameter can be one of the following values: - * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT - * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrUpdate) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC, - SrcAddrUpdate); -} - -/** - * @brief Get source address update. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 SDEC LL_DMA_GetSrcAddrUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_BURST_SRC_ADDR_INCREMENT - * @arg @ref LL_DMA_BURST_SRC_ADDR_DECREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_SDEC)); -} - -/** - * @brief Set block repeat count. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRC LL_DMA_SetBlkRptCount - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkRptCount Block repeat counter - * Value between 0 to 0x000007FF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkRptCount) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BRC, - (BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); -} - -/** - * @brief Get block repeat count. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR1 BRC LL_DMA_GetBlkRptCount - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x000007FF - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkRptCount(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, - DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos); -} - -/** - * @brief Set block data length in bytes to transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CBR1 BNDT LL_DMA_SetBlkDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkDataLength Between 0 to 0x0000FFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t BlkDataLength) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT, - BlkDataLength); -} - -/** - * @brief Get block data length in bytes to transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CBR1 BNDT LL_DMA_GetBlkDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x0000FFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR1, DMA_CBR1_BNDT)); -} - -/** - * @brief Configure the source and destination addresses. - * @note This API is used for all available DMA channels. - * @note This API must not be called when the DMA Channel is enabled. - * @rmtoll CSAR SA LL_DMA_ConfigAddresses\n - * CDAR DA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcAddress Between 0 to 0xFFFFFFFF - * @param DestAddress Between 0 to 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t - DestAddress) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); -} - -/** - * @brief Set source address. - * @note This API is used for all available DMA channels. - * @rmtoll CSAR SA LL_DMA_SetSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcAddress Between 0 to 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR, SrcAddress); -} - -/** - * @brief Get source address. - * @note This API is used for all available DMA channels. - * @rmtoll CSAR SA LL_DMA_GetSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSAR)); -} - -/** - * @brief Set destination address. - * @note This API is used for all available DMA channels. - * @rmtoll CDAR DA LL_DMA_SetDestAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestAddress Between 0 to 0xFFFFFFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddress) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR, DestAddress); -} - -/** - * @brief Get destination address. - * @note This API is used for all available DMA channels. - * @rmtoll CDAR DA LL_DMA_GetDestAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestAddress(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CDAR)); -} - -/** - * @brief Configure source and destination addresses offset. - * @note This API is used only for 2D addressing channels. - * @note This API must not be called when the DMA Channel is enabled. - * @rmtoll CTR3 DAO LL_DMA_ConfigAddrUpdateValue\n - * CTR3 SAO LL_DMA_ConfigAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestAddrOffset Between 0 to 0x00001FFF - * @param SrcAddrOffset Between 0 to 0x00001FFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset, - uint32_t DestAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, - (SrcAddrOffset & DMA_CTR3_SAO) | ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); -} - -/** - * @brief Set destination address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CTR3 DAO LL_DMA_SetDestAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DestAddrOffset Between 0 to 0x00001FFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t DestAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_DAO, - ((DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); -} - -/** - * @brief Get destination address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CDAR DAO LL_DMA_GetDestAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x00001FFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, - DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); -} - -/** - * @brief Set source address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CTR3 SAO LL_DMA_SetSrcAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param SrcAddrOffset Between 0 to 0x00001FFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO, - SrcAddrOffset & DMA_CTR3_SAO); -} - -/** - * @brief Get source address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CTR3 SAO LL_DMA_GetSrcAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x00001FFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CTR3, DMA_CTR3_SAO)); -} - -/** - * @brief Configure the block repeated source and destination addresses offset. - * @note This API is used only for 2D addressing channels. - * @note This API must not be called when the DMA Channel is enabled. - * @rmtoll CBR2 BRDAO LL_DMA_ConfigBlkRptAddrUpdateValue\n - * CBR2 BRSAO LL_DMA_ConfigBlkRptAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF - * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigBlkRptAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t BlkRptSrcAddrOffset, uint32_t BlkRptDestAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, - ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO) | (BlkRptSrcAddrOffset & DMA_CBR2_BRSAO)); -} - -/** - * @brief Set block repeated destination address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR2 BRDAO LL_DMA_SetBlkRptDestAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkRptDestAddrOffset Between 0 to 0x0000FFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t BlkRptDestAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRDAO, - ((BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO)); -} - -/** - * @brief Get block repeated destination address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR2 BRDAO LL_DMA_GetBlkRptDestAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x0000FFFF. - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkRptDestAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, - DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); -} - -/** - * @brief Set block repeated source address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR2 BRSAO LL_DMA_SetBlkRptSrcAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param BlkRptSrcAddrOffset Between 0 to 0x0000FFFF - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t BlkRptSrcAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO, - BlkRptSrcAddrOffset); -} - -/** - * @brief Get block repeated source address offset. - * @note This API is used only for 2D addressing channels. - * @rmtoll CBR2 BRSAO LL_DMA_GetBlkRptSrcAddrUpdateValue - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x0000FFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetBlkRptSrcAddrUpdateValue(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CBR2, DMA_CBR2_BRSAO)); -} - -/** - * @brief Configure registers update and node address offset during the link transfer. - * @note This API is used for all available DMA channels. - * For linear addressing channels, UT3 and UB2 fields are discarded. - * @rmtoll CLLR UT1 LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR UT2 LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR UB1 LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR USA LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR UDA LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR UT3 LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR UB2 LL_DMA_ConfigLinkUpdate\n - * @rmtoll CLLR ULL LL_DMA_ConfigLinkUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param RegistersUpdate This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_UPDATE_CTR1 - * @arg @ref LL_DMA_UPDATE_CTR2 - * @arg @ref LL_DMA_UPDATE_CBR1 - * @arg @ref LL_DMA_UPDATE_CSAR - * @arg @ref LL_DMA_UPDATE_CDAR - * @arg @ref LL_DMA_UPDATE_CTR3 (This value is allowed only for 2D addressing channels) - * @arg @ref LL_DMA_UPDATE_CBR2 (This value is allowed only for 2D addressing channels) - * @arg @ref LL_DMA_UPDATE_CLLR - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ConfigLinkUpdate(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t RegistersUpdate, - uint32_t LinkedListAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, - (DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | \ - DMA_CLLR_UB2 | DMA_CLLR_ULL | DMA_CLLR_LA), (RegistersUpdate | (LinkedListAddrOffset & DMA_CLLR_LA))); -} - -/** - * @brief Enable CTR1 update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UT1 LL_DMA_EnableCTR1Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); -} - -/** - * @brief Disable CTR1 update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UT1 LL_DMA_DisableCTR1Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1); -} - -/** - * @brief Check if CTR1 update during the link transfer is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UT1 LL_DMA_IsEnabledCTR1Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT1) - == (DMA_CLLR_UT1)) ? 1UL : 0UL); -} - -/** - * @brief Enable CTR2 update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UT2 LL_DMA_EnableCTR2Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); -} - -/** - * @brief Disable CTR2 update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UT2 LL_DMA_DisableCTR2Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2); -} - -/** - * @brief Check if CTR2 update during the link transfer is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UT2 LL_DMA_IsEnabledCTR2Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT2) - == (DMA_CLLR_UT2)) ? 1UL : 0UL); -} - -/** - * @brief Enable CBR1 update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UB1 LL_DMA_EnableCBR1Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); -} - -/** - * @brief Disable CBR1 update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UB1 LL_DMA_DisableCBR1Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1); -} - -/** - * @brief Check if CBR1 update during the link transfer is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UB1 LL_DMA_IsEnabledCBR1Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR1Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB1) - == (DMA_CLLR_UB1)) ? 1UL : 0UL); -} - -/** - * @brief Enable CSAR update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR USA LL_DMA_EnableCSARUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); -} - -/** - * @brief Disable CSAR update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR USA LL_DMA_DisableCSARUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA); -} - -/** - * @brief Check if CSAR update during the link transfer is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR USA LL_DMA_IsEnabledCSARUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCSARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_USA) - == (DMA_CLLR_USA)) ? 1UL : 0UL); -} - -/** - * @brief Enable CDAR update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UDA LL_DMA_EnableCDARUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); -} - -/** - * @brief Disable CDAR update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UDA LL_DMA_DisableCDARUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA); -} - -/** - * @brief Check if CDAR update during the link transfer is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR UDA LL_DMA_IsEnabledCDARUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCDARUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UDA) - == (DMA_CLLR_UDA)) ? 1UL : 0UL); -} - -/** - * @brief Enable CTR3 update during the link transfer. - * @note This API is used only for 2D addressing channels. - * @rmtoll CLLR UT3 LL_DMA_EnableCTR3Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); -} - -/** - * @brief Disable CTR3 update during the link transfer. - * @note This API is used only for 2D addressing channels. - * @rmtoll CLLR UT3 LL_DMA_DisableCTR3Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3); -} - -/** - * @brief Check if CTR3 update during the link transfer is enabled. - * @note This API is used only for 2D addressing channels. - * @rmtoll CLLR UT3 LL_DMA_IsEnabledCTR3Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCTR3Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UT3) - == (DMA_CLLR_UT3)) ? 1UL : 0UL); -} - -/** - * @brief Enable CBR2 update during the link transfer. - * @note This API is used only for 2D addressing channels. - * @rmtoll CLLR UB2 LL_DMA_EnableCBR2Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); -} - -/** - * @brief Disable CBR2 update during the link transfer. - * @note This API is used only for 2D addressing channels. - * @rmtoll CLLR UB2 LL_DMA_DisableCBR2Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2); -} - -/** - * @brief Check if CBR2 update during the link transfer is enabled. - * @note This API is used only for 2D addressing channels. - * @rmtoll CLLR UB2 LL_DMA_IsEnabledCBR2Update - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCBR2Update(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_UB2) - == (DMA_CLLR_UB2)) ? 1UL : 0UL); -} - -/** - * @brief Enable CLLR update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR ULL LL_DMA_EnableCLLRUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); -} - -/** - * @brief Disable CLLR update during the link transfer. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR ULL LL_DMA_DisableCLLRUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL); -} - -/** - * @brief Check if CLLR update during the link transfer is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR ULL LL_DMA_IsEnabledCLLRUpdate - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledCLLRUpdate(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_ULL) - == (DMA_CLLR_ULL)) ? 1UL : 0UL); -} - -/** - * @brief Set linked list address offset. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR LA LL_DMA_SetLinkedListAddrOffset - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param LinkedListAddrOffset Between 0 to 0x0000FFFC by increment of 4 Bytes. - * @retval None. - */ -__STATIC_INLINE void LL_DMA_SetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel, - uint32_t LinkedListAddrOffset) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, DMA_CLLR_LA, - (LinkedListAddrOffset & DMA_CLLR_LA)); -} - -/** - * @brief Get linked list address offset. - * @note This API is used for all available DMA channels. - * @rmtoll CLLR LA LL_DMA_GetLinkedListAddrOffset - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x0000FFFC. - */ -__STATIC_INLINE uint32_t LL_DMA_GetLinkedListAddrOffset(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CLLR, - DMA_CLLR_LA) >> DMA_CLLR_LA_Pos); -} - -/** - * @brief Get FIFO level. - * @note This API is not used for LPDMA channels. - * @rmtoll CSR FIFOL LL_DMA_GetFIFOLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval Between 0 to 0x000000FF. - */ -__STATIC_INLINE uint32_t LL_DMA_GetFIFOLevel(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, - DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable the DMA channel secure attribute. - * @note This API is used for all available DMA channels. - * @rmtoll SECCFGR SECx LL_DMA_EnableChannelSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); -} - -/** - * @brief Disable the DMA channel secure attribute. - * @note This API is used for all available DMA channels. - * @rmtoll SECCFGR SECx LL_DMA_DisableChannelSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))); -} -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Check if DMA channel secure is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll SECCFGR SECx LL_DMA_IsEnabledChannelSecure - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - return ((READ_BIT(DMAx->SECCFGR, (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) - == (DMA_SECCFGR_SEC0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); -} - -/** - * @brief Enable the DMA channel privilege attribute. - * @note This API is used for all available DMA channels. - * @rmtoll PRIVCFGR PRIVx LL_DMA_EnableChannelPrivilege - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); -} - -/** - * @brief Disable the DMA channel privilege attribute. - * @note This API is used for all available DMA channels. - * @rmtoll PRIVCFGR PRIVx LL_DMA_DisableChannelPrivilege - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))); -} - -/** - * @brief Check if DMA Channel privilege is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll PRIVCFGR PRIVx LL_DMA_IsEnabledChannelPrivilege - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - return ((READ_BIT(DMAx->PRIVCFGR, (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) - == (DMA_PRIVCFGR_PRIV0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable the DMA channel lock attributes. - * @note This API is used for all available DMA channels. - * @rmtoll RCFGLOCKR LOCKx LL_DMA_EnableChannelLockAttribute - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableChannelLockAttribute(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))); -} -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Check if DMA channel attributes are locked. - * @note This API is used for all available DMA channels. - * @rmtoll SECCFGR LOCKx LL_DMA_IsEnabledChannelLockAttribute - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelLockAttribute(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - return ((READ_BIT(DMAx->RCFGLOCKR, (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) - == (DMA_RCFGLOCKR_LOCK0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management Flag Management - * @{ - */ - -/** - * @brief Clear trigger overrun flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR TOF LL_DMA_ClearFlag_TO - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TOF); -} - -/** - * @brief Clear suspension flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR SUSPF LL_DMA_ClearFlag_SUSP - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_SUSPF); -} - -/** - * @brief Clear user setting error flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR USEF LL_DMA_ClearFlag_USE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_USEF); -} - -/** - * @brief Clear link transfer error flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR ULEF LL_DMA_ClearFlag_ULE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_ULEF); -} - -/** - * @brief Clear data transfer error flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR DTEF LL_DMA_ClearFlag_DTE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_DTEF); -} - -/** - * @brief Clear half transfer flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR HTF LL_DMA_ClearFlag_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_HTF); -} - -/** - * @brief Clear transfer complete flag. - * @note This API is used for all available DMA channels. - * @rmtoll CFCR TCF LL_DMA_ClearFlag_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CFCR, DMA_CFCR_TCF); -} - -/** - * @brief Get trigger overrun flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR TOF LL_DMA_IsActiveFlag_TO - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TO(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TOF) - == (DMA_CSR_TOF)) ? 1UL : 0UL); -} - -/** - * @brief Get suspension flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR SUSPF LL_DMA_IsActiveFlag_SUSP - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_SUSPF) - == (DMA_CSR_SUSPF)) ? 1UL : 0UL); -} - -/** - * @brief Get user setting error flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR USEF LL_DMA_IsActiveFlag_USE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_USE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_USEF) - == (DMA_CSR_USEF)) ? 1UL : 0UL); -} - -/** - * @brief Get user setting error flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR ULEF LL_DMA_IsActiveFlag_ULE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_ULEF) - == (DMA_CSR_ULEF)) ? 1UL : 0UL); -} - -/** - * @brief Get data transfer error flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR DTEF LL_DMA_IsActiveFlag_DTE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_DTEF) - == (DMA_CSR_DTEF)) ? 1UL : 0UL); -} - -/** - * @brief Get half transfer flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR HTF LL_DMA_IsActiveFlag_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_HTF) - == (DMA_CSR_HTF)) ? 1UL : 0UL); -} - -/** - * @brief Get transfer complete flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR TCF LL_DMA_IsActiveFlag_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_TCF) - == (DMA_CSR_TCF)) ? 1UL : 0UL); -} - -/** - * @brief Get idle flag. - * @note This API is used for all available DMA channels. - * @rmtoll CSR IDLEF LL_DMA_IsActiveFlag_IDLE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_IDLE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CSR, DMA_CSR_IDLEF) - == (DMA_CSR_IDLEF)) ? 1UL : 0UL); -} - -/** - * @brief Check if nsecure masked interrupt is active. - * @note This API is used for all available DMA channels. - * @rmtoll MISR MISx LL_DMA_IsActiveFlag_MIS - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_MIS(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - return ((READ_BIT(DMAx->MISR, (DMA_MISR_MIS0 << (Channel & 0x0FU))) - == (DMA_MISR_MIS0 << (Channel & 0x0FU))) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Check if secure masked interrupt is active. - * @note This API is used for all available DMA channels. - * @rmtoll SMISR MISx LL_DMA_IsActiveFlag_SMIS - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_SMIS(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - return ((READ_BIT(DMAx->SMISR, (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) - == (DMA_SMISR_MIS0 << (Channel & 0x0000000FU))) ? 1UL : 0UL); -} -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management Interrupt Management - * @{ - */ - -/** - * @brief Enable trigger overrun interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR TOIE LL_DMA_EnableIT_TO - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); -} - -/** - * @brief Enable suspension interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR SUSPIE LL_DMA_EnableIT_SUSP - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); -} - -/** - * @brief Enable user setting error interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR USEIE LL_DMA_EnableIT_USE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); -} - -/** - * @brief Enable update link transfer error interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR ULEIE LL_DMA_EnableIT_ULE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); -} - -/** - * @brief Enable data transfer error interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR DTEIE LL_DMA_EnableIT_DTE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); -} - -/** - * @brief Enable half transfer complete interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Enable transfer complete interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Disable trigger overrun interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR TOIE LL_DMA_DisableIT_TO - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE); -} - -/** - * @brief Disable suspension interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR SUSPIE LL_DMA_DisableIT_SUSP - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE); -} - -/** - * @brief Disable user setting error interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR USEIE LL_DMA_DisableIT_USE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE); -} - -/** - * @brief Disable update link transfer error interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR ULEIE LL_DMA_DisableIT_ULE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE); -} - -/** - * @brief Disable data transfer error interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR DTEIE LL_DMA_DisableIT_DTE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE); -} - -/** - * @brief Disable half transfer complete interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Disable transfer complete interrupt. - * @note This API is used for all available DMA channels. - * @rmtoll CCR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval None. - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Check if trigger overrun interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR TOIE LL_DMA_IsEnabledIT_TO - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TO(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TOIE) - == DMA_CCR_TOIE) ? 1UL : 0UL); -} - -/** - * @brief Check if suspension interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR SUSPIE LL_DMA_IsEnabledIT_SUSP - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_SUSP(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SUSPIE) - == DMA_CCR_SUSPIE) ? 1UL : 0UL); -} - -/** - * @brief Check if user setting error interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR USEIE LL_DMA_IsEnabledIT_USE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_USE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_USEIE) - == DMA_CCR_USEIE) ? 1UL : 0UL); -} - -/** - * @brief Check if update link transfer error interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR ULEIE LL_DMA_IsEnabledIT_ULE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_ULE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_ULEIE) - == DMA_CCR_ULEIE) ? 1UL : 0UL); -} - -/** - * @brief Check if data transfer error interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR DTEIE LL_DMA_IsEnabledIT_DTE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DTE(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DTEIE) - == DMA_CCR_DTEIE) ? 1UL : 0UL); -} - -/** - * @brief Check if half transfer complete interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE) - == DMA_CCR_HTIE) ? 1UL : 0UL); -} - -/** - * @brief Check if transfer complete interrupt is enabled. - * @note This API is used for all available DMA channels. - * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) -{ - uint32_t dma_base_addr = (uint32_t)DMAx; - return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + LL_DMA_CH_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE) - == DMA_CCR_TCIE) ? 1UL : 0UL); -} -/** - * @} - */ - -#if defined (USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); - -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); -void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); -void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct); - -uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, - LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct); -uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); - -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode); -void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, - LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx); -void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* GPDMA1 || LPDMA1 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* STM32U5xx_LL_DMA_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h deleted file mode 100644 index e021b83b4..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_exti.h +++ /dev/null @@ -1,1507 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_exti.h - * @author MCD Application Team - * @brief Header file of EXTI LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_EXTI_H -#define STM32U5xx_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -#define LL_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ - -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line_0_31; /*!< Specifies the EXTI lines to be enabled or disabled for Lines in range 0 to 31 - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR1_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR1_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR1_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR1_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR1_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR1_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR1_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR1_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR1_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR1_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR1_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR1_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR1_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR1_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR1_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR1_IM15 /*!< Extended line 15 */ -#define LL_EXTI_LINE_16 EXTI_IMR1_IM16 /*!< Extended line 16 */ -#define LL_EXTI_LINE_17 EXTI_IMR1_IM17 /*!< Extended line 17 */ -#if defined(EXTI_IMR1_IM18) -#define LL_EXTI_LINE_18 EXTI_IMR1_IM18 /*!< Extended line 18 */ -#endif /* EXTI_IMR1_IM18 */ -#define LL_EXTI_LINE_19 EXTI_IMR1_IM19 /*!< Extended line 19 */ -#define LL_EXTI_LINE_20 EXTI_IMR1_IM20 /*!< Extended line 20 */ -#define LL_EXTI_LINE_21 EXTI_IMR1_IM21 /*!< Extended line 21 */ -#define LL_EXTI_LINE_22 EXTI_IMR1_IM22 /*!< Extended line 22 */ -#define LL_EXTI_LINE_23 EXTI_IMR1_IM23 /*!< Extended line 23 */ -#if defined(EXTI_IMR1_IM24) -#define LL_EXTI_LINE_24 EXTI_IMR1_IM24 /*!< Extended line 24 */ -#endif /* EXTI_IMR1_IM24 */ -#if defined(EXTI_IMR1_IM25) -#define LL_EXTI_LINE_25 EXTI_IMR1_IM25 /*!< Extended line 25 */ -#endif /* EXTI_IMR1_IM25 */ -#if defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) -#define LL_EXTI_LINE_ALL_0_31 0x03FFFFFFU /*!< ALL Extended line */ -#else -#define LL_EXTI_LINE_ALL_0_31 0x00FFFFFFU /*!< ALL Extended line */ -#endif /* defined(EXTI_IMR1_IM24) && defined(EXTI_IMR1_IM25) */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup SYSTEM_LL_EC_EXTI_PORT EXTI EXTI PORT - * @{ - */ -#define LL_EXTI_EXTI_PORTA 0U /*!< EXTI PORT A */ -#define LL_EXTI_EXTI_PORTB EXTI_EXTICR1_EXTI0_0 /*!< EXTI PORT B */ -#define LL_EXTI_EXTI_PORTC EXTI_EXTICR1_EXTI0_1 /*!< EXTI PORT C */ -#define LL_EXTI_EXTI_PORTD (EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT D */ -#define LL_EXTI_EXTI_PORTE EXTI_EXTICR1_EXTI0_2 /*!< EXTI PORT E */ -#if defined(GPIOF) -#define LL_EXTI_EXTI_PORTF (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT F */ -#endif /* GPIOF */ -#define LL_EXTI_EXTI_PORTG (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1) /*!< EXTI PORT G */ -#define LL_EXTI_EXTI_PORTH (EXTI_EXTICR1_EXTI0_2|EXTI_EXTICR1_EXTI0_1|EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT H */ -#if defined(GPIOI) -#define LL_EXTI_EXTI_PORTI EXTI_EXTICR1_EXTI0_3 /*!< EXTI PORT I */ -#endif /* GPIOI */ -#if defined(GPIOJ) -#define LL_EXTI_EXTI_PORTJ (EXTI_EXTICR1_EXTI0_3 | EXTI_EXTICR1_EXTI0_0) /*!< EXTI PORT J */ -#endif /* GPIOJ */ - -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_EXTI_LINE EXTI EXTI LINE - * @{ - */ -#define LL_EXTI_EXTI_LINE0 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */ -#define LL_EXTI_EXTI_LINE1 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */ -#define LL_EXTI_EXTI_LINE2 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_16 | EXTICR[0] */ -#define LL_EXTI_EXTI_LINE3 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_POSITION_24 | EXTICR[0] */ -#define LL_EXTI_EXTI_LINE4 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */ -#define LL_EXTI_EXTI_LINE5 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */ -#define LL_EXTI_EXTI_LINE6 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_16 | EXTICR[1] */ -#define LL_EXTI_EXTI_LINE7 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_POSITION_24 | EXTICR[1] */ -#define LL_EXTI_EXTI_LINE8 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */ -#define LL_EXTI_EXTI_LINE9 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */ -#define LL_EXTI_EXTI_LINE10 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_16 | EXTICR[2] */ -#define LL_EXTI_EXTI_LINE11 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_POSITION_24 | EXTICR[2] */ -#define LL_EXTI_EXTI_LINE12 ((0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */ -#define LL_EXTI_EXTI_LINE13 ((8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */ -#define LL_EXTI_EXTI_LINE14 ((16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_16 | EXTICR[3] */ -#define LL_EXTI_EXTI_LINE15 ((24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 3U) /*!< EXTI_POSITION_24 | EXTICR[3] */ -/** - * @} - */ -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR1 IMx LL_EXTI_EnableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR1, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR1 IMx LL_EXTI_DisableIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR1, ExtiLine); -} - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines in range 0 to 31 - * @note The reset value for the direct or internal lines (see RM) - * is set to 1 in order to enable the interrupt by default. - * Bits are set automatically at Power on. - * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->IMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR1 EMx LL_EXTI_EnableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR1, ExtiLine); - -} - -/** - * @brief Disable ExtiLine Event request for Lines in range 0 to 31 - * @rmtoll EMR1 EMx LL_EXTI_DisableEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR1, ExtiLine); -} - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines in range 0 to 31 - * @rmtoll EMR1 EMx LL_EXTI_IsEnabledEvent_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->EMR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); - -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR1 RTx LL_EXTI_EnableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR1, ExtiLine); -} - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll RTSR1 RTx LL_EXTI_DisableRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR1, ExtiLine); - -} - -/** - * @brief Check if rising edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll RTSR1 RTx LL_EXTI_IsEnabledRisingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->RTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @rmtoll FTSR1 FTx LL_EXTI_EnableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR1, ExtiLine); -} - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines in range 0 to 31 - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @rmtoll FTSR1 FTx LL_EXTI_DisableFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR1, ExtiLine); -} - -/** - * @brief Check if falling edge trigger is enabled for Lines in range 0 to 31 - * @rmtoll FTSR1 FTx LL_EXTI_IsEnabledFallingTrig_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->FTSR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines in range 0 to 31 - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @rmtoll SWIER1 SWIx LL_EXTI_GenerateSWI_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER1, ExtiLine); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Falling Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the falling edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll FPR1 FPIFx LL_EXTI_IsActiveFallingFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFallingFlag_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->FPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -/** - * @brief Read ExtLine Combination Falling Flag for Lines in range 0 to 31 - * @note This bit is set when the falling edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll FPR1 FPIFx LL_EXTI_ReadFallingFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFallingFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->FPR1, ExtiLine)); -} - -/** - * @brief Clear ExtLine Falling Flags for Lines in range 0 to 31 - * @note This bit is set when the falling edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll FPR1 FPIFx LL_EXTI_ClearFallingFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFallingFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->FPR1, ExtiLine); -} - -/** - * @brief Check if the ExtLine Rising Flag is set or not for Lines in range 0 to 31 - * @note This bit is set when the Rising edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll RPR1 RPIFx LL_EXTI_IsActiveRisingFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveRisingFlag_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->RPR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -/** - * @brief Read ExtLine Combination Rising Flag for Lines in range 0 to 31 - * @note This bit is set when the Rising edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll RPR1 RPIFx LL_EXTI_ReadRisingFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadRisingFlag_0_31(uint32_t ExtiLine) -{ - return (uint32_t)(READ_BIT(EXTI->RPR1, ExtiLine)); -} - -/** - * @brief Clear ExtLine Rising Flags for Lines in range 0 to 31 - * @note This bit is set when the Rising edge event arrives on the interrupt - * line. This bit is cleared by writing a 1 to the bit. - * @rmtoll RPR1 RPIFx LL_EXTI_ClearRisingFlag_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearRisingFlag_0_31(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->RPR1, ExtiLine); -} - -/** - * @} - */ -/** @defgroup EXTI_LL_EF_Config EF configuration functions - * @{ - */ - -/** - * @brief Configure source input for the EXTI external interrupt. - * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR1 EXTI1 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR1 EXTI2 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR1 EXTI3 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR2 EXTI4 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR2 EXTI5 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR2 EXTI6 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR2 EXTI7 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR3 EXTI8 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR3 EXTI9 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR3 EXTI10 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR3 EXTI11 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR4 EXTI12 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR4 EXTI13 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR4 EXTI14 LL_EXTI_SetEXTISource\n - * EXTI_EXTICR4 EXTI15 LL_EXTI_SetEXTISource - * @param Port This parameter can be one of the following values: - * @arg @ref LL_EXTI_EXTI_PORTA - * @arg @ref LL_EXTI_EXTI_PORTB - * @arg @ref LL_EXTI_EXTI_PORTC - * @arg @ref LL_EXTI_EXTI_PORTD - * @arg @ref LL_EXTI_EXTI_PORTE - * @arg @ref LL_EXTI_EXTI_PORTF (*) - * @arg @ref LL_EXTI_EXTI_PORTG - * @arg @ref LL_EXTI_EXTI_PORTH - * @arg @ref LL_EXTI_EXTI_PORTI (*) - * @arg @ref LL_EXTI_EXTI_PORTJ (*) - * - * (*) value not defined in all devices - * @param Line This parameter can be one of the following values: - * @arg @ref LL_EXTI_EXTI_LINE0 - * @arg @ref LL_EXTI_EXTI_LINE1 - * @arg @ref LL_EXTI_EXTI_LINE2 - * @arg @ref LL_EXTI_EXTI_LINE3 - * @arg @ref LL_EXTI_EXTI_LINE4 - * @arg @ref LL_EXTI_EXTI_LINE5 - * @arg @ref LL_EXTI_EXTI_LINE6 - * @arg @ref LL_EXTI_EXTI_LINE7 - * @arg @ref LL_EXTI_EXTI_LINE8 - * @arg @ref LL_EXTI_EXTI_LINE9 - * @arg @ref LL_EXTI_EXTI_LINE10 - * @arg @ref LL_EXTI_EXTI_LINE11 - * @arg @ref LL_EXTI_EXTI_LINE12 - * @arg @ref LL_EXTI_EXTI_LINE13 - * @arg @ref LL_EXTI_EXTI_LINE14 - * @arg @ref LL_EXTI_EXTI_LINE15 - * @retval None - */ -__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) -{ - MODIFY_REG(EXTI->EXTICR[Line & 0x03U], EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT), \ - Port << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); -} - -/** - * @brief Get the configured defined for specific EXTI Line - * @rmtoll EXTI_EXTICR1 EXTI0 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR1 EXTI1 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR1 EXTI2 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR1 EXTI3 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR2 EXTI4 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR2 EXTI5 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR2 EXTI6 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR2 EXTI7 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR3 EXTI8 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR3 EXTI9 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR3 EXTI10 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR3 EXTI11 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR4 EXTI12 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR4 EXTI13 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR4 EXTI14 LL_EXTI_GetEXTISource\n - * EXTI_EXTICR4 EXTI15 LL_EXTI_GetEXTISource - * @param Line This parameter can be one of the following values: - * @arg @ref LL_EXTI_EXTI_LINE0 - * @arg @ref LL_EXTI_EXTI_LINE1 - * @arg @ref LL_EXTI_EXTI_LINE2 - * @arg @ref LL_EXTI_EXTI_LINE3 - * @arg @ref LL_EXTI_EXTI_LINE4 - * @arg @ref LL_EXTI_EXTI_LINE5 - * @arg @ref LL_EXTI_EXTI_LINE6 - * @arg @ref LL_EXTI_EXTI_LINE7 - * @arg @ref LL_EXTI_EXTI_LINE8 - * @arg @ref LL_EXTI_EXTI_LINE9 - * @arg @ref LL_EXTI_EXTI_LINE10 - * @arg @ref LL_EXTI_EXTI_LINE11 - * @arg @ref LL_EXTI_EXTI_LINE12 - * @arg @ref LL_EXTI_EXTI_LINE13 - * @arg @ref LL_EXTI_EXTI_LINE14 - * @arg @ref LL_EXTI_EXTI_LINE15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_EXTI_EXTI_PORTA - * @arg @ref LL_EXTI_EXTI_PORTB - * @arg @ref LL_EXTI_EXTI_PORTC - * @arg @ref LL_EXTI_EXTI_PORTD - * @arg @ref LL_EXTI_EXTI_PORTE - * @arg @ref LL_EXTI_EXTI_PORTF (*) - * @arg @ref LL_EXTI_EXTI_PORTG - * @arg @ref LL_EXTI_EXTI_PORTH - * @arg @ref LL_EXTI_EXTI_PORTI (*) - * @arg @ref LL_EXTI_EXTI_PORTJ (*) - * - * (*) value not defined in all devices - */ -__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) -{ - return (uint32_t)(READ_BIT(EXTI->EXTICR[Line & 0x03U], - (EXTI_EXTICR1_EXTI0 << (Line >> LL_EXTI_REGISTER_PINPOS_SHFT))) >> - (Line >> LL_EXTI_REGISTER_PINPOS_SHFT)); -} -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Secure_Management Secure_Management - * @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - * @brief Enable ExtiLine Secure attribute for Lines in range 0 to 31 - * @rmtoll SECCFGR1 SECx LL_EXTI_EnableSecure_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableSecure_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SECCFGR1, ExtiLine); -} - -/** - * @brief Disable ExtiLine Secure attribute for Lines in range 0 to 31 - * @rmtoll SECCFGR1 SECx LL_EXTI_DisableSecure_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableSecure_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->SECCFGR1, ExtiLine); -} - -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Indicate if ExtiLine Secure attribute is enabled for Lines in range 0 to 31 - * @rmtoll SECCFGR1 SECx LL_EXTI_IsEnabledSecure_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledSecure_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->SECCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Privilege_Management Privilege_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Privilege attribute for Lines in range 0 to 31 - * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_EnablePrivilege_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnablePrivilege_0_31(uint32_t ExtiLine) -{ - SET_BIT(EXTI->PRIVCFGR1, ExtiLine); -} - -/** - * @brief Disable ExtiLine Privilege attribute for Lines in range 0 to 31 - * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_DisablePrivilege_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisablePrivilege_0_31(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->PRIVCFGR1, ExtiLine); -} - -/** - * @brief Indicate if ExtiLine Privilege attribute is enabled for Lines in range 0 to 31 - * @rmtoll PRIVCFGR1 PRIVx LL_EXTI_IsEnabledPrivilege_0_31 - * @param ExtiLine This parameter can be one of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_20 - * @arg @ref LL_EXTI_LINE_21 - * @arg @ref LL_EXTI_LINE_22 - * @arg @ref LL_EXTI_LINE_23 - * @arg @ref LL_EXTI_LINE_24 (*) - * @arg @ref LL_EXTI_LINE_25 (*) - * @arg @ref LL_EXTI_LINE_ALL_0_31 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledPrivilege_0_31(uint32_t ExtiLine) -{ - return ((READ_BIT(EXTI->PRIVCFGR1, ExtiLine) == (ExtiLine)) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Lock the secure and privilege configuration registers. - * @rmtoll LOCKR LOCK LL_EXTI_LockAttributes - * @retval None - */ -__STATIC_INLINE void LL_EXTI_LockAttributes(void) -{ - SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); -} - -/** - * @brief Return the secure and privilege configuration registers LOCK status - * @rmtoll LOCKR LOCK LL_EXTI_GetLockAttributes - * @retval 1 if the secure and privilege configuration registers have been locked else 0. - */ -__STATIC_INLINE uint32_t LL_EXTI_GetLockAttributes(void) -{ - return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -ErrorStatus LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_EXTI_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h deleted file mode 100644 index 730888c30..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_gpio.h +++ /dev/null @@ -1,1183 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_gpio.h - * @author MCD Application Team - * @brief Header file of GPIO LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_GPIO_H -#define STM32U5xx_LL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) - -/** @defgroup GPIO_LL GPIO - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures - * @{ - */ - -/** - * @brief LL GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function - @ref LL_GPIO_SetPinMode().*/ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_SPEED. - - GPIO HW configuration can be modified afterwards using unitary function - @ref LL_GPIO_SetPinSpeed().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. - - GPIO HW configuration can be modified afterwards using unitary function - @ref LL_GPIO_SetPinOutputType().*/ - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function - @ref LL_GPIO_SetPinPull().*/ - - uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_AF. - - GPIO HW configuration can be modified afterwards using unitary function - @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ -} LL_GPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants - * @{ - */ - -/** @defgroup GPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ - GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ - GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ - GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ - GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ - GPIO_BSRR_BS15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ -#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ -#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_OUTPUT Output Type - * @{ - */ -#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ -#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_SPEED Output Speed - * @{ - */ -#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ -#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ -#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ -/** - * @} - */ -#define LL_GPIO_SPEED_LOW LL_GPIO_SPEED_FREQ_LOW -#define LL_GPIO_SPEED_MEDIUM LL_GPIO_SPEED_FREQ_MEDIUM -#define LL_GPIO_SPEED_FAST LL_GPIO_SPEED_FREQ_HIGH -#define LL_GPIO_SPEED_HIGH LL_GPIO_SPEED_FREQ_VERY_HIGH - -/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down - * @{ - */ -#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ -#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ -#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_AF Alternate Function - * @{ - */ -#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ -#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ -#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ -#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ -#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ -#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ -#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ -#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ -#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_SetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)), - (Mode << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_GetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos))) >> - (POSITION_VAL(Pin) * GPIO_MODER_MODE1_Pos)); -} - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @param OutputType This parameter can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); -} - -/** - * @brief Configure gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Speed This parameter can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) -{ - MODIFY_REG(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)), - (Speed << (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))); -} - -/** - * @brief Return gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, Fast or High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << \ - (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos))) >> \ - (POSITION_VAL(Pin) * GPIO_OSPEEDR_OSPEED1_Pos)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)), - (Pull << (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << \ - (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos))) >> \ - (POSITION_VAL(Pin) * GPIO_PUPDR_PUPD1_Pos)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)), - (Alternate << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos))) >> - (POSITION_VAL(Pin) * GPIO_AFRL_AFSEL1_Pos)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)), - (Alternate << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF15 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos))) >> - (POSITION_VAL(Pin >> 8U) * GPIO_AFRH_AFSEL9_Pos)); -} - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note Each lock bit freezes a specific configuration register - * (control and alternate function registers). - * @rmtoll LCKR LCKK LL_GPIO_LockPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - __IO uint32_t temp; - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - WRITE_REG(GPIOx->LCKR, PinMask); - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - /* Read LCKK register. This read is mandatory to complete key lock sequence */ - temp = READ_REG(GPIOx->LCKR); - (void) temp; -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - -/** - * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. - * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked - * @param GPIOx GPIO Port - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) -{ - return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup GPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_GPIO_ReadInputPort - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_GPIO_IsInputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_GPIO_WriteOutputPort - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * Value between 0 and 0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_GPIO_ReadOutputPort - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_GPIO_SetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BRR BRy LL_GPIO_ResetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BRR, PinMask); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_GPIO_TogglePin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - uint32_t odr = READ_REG(GPIOx->ODR); - WRITE_REG(GPIOx->BSRR, ((odr & PinMask) << 16u) | (~odr & PinMask)); -} - -/** - * @brief Enable speed optimization for several pin of dedicated port. - * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding - * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must - * be kept at reset value. - * @note It must be used only if the I/O supply voltage is below 2.7 V. - * @rmtoll HSLVR HSLVy LL_GPIO_EnableHighSPeedLowVoltage - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - SET_BIT(GPIOx->HSLVR, PinMask); -} - - -/** - * @brief Disable speed optimization for several pin of dedicated port. - * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding - * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must - * be kept at reset value. - * @note It must be used only if the I/O supply voltage is below 2.7 V. - * @rmtoll HSLVR HSLVy LL_GPIO_DisableHighSPeedLowVoltage - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - CLEAR_BIT(GPIOx->HSLVR, PinMask); -} - -/** - * @brief Return if speed optimization for several pin of dedicated port is enabled or not. - * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding - * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must - * be kept at reset value. - * @note It must be used only if the I/O supply voltage is below 2.7 V. - * @rmtoll HSLVR HSLVy LL_GPIO_IsEnabledHighSPeedLowVoltage - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsEnabledHighSPeedLowVoltage(const GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return ((READ_BIT(GPIOx->HSLVR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - * @brief Enable secure write only access for several pin of dedicated port. - * @rmtoll SECCFGR SECy LL_GPIO_EnablePinSecure - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_EnablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - SET_BIT(GPIOx->SECCFGR, PinMask); -} - - -/** - * @brief Disable secure write only access for several pin of dedicated port. - * @rmtoll SECCFGR SECy LL_GPIO_DisablePinSecure - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - CLEAR_BIT(GPIOx->SECCFGR, PinMask); -} - -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Return if secure write only access for several pin of dedicated port is enabled or not. - * @rmtoll SECCFGR SECy LL_GPIO_IsEnabledPinSecure - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ)*/ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_GPIO_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h deleted file mode 100644 index 1fb6e7336..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_i2c.h +++ /dev/null @@ -1,2597 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_i2c.h - * @author MCD Application Team - * @brief Header file of I2C LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_I2C_H -#define STM32U5xx_LL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) || defined (I2C5) || defined (I2C6) - -/** @defgroup I2C_LL I2C - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_LL_Private_Constants I2C Private Constants - * @{ - */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2C_LL_Private_Macros I2C Private Macros - * @{ - */ -#define IS_LL_I2C_GRP1_INSTANCE(__INSTANCE__) IS_I2C_GRP1_INSTANCE(__INSTANCE__) - -#define IS_LL_I2C_GRP2_INSTANCE(__INSTANCE__) IS_I2C_GRP2_INSTANCE(__INSTANCE__) -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeripheralMode; /*!< Specifies the peripheral mode. - This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetMode(). */ - - uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. - This parameter must be set by referring to the STM32CubeMX Tool and - the helper macro @ref __LL_I2C_CONVERT_TIMINGS(). - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetTiming(). */ - - uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. - This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION. - - This feature can be modified afterwards using unitary functions - @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ - - uint32_t DigitalFilter; /*!< Configures the digital noise filter. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetDigitalFilter(). */ - - uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetOwnAddress1(). */ - - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive - match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_AcknowledgeNextData(). */ - - uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). - This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1. - - This feature can be modified afterwards using unitary function - @ref LL_I2C_SetOwnAddress1(). */ -} LL_I2C_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_I2C_WriteReg function - * @{ - */ -#define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ -#define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ -#define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ -#define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ -#define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ -#define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ -#define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ -#define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ -#define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_I2C_ReadReg function - * @{ - */ -#define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ -#define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ -#define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ -#define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ -#define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ -#define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ -#define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ -#define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ -#define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ -#define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ -#define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ -#define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ -#define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ -#define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ -#define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions - * @{ - */ -#define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ -#define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ -#define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ -#define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ -#define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ -#define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ -#define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode - * @{ - */ -#define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ -#define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ -#define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode - (Default address not acknowledge) */ -#define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection - * @{ - */ -#define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ -#define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode - * @{ - */ -#define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ -#define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length - * @{ - */ -#define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ -#define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks - * @{ - */ -#define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ -#define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ -#define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. - All Address2 are acknowledged. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation - * @{ - */ -#define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ -#define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length - * @{ - */ -#define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ -#define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction - * @{ - */ -#define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ -#define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_MODE Transfer End Mode - * @{ - */ -#define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ -#define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode - with no HW PEC comparison. */ -#define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode - with no HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode - with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode - with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode - with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) -/*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ -#define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) -/*!< Enable SMBUS Software end mode with HW PEC comparison. */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation - * @{ - */ -#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U -/*!< Don't Generate Stop and Start condition. */ -#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) -/*!< Generate Stop condition (Size should be set to 0). */ -#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -/*!< Generate Start for read request. */ -#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Start for write request. */ -#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) -/*!< Generate Restart for read request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Restart for write request, slave 7Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | \ - I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) -/*!< Generate Restart for read request, slave 10Bit address. */ -#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) -/*!< Generate Restart for write request, slave 10Bit address.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction - * @{ - */ -#define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, - slave enters receiver mode. */ -#define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, - slave enters transmitter mode.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data - * @{ - */ -#define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for - transmission */ -#define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for - reception */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout - * @{ - */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect - SCL low level timeout. */ -#define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect - both SCL and SDA high level timeout.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection - * @{ - */ -#define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ -#define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) - enable bit */ -#define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | \ - I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB -(extended clock) enable bits */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection - * @brief I2C Autonomous Trigger selection - * @{ - */ -#define LL_I2C_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for I2C1, I2C2, I2C4, I2C5, I2C6 (depends on Product) */ -#define LL_I2C_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for I2C3 */ - -#define LL_I2C_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x00000000U)) -/*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define LL_I2C_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define LL_I2C_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define LL_I2C_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define LL_I2C_GRP1_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI5_TRG */ -#define LL_I2C_GRP1_EXTI9_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI9_TRG */ -#define LL_I2C_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define LL_I2C_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM2_CH1_TRG */ -#define LL_I2C_GRP1_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ -#define LL_I2C_GRP1_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ -#define LL_I2C_GRP1_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ -#define LL_I2C_GRP1_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP1 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ - -#define LL_I2C_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x00000000U)) -/*!< HW Trigger signal is LPDMA_CH0_TRG */ -#define LL_I2C_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x1U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH1_TRG */ -#define LL_I2C_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x2U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH2_TRG */ -#define LL_I2C_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x3U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH3_TRG */ -#define LL_I2C_GRP2_EXTI5_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x4U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI5_TRG */ -#define LL_I2C_GRP2_EXTI8_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x5U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI8_TRG */ -#define LL_I2C_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x6U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define LL_I2C_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x7U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM3_CH1_TRG */ -#define LL_I2C_GRP2_COMP1_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x8U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ -#define LL_I2C_GRP2_COMP2_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0x9U << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ -#define LL_I2C_GRP2_RTC_ALRA_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xAU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ -#define LL_I2C_GRP2_RTC_WUT_TRG (uint32_t)(LL_I2C_TRIG_GRP2 | (0xBU << I2C_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity - * @brief I2C Autonomous Trigger Polarity - * @{ - */ -#define LL_I2C_TRIG_POLARITY_RISING 0x00000000U /*!< I2C triggered on rising edge */ -#define LL_I2C_TRIG_POLARITY_FALLING I2C_AUTOCR_TRIGPOL /*!< I2C triggered on falling edge */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in I2C register - * @param __INSTANCE__ I2C Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in I2C register - * @param __INSTANCE__ I2C Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings - * @{ - */ -/** - * @brief Configure the SDA setup, hold time and the SCL high, low period. - * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - * @param __SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - (tscldel = (SCLDEL+1)xtpresc) - * @param __HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. - (tsdadel = SDADELxtpresc) - * @param __SCLH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. - (tsclh = (SCLH+1)xtpresc) - * @param __SCLL_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. - (tscll = (SCLL+1)xtpresc) - * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -#define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __SETUP_TIME__, __HOLD_TIME__, __SCLH_PERIOD__, __SCLL_PERIOD__) \ - ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ - (((uint32_t)(__SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ - (((uint32_t)(__HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ - (((uint32_t)(__SCLH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ - (((uint32_t)(__SCLL_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable I2C peripheral (PE = 1). - * @rmtoll CR1 PE LL_I2C_Enable - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Disable I2C peripheral (PE = 0). - * @note When PE = 0, the I2C SCL and SDA lines are released. - * Internal state machines and status bits are put back to their reset value. - * When cleared, PE must be kept low for at least 3 APB clock cycles. - * @rmtoll CR1 PE LL_I2C_Disable - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Check if the I2C peripheral is enabled or disabled. - * @rmtoll CR1 PE LL_I2C_IsEnabled - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL); -} - -/** - * @brief Configure Noise Filters (Analog and Digital). - * @note If the analog filter is also enabled, the digital filter is added to analog filter. - * The filters can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n - * CR1 DNF LL_I2C_ConfigFilters - * @param I2Cx I2C Instance. - * @param AnalogFilter This parameter can be one of the following values: - * @arg @ref LL_I2C_ANALOGFILTER_ENABLE - * @arg @ref LL_I2C_ANALOGFILTER_DISABLE - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) - and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). - * This parameter is used to configure the digital noise filter on SDA and SCL input. - * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); -} - -/** - * @brief Configure Digital Noise Filter. - * @note If the analog filter is also enabled, the digital filter is added to analog filter. - * This filter can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter - * @param I2Cx I2C Instance. - * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) - and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). - * This parameter is used to configure the digital noise filter on SDA and SCL input. - * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); -} - -/** - * @brief Get the current Digital Noise Filter configuration. - * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); -} - -/** - * @brief Enable Analog Noise Filter. - * @note This filter can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); -} - -/** - * @brief Disable Analog Noise Filter. - * @note This filter can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); -} - -/** - * @brief Check if Analog Noise Filter is enabled or disabled. - * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA transmission requests. - * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); -} - -/** - * @brief Disable DMA transmission requests. - * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); -} - -/** - * @brief Check if DMA transmission requests are enabled or disabled. - * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA reception requests. - * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); -} - -/** - * @brief Disable DMA reception requests. - * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); -} - -/** - * @brief Check if DMA reception requests are enabled or disabled. - * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n - * RXDR RXDATA LL_I2C_DMA_GetRegAddr - * @param I2Cx I2C Instance - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT - * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction) -{ - uint32_t data_reg_addr; - - if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) - { - /* return address of TXDR register */ - data_reg_addr = (uint32_t) &(I2Cx->TXDR); - } - else - { - /* return address of RXDR register */ - data_reg_addr = (uint32_t) &(I2Cx->RXDR); - } - - return data_reg_addr; -} - -/** - * @brief Enable Clock stretching. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); -} - -/** - * @brief Disable Clock stretching. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); -} - -/** - * @brief Check if Clock stretching is enabled or disabled. - * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL); -} - -/** - * @brief Enable hardware byte control in slave mode. - * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_SBC); -} - -/** - * @brief Disable hardware byte control in slave mode. - * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); -} - -/** - * @brief Check if hardware byte control in slave mode is enabled or disabled. - * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL); -} - -/** - * @brief Enable Wakeup from STOP. - * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not - * WakeUpFromStop feature is supported by the I2Cx Instance. - * @note This bit can only be programmed when Digital Filter is disabled. - * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); -} - -/** - * @brief Disable Wakeup from STOP. - * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not - * WakeUpFromStop feature is supported by the I2Cx Instance. - * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); -} - -/** - * @brief Check if Wakeup from STOP is enabled or disabled. - * @note The macro IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not - * WakeUpFromStop feature is supported by the I2Cx Instance. - * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable General Call. - * @note When enabled the Address 0x00 is ACKed. - * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); -} - -/** - * @brief Disable General Call. - * @note When disabled the Address 0x00 is NACKed. - * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); -} - -/** - * @brief Check if General Call is enabled or disabled. - * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable I2C Fast Mode Plus (FMP = 1). - * @note 20mA I/O drive enable - * @rmtoll CR1 FMP LL_I2C_EnableFastModePlus - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableFastModePlus(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_FMP); -} - -/** - * @brief Disable I2C Fast Mode Plus (FMP = 0). - * @note 20mA I/O drive disable - * @rmtoll CR1 FMP LL_I2C_DisableFastModePlus - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableFastModePlus(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_FMP); -} - -/** - * @brief Check if the I2C Fast Mode Plus is enabled or disabled. - * @rmtoll CR1 FMP LL_I2C_IsEnabledFastModePlus - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledFastModePlus(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_FMP) == (I2C_CR1_FMP)) ? 1UL : 0UL); -} - -/** - * @brief Enable automatic clear of ADDR flag. - * @rmtoll CR1 ADDRACLR LL_I2C_EnableAutoClearFlag_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); -} - -/** - * @brief Disable automatic clear of ADDR flag. - * @rmtoll CR1 ADDRACLR LL_I2C_DisableAutoClearFlag_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_ADDR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR); -} - -/** - * @brief Check if the automatic clear of ADDR flag is enabled or disabled. - * @rmtoll CR1 ADDRACLR LL_I2C_IsEnabledAutoClearFlag_ADDR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_ADDR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRACLR) == (I2C_CR1_ADDRACLR)) ? 1UL : 0UL); -} - -/** - * @brief Enable automatic clear of STOP flag. - * @rmtoll CR1 STOPFACLR LL_I2C_EnableAutoClearFlag_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); -} - -/** - * @brief Disable automatic clear of STOP flag. - * @rmtoll CR1 STOPFACLR LL_I2C_DisableAutoClearFlag_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAutoClearFlag_STOP(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR); -} - -/** - * @brief Check if the automatic clear of STOP flag is enabled or disabled. - * @rmtoll CR1 STOPFACLR LL_I2C_IsEnabledAutoClearFlag_STOP - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoClearFlag_STOP(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPFACLR) == (I2C_CR1_STOPFACLR)) ? 1UL : 0UL); -} - -/** - * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. - * @note Changing this bit is not allowed, when the START bit is set. - * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode - * @param I2Cx I2C Instance. - * @param AddressingMode This parameter can be one of the following values: - * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT - * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); -} - -/** - * @brief Get the Master addressing mode. - * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT - * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT - */ -__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); -} - -/** - * @brief Set the Own Address1. - * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n - * OAR1 OA1MODE LL_I2C_SetOwnAddress1 - * @param I2Cx I2C Instance. - * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. - * @param OwnAddrSize This parameter can be one of the following values: - * @arg @ref LL_I2C_OWNADDRESS1_7BIT - * @arg @ref LL_I2C_OWNADDRESS1_10BIT - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) -{ - MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); -} - -/** - * @brief Enable acknowledge on Own Address1 match address. - * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); -} - -/** - * @brief Disable acknowledge on Own Address1 match address. - * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); -} - -/** - * @brief Check if Own Address1 acknowledge is enabled or disabled. - * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL); -} - -/** - * @brief Set the 7bits Own Address2. - * @note This action has no effect if own address2 is enabled. - * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n - * OAR2 OA2MSK LL_I2C_SetOwnAddress2 - * @param I2Cx I2C Instance. - * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. - * @param OwnAddrMask This parameter can be one of the following values: - * @arg @ref LL_I2C_OWNADDRESS2_NOMASK - * @arg @ref LL_I2C_OWNADDRESS2_MASK01 - * @arg @ref LL_I2C_OWNADDRESS2_MASK02 - * @arg @ref LL_I2C_OWNADDRESS2_MASK03 - * @arg @ref LL_I2C_OWNADDRESS2_MASK04 - * @arg @ref LL_I2C_OWNADDRESS2_MASK05 - * @arg @ref LL_I2C_OWNADDRESS2_MASK06 - * @arg @ref LL_I2C_OWNADDRESS2_MASK07 - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) -{ - MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); -} - -/** - * @brief Enable acknowledge on Own Address2 match address. - * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); -} - -/** - * @brief Disable acknowledge on Own Address2 match address. - * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); -} - -/** - * @brief Check if Own Address1 acknowledge is enabled or disabled. - * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL); -} - -/** - * @brief Configure the SDA setup, hold time and the SCL high, low period. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming - * @param I2Cx I2C Instance. - * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. - * @note This parameter is computed with the STM32CubeMX Tool. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) -{ - WRITE_REG(I2Cx->TIMINGR, Timing); -} - -/** - * @brief Get the Timing Prescaler setting. - * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); -} - -/** - * @brief Get the SCL low period setting. - * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); -} - -/** - * @brief Get the SCL high period setting. - * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); -} - -/** - * @brief Get the SDA hold time. - * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); -} - -/** - * @brief Get the SDA setup time. - * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xF - */ -__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); -} - -/** - * @brief Configure peripheral mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n - * CR1 SMBDEN LL_I2C_SetMode - * @param I2Cx I2C Instance. - * @param PeripheralMode This parameter can be one of the following values: - * @arg @ref LL_I2C_MODE_I2C - * @arg @ref LL_I2C_MODE_SMBUS_HOST - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); -} - -/** - * @brief Get peripheral mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n - * CR1 SMBDEN LL_I2C_GetMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_MODE_I2C - * @arg @ref LL_I2C_MODE_SMBUS_HOST - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE - * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP - */ -__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); -} - -/** - * @brief Enable SMBus alert (Host or Device mode) - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note SMBus Device mode: - * - SMBus Alert pin is drived low and - * Alert Response Address Header acknowledge is enabled. - * SMBus Host mode: - * - SMBus Alert pin management is supported. - * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); -} - -/** - * @brief Disable SMBus alert (Host or Device mode) - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note SMBus Device mode: - * - SMBus Alert pin is not drived (can be used as a standard GPIO) and - * Alert Response Address Header acknowledge is disabled. - * SMBus Host mode: - * - SMBus Alert pin management is not supported. - * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); -} - -/** - * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable SMBus Packet Error Calculation (PEC). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); -} - -/** - * @brief Disable SMBus Packet Error Calculation (PEC). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); -} - -/** - * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL); -} - -/** - * @brief Configure the SMBus Clock Timeout. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). - * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n - * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n - * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout - * @param I2Cx I2C Instance. - * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. - * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH - * @param TimeoutB - * @retval None - */ -__STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, - uint32_t TimeoutB) -{ - MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, - TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); -} - -/** - * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note These bits can only be programmed when TimeoutA is disabled. - * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA - * @param I2Cx I2C Instance. - * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) -{ - WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); -} - -/** - * @brief Get the SMBus Clock TimeoutA setting. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); -} - -/** - * @brief Set the SMBus Clock TimeoutA mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note This bit can only be programmed when TimeoutA is disabled. - * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode - * @param I2Cx I2C Instance. - * @param TimeoutAMode This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) -{ - WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); -} - -/** - * @brief Get the SMBus Clock TimeoutA mode. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW - * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); -} - -/** - * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note These bits can only be programmed when TimeoutB is disabled. - * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB - * @param I2Cx I2C Instance. - * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) -{ - WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); -} - -/** - * @brief Get the SMBus Extended Cumulative Clock TimeoutB setting. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); -} - -/** - * @brief Enable the SMBus Clock Timeout. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n - * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout - * @param I2Cx I2C Instance. - * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA - * @arg @ref LL_I2C_SMBUS_TIMEOUTB - * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) -{ - SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); -} - -/** - * @brief Disable the SMBus Clock Timeout. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n - * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout - * @param I2Cx I2C Instance. - * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA - * @arg @ref LL_I2C_SMBUS_TIMEOUTB - * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) -{ - CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); -} - -/** - * @brief Check if the SMBus Clock Timeout is enabled or disabled. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n - * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout - * @param I2Cx I2C Instance. - * @param ClockTimeout This parameter can be one of the following values: - * @arg @ref LL_I2C_SMBUS_TIMEOUTA - * @arg @ref LL_I2C_SMBUS_TIMEOUTB - * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout) -{ - return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \ - (ClockTimeout)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable TXIS interrupt. - * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); -} - -/** - * @brief Disable TXIS interrupt. - * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); -} - -/** - * @brief Check if the TXIS Interrupt is enabled or disabled. - * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable RXNE interrupt. - * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); -} - -/** - * @brief Disable RXNE interrupt. - * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); -} - -/** - * @brief Check if the RXNE Interrupt is enabled or disabled. - * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Address match interrupt (slave mode only). - * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); -} - -/** - * @brief Disable Address match interrupt (slave mode only). - * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); -} - -/** - * @brief Check if Address match interrupt is enabled or disabled. - * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Not acknowledge received interrupt. - * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); -} - -/** - * @brief Disable Not acknowledge received interrupt. - * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); -} - -/** - * @brief Check if Not acknowledge received interrupt is enabled or disabled. - * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable STOP detection interrupt. - * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); -} - -/** - * @brief Disable STOP detection interrupt. - * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); -} - -/** - * @brief Check if STOP detection interrupt is enabled or disabled. - * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Transfer Complete interrupt. - * @note Any of these events will generate interrupt : - * Transfer Complete (TC) - * Transfer Complete Reload (TCR) - * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); -} - -/** - * @brief Disable Transfer Complete interrupt. - * @note Any of these events will generate interrupt : - * Transfer Complete (TC) - * Transfer Complete Reload (TCR) - * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); -} - -/** - * @brief Check if Transfer Complete interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable Error interrupts. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note Any of these errors will generate interrupt : - * Arbitration Loss (ARLO) - * Bus Error detection (BERR) - * Overrun/Underrun (OVR) - * SMBus Timeout detection (TIMEOUT) - * SMBus PEC error detection (PECERR) - * SMBus Alert pin event detection (ALERT) - * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); -} - -/** - * @brief Disable Error interrupts. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note Any of these errors will generate interrupt : - * Arbitration Loss (ARLO) - * Bus Error detection (BERR) - * Overrun/Underrun (OVR) - * SMBus Timeout detection (TIMEOUT) - * SMBus PEC error detection (PECERR) - * SMBus Alert pin event detection (ALERT) - * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); -} - -/** - * @brief Check if Error interrupts are enabled or disabled. - * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_FLAG_management FLAG_management - * @{ - */ - -/** - * @brief Indicate the status of Transmit data register empty flag. - * @note RESET: When next data is written in Transmit data register. - * SET: When Transmit data register is empty. - * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Transmit interrupt flag. - * @note RESET: When next data is written in Transmit data register. - * SET: When Transmit data register is empty. - * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Receive data register not empty flag. - * @note RESET: When Receive data register is read. - * SET: When the received data is copied in Receive data register. - * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Address matched flag (slave mode). - * @note RESET: Clear default value. - * SET: When the received slave address matched with one of the enabled slave address. - * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Not Acknowledge received flag. - * @note RESET: Clear default value. - * SET: When a NACK is received after a byte transmission. - * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Stop detection flag. - * @note RESET: Clear default value. - * SET: When a Stop condition is detected. - * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Transfer complete flag (master mode). - * @note RESET: Clear default value. - * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. - * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Transfer complete flag (master mode). - * @note RESET: Clear default value. - * SET: When RELOAD=1 and NBYTES date have been transferred. - * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Bus error flag. - * @note RESET: Clear default value. - * SET: When a misplaced Start or Stop condition is detected. - * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Arbitration lost flag. - * @note RESET: Clear default value. - * SET: When arbitration lost. - * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Overrun/Underrun flag (slave mode). - * @note RESET: Clear default value. - * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). - * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of SMBus PEC error flag in reception. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note RESET: Clear default value. - * SET: When the received PEC does not match with the PEC register content. - * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of SMBus Timeout detection flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note RESET: Clear default value. - * SET: When a timeout or extended clock timeout occurs. - * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of SMBus alert flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note RESET: Clear default value. - * SET: When SMBus host configuration, SMBus alert enabled and - * a falling edge event occurs on SMBA pin. - * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of Bus Busy flag. - * @note RESET: Clear default value. - * SET: When a Start condition is detected. - * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL); -} - -/** - * @brief Clear Address Matched flag. - * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); -} - -/** - * @brief Clear Not Acknowledge flag. - * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); -} - -/** - * @brief Clear Stop detection flag. - * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); -} - -/** - * @brief Clear Transmit data register empty flag (TXE). - * @note This bit can be clear by software in order to flush the transmit data register (TXDR). - * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) -{ - WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); -} - -/** - * @brief Clear Bus error flag. - * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); -} - -/** - * @brief Clear Arbitration lost flag. - * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); -} - -/** - * @brief Clear Overrun/Underrun flag. - * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); -} - -/** - * @brief Clear SMBus PEC error flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); -} - -/** - * @brief Clear SMBus Timeout detection flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); -} - -/** - * @brief Clear SMBus Alert flag. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Enable automatic STOP condition generation (master mode). - * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. - * This bit has no effect in slave mode or when RELOAD bit is set. - * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); -} - -/** - * @brief Disable automatic STOP condition generation (master mode). - * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. - * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); -} - -/** - * @brief Check if automatic STOP condition is enabled or disabled. - * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL); -} - -/** - * @brief Enable reload mode (master mode). - * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. - * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); -} - -/** - * @brief Disable reload mode (master mode). - * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). - * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); -} - -/** - * @brief Check if reload mode is enabled or disabled. - * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL); -} - -/** - * @brief Configure the number of bytes for transfer. - * @note Changing these bits when START bit is set is not allowed. - * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize - * @param I2Cx I2C Instance. - * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); -} - -/** - * @brief Get the number of bytes configured for transfer. - * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); -} - -/** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code - or next received byte. - * @note Usage in Slave mode only. - * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData - * @param I2Cx I2C Instance. - * @param TypeAcknowledge This parameter can be one of the following values: - * @arg @ref LL_I2C_ACK - * @arg @ref LL_I2C_NACK - * @retval None - */ -__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); -} - -/** - * @brief Generate a START or RESTART condition - * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. - * This action has no effect when RELOAD is set. - * @rmtoll CR2 START LL_I2C_GenerateStartCondition - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_START); -} - -/** - * @brief Generate a STOP condition after the current byte transfer (master mode). - * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_STOP); -} - -/** - * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). - * @note The master sends the complete 10bit slave address read sequence : - * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address - in Read direction. - * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); -} - -/** - * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). - * @note The master only sends the first 7 bits of 10bit address in Read direction. - * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); -} - -/** - * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. - * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL); -} - -/** - * @brief Configure the transfer direction (master mode). - * @note Changing these bits when START bit is set is not allowed. - * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest - * @param I2Cx I2C Instance. - * @param TransferRequest This parameter can be one of the following values: - * @arg @ref LL_I2C_REQUEST_WRITE - * @arg @ref LL_I2C_REQUEST_READ - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); -} - -/** - * @brief Get the transfer direction requested (master mode). - * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_REQUEST_WRITE - * @arg @ref LL_I2C_REQUEST_READ - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); -} - -/** - * @brief Configure the slave address for transfer (master mode). - * @note Changing these bits when START bit is set is not allowed. - * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr - * @param I2Cx I2C Instance. - * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); -} - -/** - * @brief Get the slave address programmed for transfer. - * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0x3F - */ -__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n - * CR2 ADD10 LL_I2C_HandleTransfer\n - * CR2 RD_WRN LL_I2C_HandleTransfer\n - * CR2 START LL_I2C_HandleTransfer\n - * CR2 STOP LL_I2C_HandleTransfer\n - * CR2 RELOAD LL_I2C_HandleTransfer\n - * CR2 NBYTES LL_I2C_HandleTransfer\n - * CR2 AUTOEND LL_I2C_HandleTransfer\n - * CR2 HEAD10R LL_I2C_HandleTransfer - * @param I2Cx I2C Instance. - * @param SlaveAddr Specifies the slave address to be programmed. - * @param SlaveAddrSize This parameter can be one of the following values: - * @arg @ref LL_I2C_ADDRSLAVE_7BIT - * @arg @ref LL_I2C_ADDRSLAVE_10BIT - * @param TransferSize Specifies the number of bytes to be programmed. - * This parameter must be a value between Min_Data=0 and Max_Data=255. - * @param EndMode This parameter can be one of the following values: - * @arg @ref LL_I2C_MODE_RELOAD - * @arg @ref LL_I2C_MODE_AUTOEND - * @arg @ref LL_I2C_MODE_SOFTEND - * @arg @ref LL_I2C_MODE_SMBUS_RELOAD - * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC - * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC - * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC - * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC - * @param Request This parameter can be one of the following values: - * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP - * @arg @ref LL_I2C_GENERATE_STOP - * @arg @ref LL_I2C_GENERATE_START_READ - * @arg @ref LL_I2C_GENERATE_START_WRITE - * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ - * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE - * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ - * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE - * @retval None - */ -__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, - uint32_t TransferSize, uint32_t EndMode, uint32_t Request) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \ - ((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \ - (((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U)); - - /* update CR2 register */ - MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | - I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | - I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, - tmp); -} - -/** - * @brief Indicate the value of transfer direction (slave mode). - * @note RESET: Write transfer, Slave enters in receiver mode. - * SET: Read transfer, Slave enters in transmitter mode. - * @rmtoll ISR DIR LL_I2C_GetTransferDirection - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_DIRECTION_WRITE - * @arg @ref LL_I2C_DIRECTION_READ - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); -} - -/** - * @brief Return the slave matched address. - * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); -} - -/** - * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition - or an Address Matched is received. - * This bit has no effect when RELOAD bit is set. - * This bit has no effect in device mode when SBC bit is not set. - * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); -} - -/** - * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL); -} - -/** - * @brief Get the SMBus Packet Error byte calculated. - * @note The macro IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll PECR PEC LL_I2C_GetSMBusPEC - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); -} - -/** - * @brief Read Receive Data register. - * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx) -{ - return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); -} - -/** - * @brief Write in Transmit Data Register . - * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 - * @param I2Cx I2C Instance. - * @param Data Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) -{ - WRITE_REG(I2Cx->TXDR, Data); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature - * @{ - */ - -/** - * @brief Enable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_I2C_Enable_SelectedTrigger - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Enable_SelectedTrigger(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN); -} - -/** - * @brief Disable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_I2C_Disable_SelectedTrigger - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Disable_SelectedTrigger(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN); -} - -/** - * @brief Indicate if selected Trigger is disabled or enabled - * @rmtoll AUTOCR TRIGEN LL_I2C_IsEnabled_SelectedTrigger - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled_SelectedTrigger(const I2C_TypeDef *I2Cx) -{ - return ((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGEN) == (I2C_AUTOCR_TRIGEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_I2C_SetTriggerPolarity - * @param I2Cx I2C Instance. - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_I2C_TRIG_POLARITY_RISING - * @arg @ref LL_I2C_TRIG_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetTriggerPolarity(I2C_TypeDef *I2Cx, uint32_t Polarity) -{ - MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL, Polarity); -} - -/** - * @brief Get the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_I2C_GetTriggerPolarity - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_TRIG_POLARITY_RISING - * @arg @ref LL_I2C_TRIG_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_I2C_GetTriggerPolarity(const I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGPOL)); -} - -/** - * @brief Set the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_I2C_SetSelectedTrigger - * @param I2Cx I2C Instance. - * @param Trigger This parameter can be one of the following values: - * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG - * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG - * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG - * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG - * @arg @ref LL_I2C_GRP1_EXTI5_TRG - * @arg @ref LL_I2C_GRP1_EXTI9_TRG - * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG - * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG - * @arg @ref LL_I2C_GRP1_COMP1_TRG - * @arg @ref LL_I2C_GRP1_COMP2_TRG - * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG - * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG - * @arg @ref LL_I2C_GRP2_EXTI5_TRG - * @arg @ref LL_I2C_GRP2_EXTI8_TRG - * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG - * @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG - * @arg @ref LL_I2C_GRP2_COMP1_TRG - * @arg @ref LL_I2C_GRP2_COMP2_TRG - * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG - * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetSelectedTrigger(I2C_TypeDef *I2Cx, uint32_t Trigger) -{ - MODIFY_REG(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL, (Trigger & I2C_AUTOCR_TRIGSEL_Msk)); -} - -/** - * @brief Get the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_I2C_GetSelectedTrigger - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_GRP1_GPDMA_CH0_TCF_TRG - * @arg @ref LL_I2C_GRP1_GPDMA_CH1_TCF_TRG - * @arg @ref LL_I2C_GRP1_GPDMA_CH2_TCF_TRG - * @arg @ref LL_I2C_GRP1_GPDMA_CH3_TCF_TRG - * @arg @ref LL_I2C_GRP1_EXTI5_TRG - * @arg @ref LL_I2C_GRP1_EXTI9_TRG - * @arg @ref LL_I2C_GRP1_LPTIM1_CH1_TRG - * @arg @ref LL_I2C_GRP1_LPTIM2_CH1_TRG - * @arg @ref LL_I2C_GRP1_COMP1_TRG - * @arg @ref LL_I2C_GRP1_COMP2_TRG - * @arg @ref LL_I2C_GRP1_RTC_ALRA_TRG - * @arg @ref LL_I2C_GRP1_RTC_WUT_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH0_TCF_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH1_TCF_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH2_TCF_TRG - * @arg @ref LL_I2C_GRP2_LPDMA_CH3_TCF_TRG - * @arg @ref LL_I2C_GRP2_EXTI5_TRG - * @arg @ref LL_I2C_GRP2_EXTI8_TRG - * @arg @ref LL_I2C_GRP2_LPTIM1_CH1_TRG - * @arg @ref LL_I2C_GRP2_LPTIM3_CH1_TRG - * @arg @ref LL_I2C_GRP2_COMP1_TRG - * @arg @ref LL_I2C_GRP2_COMP2_TRG - * @arg @ref LL_I2C_GRP2_RTC_ALRA_TRG - * @arg @ref LL_I2C_GRP2_RTC_WUT_TRG - */ -__STATIC_INLINE uint32_t LL_I2C_GetSelectedTrigger(const I2C_TypeDef *I2Cx) -{ - if (IS_LL_I2C_GRP2_INSTANCE(I2Cx)) - { - return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP2)); - } - else - { - return (uint32_t)((READ_BIT(I2Cx->AUTOCR, I2C_AUTOCR_TRIGSEL) | LL_I2C_TRIG_GRP1)); - } -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); -void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* I2C1 || I2C2 || I2C3 || I2C4 || I2C5 || I2C6 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_I2C_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h deleted file mode 100644 index f419b8131..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_icache.h +++ /dev/null @@ -1,782 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_icache.h - * @author MCD Application Team - * @brief Header file of ICACHE LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion ------------------------------------*/ -#ifndef STM32U5xx_LL_ICACHE_H -#define STM32U5xx_LL_ICACHE_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes -----------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(ICACHE) - -/** @defgroup ICACHE_LL ICACHE - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ICACHE_LL_REGION_CONFIG ICACHE Exported Configuration structure - * @{ - */ - -/** - * @brief LL ICACHE region configuration structure definition - */ -typedef struct -{ - uint32_t BaseAddress; /*!< Configures the C-AHB base address to be remapped */ - - uint32_t RemapAddress; /*!< Configures the remap address to be remapped */ - - uint32_t Size; /*!< Configures the region size. - This parameter can be a value of @ref ICACHE_LL_EC_Region_Size */ - - uint32_t TrafficRoute; /*!< Selects the traffic route. - This parameter can be a value of @ref ICACHE_LL_EC_Traffic_Route */ - - uint32_t OutputBurstType; /*!< Selects the output burst type. - This parameter can be a value of @ref ICACHE_LL_EC_Output_Burst_Type */ -} LL_ICACHE_RegionTypeDef; - -/** - * @} - */ - -/* Exported constants -------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Constants ICACHE Exported Constants - * @{ - */ - -/** @defgroup ICACHE_LL_EC_WaysSelection Ways selection - * @{ - */ -#define LL_ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ -#define LL_ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Monitor_Type Monitor type - * @{ - */ -#define LL_ICACHE_MONITOR_HIT ICACHE_CR_HITMEN /*!< Hit monitor counter */ -#define LL_ICACHE_MONITOR_MISS ICACHE_CR_MISSMEN /*!< Miss monitor counter */ -#define LL_ICACHE_MONITOR_ALL (ICACHE_CR_HITMEN | ICACHE_CR_MISSMEN) /*!< All monitors counters */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_ICACHE_ReadReg function - * @{ - */ -#define LL_ICACHE_SR_BUSYF ICACHE_SR_BUSYF /*!< Busy flag */ -#define LL_ICACHE_SR_BSYENDF ICACHE_SR_BSYENDF /*!< Busy end flag */ -#define LL_ICACHE_SR_ERRF ICACHE_SR_ERRF /*!< Cache error flag */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_ICACHE_WriteReg function - * @{ - */ -#define LL_ICACHE_FCR_CBSYENDF ICACHE_FCR_CBSYENDF /*!< Busy end flag */ -#define LL_ICACHE_FCR_CERRF ICACHE_FCR_CERRF /*!< Cache error flag */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_ICACHE_ReadReg and LL_ICACHE_WriteReg functions - * @{ - */ -#define LL_ICACHE_IER_BSYENDIE ICACHE_IER_BSYENDIE /*!< Busy end interrupt */ -#define LL_ICACHE_IER_ERRIE ICACHE_IER_ERRIE /*!< Cache error interrupt */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Region Remapped Region number - * @{ - */ -#define LL_ICACHE_REGION_0 0U /*!< Region 0 */ -#define LL_ICACHE_REGION_1 1U /*!< Region 1 */ -#define LL_ICACHE_REGION_2 2U /*!< Region 2 */ -#define LL_ICACHE_REGION_3 3U /*!< Region 3 */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Region_Size Remapped Region size - * @{ - */ -#define LL_ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define LL_ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define LL_ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define LL_ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define LL_ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define LL_ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define LL_ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Traffic_Route Remapped Traffic route - * @{ - */ -#define LL_ICACHE_MASTER1_PORT 0U /*!< Master1 port */ -#define LL_ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ -/** - * @} - */ - -/** @defgroup ICACHE_LL_EC_Output_Burst_Type Remapped Output burst type - * @{ - */ -#define LL_ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ -#define LL_ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros ----------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Macros ICACHE Exported Macros - * @{ - */ - -/** @defgroup ICACHE_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ICACHE register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ICACHE_WriteReg(__REG__, __VALUE__) WRITE_REG(ICACHE->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ICACHE register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ICACHE_ReadReg(__REG__) READ_REG(ICACHE->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ICACHE_LL_Exported_Functions ICACHE Exported Functions - * @{ - */ - -/** @defgroup ICACHE_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable the ICACHE. - * @rmtoll CR EN LL_ICACHE_Enable - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Enable(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_EN); -} - -/** - * @brief Disable the ICACHE. - * @rmtoll CR EN LL_ICACHE_Disable - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Disable(void) -{ - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); -} - -/** - * @brief Return if ICACHE is enabled or not. - * @rmtoll CR EN LL_ICACHE_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabled(void) -{ - return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) == (ICACHE_CR_EN)) ? 1UL : 0UL); -} - -/** - * @brief Select the ICACHE operating mode. - * @rmtoll CR WAYSEL LL_ICACHE_SetMode - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_ICACHE_1WAY - * @arg @ref LL_ICACHE_2WAYS - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetMode(uint32_t Mode) -{ - MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, Mode); -} - -/** - * @brief Get the selected ICACHE operating mode. - * @rmtoll CR WAYSEL LL_ICACHE_GetMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_1WAY - * @arg @ref LL_ICACHE_2WAYS - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetMode(void) -{ - return (READ_BIT(ICACHE->CR, ICACHE_CR_WAYSEL)); -} - -/** - * @brief Invalidate the ICACHE. - * @note Until the BSYEND flag is set, the cache is bypassed. - * @rmtoll CR CACHEINV LL_ICACHE_Invalidate - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_Invalidate(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_Monitors Monitors - * @{ - */ - -/** - * @brief Enable the hit/miss monitor(s). - * @rmtoll CR HITMEN LL_ICACHE_EnableMonitors - * @rmtoll CR MISSMEN LL_ICACHE_EnableMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableMonitors(uint32_t Monitors) -{ - SET_BIT(ICACHE->CR, Monitors); -} - -/** - * @brief Disable the hit/miss monitor(s). - * @rmtoll CR HITMEN LL_ICACHE_DisableMonitors - * @rmtoll CR MISSMEN LL_ICACHE_DisableMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableMonitors(uint32_t Monitors) -{ - CLEAR_BIT(ICACHE->CR, Monitors); -} - -/** - * @brief Check if the monitor(s) is(are) enabled or disabled. - * @rmtoll CR HITMEN LL_ICACHE_IsEnabledMonitors - * @rmtoll CR MISSMEN LL_ICACHE_IsEnabledMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval State of parameter value (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledMonitors(uint32_t Monitors) -{ - return ((READ_BIT(ICACHE->CR, Monitors) == (Monitors)) ? 1UL : 0UL); -} - -/** - * @brief Reset the hit/miss monitor(s). - * @rmtoll CR HITMRST LL_ICACHE_ResetMonitors - * @rmtoll CR MISSMRST LL_ICACHE_ResetMonitors - * @param Monitors This parameter can be one or a combination of the following values: - * @arg @ref LL_ICACHE_MONITOR_HIT - * @arg @ref LL_ICACHE_MONITOR_MISS - * @arg @ref LL_ICACHE_MONITOR_ALL - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ResetMonitors(uint32_t Monitors) -{ - /* Reset */ - SET_BIT(ICACHE->CR, (Monitors << 2U)); - /* Release reset */ - CLEAR_BIT(ICACHE->CR, (Monitors << 2U)); -} - -/** - * @brief Get the Hit monitor. - * @note Upon reaching the 32-bit maximum value, hit monitor does not wrap. - * @rmtoll HMONR HITMON LL_ICACHE_GetHitMonitor - * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetHitMonitor(void) -{ - return (ICACHE->HMONR); -} - -/** - * @brief Get the Miss monitor. - * @note Upon reaching the 16-bit maximum value, miss monitor does not wrap. - * @rmtoll MMONR MISSMON LL_ICACHE_GetMissMonitor - * @retval Value between Min_Data=0 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetMissMonitor(void) -{ - return (ICACHE->MMONR); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable BSYEND interrupt. - * @rmtoll IER BSYENDIE LL_ICACHE_EnableIT_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableIT_BSYEND(void) -{ - SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); -} - -/** - * @brief Disable BSYEND interrupt. - * @rmtoll IER BSYENDIE LL_ICACHE_DisableIT_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableIT_BSYEND(void) -{ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); -} - -/** - * @brief Check if the BSYEND Interrupt is enabled or disabled. - * @rmtoll IER BSYENDIE LL_ICACHE_IsEnabledIT_BSYEND - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_BSYEND(void) -{ - return ((READ_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE) == (ICACHE_IER_BSYENDIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable ERR interrupt. - * @rmtoll IER ERRIE LL_ICACHE_EnableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableIT_ERR(void) -{ - SET_BIT(ICACHE->IER, ICACHE_IER_ERRIE); -} - -/** - * @brief Disable ERR interrupt. - * @rmtoll IER ERRIE LL_ICACHE_DisableIT_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableIT_ERR(void) -{ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); -} - -/** - * @brief Check if the ERR Interrupt is enabled or disabled. - * @rmtoll IER ERRIE LL_ICACHE_IsEnabledIT_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledIT_ERR(void) -{ - return ((READ_BIT(ICACHE->IER, ICACHE_IER_ERRIE) == (ICACHE_IER_ERRIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Indicate the status of an ongoing operation flag. - * @rmtoll SR BUSYF LL_ICACHE_IsActiveFlag_BUSY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BUSY(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == (ICACHE_SR_BUSYF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of an operation end flag. - * @rmtoll SR BSYEND LL_ICACHE_IsActiveFlag_BSYEND - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_BSYEND(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == (ICACHE_SR_BSYENDF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate the status of an error flag. - * @rmtoll SR ERRF LL_ICACHE_IsActiveFlag_ERR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsActiveFlag_ERR(void) -{ - return ((READ_BIT(ICACHE->SR, ICACHE_SR_ERRF) == (ICACHE_SR_ERRF)) ? 1UL : 0UL); -} - -/** - * @brief Clear busy end of operation flag. - * @rmtoll FCR CBSYENDF LL_ICACHE_ClearFlag_BSYEND - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ClearFlag_BSYEND(void) -{ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); -} - -/** - * @brief Clear error flag. - * @rmtoll FCR ERRF LL_ICACHE_ClearFlag_ERR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_ClearFlag_ERR(void) -{ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); -} - -/** - * @} - */ - -/** @defgroup ICACHE_LL_EF_REGION_Management REGION_Management - * @{ - */ - -/** - * @brief Enable the remapped memory region. - * @note The region must have been already configured. - * @rmtoll CRRx REN LL_ICACHE_EnableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_EnableRegion(uint32_t Region) -{ - SET_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN); -} - -/** - * @brief Disable the remapped memory region. - * @rmtoll CRRx REN LL_ICACHE_DisableRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_DisableRegion(uint32_t Region) -{ - CLEAR_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN); -} - -/** - * @brief Return if remapped memory region is enabled or not. - * @rmtoll CRRx REN LL_ICACHE_IsEnabledRegion - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ICACHE_IsEnabledRegion(uint32_t Region) -{ - return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REN) == (ICACHE_CRRx_REN)) ? 1UL : 0UL); -} - -/** - * @brief Select the memory remapped region base address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx BASEADDR LL_ICACHE_SetRegionBaseAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Address Alias address in the Code region - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionBaseAddress(uint32_t Region, uint32_t Address) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR, ((Address & 0x1FFFFFFFU) >> 21U)); -} - -/** - * @brief Get the memory remapped region base address. - * @note The base address is the alias in the Code region. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx BASEADDR LL_ICACHE_GetRegionBaseAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Address Alias address in the Code region - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionBaseAddress(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_BASEADDR) << 21U); -} - -/** - * @brief Select the memory remapped region address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx REMAPADDR LL_ICACHE_SetRegionRemapAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Address Memory address to remap - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionRemapAddress(uint32_t Region, uint32_t Address) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REMAPADDR, ((Address >> 21U) << ICACHE_CRRx_REMAPADDR_Pos)); -} - -/** - * @brief Get the memory remapped region address. - * @note The useful bits depends on RSIZE as described in the Reference Manual. - * @rmtoll CRRx REMAPADDR LL_ICACHE_GetRegionRemapAddress - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Address Remapped memory address - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionRemapAddress(uint32_t Region) -{ - return ((READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_REMAPADDR) >> ICACHE_CRRx_REMAPADDR_Pos) << 21U); -} - -/** - * @brief Select the memory remapped region size. - * @rmtoll CRRx RSIZE LL_ICACHE_SetRegionSize - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Size This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGIONSIZE_2MB - * @arg @ref LL_ICACHE_REGIONSIZE_4MB - * @arg @ref LL_ICACHE_REGIONSIZE_8MB - * @arg @ref LL_ICACHE_REGIONSIZE_16MB - * @arg @ref LL_ICACHE_REGIONSIZE_32MB - * @arg @ref LL_ICACHE_REGIONSIZE_64MB - * @arg @ref LL_ICACHE_REGIONSIZE_128MB - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionSize(uint32_t Region, uint32_t Size) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_RSIZE, (Size << ICACHE_CRRx_RSIZE_Pos)); -} - -/** - * @brief Get the selected the memory remapped region size. - * @rmtoll CRRx RSIZE LL_ICACHE_GetRegionSize - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_REGIONSIZE_2MB - * @arg @ref LL_ICACHE_REGIONSIZE_4MB - * @arg @ref LL_ICACHE_REGIONSIZE_8MB - * @arg @ref LL_ICACHE_REGIONSIZE_16MB - * @arg @ref LL_ICACHE_REGIONSIZE_32MB - * @arg @ref LL_ICACHE_REGIONSIZE_64MB - * @arg @ref LL_ICACHE_REGIONSIZE_128MB - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionSize(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_RSIZE) >> ICACHE_CRRx_RSIZE_Pos); -} - -/** - * @brief Select the memory remapped region output burst type. - * @rmtoll CRRx HBURST LL_ICACHE_SetRegionOutputBurstType - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Type This parameter can be one of the following values: - * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP - * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionOutputBurstType(uint32_t Region, uint32_t Type) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_HBURST, Type); -} - -/** - * @brief Get the selected the memory remapped region output burst type. - * @rmtoll CRRx HBURST LL_ICACHE_GetRegionOutputBurstType - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_OUTPUT_BURST_WRAP - * @arg @ref LL_ICACHE_OUTPUT_BURST_INCR - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionOutputBurstType(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_HBURST)); -} - -/** - * @brief Select the memory remapped region cache master port. - * @rmtoll CRRx MSTSEL LL_ICACHE_SetRegionMasterPort - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @param Port This parameter can be one of the following values: - * @arg @ref LL_ICACHE_MASTER1_PORT - * @arg @ref LL_ICACHE_MASTER2_PORT - * @retval None - */ -__STATIC_INLINE void LL_ICACHE_SetRegionMasterPort(uint32_t Region, uint32_t Port) -{ - MODIFY_REG(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_MSTSEL, Port); -} - -/** - * @brief Get the selected the memory remapped region cache master port. - * @rmtoll CRRx MSTSEL LL_ICACHE_GetRegionMasterPort - * @param Region This parameter can be one of the following values: - * @arg @ref LL_ICACHE_REGION_0 - * @arg @ref LL_ICACHE_REGION_1 - * @arg @ref LL_ICACHE_REGION_2 - * @arg @ref LL_ICACHE_REGION_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ICACHE_MASTER1_PORT - * @arg @ref LL_ICACHE_MASTER2_PORT - */ -__STATIC_INLINE uint32_t LL_ICACHE_GetRegionMasterPort(uint32_t Region) -{ - return (READ_BIT(*((__IO uint32_t *)(&(ICACHE->CRR0) + (1U * Region))), \ - ICACHE_CRRx_MSTSEL)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ICACHE_LL_EF_REGION_Init Region Initialization functions - * @{ - */ - -void LL_ICACHE_ConfigRegion(uint32_t Region, const LL_ICACHE_RegionTypeDef *const pICACHE_RegionStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ICACHE */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_ICACHE_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h deleted file mode 100644 index 4a2602911..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpgpio.h +++ /dev/null @@ -1,457 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_lpgpio.h - * @author MCD Application Team - * @brief Header file of LPGPIO LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_LPGPIO_H -#define STM32U5xx_LL_LPGPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (LPGPIO1) - -/** @defgroup LPGPIO_LL LPGPIO - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPGPIO_LL_Private_Macros LPGPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPGPIO_LL_ES_INIT LPGPIO Exported Init structures - * @{ - */ - -/** - * @brief LL LPGPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the LPGPIO pins to be configured. - This parameter can be any value of @ref LPGPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref LPGPIO_LL_EC_MODE.*/ - -} LL_LPGPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LPGPIO_LL_Exported_Constants LPGPIO Exported Constants - * @{ - */ - -/** @defgroup LPGPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_LPGPIO_PIN_0 LPGPIO_BSRR_BS0 /*!< Select pin 0 */ -#define LL_LPGPIO_PIN_1 LPGPIO_BSRR_BS1 /*!< Select pin 1 */ -#define LL_LPGPIO_PIN_2 LPGPIO_BSRR_BS2 /*!< Select pin 2 */ -#define LL_LPGPIO_PIN_3 LPGPIO_BSRR_BS3 /*!< Select pin 3 */ -#define LL_LPGPIO_PIN_4 LPGPIO_BSRR_BS4 /*!< Select pin 4 */ -#define LL_LPGPIO_PIN_5 LPGPIO_BSRR_BS5 /*!< Select pin 5 */ -#define LL_LPGPIO_PIN_6 LPGPIO_BSRR_BS6 /*!< Select pin 6 */ -#define LL_LPGPIO_PIN_7 LPGPIO_BSRR_BS7 /*!< Select pin 7 */ -#define LL_LPGPIO_PIN_8 LPGPIO_BSRR_BS8 /*!< Select pin 8 */ -#define LL_LPGPIO_PIN_9 LPGPIO_BSRR_BS9 /*!< Select pin 9 */ -#define LL_LPGPIO_PIN_10 LPGPIO_BSRR_BS10 /*!< Select pin 10 */ -#define LL_LPGPIO_PIN_11 LPGPIO_BSRR_BS11 /*!< Select pin 11 */ -#define LL_LPGPIO_PIN_12 LPGPIO_BSRR_BS12 /*!< Select pin 12 */ -#define LL_LPGPIO_PIN_13 LPGPIO_BSRR_BS13 /*!< Select pin 13 */ -#define LL_LPGPIO_PIN_14 LPGPIO_BSRR_BS14 /*!< Select pin 14 */ -#define LL_LPGPIO_PIN_15 LPGPIO_BSRR_BS15 /*!< Select pin 15 */ -#define LL_LPGPIO_PIN_ALL (LPGPIO_BSRR_BS0 | LPGPIO_BSRR_BS1 | LPGPIO_BSRR_BS2 | \ - LPGPIO_BSRR_BS3 | LPGPIO_BSRR_BS4 | LPGPIO_BSRR_BS5 | \ - LPGPIO_BSRR_BS6 | LPGPIO_BSRR_BS7 | LPGPIO_BSRR_BS8 | \ - LPGPIO_BSRR_BS9 | LPGPIO_BSRR_BS10 | LPGPIO_BSRR_BS11 | \ - LPGPIO_BSRR_BS12 | LPGPIO_BSRR_BS13 | LPGPIO_BSRR_BS14 | \ - LPGPIO_BSRR_BS15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup LPGPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_LPGPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_LPGPIO_MODE_OUTPUT LPGPIO_MODER_MOD0 /*!< Select output mode */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup LPGPIO_LL_Exported_Macros LPGPIO Exported Macros - * @{ - */ - -/** @defgroup LPGPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in LPGPIO register - * @param __INSTANCE__ LPGPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_LPGPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in LPGPIO register - * @param __INSTANCE__ LPGPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_LPGPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LPGPIO_LL_Exported_Functions LPGPIO Exported Functions - * @{ - */ - -/** @defgroup LPGPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure lpgpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_LPGPIO_SetPinMode - * @param LPGPIOx LPGPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_LPGPIO_MODE_INPUT - * @arg @ref LL_LPGPIO_MODE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_LPGPIO_SetPinMode(GPIO_TypeDef *LPGPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(LPGPIOx->MODER, (LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin))), (Mode << (POSITION_VAL(Pin)))); -} - -/** - * @brief Return lpgpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_LPGPIO_GetPinMode - * @param LPGPIOx LPGPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPGPIO_MODE_INPUT - * @arg @ref LL_LPGPIO_MODE_OUTPUT - */ -__STATIC_INLINE uint32_t LL_LPGPIO_GetPinMode(const GPIO_TypeDef *LPGPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(LPGPIOx->MODER, - (LPGPIO_MODER_MOD0 << (POSITION_VAL(Pin)))) >> (POSITION_VAL(Pin))); -} - -/** - * @} - */ - - -/** @defgroup LPGPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_LPGPIO_ReadInputPort - * @param LPGPIOx LPGPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_LPGPIO_ReadInputPort(const GPIO_TypeDef *LPGPIOx) -{ - return (uint32_t)(READ_REG(LPGPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_LPGPIO_IsInputPinSet - * @param LPGPIOx LPGPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @arg @ref LL_LPGPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPGPIO_IsInputPinSet(const GPIO_TypeDef *LPGPIOx, uint32_t PinMask) -{ - return ((READ_BIT(LPGPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_LPGPIO_WriteOutputPort - * @param LPGPIOx LPGPIO Port - * @param PortValue Level value for each pin of the port - Value between 0 and 0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_LPGPIO_WriteOutputPort(GPIO_TypeDef *LPGPIOx, uint32_t PortValue) -{ - WRITE_REG(LPGPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_LPGPIO_ReadOutputPort - * @param LPGPIOx LPGPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_LPGPIO_ReadOutputPort(const GPIO_TypeDef *LPGPIOx) -{ - return (uint32_t)(READ_REG(LPGPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_LPGPIO_IsOutputPinSet - * @param LPGPIOx LPGPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @arg @ref LL_LPGPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPGPIO_IsOutputPinSet(const GPIO_TypeDef *LPGPIOx, uint32_t PinMask) -{ - return ((READ_BIT(LPGPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_LPGPIO_SetOutputPin - * @param LPGPIOx LPGPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @arg @ref LL_LPGPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_LPGPIO_SetOutputPin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask) -{ - WRITE_REG(LPGPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BRR BRy LL_LPGPIO_ResetOutputPin - * @param LPGPIOx LPGPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @arg @ref LL_LPGPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_LPGPIO_ResetOutputPin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask) -{ - WRITE_REG(LPGPIOx->BRR, PinMask); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_LPGPIO_TogglePin - * @param LPGPIOx LPGPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_LPGPIO_PIN_0 - * @arg @ref LL_LPGPIO_PIN_1 - * @arg @ref LL_LPGPIO_PIN_2 - * @arg @ref LL_LPGPIO_PIN_3 - * @arg @ref LL_LPGPIO_PIN_4 - * @arg @ref LL_LPGPIO_PIN_5 - * @arg @ref LL_LPGPIO_PIN_6 - * @arg @ref LL_LPGPIO_PIN_7 - * @arg @ref LL_LPGPIO_PIN_8 - * @arg @ref LL_LPGPIO_PIN_9 - * @arg @ref LL_LPGPIO_PIN_10 - * @arg @ref LL_LPGPIO_PIN_11 - * @arg @ref LL_LPGPIO_PIN_12 - * @arg @ref LL_LPGPIO_PIN_13 - * @arg @ref LL_LPGPIO_PIN_14 - * @arg @ref LL_LPGPIO_PIN_15 - * @arg @ref LL_LPGPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_LPGPIO_TogglePin(GPIO_TypeDef *LPGPIOx, uint32_t PinMask) -{ - WRITE_REG(LPGPIOx->ODR, READ_REG(LPGPIOx->ODR) ^ PinMask); -} - -/** - * @} - */ - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_LPGPIO_DeInit(const GPIO_TypeDef *LPGPIOx); -ErrorStatus LL_LPGPIO_Init(GPIO_TypeDef *LPGPIOx, const LL_LPGPIO_InitTypeDef *const LPGPIO_InitStruct); -void LL_LPGPIO_StructInit(LL_LPGPIO_InitTypeDef *LPGPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -#endif /* defined (LPGPIO1) */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_LPGPIO_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h deleted file mode 100644 index 4eb069cdf..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_lpuart.h +++ /dev/null @@ -1,2761 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_lpuart.h - * @author MCD Application Team - * @brief Header file of LPUART LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_LPUART_H -#define STM32U5xx_LL_LPUART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (LPUART1) - -/** @defgroup LPUART_LL LPUART - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup LPUART_LL_Private_Variables LPUART Private Variables - * @{ - */ -/* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ -static const uint16_t LPUART_PRESCALER_TAB[] = -{ - (uint16_t)1, - (uint16_t)2, - (uint16_t)4, - (uint16_t)6, - (uint16_t)8, - (uint16_t)10, - (uint16_t)12, - (uint16_t)16, - (uint16_t)32, - (uint16_t)64, - (uint16_t)128, - (uint16_t)256 -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup LPUART_LL_Private_Constants LPUART Private Constants - * @{ - */ -/* Defines used in Baud Rate related macros and corresponding register setting computation */ -#define LPUART_LPUARTDIV_FREQ_MUL 256U -#define LPUART_BRR_MASK 0x000FFFFFU -#define LPUART_BRR_MIN_VALUE 0x00000300U -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPUART_LL_Private_Macros LPUART Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures - * @{ - */ - -/** - * @brief LL LPUART Init Structure definition - */ -typedef struct -{ - uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. - This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetPrescaler().*/ - - uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetBaudRate().*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetDataWidth().*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetStopBitsLength().*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref LPUART_LL_EC_PARITY. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetParity().*/ - - uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. - This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetTransferDirection().*/ - - uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. - - This feature can be modified afterwards using unitary - function @ref LL_LPUART_SetHWFlowCtrl().*/ - -} LL_LPUART_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants - * @{ - */ - -/** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_LPUART_WriteReg function - * @{ - */ -#define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ -#define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ -#define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected clear flag */ -#define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ -#define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ -#define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ -#define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ -#define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_LPUART_ReadReg function - * @{ - */ -#define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ -#define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ -#define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ -#define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ -#define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions - * @{ - */ -#define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty - interrupt enable */ -#define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO - not full interrupt enable */ -#define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ -#define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold - * @{ - */ -#define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ -#define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ -#define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ -#define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ -#define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ -#define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_DIRECTION Direction - * @{ - */ -#define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_PARITY Parity Control - * @{ - */ -#define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_WAKEUP Wakeup - * @{ - */ -#define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ -#define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler - * @{ - */ -#define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ -#define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ -#define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ -#define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 |\ - USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ -#define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ -#define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 |\ - USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ -#define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 |\ - USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ -#define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 |\ - USART_PRESC_PRESCALER_1 |\ - USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ -#define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ -#define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 |\ - USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ -#define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 |\ - USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ -#define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 |\ - USART_PRESC_PRESCALER_1 |\ - USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_STOPBITS Stop Bits - * @{ - */ -#define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap - * @{ - */ -#define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion - * @{ - */ -#define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion - * @{ - */ -#define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion - * @{ - */ -#define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received - in positive/direct logic. (1=H, 0=L) */ -#define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received - in negative/inverse logic. (1=L, 0=H). - The parity bit is also inverted. */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_BITORDER Bit Order - * @{ - */ -#define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, - following the start bit */ -#define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, - following the start bit */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection - * @{ - */ -#define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control - * @{ - */ -#define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested - when there is space in the receive buffer */ -#define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted - when the nCTS input is asserted (tied to 0)*/ -#define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity - * @{ - */ -#define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data - * @{ - */ -#define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection - * @brief LPUART Autonomous Trigger selection - * @{ - */ -#define LL_LPUART_LPDMA1_CH0_TCF_TRG 0U /*!< LPUART LPDMA1 channel0 Internal Trigger */ -#define LL_LPUART_LPDMA1_CH1_TCF_TRG 1U /*!< LPUART LPDMA1 channel1 Internal Trigger */ -#define LL_LPUART_LPDMA1_CH2_TCF_TRG 2U /*!< LPUART LPDMA1 channel2 Internal Trigger */ -#define LL_LPUART_LPDMA1_CH3_TCF_TRG 3U /*!< LPUART LPDMA1 channel3 Internal Trigger */ -#define LL_LPUART_EXTI_LINE6_TRG 4U /*!< LPUART EXTI line 6 Internal Trigger */ -#define LL_LPUART_EXTI_LINE8_TRG 5U /*!< LPUART EXTI line 8 Internal Trigger */ -#define LL_LPUART_LPTIM1_OUT_TRG 6U /*!< LPUART LPTIM1 out Internal Trigger */ -#define LL_LPUART_LPTIM3_OUT_TRG 7U /*!< LPUART LPTIM3 out Internal Trigger */ -#define LL_LPUART_COMP1_OUT_TRG 8U /*!< LPUART COMP1 out Internal Trigger */ -#define LL_LPUART_COMP2_OUT_TRG 9U /*!< LPUART COMP2 out Internal Trigger */ -#define LL_LPUART_RTC_ALRA_TRG 10U /*!< LPUART RTC alarm Internal Trigger */ -#define LL_LPUART_RTC_WUT_TRG 11U /*!< LPUART RTC wakeup Internal Trigger */ -/** - * @} - */ - -/** @defgroup LPUART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity - * @brief LPUART Autonomous Trigger Polarity - * @{ - */ -#define LL_LPUART_TRIG_POLARITY_RISING 0x00000000U /*!< LPUART triggered on rising edge */ -#define LL_LPUART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< LPUART triggered on falling edge */ -/** - * @} - */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros - * @{ - */ - -/** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in LPUART register - * @param __INSTANCE__ LPUART Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in LPUART register - * @param __INSTANCE__ LPUART Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros - * @{ - */ - -/** - * @brief Compute LPUARTDIV value according to Peripheral Clock and - * expected Baud Rate (20-bit value of LPUARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance - * @param __PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_LPUART_PRESCALER_DIV1 - * @arg @ref LL_LPUART_PRESCALER_DIV2 - * @arg @ref LL_LPUART_PRESCALER_DIV4 - * @arg @ref LL_LPUART_PRESCALER_DIV6 - * @arg @ref LL_LPUART_PRESCALER_DIV8 - * @arg @ref LL_LPUART_PRESCALER_DIV10 - * @arg @ref LL_LPUART_PRESCALER_DIV12 - * @arg @ref LL_LPUART_PRESCALER_DIV16 - * @arg @ref LL_LPUART_PRESCALER_DIV32 - * @arg @ref LL_LPUART_PRESCALER_DIV64 - * @arg @ref LL_LPUART_PRESCALER_DIV128 - * @arg @ref LL_LPUART_PRESCALER_DIV256 - * @param __BAUDRATE__ Baud Rate value to achieve - * @retval LPUARTDIV value to be used for BRR register filling - */ -#define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (uint32_t)\ - ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(uint16_t)(__PRESCALER__)]))\ - * LPUART_LPUARTDIV_FREQ_MUL) + (uint32_t)((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions - * @{ - */ - -/** @defgroup LPUART_LL_EF_Configuration Configuration functions - * @{ - */ - -/** - * @brief LPUART Enable - * @rmtoll CR1 UE LL_LPUART_Enable - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR1, USART_CR1_UE); -} - -/** - * @brief LPUART Disable - * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, - * and current operations are discarded. The configuration of the LPUART is kept, but all the status - * flags, in the LPUARTx_ISR are set to their default values. - * @note In order to go into low-power mode without generating errors on the line, - * the TE bit must be reset before and the software must wait - * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. - * The DMA requests are also reset when UE = 0 so the DMA channel must - * be disabled before resetting the UE bit. - * @rmtoll CR1 UE LL_LPUART_Disable - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); -} - -/** - * @brief Indicate if LPUART is enabled - * @rmtoll CR1 UE LL_LPUART_IsEnabled - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); -} - -/** - * @brief FIFO Mode Enable - * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); -} - -/** - * @brief FIFO Mode Disable - * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); -} - -/** - * @brief Indicate if FIFO Mode is enabled - * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); -} - -/** - * @brief Configure TX FIFO Threshold - * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold - * @param LPUARTx LPUART Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) -{ - ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); -} - -/** - * @brief Return TX FIFO Threshold Configuration - * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 - */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); -} - -/** - * @brief Configure RX FIFO Threshold - * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold - * @param LPUARTx LPUART Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) -{ - ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); -} - -/** - * @brief Return RX FIFO Threshold Configuration - * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 - */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); -} - -/** - * @brief Configure TX and RX FIFOs Threshold - * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n - * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold - * @param LPUARTx LPUART Instance - * @param TXThreshold This parameter can be one of the following values: - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 - * @param RXThreshold This parameter can be one of the following values: - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) -{ - ATOMIC_MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | \ - (RXThreshold << USART_CR3_RXFTCFG_Pos)); -} - -/** - * @brief LPUART enabled in STOP Mode - * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that - * LPUART clock selection is HSI or LSE in RCC. - * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief LPUART disabled in STOP Mode - * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode - * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief Indicate if LPUART is enabled in STOP Mode - * (able to wake up MCU from Stop mode or not) - * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); -} - -/** - * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) - * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Receiver Disable - * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Transmitter Enable - * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Transmitter Disable - * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Configure simultaneously enabled/disabled states - * of Transmitter and Receiver - * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n - * CR1 TE LL_LPUART_SetTransferDirection - * @param LPUARTx LPUART Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_LPUART_DIRECTION_NONE - * @arg @ref LL_LPUART_DIRECTION_RX - * @arg @ref LL_LPUART_DIRECTION_TX - * @arg @ref LL_LPUART_DIRECTION_TX_RX - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) -{ - ATOMIC_MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); -} - -/** - * @brief Return enabled/disabled states of Transmitter and Receiver - * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n - * CR1 TE LL_LPUART_GetTransferDirection - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_DIRECTION_NONE - * @arg @ref LL_LPUART_DIRECTION_RX - * @arg @ref LL_LPUART_DIRECTION_TX - * @arg @ref LL_LPUART_DIRECTION_TX_RX - */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); -} - -/** - * @brief Configure Parity (enabled/disabled and parity mode if enabled) - * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. - * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position - * (depending on data width) and parity is checked on the received data. - * @rmtoll CR1 PS LL_LPUART_SetParity\n - * CR1 PCE LL_LPUART_SetParity - * @param LPUARTx LPUART Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_LPUART_PARITY_NONE - * @arg @ref LL_LPUART_PARITY_EVEN - * @arg @ref LL_LPUART_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) -{ - MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); -} - -/** - * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) - * @rmtoll CR1 PS LL_LPUART_GetParity\n - * CR1 PCE LL_LPUART_GetParity - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_PARITY_NONE - * @arg @ref LL_LPUART_PARITY_EVEN - * @arg @ref LL_LPUART_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_LPUART_GetParity(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); -} - -/** - * @brief Set Receiver Wake Up method from Mute mode. - * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod - * @param LPUARTx LPUART Instance - * @param Method This parameter can be one of the following values: - * @arg @ref LL_LPUART_WAKEUP_IDLELINE - * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) -{ - MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); -} - -/** - * @brief Return Receiver Wake Up method from Mute mode - * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_WAKEUP_IDLELINE - * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK - */ -__STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); -} - -/** - * @brief Set Word length (nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M LL_LPUART_SetDataWidth - * @param LPUARTx LPUART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_LPUART_DATAWIDTH_7B - * @arg @ref LL_LPUART_DATAWIDTH_8B - * @arg @ref LL_LPUART_DATAWIDTH_9B - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) -{ - MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); -} - -/** - * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M LL_LPUART_GetDataWidth - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_DATAWIDTH_7B - * @arg @ref LL_LPUART_DATAWIDTH_8B - * @arg @ref LL_LPUART_DATAWIDTH_9B - */ -__STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); -} - -/** - * @brief Allow switch between Mute Mode and Active mode - * @rmtoll CR1 MME LL_LPUART_EnableMuteMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. - * @rmtoll CR1 MME LL_LPUART_DisableMuteMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Indicate if switch between Mute Mode and Active mode is allowed - * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); -} - -/** - * @brief Configure Clock source prescaler for baudrate generator and oversampling - * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler - * @param LPUARTx LPUART Instance - * @param PrescalerValue This parameter can be one of the following values: - * @arg @ref LL_LPUART_PRESCALER_DIV1 - * @arg @ref LL_LPUART_PRESCALER_DIV2 - * @arg @ref LL_LPUART_PRESCALER_DIV4 - * @arg @ref LL_LPUART_PRESCALER_DIV6 - * @arg @ref LL_LPUART_PRESCALER_DIV8 - * @arg @ref LL_LPUART_PRESCALER_DIV10 - * @arg @ref LL_LPUART_PRESCALER_DIV12 - * @arg @ref LL_LPUART_PRESCALER_DIV16 - * @arg @ref LL_LPUART_PRESCALER_DIV32 - * @arg @ref LL_LPUART_PRESCALER_DIV64 - * @arg @ref LL_LPUART_PRESCALER_DIV128 - * @arg @ref LL_LPUART_PRESCALER_DIV256 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); -} - -/** - * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling - * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_PRESCALER_DIV1 - * @arg @ref LL_LPUART_PRESCALER_DIV2 - * @arg @ref LL_LPUART_PRESCALER_DIV4 - * @arg @ref LL_LPUART_PRESCALER_DIV6 - * @arg @ref LL_LPUART_PRESCALER_DIV8 - * @arg @ref LL_LPUART_PRESCALER_DIV10 - * @arg @ref LL_LPUART_PRESCALER_DIV12 - * @arg @ref LL_LPUART_PRESCALER_DIV16 - * @arg @ref LL_LPUART_PRESCALER_DIV32 - * @arg @ref LL_LPUART_PRESCALER_DIV64 - * @arg @ref LL_LPUART_PRESCALER_DIV128 - * @arg @ref LL_LPUART_PRESCALER_DIV256 - */ -__STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); -} - -/** - * @brief Set the length of the stop bits - * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength - * @param LPUARTx LPUART Instance - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_LPUART_STOPBITS_1 - * @arg @ref LL_LPUART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Retrieve the length of the stop bits - * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_STOPBITS_1 - * @arg @ref LL_LPUART_STOPBITS_2 - */ -__STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); -} - -/** - * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) - * @note Call of this function is equivalent to following function call sequence : - * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function - * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function - * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function - * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n - * CR1 PCE LL_LPUART_ConfigCharacter\n - * CR1 M LL_LPUART_ConfigCharacter\n - * CR2 STOP LL_LPUART_ConfigCharacter - * @param LPUARTx LPUART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_LPUART_DATAWIDTH_7B - * @arg @ref LL_LPUART_DATAWIDTH_8B - * @arg @ref LL_LPUART_DATAWIDTH_9B - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_LPUART_PARITY_NONE - * @arg @ref LL_LPUART_PARITY_EVEN - * @arg @ref LL_LPUART_PARITY_ODD - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_LPUART_STOPBITS_1 - * @arg @ref LL_LPUART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, - uint32_t StopBits) -{ - MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); - MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Configure TX/RX pins swapping setting. - * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap - * @param LPUARTx LPUART Instance - * @param SwapConfig This parameter can be one of the following values: - * @arg @ref LL_LPUART_TXRX_STANDARD - * @arg @ref LL_LPUART_TXRX_SWAPPED - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); -} - -/** - * @brief Retrieve TX/RX pins swapping configuration. - * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_TXRX_STANDARD - * @arg @ref LL_LPUART_TXRX_SWAPPED - */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); -} - -/** - * @brief Configure RX pin active level logic - * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel - * @param LPUARTx LPUART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); -} - -/** - * @brief Retrieve RX pin active level logic configuration - * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); -} - -/** - * @brief Configure TX pin active level logic - * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel - * @param LPUARTx LPUART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); -} - -/** - * @brief Retrieve TX pin active level logic configuration - * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); -} - -/** - * @brief Configure Binary data logic. - * - * @note Allow to define how Logical data from the data register are send/received : - * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) - * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic - * @param LPUARTx LPUART Instance - * @param DataLogic This parameter can be one of the following values: - * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); -} - -/** - * @brief Retrieve Binary data configuration - * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE - */ -__STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); -} - -/** - * @brief Configure transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder - * @param LPUARTx LPUART Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_LPUART_BITORDER_LSBFIRST - * @arg @ref LL_LPUART_BITORDER_MSBFIRST - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); -} - -/** - * @brief Return transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_BITORDER_LSBFIRST - * @arg @ref LL_LPUART_BITORDER_MSBFIRST - */ -__STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); -} - -/** - * @brief Set Address of the LPUART node. - * @note This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with address mark detection. - * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. - * (b7-b4 should be set to 0) - * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. - * (This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with 7-bit address mark detection. - * The MSB of the character sent by the transmitter should be equal to 1. - * It may also be used for character detection during normal reception, - * Mute mode inactive (for example, end of block detection in ModBus protocol). - * In this case, the whole received character (8-bit) is compared to the ADD[7:0] - * value and CMF flag is set on match) - * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n - * CR2 ADDM7 LL_LPUART_ConfigNodeAddress - * @param LPUARTx LPUART Instance - * @param AddressLen This parameter can be one of the following values: - * @arg @ref LL_LPUART_ADDRESS_DETECT_4B - * @arg @ref LL_LPUART_ADDRESS_DETECT_7B - * @param NodeAddress 4 or 7 bit Address of the LPUART node. - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) -{ - MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); -} - -/** - * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. - * @note If 4-bit Address Detection is selected in ADDM7, - * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) - * If 7-bit Address Detection is selected in ADDM7, - * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) - * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress - * @param LPUARTx LPUART Instance - * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) - */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); -} - -/** - * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) - * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_ADDRESS_DETECT_4B - * @arg @ref LL_LPUART_ADDRESS_DETECT_7B - */ -__STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); -} - -/** - * @brief Enable RTS HW Flow Control - * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Disable RTS HW Flow Control - * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Enable CTS HW Flow Control - * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Disable CTS HW Flow Control - * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Configure HW Flow Control mode (both CTS and RTS) - * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n - * CR3 CTSE LL_LPUART_SetHWFlowCtrl - * @param LPUARTx LPUART Instance - * @param HardwareFlowControl This parameter can be one of the following values: - * @arg @ref LL_LPUART_HWCONTROL_NONE - * @arg @ref LL_LPUART_HWCONTROL_RTS - * @arg @ref LL_LPUART_HWCONTROL_CTS - * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) -{ - MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); -} - -/** - * @brief Return HW Flow Control configuration (both CTS and RTS) - * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n - * CR3 CTSE LL_LPUART_GetHWFlowCtrl - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_HWCONTROL_NONE - * @arg @ref LL_LPUART_HWCONTROL_RTS - * @arg @ref LL_LPUART_HWCONTROL_CTS - * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS - */ -__STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); -} - -/** - * @brief Enable Overrun detection - * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Disable Overrun detection - * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Indicate if Overrun detection is enabled - * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); -} - -/** - * @brief Configure LPUART BRR register for achieving expected Baud Rate value. - * - * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock and expected Baud Rate values - * @note Peripheral clock and Baud Rate values provided as function parameters should be valid - * (Baud rate value != 0). - * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, - * a care should be taken when generating high baud rates using high PeriphClk - * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. - * @rmtoll BRR BRR LL_LPUART_SetBaudRate - * @param LPUARTx LPUART Instance - * @param PeriphClk Peripheral Clock - * @param PrescalerValue This parameter can be one of the following values: - * @arg @ref LL_LPUART_PRESCALER_DIV1 - * @arg @ref LL_LPUART_PRESCALER_DIV2 - * @arg @ref LL_LPUART_PRESCALER_DIV4 - * @arg @ref LL_LPUART_PRESCALER_DIV6 - * @arg @ref LL_LPUART_PRESCALER_DIV8 - * @arg @ref LL_LPUART_PRESCALER_DIV10 - * @arg @ref LL_LPUART_PRESCALER_DIV12 - * @arg @ref LL_LPUART_PRESCALER_DIV16 - * @arg @ref LL_LPUART_PRESCALER_DIV32 - * @arg @ref LL_LPUART_PRESCALER_DIV64 - * @arg @ref LL_LPUART_PRESCALER_DIV128 - * @arg @ref LL_LPUART_PRESCALER_DIV256 - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, - uint32_t BaudRate) -{ - if (BaudRate != 0U) - { - LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, PrescalerValue, BaudRate); - } -} - -/** - * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @rmtoll BRR BRR LL_LPUART_GetBaudRate - * @param LPUARTx LPUART Instance - * @param PeriphClk Peripheral Clock - * @param PrescalerValue This parameter can be one of the following values: - * @arg @ref LL_LPUART_PRESCALER_DIV1 - * @arg @ref LL_LPUART_PRESCALER_DIV2 - * @arg @ref LL_LPUART_PRESCALER_DIV4 - * @arg @ref LL_LPUART_PRESCALER_DIV6 - * @arg @ref LL_LPUART_PRESCALER_DIV8 - * @arg @ref LL_LPUART_PRESCALER_DIV10 - * @arg @ref LL_LPUART_PRESCALER_DIV12 - * @arg @ref LL_LPUART_PRESCALER_DIV16 - * @arg @ref LL_LPUART_PRESCALER_DIV32 - * @arg @ref LL_LPUART_PRESCALER_DIV64 - * @arg @ref LL_LPUART_PRESCALER_DIV128 - * @arg @ref LL_LPUART_PRESCALER_DIV256 - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(const USART_TypeDef *LPUARTx, uint32_t PeriphClk, - uint32_t PrescalerValue) -{ - uint32_t lpuartdiv; - uint32_t brrresult; - uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); - - lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; - - if (lpuartdiv >= LPUART_BRR_MIN_VALUE) - { - brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); - } - else - { - brrresult = 0x0UL; - } - - return (brrresult); -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature - * @{ - */ - -/** - * @brief Enable Single Wire Half-Duplex mode - * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Disable Single Wire Half-Duplex mode - * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature - * @{ - */ - -/** - * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime - * @param LPUARTx LPUART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) -{ - MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); -} - -/** - * @brief Return DEDT (Driver Enable De-Assertion Time) - * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime - * @param LPUARTx LPUART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : c - */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); -} - -/** - * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime - * @param LPUARTx LPUART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) -{ - MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); -} - -/** - * @brief Return DEAT (Driver Enable Assertion Time) - * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime - * @param LPUARTx LPUART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); -} - -/** - * @brief Enable Driver Enable (DE) Mode - * @rmtoll CR3 DEM LL_LPUART_EnableDEMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Disable Driver Enable (DE) Mode - * @rmtoll CR3 DEM LL_LPUART_DisableDEMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Indicate if Driver Enable (DE) Mode is enabled - * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); -} - -/** - * @brief Select Driver Enable Polarity - * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity - * @param LPUARTx LPUART Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_LPUART_DE_POLARITY_HIGH - * @arg @ref LL_LPUART_DE_POLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) -{ - MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); -} - -/** - * @brief Return Driver Enable Polarity - * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_DE_POLARITY_HIGH - * @arg @ref LL_LPUART_DE_POLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if the LPUART Parity Error Flag is set or not - * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Framing Error Flag is set or not - * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Noise error detected Flag is set or not - * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART OverRun Error Flag is set or not - * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART IDLE line detected Flag is set or not - * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); -} - -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not - * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Transmission Complete Flag is set or not - * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); -} - -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not - * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART CTS interrupt Flag is set or not - * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART CTS Flag is set or not - * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Busy Flag is set or not - * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Character Match Flag is set or not - * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Send Break Flag is set or not - * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not - * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not - * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not - * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART TX FIFO Empty Flag is set or not - * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART RX FIFO Full Flag is set or not - * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART TX FIFO Threshold Flag is set or not - * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART RX FIFO Threshold Flag is set or not - * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); -} - -/** - * @brief Clear Parity Error Flag - * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); -} - -/** - * @brief Clear Framing Error Flag - * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); -} - -/** - * @brief Clear Noise detected Flag - * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); -} - -/** - * @brief Clear OverRun Error Flag - * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); -} - -/** - * @brief Clear IDLE line detected Flag - * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); -} - -/** - * @brief Clear Transmission Complete Flag - * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); -} - -/** - * @brief Clear CTS Interrupt Flag - * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); -} - -/** - * @brief Clear Character Match Flag - * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) -{ - WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); -} - -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt - * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); -} - -/** - * @brief Enable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); -} - -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Enable TX Empty and TX FIFO Not Full Interrupt - * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); -} - -/** - * @brief Enable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Enable Character Match Interrupt - * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Enable TX FIFO Empty Interrupt - * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); -} - -/** - * @brief Enable RX FIFO Full Interrupt - * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); -} - -/** - * @brief Enable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). - * - 0: Interrupt is inhibited - * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. - * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Enable CTS Interrupt - * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Enable TX FIFO Threshold Interrupt - * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); -} - -/** - * @brief Enable RX FIFO Threshold Interrupt - * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); -} - -/** - * @brief Disable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); -} - -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt - * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); -} - -/** - * @brief Disable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); -} - -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Disable TX Empty and TX FIFO Not Full Interrupt - * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); -} - -/** - * @brief Disable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Disable Character Match Interrupt - * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Disable TX FIFO Empty Interrupt - * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); -} - -/** - * @brief Disable RX FIFO Full Interrupt - * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); -} - -/** - * @brief Disable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). - * - 0: Interrupt is inhibited - * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. - * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Disable CTS Interrupt - * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Disable TX FIFO Threshold Interrupt - * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); -} - -/** - * @brief Disable RX FIFO Threshold Interrupt - * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); -} - -/** - * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. - * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); -} - -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. - * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); -} - -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled - * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. - * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. - * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled - * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled - * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART Error Interrupt is enabled or disabled. - * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the LPUART CTS Interrupt is enabled or disabled. - * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled - * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled - * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_DMA_Management DMA_Management - * @{ - */ - -/** - * @brief Enable DMA Mode for reception - * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Disable DMA Mode for reception - * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Check if DMA Mode is enabled for reception - * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) -{ - ATOMIC_SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Disable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) -{ - ATOMIC_CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Check if DMA Mode is enabled for transmission - * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Disable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Indicate if DMA Disabling on Reception Error is disabled - * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); -} - -/** - * @brief Get the LPUART data register address used for DMA transfer - * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n - * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr - * @param LPUARTx LPUART Instance - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT - * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(const USART_TypeDef *LPUARTx, uint32_t Direction) -{ - uint32_t data_reg_addr; - - if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) - { - /* return address of TDR register */ - data_reg_addr = (uint32_t) &(LPUARTx->TDR); - } - else - { - /* return address of RDR register */ - data_reg_addr = (uint32_t) &(LPUARTx->RDR); - } - - return data_reg_addr; -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Read Receiver Data register (Receive Data value, 8 bits) - * @rmtoll RDR RDR LL_LPUART_ReceiveData8 - * @param LPUARTx LPUART Instance - * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(const USART_TypeDef *LPUARTx) -{ - return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR) & 0xFFU); -} - -/** - * @brief Read Receiver Data register (Receive Data value, 9 bits) - * @rmtoll RDR RDR LL_LPUART_ReceiveData9 - * @param LPUARTx LPUART Instance - * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(const USART_TypeDef *LPUARTx) -{ - return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) - * @rmtoll TDR TDR LL_LPUART_TransmitData8 - * @param LPUARTx LPUART Instance - * @param Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) -{ - LPUARTx->TDR = Value; -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) - * @rmtoll TDR TDR LL_LPUART_TransmitData9 - * @param LPUARTx LPUART Instance - * @param Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) -{ - LPUARTx->TDR = Value & 0x1FFUL; -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_Execution Execution - * @{ - */ - -/** - * @brief Request Break sending - * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_SBKRQ); -} - -/** - * @brief Put LPUART in mute mode and set the RWU flag - * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_MMRQ); -} - -/** - * @brief Request a Receive Data and FIFO flush - * @note Allows to discard the received data without reading them, and avoid an overrun - * condition. - * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); -} - -/** - * @brief Request a Transmit data FIFO flush - * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This - * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); -} - -/** - * @} - */ - -/** @defgroup LPUART_LL_EF_AutonomousMode Configuration functions related to Autonomous mode feature - * @{ - */ - -/** - * @brief Enable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_LPUART_Enable_SelectedTrigger - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_Enable_SelectedTrigger(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN); -} - -/** - * @brief Disable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_LPUART_Disable_SelectedTrigger - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_Disable_SelectedTrigger(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN); -} - -/** - * @brief Indicate if selected Trigger is disabled or enabled - * @rmtoll AUTOCR TRIGEN LL_LPUART_IsEnabled_SelectedTrigger - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_SelectedTrigger(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable Autonomous Send Idle Frame feature - * @rmtoll AUTOCR IDLEDIS LL_LPUART_Enable_AutonomousSendIdleFrame - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_Enable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) -{ - CLEAR_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS); -} - -/** - * @brief Disable Autonomous Send Idle Frame feature - * @rmtoll AUTOCR IDLEDIS LL_LPUART_Disable_AutonomousSendIdleFrame - * @param LPUARTx LPUART Instance - * @retval None - */ -__STATIC_INLINE void LL_LPUART_Disable_AutonomousSendIdleFrame(USART_TypeDef *LPUARTx) -{ - SET_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS); -} - -/** - * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled - * @rmtoll AUTOCR IDLEDIS LL_LPUART_IsEnabled_AutonomousSendIdleFrame - * @param LPUARTx LPUART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LPUART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *LPUARTx) -{ - return ((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); -} - -/** - * @brief Configure the Number of transferred data in bytes - * @rmtoll AUTOCR TDN LL_LPUART_SetNbTxData - * @param LPUARTx LPUART Instance - * @param Nbdata This parameter can be a value between 0 and 0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetNbTxData(USART_TypeDef *LPUARTx, uint32_t Nbdata) -{ - MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata); -} - -/** - * @brief Retrieve the Number of transferred data in bytes - * @rmtoll AUTOCR TDN LL_LPUART_GetNbTxData - * @param LPUARTx LPUART Instance - * @retval Returned value can be a value between 0 and 0xFFFF - */ -__STATIC_INLINE uint32_t LL_LPUART_GetNbTxData(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TDN)); -} - -/** - * @brief Set the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_LPUART_SetTriggerPolarity - * @param LPUARTx LPUART Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_LPUART_TRIG_POLARITY_RISING - * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetTriggerPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) -{ - MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity); -} - -/** - * @brief Get the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_LPUART_GetTriggerPolarity - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_TRIG_POLARITY_RISING - * @arg @ref LL_LPUART_TRIG_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_LPUART_GetTriggerPolarity(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)(READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); -} - -/** - * @brief Set the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_LPUART_SetSelectedTrigger - * @param LPUARTx LPUART Instance - * @param Trigger This parameter can be one of the following values: - * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG - * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG - * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG - * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG - * @arg @ref LL_LPUART_EXTI_LINE6_TRG - * @arg @ref LL_LPUART_EXTI_LINE8_TRG - * @arg @ref LL_LPUART_LPTIM1_OUT_TRG - * @arg @ref LL_LPUART_LPTIM3_OUT_TRG - * @arg @ref LL_LPUART_COMP1_OUT_TRG - * @arg @ref LL_LPUART_COMP2_OUT_TRG - * @arg @ref LL_LPUART_RTC_ALRA_TRG - * @arg @ref LL_LPUART_RTC_WUT_TRG - * @retval None - */ -__STATIC_INLINE void LL_LPUART_SetSelectedTrigger(USART_TypeDef *LPUARTx, uint32_t Trigger) -{ - MODIFY_REG(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos)); -} - -/** - * @brief Get the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_LPUART_GetSelectedTrigger - * @param LPUARTx LPUART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LPUART_LPDMA1_CH0_TCF_TRG - * @arg @ref LL_LPUART_LPDMA1_CH1_TCF_TRG - * @arg @ref LL_LPUART_LPDMA1_CH2_TCF_TRG - * @arg @ref LL_LPUART_LPDMA1_CH3_TCF_TRG - * @arg @ref LL_LPUART_EXTI_LINE6_TRG - * @arg @ref LL_LPUART_EXTI_LINE8_TRG - * @arg @ref LL_LPUART_LPTIM1_OUT_TRG - * @arg @ref LL_LPUART_LPTIM3_OUT_TRG - * @arg @ref LL_LPUART_COMP1_OUT_TRG - * @arg @ref LL_LPUART_COMP2_OUT_TRG - * @arg @ref LL_LPUART_RTC_ALRA_TRG - * @arg @ref LL_LPUART_RTC_WUT_TRG - */ -__STATIC_INLINE uint32_t LL_LPUART_GetSelectedTrigger(const USART_TypeDef *LPUARTx) -{ - return (uint32_t)((READ_BIT(LPUARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_LPUART_DeInit(const USART_TypeDef *LPUARTx); -ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, const LL_LPUART_InitTypeDef *LPUART_InitStruct); -void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* LPUART1 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_LPUART_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h deleted file mode 100644 index 8b7fe9fda..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_pwr.h +++ /dev/null @@ -1,3394 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_pwr.h - * @author MCD Application Team - * @brief Header file of PWR LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_PWR_H -#define STM32U5xx_LL_PWR_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (PWR) - -/** @defgroup PWR_LL PWR - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PWR_LL_Exported_Constants PWR Exported Constants - * @{ - */ - -/** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_PWR_WriteReg function - * @{ - */ -#define LL_PWR_SR_CSSF PWR_SR_CSSF /*!< Clear Stop and Standby flags */ -#define LL_PWR_WUSCR_CWUF1 PWR_WUSCR_CWUF1 /*!< Clear Wakeup flag 1 */ -#define LL_PWR_WUSCR_CWUF2 PWR_WUSCR_CWUF2 /*!< Clear Wakeup flag 2 */ -#define LL_PWR_WUSCR_CWUF3 PWR_WUSCR_CWUF3 /*!< Clear Wakeup flag 3 */ -#define LL_PWR_WUSCR_CWUF4 PWR_WUSCR_CWUF4 /*!< Clear Wakeup flag 4 */ -#define LL_PWR_WUSCR_CWUF5 PWR_WUSCR_CWUF5 /*!< Clear Wakeup flag 5 */ -#define LL_PWR_WUSCR_CWUF6 PWR_WUSCR_CWUF6 /*!< Clear Wakeup flag 6 */ -#define LL_PWR_WUSCR_CWUF7 PWR_WUSCR_CWUF7 /*!< Clear Wakeup flag 7 */ -#define LL_PWR_WUSCR_CWUF8 PWR_WUSCR_CWUF8 /*!< Clear Wakeup flag 8 */ -#define LL_PWR_WUSCR_CWUF_ALL PWR_WUSCR_CWUF /*!< Clear all Wakeup flags */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_PWR_ReadReg function - * @{ - */ -#define LL_PWR_FLAG_VOSRDY PWR_VOSR_VOSRDY /*!< Voltage scaling ready flag */ -#define LL_PWR_FLAG_BOOSTRDY PWR_VOSR_BOOSTRDY /*!< VOS EPOD booster ready flag */ -#if defined (PWR_VOSR_USBBOOSTRDY) -#define LL_PWR_FLAG_USBBOOSTRDY PWR_VOSR_USBBOOSTRDY /*!< USB EPOD booster ready flag */ -#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ -#define LL_PWR_FLAG_STOPF PWR_SR_STOPF /*!< Stop flag */ -#define LL_PWR_FLAG_SBF PWR_SR_SBF /*!< Standby flag */ -#define LL_PWR_FLAG_VDDA2RDY PWR_SVMSR_VDDA2RDY /*!< VDDA ready flag (versus 1.8 V threshold) */ -#define LL_PWR_FLAG_VDDA1RDY PWR_SVMSR_VDDA1RDY /*!< VDDA ready flag (versus 1.6 V threshold) */ -#define LL_PWR_FLAG_VDDIO2RDY PWR_SVMSR_VDDIO2RDY /*!< VDDIO2 ready flag */ -#define LL_PWR_FLAG_VDDUSBRDY PWR_SVMSR_VDDUSBRDY /*!< VDDUSB ready flag */ -#define LL_PWR_FLAG_ACTVOSRDY PWR_SVMSR_ACTVOSRDY /*!< Currently applied VOS ready flag */ -#define LL_PWR_FLAG_PVDO PWR_SR2_PVDO /*!< VDD voltage detector output flag */ -#define LL_PWR_FLAG_REGS PWR_SVMSR_REGS /*!< Regulator selection flag */ -#define LL_PWR_FLAG_TEMPH PWR_BDSR_TEMPH /*!< Temperature level flag (versus high threshold) */ -#define LL_PWR_FLAG_TEMPL PWR_BDSR_TEMPL /*!< Temperature level flag (versus low threshold) */ -#define LL_PWR_FLAG_VBATH PWR_BDSR_VBATH /*!< Backup domain voltage level flag (versus high threshold) */ - -#define LL_PWR_WAKEUP_FLAG1 PWR_WUSR_WUF1 /*!< Wakeup flag 1 */ -#define LL_PWR_WAKEUP_FLAG2 PWR_WUSR_WUF2 /*!< Wakeup flag 2 */ -#define LL_PWR_WAKEUP_FLAG3 PWR_WUSR_WUF3 /*!< Wakeup flag 3 */ -#define LL_PWR_WAKEUP_FLAG4 PWR_WUSR_WUF4 /*!< Wakeup flag 4 */ -#define LL_PWR_WAKEUP_FLAG5 PWR_WUSR_WUF5 /*!< Wakeup flag 5 */ -#define LL_PWR_WAKEUP_FLAG6 PWR_WUSR_WUF6 /*!< Wakeup flag 6 */ -#define LL_PWR_WAKEUP_FLAG7 PWR_WUSR_WUF7 /*!< Wakeup flag 7 */ -#define LL_PWR_WAKEUP_FLAG8 PWR_WUSR_WUF8 /*!< Wakeup flag 8 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_LOW_POWER_MODE_SELCTION Low Power Mode Selection - * @{ - */ -#define LL_PWR_STOP0_MODE (0U) /*!< Stop 0 mode */ -#define LL_PWR_STOP1_MODE PWR_CR1_LPMS_0 /*!< Stop 1 mode */ -#define LL_PWR_STOP2_MODE PWR_CR1_LPMS_1 /*!< Stop 2 mode */ -#define LL_PWR_STOP3_MODE (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Stop 3 mode */ -#define LL_PWR_STANDBY_MODE PWR_CR1_LPMS_2 /*!< Standby mode */ -#define LL_PWR_SHUTDOWN_MODE (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1) /*!< Shutdown mode */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_SRAM2_SB_CONTENTS_RETENTION PWR SRAM2 Content Retention in Standby Mode - * @note For some products of the U5 family (please see the Reference Manual), - * the SRAM2 content is preserved based on the same defines in Stop 3 mode. - * @{ - */ -#define LL_PWR_SRAM2_SB_NO_RETENTION 0U /*!< SRAM2 no retention in Stop 3 and Standby mode */ -#define LL_PWR_SRAM2_SB_PAGE1_RETENTION PWR_CR1_RRSB1 /*!< SRAM2 page 1 (8 KB) retention in Stop 3 and Standby mode */ -#define LL_PWR_SRAM2_SB_PAGE2_RETENTION PWR_CR1_RRSB2 /*!< SRAM2 page 2 (54 KB) retention in Stop 3 and Standby mode */ -#define LL_PWR_SRAM2_SB_FULL_RETENTION (PWR_CR1_RRSB1 | PWR_CR1_RRSB2) /*!< SRAM2 all pages retention in Stop 3 and Standby mode */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_SRAM1_STOP_CONTENTS_RETENTION PWR SRAM1 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_SRAM1_STOP_NO_RETENTION 0U /*!< SRAM1 no retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE1_RETENTION (PWR_CR2_SRAM1PDS1) /*!< SRAM1 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE2_RETENTION (PWR_CR2_SRAM1PDS2) /*!< SRAM1 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE3_RETENTION (PWR_CR2_SRAM1PDS3) /*!< SRAM1 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR4_SRAM1PDS4) -#define LL_PWR_SRAM1_STOP_PAGE4_RETENTION (PWR_CR4_SRAM1PDS4) /*!< SRAM1 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE5_RETENTION (PWR_CR4_SRAM1PDS5) /*!< SRAM1 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE6_RETENTION (PWR_CR4_SRAM1PDS6) /*!< SRAM1 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE7_RETENTION (PWR_CR4_SRAM1PDS7) /*!< SRAM1 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE8_RETENTION (PWR_CR4_SRAM1PDS8) /*!< SRAM1 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE9_RETENTION (PWR_CR4_SRAM1PDS9) /*!< SRAM1 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE10_RETENTION (PWR_CR4_SRAM1PDS10) /*!< SRAM1 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE11_RETENTION (PWR_CR4_SRAM1PDS11) /*!< SRAM1 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM1_STOP_PAGE12_RETENTION (PWR_CR4_SRAM1PDS12) /*!< SRAM1 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM1PDS4) */ -#define LL_PWR_SRAM1_STOP_1_3_RETENTION (PWR_CR2_SRAM1PDS1 | PWR_CR2_SRAM1PDS2 | \ - PWR_CR2_SRAM1PDS3) /*!< SRAM1 pages (1 to 3) retention in Stop mode (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR4_SRAM1PDS4) -#define LL_PWR_SRAM1_STOP_4_12_RETENTION (PWR_CR4_SRAM1PDS4 | PWR_CR4_SRAM1PDS5 | \ - PWR_CR4_SRAM1PDS6 | PWR_CR4_SRAM1PDS7 | \ - PWR_CR4_SRAM1PDS8 | PWR_CR4_SRAM1PDS9 | \ - PWR_CR4_SRAM1PDS10 | PWR_CR4_SRAM1PDS11 | \ - PWR_CR4_SRAM1PDS12) /*!< SRAM1 pages (4 to 12) retention in Stop mode (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM1PDS4) */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_SRAM2_STOP_CONTENTS_RETENTION PWR SRAM2 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_SRAM2_STOP_NO_RETENTION 0U /*!< SRAM2 no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_SRAM2_STOP_PAGE1_RETENTION (PWR_CR2_SRAM2PDS1) /*!< SRAM2 page 1 (8 KB) retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_SRAM2_STOP_PAGE2_RETENTION (PWR_CR2_SRAM2PDS2) /*!< SRAM2 page 2 (54 KB) retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_SRAM2_STOP_FULL_RETENTION (PWR_CR2_SRAM2PDS1 | PWR_CR2_SRAM2PDS2) /*!< SRAM2 all pages retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -#if defined (PWR_CR2_SRAM3PDS1) -/** @defgroup PWR_LL_EC_SRAM3_STOP_CONTENTS_RETENTION PWR SRAM3 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_SRAM3_STOP_NO_RETENTION 0U /*!< SRAM3 no retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE1_RETENTION (PWR_CR2_SRAM3PDS1) /*!< SRAM3 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE2_RETENTION (PWR_CR2_SRAM3PDS2) /*!< SRAM3 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE3_RETENTION (PWR_CR2_SRAM3PDS3) /*!< SRAM3 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE4_RETENTION (PWR_CR2_SRAM3PDS4) /*!< SRAM3 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE5_RETENTION (PWR_CR2_SRAM3PDS5) /*!< SRAM3 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE6_RETENTION (PWR_CR2_SRAM3PDS6) /*!< SRAM3 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE7_RETENTION (PWR_CR2_SRAM3PDS7) /*!< SRAM3 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE8_RETENTION (PWR_CR2_SRAM3PDS8) /*!< SRAM3 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR4_SRAM3PDS9) -#define LL_PWR_SRAM3_STOP_PAGE9_RETENTION (PWR_CR4_SRAM3PDS9) /*!< SRAM3 page 9 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE10_RETENTION (PWR_CR4_SRAM3PDS10) /*!< SRAM3 page 10 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE11_RETENTION (PWR_CR4_SRAM3PDS11) /*!< SRAM3 page 11 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE12_RETENTION (PWR_CR4_SRAM3PDS12) /*!< SRAM3 page 12 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM3_STOP_PAGE13_RETENTION (PWR_CR4_SRAM3PDS13) /*!< SRAM3 page 13 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM3PDS9) */ -#define LL_PWR_SRAM3_STOP_1_8_RETENTION (PWR_CR2_SRAM3PDS1 | PWR_CR2_SRAM3PDS2 | PWR_CR2_SRAM3PDS3 | \ - PWR_CR2_SRAM3PDS4 | PWR_CR2_SRAM3PDS5 | PWR_CR2_SRAM3PDS6 | \ - PWR_CR2_SRAM3PDS7 | PWR_CR2_SRAM3PDS8) /*!< SRAM3 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ -#if defined (PWR_CR4_SRAM3PDS9) -#define LL_PWR_SRAM3_STOP_9_13_RETENTION (PWR_CR4_SRAM3PDS9 | PWR_CR4_SRAM3PDS10 | PWR_CR4_SRAM3PDS11 | \ - PWR_CR4_SRAM3PDS12 | PWR_CR4_SRAM3PDS13) /*!< SRAM3 pages (9 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */ -#endif /* defined (PWR_CR4_SRAM3PDS9) */ -/** - * @} - */ -#endif /* PWR_CR2_SRAM3PDS1 */ - -/** @defgroup PWR_LL_EC_SRAM4_STOP_CONTENTS_RETENTION PWR SRAM4 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_SRAM4_STOP_NO_RETENTION 0U /*!< SRAM4 no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_SRAM4_STOP_FULL_RETENTION PWR_CR2_SRAM4PDS /*!< SRAM4 retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -#if defined (PWR_CR4_SRAM5PDS1) -/** @defgroup PWR_LL_EC_SRAM5_STOP_CONTENTS_RETENTION PWR SRAM5 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_SRAM5_STOP_NO_RETENTION 0U /*!< SRAM5 no retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE1_RETENTION (PWR_CR4_SRAM5PDS1) /*!< SRAM5 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE2_RETENTION (PWR_CR4_SRAM5PDS2) /*!< SRAM5 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE3_RETENTION (PWR_CR4_SRAM5PDS3) /*!< SRAM5 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE4_RETENTION (PWR_CR4_SRAM5PDS4) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE5_RETENTION (PWR_CR4_SRAM5PDS5) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE6_RETENTION (PWR_CR4_SRAM5PDS6) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE7_RETENTION (PWR_CR4_SRAM5PDS7) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE8_RETENTION (PWR_CR4_SRAM5PDS8) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE9_RETENTION (PWR_CR4_SRAM5PDS9) /*!< SRAM5 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE10_RETENTION (PWR_CR4_SRAM5PDS10) /*!< SRAM5 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE11_RETENTION (PWR_CR4_SRAM5PDS11) /*!< SRAM5 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE12_RETENTION (PWR_CR4_SRAM5PDS12) /*!< SRAM5 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_PAGE13_RETENTION (PWR_CR4_SRAM5PDS13) /*!< SRAM5 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM5_STOP_FULL_RETENTION (PWR_CR4_SRAM5PDS1 | PWR_CR4_SRAM5PDS2 | PWR_CR4_SRAM5PDS3 | \ - PWR_CR4_SRAM5PDS4 | PWR_CR4_SRAM5PDS5 | PWR_CR4_SRAM5PDS6 | \ - PWR_CR4_SRAM5PDS7 | PWR_CR4_SRAM5PDS8 | PWR_CR4_SRAM5PDS9 | \ - PWR_CR4_SRAM5PDS10 | PWR_CR4_SRAM5PDS11 | PWR_CR4_SRAM5PDS12 | \ - PWR_CR4_SRAM5PDS13) /*!< SRAM5 pages (1 to 13) retention in Stop modes (Stop 0, 1, 2, 3) */ -/** - * @} - */ -#endif /* defined (PWR_CR4_SRAM5PDS1) */ - -#if defined (PWR_CR5_SRAM6PDS1) -/** @defgroup PWR_LL_EC_SRAM6_STOP_CONTENTS_RETENTION PWR SRAM6 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_SRAM6_STOP_NO_RETENTION 0U /*!< SRAM6 no retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE1_RETENTION (PWR_CR5_SRAM6PDS1) /*!< SRAM6 page 1 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE2_RETENTION (PWR_CR5_SRAM6PDS2) /*!< SRAM6 page 2 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE3_RETENTION (PWR_CR5_SRAM6PDS3) /*!< SRAM6 page 3 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE4_RETENTION (PWR_CR5_SRAM6PDS4) /*!< SRAM6 page 4 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE5_RETENTION (PWR_CR5_SRAM6PDS5) /*!< SRAM6 page 5 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE6_RETENTION (PWR_CR5_SRAM6PDS6) /*!< SRAM6 page 6 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE7_RETENTION (PWR_CR5_SRAM6PDS7) /*!< SRAM6 page 7 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_PAGE8_RETENTION (PWR_CR5_SRAM6PDS8) /*!< SRAM6 page 8 (64 KB) retention in Stop mode (Stop 0, 1, 2, 3) */ -#define LL_PWR_SRAM6_STOP_FULL_RETENTION (PWR_CR5_SRAM6PDS1 | PWR_CR5_SRAM6PDS2 | PWR_CR5_SRAM6PDS3 | \ - PWR_CR5_SRAM6PDS4 | PWR_CR5_SRAM6PDS5 | PWR_CR5_SRAM6PDS6 | \ - PWR_CR5_SRAM6PDS7 | \ - PWR_CR5_SRAM6PDS8) /*!< SRAM6 pages (1 to 8) retention in Stop modes (Stop 0, 1, 2, 3) */ -/** - * @} - */ -#endif /* defined (PWR_CR5_SRAM6PDS1) */ - -/** @defgroup PWR_LL_EC_ICACHERAM_STOP_CONTENTS_RETENTION PWR ICACHE Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_ICACHERAM_STOP_NO_RETENTION 0U /*!< ICACHE SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_ICACHERAM_STOP_FULL_RETENTION PWR_CR2_ICRAMPDS /*!< ICACHE SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_DCACHE1RAM_STOP_CONTENTS_RETENTION PWR DCACHE1 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_DCACHE1RAM_STOP_NO_RETENTION 0U /*!< DCACHE1 SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION PWR_CR2_DC1RAMPDS /*!< DCACHE1 SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -#if defined (PWR_CR2_DC2RAMPDS) -/** @defgroup PWR_LL_EC_DCACHE2RAM_STOP_CONTENTS_RETENTION PWR DCACHE2 Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_DCACHE2RAM_STOP_NO_RETENTION 0U /*!< DCACHE2 SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION PWR_CR2_DC2RAMPDS /*!< DCACHE2 SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ -#endif /* defined (PWR_CR2_DC2RAMPDS) */ - -#if defined (PWR_CR2_DMA2DRAMPDS) -/** @defgroup PWR_LL_EC_DMA2DRAM_STOP_CONTENTS_RETENTION PWR DMA2DRAM Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_DMA2DRAM_STOP_NO_RETENTION 0U /*!< DMA2D SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_DMA2DRAM_STOP_FULL_RETENTION PWR_CR2_DMA2DRAMPDS /*!< DMA2D SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ -#endif /* PWR_CR2_DMA2DRAMPDS */ - -/** @defgroup PWR_LL_EC_PERIPHRAM_STOP_CONTENTS_RETENTION PWR PERIPHRAM Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_PERIPHRAM_STOP_NO_RETENTION 0U /*!< FMAC, FDCAN and USB SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_PERIPHRAM_STOP_FULL_RETENTION PWR_CR2_PRAMPDS /*!< FMAC, FDCAN and USB SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_PKARAM_STOP_CONTENTS_RETENTION PWR PKARAM Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_PKARAM_STOP_NO_RETENTION 0U /*!< PKA32 SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_PKARAM_STOP_FULL_RETENTION PWR_CR2_PKARAMPDS /*!< PKA32 SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -#if defined (PWR_CR2_GPRAMPDS) -/** @defgroup PWR_LL_EC_GPRAM_STOP_CONTENTS_RETENTION PWR GPRAM Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION 0U /*!< Graphic peripherals (LTDC, GFXMMU) SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION PWR_CR2_GPRAMPDS /*!< Graphic peripherals (LTDC, GFXMMU) SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ -#endif /* defined (PWR_CR2_GPRAMPDS) */ - -#if defined (PWR_CR2_DSIRAMPDS) -/** @defgroup PWR_LL_EC_DSIRAM_STOP_CONTENTS_RETENTION PWR DSI RAM Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_DSIRAM_STOP_NO_RETENTION 0U /*!< DSI SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_DSIRAM_STOP_FULL_RETENTION PWR_CR2_DSIRAMPDS /*!< DSI SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ -#endif /* defined (PWR_CR2_JPEGRAMPDS) */ - -#if defined (PWR_CR2_JPEGRAMPDS) -/** @defgroup PWR_LL_EC_JPEGRAM_STOP_CONTENTS_RETENTION PWR JPEG RAM Content Retention in Stop Mode - * @{ - */ -#define LL_PWR_JPEGRAM_STOP_NO_RETENTION 0U /*!< JPEG SRAM no retention in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_JPEGRAM_STOP_FULL_RETENTION PWR_CR2_JPEGRAMPDS /*!< JPEG SRAM retention in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ -#endif /* defined (PWR_CR2_JPEGRAMPDS) */ - -/** @defgroup PWR_LL_EC_SRAM1_RUN_CONTENTS_RETENTION PWR SRAM1 Content Retention in Run Mode - * @{ - */ -#define LL_PWR_SRAM1_RUN_NO_RETENTION 0U /*!< SRAM1 no retention in Run mode */ -#define LL_PWR_SRAM1_RUN_FULL_RETENTION PWR_CR1_SRAM1PD /*!< SRAM1 retention in Run mode */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_SRAM2_RUN_CONTENTS_RETENTION PWR SRAM2 Content Retention in Run Mode - * @{ - */ -#define LL_PWR_SRAM2_RUN_NO_RETENTION 0U /*!< SRAM2 no retention in Run mode */ -#define LL_PWR_SRAM2_RUN_FULL_RETENTION PWR_CR1_SRAM2PD /*!< SRAM2 retention in Run mode */ -/** - * @} - */ - -#if defined (PWR_CR1_SRAM3PD) -/** @defgroup PWR_LL_EC_SRAM3_RUN_CONTENTS_RETENTION PWR SRAM3 Content Retention in Run Mode - * @{ - */ -#define LL_PWR_SRAM3_RUN_NO_RETENTION 0U /*!< SRAM3 no retention in Run mode */ -#define LL_PWR_SRAM3_RUN_FULL_RETENTION PWR_CR1_SRAM3PD /*!< SRAM3 retention in Run mode */ -/** - * @} - */ -#endif /* PWR_CR1_SRAM3PD */ - -/** @defgroup PWR_LL_EC_SRAM4_RUN_CONTENTS_RETENTION PWR SRAM4 Content Retention in Run Mode - * @{ - */ -#define LL_PWR_SRAM4_RUN_NO_RETENTION 0U /*!< SRAM4 no retention in Run mode */ -#define LL_PWR_SRAM4_RUN_FULL_RETENTION PWR_CR1_SRAM4PD /*!< SRAM4 retention in Run mode */ -/** - * @} - */ - -#if defined (PWR_CR1_SRAM5PD) -/** @defgroup PWR_LL_EC_SRAM5_RUN_CONTENTS_RETENTION PWR SRAM5 Content Retention in Run Mode - * @{ - */ -#define LL_PWR_SRAM5_RUN_NO_RETENTION 0U /*!< SRAM5 no retention in Run mode */ -#define LL_PWR_SRAM5_RUN_FULL_RETENTION PWR_CR1_SRAM5PD /*!< SRAM5 retention in Run mode */ -/** - * @} - */ -#endif /* defined (PWR_CR1_SRAM5PD) */ - -#if defined (PWR_CR1_SRAM6PD) -/** @defgroup PWR_LL_EC_SRAM6_RUN_CONTENTS_RETENTION PWR SRAM6 Content Retention in Run Mode - * @{ - */ -#define LL_PWR_SRAM6_RUN_NO_RETENTION 0U /*!< SRAM6 no retention in Run mode */ -#define LL_PWR_SRAM6_RUN_FULL_RETENTION PWR_CR1_SRAM6PD /*!< SRAM6 retention in Run mode */ -/** - * @} - */ -#endif /* defined (PWR_CR1_SRAM6PD) */ - -/** @defgroup PWR_LL_EC_SRD_MODE PWR Smart Run Domain Mode - * @{ - */ -#define LL_PWR_SRD_STOP_MODE 0U /*!< SmartRun domain AHB3 and APB3 clocks disabled by default in Stop mode (Stop 0, 1, 2) */ -#define LL_PWR_SRD_RUN_MODE PWR_CR2_SRDRUN /*!< SmartRun domain AHB3 and APB3 clocks kept enabled in Stop mode (Stop 0, 1, 2) */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_REGULATOR_SUPPLY_SELECTION PWR Regulator Supply Selection - * @{ - */ -#define LL_PWR_LDO_SUPPLY 0U /*!< LDO regulator supply */ -#define LL_PWR_SMPS_SUPPLY PWR_CR3_REGSEL /*!< SMPS regulator supply */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_VOLTAGE_SCALING_RANGE_SELECTION PWR Voltage scaling range selection - * @{ - */ -#define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_VOSR_VOS /*!< Voltage scaling range 1 */ -#define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_VOSR_VOS_1 /*!< Voltage scaling range 2 */ -#define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_VOSR_VOS_0 /*!< Voltage scaling range 3 */ -#define LL_PWR_REGU_VOLTAGE_SCALE4 0x00000000U /*!< Voltage scaling range 4 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_PVD_LEVEL_SELECTION PWR Power Voltage Detector Level Selection - * @{ - */ -#define LL_PWR_PVDLEVEL_0 0U /*!< Voltage threshold detected by PVD 2.0 V */ -#define LL_PWR_PVDLEVEL_1 PWR_SVMCR_PVDLS_0 /*!< Voltage threshold detected by PVD 2.2 V */ -#define LL_PWR_PVDLEVEL_2 PWR_SVMCR_PVDLS_1 /*!< Voltage threshold detected by PVD 2.4 V */ -#define LL_PWR_PVDLEVEL_3 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_1) /*!< Voltage threshold detected by PVD 2.5 V */ -#define LL_PWR_PVDLEVEL_4 PWR_SVMCR_PVDLS_2 /*!< Voltage threshold detected by PVD 2.6 V */ -#define LL_PWR_PVDLEVEL_5 (PWR_SVMCR_PVDLS_0 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.8 V */ -#define LL_PWR_PVDLEVEL_6 (PWR_SVMCR_PVDLS_1 | PWR_SVMCR_PVDLS_2) /*!< Voltage threshold detected by PVD 2.9 V */ -#define LL_PWR_PVDLEVEL_7 PWR_SVMCR_PVDLS /*!< External input analog voltage on PVD_IN - pin, compared to internal VREFINT level */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_WAKEUP_PIN PWR Wake Up Pin - * @{ - */ -#define LL_PWR_WAKEUP_PIN1 PWR_WUCR1_WUPEN1 /*!< Wakeup pin 1 enable */ -#define LL_PWR_WAKEUP_PIN2 PWR_WUCR1_WUPEN2 /*!< Wakeup pin 2 enable */ -#define LL_PWR_WAKEUP_PIN3 PWR_WUCR1_WUPEN3 /*!< Wakeup pin 3 enable */ -#define LL_PWR_WAKEUP_PIN4 PWR_WUCR1_WUPEN4 /*!< Wakeup pin 4 enable */ -#define LL_PWR_WAKEUP_PIN5 PWR_WUCR1_WUPEN5 /*!< Wakeup pin 5 enable */ -#define LL_PWR_WAKEUP_PIN6 PWR_WUCR1_WUPEN6 /*!< Wakeup pin 6 enable */ -#define LL_PWR_WAKEUP_PIN7 PWR_WUCR1_WUPEN7 /*!< Wakeup pin 7 enable */ -#define LL_PWR_WAKEUP_PIN8 PWR_WUCR1_WUPEN8 /*!< Wakeup pin 8 enable */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_WAKEUP_PIN_SELECTION PWR Wakeup Pin Selection - * @{ - */ -#define LL_PWR_WAKEUP_PIN_SELECTION_0 0UL /*!< Wakeup pin selection 0 */ -#define LL_PWR_WAKEUP_PIN_SELECTION_1 PWR_WUCR3_WUSEL1_0 /*!< Wakeup pin selection 1 */ -#define LL_PWR_WAKEUP_PIN_SELECTION_2 PWR_WUCR3_WUSEL1_1 /*!< Wakeup pin selection 2 */ -#define LL_PWR_WAKEUP_PIN_SELECTION_3 PWR_WUCR3_WUSEL1 /*!< Wakeup pin selection 3 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_CHARGING_RESISTOR_SELECTION PWR VBAT Charging Resistor Selection - * @{ - */ -#define LL_PWR_BATT_CHARG_RESISTOR_5K 0U /*!< Charge the battery through a 5 kO resistor */ -#define LL_PWR_BATT_CHARG_RESISTOR_1_5K PWR_BDCR2_VBRS /*!< Charge the battery through a 1.5 kO resistor */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GPIO_PORT_SELECTION PWR GPIO Port Selection - * @{ - */ -#define LL_PWR_GPIO_PORTA (&(PWR->PUCRA)) /*!< GPIO port A */ -#define LL_PWR_GPIO_PORTB (&(PWR->PUCRB)) /*!< GPIO port B */ -#define LL_PWR_GPIO_PORTC (&(PWR->PUCRC)) /*!< GPIO port C */ -#define LL_PWR_GPIO_PORTD (&(PWR->PUCRD)) /*!< GPIO port D */ -#define LL_PWR_GPIO_PORTE (&(PWR->PUCRE)) /*!< GPIO port E */ -#ifdef PWR_PUCRF_PU0 -#define LL_PWR_GPIO_PORTF (&(PWR->PUCRF)) /*!< GPIO port F */ -#endif /* PWR_PUCRF_PU0 */ -#define LL_PWR_GPIO_PORTG (&(PWR->PUCRG)) /*!< GPIO port G */ -#define LL_PWR_GPIO_PORTH (&(PWR->PUCRH)) /*!< GPIO port H */ -#ifdef PWR_PUCRI_PU0 -#define LL_PWR_GPIO_PORTI (&(PWR->PUCRI)) /*!< GPIO port I */ -#endif /* PWR_PUCRI_PU0 */ -#if defined (PWR_PUCRJ_PU0) -#define LL_PWR_GPIO_PORTJ (&(PWR->PUCRJ)) /*!< GPIO port J */ -#endif /* defined (PWR_PUCRJ_PU0) */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_GPIO_PIN_MASK PWR GPIO Pin Mask - * @{ - */ -#define LL_PWR_GPIO_PIN_0 (0x0001U) /*!< GPIO port I/O pin 0 */ -#define LL_PWR_GPIO_PIN_1 (0x0002U) /*!< GPIO port I/O pin 1 */ -#define LL_PWR_GPIO_PIN_2 (0x0004U) /*!< GPIO port I/O pin 2 */ -#define LL_PWR_GPIO_PIN_3 (0x0008U) /*!< GPIO port I/O pin 3 */ -#define LL_PWR_GPIO_PIN_4 (0x0010U) /*!< GPIO port I/O pin 4 */ -#define LL_PWR_GPIO_PIN_5 (0x0020U) /*!< GPIO port I/O pin 5 */ -#define LL_PWR_GPIO_PIN_6 (0x0040U) /*!< GPIO port I/O pin 6 */ -#define LL_PWR_GPIO_PIN_7 (0x0080U) /*!< GPIO port I/O pin 7 */ -#define LL_PWR_GPIO_PIN_8 (0x0100U) /*!< GPIO port I/O pin 8 */ -#define LL_PWR_GPIO_PIN_9 (0x0200U) /*!< GPIO port I/O pin 9 */ -#define LL_PWR_GPIO_PIN_10 (0x0400U) /*!< GPIO port I/O pin 10 */ -#define LL_PWR_GPIO_PIN_11 (0x0800U) /*!< GPIO port I/O pin 11 */ -#define LL_PWR_GPIO_PIN_12 (0x1000U) /*!< GPIO port I/O pin 12 */ -#define LL_PWR_GPIO_PIN_13 (0x2000U) /*!< GPIO port I/O pin 13 */ -#define LL_PWR_GPIO_PIN_14 (0x4000U) /*!< GPIO port I/O pin 14 */ -#define LL_PWR_GPIO_PIN_15 (0x8000U) /*!< GPIO port I/O pin 15 */ -/** - * @} - */ - -/** @defgroup PWR_LL_EC_ITEMS_SECURE_ATTRIBUTE PWR Items Secure Attribute - * @{ - */ -#define LL_PWR_WAKEUP_PIN1_NSEC 0U /*!< Wake up pin 1 nsecure mode */ -#define LL_PWR_WAKEUP_PIN1_SEC PWR_SECCFGR_WUP1SEC /*!< Wake up pin 1 secure mode */ -#define LL_PWR_WAKEUP_PIN2_NSEC 0U /*!< Wake up pin 2 nsecure mode */ -#define LL_PWR_WAKEUP_PIN2_SEC PWR_SECCFGR_WUP2SEC /*!< Wake up pin 2 secure mode */ -#define LL_PWR_WAKEUP_PIN3_NSEC 0U /*!< Wake up pin 3 nsecure mode */ -#define LL_PWR_WAKEUP_PIN3_SEC PWR_SECCFGR_WUP3SEC /*!< Wake up pin 3 secure mode */ -#define LL_PWR_WAKEUP_PIN4_NSEC 0U /*!< Wake up pin 4 nsecure mode */ -#define LL_PWR_WAKEUP_PIN4_SEC PWR_SECCFGR_WUP4SEC /*!< Wake up pin 4 secure mode */ -#define LL_PWR_WAKEUP_PIN5_NSEC 0U /*!< Wake up pin 5 nsecure mode */ -#define LL_PWR_WAKEUP_PIN5_SEC PWR_SECCFGR_WUP5SEC /*!< Wake up pin 5 secure mode */ -#define LL_PWR_WAKEUP_PIN6_NSEC 0U /*!< Wake up pin 6 nsecure mode */ -#define LL_PWR_WAKEUP_PIN6_SEC PWR_SECCFGR_WUP6SEC /*!< Wake up pin 6 secure mode */ -#define LL_PWR_WAKEUP_PIN7_NSEC 0U /*!< Wake up pin 7 nsecure mode */ -#define LL_PWR_WAKEUP_PIN7_SEC PWR_SECCFGR_WUP7SEC /*!< Wake up pin 7 secure mode */ -#define LL_PWR_WAKEUP_PIN8_NSEC 0U /*!< Wake up pin 8 nsecure mode */ -#define LL_PWR_WAKEUP_PIN8_SEC PWR_SECCFGR_WUP8SEC /*!< Wake up pin 8 secure mode */ - -#define LL_PWR_LPM_NSEC 0U /*!< Low-power modes nsecure mode */ -#define LL_PWR_LPM_SEC PWR_SECCFGR_LPMSEC /*!< Low-power modes secure mode */ -#define LL_PWR_VDM_NSEC 0U /*!< Voltage detection and monitoring nsecure mode */ -#define LL_PWR_VDM_SEC PWR_SECCFGR_VDMSEC /*!< Voltage detection and monitoring secure mode */ -#define LL_PWR_VB_NSEC 0U /*!< Backup domain nsecure mode */ -#define LL_PWR_VB_SEC PWR_SECCFGR_VBSEC /*!< Backup domain secure mode */ -#define LL_PWR_APC_NSEC 0U /*!< Pull-up/pull-down nsecure mode */ -#define LL_PWR_APC_SEC PWR_SECCFGR_APCSEC /*!< Pull-up/pull-down secure mode */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup PWR_LL_Exported_Macros PWR Exported Macros - * @{ - */ - -/** @defgroup PWR_LL_EM_WRITE_READ Common Write and Read Registers Macros - * @{ - */ - -/** - * @brief Write a value in PWR register. - * @param __REG__ Register to be written. - * @param __VALUE__ Value to be written in the register. - * @retval None. - */ -#define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) - -/** - * @brief Read a value in PWR register. - * @param __REG__ Register to be read. - * @retval Register value. - */ -#define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWR_LL_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_LL_EF_CONFIGURATION PWR Configuration - * @{ - */ - -/** - * @brief Set system power mode. - * @rmtoll CR1 LPMS LL_PWR_SetPowerMode - * @param Mode : This parameter can be one of the following values: - * @arg @ref LL_PWR_STOP0_MODE - * @arg @ref LL_PWR_STOP1_MODE - * @arg @ref LL_PWR_STOP2_MODE - * @arg @ref LL_PWR_STOP3_MODE - * @arg @ref LL_PWR_STANDBY_MODE - * @arg @ref LL_PWR_SHUTDOWN_MODE - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t Mode) -{ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, Mode); -} - -/** - * @brief Get system power mode. - * @rmtoll CR1 LPMS LL_PWR_GetPowerMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_STOP0_MODE - * @arg @ref LL_PWR_STOP1_MODE - * @arg @ref LL_PWR_STOP2_MODE - * @arg @ref LL_PWR_STOP3_MODE - * @arg @ref LL_PWR_STANDBY_MODE - * @arg @ref LL_PWR_SHUTDOWN_MODE - */ -__STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) -{ - return (READ_BIT(PWR->CR1, PWR_CR1_LPMS)); -} - -/** - * @brief Set the SRAM2 page(s) retention in Standby mode. - * @rmtoll CR1 RRSB1 LL_PWR_SetSRAM2SBRetention\n - * @rmtoll CR1 RRSB2 LL_PWR_SetSRAM2SBRetention - * @param SRAM2PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION - * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM2SBRetention(uint32_t SRAM2PageRetention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_SB_FULL_RETENTION, SRAM2PageRetention); -} - -/** - * @brief Get the SRAM2 page(s) retention in Standby mode. - * @rmtoll CR1 RRSB1 LL_PWR_GetSRAM2SBRetention\n - * @rmtoll CR1 RRSB2 LL_PWR_GetSRAM2SBRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM2_SB_NO_RETENTION - * @arg @ref LL_PWR_SRAM2_SB_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM2_SB_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM2_SB_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM2SBRetention(void) -{ - return (READ_BIT(PWR->CR1, (PWR_CR1_RRSB1 | PWR_CR1_RRSB2))); -} - -/** - * @brief Enable BOR ultra low power mode. - * @rmtoll CR1 UPLMEN LL_PWR_EnableUltraLowPowerMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUltraLowPowerMode(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); -} - -/** - * @brief Disable BOR ultra low-power mode. - * @rmtoll CR1 UPLMEN LL_PWR_DisableUltraLowPowerMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUltraLowPowerMode(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); -} - -/** - * @brief Check if BOR ultra low power mode is enabled. - * @rmtoll CR1 UPLMEN LL_PWR_IsEnabledUltraLowPowerMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUltraLowPowerMode(void) -{ - return ((READ_BIT(PWR->CR1, PWR_CR1_ULPMEN) == (PWR_CR1_ULPMEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the SRAM1 retention in Run mode. - * @rmtoll CR1 SRAM1PD LL_PWR_SetSRAM1RunRetention\n - * @param SRAM1Retention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM1RunRetention(uint32_t SRAM1Retention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION, ((~SRAM1Retention) & LL_PWR_SRAM1_RUN_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM1 retention in Run mode. - * @rmtoll CR1 SRAM1PD LL_PWR_GetSRAM1RunRetention\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM1_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM1_RUN_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM1RunRetention(void) -{ - return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM1_RUN_FULL_RETENTION))) & LL_PWR_SRAM1_RUN_FULL_RETENTION); -} - -/** - * @brief Set the SRAM2 retention in Run mode. - * @rmtoll CR1 SRAM2PD LL_PWR_SetSRAM2RunRetention\n - * @param SRAM2Retention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM2RunRetention(uint32_t SRAM2Retention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION, ((~SRAM2Retention) & LL_PWR_SRAM2_RUN_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM2 retention in Run mode. - * @rmtoll CR1 SRAM2PD LL_PWR_GetSRAM2RunRetention\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM2_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM2_RUN_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM2RunRetention(void) -{ - return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM2_RUN_FULL_RETENTION))) & LL_PWR_SRAM2_RUN_FULL_RETENTION); -} - -#if defined (PWR_CR1_SRAM3PD) -/** - * @brief Set the SRAM3 retention in Run mode. - * @rmtoll CR1 SRAM3PD LL_PWR_SetSRAM3RunRetention\n - * @param SRAM3Retention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM3RunRetention(uint32_t SRAM3Retention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION, ((~SRAM3Retention) & LL_PWR_SRAM3_RUN_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM3 retention in Run mode. - * @rmtoll CR1 SRAM3PD LL_PWR_GetSRAM3RunRetention\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM3_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM3_RUN_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM3RunRetention(void) -{ - return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM3_RUN_FULL_RETENTION))) & LL_PWR_SRAM3_RUN_FULL_RETENTION); -} -#endif /* PWR_CR1_SRAM3PD */ - -/** - * @brief Set the SRAM4 retention in Run mode. - * @rmtoll CR1 SRAM4PD LL_PWR_SetSRAM4RunRetention\n - * @param SRAM4Retention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM4RunRetention(uint32_t SRAM4Retention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION, ((~SRAM4Retention) & LL_PWR_SRAM4_RUN_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM4 retention in Run mode. - * @rmtoll CR1 SRAM4PD LL_PWR_GetSRAM4RunRetention\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM4_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM4_RUN_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM4RunRetention(void) -{ - return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM4_RUN_FULL_RETENTION))) & LL_PWR_SRAM4_RUN_FULL_RETENTION); -} - -#if defined (PWR_CR1_SRAM5PD) -/** - * @brief Set the SRAM5 retention in Run mode. - * @rmtoll CR1 SRAM5PD LL_PWR_SetSRAM5RunRetention\n - * @param SRAM5Retention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM5RunRetention(uint32_t SRAM5Retention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION, ((~SRAM5Retention) & LL_PWR_SRAM5_RUN_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM5 retention in Run mode. - * @rmtoll CR1 SRAM5PD LL_PWR_GetSRAM5RunRetention\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM5_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM5_RUN_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM5RunRetention(void) -{ - return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM5_RUN_FULL_RETENTION))) & LL_PWR_SRAM5_RUN_FULL_RETENTION); -} -#endif /* defined (PWR_CR1_SRAM5PD) */ - -#if defined (PWR_CR1_SRAM6PD) -/** - * @brief Set the SRAM6 retention in Run mode. - * @rmtoll CR1 SRAM6PD LL_PWR_SetSRAM6RunRetention\n - * @param SRAM6Retention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM6RunRetention(uint32_t SRAM6Retention) -{ - MODIFY_REG(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION, ((~SRAM6Retention) & LL_PWR_SRAM6_RUN_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM6 retention in Run mode. - * @rmtoll CR1 SRAM6PD LL_PWR_GetSRAM6RunRetention\n - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM6_RUN_NO_RETENTION - * @arg @ref LL_PWR_SRAM6_RUN_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM6RunRetention(void) -{ - return ((~(READ_BIT(PWR->CR1, LL_PWR_SRAM6_RUN_FULL_RETENTION))) & LL_PWR_SRAM6_RUN_FULL_RETENTION); -} -#endif /* defined (PWR_CR1_SRAM6PD) */ - -#if defined (PWR_CR1_FORCE_USBPWR) -/** - * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby). - * @rmtoll CR1 FORCE_USBPWR LL_PWR_EnableOTGHSPHYLowPowerRetention - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableOTGHSPHYLowPowerRetention(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); -} - -/** - * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby). - * @rmtoll CR1 FORCE_USBPWR LL_PWR_DisableOTGHSPHYLowPowerRetention - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableOTGHSPHYLowPowerRetention(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); -} - -/** - * @brief Check if OTG_HS PHY power during low power modes (Stop2, Stop 3 and Standby) is enabled. - * @rmtoll CR1 FORCE_USBPWR LL_PWR_IsEnabledOTGHSPHYLowPowerRetention - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledOTGHSPHYLowPowerRetention(void) -{ - return ((READ_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR) == (PWR_CR1_FORCE_USBPWR)) ? 1UL : 0UL); -} -#endif /* defined (PWR_CR1_FORCE_USBPWR) */ - -/** - * @brief Set the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode. - * @rmtoll CR2 SRAM1PDS1 LL_PWR_SetSRAM1StopRetention_1_3\n - * @rmtoll CR2 SRAM1PDS2 LL_PWR_SetSRAM1StopRetention_1_3\n - * @rmtoll CR2 SRAM1PDS3 LL_PWR_SetSRAM1StopRetention_1_3 - * @param SRAM1PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_1_3(uint32_t SRAM1PageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_1_3_RETENTION)); -} - -#if defined (PWR_CR4_SRAM1PDS4) -/** - * @brief Set the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode. - * @rmtoll CR2 SRAM1PDS4 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS5 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS6 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS7 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS8 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS9 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS10 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS11 LL_PWR_SetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS12 LL_PWR_SetSRAM1StopRetention_4_12 - * @param SRAM1PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM1StopRetention_4_12(uint32_t SRAM1PageRetention) -{ - MODIFY_REG(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION, ((~SRAM1PageRetention) & LL_PWR_SRAM1_STOP_4_12_RETENTION)); -} -#endif /* defined (PWR_CR4_SRAM1PDS4) */ - -/** - * @brief Get the SRAM1 page(s) (From page 1 to page 3) retention in Stop mode. - * @rmtoll CR2 SRAM1PDS1 LL_PWR_GetSRAM1StopRetention_1_3\n - * @rmtoll CR2 SRAM1PDS2 LL_PWR_GetSRAM1StopRetention_1_3\n - * @rmtoll CR2 SRAM1PDS3 LL_PWR_GetSRAM1StopRetention_1_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_1_3_RETENTION - * Or a combination of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE3_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_1_3(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM1_STOP_1_3_RETENTION))) & LL_PWR_SRAM1_STOP_1_3_RETENTION); -} - -#if defined (PWR_CR4_SRAM1PDS4) -/** - * @brief Get the SRAM1 page(s) (From page 4 to page 12) retention in Stop mode. - * @rmtoll CR2 SRAM1PDS4 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS5 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS6 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS7 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS8 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS9 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS10 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS11 LL_PWR_GetSRAM1StopRetention_4_12\n - * @rmtoll CR2 SRAM1PDS12 LL_PWR_GetSRAM1StopRetention_4_12 - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_4_12_RETENTION - * Or a combination of the following values: - * @arg @ref LL_PWR_SRAM1_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE8_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE9_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE10_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE11_RETENTION - * @arg @ref LL_PWR_SRAM1_STOP_PAGE12_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM1StopRetention_4_12(void) -{ - return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM1_STOP_4_12_RETENTION))) & LL_PWR_SRAM1_STOP_4_12_RETENTION); -} -#endif /* defined (PWR_CR4_SRAM1PDS4) */ - -/** - * @brief Set the SRAM2 page(s) retention in Stop mode. - * @rmtoll CR2 SRAM2PDS1 LL_PWR_SetSRAM2StopRetention\n - * @rmtoll CR2 SRAM2PDS2 LL_PWR_SetSRAM2StopRetention - * @param SRAM2PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM2StopRetention(uint32_t SRAM2PageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION, ((~SRAM2PageRetention) & LL_PWR_SRAM2_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM2 page(s) retention in Stop mode. - * @rmtoll CR2 SRAM2PDS1 LL_PWR_GetSRAM2StopRetention\n - * @rmtoll CR2 SRAM2PDS2 LL_PWR_GetSRAM2StopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM2_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM2_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM2_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM2_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM2StopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM2_STOP_FULL_RETENTION))) & LL_PWR_SRAM2_STOP_FULL_RETENTION); -} - -#if defined (PWR_CR2_SRAM3PDS1) -/** - * @brief Set the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode. - * @rmtoll CR2 SRAM3PDS1 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS2 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS3 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS4 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS5 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS6 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS7 LL_PWR_SetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS8 LL_PWR_SetSRAM3StopRetention_1_8 - * @param SRAM3PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_1_8(uint32_t SRAM3PageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_1_8_RETENTION)); -} - -#if defined (PWR_CR4_SRAM3PDS9) -/** - * @brief Set the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode. - * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13 - * @param SRAM3PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM3StopRetention_9_13(uint32_t SRAM3PageRetention) -{ - MODIFY_REG(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION, ((~SRAM3PageRetention) & LL_PWR_SRAM3_STOP_9_13_RETENTION)); -} -#endif /* defined (PWR_CR4_SRAM3PDS9) */ - -/** - * @brief Get the SRAM3 page(s) (From page 1 to page 8) retention in Stop mode. - * @rmtoll CR2 SRAM3PDS1 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS2 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS3 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS4 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS5 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS6 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS7 LL_PWR_GetSRAM3StopRetention_1_8\n - * @rmtoll CR2 SRAM3PDS8 LL_PWR_GetSRAM3StopRetention_1_8 - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_1_8_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE3_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE8_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_1_8(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM3_STOP_1_8_RETENTION))) & LL_PWR_SRAM3_STOP_1_8_RETENTION); -} - -#if defined (PWR_CR4_SRAM3PDS9) -/** - * @brief Get the SRAM3 page(s) (From page 9 to page 13) retention in Stop mode. - * @rmtoll CR2 SRAM3PDS9 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS10 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS11 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS12 LL_PWR_SetSRAM3StopRetention_9_13\n - * @rmtoll CR2 SRAM3PDS13 LL_PWR_SetSRAM3StopRetention_9_13 - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_9_13_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM3_STOP_PAGE9_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE10_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE11_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE12_RETENTION - * @arg @ref LL_PWR_SRAM3_STOP_PAGE13_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM3StopRetention_9_13(void) -{ - return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM3_STOP_9_13_RETENTION))) & LL_PWR_SRAM3_STOP_9_13_RETENTION); -} -#endif /* defined (PWR_CR4_SRAM3PDS9) */ -#endif /* PWR_CR2_SRAM3PDS1 */ - -/** - * @brief Set the SRAM4 page retention in Stop mode. - * @rmtoll CR2 SRAM4PDS LL_PWR_SetSRAM4StopRetention\n - * @param SRAM4PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM4StopRetention(uint32_t SRAM4PageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION, ((~SRAM4PageRetention) & LL_PWR_SRAM4_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM4 page retention in Stop mode. - * @rmtoll CR2 SRAM4PDS LL_PWR_GetSRAM4StopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM4_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM4_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM4StopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_SRAM4_STOP_FULL_RETENTION))) & LL_PWR_SRAM4_STOP_FULL_RETENTION); -} - -#if defined (PWR_CR4_SRAM5PDS1) -/** - * @brief Set the SRAM5 page(s) retention in Stop mode. - * @rmtoll CR4 SRAM5PDS1 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS2 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS3 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS4 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS5 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS6 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS7 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS8 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS9 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS10 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS11 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS12 LL_PWR_SetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS13 LL_PWR_SetSRAM5StopRetention - * @param SRAM5PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM5StopRetention(uint32_t SRAM5PageRetention) -{ - MODIFY_REG(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION, ((~SRAM5PageRetention) & LL_PWR_SRAM5_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM5 page(s) retention in Stop mode. - * @rmtoll CR4 SRAM5PDS1 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS2 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS3 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS4 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS5 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS6 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS7 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS8 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS9 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS10 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS11 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS12 LL_PWR_GetSRAM5StopRetention\n - * @rmtoll CR4 SRAM5PDS13 LL_PWR_GetSRAM5StopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM5_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_FULL_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM5_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE3_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE8_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE9_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE10_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE11_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE12_RETENTION - * @arg @ref LL_PWR_SRAM5_STOP_PAGE13_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM5StopRetention(void) -{ - return ((~(READ_BIT(PWR->CR4, LL_PWR_SRAM5_STOP_FULL_RETENTION))) & LL_PWR_SRAM5_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR4_SRAM5PDS1) */ - -#if defined (PWR_CR5_SRAM6PDS1) -/** - * @brief Set the SRAM6 page(s) retention in Stop mode. - * @rmtoll CR5 SRAM6PDS1 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS2 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS3 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS4 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS5 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS6 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS7 LL_PWR_SetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS8 LL_PWR_SetSRAM6StopRetention - * @param SRAM6PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSRAM6StopRetention(uint32_t SRAM6PageRetention) -{ - MODIFY_REG(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION, ((~SRAM6PageRetention) & LL_PWR_SRAM6_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the SRAM6 page(s) retention in Stop mode. - * @rmtoll CR5 SRAM6PDS1 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS2 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS3 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS4 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS5 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS6 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS7 LL_PWR_GetSRAM6StopRetention\n - * @rmtoll CR5 SRAM6PDS8 LL_PWR_GetSRAM6StopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRAM6_STOP_NO_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_FULL_RETENTION - * Or can be a combination of the following values: - * @arg @ref LL_PWR_SRAM6_STOP_PAGE1_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE2_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE3_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE4_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE5_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE6_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE7_RETENTION - * @arg @ref LL_PWR_SRAM6_STOP_PAGE8_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetSRAM6StopRetention(void) -{ - return ((~(READ_BIT(PWR->CR5, LL_PWR_SRAM6_STOP_FULL_RETENTION))) & LL_PWR_SRAM6_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR5_SRAM6PDS1) */ - -/** - * @brief Set the ICACHE SRAM page retention in Stop mode. - * @rmtoll CR2 ICRAMPDS LL_PWR_SetICacheRAMStopRetention\n - * @param ICachePageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetICacheRAMStopRetention(uint32_t ICachePageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION, - ((~ICachePageRetention) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the ICACHE SRAM page retention in Stop mode. - * @rmtoll CR2 ICRAMPDS LL_PWR_GetICacheRAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_ICACHERAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_ICACHERAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetICacheRAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_ICACHERAM_STOP_FULL_RETENTION))) & LL_PWR_ICACHERAM_STOP_FULL_RETENTION); -} - -/** - * @brief Set the DCACHE1 SRAM page retention in Stop mode. - * @rmtoll CR2 DC1RAMPDS LL_PWR_SetDCache1RAMStopRetention\n - * @param DCache1PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetDCache1RAMStopRetention(uint32_t DCache1PageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION, - ((~DCache1PageRetention) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the DCACHE1 SRAM page retention in Stop mode. - * @rmtoll CR2 DC1RAMPDS LL_PWR_GetDCache1RAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_DCACHE1RAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetDCache1RAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE1RAM_STOP_FULL_RETENTION); -} - -#if defined (PWR_CR2_DC2RAMPDS) -/** - * @brief Set the DCACHE2 SRAM page retention in Stop mode. - * @rmtoll CR2 DC2RAMPDS LL_PWR_SetDCache2RAMStopRetention\n - * @param DCache2PageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetDCache2RAMStopRetention(uint32_t DCache2PageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION, - ((~DCache2PageRetention) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the DCACHE2 SRAM page retention in Stop mode. - * @rmtoll CR2 DC2RAMPDS LL_PWR_GetDCache2RAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_DCACHE2RAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetDCache2RAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION))) & LL_PWR_DCACHE2RAM_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR2_DC2RAMPDS) */ - -#if defined (PWR_CR2_DMA2DRAMPDS) -/** - * @brief Set the DMA2D SRAM page retention in Stop mode. - * @rmtoll CR2 DMA2DRAMPDS LL_PWR_SetDMA2DRAMStopRetention\n - * @param DMA2DRAMPageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetDMA2DRAMStopRetention(uint32_t DMA2DRAMPageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION, - ((~DMA2DRAMPageRetention) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the DMA2D SRAM page retention in Stop mode. - * @rmtoll CR2 DMA2DRAMPDS LL_PWR_GetDMA2DRAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_DMA2DRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DMA2DRAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetDMA2DRAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_DMA2DRAM_STOP_FULL_RETENTION))) & LL_PWR_DMA2DRAM_STOP_FULL_RETENTION); -} -#endif /* PWR_CR2_DMA2DRAMPDS */ - -/** - * @brief Set the FMAC, FDCAN and USB SRAMs pages retention in Stop mode. - * @rmtoll CR2 PRAMPDS LL_PWR_SetPeriphRAMStopRetention\n - * @param PriphRAMPageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPeriphRAMStopRetention(uint32_t PriphRAMPageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION, - ((~PriphRAMPageRetention) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the FMAC, FDCAN and USB SRAMs pages retention in Stop mode. - * @rmtoll CR2 PRAMPDS LL_PWR_GetPeriphRAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PERIPHRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_PERIPHRAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetPeriphRAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_PERIPHRAM_STOP_FULL_RETENTION))) & LL_PWR_PERIPHRAM_STOP_FULL_RETENTION); -} - -#if defined (PWR_CR2_PKARAMPDS) -/** - * @brief Set the PKA32 SRAM page retention in Stop mode. - * @rmtoll CR2 PKARAMPDS LL_PWR_SetPKARAMStopRetention - * @param PKARAMPageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPKARAMStopRetention(uint32_t PKARAMPageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION, ((~PKARAMPageRetention) & LL_PWR_PKARAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the PKA32 SRAM page retention in Stop mode. - * @rmtoll CR2 PKARAMPDS LL_PWR_GetPKARAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PKARAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_PKARAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetPKARAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_PKARAM_STOP_FULL_RETENTION))) & LL_PWR_PKARAM_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR2_PKARAMPDS) */ - -#if defined (PWR_CR2_GPRAMPDS) -/** - * @brief Set the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode. - * @rmtoll CR2 GPRAMPDS LL_PWR_SetGraphicPeriphRAMStopRetention - * @param GraphicPeriphRAMPageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetGraphicPeriphRAMStopRetention(uint32_t GraphicPeriphRAMPageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION, - ((~GraphicPeriphRAMPageRetention) & LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the Graphic peripherals (LTDC, GFXMMU) SRAM page retention in Stop mode. - * @rmtoll CR2 GPRAMPDS LL_PWR_GetGraphicPeriphRAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetGraphicPeriphRAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION))) & - LL_PWR_GRAPHICPERIPHRAM_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR2_GPRAMPDS) */ - -#if defined (PWR_CR2_DSIRAMPDS) -/** - * @brief Set the DSI SRAM page retention in Stop mode. - * @rmtoll CR2 DSIRAMPDS LL_PWR_SetDSIRAMStopRetention - * @param DSIRAMPageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetDSIRAMStopRetention(uint32_t DSIRAMPageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION, ((~DSIRAMPageRetention) & LL_PWR_DSIRAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the DSI SRAM page retention in Stop mode. - * @rmtoll CR2 DSIRAMPDS LL_PWR_GetDSIRAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_DSIRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_DSIRAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetDSIRAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_DSIRAM_STOP_FULL_RETENTION))) & LL_PWR_DSIRAM_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR2_DSIRAMPDS) */ - -#if defined (PWR_CR2_JPEGRAMPDS) -/** - * @brief Set the JPEG SRAM page retention in Stop mode. - * @rmtoll CR2 JPEGRAMPDS LL_PWR_SetJPEGRAMStopRetention - * @param JPEGRAMPageRetention : This parameter can be one of the following values: - * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetJPEGRAMStopRetention(uint32_t JPEGRAMPageRetention) -{ - MODIFY_REG(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION, - ((~JPEGRAMPageRetention) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION)); -} - -/** - * @brief Get the JPEG SRAM page retention in Stop mode. - * @rmtoll CR2 JPEGRAMPDS LL_PWR_GetJPEGRAMStopRetention - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_JPEGRAM_STOP_NO_RETENTION - * @arg @ref LL_PWR_JPEGRAM_STOP_FULL_RETENTION - */ -__STATIC_INLINE uint32_t LL_PWR_GetJPEGRAMStopRetention(void) -{ - return ((~(READ_BIT(PWR->CR2, LL_PWR_JPEGRAM_STOP_FULL_RETENTION))) & LL_PWR_JPEGRAM_STOP_FULL_RETENTION); -} -#endif /* defined (PWR_CR2_JPEGRAMPDS) */ - -/** - * @brief Enable the flash memory fast wakeup from Stop mode (Stop 0, 1). - * @rmtoll CR2 FLASHFWU LL_PWR_EnableFlashFastWakeUp - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableFlashFastWakeUp(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); -} - -/** - * @brief Disable the flash memory fast wakeup from Stop mode (Stop 0, 1). - * @rmtoll CR2 FLASHFWU LL_PWR_DisableFlashFastWakeUp - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableFlashFastWakeUp(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); -} - -/** - * @brief Check if the flash memory fast wakeup from Stop mode (Stop 0, 1) - * is enabled. - * @rmtoll CR2 FLASHFWU LL_PWR_IsEnabledFlashFastWakeUp - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashFastWakeUp(void) -{ - return ((READ_BIT(PWR->CR2, PWR_CR2_FLASHFWU) == (PWR_CR2_FLASHFWU)) ? 1UL : 0UL); -} - -/** - * @brief Enable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2). - * @rmtoll CR2 SRAM4FWU LL_PWR_EnableSRAM4FastWakeUp - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableSRAM4FastWakeUp(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); -} - -/** - * @brief Disable the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2). - * @rmtoll CR2 SRAM4FWU LL_PWR_DisableSRAM4FastWakeUp - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableSRAM4FastWakeUp(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); -} - -/** - * @brief Check if the SRAM4 memory fast wakeup from Stop mode (Stop 0, 1, 2). - * is enabled. - * @rmtoll CR2 SRAM4FWU LL_PWR_IsEnabledSRAM4FastWakeUp - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM4FastWakeUp(void) -{ - return ((READ_BIT(PWR->CR2, PWR_CR2_SRAM4FWU) == (PWR_CR2_SRAM4FWU)) ? 1UL : 0UL); -} - -/** - * @brief Set the smart run domain mode. - * @rmtoll CR2 SRDRUN LL_PWR_SetSmartRunDomainMode - * @param SRDMode : This parameter can be one of the following values: - * @arg @ref LL_PWR_SRD_RUN_MODE - * @arg @ref LL_PWR_SRD_STOP_MODE - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetSmartRunDomainMode(uint32_t SRDMode) -{ - MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDMode); -} - -/** - * @brief Get the smart run domain mode. - * @rmtoll CR2 SRDRUN LL_PWR_GetSmartRunDomainMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_SRD_RUN_MODE - * @arg @ref LL_PWR_SRD_STOP_MODE - */ -__STATIC_INLINE uint32_t LL_PWR_GetSmartRunDomainMode(void) -{ - return (READ_BIT(PWR->CR2, PWR_CR2_SRDRUN)); -} - -/** - * @brief Set the VCore regulator supply. - * @rmtoll CR3 REGSEL LL_PWR_SetRegulatorSupply - * @param RegulatorSupply : This parameter can be one of the following values: - * @arg @ref LL_PWR_LDO_SUPPLY - * @arg @ref LL_PWR_SMPS_SUPPLY - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulatorSupply(uint32_t RegulatorSupply) -{ - MODIFY_REG(PWR->CR3, PWR_CR3_REGSEL, RegulatorSupply); -} - -/** - * @brief Get the VCore regulator supply. - * @rmtoll CR3 REGSEL LL_PWR_GetRegulatorSupply - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_LDO_SUPPLY - * @arg @ref LL_PWR_SMPS_SUPPLY - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulatorSupply(void) -{ - return (READ_BIT(PWR->CR3, PWR_CR3_REGSEL)); -} - -/** - * @brief Enable the fast soft start for selected regulator. - * @rmtoll CR3 FSTEN LL_PWR_EnableFastSoftStart - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableFastSoftStart(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_FSTEN); -} - -/** - * @brief Disable the fast soft start for selected regulator. - * @rmtoll CR3 FSTEN LL_PWR_DisableFastSoftStart - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableFastSoftStart(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); -} - -/** - * @brief Check if the fast soft start for selected regulator is enabled. - * @rmtoll CR3 FSTEN LL_PWR_IsEnabledFastSoftStart - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledFastSoftStart(void) -{ - return ((READ_BIT(PWR->CR3, PWR_CR3_FSTEN) == (PWR_CR3_FSTEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the regulator supply output voltage. - * @rmtoll VOSR VOS LL_PWR_SetRegulVoltageScaling - * @param VoltageScaling This parameter can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) -{ - MODIFY_REG(PWR->VOSR, PWR_VOSR_VOS, VoltageScaling); -} - -/** - * @brief Get the regulator supply output voltage. - * @rmtoll VOSR VOS LL_PWR_GetRegulVoltageScaling - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4 - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) -{ - return (uint32_t)(READ_BIT(PWR->VOSR, PWR_VOSR_VOS)); -} - -/** - * @brief Enable the EPOD (Embedded Power Distribution) booster. - * @rmtoll VOSR BOOSTEN LL_PWR_EnableEPODBooster - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableEPODBooster(void) -{ - SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); -} - -/** - * @brief Disable the EPOD (Embedded Power Distribution) booster. - * @rmtoll VOSR BOOSTEN LL_PWR_DisableEPODBooster - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableEPODBooster(void) -{ - CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); -} - -/** - * @brief Check if the EPOD (Embedded Power Distribution) booster is enabled. - * @rmtoll VOSR BOOSTEN LL_PWR_IsEnabledEPODBooster - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledEPODBooster(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == (PWR_VOSR_BOOSTEN)) ? 1UL : 0UL); -} - -#if defined (PWR_VOSR_USBPWREN) -/** - * @brief Enable the USB power supply. - * @rmtoll VOSR USBPWREN LL_PWR_EnableUSBPowerSupply - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUSBPowerSupply(void) -{ - SET_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); -} - -/** - * @brief Disable the USB power supply. - * @rmtoll VOSR USBPWREN LL_PWR_DisableUSBPowerSupply - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUSBPowerSupply(void) -{ - CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBPWREN); -} - -/** - * @brief Check if the USB power supply is enabled. - * @rmtoll VOSR USBPWREN LL_PWR_IsEnabledUSBPowerSupply - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBPowerSupply(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBPWREN) == (PWR_VOSR_USBPWREN)) ? 1UL : 0UL); -} -#endif /* defined (PWR_VOSR_USBPWREN) */ - -#if defined (PWR_VOSR_USBBOOSTEN) -/** - * @brief Enable the USB EPOD (Embedded Power Distribution) booster. - * @rmtoll VOSR USBBOOSTEN LL_PWR_EnableUSBEPODBooster - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUSBEPODBooster(void) -{ - SET_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); -} - -/** - * @brief Disable the USB EPOD (Embedded Power Distribution) booster. - * @rmtoll VOSR USBBOOSTEN LL_PWR_DisableUSBEPODBooster - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUSBEPODBooster(void) -{ - CLEAR_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN); -} - -/** - * @brief Check if the USB EPOD (Embedded Power Distribution) booster is enabled. - * @rmtoll VOSR USBBOOSTEN LL_PWR_IsEnabledUSBEPODBooster - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBEPODBooster(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTEN) == (PWR_VOSR_USBBOOSTEN)) ? 1UL : 0UL); -} -#endif /* defined (PWR_VOSR_USBBOOSTEN) */ - -#if defined (PWR_VOSR_VDD11USBDIS) -/** - * @brief Enable the VDD11USB. - * @rmtoll VOSR VDD11USBDIS LL_PWR_EnableVDD11USB - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVDD11USB(void) -{ - CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); -} - -/** - * @brief Disable the VDD11USB. - * @rmtoll VOSR VDD11USBDIS LL_PWR_DisableVDD11USB - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVDD11USB(void) -{ - SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); -} - -/** - * @brief Check if the VDD11USB is enabled. - * @rmtoll VOSR VDD11USBDIS LL_PWR_IsEnabledVDD11USB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVDD11USB(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS) == (0U)) ? 1UL : 0UL); -} -#endif /* defined (PWR_VOSR_VDD11USBDIS) */ - -/** - * @brief Set the Power voltage detector level. - * @rmtoll SVMCR PVDLS LL_PWR_SetPVDLevel - * @param PVDLevel This parameter can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) -{ - MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, PVDLevel); -} - -/** - * @brief Get the Power voltage detector level. - * @rmtoll SVMCR PVDLS LL_PWR_GetPVDLevel - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_PVDLEVEL_0 - * @arg @ref LL_PWR_PVDLEVEL_1 - * @arg @ref LL_PWR_PVDLEVEL_2 - * @arg @ref LL_PWR_PVDLEVEL_3 - * @arg @ref LL_PWR_PVDLEVEL_4 - * @arg @ref LL_PWR_PVDLEVEL_5 - * @arg @ref LL_PWR_PVDLEVEL_6 - * @arg @ref LL_PWR_PVDLEVEL_7 - */ -__STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) -{ - return (READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDLS)); -} - -/** - * @brief Enable the power voltage detector. - * @rmtoll SVMCR PVDE LL_PWR_EnablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); -} - -/** - * @brief Disable the power voltage detector. - * @rmtoll SVMCR PVDE LL_PWR_DisablePVD - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); -} - -/** - * @brief Check if the power voltage detector is enabled. - * @rmtoll SVMCR PVDE LL_PWR_IsEnabledPVD - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_PVDE) == (PWR_SVMCR_PVDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable the independent USB supply. - * @rmtoll SVMCR USV LL_PWR_EnableVddUSB - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddUSB(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); -} -#define LL_PWR_EnableVDDUSB LL_PWR_EnableVddUSB /* for legacy purpose */ - -/** - * @brief Disable the independent USB supply. - * @rmtoll SVMCR USV LL_PWR_DisableVDDUSB - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddUSB(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); -} -#define LL_PWR_DisableVDDUSB LL_PWR_DisableVddUSB /* for legacy purpose */ - -/** - * @brief Check if the independent USB supply is enabled. - * @rmtoll SVMCR USV LL_PWR_IsEnabledVddUSB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_USV) == (PWR_SVMCR_USV)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDUSB LL_PWR_IsEnabledVddUSB /* for legacy purpose */ - -/** - * @brief Enable the independent I/Os supply. - * @rmtoll SVMCR IO2SV LL_PWR_EnableVddIO2 - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddIO2(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); -} -#define LL_PWR_EnableVDDIO2 LL_PWR_EnableVddIO2 /* for legacy purpose */ - -/** - * @brief Disable the independent I/Os supply. - * @rmtoll SVMCR IO2SV LL_PWR_DisableVddIO2 - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddIO2(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); -} -#define LL_PWR_DisableVDDIO2 LL_PWR_DisableVddIO2 /* for legacy purpose */ - -/** - * @brief Check if the independent I/Os supply is enabled. - * @rmtoll SVMCR IO2SV LL_PWR_IsEnabledVddIO2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV) == (PWR_SVMCR_IO2SV)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDIO2 LL_PWR_IsEnabledVddIO2 /* for legacy purpose */ - -/** - * @brief Enable the independent analog supply. - * @rmtoll SVMCR ASV LL_PWR_EnableVddA - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddA(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV); -} -#define LL_PWR_EnableVDDA LL_PWR_EnableVddA /* for legacy purpose */ - -/** - * @brief Disable the independent analog supply. - * @rmtoll SVMCR ASV LL_PWR_DisableVddA - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddA(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV); -} -#define LL_PWR_DisableVDDA LL_PWR_DisableVddA /* for legacy purpose */ - -/** - * @brief Check if the independent analog supply is enabled. - * @rmtoll SVMCR ASV LL_PWR_IsEnabledVddA - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddA(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_ASV) == (PWR_SVMCR_ASV)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDA LL_PWR_IsEnabledVddA /* for legacy purpose */ - -/** - * @brief Enable the independent USB supply monitor. - * @rmtoll SVMCR UVMEN LL_PWR_EnableVddUSBMonitor - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddUSBMonitor(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); -} -#define LL_PWR_EnableVDDUSBMonitor LL_PWR_EnableVddUSBMonitor /* for legacy purpose */ - -/** - * @brief Disable the independent USB supply monitor. - * @rmtoll SVMCR UVMEN LL_PWR_DisableVddUSBMonitor - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddUSBMonitor(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); -} -#define LL_PWR_DisableVDDUSBMonitor LL_PWR_DisableVddUSBMonitor /* for legacy purpose */ - -/** - * @brief Check if the independent USB supply monitor is enabled. - * @rmtoll SVMCR UVMEN LL_PWR_IsEnabledVddUSBMonitor - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSBMonitor(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN) == (PWR_SVMCR_UVMEN)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDUSBMonitor LL_PWR_IsEnabledVddUSBMonitor /* for legacy purpose */ - -/** - * @brief Enable the independent I/Os supply monitor. - * @rmtoll SVMCR IO2VMEN LL_PWR_EnableVddIO2Monitor - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddIO2Monitor(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); -} -#define LL_PWR_EnableVDDIO2Monitor LL_PWR_EnableVddIO2Monitor /* for legacy purpose */ - -/** - * @brief Disable the independent I/Os supply monitor. - * @rmtoll SVMCR IO2VMEN LL_PWR_DisableVddIO2Monitor - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddIO2Monitor(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); -} -#define LL_PWR_DisableVDDIO2Monitor LL_PWR_DisableVddIO2Monitor /* for legacy purpose */ - -/** - * @brief Check if the independent I/Os supply monitor is enabled. - * @rmtoll SVMCR IO2VMEN LL_PWR_IsEnabledVddIO2Monitor - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2Monitor(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN) == (PWR_SVMCR_IO2VMEN)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDIO2Monitor LL_PWR_IsEnabledVddIO2Monitor /* for legacy purpose */ - -/** - * @brief Enable the independent analog supply monitor 1. - * @rmtoll SVMCR AVM1EN LL_PWR_EnableVddAMonitor1 - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddAMonitor1(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); -} -#define LL_PWR_EnableVDDAMonitor1 LL_PWR_EnableVddAMonitor1 /* for legacy purpose */ - -/** - * @brief Disable the independent analog supply monitor 1. - * @rmtoll SVMCR AVM1EN LL_PWR_DisableVddAMonitor1 - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddAMonitor1(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); -} -#define LL_PWR_DisableVDDAMonitor1 LL_PWR_DisableVddAMonitor1 /* for legacy purpose */ - -/** - * @brief Check if the independent analog supply monitor 1 is enabled. - * @rmtoll SVMCR AVM1EN LL_PWR_IsEnabledVddAMonitor1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor1(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN) == (PWR_SVMCR_AVM1EN)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDAMonitor1 LL_PWR_IsEnabledVddAMonitor1 /* for legacy purpose */ - -/** - * @brief Enable the independent analog supply monitor 2. - * @rmtoll SVMCR AVM2EN LL_PWR_EnableVddAMonitor2 - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableVddAMonitor2(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); -} -#define LL_PWR_EnableVDDAMonitor2 LL_PWR_EnableVddAMonitor2 /* for legacy purpose */ - -/** - * @brief Disable the independent analog supply monitor 2. - * @rmtoll SVMCR AVM2EN LL_PWR_DisableVddAMonitor2 - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableVddAMonitor2(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); -} -#define LL_PWR_DisableVDDAMonitor2 LL_PWR_DisableVddAMonitor2 /* for legacy purpose */ - -/** - * @brief Check if the independent analog supply monitor 2 is enabled. - * @rmtoll SVMCR AVM2EN LL_PWR_IsEnabledVddAMonitor2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledVddAMonitor2(void) -{ - return ((READ_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN) == (PWR_SVMCR_AVM2EN)) ? 1UL : 0UL); -} -#define LL_PWR_IsEnabledVDDAMonitor2 LL_PWR_IsEnabledVddAMonitor2 /* for legacy purpose */ - -/** - * @brief Enable the wake up pin_x. - * @rmtoll WUCR1 WUPENx LL_PWR_EnableWakeUpPin - * @param WakeUpPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - SET_BIT(PWR->WUCR1, WakeUpPin); -} - -/** - * @brief Disable the wake up pin_x. - * @rmtoll WUCR1 WUPENx LL_PWR_DisableWakeUpPin - * @param WakeUpPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->WUCR1, WakeUpPin); -} - -/** - * @brief Check if the wake up pin_x is enabled. - * @rmtoll WUCR1 WUPENx LL_PWR_IsEnabledWakeUpPin - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) -{ - return ((READ_BIT(PWR->WUCR1, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL); -} - -/** - * @brief Set the wake up pin polarity low for the event detection. - * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityLow - * @param WakeUpPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) -{ - SET_BIT(PWR->WUCR2, WakeUpPin); -} - -/** - * @brief Set the wake up pin polarity high for the event detection. - * @rmtoll WUCR2 WUPPx LL_PWR_SetWakeUpPinPolarityHigh - * @param WakeUpPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) -{ - CLEAR_BIT(PWR->WUCR2, WakeUpPin); -} - -/** - * @brief Get the wake up pin polarity for the event detection. - * @rmtoll WUCR2 WUPPx LL_PWR_GetWakeUpPinPolarity - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval State of bit (1 : polarity or 0 : polarity high). - */ -__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPolarity(uint32_t WakeUpPin) -{ - return ((READ_BIT(PWR->WUCR2, WakeUpPin) == WakeUpPin) ? 1UL : 0UL); -} - -/** - * @brief Set the wakeup pin_x selection 0. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal0Selection - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal0Selection(uint32_t WakeUpPin) -{ - MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), - (LL_PWR_WAKEUP_PIN_SELECTION_0 << (POSITION_VAL(WakeUpPin) * 2U))); -} - -/** - * @brief Set the wakeup pin_x selection 1. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal1Selection - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal1Selection(uint32_t WakeUpPin) -{ - MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), - (LL_PWR_WAKEUP_PIN_SELECTION_1 << (POSITION_VAL(WakeUpPin) * 2U))); -} - -/** - * @brief Set the wakeup pin_x selection 2. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal2Selection - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal2Selection(uint32_t WakeUpPin) -{ - MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), - (LL_PWR_WAKEUP_PIN_SELECTION_2 << (POSITION_VAL(WakeUpPin) * 2U))); -} - -/** - * @brief Set the wakeup pin_x selection 3. - * @rmtoll WUCR3 WUSELx LL_PWR_SetWakeUpPinSignal3Selection - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetWakeUpPinSignal3Selection(uint32_t WakeUpPin) -{ - MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)), - (LL_PWR_WAKEUP_PIN_SELECTION_3 << (POSITION_VAL(WakeUpPin) * 2U))); -} - -/** - * @brief Get the wakeup pin_x selection. - * @rmtoll WUCR3 WUSELx LL_PWR_GetWakeUpPinSignalSelection - * @param WakeUpPin This parameter can be one of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1 - * @arg @ref LL_PWR_WAKEUP_PIN2 - * @arg @ref LL_PWR_WAKEUP_PIN3 - * @arg @ref LL_PWR_WAKEUP_PIN4 - * @arg @ref LL_PWR_WAKEUP_PIN5 - * @arg @ref LL_PWR_WAKEUP_PIN6 - * @arg @ref LL_PWR_WAKEUP_PIN7 - * @arg @ref LL_PWR_WAKEUP_PIN8 - */ -__STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinSignalSelection(uint32_t WakeUpPin) -{ - return (READ_BIT(PWR->WUCR3, (3UL << (POSITION_VAL(WakeUpPin) * 2U)))); -} - -/** - * @brief Enable backup regulator. - * @rmtoll BDCR1 BREN LL_PWR_EnableBkUpRegulator - * @note When this bit is set, the backup RAM content is kept in Standby and - * VBAT modes. If BREN is reset, the backup RAM can still be used in - * Run, Sleep and Stop modes. However, its content is lost in Standby, - * Shutdown and VBAT modes. This bit can be written only when the - * regulator is LDO, which must be configured before switching to SMPS. - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void) -{ - SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); -} - -/** - * @brief Disable backup regulator - * @rmtoll BDCR1 BREN LL_PWR_DisableBkUpRegulator - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void) -{ - CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); -} - -/** - * @brief Check if the backup regulator is enabled - * @rmtoll BDCR1 BREN LL_PWR_IsEnabledBkUpRegulator - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void) -{ - return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_BREN) == (PWR_BDCR1_BREN)) ? 1UL : 0UL); -} - -/** - * @brief Enable the backup domain voltage and temperature monitoring. - * @rmtoll BDCR1 MONEN LL_PWR_EnableMonitoring - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableMonitoring(void) -{ - SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); -} - -/** - * @brief Disable the backup domain voltage and temperature monitoring. - * @rmtoll BDCR1 MONEN LL_PWR_DisableMonitoring - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableMonitoring(void) -{ - CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); -} - -/** - * @brief Check if the backup domain voltage and temperature monitoring is - * enabled. - * @rmtoll BDCR1 MONEN LL_PWR_IsEnabledMonitoring - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void) -{ - return ((READ_BIT(PWR->BDCR1, PWR_BDCR1_MONEN) == (PWR_BDCR1_MONEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable battery charging. - * @rmtoll BDCR2 VBE LL_PWR_EnableBatteryCharging - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) -{ - SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); -} - -/** - * @brief Disable battery charging. - * @rmtoll BDCR2 VBE LL_PWR_DisableBatteryCharging - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) -{ - CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); -} - -/** - * @brief Check if battery charging is enabled. - * @rmtoll BDCR2 VBE LL_PWR_IsEnabledBatteryCharging - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) -{ - return ((READ_BIT(PWR->BDCR2, PWR_BDCR2_VBE) == (PWR_BDCR2_VBE)) ? 1UL : 0UL); -} - -/** - * @brief Set the Battery charge resistor impedance - * @rmtoll BDCR2 VBRS LL_PWR_SetBattChargResistor - * @param Resistor This parameter can be one of the following values: - * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K - * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K - * @retval None - */ -__STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) -{ - MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, Resistor); -} - -/** - * @brief Get the Battery charge resistor impedance - * @rmtoll BDCR2 VBRS LL_PWR_GetBattChargResistor - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K - * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_1_5K - */ -__STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) -{ - return (uint32_t)(READ_BIT(PWR->BDCR2, PWR_BDCR2_VBRS)); -} - -/** - * @brief Enable access to the backup domain. - * @rmtoll DBPR DBP LL_PWR_EnableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->DBPR, PWR_DBPR_DBP); -} - -/** - * @brief Disable access to the backup domain. - * @rmtoll DBPR DBP LL_PWR_DisableBkUpAccess - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); -} - -/** - * @brief Check if the access to backup domain is enabled. - * @rmtoll DBPR DBP LL_PWR_IsEnabledBkUpAccess - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) -{ - return ((READ_BIT(PWR->DBPR, PWR_DBPR_DBP) == (PWR_DBPR_DBP)) ? 1UL : 0UL); -} - -#ifdef UCPD1 -/** - * @brief Enable the USB Type-C and Power Delivery memorization in Standby mode. - * @note This function must be called just before entering Standby mode. - * @rmtoll UCPDR UCPD_STDBY LL_PWR_EnableUCPDStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUCPDStandbyMode(void) -{ - SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); -} - -/** - * @brief Disable the USB Type-C and Power Delivery memorization in Standby mode. - * @note This function must be called after exiting Standby mode and before any - * UCPD configuration update. - * @rmtoll UCPDR UCPD_STDBY LL_PWR_DisableUCPDStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUCPDStandbyMode(void) -{ - CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); -} - -/** - * @brief Check the USB Type-C and Power Delivery Standby mode memorization state. - * @rmtoll UCPDR UCPD_STDBY LL_PWR_IsEnabledUCPDStandbyMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDStandbyMode(void) -{ - return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY) == (PWR_UCPDR_UCPD_STDBY)) ? 1UL : 0UL); -} - -/** - * @brief Enable the USB Type-C and power delivery dead battery pull-down behavior - * on UCPD CC1 and CC2 pins. - * @note After exiting reset, the USB Type-C dead battery behavior is enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended - * to disable it in all cases, either to stop this pull-down or to hand over - * control to the UCPD (which should therefore be initialized before doing the disable). - * @rmtoll UCPDR UCPD_DBDIS LL_PWR_EnableUCPDDeadBattery - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableUCPDDeadBattery(void) -{ - CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); -} - -/** - * @brief Disable the USB Type-C and power delivery dead battery pull-down behavior - * on UCPD CC1 and CC2 pins. - * @note After exiting reset, the USB Type-C dead battery behavior is enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended - * to disable it in all cases, either to stop this pull-down or to hand over - * control to the UCPD (which should therefore be initialized before doing the disable). - * @rmtoll UCPDR UCPD_DBDIS LL_PWR_DisableUCPDDeadBattery - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableUCPDDeadBattery(void) -{ - SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); -} - -/** - * @brief Check the USB Type-C and power delivery dead battery pull-down behavior - * on UCPD CC1 and CC2 pins. - * @note After exiting reset, the USB Type-C dead battery behavior is enabled, - * which may have a pull-down effect on CC1 and CC2 pins. It is recommended - * to disable it in all cases, either to stop this pull-down or to hand over - * control to the UCPD (which should therefore be initialized before doing the disable). - * @rmtoll UCPDR UCPD_DBDIS LL_PWR_IsEnabledUCPDDeadBattery - * @retval State of feature (1 : enabled; 0 : disabled). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledUCPDDeadBattery(void) -{ - return ((READ_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS) == (PWR_UCPDR_UCPD_DBDIS)) ? 0UL : 1UL); -} -#endif /* UCPD1 */ - -/** - * @brief Enable the pull-up and pull-down configuration. - * @rmtoll APCR APC LL_PWR_EnablePUPDConfig - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnablePUPDConfig(void) -{ - SET_BIT(PWR->APCR, PWR_APCR_APC); -} - -/** - * @brief Disable the pull-up and pull-down configuration. - * @rmtoll APCR APC LL_PWR_DisablePUPDConfig - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisablePUPDConfig(void) -{ - CLEAR_BIT(PWR->APCR, PWR_APCR_APC); -} - -/** - * @brief Check if the pull-up and pull-down configuration is enabled. - * @rmtoll APCR APC LL_PWR_IsEnabledPUPDConfig - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDConfig(void) -{ - return ((READ_BIT(PWR->APCR, PWR_APCR_APC) == (PWR_APCR_APC)) ? 1UL : 0UL); -} - -/** - * @brief Enable GPIO pull-up in Standby and Shutdown modes - * @rmtoll PUCRx PUx LL_PWR_EnableGPIOPullUp - * @param GPIOPort This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PORTA - * @arg @ref LL_PWR_GPIO_PORTB - * @arg @ref LL_PWR_GPIO_PORTC - * @arg @ref LL_PWR_GPIO_PORTD - * @arg @ref LL_PWR_GPIO_PORTE - * @arg @ref LL_PWR_GPIO_PORTF - * @arg @ref LL_PWR_GPIO_PORTG - * @arg @ref LL_PWR_GPIO_PORTH - * @arg @ref LL_PWR_GPIO_PORTI - * @arg @ref LL_PWR_GPIO_PORTJ (*) - * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. - * @param GPIOPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_GPIO_PIN_0 - * @arg @ref LL_PWR_GPIO_PIN_1 - * @arg @ref LL_PWR_GPIO_PIN_2 - * @arg @ref LL_PWR_GPIO_PIN_3 - * @arg @ref LL_PWR_GPIO_PIN_4 - * @arg @ref LL_PWR_GPIO_PIN_5 - * @arg @ref LL_PWR_GPIO_PIN_6 - * @arg @ref LL_PWR_GPIO_PIN_7 - * @arg @ref LL_PWR_GPIO_PIN_8 - * @arg @ref LL_PWR_GPIO_PIN_9 - * @arg @ref LL_PWR_GPIO_PIN_10 - * @arg @ref LL_PWR_GPIO_PIN_11 - * @arg @ref LL_PWR_GPIO_PIN_12 - * @arg @ref LL_PWR_GPIO_PIN_13 - * @arg @ref LL_PWR_GPIO_PIN_14 - * @arg @ref LL_PWR_GPIO_PIN_15 - * @retval None. - */ -__STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin) -{ - SET_BIT(*((uint32_t *)GPIOPort), GPIOPin); -} - -/** - * @brief Disable GPIO pull-up in Standby and Shutdown modes - * @rmtoll PUCRx PUx LL_PWR_DisableGPIOPullUp - * @param GPIOPort This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PORTA - * @arg @ref LL_PWR_GPIO_PORTB - * @arg @ref LL_PWR_GPIO_PORTC - * @arg @ref LL_PWR_GPIO_PORTD - * @arg @ref LL_PWR_GPIO_PORTE - * @arg @ref LL_PWR_GPIO_PORTF - * @arg @ref LL_PWR_GPIO_PORTG - * @arg @ref LL_PWR_GPIO_PORTH - * @arg @ref LL_PWR_GPIO_PORTI - * @arg @ref LL_PWR_GPIO_PORTJ (*) - * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. - * @param GPIOPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_GPIO_PIN_0 - * @arg @ref LL_PWR_GPIO_PIN_1 - * @arg @ref LL_PWR_GPIO_PIN_2 - * @arg @ref LL_PWR_GPIO_PIN_3 - * @arg @ref LL_PWR_GPIO_PIN_4 - * @arg @ref LL_PWR_GPIO_PIN_5 - * @arg @ref LL_PWR_GPIO_PIN_6 - * @arg @ref LL_PWR_GPIO_PIN_7 - * @arg @ref LL_PWR_GPIO_PIN_8 - * @arg @ref LL_PWR_GPIO_PIN_9 - * @arg @ref LL_PWR_GPIO_PIN_10 - * @arg @ref LL_PWR_GPIO_PIN_11 - * @arg @ref LL_PWR_GPIO_PIN_12 - * @arg @ref LL_PWR_GPIO_PIN_13 - * @arg @ref LL_PWR_GPIO_PIN_14 - * @arg @ref LL_PWR_GPIO_PIN_15 - * @retval None. - */ -__STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin) -{ - CLEAR_BIT(*((uint32_t *)GPIOPort), GPIOPin); -} - -/** - * @brief Check if GPIO pull-up in Standby and Shutdown modes is enabled - * @rmtoll PUCRx PUx LL_PWR_IsEnabledGPIOPullUp - * @param GPIOPort This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PORTA - * @arg @ref LL_PWR_GPIO_PORTB - * @arg @ref LL_PWR_GPIO_PORTC - * @arg @ref LL_PWR_GPIO_PORTD - * @arg @ref LL_PWR_GPIO_PORTE - * @arg @ref LL_PWR_GPIO_PORTF - * @arg @ref LL_PWR_GPIO_PORTG - * @arg @ref LL_PWR_GPIO_PORTH - * @arg @ref LL_PWR_GPIO_PORTI - * @arg @ref LL_PWR_GPIO_PORTJ (*) - * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. - * @param GPIOPin This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PIN_0 - * @arg @ref LL_PWR_GPIO_PIN_1 - * @arg @ref LL_PWR_GPIO_PIN_2 - * @arg @ref LL_PWR_GPIO_PIN_3 - * @arg @ref LL_PWR_GPIO_PIN_4 - * @arg @ref LL_PWR_GPIO_PIN_5 - * @arg @ref LL_PWR_GPIO_PIN_6 - * @arg @ref LL_PWR_GPIO_PIN_7 - * @arg @ref LL_PWR_GPIO_PIN_8 - * @arg @ref LL_PWR_GPIO_PIN_9 - * @arg @ref LL_PWR_GPIO_PIN_10 - * @arg @ref LL_PWR_GPIO_PIN_11 - * @arg @ref LL_PWR_GPIO_PIN_12 - * @arg @ref LL_PWR_GPIO_PIN_13 - * @arg @ref LL_PWR_GPIO_PIN_14 - * @arg @ref LL_PWR_GPIO_PIN_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIOPort, uint32_t GPIOPin) -{ - return ((READ_BIT(*((uint32_t *)(GPIOPort)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL); -} - -/** - * @brief Enable GPIO pull-down in Standby and Shutdown modes. - * @rmtoll PDCRx PDx LL_PWR_EnableGPIOPullDown - * @param GPIOPort This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PORTA - * @arg @ref LL_PWR_GPIO_PORTB - * @arg @ref LL_PWR_GPIO_PORTC - * @arg @ref LL_PWR_GPIO_PORTD - * @arg @ref LL_PWR_GPIO_PORTE - * @arg @ref LL_PWR_GPIO_PORTF - * @arg @ref LL_PWR_GPIO_PORTG - * @arg @ref LL_PWR_GPIO_PORTH - * @arg @ref LL_PWR_GPIO_PORTI - * @arg @ref LL_PWR_GPIO_PORTJ (*) - * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. - * @param GPIOPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_GPIO_PIN_0 - * @arg @ref LL_PWR_GPIO_PIN_1 - * @arg @ref LL_PWR_GPIO_PIN_2 - * @arg @ref LL_PWR_GPIO_PIN_3 - * @arg @ref LL_PWR_GPIO_PIN_4 - * @arg @ref LL_PWR_GPIO_PIN_5 - * @arg @ref LL_PWR_GPIO_PIN_6 - * @arg @ref LL_PWR_GPIO_PIN_7 - * @arg @ref LL_PWR_GPIO_PIN_8 - * @arg @ref LL_PWR_GPIO_PIN_9 - * @arg @ref LL_PWR_GPIO_PIN_10 - * @arg @ref LL_PWR_GPIO_PIN_11 - * @arg @ref LL_PWR_GPIO_PIN_12 - * @arg @ref LL_PWR_GPIO_PIN_13 - * @arg @ref LL_PWR_GPIO_PIN_14 - * @arg @ref LL_PWR_GPIO_PIN_15 - * @retval None. - */ -__STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin) -{ - SET_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin); -} - -/** - * @brief Disable GPIO pull-down in Standby and Shutdown modes. - * @rmtoll PDCRx PDx LL_PWR_DisableGPIOPullDown - * @param GPIOPort This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PORTA - * @arg @ref LL_PWR_GPIO_PORTB - * @arg @ref LL_PWR_GPIO_PORTC - * @arg @ref LL_PWR_GPIO_PORTD - * @arg @ref LL_PWR_GPIO_PORTE - * @arg @ref LL_PWR_GPIO_PORTF - * @arg @ref LL_PWR_GPIO_PORTG - * @arg @ref LL_PWR_GPIO_PORTH - * @arg @ref LL_PWR_GPIO_PORTI - * @arg @ref LL_PWR_GPIO_PORTJ (*) - * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. - * @param GPIOPin This parameter can be a combination of the following values: - * @arg @ref LL_PWR_GPIO_PIN_0 - * @arg @ref LL_PWR_GPIO_PIN_1 - * @arg @ref LL_PWR_GPIO_PIN_2 - * @arg @ref LL_PWR_GPIO_PIN_3 - * @arg @ref LL_PWR_GPIO_PIN_4 - * @arg @ref LL_PWR_GPIO_PIN_5 - * @arg @ref LL_PWR_GPIO_PIN_6 - * @arg @ref LL_PWR_GPIO_PIN_7 - * @arg @ref LL_PWR_GPIO_PIN_8 - * @arg @ref LL_PWR_GPIO_PIN_9 - * @arg @ref LL_PWR_GPIO_PIN_10 - * @arg @ref LL_PWR_GPIO_PIN_11 - * @arg @ref LL_PWR_GPIO_PIN_12 - * @arg @ref LL_PWR_GPIO_PIN_13 - * @arg @ref LL_PWR_GPIO_PIN_14 - * @arg @ref LL_PWR_GPIO_PIN_15 - * @retval None. - */ -__STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin) -{ - CLEAR_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin); -} - -/** - * @brief Check if GPIO pull-down in Standby and Shutdown modes is enabled - * @rmtoll PDCRx PDx LL_PWR_IsEnabledGPIOPullUp - * @param GPIOPort This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PORTA - * @arg @ref LL_PWR_GPIO_PORTB - * @arg @ref LL_PWR_GPIO_PORTC - * @arg @ref LL_PWR_GPIO_PORTD - * @arg @ref LL_PWR_GPIO_PORTE - * @arg @ref LL_PWR_GPIO_PORTF - * @arg @ref LL_PWR_GPIO_PORTG - * @arg @ref LL_PWR_GPIO_PORTH - * @arg @ref LL_PWR_GPIO_PORTI - * @arg @ref LL_PWR_GPIO_PORTJ (*) - * (*) value can be used only for STM32U59xxx and STM32U5A9xx devices. - * @param GPIOPin This parameter can be one of the following values: - * @arg @ref LL_PWR_GPIO_PIN_0 - * @arg @ref LL_PWR_GPIO_PIN_1 - * @arg @ref LL_PWR_GPIO_PIN_2 - * @arg @ref LL_PWR_GPIO_PIN_3 - * @arg @ref LL_PWR_GPIO_PIN_4 - * @arg @ref LL_PWR_GPIO_PIN_5 - * @arg @ref LL_PWR_GPIO_PIN_6 - * @arg @ref LL_PWR_GPIO_PIN_7 - * @arg @ref LL_PWR_GPIO_PIN_8 - * @arg @ref LL_PWR_GPIO_PIN_9 - * @arg @ref LL_PWR_GPIO_PIN_10 - * @arg @ref LL_PWR_GPIO_PIN_11 - * @arg @ref LL_PWR_GPIO_PIN_12 - * @arg @ref LL_PWR_GPIO_PIN_13 - * @arg @ref LL_PWR_GPIO_PIN_14 - * @arg @ref LL_PWR_GPIO_PIN_15 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIOPort, uint32_t GPIOPin) -{ - return ((READ_BIT(*((__IO uint32_t *)(GPIOPort + 4U)), GPIOPin) == (GPIOPin)) ? 1UL : 0UL); -} - -/** - * @brief Get currently voltage scaling applied to VCORE. - * @rmtoll SVMSR ACTVOS[1:0] LL_PWR_GetRegulCurrentVOS - * @retval Returned value can be one of the following values: - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3 - * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE4 - */ -__STATIC_INLINE uint32_t LL_PWR_GetRegulCurrentVOS(void) -{ - return (READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS)); -} -/** - * @} - */ - -/** @defgroup PWR_LL_EF_FLAG_MANAGEMENT PWR FLAG Management - * @{ - */ - -/** - * @brief Indicate whether the EPOD (Embedded Power Distribution) booster is - * ready OR not. - * @rmtoll VOSR BOOSTRDY LL_PWR_IsActiveFlag_BOOST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BOOST(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == (PWR_VOSR_BOOSTRDY)) ? 1UL : 0UL); -} - -#if defined (PWR_VOSR_USBBOOSTRDY) -/** - * @brief Indicate whether the USB EPOD (Embedded Power Distribution) booster is - * ready OR not. - * @rmtoll VOSR USBBOOSTRDY LL_PWR_IsActiveFlag_USBBOOST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USBBOOST(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_USBBOOSTRDY) == (PWR_VOSR_USBBOOSTRDY)) ? 1UL : 0UL); -} -#endif /* defined (PWR_VOSR_USBBOOSTRDY) */ - -/** - * @brief Indicate whether the regulator voltage output is above voltage - * scaling range or not. - * @rmtoll VOSR VOSRDY LL_PWR_IsActiveFlag_VOS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) -{ - return ((READ_BIT(PWR->VOSR, PWR_VOSR_VOSRDY) == (PWR_VOSR_VOSRDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the system was in standby mode or not. - * @rmtoll SR SBF LL_PWR_IsActiveFlag_SB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) -{ - return ((READ_BIT(PWR->SR, PWR_SR_SBF) == (PWR_SR_SBF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the system was in stop mode or not. - * @rmtoll SR STOPF LL_PWR_IsActiveFlag_STOP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_STOP(void) -{ - return ((READ_BIT(PWR->SR, PWR_SR_STOPF) == (PWR_SR_STOPF)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the regulator supply is LDO or SMPS. - * @rmtoll SVMSR REGS LL_PWR_IsActiveFlag_REGULATOR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGULATOR(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_REGS) == (PWR_SVMSR_REGS)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the VDD voltage is below the threshold or not. - * @rmtoll SVMSR PVDO LL_PWR_IsActiveFlag_PVDO - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_PVDO) == (PWR_SVMSR_PVDO)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the regulator voltage output is equal to current - * used voltage scaling range or not. - * @rmtoll SVMSR ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY) == (PWR_SVMSR_ACTVOSRDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the VDDUSB is below the threshold of monitor or not. - * @rmtoll SVMSR VDDUSBRDY LL_PWR_IsActiveFlag_VDDUSB - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDUSB(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDUSBRDY) == (PWR_SVMSR_VDDUSBRDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the VDDIO2 is below the threshold of monitor or not. - * @rmtoll SVMSR VDDIO2RDY LL_PWR_IsActiveFlag_VDDIO2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDIO2(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDIO2RDY) == (PWR_SVMSR_VDDIO2RDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the VDDA1 is below the threshold of monitor 1 or - * not. - * @rmtoll SVMSR VDDA1RDY LL_PWR_IsActiveFlag_VDDA1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA1(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA1RDY) == (PWR_SVMSR_VDDA1RDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the VDDA2 is below the threshold of monitor 2 or - * not. - * @rmtoll SVMSR VDDA2RDY LL_PWR_IsActiveFlag_VDDA2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VDDA2(void) -{ - return ((READ_BIT(PWR->SVMSR, PWR_SVMSR_VDDA2RDY) == (PWR_SVMSR_VDDA2RDY)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the VBAT level is below high threshold or not. - * @rmtoll BDSR VBATH LL_PWR_IsActiveFlag_VBATH - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void) -{ - return ((READ_BIT(PWR->BDSR, PWR_BDSR_VBATH) == (PWR_BDSR_VBATH)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the CPU temperature level is above low threshold or - * not. - * @rmtoll BDSR TEMPL LL_PWR_IsActiveFlag_TEMPL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void) -{ - return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPL) == (PWR_BDSR_TEMPL)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether the CPU temperature level is below high threshold - * or not. - * @rmtoll BDSR TEMPH LL_PWR_IsActiveFlag_TEMPH - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void) -{ - return ((READ_BIT(PWR->BDSR, PWR_BDSR_TEMPH) == (PWR_BDSR_TEMPH)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 1. - * @rmtoll WUSR WUF1 LL_PWR_IsActiveFlag_WU1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) == (PWR_WUSR_WUF1)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 2. - * @rmtoll WUSR WUF2 LL_PWR_IsActiveFlag_WU2 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) == (PWR_WUSR_WUF2)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 3. - * @rmtoll WUSR WUF3 LL_PWR_IsActiveFlag_WU3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) == (PWR_WUSR_WUF3)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 4. - * @rmtoll WUSR WUF4 LL_PWR_IsActiveFlag_WU4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) == (PWR_WUSR_WUF4)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 5. - * @rmtoll WUSR WUF5 LL_PWR_IsActiveFlag_WU5 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) == (PWR_WUSR_WUF5)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 6. - * @rmtoll WUSR WUF6 LL_PWR_IsActiveFlag_WU6 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) == (PWR_WUSR_WUF6)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 7. - * @rmtoll WUSR WUF7 LL_PWR_IsActiveFlag_WU7 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU7(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) == (PWR_WUSR_WUF7)) ? 1UL : 0UL); -} - -/** - * @brief Indicate whether a wakeup event is detected on wake up pin 8. - * @rmtoll WUSR WUF8 LL_PWR_IsActiveFlag_WU8 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU8(void) -{ - return ((READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) == (PWR_WUSR_WUF8)) ? 1UL : 0UL); -} - -/** - * @brief Clear stop flag. - * @rmtoll SR CSSF LL_PWR_ClearFlag_STOP - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_STOP(void) -{ - WRITE_REG(PWR->SR, PWR_SR_CSSF); -} - -/** - * @brief Clear standby flag. - * @rmtoll SR CSSF LL_PWR_ClearFlag_SB - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_SB(void) -{ - WRITE_REG(PWR->SR, PWR_SR_CSSF); -} - -/** - * @brief Clear wake up flag 1. - * @rmtoll WUSCR CWUF1 LL_PWR_ClearFlag_WU1 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF1); -} - -/** - * @brief Clear wake up flag 2. - * @rmtoll WUSCR CWUF2 LL_PWR_ClearFlag_WU2 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF2); -} - -/** - * @brief Clear wake up flag 3. - * @rmtoll WUSCR CWUF3 LL_PWR_ClearFlag_WU3 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF3); -} - -/** - * @brief Clear wake up flag 4. - * @rmtoll WUSCR CWUF4 LL_PWR_ClearFlag_WU4 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF4); -} - -/** - * @brief Clear wake up flag 5. - * @rmtoll WUSCR CWUF5 LL_PWR_ClearFlag_WU5 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF5); -} - -/** - * @brief Clear wake up flag 6. - * @rmtoll WUSCR CWUF6 LL_PWR_ClearFlag_WU6 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU6(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF6); -} - -/** - * @brief Clear wake up flag 7. - * @rmtoll WUSCR CWUF7 LL_PWR_ClearFlag_WU7 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU7(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF7); -} - -/** - * @brief Clear wake up flag 8. - * @rmtoll WUSCR CWUF8 LL_PWR_ClearFlag_WU8 - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU8(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF8); -} - -/** - * @brief Clear all wake up flags. - * @rmtoll WUSCR CWUF LL_PWR_ClearFlag_WU - * @retval None - */ -__STATIC_INLINE void LL_PWR_ClearFlag_WU(void) -{ - WRITE_REG(PWR->WUSCR, PWR_WUSCR_CWUF); -} -/** - * @} - */ - -/** @defgroup PWR_LL_EF_ATTRIBUTE_MANAGEMENT PWR Attribute Management - * @{ - */ - -/** - * @brief Enable privileged mode for nsecure items. - * @rmtoll PRIVCFGR NSPRIV LL_PWR_EnableNSecurePrivilege - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableNSecurePrivilege(void) -{ - SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); -} - -/** - * @brief Disable privileged mode for nsecure items. - * @rmtoll PRIVCFGR NSPRIV LL_PWR_DisableNSecurePrivilege - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableNSecurePrivilege(void) -{ - CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); -} - -/** - * @brief Check if privileged mode for nsecure items is enabled. - * @rmtoll PRIVCFGR NSPRIV LL_PWR_IsEnabledNSecurePrivilege - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledNSecurePrivilege(void) -{ - return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV) == PWR_PRIVCFGR_NSPRIV) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable privileged mode for secure items. - * @rmtoll PRIVCFGR SPRIV LL_PWR_EnableSecurePrivilege - * @retval None - */ -__STATIC_INLINE void LL_PWR_EnableSecurePrivilege(void) -{ - SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); -} - -/** - * @brief Disable privileged mode for secure items. - * @rmtoll PRIVCFGR SPRIV LL_PWR_DisableSecurePrivilege - * @retval None - */ -__STATIC_INLINE void LL_PWR_DisableSecurePrivilege(void) -{ - CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Check if privileged mode for secure items is enabled. - * @rmtoll PRIVCFGR SPRIV LL_PWR_IsEnabledSecurePrivilege - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_PWR_IsEnabledSecurePrivilege(void) -{ - return ((READ_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV) == PWR_PRIVCFGR_SPRIV) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure secure attribute mode. - * @note This API can be executed only by CPU in secure mode. - * @rmtoll SECCFGR WUP1SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP2SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP3SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP4SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP5SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP6SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP7SEC LL_PWR_ConfigSecure\n - * SECCFGR WUP8SEC LL_PWR_ConfigSecure\n - * SECCFGR LPMSEC LL_PWR_ConfigSecure\n - * SECCFGR VDMSEC LL_PWR_ConfigSecure\n - * SECCFGR VBSEC LL_PWR_ConfigSecure\n - * SECCFGR APCSEC LL_PWR_ConfigSecure - * @param SecureConfig This parameter can be the full combination - * of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC - * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC - * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC - * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC - * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC - * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC - * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC - * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC - * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC - * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC - * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC - * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC - * @retval None. - */ -__STATIC_INLINE void LL_PWR_ConfigSecure(uint32_t SecureConfig) -{ - WRITE_REG(PWR->SECCFGR, SecureConfig); -} - -/** - * @brief Get secure attribute configuration. - * @note This API can be executed only by CPU in secure mode. - * @rmtoll SECCFGR WUP1SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP2SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP3SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP4SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP5SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP6SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP7SEC LL_PWR_GetConfigSecure\n - * SECCFGR WUP8SEC LL_PWR_GetConfigSecure\n - * SECCFGR LPMSEC LL_PWR_GetConfigSecure\n - * SECCFGR VDMSEC LL_PWR_GetConfigSecure\n - * SECCFGR VBSEC LL_PWR_GetConfigSecure\n - * SECCFGR APCSEC LL_PWR_GetConfigSecure - * @retval Returned value is the combination of the following values: - * @arg @ref LL_PWR_WAKEUP_PIN1_NSEC or LL_PWR_WAKEUP_PIN1_SEC - * @arg @ref LL_PWR_WAKEUP_PIN2_NSEC or LL_PWR_WAKEUP_PIN2_SEC - * @arg @ref LL_PWR_WAKEUP_PIN3_NSEC or LL_PWR_WAKEUP_PIN3_SEC - * @arg @ref LL_PWR_WAKEUP_PIN4_NSEC or LL_PWR_WAKEUP_PIN4_SEC - * @arg @ref LL_PWR_WAKEUP_PIN5_NSEC or LL_PWR_WAKEUP_PIN5_SEC - * @arg @ref LL_PWR_WAKEUP_PIN6_NSEC or LL_PWR_WAKEUP_PIN6_SEC - * @arg @ref LL_PWR_WAKEUP_PIN7_NSEC or LL_PWR_WAKEUP_PIN7_SEC - * @arg @ref LL_PWR_WAKEUP_PIN8_NSEC or LL_PWR_WAKEUP_PIN8_SEC - * @arg @ref LL_PWR_LPM_NSEC or LL_PWR_LPM_SEC - * @arg @ref LL_PWR_VDM_NSEC or LL_PWR_VDM_SEC - * @arg @ref LL_PWR_VB_NSEC or LL_PWR_VB_SEC - * @arg @ref LL_PWR_APC_NSEC or LL_PWR_APC_SEC - */ -__STATIC_INLINE uint32_t LL_PWR_GetConfigSecure(void) -{ - return (READ_REG(PWR->SECCFGR)); -} -#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/** - * @} - */ - -#if defined (USE_FULL_LL_DRIVER) -/** @defgroup PWR_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_PWR_DeInit(void); -/** - * @} - */ -#endif /* defined (USE_FULL_LL_DRIVER) */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (PWR) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - -#endif /* STM32U5xx_LL_PWR_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h deleted file mode 100644 index a152ca2c3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_rcc.h +++ /dev/null @@ -1,6120 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_rcc.h - * @author MCD Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_RCC_H -#define STM32U5xx_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Constants RCC Private Constants - * @{ - */ -/* Defines used to perform offsets*/ -/* Offset used to access to RCC_CCIPR1 and RCC_CCIPR2 registers */ -#define RCC_OFFSET_CCIPR1 0U -#define RCC_OFFSET_CCIPR2 0x04U -#define RCC_OFFSET_CCIPR3 0x08U - -/* Defines used for security configuration extension */ -#define RCC_SECURE_MASK 0x1FFFU -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ - uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */ - uint32_t PCLK3_Frequency; /*!< PCLK3 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 8000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ - -#if !defined (LSI_VALUE) -#define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ - -#if !defined (HSI48_VALUE) -#define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */ -#endif /* HSI48_VALUE */ - -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) -#define EXTERNAL_SAI1_CLOCK_VALUE 48000U /*!< Value of the SAI1_EXTCLK external oscillator in Hz */ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -#if !defined (EXTERNAL_SAI2_CLOCK_VALUE) -#define EXTERNAL_SAI2_CLOCK_VALUE 48000U /*!< Value of the SAI2_EXTCLK external oscillator in Hz */ -#endif /* EXTERNAL_SAI2_CLOCK_VALUE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LSIPRE LSI prescaler - * @{ - */ -#define LL_RCC_LSI_DIV_1 0x00000000U /*!< LSI divided by 1 */ -#define LL_RCC_LSI_DIV_128 RCC_BDCR_LSIPREDIV /*!< LSI divided by 128 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability - * @{ - */ -#define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium low driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium high driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSI_OSCILLATOR MSI clock Trimming - * @{ - */ -#define LL_RCC_MSI_OSCILLATOR_0 0x00000000U /*!< MSI clock trimming for ranges 0 to 3 */ -#define LL_RCC_MSI_OSCILLATOR_1 0x00000005U /*!< MSI clock trimming for ranges 4 to 7 */ -#define LL_RCC_MSI_OSCILLATOR_2 0x0000000AU /*!< MSI clock trimming for ranges 8 to 11 */ -#define LL_RCC_MSI_OSCILLATOR_3 0x0000000FU /*!< MSI clock trimming for ranges 12 to 15 */ -/** - * @} - */ - - -/** @defgroup RCC_LL_EC_MSISRANGE MSIS Clock Range - * @{ - */ -#define LL_RCC_MSISRANGE_0 0x00000000U /*!< MSIS = 48 MHz */ -#define LL_RCC_MSISRANGE_1 RCC_ICSCR1_MSISRANGE_0 /*!< MSIS = 24 MHz */ -#define LL_RCC_MSISRANGE_2 RCC_ICSCR1_MSISRANGE_1 /*!< MSIS = 16 MHz */ -#define LL_RCC_MSISRANGE_3 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1) /*!< MSIS = 12 MHz */ -#define LL_RCC_MSISRANGE_4 RCC_ICSCR1_MSISRANGE_2 /*!< MSIS = 4 MHz */ -#define LL_RCC_MSISRANGE_5 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 2 MHz */ -#define LL_RCC_MSISRANGE_6 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1.5 MHz */ -#define LL_RCC_MSISRANGE_7 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2) /*!< MSIS = 1 MHz */ -#define LL_RCC_MSISRANGE_8 RCC_ICSCR1_MSISRANGE_3 /*!< MSIS = 3.072 MHz */ -#define LL_RCC_MSISRANGE_9 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.536 MHz */ -#define LL_RCC_MSISRANGE_10 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 1.024 MHz */ -#define LL_RCC_MSISRANGE_11 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 768 KHz */ -#define LL_RCC_MSISRANGE_12 (RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 400 KHz */ -#define LL_RCC_MSISRANGE_13 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 200 KHz */ -#define LL_RCC_MSISRANGE_14 (RCC_ICSCR1_MSISRANGE_1 | RCC_ICSCR1_MSISRANGE_2 | RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 150 KHz */ -#define LL_RCC_MSISRANGE_15 (RCC_ICSCR1_MSISRANGE_0 | RCC_ICSCR1_MSISRANGE_1| RCC_ICSCR1_MSISRANGE_2 | \ - RCC_ICSCR1_MSISRANGE_3) /*!< MSIS = 100 KHz */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSIKRANGE MSIK Clock Range - * @{ - */ -#define LL_RCC_MSIKRANGE_0 0x00000000U /*!< MSIK = 48 MHz */ -#define LL_RCC_MSIKRANGE_1 RCC_ICSCR1_MSIKRANGE_0 /*!< MSIK = 24 MHz */ -#define LL_RCC_MSIKRANGE_2 RCC_ICSCR1_MSIKRANGE_1 /*!< MSIK = 16 MHz */ -#define LL_RCC_MSIKRANGE_3 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1) /*!< MSIK = 12 MHz */ -#define LL_RCC_MSIKRANGE_4 RCC_ICSCR1_MSIKRANGE_2 /*!< MSIK = 4 MHz */ -#define LL_RCC_MSIKRANGE_5 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 2 MHz */ -#define LL_RCC_MSIKRANGE_6 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1.5 MHz */ -#define LL_RCC_MSIKRANGE_7 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2) /*!< MSIK = 1 MHz */ -#define LL_RCC_MSIKRANGE_8 RCC_ICSCR1_MSIKRANGE_3 /*!< MSIK = 3.072 MHz */ -#define LL_RCC_MSIKRANGE_9 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.536 MHz */ -#define LL_RCC_MSIKRANGE_10 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 1.024 MHz */ -#define LL_RCC_MSIKRANGE_11 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 768 KHz */ -#define LL_RCC_MSIKRANGE_12 (RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 400 KHz */ -#define LL_RCC_MSIKRANGE_13 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 200 KHz */ -#define LL_RCC_MSIKRANGE_14 (RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 150 KHz */ -#define LL_RCC_MSIKRANGE_15 (RCC_ICSCR1_MSIKRANGE_0 | RCC_ICSCR1_MSIKRANGE_1 | RCC_ICSCR1_MSIKRANGE_2 | \ - RCC_ICSCR1_MSIKRANGE_3) /*!< MSIK = 100 KHz */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSISSRANGE MSIS range after Standby mode - * @{ - */ -#define LL_RCC_MSISSRANGE_4 RCC_CSR_MSISSRANGE_2 /*!< MSIS = 4 MHz */ -#define LL_RCC_MSISSRANGE_5 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_0) /*!< MSIS = 2 MHz */ -#define LL_RCC_MSISSRANGE_6 (RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1.5 MHz */ -#define LL_RCC_MSISSRANGE_7 (RCC_CSR_MSISSRANGE_0 | RCC_CSR_MSISSRANGE_2 | RCC_CSR_MSISSRANGE_1) /*!< MSIS = 1 MHz */ -#define LL_RCC_MSISSRANGE_8 RCC_CSR_MSISSRANGE_3 /*!< MSIS = 3.072 MHz*/ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSIKSRANGE MSIK range after Standby mode - * @{ - */ -#define LL_RCC_MSIKSRANGE_4 RCC_CSR_MSIKSRANGE_2 /*!< MSIK = 4 MHz */ -#define LL_RCC_MSIKSRANGE_5 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 2 MHz */ -#define LL_RCC_MSIKSRANGE_6 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1) /*!< MSIK = 1.5 MHz */ -#define LL_RCC_MSIKSRANGE_7 (RCC_CSR_MSIKSRANGE_2 | RCC_CSR_MSIKSRANGE_1 | RCC_CSR_MSIKSRANGE_0) /*!< MSIK = 1 MHz */ -#define LL_RCC_MSIKSRANGE_8 RCC_CSR_MSIKSRANGE_3 /*!< MSIK = 3.072 MHz*/ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSIPLLMODE MSIS/MSIK Pll Mode - * @{ - */ -#define LL_RCC_PLLMODE_MSIS RCC_CR_MSIPLLSEL /*!< MSIS selection for Pll Mode */ -#define LL_RCC_PLLMODE_MSIK 0U /*!< MSIK selection for Pll Mode */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSIBIASMODE MSI BIAS Mode - * @{ - */ -#define LL_RCC_MSIBIASMODE_SAMPLING RCC_ICSCR1_MSIBIAS /*!< Sampling mode selection for MSI*/ -#define LL_RCC_MSIBIASMODE_CONTINUOUS 0U /*!< Continuous mode selection for MSI*/ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_HSEEXT EXTERNAL HSE Mode - * @{ - */ -#define LL_RCC_HSE_ANALOG_MODE 0U /*!< HSE clock used as ANALOG clock source */ -#define LL_RCC_HSE_DIGITAL_MODE RCC_CR_HSEEXT /*!< HSE clock used as DIGITAL clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection - * @{ - */ -#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ -#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ -/** - * @} - */ - - -/** @defgroup RCC_LL_EC_PLL1MBOOST_DIV EPOD prescaler - * @{ - */ -#define LL_RCC_PLL1MBOOST_DIV_1 0x00000000U /*!< PLL1CLK not divided */ -#define LL_RCC_PLL1MBOOST_DIV_2 RCC_PLL1CFGR_PLL1MBOOST_0 /*!< PLL1CLK divided by 2 */ -#define LL_RCC_PLL1MBOOST_DIV_4 RCC_PLL1CFGR_PLL1MBOOST_1 /*!< PLL1CLK divided by 4 */ -#define LL_RCC_PLL1MBOOST_DIV_6 (RCC_PLL1CFGR_PLL1MBOOST_1 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 6 */ -#define LL_RCC_PLL1MBOOST_DIV_8 RCC_PLL1CFGR_PLL1MBOOST_2 /*!< PLL1CLK divided by 8 */ -#define LL_RCC_PLL1MBOOST_DIV_10 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 10 */ -#define LL_RCC_PLL1MBOOST_DIV_12 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1) /*!< PLL1CLK divided by 12 */ -#define LL_RCC_PLL1MBOOST_DIV_14 (RCC_PLL1CFGR_PLL1MBOOST_2 | RCC_PLL1CFGR_PLL1MBOOST_1 | \ - RCC_PLL1CFGR_PLL1MBOOST_0) /*!< PLL1CLK divided by 14 */ -#define LL_RCC_PLL1MBOOST_DIV_16 RCC_PLL1CFGR_PLL1MBOOST_3 /*!< PLL1CLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_MSIS 0x00000000U /*!< MSIS selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR1_SW_0 /*!< HSI oscillator selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR1_SW_1 /*!< HSE selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_PLL1 (RCC_CFGR1_SW_1 | RCC_CFGR1_SW_0) /*!< PLL selection as system clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_MSIS 0x00000000U /*!< MSIS used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR1_SWS_0 /*!< HSI used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR1_SWS_1 /*!< HSE used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 (RCC_CFGR1_SWS_1 | RCC_CFGR1_SWS_0) /*!< PLL1 used as system clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR2_HPRE_3 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_1 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2) /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_0) /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1) /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR2_HPRE_3 | RCC_CFGR2_HPRE_2 | RCC_CFGR2_HPRE_1 | \ - RCC_CFGR2_HPRE_0)/*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSTICK_CLKSOURCE SYSTICK clock source selection - * @{ - */ -#define LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 0x00000000U /*!< HCLKDIV8 clock used as SYSTICK clock source */ -#define LL_RCC_SYSTICK_CLKSOURCE_LSI RCC_CCIPR1_SYSTICKSEL_0 /*!< LSI clock used as SYSTICK clock source */ -#define LL_RCC_SYSTICK_CLKSOURCE_LSE RCC_CCIPR1_SYSTICKSEL_1 /*!< LSE clock used as SYSTICK clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR2_PPRE1_2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1) /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 (RCC_CFGR2_PPRE1_2 | RCC_CFGR2_PPRE1_1 | RCC_CFGR2_PPRE1_0) /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2) - * @{ - */ -#define LL_RCC_APB2_DIV_1 0x00000000U /*!< HCLK not divided */ -#define LL_RCC_APB2_DIV_2 RCC_CFGR2_PPRE2_2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB2_DIV_4 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 4 */ -#define LL_RCC_APB2_DIV_8 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1) /*!< HCLK divided by 8 */ -#define LL_RCC_APB2_DIV_16 (RCC_CFGR2_PPRE2_2 | RCC_CFGR2_PPRE2_1 | RCC_CFGR2_PPRE2_0) /*!< HCLK divided by 16 */ -/** - * @} - */ - - -/** @defgroup RCC_LL_EC_APB3_DIV APB high-speed prescaler (APB3) - * @{ - */ -#define LL_RCC_APB3_DIV_1 0x00000000U /*!< HCLK not divided */ -#define LL_RCC_APB3_DIV_2 RCC_CFGR3_PPRE3_2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB3_DIV_4 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 4 */ -#define LL_RCC_APB3_DIV_8 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1) /*!< HCLK divided by 8 */ -#define LL_RCC_APB3_DIV_16 (RCC_CFGR3_PPRE3_2 | RCC_CFGR3_PPRE3_1 | RCC_CFGR3_PPRE3_0) /*!< HCLK divided by 16 */ -/** - * @} - */ - -#if defined(RCC_CFGR2_PPRE_DPHY) -/** @defgroup RCC_LL_EC_DPHY_DIV DSI PHY clock prescaler (DCLK) - * @{ - */ -#define LL_RCC_DPHY_DIV_1 0x00000000U /*!< DCLK not divided */ -#define LL_RCC_DPHY_DIV_2 RCC_CFGR2_PPRE_DPHY_2 /*!< DCLK divided by 2 */ -#define LL_RCC_DPHY_DIV_4 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 4 */ -#define LL_RCC_DPHY_DIV_8 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1) /*!< DCLK divided by 8 */ -#define LL_RCC_DPHY_DIV_16 (RCC_CFGR2_PPRE_DPHY_2 | RCC_CFGR2_PPRE_DPHY_1 | RCC_CFGR2_PPRE_DPHY_0) /*!< DCLK divided by 16 */ -/** - * @} - */ -#endif /* RCC_CFGR2_PPRE_DPHY */ - -/** @defgroup RCC_LL_EC_STOP_WAKEUPCLOCK Wakeup from Stop and CSS backup clock selection - * @{ - */ -#define LL_RCC_STOP_WAKEUPCLOCK_MSIS 0x00000000U /*!< MSIS selection after wake-up from STOP */ -#define LL_RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR1_STOPWUCK /*!< HSI selection after wake-up from STOP */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_STOP_WAKEUPKERCLOCK Wakeup from Stop kernel clock automatic enable selection - * @{ - */ -#define LL_RCC_STOP_WAKEUPKERCLOCK_MSIK 0x00000000U /*!< MSIK oscillator automatically enabled when exiting Stop mode */ -#define LL_RCC_STOP_WAKEUPKERCLOCK_HSI RCC_CFGR1_STOPKERWUCK /*!< HSI oscillator automatically enabled when exiting Stop mode */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ -#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR1_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_MSIS RCC_CFGR1_MCOSEL_1 /*!< MSIS selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1) /*!< HSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR1_MCOSEL_2 /*!< HSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR1_MCOSEL_1 | RCC_CFGR1_MCOSEL_2) /*!< LSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_1| RCC_CFGR1_MCOSEL_2)/*!< LSE selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSI48 RCC_CFGR1_MCOSEL_3 /*!< HSI48 selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_MSIK (RCC_CFGR1_MCOSEL_0 | RCC_CFGR1_MCOSEL_3) /*!< MSIK selection as MCO1 source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler - * @{ - */ -#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO not divided */ -#define LL_RCC_MCO1_DIV_2 RCC_CFGR1_MCOPRE_0 /*!< MCO divided by 2 */ -#define LL_RCC_MCO1_DIV_4 RCC_CFGR1_MCOPRE_1 /*!< MCO divided by 4 */ -#define LL_RCC_MCO1_DIV_8 (RCC_CFGR1_MCOPRE_1 | RCC_CFGR1_MCOPRE_0) /*!< MCO divided by 8 */ -#define LL_RCC_MCO1_DIV_16 RCC_CFGR1_MCOPRE_2 /*!< MCO divided by 16 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 32 used as RTC clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_USART_CLKSOURCE Peripheral USARTx clock source selection - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U)| (RCC_CCIPR1_USART1SEL_Pos << 16U)) /*!< PCLK2 clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_0 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< SYSCLK clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL_1 >> RCC_CCIPR1_USART1SEL_Pos)) /*!< HSI clock used as USART1 clock source */ -#define LL_RCC_USART1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART1SEL_Pos << 16U) | (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< LSE clock used as USART1 clock source */ -#if defined(USART2) -#define LL_RCC_USART2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U)) /*!< PCLK1 clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_0 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< SYSCLK clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL_1 >> RCC_CCIPR1_USART2SEL_Pos)) /*!< HSI clock used as USART2 clock source */ -#define LL_RCC_USART2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART2SEL_Pos << 16U) | (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< LSE clock used as USART2 clock source */ -#endif /* USART2 */ -#define LL_RCC_USART3_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U)) /*!< PCLK3 clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_0 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< SYSCLK clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL_1 >> RCC_CCIPR1_USART3SEL_Pos)) /*!< HSI clock used as USART3 clock source */ -#define LL_RCC_USART3_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) |(RCC_CCIPR1_USART3SEL_Pos << 16U) | (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< LSE clock used as USART3 clock source */ -#if defined (RCC_CCIPR2_USART6SEL) -#define LL_RCC_USART6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U)) /*!< PCLK1 clock used as USART6 clock source */ -#define LL_RCC_USART6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_0 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< SYSCLK clock used as USART6 clock source */ -#define LL_RCC_USART6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL_1 >> RCC_CCIPR2_USART6SEL_Pos)) /*!< HSI clock used as USART6 clock source */ -#define LL_RCC_USART6_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< LSE clock used as USART6 clock source */ -/* Legacy define */ -#define LL_RCC_USART6_CLKSOURCE_PCLK2 LL_RCC_USART6_CLKSOURCE_PCLK1 -#endif /* RCC_CCIPR2_USART6SEL */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_UART_CLKSOURCE Peripheral UARTx clock source selection - * @{ - */ -#define LL_RCC_UART4_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART4SEL << 16U) /*!< PCLK1 clock used as UART4 clock source */ -#define LL_RCC_UART4_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */ -#define LL_RCC_UART4_CLKSOURCE_HSI ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL_1) /*!< HSI clock used as UART4 clock source */ -#define LL_RCC_UART4_CLKSOURCE_LSE ((RCC_CCIPR1_UART4SEL << 16U) | RCC_CCIPR1_UART4SEL) /*!< LSE clock used as UART4 clock source */ -#define LL_RCC_UART5_CLKSOURCE_PCLK1 (RCC_CCIPR1_UART5SEL << 16U) /*!< PCLK1 clock used as UART5 clock source */ -#define LL_RCC_UART5_CLKSOURCE_SYSCLK ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */ -#define LL_RCC_UART5_CLKSOURCE_HSI ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL_1) /*!< HSI clock used as UART5 clock source */ -#define LL_RCC_UART5_CLKSOURCE_LSE ((RCC_CCIPR1_UART5SEL << 16U) | RCC_CCIPR1_UART5SEL) /*!< LSE clock used as UART5 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LPUART_CLKSOURCE Peripheral LPUARTx clock source selection - * @{ - */ -#define LL_RCC_LPUART1_CLKSOURCE_PCLK3 0x00000000U /*!< PCLK3 clock used as LPUART1 clock source */ -#define LL_RCC_LPUART1_CLKSOURCE_SYSCLK RCC_CCIPR3_LPUART1SEL_0 /*!< SYSCLK clock used as LPUART1 clock source */ -#define LL_RCC_LPUART1_CLKSOURCE_HSI RCC_CCIPR3_LPUART1SEL_1 /*!< HSI clock used as LPUART1 clock source */ -#define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_CCIPR3_LPUART1SEL_0 | RCC_CCIPR3_LPUART1SEL_1) /*!< LSE clock used as LPUART1 clock source */ -#define LL_RCC_LPUART1_CLKSOURCE_MSIK RCC_CCIPR3_LPUART1SEL_2 /*!< MSIK clock used as LPUART1 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_I2C_CLKSOURCE Peripheral I2Cx clock source selection - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C1SEL_0 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< SYSCLK clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C1SEL_1 >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< HSI clock used as I2C1 clock source */ -#define LL_RCC_I2C1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< MSIK clock used as I2C1 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C2SEL_0 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< SYSCLK clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C2SEL_1 >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< HSI clock used as I2C2 clock source */ -#define LL_RCC_I2C2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< MSIK clock used as I2C2 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U)) /*!< PCLK3 clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ - (RCC_CCIPR3_I2C3SEL_0 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< SYSCLK clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ - (RCC_CCIPR3_I2C3SEL_1 >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< HSI clock used as I2C3 clock source */ -#define LL_RCC_I2C3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ - (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< MSIK clock used as I2C3 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C4SEL_0 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< SYSCLK clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C4SEL_1 >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< HSI clock used as I2C4 clock source */ -#define LL_RCC_I2C4_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< MSIK clock used as I2C4 clock source */ -#if defined (RCC_CCIPR2_I2C5SEL) -#define LL_RCC_I2C5_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C5 clock source */ -#define LL_RCC_I2C5_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C5SEL_0 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< SYSCLK clock used as I2C5 clock source */ -#define LL_RCC_I2C5_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C5SEL_1 >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< HSI clock used as I2C5 clock source */ -#define LL_RCC_I2C5_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< MSIK clock used as I2C5 clock source */ -#endif /* RCC_CCIPR2_I2C5SEL */ -#if defined (RCC_CCIPR2_I2C6SEL) -#define LL_RCC_I2C6_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U)) /*!< PCLK1 clock used as I2C6 clock source */ -#define LL_RCC_I2C6_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C6SEL_0 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< SYSCLK clock used as I2C6 clock source */ -#define LL_RCC_I2C6_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C6SEL_1 >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< HSI clock used as I2C6 clock source */ -#define LL_RCC_I2C6_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< MSIK clock used as I2C6 clock source */ -#endif /* RCC_CCIPR2_I2C6SEL */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SPI_CLKSOURCE Peripheral SPIx clock source selection - * @{ - */ -#define LL_RCC_SPI1_CLKSOURCE_PCLK2 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U)) /*!< PCLK2 clock used as SPI1 clock source */ -#define LL_RCC_SPI1_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI1SEL_0 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SYSCLK clock used as SPI1 clock source */ -#define LL_RCC_SPI1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI1SEL_1 >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< HSI clock used as SPI1 clock source */ -#define LL_RCC_SPI1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< MSIK clock used as SPI1 clock source */ -#define LL_RCC_SPI2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U)) /*!< PCLK1 clock used as SPI2 clock source */ -#define LL_RCC_SPI2_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI2SEL_0 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SYSCLK clock used as SPI2 clock source */ -#define LL_RCC_SPI2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI2SEL_1 >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< HSI clock used as SPI2 clock source */ -#define LL_RCC_SPI2_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< MSIK clock used as SPI2 clock source */ -#define LL_RCC_SPI3_CLKSOURCE_PCLK3 ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U)) /*!< PCLK3 clock used as SPI3 clock source */ -#define LL_RCC_SPI3_CLKSOURCE_SYSCLK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ - (RCC_CCIPR3_SPI3SEL_0 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SYSCLK clock used as SPI3 clock source */ -#define LL_RCC_SPI3_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ - (RCC_CCIPR3_SPI3SEL_1 >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< HSI clock used as SPI3 clock source */ -#define LL_RCC_SPI3_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ - (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< MSIK clock used as SPI3 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LPTIM_CLKSOURCE Peripheral LPTIMx clock source selection - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM1 clock source */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM1SEL_0 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSI clock used as LPTIM1 clock source */ -#define LL_RCC_LPTIM1_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM1SEL_1 >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< HSI clock used as LPTIM1 clock source */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LSE clock used as LPTIM1 clock source */ -#define LL_RCC_LPTIM2_CLKSOURCE_PCLK1 ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U)) /*!< PCLK1 clock used as LPTIM2 clock source */ -#define LL_RCC_LPTIM2_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ - (RCC_CCIPR1_LPTIM2SEL_0 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSI clock used as LPTIM2 clock source */ -#define LL_RCC_LPTIM2_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ - (RCC_CCIPR1_LPTIM2SEL_1 >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< HSI clock used as LPTIM2 clock source */ -#define LL_RCC_LPTIM2_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ - (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LSE clock used as LPTIM2 clock source */ -#define LL_RCC_LPTIM34_CLKSOURCE_MSIK ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U)) /*!< MSIK clock used as LPTIM34 clock source*/ -#define LL_RCC_LPTIM34_CLKSOURCE_LSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM34SEL_0 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSI clock used as LPTIM34 clock source */ -#define LL_RCC_LPTIM34_CLKSOURCE_HSI ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM34SEL_1 >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< HSI clock used as LPTIM34 clock source */ -#define LL_RCC_LPTIM34_CLKSOURCE_LSE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LSE clock used as LPTIM34 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN kernel clock source selection - * @{ - */ -#define LL_RCC_FDCAN_CLKSOURCE_HSE 0x00000000U /*!< HSE clock used as FDCAN kernel clock source */ -#define LL_RCC_FDCAN_CLKSOURCE_PLL1 RCC_CCIPR1_FDCANSEL_0 /*!< PLL1 Q clock used as FDCAN kernel clock source */ -#define LL_RCC_FDCAN_CLKSOURCE_PLL2 RCC_CCIPR1_FDCANSEL_1 /*!< PLL2 P clock used as FDCAN kernel clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SAI_CLKSOURCE Peripheral SAIx clock source selection - * @{ - */ -#define LL_RCC_SAI1_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI1SEL << 16U) /*!< PLL2 clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_0) /*!< PLL3 clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_1) /*!< PLL1 clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_HSI ((RCC_CCIPR2_SAI1SEL << 16U) | RCC_CCIPR2_SAI1SEL_2) /*!< HSI clock used as SAI1 clock source */ -#define LL_RCC_SAI1_CLKSOURCE_PIN ((RCC_CCIPR2_SAI1SEL << 16U) | (RCC_CCIPR2_SAI1SEL_1 | \ - RCC_CCIPR2_SAI1SEL_0)) /*!< External input clock used as SAI1 clock source */ -#if defined(SAI2) -#define LL_RCC_SAI2_CLKSOURCE_PLL2 (RCC_CCIPR2_SAI2SEL << 16U) /*!< PLL2 clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PLL3 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_0) /*!< PLL3 clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PLL1 ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_1) /*!< PLL1clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_HSI ((RCC_CCIPR2_SAI2SEL << 16U) | RCC_CCIPR2_SAI2SEL_2) /*!< HSI clock used as SAI2 clock source */ -#define LL_RCC_SAI2_CLKSOURCE_PIN ((RCC_CCIPR2_SAI2SEL << 16U) | (RCC_CCIPR2_SAI2SEL_1 | \ - RCC_CCIPR2_SAI2SEL_0)) /*!< External input clock used as SAI2 clock source */ -#endif /* SAI2 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SDMMC_KERNELCLKSOURCE Peripheral SDMMC1/2 kernel clock source selection - * @{ - */ -#define LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK 0x00000000U /*!< 48MHz clock from internal multiplexor used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 RCC_CCIPR2_SDMMCSEL /*!< PLL1 "P" used as SDMMC1/2 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SDMMC12_CLKSOURCE Peripheral SDMMC clock source selection - * @{ - */ -#define LL_RCC_SDMMC12_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as SDMMC1/2 clock source */ -#define LL_RCC_SDMMC12_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as SDMMC1/2 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection - * @{ - */ -#define LL_RCC_RNG_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as RNG clock source */ -#define LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 RCC_CCIPR2_RNGSEL_0 /*!< HSI48/2 clock used as RNG clock source */ -#define LL_RCC_RNG_CLKSOURCE_HSI RCC_CCIPR2_RNGSEL_1 /*!< HSI clock used as RNG clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection - * @{ - */ -#define LL_RCC_USB_CLKSOURCE_HSI48 0x00000000U /*!< HSI48 clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_PLL2 RCC_CCIPR1_ICLKSEL_0 /*!< PLL2 "Q" clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_PLL1 RCC_CCIPR1_ICLKSEL_1 /*!< PLL1 "Q" clock used as USB clock source */ -#define LL_RCC_USB_CLKSOURCE_MSIK RCC_CCIPR1_ICLKSEL /*!< MSIK clock used as USB clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_ADCDAC_CLKSOURCE Peripheral ADCx and DAC1 clock source selection - * @{ - */ -#define LL_RCC_ADCDAC_CLKSOURCE_HCLK 0x00000000U /*!< No clock used as ADCx/DAC1 clock source */ -#define LL_RCC_ADCDAC_CLKSOURCE_SYSCLK RCC_CCIPR3_ADCDACSEL_0 /*!< SYSCLK clock used as ADCx/DAC1 clock source */ -#define LL_RCC_ADCDAC_CLKSOURCE_PLL2 RCC_CCIPR3_ADCDACSEL_1 /*!< PLL2 clock used as ADCx/DAC1 clock source */ -#define LL_RCC_ADCDAC_CLKSOURCE_HSI RCC_CCIPR3_ADCDACSEL_2 /*!< HSI clock used as ADCx/DAC1 clock source */ -#define LL_RCC_ADCDAC_CLKSOURCE_HSE (RCC_CCIPR3_ADCDACSEL_1 | RCC_CCIPR3_ADCDACSEL_0) /*!< HSE clock used as ADCx/DAC1 clock source */ -#define LL_RCC_ADCDAC_CLKSOURCE_MSIK (RCC_CCIPR3_ADCDACSEL_2 | RCC_CCIPR3_ADCDACSEL_0) /*!< MSIK clock used as ADCx/DAC1 clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_DAC1_CLKSOURCE Peripheral DAC1 clock source selection - * @{ - */ -#define LL_RCC_DAC1_CLKSOURCE_LSE 0x00000000U /*!< LSE clock used as DAC1 clock */ -#define LL_RCC_DAC1_CLKSOURCE_LSI RCC_CCIPR3_DAC1SEL /*!< LSI clock used as DAC1 clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_ADF1_CLKSOURCE Peripheral ADF1 clock source selection - * @{ - */ -#define LL_RCC_ADF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as ADF1 clock */ -#define LL_RCC_ADF1_CLKSOURCE_PLL1 RCC_CCIPR3_ADF1SEL_0 /*!< PLL1 clock used as ADF1 clock */ -#define LL_RCC_ADF1_CLKSOURCE_PLL3 RCC_CCIPR3_ADF1SEL_1 /*!< PLL3 clock used as ADF1 clock */ -#define LL_RCC_ADF1_CLKSOURCE_MSIK RCC_CCIPR3_ADF1SEL_2 /*!< MSIK clock used as ADF1 clock */ -#define LL_RCC_ADF1_CLKSOURCE_PIN (RCC_CCIPR3_ADF1SEL_1 | RCC_CCIPR3_ADF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as ADF1 clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MDF1_CLKSOURCE Peripheral MDF1 clock source selection - * @{ - */ -#define LL_RCC_MDF1_CLKSOURCE_HCLK 0x00000000U /*!< HCLK clock used as MDF1 clock */ -#define LL_RCC_MDF1_CLKSOURCE_PLL1 RCC_CCIPR2_MDF1SEL_0 /*!< PLL1 clock used as MDF1 clock */ -#define LL_RCC_MDF1_CLKSOURCE_PLL3 RCC_CCIPR2_MDF1SEL_1 /*!< PLL3 clock used as MDF1 clock */ -#define LL_RCC_MDF1_CLKSOURCE_MSIK RCC_CCIPR2_MDF1SEL_2 /*!< MSIK clock used as MDF1 clock */ -#define LL_RCC_MDF1_CLKSOURCE_PIN (RCC_CCIPR2_MDF1SEL_1 | RCC_CCIPR2_MDF1SEL_0) /*!< PIN SAI1_EXTCLK clock used as MDF1 clock */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_OCTOSPI_CLKSOURCE Peripheral OCTOSPI kernel clock source selection - * @{ - */ -#define LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK 0x00000000U /*!< SYSCLK clock used as OctoSPI kernel clock source */ -#define LL_RCC_OCTOSPI_CLKSOURCE_MSIK RCC_CCIPR2_OCTOSPISEL_0 /*!< MSIK clock used as OctoSPI kernel clock source */ -#define LL_RCC_OCTOSPI_CLKSOURCE_PLL1 RCC_CCIPR2_OCTOSPISEL_1 /*!< PLL1 "Q" clock used as OctoSPI kernel clock source */ -#define LL_RCC_OCTOSPI_CLKSOURCE_PLL2 (RCC_CCIPR2_OCTOSPISEL_1|RCC_CCIPR2_OCTOSPISEL_0) /*!< PLL2 "Q" clock used as OctoSPI kernel clock source */ -/** - * @} - */ - -#if defined (HSPI1) -/** @defgroup RCC_LL_EC_HSPI1_CLKSOURCE Peripheral HSPI1 kernel clock source selection - * @{ - */ -#define LL_RCC_HSPI_CLKSOURCE_SYSCLK (0x00000000U) -#define LL_RCC_HSPI_CLKSOURCE_PLL1 RCC_CCIPR2_HSPISEL_0 -#define LL_RCC_HSPI_CLKSOURCE_PLL2 RCC_CCIPR2_HSPISEL_1 -#define LL_RCC_HSPI_CLKSOURCE_PLL3 RCC_CCIPR2_HSPISEL -/** - * @} - */ -#endif /* HSPI1 */ - -/** @defgroup RCC_LL_EC_TIM_INPUT_CAPTURE_CLOCKSource TIM Input capture clock source selection - * @{ - */ -#define LL_RCC_TIMIC_CLKSOURCE_NONE 0x00000000U /*!< No clock available for TIM16/TIM17 and LPTIM2 input capture */ -#define LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 RCC_CCIPR1_TIMICSEL_2 /*!< HSI/256 selected for TIM16/TIM17 and LPTIM2 input capture */ -#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 RCC_CCIPR1_TIMICSEL_2 /*!< MSIS/1024 selected for TIM16/TIM17 and LPTIM2 input capture */ -#define LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1) /*!< MSIS/4 selected for TIM16/TIM17 and LPTIM2 input capture */ -#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/4 selected for TIM16/TIM17 and LPTIM2 input capture */ -#define LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 (RCC_CCIPR1_TIMICSEL_2 | RCC_CCIPR1_TIMICSEL_1 | \ - RCC_CCIPR1_TIMICSEL_0) /*!< MSIK/1024 selected for TIM16/TIM17 and LPTIM2 input capture */ -/** - * @} - */ - - -#if defined(SAES) -/** @defgroup RCC_LL_EC_SAES_CLKSOURCE Peripheral SAES clock source selection - * @{ - */ -#define LL_RCC_SAES_CLKSOURCE_SHSI 0x00000000U /*!< SHSI clock used as SAES clock source */ -#define LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 RCC_CCIPR2_SAESSEL /*!< SHSI_DIV2 clock used as SAES clock source */ -/** - * @} - */ -#endif /* SAES */ - -/** @defgroup RCC_LL_EC_USART Peripheral USARTx get clock source - * @{ - */ -#define LL_RCC_USART1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART1SEL_Pos << 16U) | \ - (RCC_CCIPR1_USART1SEL >> RCC_CCIPR1_USART1SEL_Pos)) /*!< USART1 Clock source selection */ -#if defined(USART2) -#define LL_RCC_USART2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART2SEL_Pos << 16U) | \ - (RCC_CCIPR1_USART2SEL >> RCC_CCIPR1_USART2SEL_Pos)) /*!< USART2 Clock source selection */ -#endif /* USART2 */ -#define LL_RCC_USART3_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_USART3SEL_Pos << 16U) | \ - (RCC_CCIPR1_USART3SEL >> RCC_CCIPR1_USART3SEL_Pos)) /*!< USART3 Clock source selection */ -#if defined (RCC_CCIPR2_USART6SEL) -#define LL_RCC_USART6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_USART6SEL_Pos << 16U) | \ - (RCC_CCIPR2_USART6SEL >> RCC_CCIPR2_USART6SEL_Pos)) /*!< USART6 Clock source selection */ -#endif /* RCC_CCIPR2_USART6SEL */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_UART Peripheral UARTx get clock source - * @{ - */ -#define LL_RCC_UART4_CLKSOURCE RCC_CCIPR1_UART4SEL /*!< UART4 Clock source selection */ -#define LL_RCC_UART5_CLKSOURCE RCC_CCIPR1_UART5SEL /*!< UART5 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SPI Peripheral SPIx get clock source - * @{ - */ -#define LL_RCC_SPI1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI1SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI1SEL >> RCC_CCIPR1_SPI1SEL_Pos)) /*!< SPI1 Clock source selection */ -#define LL_RCC_SPI2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_SPI2SEL_Pos << 16U) | \ - (RCC_CCIPR1_SPI2SEL >> RCC_CCIPR1_SPI2SEL_Pos)) /*!< SPI2 Clock source selection */ -#define LL_RCC_SPI3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_SPI3SEL_Pos << 16U) | \ - (RCC_CCIPR3_SPI3SEL >> RCC_CCIPR3_SPI3SEL_Pos)) /*!< SPI3 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LPUART Peripheral LPUARTx get clock source - * @{ - */ -#define LL_RCC_LPUART1_CLKSOURCE RCC_CCIPR3_LPUART1SEL /*!< LPUART1 Clock source selection */ -/** - * @} - */ - -#if defined(DSI) -/** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection - * @{ - */ -#define LL_RCC_DSI_CLKSOURCE_PHY (RCC_CCIPR2_DSIHOSTSEL) -#define LL_RCC_DSI_CLKSOURCE_PLL3 (0x00000000U) -/** - * @} - */ -#endif /* DSI */ - -#if defined(LTDC) -/** @defgroup RCC_LL_EC_LTDC_CLKSOURCE Peripheral LTDC clock source selection - * @{ - */ -#define LL_RCC_LTDC_CLKSOURCE_PLL2 (RCC_CCIPR2_LTDCSEL) -#define LL_RCC_LTDC_CLKSOURCE_PLL3 (0x00000000U) -/** - * @} - */ -#endif /* LTDC */ - -#if defined (RCC_CCIPR2_USBPHYCSEL) -/** @defgroup RCC_LL_EC_USBPHY_CLKSOURCE Peripheral USBPHY clock source selection - * @{ - */ -#define LL_RCC_USBPHYCLKSOURCE_HSE (0x00000000U) /*!< HSE clock selected as USBPHYC clock */ -#define LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 RCC_CCIPR2_USBPHYCSEL_1 /*!< HSE clock divided by 2 selected as USBPHYC clock */ -#define LL_RCC_USBPHYCLKSOURCE_PLL1 RCC_CCIPR2_USBPHYCSEL_0 /*!< PLL1 divider P selected as USBPHYC clock */ -#define LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 (RCC_CCIPR2_USBPHYCSEL_1 | RCC_CCIPR2_USBPHYCSEL_0) /*!< PLL1 divider P divided by 2 selected as USBPHYC clock */ -/** - * @} - */ -#endif /* RCC_CCIPR2_USBPHYCSEL */ - -/** @defgroup RCC_LL_EC_I2C Peripheral I2Cx get clock source - * @{ - */ -#define LL_RCC_I2C1_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C1SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C1SEL >> RCC_CCIPR1_I2C1SEL_Pos)) /*!< I2C1 Clock source selection */ -#define LL_RCC_I2C2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C2SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C2SEL >> RCC_CCIPR1_I2C2SEL_Pos)) /*!< I2C2 Clock source selection */ -#define LL_RCC_I2C3_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_I2C3SEL_Pos << 16U) | \ - (RCC_CCIPR3_I2C3SEL >> RCC_CCIPR3_I2C3SEL_Pos)) /*!< I2C3 Clock source selection */ -#define LL_RCC_I2C4_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_I2C4SEL_Pos << 16U) | \ - (RCC_CCIPR1_I2C4SEL >> RCC_CCIPR1_I2C4SEL_Pos)) /*!< I2C4 Clock source selection */ -#if defined (RCC_CCIPR2_I2C5SEL) -#define LL_RCC_I2C5_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C5SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C5SEL >> RCC_CCIPR2_I2C5SEL_Pos)) /*!< I2C1 Clock source selection */ -#endif /* RCC_CCIPR2_I2C5SEL */ -#if defined (RCC_CCIPR2_I2C6SEL) -#define LL_RCC_I2C6_CLKSOURCE ((RCC_OFFSET_CCIPR2 << 24U) | (RCC_CCIPR2_I2C6SEL_Pos << 16U) | \ - (RCC_CCIPR2_I2C6SEL >> RCC_CCIPR2_I2C6SEL_Pos)) /*!< I2C1 Clock source selection */ -#endif /* RCC_CCIPR2_I2C6SEL */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIMx get clock source - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM1SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM1SEL >> RCC_CCIPR3_LPTIM1SEL_Pos)) /*!< LPTIM1 Clock source selection */ -#define LL_RCC_LPTIM2_CLKSOURCE ((RCC_OFFSET_CCIPR1 << 24U) | (RCC_CCIPR1_LPTIM2SEL_Pos << 16U) | \ - (RCC_CCIPR1_LPTIM2SEL >> RCC_CCIPR1_LPTIM2SEL_Pos)) /*!< LPTIM2 Clock source selection */ -#define LL_RCC_LPTIM34_CLKSOURCE ((RCC_OFFSET_CCIPR3 << 24U) | (RCC_CCIPR3_LPTIM34SEL_Pos << 16U) | \ - (RCC_CCIPR3_LPTIM34SEL >> RCC_CCIPR3_LPTIM34SEL_Pos)) /*!< LPTIM3 and LPTIM4 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SAI Peripheral SAIx get clock source - * @{ - */ -#define LL_RCC_SAI1_CLKSOURCE RCC_CCIPR2_SAI1SEL /*!< SAI1 Clock source selection */ -#if defined (SAI2) -#define LL_RCC_SAI2_CLKSOURCE RCC_CCIPR2_SAI2SEL /*!< SAI2 Clock source selection */ -#endif /* SAI2 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SDMMC_KERNEL Peripheral SDMMC get kernel clock source - * @{ - */ -#define LL_RCC_SDMMC_KERNELCLKSOURCE RCC_CCIPR2_SDMMCSEL /*!< SDMMC1/2 Kernel Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SDMMC1/2 Peripheral SDMMC get clock source - * @{ - */ -#define LL_RCC_SDMMC_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< SDMMC1/2 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source - * @{ - */ -#define LL_RCC_RNG_CLKSOURCE RCC_CCIPR2_RNGSEL /*!< RNG Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_USB Peripheral USB get clock source - * @{ - */ -#define LL_RCC_USB_CLKSOURCE RCC_CCIPR1_ICLKSEL /*!< USB Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_ADCDAC Peripheral ADCDAC get clock source - * @{ - */ -#define LL_RCC_ADCDAC_CLKSOURCE RCC_CCIPR3_ADCDACSEL /*!< ADCDACs Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MDF1 Peripheral MDF1 get clock source - * @{ - */ -#define LL_RCC_MDF1_CLKSOURCE RCC_CCIPR2_MDF1SEL /* MDF1 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_DAC1 Peripheral DAC1 get clock source - * @{ - */ -#define LL_RCC_DAC1_CLKSOURCE RCC_CCIPR3_DAC1SEL /* DAC1 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_ADF1 Peripheral ADF1 get clock source - * @{ - */ -#define LL_RCC_ADF1_CLKSOURCE RCC_CCIPR3_ADF1SEL /*!< ADF1 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get kernel clock source - * @{ - */ -#define LL_RCC_FDCAN_CLKSOURCE RCC_CCIPR1_FDCANSEL /*!< FDCAN Kernel Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_OCTOSPI Peripheral OCTOSPI get clock source - * @{ - */ -#define LL_RCC_OCTOSPI_CLKSOURCE RCC_CCIPR2_OCTOSPISEL /*!< OctoSPI Clock source selection */ -/** - * @} - */ -#if defined (HSPI1) -/** @defgroup RCC_LL_EC_HSPI Peripheral HSPI get clock source - * @{ - */ -#define LL_RCC_HSPI_CLKSOURCE RCC_CCIPR2_HSPISEL /*!< HSPI Clock source selection */ -/** - * @} - */ -#endif /* HSPI */ - -#if defined(SAES) -/** @defgroup RCC_LL_EC_SAES Peripheral SAES get clock source - * @{ - */ -#define LL_RCC_SAES_CLKSOURCE RCC_CCIPR2_SAESSEL /*!< SAES Clock source selection */ -/** - * @} - */ -#endif /* SAES */ - -#if defined(DSI) -/** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source - * @{ - */ -#define LL_RCC_DSI_CLKSOURCE RCC_CCIPR2_DSIHOSTSEL -/** - * @} - */ -#endif /* DSI */ - -#if defined(LTDC) -/** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source - * @{ - */ -#define LL_RCC_LTDC_CLKSOURCE RCC_CCIPR2_LTDCSEL -/** - * @} - */ -#endif /* LTDC */ - -#if defined (RCC_CCIPR2_USBPHYCSEL) -/** @defgroup RCC_LL_EC_USBPHY Peripheral USBPHY get clock source - * @{ - */ -#define LL_RCC_USBPHY_CLKSOURCE RCC_CCIPR2_USBPHYCSEL -/** - * @} - */ -#endif /* RCC_CCIPR2_USBPHYCSEL */ - -/** @defgroup RCC_LL_EC_PLL1SOURCE PLL1 entry clock source - * @{ - */ -#define LL_RCC_PLL1SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL1 entry clock source */ -#define LL_RCC_PLL1SOURCE_MSIS RCC_PLL1CFGR_PLL1SRC_0 /*!< MSIS clock selected as main PLL1 entry clock source */ -#define LL_RCC_PLL1SOURCE_HSI RCC_PLL1CFGR_PLL1SRC_1 /*!< HSI clock selected as main PLL1 entry clock source */ -#define LL_RCC_PLL1SOURCE_HSE (RCC_PLL1CFGR_PLL1SRC_0 | RCC_PLL1CFGR_PLL1SRC_1) /*!< HSE clock selected as main PLL1 entry clock source */ - -#define LL_RCC_PLLSOURCE_NONE LL_RCC_PLL1SOURCE_NONE /*!< alias define for compatibility with legacy code */ -#define LL_RCC_PLLSOURCE_MSIS LL_RCC_PLL1SOURCE_MSIS /*!< alias define for compatibility with legacy code */ -#define LL_RCC_PLLSOURCE_HSI LL_RCC_PLL1SOURCE_HSI /*!< alias define for compatibility with legacy code */ -#define LL_RCC_PLLSOURCE_HSE LL_RCC_PLL1SOURCE_HSE /*!< alias define for compatibility with legacy code */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input ranges - * @{ - */ -#define LL_RCC_PLLINPUTRANGE_4_8 0x00000000U /*!< VCO input range: 4 to 8 MHz */ -#define LL_RCC_PLLINPUTRANGE_8_16 RCC_PLL1CFGR_PLL1RGE /*!< VCO input range: 8 to 16 MHz */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL2SOURCE PLL2 entry clock source - * @{ - */ -#define LL_RCC_PLL2SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL2 entry clock source */ -#define LL_RCC_PLL2SOURCE_MSIS RCC_PLL2CFGR_PLL2SRC_0 /*!< MSIS clock selected as main PLL2 entry clock source */ -#define LL_RCC_PLL2SOURCE_HSI RCC_PLL2CFGR_PLL2SRC_1 /*!< HSI clock selected as main PLL2 entry clock source */ -#define LL_RCC_PLL2SOURCE_HSE (RCC_PLL2CFGR_PLL2SRC_0 | RCC_PLL2CFGR_PLL2SRC_1) /*!< HSE clock selected as main PLL2 entry clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_PLL3SOURCE PLL3 entry clock source - * @{ - */ -#define LL_RCC_PLL3SOURCE_NONE 0x00000000U /*!< No clock selected as main PLL3 entry clock source */ -#define LL_RCC_PLL3SOURCE_MSIS RCC_PLL3CFGR_PLL3SRC_0 /*!< MSIS clock selected as main PLL3 entry clock source */ -#define LL_RCC_PLL3SOURCE_HSI RCC_PLL3CFGR_PLL3SRC_1 /*!< HSI clock selected as main PLL3 entry clock source */ -#define LL_RCC_PLL3SOURCE_HSE (RCC_PLL3CFGR_PLL3SRC_0 | RCC_PLL3CFGR_PLL3SRC_1) /*!< HSE clock selected as main PLL3 entry clock source */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MSIRANGESEL MSI clock range selection - * @{ - */ -#define LL_RCC_MSIRANGESEL_STANDBY 0U /*!< MSI Range is provided by MSISRANGE */ -#define LL_RCC_MSIRANGESEL_RUN 1U /*!< MSI Range is provided by MSISRANGE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Security_Services Security Services - * @note Only available when system implements security (TZEN=1) - * @{ - */ -#define LL_RCC_ALL_NSEC 0U /*!< No security on RCC resources (default) */ -#define LL_RCC_ALL_SEC RCC_SECURE_MASK /*!< Security on all RCC resources */ - -#define LL_RCC_HSI_SEC RCC_SECCFGR_HSISEC /*!< HSI clock configuration security */ -#define LL_RCC_HSI_NSEC 0U /*!< HSI clock configuration secure/non-secure access */ -#define LL_RCC_HSE_SEC RCC_SECCFGR_HSESEC /*!< HSE clock configuration security */ -#define LL_RCC_HSE_NSEC 0U /*!< HSE clock configuration secure/non-secure access */ -#define LL_RCC_MSI_SEC RCC_SECCFGR_MSISEC /*!< MSI clock configuration security */ -#define LL_RCC_MSI_NSEC 0U /*!< MSI clock configuration secure/non-secure access */ -#define LL_RCC_LSE_SEC RCC_SECCFGR_LSESEC /*!< LSE clock configuration security */ -#define LL_RCC_LSE_NSEC 0U /*!< LSE clock configuration secure/non-secure access */ -#define LL_RCC_LSI_SEC RCC_SECCFGR_LSISEC /*!< LSI clock configuration security */ -#define LL_RCC_LSI_NSEC 0U /*!< LSI clock configuration secure/non-secure access */ -#define LL_RCC_SYSCLK_SEC RCC_SECCFGR_SYSCLKSEC /*!< SYSCLK clock; STOPWUCK and MCO output configuration security */ -#define LL_RCC_SYSCLK_NSEC 0U /*!< SYSCLK clock; STOPWUCK and MCO output configuration secure/non-secure access */ -#define LL_RCC_PRESCALERS_SEC RCC_SECCFGR_PRESCSEC /*!< AHBx/APBx prescaler configuration security */ -#define LL_RCC_PRESCALERS_NSEC 0U /*!< AHBx/APBx prescaler configuration secure/non-secure access */ -#define LL_RCC_PLL1_SEC RCC_SECCFGR_PLL1SEC /*!< PLL1 clock configuration security */ -#define LL_RCC_PLL1_NSEC 0U /*!< main PLL1 clock configuration secure/non-secure access */ -#define LL_RCC_PLL2_SEC RCC_SECCFGR_PLL2SEC /*!< PLL2 clock configuration security */ -#define LL_RCC_PLL2_NSEC 0U /*!< main PLL2 clock configuration secure/non-secure access */ -#define LL_RCC_PLL3_SEC RCC_SECCFGR_PLL3SEC /*!< PLL3 clock configuration security */ -#define LL_RCC_PLL3_NSEC 0U /*!< main PLL3 clock configuration secure/non-secure access */ -#define LL_RCC_ICLK_SEC RCC_SECCFGR_ICLKSEC /*!< ICLK clock source selection security */ -#define LL_RCC_ICLK_NSEC 0U /*!< ICLK clock source selection secure/non-secure access */ -#define LL_RCC_HSI48_SEC RCC_SECCFGR_HSI48SEC /*!< HSI48 clock configuration security */ -#define LL_RCC_HSI48_NSEC 0U /*!< HSI48 clock configuration secure/non-secure access */ -#define LL_RCC_RESET_FLAGS_SEC RCC_SECCFGR_RMVFSEC /*!< Remove reset flag security */ -#define LL_RCC_RESET_FLAGS_NSEC 0U - -#define LL_RCC_PLL_SEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ -#define LL_RCC_PLL_NSEC LL_RCC_PLL1_NSEC /*!< alias define for compatibility with legacy code */ -#define LL_RCC_CLK48M_SEC LL_RCC_ICLK_SEC /*!< alias define for compatibility with legacy code */ -#define LL_RCC_CLK48M_NSEC LL_RCC_ICLK_NSEC /*!< alias define for compatibility with legacy code */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ - -/** - * @brief Helper macro to calculate the PLL1CLK frequency on system domain - * @note ex: @ref __LL_RCC_CALC_PLL1CLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), - * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetR ()); - * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) - * @param __PLL1M__ parameter can be a value between 1 and 16 - * @param __PLL1N__ parameter can be a value between 4 and 512 - * @param __PLL1R__ parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) - * @retval PLL1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL1CLK_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1R__) ((((__INPUTFREQ__) /(__PLL1M__)) * \ - (__PLL1N__)) / (__PLL1R__)) -#define __LL_RCC_CALC_PLLCLK_FREQ __LL_RCC_CALC_PLL1CLK_FREQ /*!< alias for compatibility with legacy code */ - -/** - * @brief Helper macro to calculate the PLL1CLK frequency used on SAI domain - * @note ex: @ref __LL_RCC_CALC_PLL1CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), - * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetP ()); - * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) - * @param __PLL1M__ parameter can be a value between 1 and 16 - * @param __PLL1N__ parameter can be a value between 4 and 512 - * @param __PLL1P__ parameter can be a value between 1 and 128 - * @retval PLL1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL1CLK_SAI_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1P__) ((((__INPUTFREQ__) \ - /(__PLL1M__)) * (__PLL1N__)) / (__PLL1P__)) -#define __LL_RCC_CALC_PLLCLK_SAI_FREQ __LL_RCC_CALC_PLL1CLK_SAI_FREQ /*!< alias for compatibility with legacy code */ - -/** - * @brief Helper macro to calculate the PLL1CLK frequency used on 48M domain - * @note ex: @ref __LL_RCC_CALC_PLL1CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL1_GetDivider (), - * @ref LL_RCC_PLL1_GetN (), @ref LL_RCC_PLL1_GetQ ()); - * @param __INPUTFREQ__ PLL1 Input frequency (based on MSI/HSE/HSI) - * @param __PLL1M__ parameter can be a value between 1 and 16 - * @param __PLL1N__ parameter can be a value between 4 and 512 - * @param __PLL1Q__ parameter can be a value between 1 and 128 - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL1CLK_48M_FREQ(__INPUTFREQ__, __PLL1M__, __PLL1N__, __PLL1Q__) ((((__INPUTFREQ__) \ - /(__PLL1M__)) * (__PLL1N__)) / (__PLL1Q__)) -#define __LL_RCC_CALC_PLLCLK_48M_FREQ __LL_RCC_CALC_PLL1CLK_48M_FREQ /*!< alias for compatibility with legacy code */ - -/** - * @brief Helper macro to calculate the PLL2 frequency used for SAI domain - * @note ex: @ref __LL_RCC_CALC_PLL2CLK_SAI_FREQ (HSE_ALUE,@ref LL_RCC_PLL2_GetDivider (), - * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetP ()); - * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) - * @param __PLL2M__ parameter can be a value between 1 and 16 - * @param __PLL2N__ parameter can be a value between 4 and 512 - * @param __PLL2P__ parameter can be a value between 1 and 128 - * @retval PLL2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL2CLK_SAI_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2P__) ((((__INPUTFREQ__) \ - /(__PLL2M__)) * (__PLL2N__)) / (__PLL2P__)) - -/** - * @brief Helper macro to calculate the PLL2 frequency used on 48M domain - * @note ex: @ref __LL_RCC_CALC_PLL2CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (), - * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetQ ()); - * @param __INPUTFREQ__ PLL Input frequency (based on MSI/HSE/HSI) - * @param __PLL2M__ parameter can be a value between 1 and 16 - * @param __PLL2N__ parameter can be a value between 4 and 512 - * @param __PLL2Q__ parameter can be a value between 1 and 128 - * @retval PLL2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL2CLK_48M_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2Q__) ((((__INPUTFREQ__) \ - /(__PLL2M__)) * (__PLL2N__)) / (__PLL2Q__)) - -/** - * @brief Helper macro to calculate the PLL2 frequency used on ADC domain - * @note ex: @ref __LL_RCC_CALC_PLL2CLK_ADC_FREQ (HSE_VALUE,@ref LL_RCC_PLL2_GetDivider (), - * @ref LL_RCC_PLL2_GetN (), @ref LL_RCC_PLL2_GetR ()); - * @param __INPUTFREQ__ PLL2 Input frequency (based on MSI/HSE/HSI) - * @param __PLL2M__ parameter can be a value between 1 and 16 - * @param __PLL2N__ parameter can be a value between 4 and 512 - * @param __PLL2R__ parameter can be a value between 1 and 128 - * @retval PLL2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL2CLK_ADC_FREQ(__INPUTFREQ__, __PLL2M__, __PLL2N__, __PLL2R__) ((((__INPUTFREQ__) \ - /(__PLL2M__)) * (__PLL2N__)) / (__PLL2R__)) - -/** - * @brief Helper macro to calculate the PLL3 frequency used for SAI domain - * @note ex: @ref __LL_RCC_CALC_PLL3CLK_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), - * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetP ()); - * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) - * @param __PLL3M__ parameter can be a value between 1 and 16 - * @param __PLL3N__ parameter can be a value between 4 and 512 - * @param __PLL3P__ parameter can be a value between 1 and 128 - * @retval PLL3 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL3CLK_SAI_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3P__)((((__INPUTFREQ__) \ - /(__PLL3M__)) * (__PLL3N__)) / (__PLL3P__)) - -/** - * @brief Helper macro to calculate the PLL2 frequency used on 48M domain - * @note ex: @ref __LL_RCC_CALC_PLL3CLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), - * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); - * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) - * @param __PLL3M__ parameter can be a value between 1 and 16 - * @param __PLL3N__ parameter can be a value between 4 and 512 - * @param __PLL3Q__ parameter can be a value between 1 and 128 - * @retval PLL3 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL3CLK_48M_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3Q__) ((((__INPUTFREQ__) \ - /(__PLL3M__)) * (__PLL3N__)) / (__PLL3Q__)) - -#if defined(HSPI1) || defined(LTDC) -/** - * @brief Helper macro to calculate the PLL3 frequency used on HSPI domain - * @note ex: @ref __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL3_GetDivider (), - * @ref LL_RCC_PLL3_GetN (), @ref LL_RCC_PLL3_GetQ ()); - * @param __INPUTFREQ__ PLL3 Input frequency (based on MSI/HSE/HSI) - * @param __PLL3M__ parameter can be a value between 1 and 16 - * @param __PLL3N__ parameter can be a value between 4 and 512 - * @param __PLL3R__ parameter can be a value between 1 and 128 - * @retval PLL3 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ(__INPUTFREQ__, __PLL3M__, __PLL3N__, __PLL3R__) ((((__INPUTFREQ__) \ - /(__PLL3M__)) * (__PLL3N__)) / (__PLL3R__)) -/* Legacy define */ -#define __LL_RCC_CALC_PLL3CLK_HSPI_FREQ __LL_RCC_CALC_PLL3CLK_HSPI_LTDC_FREQ -#endif /* HSPI1 || LTDC */ - -/** - * @brief Helper macro to calculate the HCLK frequency - * @param __SYSCLKFREQ__ SYSCLK frequency (based on MSI/HSE/HSI/PLLCLK) - * @param __AHBPRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> \ - AHBPrescTable[((__AHBPRESCALER__)& RCC_CFGR2_HPRE) \ - >> RCC_CFGR2_HPRE_Pos]) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (ABP1) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> \ - (APBPrescTable[((__APB1PRESCALER__)& \ - RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos])) - -/** - * @brief Helper macro to calculate the PCLK2 frequency (ABP2) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB2PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval PCLK2 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >>\ - APBPrescTable[(__APB2PRESCALER__) >> \ - RCC_CFGR2_PPRE2_Pos]) - -/** - * @brief Helper macro to calculate the PCLK3 frequency (ABP3) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB3PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB3_DIV_1 - * @arg @ref LL_RCC_APB3_DIV_2 - * @arg @ref LL_RCC_APB3_DIV_4 - * @arg @ref LL_RCC_APB3_DIV_8 - * @arg @ref LL_RCC_APB3_DIV_16 - * @retval PCLK3 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> \ - APBPrescTable[(__APB3PRESCALER__) >> \ - RCC_CFGR3_PPRE3_Pos]) - -/** - * @brief Helper macro to calculate the MSIS frequency (in Hz) - * @note __MSISSEL__ can be retrieved thanks to function LL_RCC_MSI_IsEnabledRangeSelect() - * @note if __MSISSEL__ is equal to LL_RCC_MSIRANGESEL_STANDBY, - * __MSISRANGE__can be retrieved by LL_RCC_MSI_GetRangeAfterStandby() - * else by LL_RCC_MSI_GetRange() - * ex: __LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), - * (LL_RCC_MSI_IsEnabledRangeSelect()? - * LL_RCC_MSI_GetRange(): - * LL_RCC_MSI_GetRangeAfterStandby())) - * @param __MSISSEL__ This parameter can be one of the following values: - * @arg @ref LL_RCC_MSIRANGESEL_STANDBY - * @arg @ref LL_RCC_MSIRANGESEL_RUN - * @param __MSISRANGE__ This parameter can be one of the following values: - * @arg @ref LL_RCC_MSISRANGE_0 - * @arg @ref LL_RCC_MSISRANGE_1 - * @arg @ref LL_RCC_MSISRANGE_2 - * @arg @ref LL_RCC_MSISRANGE_3 - * @arg @ref LL_RCC_MSISRANGE_4 - * @arg @ref LL_RCC_MSISRANGE_5 - * @arg @ref LL_RCC_MSISRANGE_6 - * @arg @ref LL_RCC_MSISRANGE_7 - * @arg @ref LL_RCC_MSISRANGE_8 - * @arg @ref LL_RCC_MSISRANGE_9 - * @arg @ref LL_RCC_MSISRANGE_10 - * @arg @ref LL_RCC_MSISRANGE_11 - * @arg @ref LL_RCC_MSISRANGE_12 - * @arg @ref LL_RCC_MSISRANGE_13 - * @arg @ref LL_RCC_MSISRANGE_14 - * @arg @ref LL_RCC_MSISRANGE_15 - * @retval MSI clock frequency (in Hz) - */ -#define __LL_RCC_CALC_MSIS_FREQ(__MSISSEL__, __MSISRANGE__) (((__MSISSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \ - (MSIRangeTable[((__MSISRANGE__) >> 28U) & 0x0FU]) : \ - (MSIRangeTable[((__MSISRANGE__) >> 12U) & 0x0FU])) - - -/** - * @brief Helper macro to calculate the MSIK frequency (in Hz) - * @note __MSIKSEL__ can be retrieved thanks to function LL_RCC_MSIK_IsEnabledRangeSelect() - * @note if __MSIKSEL__ is equal to LL_RCC_MSIKRANGESEL_STANDBY, - * __MSIKRANGE__can be retrieved by LL_RCC_MSIK_GetRangeAfterStandby() - * else by LL_RCC_MSIK_GetRange() - * ex: __LL_RCC_CALC_MSIK_FREQ(LL_RCC_MSIK_IsEnabledRangeSelect(), - * (LL_RCC_MSIK_IsEnabledRangeSelect()? - * LL_RCC_MSIK_GetRange(): - * LL_RCC_MSIK_GetRangeAfterStandby())) - * @param __MSIKSEL__ This parameter can be one of the following values: - * @arg @ref LL_RCC_MSIRANGESEL_STANDBY - * @arg @ref LL_RCC_MSIRANGESEL_RUN - * @param __MSIKRANGE__ This parameter can be one of the following values: - * @arg @ref LL_RCC_MSIKRANGE_0 - * @arg @ref LL_RCC_MSIKRANGE_1 - * @arg @ref LL_RCC_MSIKRANGE_2 - * @arg @ref LL_RCC_MSIKRANGE_3 - * @arg @ref LL_RCC_MSIKRANGE_4 - * @arg @ref LL_RCC_MSIKRANGE_5 - * @arg @ref LL_RCC_MSIKRANGE_6 - * @arg @ref LL_RCC_MSIKRANGE_7 - * @arg @ref LL_RCC_MSIKRANGE_8 - * @arg @ref LL_RCC_MSIKRANGE_9 - * @arg @ref LL_RCC_MSIKRANGE_10 - * @arg @ref LL_RCC_MSIKRANGE_11 - * @arg @ref LL_RCC_MSIKRANGE_12 - * @arg @ref LL_RCC_MSIKRANGE_13 - * @arg @ref LL_RCC_MSIKRANGE_14 - * @arg @ref LL_RCC_MSIKRANGE_15 - * @retval MSIK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_MSIK_FREQ(__MSIKSEL__, __MSIKRANGE__) (((__MSIKSEL__) == LL_RCC_MSIRANGESEL_RUN) ? \ - (MSIRangeTable[((__MSIKRANGE__) >> 24U) & 0x0FU]) : \ - (MSIRangeTable[((__MSIKRANGE__) >> 8U) & 0x0FU])) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == RCC_CR_HSERDY) ? 1UL : 0UL); -} - -/** - * @brief Set external HSE clock mode - * @note This bit can be written only if the HSE oscillator is disabled - * @rmtoll CR HSEEXT LL_RCC_HSE_SetClockMode - * @param HSEMode This parameter can be one of the following values: - * @arg @ref LL_RCC_HSE_ANALOG_MODE - * @arg @ref LL_RCC_HSE_DIGITAL_MODE - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_SetClockMode(uint32_t HSEMode) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSEEXT, HSEMode); -} - -/** - * @brief Get External HSE clock mode - * @rmtoll CR HSEEXT LL_RCC_HSE_GetClockMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_HSE_ANALOG_MODE - * @arg @ref LL_RCC_HSE_DIGITAL_MODE - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_GetClockMode(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSEEXT)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI even in stop mode - * @note HSI oscillator is forced ON even in Stop mode - * @rmtoll CR HSIKERON LL_RCC_HSI_EnableInStopMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_EnableInStopMode(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSIKERON); -} - -/** - * @brief Disable HSI in stop mode - * @rmtoll CR HSIKERON LL_RCC_HSI_DisableInStopMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_DisableInStopMode(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON); -} - -/** - * @brief Check if HSI is enabled in stop mode - * @rmtoll CR HSIKERON LL_RCC_HSI_IsEnabledInStopMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsEnabledInStopMode(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_HSIKERON) == RCC_CR_HSIKERON) ? 1UL : 0UL); -} - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RCC_CR_HSIRDY) ? 1UL : 0UL); -} - -/** - * @brief Get HSI Calibration value - * @note When HSITRIM is written, HSICAL is updated with the sum of - * HSITRIM and the factory trim value - * @rmtoll ICSCR3 HSICAL LL_RCC_HSI_GetCalibration - * @retval Between Min_Data = 0 and Max_Data = 127 - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSICAL) >> RCC_ICSCR3_HSICAL_Pos); -} - -/** - * @brief Set HSI Calibration trimming - * @note user-programmable trimming value that is added to the HSICAL - * @note Default value is 64, which, when added to the HSICAL value, - * should trim the HSI to 16 MHz +/- 1 % - * @rmtoll ICSCR3 HSITRIM LL_RCC_HSI_SetCalibTrimming - * @param Value Between Min_Data = 0 and Max_Data = 127 - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->ICSCR3, RCC_ICSCR3_HSITRIM, Value << RCC_ICSCR3_HSITRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll ICSC3R HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0 and Max_Data = 127 - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR3, RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI48 HSI48 - * @{ - */ - -/** - * @brief Enable HSI48 - * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI48_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSI48ON); -} - -/** - * @brief Disable HSI48 - * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI48_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON); -} - -/** - * @brief Check if HSI48 oscillator Ready - * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == RCC_CR_HSI48RDY) ? 1UL : 0UL); -} - -/** - * @brief Get HSI48 Calibration value - * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration - * @retval Between Min_Data = 0x00 and Max_Data = 0x1FF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void) -{ - return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Set LSE oscillator drive capability - * @note The oscillator is in Xtal mode when it is not in bypass mode. - * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability - * @param LSEDrive This parameter can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); -} - -/** - * @brief Get LSE oscillator drive capability - * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH - * @arg @ref LL_RCC_LSEDRIVE_HIGH - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV)); -} - -/** - * @brief Enable Clock security system on LSE. - * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); -} - -/** - * @brief Disable Clock security system on LSE. - * @note Clock security system can be disabled only after a LSE - * failure detection. In that case it MUST be disabled by software. - * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); -} - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == RCC_BDCR_LSERDY) ? 1UL : 0UL); -} - -/** - * @brief Enable LSE oscillator propagation for system clock - * @rmtoll BDCR LSESYSEN LL_RCC_LSE_EnablePropagation - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnablePropagation(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); -} - -/** - * @brief Check if LSESYS oscillator Ready - * @rmtoll BDCR LSESYSRDY LL_RCC_LSESYS_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSESYS_IsReady(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL); -} - -/** - * @brief Disable LSE oscillator propagation for system clock - * @rmtoll BDCR LSESYSEN LL_RCC_LSE_DisablePropagation - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisablePropagation(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); -} - -/** - * @brief Check if LSE oscillator propagation for system clock Ready - * @rmtoll BDCR LSESYSRDY LL_RCC_LSE_IsPropagationReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsPropagationReady(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == RCC_BDCR_LSESYSRDY) ? 1UL : 0UL); -} - -/** - * @brief Check if CSS on LSE failure Detection - * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == RCC_BDCR_LSECSSD) ? 1UL : 0UL); -} - -/** - * @brief Enable LSE clock glitch filter. - * @note The glitches on LSE can be filtred by setting the LSEGFON. - * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). - * @rmtoll BDCR LSEGFON LL_RCC_LSE_EnableGlitchFilter - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableGlitchFilter(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); -} - -/** - * @brief Disable LSE clock glitch filter. - * @note LSEGFON must be written when the LSE is disabled (LSEON = 0 and LSERDY = 0). - * @rmtoll BDCR LSEGFON LL_RCC_LSE_DisableGlitchFilter - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableGlitchFilter(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEGFON); -} - -/** - * @brief Check if LSE clock glitch filter is enabled - * @rmtoll BDCR LSEGFON LL_RCC_LSE_IsGlitchFilterEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsGlitchFilterEnabled(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSEGFON) == RCC_BDCR_LSEGFON) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll BDCR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll BDCR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll BDCR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) ? 1UL : 0UL); -} - -/** - * @brief Set LSI prescaler - * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_SetPrescaler - * @param LSIPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_LSI_DIV_1 - * @arg @ref LL_RCC_LSI_DIV_128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_SetPrescaler(uint32_t LSIPrescaler) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, LSIPrescaler); -} - -/** - * @brief Get LSI prescaler - * @rmtoll BDCR LSIPREDIV LL_RCC_LSI_GetPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSI_DIV_1 - * @arg @ref LL_RCC_LSI_DIV_128 - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_GetPrescaler(void) -{ - return (READ_BIT(RCC->BDCR, RCC_BDCR_LSIPREDIV)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MSIK MSIK - * @{ - */ - -/** - * @brief Enable MSIK oscillator - * @rmtoll CR MSIKON LL_RCC_MSIK_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIK_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIKON); -} - -/** - * @brief Disable MSIK oscillator - * @rmtoll CR MSIKON LL_RCC_MSIK_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIK_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIKON); -} - -/** - * @brief Check if MSIK oscillator Ready - * @rmtoll CR MSIKRDY LL_RCC_MSIK_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_MSIK_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == RCC_CR_MSIKRDY) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_SHSI SHSI - * @{ - */ - -/** - * @brief Enable SHSI oscillator - * @rmtoll CR SHSION LL_RCC_SHSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_SHSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_SHSION); -} - -/** - * @brief Disable SHSI oscillator - * @rmtoll CR SHSION LL_RCC_SHSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_SHSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_SHSION); -} - -/** - * @brief Check if SHSI oscillator Ready - * @rmtoll CR SHSIRDY LL_RCC_SHSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_SHSI_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == RCC_CR_SHSIRDY) ? 1UL : 0UL); -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MSI MSI - * @{ - */ - -/** - * @brief Enable MSIS oscillator - * @rmtoll CR MSISON LL_RCC_MSIS_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIS_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSISON); -} -#define LL_RCC_MSI_Enable LL_RCC_MSIS_Enable /*!< alias define for compatibility with legacy code */ - -/** - * @brief Disable MSIS oscillator - * @rmtoll CR MSISON LL_RCC_MSIS_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIS_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSISON); -} -#define LL_RCC_MSI_Disable LL_RCC_MSIS_Disable /*!< alias define for compatibility with legacy code */ - -/** - * @brief Check if MSIS oscillator Ready - * @rmtoll CR MSISRDY LL_RCC_MSIS_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_MSIS_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_MSISRDY) == RCC_CR_MSISRDY) ? 1UL : 0UL); -} -#define LL_RCC_MSI_IsReady LL_RCC_MSIS_IsReady /*!< alias define for compatibility with legacy code */ - -/** - * @brief Enable MSI PLL-mode (Hardware auto calibration with LSE) - * @note MSIPLLEN must be enabled after LSE is enabled (LSEON enabled) - * and ready (LSERDY set by hardware) - * @note hardware protection to avoid enabling MSIPLLEN if LSE is not - * ready - * @rmtoll CR MSIPLLEN LL_RCC_MSI_EnablePLLMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSI_EnablePLLMode(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); -} - -/** - * @brief Disable MSI-PLL mode - * @note cleared by hardware when LSE is disabled (LSEON = 0) or when - * the Clock Security System on LSE detects a LSE failure - * @rmtoll CR MSIPLLEN LL_RCC_MSI_DisablePLLMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSI_DisablePLLMode(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); -} - -/** - * @brief Check if MSI-PLL mode has been enabled or not - * @rmtoll CR MSIPLLEN LL_RCC_IsEnabledPLLMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledPLLMode(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) ? 1UL : 0UL); -} - -/** - * @brief Set clock source in PLL mode - * @rmtoll CR MSIPLLSEL LL_RCC_SetMSIPLLMode - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLMODE_MSIS - * @arg @ref LL_RCC_PLLMODE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetMSIPLLMode(uint32_t Source) -{ - MODIFY_REG(RCC->CR, RCC_CR_MSIPLLSEL, Source); -} - -/** - * @brief Get Clock source in PLL Mode - * @rmtoll CR MSIPLLSEL LL_RCC_GetMSIPLLMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLMODE_MSIS - * @arg @ref LL_RCC_PLLMODE_MSIK - */ -__STATIC_INLINE uint32_t LL_RCC_GetMSIPLLMode(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIPLLSEL)); -} - -/** - * @brief Enable MSI fast mode - * @rmtoll CR MSIPLLFAST LL_RCC_Enable_MSIPLLFAST - * @note This bit is used only if PLL mode is selected. - */ -__STATIC_INLINE void LL_RCC_Enable_MSIPLLFAST(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST); -} - -/** - * @brief Disable MSI fast mode - * @rmtoll CR MSIPLLFAST LL_RCC_Disable_MSIPLLFAST - * @note This bit is used only if PLL mode is selected. - */ -__STATIC_INLINE void LL_RCC_Disable_MSIPLLFAST(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST); -} - -/** - * @brief Check if MSI PLL Fast Mode is enable - * @rmtoll CR MSIPLLFAST LL_RCC_MSI_IsEnabledMSIPLLFAST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledMSIPLLFAST(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_MSIPLLFAST) == RCC_CR_MSIPLLFAST) ? 1UL : 0UL); -} - -/** - * @brief Set MSI Bias mode - * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_SetMSIBiasMode - * @param BiasMode This parameter can be one of the following values: - * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS - * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING - - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSI_SetMSIBiasMode(uint32_t BiasMode) -{ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS, BiasMode); -} - -/** - * @brief Get MSI Bias mode - * @rmtoll ICSCR1 MSIBIAS LL_RCC_MSI_GetMSIBiasMode - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MSIBIASMODE_CONTINUOUS - * @arg @ref LL_RCC_MSIBIASMODE_SAMPLING - - */ -__STATIC_INLINE uint32_t LL_RCC_MSI_GetMSIBiasMode(void) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIBIAS)); -} - -/** - * @brief Enable MSIK even in stop mode - * @note MSIK oscillator is forced ON even in Stop mode - * @rmtoll CR MSIKERON LL_RCC_MSIK_EnableInStopMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIK_EnableInStopMode(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIKERON); -} - -/** - * @brief Disable MSIK in stop mode - * @rmtoll CR MSIKERON LL_RCC_MSIK_DisableInStopMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIK_DisableInStopMode(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIKERON); -} - -/** - * @brief Check if MSIK is enabled in stop mode - * @rmtoll CR MSIKERON LL_RCC_MSIK_IsEnabledInStopMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_MSIK_IsEnabledInStopMode(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_MSIKERON) == RCC_CR_MSIKERON) ? 1UL : 0UL); -} - -/** - * @brief Enable MSI clock range selection with MSIRANGE register - * @note Write 0 has no effect. After a standby or a reset - * MSIRGSEL is at 0 and the MSI range value is provided by - * MSISRANGE - * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_EnableRangeSelection - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSI_EnableRangeSelection(void) -{ - SET_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL); -} - -/** - * @brief Check if MSI clock range is selected with MSIRANGE register - * @rmtoll ICSCR1 MSIRGSEL LL_RCC_MSI_IsEnabledRangeSelect - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_MSI_IsEnabledRangeSelect(void) -{ - return ((READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == RCC_ICSCR1_MSIRGSEL) ? 1UL : 0UL); -} - -/** - * @brief Configure the Internal Multi Speed oscillator (MSI) clock range in run mode. - * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_SetRange - * @param Range This parameter can be one of the following values: - * @arg @ref LL_RCC_MSISRANGE_0 - * @arg @ref LL_RCC_MSISRANGE_1 - * @arg @ref LL_RCC_MSISRANGE_2 - * @arg @ref LL_RCC_MSISRANGE_3 - * @arg @ref LL_RCC_MSISRANGE_4 - * @arg @ref LL_RCC_MSISRANGE_5 - * @arg @ref LL_RCC_MSISRANGE_6 - * @arg @ref LL_RCC_MSISRANGE_7 - * @arg @ref LL_RCC_MSISRANGE_8 - * @arg @ref LL_RCC_MSISRANGE_9 - * @arg @ref LL_RCC_MSISRANGE_10 - * @arg @ref LL_RCC_MSISRANGE_11 - * @arg @ref LL_RCC_MSISRANGE_12 - * @arg @ref LL_RCC_MSISRANGE_13 - * @arg @ref LL_RCC_MSISRANGE_14 - * @arg @ref LL_RCC_MSISRANGE_15 - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIS_SetRange(uint32_t Range) -{ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, Range); -} -#define LL_RCC_MSI_SetRange LL_RCC_MSIS_SetRange /*!< alias define for compatibility with legacy code */ - -/** - * @brief Get the Internal Multi Speed oscillator (MSI) clock range in run mode. - * @rmtoll ICSCR1 MSISRANGE LL_RCC_MSIS_GetRange - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MSISRANGE_0 - * @arg @ref LL_RCC_MSISRANGE_1 - * @arg @ref LL_RCC_MSISRANGE_2 - * @arg @ref LL_RCC_MSISRANGE_3 - * @arg @ref LL_RCC_MSISRANGE_4 - * @arg @ref LL_RCC_MSISRANGE_5 - * @arg @ref LL_RCC_MSISRANGE_6 - * @arg @ref LL_RCC_MSISRANGE_7 - * @arg @ref LL_RCC_MSISRANGE_8 - * @arg @ref LL_RCC_MSISRANGE_9 - * @arg @ref LL_RCC_MSISRANGE_10 - * @arg @ref LL_RCC_MSISRANGE_11 - * @arg @ref LL_RCC_MSISRANGE_12 - * @arg @ref LL_RCC_MSISRANGE_13 - * @arg @ref LL_RCC_MSISRANGE_14 - * @arg @ref LL_RCC_MSISRANGE_15 - */ -__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRange(void) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE)); -} -#define LL_RCC_MSI_GetRange LL_RCC_MSIS_GetRange /*!< alias define for compatibility with legacy code */ - -/** - * @brief Configure MSIS range used after standby - * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_SetRangeAfterStandby - * @param Range This parameter can be one of the following values: - * @arg @ref LL_RCC_MSISSRANGE_4 - * @arg @ref LL_RCC_MSISSRANGE_5 - * @arg @ref LL_RCC_MSISSRANGE_6 - * @arg @ref LL_RCC_MSISSRANGE_7 - * @arg @ref LL_RCC_MSISSRANGE_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIS_SetRangeAfterStandby(uint32_t Range) -{ - MODIFY_REG(RCC->CSR, RCC_CSR_MSISSRANGE, Range); -} -#define LL_RCC_MSI_SetRangeAfterStandby LL_RCC_MSIS_SetRangeAfterStandby /*!< alias define for compatibility with legacy code */ - -/** - * @brief Get MSIS range used after standby - * @rmtoll CSR MSISSRANGE LL_RCC_MSIS_GetRangeAfterStandby - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MSISSRANGE_4 - * @arg @ref LL_RCC_MSISSRANGE_5 - * @arg @ref LL_RCC_MSISSRANGE_6 - * @arg @ref LL_RCC_MSISSRANGE_7 - * @arg @ref LL_RCC_MSISSRANGE_8 - */ -__STATIC_INLINE uint32_t LL_RCC_MSIS_GetRangeAfterStandby(void) -{ - return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISSRANGE)); -} -#define LL_RCC_MSI_GetRangeAfterStandby LL_RCC_MSIS_GetRangeAfterStandby /*!< alias define for compatibility with legacy code */ - -/** - * @brief Set MSI OSCILLATORx Calibration trimming - * @note user-programmable trimming value that is added to the MSICALx - * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_SetCalibTrimming - * @param Value Between Min_Data = 0 and Max_Data = 31 - * @param Oscillator This parameter can be one of the following values: - * @arg @ref LL_RCC_MSI_OSCILLATOR_0 - * @arg @ref LL_RCC_MSI_OSCILLATOR_1 - * @arg @ref LL_RCC_MSI_OSCILLATOR_2 - * @arg @ref LL_RCC_MSI_OSCILLATOR_3 - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSI_SetCalibTrimming(uint32_t Value, uint32_t Oscillator) -{ - MODIFY_REG(RCC->ICSCR2, (RCC_ICSCR2_MSITRIM0 >> Oscillator), Value << (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); -} - -/** - * @brief Get MSI OSCILLATORx Calibration trimming - * @rmtoll ICSCR2 MSITRIMx LL_RCC_MSI_GetCalibTrimming - * @retval Between 0 and 31 - * @param Oscillator This parameter can be one of the following values: - * @arg @ref LL_RCC_MSI_OSCILLATOR_0 - * @arg @ref LL_RCC_MSI_OSCILLATOR_1 - * @arg @ref LL_RCC_MSI_OSCILLATOR_2 - * @arg @ref LL_RCC_MSI_OSCILLATOR_3 - */ -__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibTrimming(uint32_t Oscillator) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR2, - (RCC_ICSCR2_MSITRIM0 >> Oscillator)) >> (RCC_ICSCR2_MSITRIM0_Pos - Oscillator)); -} - -/** - * @brief Get MSI OSCILLATORx Calibration value - * @note When MSITRIMx is written, MSICALx is updated with the sum of - * MSITRIMx and the factory trim value - * @rmtoll ICSCR1 MSICALx LL_RCC_MSI_GetCalibration - * @param Oscillator This parameter can be one of the following values: - * @arg @ref LL_RCC_MSI_OSCILLATOR_0 - * @arg @ref LL_RCC_MSI_OSCILLATOR_1 - * @arg @ref LL_RCC_MSI_OSCILLATOR_2 - * @arg @ref LL_RCC_MSI_OSCILLATOR_3 - * @retval Between Min_Data = 0 and Max_Data = 31 - */ -__STATIC_INLINE uint32_t LL_RCC_MSI_GetCalibration(uint32_t Oscillator) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR1, (RCC_ICSCR1_MSICAL0 >> Oscillator)) >> (RCC_ICSCR1_MSICAL0_Pos - Oscillator)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MSIK MSIK - * @{ - */ - -/** - * @brief Configure the Internal Multi Speed oscillator (MSIK) clock range in run mode. - * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_SetRange - * @param Range This parameter can be one of the following values: - * @arg @ref LL_RCC_MSIKRANGE_0 - * @arg @ref LL_RCC_MSIKRANGE_1 - * @arg @ref LL_RCC_MSIKRANGE_2 - * @arg @ref LL_RCC_MSIKRANGE_3 - * @arg @ref LL_RCC_MSIKRANGE_4 - * @arg @ref LL_RCC_MSIKRANGE_5 - * @arg @ref LL_RCC_MSIKRANGE_6 - * @arg @ref LL_RCC_MSIKRANGE_7 - * @arg @ref LL_RCC_MSIKRANGE_8 - * @arg @ref LL_RCC_MSIKRANGE_9 - * @arg @ref LL_RCC_MSIKRANGE_10 - * @arg @ref LL_RCC_MSIKRANGE_11 - * @arg @ref LL_RCC_MSIKRANGE_12 - * @arg @ref LL_RCC_MSIKRANGE_13 - * @arg @ref LL_RCC_MSIKRANGE_14 - * @arg @ref LL_RCC_MSIKRANGE_15 - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIK_SetRange(uint32_t Range) -{ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, Range); -} - -/** - * @brief Get the Internal Multi Speed oscillator (MSIK) clock range in run mode. - * @rmtoll ICSCR1 MSIKRANGE LL_RCC_MSIK_GetRange - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MSIKRANGE_0 - * @arg @ref LL_RCC_MSIKRANGE_1 - * @arg @ref LL_RCC_MSIKRANGE_2 - * @arg @ref LL_RCC_MSIKRANGE_3 - * @arg @ref LL_RCC_MSIKRANGE_4 - * @arg @ref LL_RCC_MSIKRANGE_5 - * @arg @ref LL_RCC_MSIKRANGE_6 - * @arg @ref LL_RCC_MSIKRANGE_7 - * @arg @ref LL_RCC_MSIKRANGE_8 - * @arg @ref LL_RCC_MSIKRANGE_9 - * @arg @ref LL_RCC_MSIKRANGE_10 - * @arg @ref LL_RCC_MSIKRANGE_11 - * @arg @ref LL_RCC_MSIKRANGE_12 - * @arg @ref LL_RCC_MSIKRANGE_13 - * @arg @ref LL_RCC_MSIKRANGE_14 - * @arg @ref LL_RCC_MSIKRANGE_15 - */ -__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRange(void) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE)); -} - -/** - * @brief Configure MSIK range used after standby - * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_SetRangeAfterStandby - * @param Range This parameter can be one of the following values: - * @arg @ref LL_RCC_MSIKSRANGE_4 - * @arg @ref LL_RCC_MSIKSRANGE_5 - * @arg @ref LL_RCC_MSIKSRANGE_6 - * @arg @ref LL_RCC_MSIKSRANGE_7 - * @arg @ref LL_RCC_MSIKSRANGE_8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_MSIK_SetRangeAfterStandby(uint32_t Range) -{ - MODIFY_REG(RCC->CSR, RCC_CSR_MSIKSRANGE, Range); -} - -/** - * @brief Get MSIK range used after standby - * @rmtoll CSR MSIKSRANGE LL_RCC_MSIK_GetRangeAfterStandby - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MSIKSRANGE_4 - * @arg @ref LL_RCC_MSIKSRANGE_5 - * @arg @ref LL_RCC_MSIKSRANGE_6 - * @arg @ref LL_RCC_MSIKSRANGE_7 - * @arg @ref LL_RCC_MSIKSRANGE_8 - */ -__STATIC_INLINE uint32_t LL_RCC_MSIK_GetRangeAfterStandby(void) -{ - return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSIKSRANGE)); -} -/** - * @} - */ - -/** @defgroup RCC_LL_EF_LSCO LSCO - * @{ - */ - -/** - * @brief Enable Low speed clock - * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSCO_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); -} - -/** - * @brief Disable Low speed clock - * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSCO_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); -} - -/** - * @brief Configure Low speed clock selection - * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); -} - -/** - * @brief Get Low speed clock selection - * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR1 SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_MSIS - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR1 SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_MSIS - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR2 HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, Prescaler); -} - -/** - * @brief Set Systick clock source - * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource - * @param SystickSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI - * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE - * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSystickClockSource(uint32_t SystickSource) -{ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, SystickSource); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR2 PPRE1 LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, Prescaler); -} - -/** - * @brief Set APB2 prescaler - * @rmtoll CFGR2 PPRE2 LL_RCC_SetAPB2Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, Prescaler); -} - -/** - * @brief Set APB3 prescaler - * @rmtoll CFGR3 PPRE3 LL_RCC_SetAPB3Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB3_DIV_1 - * @arg @ref LL_RCC_APB3_DIV_2 - * @arg @ref LL_RCC_APB3_DIV_4 - * @arg @ref LL_RCC_APB3_DIV_8 - * @arg @ref LL_RCC_APB3_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, Prescaler); -} - -#if defined(RCC_CFGR2_PPRE_DPHY) -/** - * @brief Set DPHY clock prescaler - * @rmtoll CFGR2 PPRE_DPHY LL_RCC_SetDPHYPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_DPHY_DIV_1 - * @arg @ref LL_RCC_DPHY_DIV_2 - * @arg @ref LL_RCC_DPHY_DIV_4 - * @arg @ref LL_RCC_DPHY_DIV_8 - * @arg @ref LL_RCC_DPHY_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDPHYPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY, Prescaler); -} -#endif /* RCC_CFGR2_PPRE_DPHY */ - -/** - * @brief Get AHB prescaler - * @rmtoll CFGR2 HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_HPRE)); -} - -/** - * @brief Get Sysctick clock source - * @rmtoll CCIPR1 SYSTICKSEL LL_RCC_SetSystickClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSI - * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_LSE - * @arg @ref LL_RCC_SYSTICK_CLKSOURCE_HCLKDIV8 - */ -__STATIC_INLINE uint32_t LL_RCC_GetSystickClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR2 PPRE1 LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE1)); -} - -/** - * @brief Get APB2 prescaler - * @rmtoll CFGR2 PPRE2 LL_RCC_GetAPB2Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB2_DIV_1 - * @arg @ref LL_RCC_APB2_DIV_2 - * @arg @ref LL_RCC_APB2_DIV_4 - * @arg @ref LL_RCC_APB2_DIV_8 - * @arg @ref LL_RCC_APB2_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE2)); -} - -/** - * @brief Get APB3 prescaler - * @rmtoll CFGR3 PPRE3 LL_RCC_GetAPB2Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB3_DIV_1 - * @arg @ref LL_RCC_APB3_DIV_2 - * @arg @ref LL_RCC_APB3_DIV_4 - * @arg @ref LL_RCC_APB3_DIV_8 - * @arg @ref LL_RCC_APB3_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_PPRE3)); -} - -#if defined(RCC_CFGR2_PPRE_DPHY) -/** - * @brief Get DPHY clock prescaler - * @rmtoll CFGR2 PPRE_DPHY LL_RCC_GetDPHYPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DPHY_DIV_1 - * @arg @ref LL_RCC_DPHY_DIV_2 - * @arg @ref LL_RCC_DPHY_DIV_4 - * @arg @ref LL_RCC_DPHY_DIV_8 - * @arg @ref LL_RCC_DPHY_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetDPHYPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_PPRE_DPHY)); -} -#endif /* RCC_CFGR2_PPRE_DPHY */ - -/** - * @brief Set Clock After Wake-Up From Stop mode - * @rmtoll CFGR1 STOPWUCK LL_RCC_SetClkAfterWakeFromStop - * @param Clock This parameter can be one of the following values: - * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS - * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetClkAfterWakeFromStop(uint32_t Clock) -{ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPWUCK, Clock); -} - -/** - * @brief Get Clock After Wake-Up From Stop mode - * @rmtoll CFGR1 STOPWUCK LL_RCC_GetClkAfterWakeFromStop - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_MSIS - * @arg @ref LL_RCC_STOP_WAKEUPCLOCK_HSI - */ -__STATIC_INLINE uint32_t LL_RCC_GetClkAfterWakeFromStop(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPWUCK)); -} - -/** - * @brief Set Kernel Clock After Wake-Up From Stop mode - * @rmtoll CFGR1 STOPKERWUCK LL_RCC_SetKerClkAfterWakeFromStop - * @param Clock This parameter can be one of the following values: - * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK - * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetKerClkAfterWakeFromStop(uint32_t Clock) -{ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK, Clock); -} - -/** - * @brief Get Kernel Clock After Wake-Up From Stop mode - * @rmtoll CFGR1 STOPKERWUCK LL_RCC_GetKerClkAfterWakeFromStop - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_MSIK - * @arg @ref LL_RCC_STOP_WAKEUPKERCLOCK_HSI - */ -__STATIC_INLINE uint32_t LL_RCC_GetKerClkAfterWakeFromStop(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR1, RCC_CFGR1_STOPKERWUCK)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR1 MCOSEL LL_RCC_ConfigMCO\n - * CFGR1 MCOPRE LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK - * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO1SOURCE_MSIS - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_HSI48 - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK - * @arg @ref LL_RCC_MCO1SOURCE_LSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @param MCOxPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 - * @arg @ref LL_RCC_MCO1_DIV_4 - * @arg @ref LL_RCC_MCO1_DIV_8 - * @arg @ref LL_RCC_MCO1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) -{ - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE, MCOxSource | MCOxPrescaler); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ - -/** - * @brief Configure USARTx clock source - * @rmtoll CCIPR1 USART1SEL LL_RCC_SetUSARTClockSource\n - * CCIPR1 USART2SEL LL_RCC_SetUSARTClockSource\n - * CCIPR1 USART3SEL LL_RCC_SetUSARTClockSource\n - * CCIPR2 USART6SEL LL_RCC_SetUSARTClockSource - * @param USARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) - * - * (*) Availability depends on devices. - - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource) -{ - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTxSource >> 24U)); - MODIFY_REG(*reg, 3UL << ((USARTxSource & 0x001F0000U) >> 16U), ((USARTxSource & 0x000000FFU) << \ - ((USARTxSource & 0x001F0000U) >> 16U))); -} - -/** - * @brief Configure UARTx clock source - * @rmtoll CCIPR1 UART4SEL LL_RCC_SetUARTClockSource\n - * CCIPR1 UART5SEL LL_RCC_SetUARTClockSource - * @param UARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource) -{ - MODIFY_REG(RCC->CCIPR1, UARTxSource >> 16U, (UARTxSource & 0x0000FFFFU)); -} - -/** - * @brief Configure LPUARTx clock source - * @rmtoll CCIPR3 LPUART1SEL LL_RCC_SetLPUARTClockSource - * @param LPUARTxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t LPUARTxSource) -{ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_LPUART1SEL, LPUARTxSource); -} - -/** - * @brief Configure I2Cx clock source - * @rmtoll CCIPR1 I2C1SEL LL_RCC_SetI2CClockSource\n - * CCIPR1 I2C2SEL LL_RCC_SetI2CClockSource\n - * CCIPR3 I2C3SEL LL_RCC_SetI2CClockSource\n - * CCIPR1 I2C4SEL LL_RCC_SetI2CClockSource - * @param I2CxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C2_CLKSOURCE_MSIK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 - * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C3_CLKSOURCE_MSIK - * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C4_CLKSOURCE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource) -{ - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2CxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((I2CxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((I2CxSource & 0x000000FFU) << \ - (((I2CxSource & 0x00FF0000U) >> 16U) & \ - 0x1FU))); -} - -/** - * @brief Configure SPIx clock source - * @rmtoll CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n - * CCIPR1 SPI1SEL LL_RCC_SetSPIClockSource\n - * CCIPR1 SPI2SEL LL_RCC_SetSPIClockSource\n - * CCIPR3 SPI3SEL LL_RCC_SetSPIClockSource - * @param SPIxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI - * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI - * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK - * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3 - * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI - * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t SPIxSource) -{ - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((SPIxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((SPIxSource & 0x000000FFU) << \ - (((SPIxSource & 0x00FF0000U) >> 16U) & \ - 0x1FU))); -} - -/** - * @brief Configure LPTIMx clock source - * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n - * CCIPR3 LPTIM2SEL LL_RCC_SetLPTIMClockSource\n - * CCIPR3 LPTIM34SEL LL_RCC_SetLPTIMClockSource - * @param LPTIMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) -{ - __IO uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMxSource >> 24U)); - MODIFY_REG(*reg, 3U << (((LPTIMxSource & 0x00FF0000U) >> 16U) & 0x1FU), ((LPTIMxSource & 0x000000FFU) << \ - (((LPTIMxSource & 0x00FF0000U) >> 16U) & \ - 0x1FU))); -} - -/** - * @brief Configure FDCAN kernel clock source - * @rmtoll CCIPR1 FDCANSEL LL_RCC_SetFDCANClockSource - * @param FDCANxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE - * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t FDCANxSource) -{ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_FDCANSEL, FDCANxSource); -} - -/** - * @brief Configure SAIx clock source - * @rmtoll CCIPR2 SAI1SEL LL_RCC_SetSAIClockSource\n - * CCIPR2 SAI2SEL LL_RCC_SetSAIClockSource - * @param SAIxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) - * - * (*) Availability depends on devices. - * - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource) -{ - MODIFY_REG(RCC->CCIPR2, (SAIxSource >> 16U), (SAIxSource & 0x0000FFFFU)); -} - -/** - * @brief Configure SDMMC1/2 kernel clock source - * @rmtoll CCIPR2 SDMMCSEL LL_RCC_SetSDMMCKernelClockSource - * @param SDMMCxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK - * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P" - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSDMMCKernelClockSource(uint32_t SDMMCxSource) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SDMMCSEL, SDMMCxSource); -} - -/** - * @brief Configure SDMMC1/2 clock source - * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetSDMMCClockSource - * @param SDMMCxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource) -{ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, SDMMCxSource); -} - -/** - * @brief Configure RNG clock source - * @rmtoll CCIPR2 RNGSEL LL_RCC_SetRNGClockSource - * @param RNGxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 - * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_RNGSEL, RNGxSource); -} - -#if defined(RCC_CCIPR2_USBPHYCSEL) -/** - * @brief Configure USBPHY clock source - * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_SetUSBPHYClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE - * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 - * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 - * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBPHYClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_USBPHYCSEL, Source); -} -#endif /* RCC_CCIPR2_USBPHYCSEL */ - -/** - * @brief Configure USB clock source - * @rmtoll CCIPR1 ICLKSEL LL_RCC_SetUSBClockSource - * @param USBxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource) -{ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_ICLKSEL, USBxSource); -} - -/** - * @brief Configure ADC clock source - * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource - * @param ADCxDAC1Source This parameter can be one of the following values: - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSI - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetADCDACClockSource(uint32_t ADCxDAC1Source) -{ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADCDACSEL, ADCxDAC1Source); -} - -/** - * @brief Configure DAC1 clock source - * @rmtoll CCIPR3 DAC1SEL LL_RCC_SetDAC1ClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE - * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDAC1ClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_DAC1SEL, Source); -} - -/** - * @brief Configure ADF1 clock source - * @rmtoll CCIPR3 ADF1SEL LL_RCC_SetADF1ClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK - * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetADF1ClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR3, RCC_CCIPR3_ADF1SEL, Source); -} - -/** - * @brief Configure MDF1 clock source - * @rmtoll CCIPR3 MDF1SEL LL_RCC_SetMDF1ClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK - * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetMDF1ClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_MDF1SEL, Source); -} - -/** - * @brief Configure OCTOSPI kernel clock source - * @rmtoll CCIPR2 OSPISEL LL_RCC_SetOCTOSPIClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetOCTOSPIClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_OCTOSPISEL, Source); -} - -#if defined (HSPI1) -/** - * @brief Configure HSPI kernel clock source - * @rmtoll CCIPR2 HSPISEL LL_RCC_SetHSPIClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetHSPIClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_HSPISEL, Source); -} -#endif /* HSPI1 */ - -#if defined(SAES) -/** - * @brief Configure SAES clock source - * @rmtoll CCIPR2 SAESSEL LL_RCC_SetSAESClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI - * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSAESClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_SAESSEL, Source); -} -#endif /* SAES */ - -#if defined(DSI) -/** - * @brief Configure DSIx clock source - * @rmtoll CCIPR2 DSISEL LL_RCC_SetDSIClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY - * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_DSIHOSTSEL, Source); -} -#endif /* DSI */ - -#if defined(LTDC) -/** - * @brief Configure LTDCx clock source - * @rmtoll CCIPR2 LTDCSEL LL_RCC_SetLTDCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetLTDCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->CCIPR2, RCC_CCIPR2_LTDCSEL, Source); -} -#endif /* LTDC */ -/** - * @brief Get USARTx clock source - * @rmtoll CCIPR1 USART1SEL LL_RCC_GetUSARTClockSource\n - * CCIPR1 USART2SEL LL_RCC_GetUSARTClockSource\n - * CCIPR1 USART3SEL LL_RCC_GetUSARTClockSource\n - * CCIPR2 USART6SEL LL_RCC_GetUSARTClockSource - * @param USARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE - * @arg @ref LL_RCC_USART2_CLKSOURCE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE - * @arg @ref LL_RCC_USART6_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE (*) - * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI - * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE - * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK1 (*) - * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK (*) - * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI (*) - * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE (*) - * - * (*) Availability depends on devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx) -{ - __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (USARTx >> 24U)); - return (uint32_t)((READ_BIT(*reg, 3UL << ((USARTx & 0x001F0000U) >> 16U)) >> \ - ((USARTx & 0x001F0000U) >> 16U)) | (USARTx & 0xFFFF0000U)); -} - -/** - * @brief Get UARTx clock source - * @rmtoll CCIPR1 UART4SEL LL_RCC_GetUARTClockSource\n - * CCIPR1 UART5SEL LL_RCC_GetUARTClockSource - * @param UARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE - * @arg @ref LL_RCC_UART5_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE - * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI - * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR1, UARTx) | (UARTx << 16U)); -} - -/** - * @brief Get LPUARTx clock source - * @rmtoll CCIPR1 LPUART1SEL LL_RCC_GetLPUARTClockSource - * @param LPUARTx This parameter can be one of the following values: - * @arg @ref LL_RCC_LPUART1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK3 - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t LPUARTx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR3, LPUARTx)); -} - -/** - * @brief Get I2Cx clock source - * @rmtoll CCIPR1 I2C1SEL LL_RCC_GetI2CClockSource\n - * CCIPR1 I2C2SEL LL_RCC_GetI2CClockSource\n - * CCIPR3 I2C3SEL LL_RCC_GetI2CClockSource\n - * CCIPR1 I2C4SEL LL_RCC_GetI2CClockSource - * @param I2Cx This parameter can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE - * @arg @ref LL_RCC_I2C2_CLKSOURCE - * @arg @ref LL_RCC_I2C3_CLKSOURCE - * @arg @ref LL_RCC_I2C4_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK3 - * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI - * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI - */ -__STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx) -{ - __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (I2Cx >> 24U)); - return (uint32_t)((READ_BIT(*reg, (3UL << (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ - (((I2Cx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (I2Cx & 0xFFFF0000UL)); -} - -/** - * @brief Get SPIx clock source - * @rmtoll CCIPR1 SPI1SEL LL_RCC_GetSPIClockSource\n - * CCIPR1 SPI2SEL LL_RCC_GetSPIClockSource\n - * CCIPR3 SPI3SEL LL_RCC_GetSPIClockSource - * @param SPIx This parameter can be one of the following values: - * @arg @ref LL_RCC_SPI1_CLKSOURCE - * @arg @ref LL_RCC_SPI2_CLKSOURCE - * @arg @ref LL_RCC_SPI3_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SPI1_CLKSOURCE_PCLK2 - * @arg @ref LL_RCC_SPI1_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SPI1_CLKSOURCE_HSI - * @arg @ref LL_RCC_SPI1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_SPI2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_SPI2_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SPI2_CLKSOURCE_HSI - * @arg @ref LL_RCC_SPI2_CLKSOURCE_MSIK - * @arg @ref LL_RCC_SPI3_CLKSOURCE_PCLK3 - * @arg @ref LL_RCC_SPI3_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_SPI3_CLKSOURCE_HSI - * @arg @ref LL_RCC_SPI3_CLKSOURCE_MSIK - */ -__STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t SPIx) -{ - __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (SPIx >> 24U)); - return (uint32_t)((READ_BIT(*reg, (3UL << (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ - (((SPIx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (SPIx & 0xFFFF0000UL)); -} - -/** - * @brief Get LPTIMx clock source - * @rmtoll CCIPR1 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n - * CCIPR3 LPTIM2SEL LL_RCC_GetLPTIMClockSource\n - * CCIPR3 LPTIM34SEL LL_RCC_GetLPTIMClockSource - * @param LPTIMx This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_MSIK - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_HSI - * @arg @ref LL_RCC_LPTIM34_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) -{ - __IO const uint32_t *reg = (__IO uint32_t *)(uint32_t)(RCC_BASE + 0xE0U + (LPTIMx >> 24U)); - return (uint32_t)((READ_BIT(*reg, (3UL << (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL))) >> \ - (((LPTIMx & 0x00FF0000UL) >> 16U) & 0x1FUL)) | (LPTIMx & 0xFFFF0000UL)); -} - -/** - * @brief Set Tim Input capture clock source - * @rmtoll CCIPR1 TIMICSEL LL_RCC_SetTIMICClockSource - * @param TIMICSource This parameter can be one of the following combined values: - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 - * @note HSI, MSI and MSIK clocks without division are also available when TIMICSEL[2] is 1. - * @note combination to be avoided : - * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV1024 - * LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 and LL_RCC_CLKSOURCE_TIMIC_MSIK_DIV4 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetTIMICClockSource(uint32_t TIMICSource) -{ - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL, TIMICSource); -} - -/** - * @brief Get Tim Input capture clock source - * @rmtoll CCIPR1 TIMICSEL LL_RCC_GetTIMICClockSource - * @retval Returned value can be one of the following combined values: - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_NONE - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_HSI_DIV256 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV1024 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIS_DIV4 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV4 - * @arg @ref LL_RCC_TIMIC_CLKSOURCE_MSIK_DIV1024 - */ -__STATIC_INLINE uint32_t LL_RCC_GetTIMICClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR1, RCC_CCIPR1_TIMICSEL)); -} - -/** - * @brief Get FDCAN kernel clock source - * @rmtoll CCIPR1 FDCANSEL LL_RCC_GetFDCANClockSource - * @param FDCANx This parameter can be one of the following values: - * @arg @ref LL_RCC_FDCAN_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE - * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2 - */ -__STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t FDCANx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR1, FDCANx)); -} - -/** - * @brief Get SAIx clock source - * @rmtoll CCIPR2 SAI1SEL LL_RCC_GetSAIClockSource\n - * CCIPR2 SAI2SEL LL_RCC_GetSAIClockSource - * @param SAIx This parameter can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE - * @arg @ref LL_RCC_SAI2_CLKSOURCE (*) - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN - * @arg @ref LL_RCC_SAI1_CLKSOURCE_HSI - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL1 (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL2 (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLL3 (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN (*) - * @arg @ref LL_RCC_SAI2_CLKSOURCE_HSI (*) - * - * (*) Availability depends on devices. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, SAIx) | (SAIx << 16U)); -} - -/** - * @brief Get SDMMCx kernel clock source - * @rmtoll CCIPR2 SDMMCSEL LL_RCC_GetSDMMCKernelClockSource - * @param SDMMCx This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC_KERNELCLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_48CLK - * @arg @ref LL_RCC_SDMMC12_KERNELCLKSOURCE_PLL1 "P" - */ -__STATIC_INLINE uint32_t LL_RCC_GetSDMMCKernelClockSource(uint32_t SDMMCx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, SDMMCx)); -} - -/** - * @brief Get SDMMC1/2 clock source - * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetSDMMCClockSource - * @param SDMMCx This parameter can be one of the following values: - * @arg @ref LL_RCC_SDMMC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_SDMMC12_CLKSOURCE_MSIK - */ -__STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR1, SDMMCx)); -} - -/** - * @brief Get RNGx clock source - * @rmtoll CCIPR2 RNGSEL LL_RCC_GetRNGClockSource - * @param RNGx This parameter can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48_DIV2 - * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI - */ -__STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, RNGx)); -} - -#if defined(RCC_CCIPR2_USBPHYCSEL) -/** - * @brief Get USBPHYx clock source - * @rmtoll CCIPR2 USBPHYCSEL LL_RCC_GetUSBPHYClockSource - * @param USBPHYx This parameter can be one of the following values: - * @arg @ref LL_RCC_USBPHY_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE - * @arg @ref LL_RCC_USBPHYCLKSOURCE_HSE_DIV2 - * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1 - * @arg @ref LL_RCC_USBPHYCLKSOURCE_PLL1_DIV2 - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBPHYClockSource(uint32_t USBPHYx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, USBPHYx)); -} -#endif /* RCC_CCIPR2_USBPHYCSEL */ - -/** - * @brief Get USBx clock source - * @rmtoll CCIPR1 ICLKSEL LL_RCC_GetUSBClockSource - * @param USBx This parameter can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_USB_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_USB_CLKSOURCE_MSIK - */ -__STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR1, USBx)); -} - -/** - * @brief Get ADCx clock source - * @rmtoll CCIPR3 ADCDACSEL LL_RCC_SetADCDACClockSource - * @param ADCxDAC1 This parameter can be one of the following values: - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HCLK - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_MSIK - * @arg @ref LL_RCC_ADCDAC_CLKSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_GetADCDACClockSource(uint32_t ADCxDAC1) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR3, ADCxDAC1)); -} - -/** - * @brief Get DFSDM Audio Clock Source - * @rmtoll CCIPR3 ADF1SEL LL_RCC_GetADF1ClockSource - * @param ADF1x This parameter can be one of the following values: - * @arg @ref LL_RCC_ADF1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_ADF1_CLKSOURCE_HCLK - * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_ADF1_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_ADF1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_ADF1_CLKSOURCE_PIN - */ -__STATIC_INLINE uint32_t LL_RCC_GetADF1ClockSource(uint32_t ADF1x) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR3, ADF1x)); -} - -/** - * @brief Get DAC1 Clock Source - * @rmtoll CCIPR3 DAC1SEL LL_RCC_GetDAC1ClockSource - * @param DAC1x This parameter can be one of the following values: - * @arg @ref LL_RCC_DAC1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSE - * @arg @ref LL_RCC_DAC1_CLKSOURCE_LSI - */ -__STATIC_INLINE uint32_t LL_RCC_GetDAC1ClockSource(uint32_t DAC1x) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR3, DAC1x)); -} - -/** - * @brief Get MDF1 Clock Source - * @rmtoll CCIPR2 MDF1SEL LL_RCC_GetMDF1ClockSource - * @param MDF1x This parameter can be one of the following values: - * @arg @ref LL_RCC_MDF1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MDF1_CLKSOURCE_HCLK - * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_MDF1_CLKSOURCE_PLL3 - * @arg @ref LL_RCC_MDF1_CLKSOURCE_MSIK - * @arg @ref LL_RCC_MDF1_CLKSOURCE_PIN - */ -__STATIC_INLINE uint32_t LL_RCC_GetMDF1ClockSource(uint32_t MDF1x) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, MDF1x)); -} - -/** - * @brief Get OCTOSPI clock source - * @rmtoll CCIPR2 OSPISEL LL_RCC_GetOCTOSPIClockSource - * @param OCTOSPIx This parameter can be one of the following values: - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_MSIK - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_OCTOSPI_CLKSOURCE_PLL2 - */ -__STATIC_INLINE uint32_t LL_RCC_GetOCTOSPIClockSource(uint32_t OCTOSPIx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, OCTOSPIx)); -} - -#if defined (HSPI1) -/** - * @brief Get HSPI clock source - * @rmtoll CCIPR2 HSPISEL LL_RCC_GetHSPIClockSource - * @param HSPIx This parameter can be one of the following values: - * @arg @ref LL_RCC_HSPI_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_HSPI_CLKSOURCE_SYSCLK - * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL1 - * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_HSPI_CLKSOURCE_PLL3 - */ -__STATIC_INLINE uint32_t LL_RCC_GetHSPIClockSource(uint32_t HSPIx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, HSPIx)); -} -#endif /* HSPI1 */ -/** - * @} - */ - -#if defined(SAES) -/** - * @brief Get SAES kernel clock source - * @rmtoll CCIPR2 SAESSEL LL_RCC_GetSAESClockSource - * @param SAESx This parameter can be one of the following values: - * @arg @ref LL_RCC_SAES_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI - * @arg @ref LL_RCC_SAES_CLKSOURCE_SHSI_DIV2 - */ -__STATIC_INLINE uint32_t LL_RCC_GetSAESClockSource(uint32_t SAESx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, SAESx)); -} -#endif /* SAES */ - -#if defined(DSI) -/** - * @brief Get DSI clock source - * @rmtoll CCIPR2 DSISEL LL_RCC_GetDSIClockSource - * @param DSIx This parameter can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY - * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL3 - */ -__STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, DSIx)); -} -#endif /* DSI */ - -#if defined(LTDC) -/** - * @brief Get LTDC clock source - * @rmtoll CCIPR2 LTDCSEL LL_RCC_GetLTDCClockSource - * @param LTDCx This parameter can be one of the following values: - * @arg @ref LL_RCC_LTDC_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL2 - * @arg @ref LL_RCC_LTDC_CLKSOURCE_PLL3 - */ -__STATIC_INLINE uint32_t LL_RCC_GetLTDCClockSource(uint32_t LTDCx) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR2, LTDCx)); -} -#endif /* LTDC */ - -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed anymore unless - * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is - * set). The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV32 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} - -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == RCC_BDCR_RTCEN) ? 1UL : 0UL); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @} - */ - - -/** @defgroup RCC_LL_EF_PLL1 PLL1 - * @{ - */ - -/** - * @brief Enable PLL1 - * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLL1ON); -} -#define LL_RCC_PLL_Enable LL_RCC_PLL1_Enable /*!< alias for compatibility with legacy code */ - -/** - * @brief Disable PLL1 - * @note Cannot be disabled if the PLL1 clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL1_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); -} -#define LL_RCC_PLL_Disable LL_RCC_PLL1_Disable /*!< alias for compatibility with legacy code */ - -/** - * @brief Check if PLL1 Ready - * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == RCC_CR_PLL1RDY) ? 1UL : 0UL); -} -#define LL_RCC_PLL_IsReady LL_RCC_PLL1_IsReady /*!< alias for compatibility with legacy code */ - -/** - * @brief Configure PLL1 used for SYSCLK Domain - * @note PLL1 Source, PLLM, PLLN and PLLR can be written only when PLL1 is disabled. - * @note PLLN/PLLR can be written only when PLL is disabled. - * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SYS\n - * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_SYS\n - * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_SYS\n - * PLL1CFGR PLL1R LL_RCC_PLL1_ConfigDomain_SYS - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL1SOURCE_NONE - * @arg @ref LL_RCC_PLL1SOURCE_MSIS - * @arg @ref LL_RCC_PLL1SOURCE_HSI - * @arg @ref LL_RCC_PLL1SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLR parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) - * @param PLLN parameter can be a value between 4 and 512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ - ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1R, ((PLLN - 1UL) << \ - RCC_PLL1DIVR_PLL1N_Pos) | ((PLLR - 1UL) << \ - RCC_PLL1DIVR_PLL1R_Pos)); -} -#define LL_RCC_PLL_ConfigDomain_SYS LL_RCC_PLL1_ConfigDomain_SYS /*!< alias for compatibility with legacy code */ - -/** - * @brief Configure PLL1 used for SAI domain clock - * @note PLL1 Source, PLLM, PLLN and PLLPDIV can be written only when PLL1 is disabled. - * @note This can be selected for SAI1 or SAI2 - * @rmtoll PLLC1FGR PLL1SRC LL_RCC_PLL1_ConfigDomain_SAI\n - * PLLC1FGR PLL1M LL_RCC_PLL1_ConfigDomain_SAI\n - * PLLC1FGR PLL1N LL_RCC_PLL1_ConfigDomain_SAI\n - * PLLC1FGR PLL1P LL_RCC_PLL1_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL1SOURCE_NONE - * @arg @ref LL_RCC_PLL1SOURCE_MSIS - * @arg @ref LL_RCC_PLL1SOURCE_HSI - * @arg @ref LL_RCC_PLL1SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLP parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ - ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1P, ((PLLN - 1UL) << \ - RCC_PLL1DIVR_PLL1N_Pos) | ((PLLP - 1UL) << \ - RCC_PLL1DIVR_PLL1P_Pos)); -} -#define LL_RCC_PLL_ConfigDomain_SAI LL_RCC_PLL1_ConfigDomain_SAI /*!< alias for compatibility with legacy code */ - -/** - * @brief Configure PLL1 used for 48Mhz domain clock - * @note PLL1 Source, PLLM, PLLN and PLLQ can be written only when PLL1 is disabled. - * @note This can be selected for USB, SDMMC - * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_ConfigDomain_48M\n - * PLL1CFGR PLL1M LL_RCC_PLL1_ConfigDomain_48M\n - * PLL1CFGR PLL1N LL_RCC_PLL1_ConfigDomain_48M\n - * PLL1CFGR PLL1Q LL_RCC_PLL1_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL1SOURCE_NONE - * @arg @ref LL_RCC_PLL1SOURCE_MSIS - * @arg @ref LL_RCC_PLL1SOURCE_HSI - * @arg @ref LL_RCC_PLL1SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLQ parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1M, Source | \ - ((PLLM - 1UL) << RCC_PLL1CFGR_PLL1M_Pos)); - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N | RCC_PLL1DIVR_PLL1Q, ((PLLN - 1UL) << \ - RCC_PLL1DIVR_PLL1N_Pos) | ((PLLQ - 1UL) << \ - RCC_PLL1DIVR_PLL1Q_Pos)); -} -#define LL_RCC_PLL_ConfigDomain_48M LL_RCC_PLL1_ConfigDomain_48M /*!< alias for compatibility with legacy code */ - -/** - * @brief Configure PLL clock source - * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_SetMainSource - * @param PLL1Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL1SOURCE_NONE - * @arg @ref LL_RCC_PLL1SOURCE_MSIS - * @arg @ref LL_RCC_PLL1SOURCE_HSI - * @arg @ref LL_RCC_PLL1SOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_SetMainSource(uint32_t PLL1Source) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC, PLL1Source); -} -#define LL_RCC_PLL_SetMainSource LL_RCC_PLL1_SetMainSource /*!< alias for compatibility with legacy code */ - -/** - * @brief Get the oscillator used as PLL1 clock source. - * @rmtoll PLL1CFGR PLL1SRC LL_RCC_PLL1_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL1SOURCE_NONE - * @arg @ref LL_RCC_PLL1SOURCE_MSIS - * @arg @ref LL_RCC_PLL1SOURCE_HSI - * @arg @ref LL_RCC_PLL1SOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1SRC)); -} -#define LL_RCC_PLL_GetMainSource LL_RCC_PLL1_GetMainSource /*!< alias for compatibility with legacy code */ - -/** - * @brief Set Main PLL1 multiplication factor for VCO - * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_SetN - * @param PLL1N parameter can be a value between 4 and 512 - */ -__STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t PLL1N) -{ - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N, (PLL1N - 1UL) << RCC_PLL1DIVR_PLL1N_Pos); -} -#define LL_RCC_PLL_SetN LL_RCC_PLL1_SetN /*!< alias for compatibility with legacy code */ - -/** - * @brief Get Main PLL1 multiplication factor for VCO - * @rmtoll PLL1CFGR PLL1N LL_RCC_PLL1_GetN - * @retval Between 4 and 512 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1UL); -} -#define LL_RCC_PLL_GetN LL_RCC_PLL1_GetN /*!< alias for compatibility with legacy code */ - -/** - * @brief Set Main PLL1 division factor for PLL1P - * @note Used for SAI1 and SAI2 clock - * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_SetP - * @param PLL1P parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t PLL1P) -{ - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P, (PLL1P - 1UL) << RCC_PLL1DIVR_PLL1P_Pos); -} -#define LL_RCC_PLL_SetP LL_RCC_PLL1_SetP /*!< alias for compatibility with legacy code */ - -/** - * @brief Get Main PLL1 division factor for PLL1P - * @note Used for SAI1 and SAI2 clock - * @rmtoll PLL1CFGR PLL1P LL_RCC_PLL1_GetP - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1UL); -} -#define LL_RCC_PLL_GetP LL_RCC_PLL1_GetP /*!< alias for compatibility with legacy code */ - -/** - * @brief Set Main PLL division factor for PLLQ - * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLLCFGR PLL1Q LL_RCC_PLL1_SetQ - * @param PLL1Q parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t PLL1Q) -{ - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q, (PLL1Q - 1UL) << RCC_PLL1DIVR_PLL1Q_Pos); -} -#define LL_RCC_PLL_SetQ LL_RCC_PLL1_SetQ /*!< alias for compatibility with legacy code */ - -/** - * @brief Get Main PLL division factor for PLLQ - * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLL1CFGR PLL1Q LL_RCC_PLL1_GetQ - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1UL); -} -#define LL_RCC_PLL_GetQ LL_RCC_PLL1_GetQ /*!< alias for compatibility with legacy code */ - -/** - * @brief Set Main PLL division factor for PLL1R - * @note Used for PLL1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_SetR - * @param PLL1R parameter can be a value between 1 and 128 (Only division by 1 and even division are allowed) - */ -__STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t PLL1R) -{ - MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R, (PLL1R - 1UL) << RCC_PLL1DIVR_PLL1R_Pos); -} -#define LL_RCC_PLL_SetR LL_RCC_PLL1_SetR /*!< alias for compatibility with legacy code */ - -/** - * @brief Get Main PLL1 division factor for PLL1R - * @note Used for PLL1CLK (system clock) - * @rmtoll PLL1DIVR PLL1R LL_RCC_PLL1_GetR - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1UL); -} -#define LL_RCC_PLL_GetR LL_RCC_PLL1_GetR /*!< alias for compatibility with legacy code */ - -/** - * @brief Set Division factor for the main PLL and other PLL - * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_SetDivider - * @param PLL1M parameter can be a value between 1 and 16 - */ -__STATIC_INLINE void LL_RCC_PLL1_SetDivider(uint32_t PLL1M) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M, (PLL1M - 1UL) << RCC_PLL1CFGR_PLL1M_Pos); -} -#define LL_RCC_PLL_SetDivider LL_RCC_PLL1_SetDivider /*!< alias for compatibility with legacy code */ - -/** - * @brief Get Division factor for the main PLL and other PLL - * @rmtoll PLL1CFGR PLL1M LL_RCC_PLL1_GetDivider - * @retval Between 1 and 16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetDivider(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1UL); -} -#define LL_RCC_PLL_GetDivider LL_RCC_PLL1_GetDivider /*!< alias for compatibility with legacy code */ - -/** - * @brief Enable PLL1 output mapped on SAI domain clock - * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_EnableDomain_SAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SAI(void) -{ - SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); -} -#define LL_RCC_PLL_EnableDomain_SAI LL_RCC_PLL1_EnableDomain_SAI /*!< alias for compatibility with legacy code */ - -/** - * @brief Disable PLL1 output mapped on SAI domain clock - * @note Cannot be disabled if the PLL1 clock is used as the system - * clock - * @note In order to save power, when the PLL1CLK of the PLL1 is - * not used, should be 0 - * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_DisableDomain_SAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SAI(void) -{ - CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN); -} -#define LL_RCC_PLL_DisableDomain_SAI LL_RCC_PLL1_DisableDomain_SAI /*!< alias for compatibility with legacy code */ - -/** - * @brief Check if PLL1 output mapped on SAI domain clock is enabled - * @rmtoll PLL1CFGR PLL1PEN LL_RCC_PLL1_IsEnabledDomain_SAI - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SAI(void) -{ - return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1PEN) == (RCC_PLL1CFGR_PLL1PEN)) ? 1UL : 0UL); -} -#define LL_RCC_PLL_IsEnabledDomain_SAI LL_RCC_PLL1_IsEnabledDomain_SAI /*!< alias for compatibility with legacy code */ - -/** - * @brief Enable PLL output mapped on 48MHz domain clock - * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_EnableDomain_48M - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_48M(void) -{ - SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); -} - -/** - * @brief Disable PLL1 output mapped on 48MHz domain clock - * @note Cannot be disabled if the PLL clock is used as the system - * clock - * @note In order to save power, when the PLL1CLK of the PLL1 is - * not used, should be 0 - * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_DisableDomain_48M - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_48M(void) -{ - CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN); -} -#define LL_RCC_PLL_DisableDomain_48M LL_RCC_PLL1_DisableDomain_48M /*!< alias for compatibility with legacy code */ - -/** - * @brief Check if PLL1 output mapped on 48M domain clock is enabled - * @rmtoll PLL1CFGR PLL1QEN LL_RCC_PLL1_IsEnabledDomain_48M - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_48M(void) -{ - return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1QEN) == (RCC_PLL1CFGR_PLL1QEN)) ? 1UL : 0UL); -} -#define LL_RCC_PLL_IsEnabledDomain_48M LL_RCC_PLL1_IsEnabledDomain_48M /*!< alias for compatibility with legacy code */ - -/** - * @brief Enable PLL1 output mapped on SYSCLK domain - * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_EnableDomain_SYS - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_EnableDomain_SYS(void) -{ - SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); -} -#define LL_RCC_PLL_EnableDomain_SYS LL_RCC_PLL1_EnableDomain_SYS /*!< alias for compatibility with legacy code */ - -/** - * @brief Disable PLL1 output mapped on SYSCLK domain - * @note Cannot be disabled if the PLL1 clock is used as the system - * clock - * @note In order to save power, when the PLL1CLK of the PLL1 is - * not used, Main PLL1 should be 0 - * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_DisableDomain_SYS - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_DisableDomain_SYS(void) -{ - CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN); -} -#define LL_RCC_PLL_DisableDomain_SYS LL_RCC_PLL1_DisableDomain_SYS /*!< alias for compatibility with legacy code */ - -/** - * @brief Check if PLL1 output mapped on SYS domain clock is enabled - * @rmtoll PLL1CFGR PLL1REN LL_RCC_PLL1_IsEnabledDomain_SYS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_IsEnabledDomain_SYS(void) -{ - return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1REN) == (RCC_PLL1CFGR_PLL1REN)) ? 1UL : 0UL); -} -#define LL_RCC_PLL_IsEnabledDomain_SYS LL_RCC_PLL1_IsEnabledDomain_SYS /*!< alias for compatibility with legacy code */ - -/** - * @brief Enable PLL1 FRACN - * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void) -{ - SET_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); -} -#define LL_RCC_PLLFRACN_Enable LL_RCC_PLL1FRACN_Enable /*!< alias for compatibility with legacy code */ - -/** - * @brief Check if PLL1 FRACN is enabled - * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void) -{ - return ((READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN) == RCC_PLL1CFGR_PLL1FRACEN) ? 1UL : 0UL); -} -#define LL_RCC_PLLFRACN_IsEnabled LL_RCC_PLL1FRACN_IsEnabled /*!< alias for compatibility with legacy code */ - -/** - * @brief Disable PLL1 FRACN - * @rmtoll PLL1CFGR PLL1FRACEN LL_RCC_PLL1FRACN_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void) -{ - CLEAR_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1FRACEN); -} -#define LL_RCC_PLLFRACN_Disable LL_RCC_PLL1FRACN_Disable /*!< alias for compatibility with legacy code */ - -/** - * @brief Set PLL1 FRACN Coefficient - * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_SetFRACN - * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) - */ -__STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN) -{ - MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN, FRACN << RCC_PLL1FRACR_PLL1FRACN_Pos); -} -#define LL_RCC_PLL_SetFRACN LL_RCC_PLL1_SetFRACN /*!< alias for compatibility with legacy code */ - -/** - * @brief Get PLL1 FRACN Coefficient - * @rmtoll PLL1FRACR PLL1FRACN LL_RCC_PLL1_GetFRACN - * @retval A value between 0 and 8191 (0x1FFF) - */ -__STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> RCC_PLL1FRACR_PLL1FRACN_Pos); -} -#define LL_RCC_PLL_GetFRACN LL_RCC_PLL1_GetFRACN /*!< alias for compatibility with legacy code */ - -/** - * @brief Set PLL1 VCO Input Range - * @note This API shall be called only when PLL1 is disabled. - * @rmtoll PLL1CFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange - * @param InputRange This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 - * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1RGE, InputRange); -} -#define LL_RCC_PLL_SetVCOInputRange LL_RCC_PLL1_SetVCOInputRange /*!< alias for compatibility with legacy code */ - -/** - * @brief Set PLL1 EPOD Prescaler booster input clock - * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_SetPll1EPodPrescaler - * @param BoostDiv This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL1MBOOST_DIV_1 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_2 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_4 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_6 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_8 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_10 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_12 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_14 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_16 - */ -__STATIC_INLINE void LL_RCC_SetPll1EPodPrescaler(uint32_t BoostDiv) -{ - MODIFY_REG(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST, BoostDiv); -} - -/** - * @brief Get PLL1 EPOD Prescaler booster input clock - * @rmtoll PLL1CFGR PLL1MBOOST LL_RCC_GetPll1EPodPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL1MBOOST_DIV_1 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_2 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_4 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_6 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_8 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_10 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_12 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_14 - * @arg @ref LL_RCC_PLL1MBOOST_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetPll1EPodPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL1CFGR, RCC_PLL1CFGR_PLL1MBOOST)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLL2 PLL2 - * @{ - */ - -/** - * @brief Enable PLL2 - * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLL2ON); -} - -/** - * @brief Disable PLL2 - * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); -} - -/** - * @brief Check if PLL2 Ready - * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == RCC_CR_PLL2RDY) ? 1UL : 0UL); -} - -/** - * @brief Configure PLL2 used for 48Mhz domain clock - * @note PLL2 Source, PLLM, PLLN and PLLQ can be written only when PLL2 is disabled. - * @note This can be selected for USB, SDMMC - * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_48M\n - * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_48M\n - * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_48M\n - * PLL2CFGR PLL2Q LL_RCC_PLL2_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL2SOURCE_NONE - * @arg @ref LL_RCC_PLL2SOURCE_MSIS - * @arg @ref LL_RCC_PLL2SOURCE_HSI - * @arg @ref LL_RCC_PLL2SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLQ parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) -{ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ - ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2Q, ((PLLN - 1UL) << \ - RCC_PLL2DIVR_PLL2N_Pos) | ((PLLQ - 1UL) << \ - RCC_PLL2DIVR_PLL2Q_Pos)); -} - -/** - * @brief Configure PLL2 used for SAI domain clock - * @note PLL1 Source, PLLM, PLLN and PLL2P can be written only when PLL1 is disabled. - * @note This can be selected for SAI1 or SAI2 - * @rmtoll PLLC2FGR PLL2SRC LL_RCC_PLL2_ConfigDomain_SAI\n - * PLLC2FGR PLL2M LL_RCC_PLL2_ConfigDomain_SAI\n - * PLLC2FGR PLL2N LL_RCC_PLL2_ConfigDomain_SAI\n - * PLLC2FGR PLL2P LL_RCC_PLL2_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL2SOURCE_NONE - * @arg @ref LL_RCC_PLL2SOURCE_MSIS - * @arg @ref LL_RCC_PLL2SOURCE_HSI - * @arg @ref LL_RCC_PLL2SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLP parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ - ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2P, ((PLLN - 1UL) << \ - RCC_PLL2DIVR_PLL2N_Pos) | ((PLLP - 1UL) << \ - RCC_PLL2DIVR_PLL2P_Pos)); -} - -/** - * @brief Configure PLL2 used for ADC domain clock - * @note PLL2SRC/PLL2M/PLL2N/PLL2R can be written only when PLL2 is disabled. - * @note This can be selected for ADC - * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_ConfigDomain_ADC\n - * PLL2CFGR PLL2M LL_RCC_PLL2_ConfigDomain_ADC\n - * PLL2CFGR PLL2N LL_RCC_PLL2_ConfigDomain_ADC\n - * PLL2CFGR PLL2R LL_RCC_PLL2_ConfigDomain_ADC - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL2SOURCE_NONE - * @arg @ref LL_RCC_PLL2SOURCE_MSIS - * @arg @ref LL_RCC_PLL2SOURCE_HSI - * @arg @ref LL_RCC_PLL2SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLR parameter can be a value between 1 and 128 - * @param PLLN parameter can be a value between 4 and 512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_ConfigDomain_ADC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC | RCC_PLL2CFGR_PLL2M, Source | \ - ((PLLM - 1UL) << RCC_PLL2CFGR_PLL2M_Pos)); - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N | RCC_PLL2DIVR_PLL2R, ((PLLN - 1UL) << \ - RCC_PLL2DIVR_PLL2N_Pos) | ((PLLR - 1UL) << \ - RCC_PLL2DIVR_PLL2R_Pos)); -} - -/** - * @brief Configure PLL2 clock source - * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_SetSource - * @param PLL2Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL2SOURCE_NONE - * @arg @ref LL_RCC_PLL2SOURCE_MSIS - * @arg @ref LL_RCC_PLL2SOURCE_HSI - * @arg @ref LL_RCC_PLL2SOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_SetSource(uint32_t PLL2Source) -{ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC, PLL2Source); -} - -/** - * @brief Get the oscillator used as PLL2 clock source. - * @rmtoll PLL2CFGR PLL2SRC LL_RCC_PLL2_GetSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL2SOURCE_NONE - * @arg @ref LL_RCC_PLL2SOURCE_MSIS - * @arg @ref LL_RCC_PLL2SOURCE_HSI - * @arg @ref LL_RCC_PLL2SOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2SRC)); -} - -/** - * @brief Set Main PLL2 multiplication factor for VCO - * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_SetN - * @param PLL2N parameter can be a value between 4 and 512 - */ -__STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t PLL2N) -{ - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N, (PLL2N - 1UL) << RCC_PLL2DIVR_PLL2N_Pos); -} - -/** - * @brief Get Main PLL2 multiplication factor for VCO - * @rmtoll PLL2CFGR PLL2N LL_RCC_PLL2_GetN - * @retval Between 4 and 512 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1UL); -} - - -/** - * @brief Set Main PLL2 division factor for PLL2P - * @note Used for SAI1 and SAI2 clock - * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_SetP - * @param PLL2P parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t PLL2P) -{ - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P, (PLL2P - 1UL) << RCC_PLL2DIVR_PLL2P_Pos); -} - -/** - * @brief Get Main PLL2 division factor for PLL2P - * @note Used for SAI1 and SAI2 clock - * @rmtoll PLL2CFGR PLL2P LL_RCC_PLL2_GetP - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1UL); -} - - -/** - * @brief Set Main PLL division factor for PLLQ - * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLLCFGR PLL2Q LL_RCC_PLL2_SetQ - * @param PLL2Q parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t PLL2Q) -{ - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q, (PLL2Q - 1UL) << RCC_PLL2DIVR_PLL2Q_Pos); -} - -/** - * @brief Get Main PLL division factor for PLLQ - * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLL2CFGR PLL2Q LL_RCC_PLL2_GetQ - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); -} - -/** - * @brief Set Main PLL division factor for PLLQ - * @note Used for PLL2CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLL2CFGR PLL2R LL_RCC_PLL2_SetR - * @param PLL2R parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t PLL2R) -{ - MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2R, (PLL2R - 1UL) << RCC_PLL2DIVR_PLL2R_Pos); -} - -/** - * @brief Get Main PLL2 division factor for PLL2R - * @note Used for PLL2CLK (system clock) - * @rmtoll PLL2DIVR PLL2R LL_RCC_PLL2_GetR - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1UL); -} - -/** - * @brief Set Division factor for the main PLL and other PLL - * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_SetDivider - * @param PLL2M parameter can be a value between 1 and 16 - */ -__STATIC_INLINE void LL_RCC_PLL2_SetDivider(uint32_t PLL2M) -{ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M, (PLL2M - 1UL) << RCC_PLL2CFGR_PLL2M_Pos); -} - -/** - * @brief Get Division factor for the main PLL and other PLL - * @rmtoll PLL2CFGR PLL2M LL_RCC_PLL2_GetDivider - * @retval Between 1 and 16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetDivider(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1UL); -} - -/** - * @brief Enable PLL2 output mapped on SAI domain clock - * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_EnableDomain_SAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_SAI(void) -{ - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); -} - -/** - * @brief Disable PLL2 output mapped on SAI domain clock - * @note In order to save power, when of the PLL2 is - * not used, should be 0 - * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_DisableDomain_SAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_SAI(void) -{ - CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN); -} - -/** - * @brief Check if PLL2 output mapped on SAI domain clock is enabled - * @rmtoll PLL2CFGR PLL2PEN LL_RCC_PLL2_IsEnabledDomain_SAI - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_SAI(void) -{ - return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN) == (RCC_PLL2CFGR_PLL2PEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable PLL2 output mapped on 48MHz domain clock - * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_EnableDomain_48M - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_48M(void) -{ - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); -} - -/** - * @brief Disable PLL2 output mapped on 48MHz domain clock - * @note In order to save power, when of the PLL2 48M is - * not used, should be 0 - * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_DisableDomain_48M - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_48M(void) -{ - CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN); -} - -/** - * @brief Check if PLL2 output mapped on 48M domain clock is enabled - * @rmtoll PLL2CFGR PLL2QEN LL_RCC_PLL2_IsEnabledDomain_48M - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_48M(void) -{ - return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2QEN) == (RCC_PLL2CFGR_PLL2QEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable PLL2 output mapped on ADC domain clock - * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_EnableDomain_ADC - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_EnableDomain_ADC(void) -{ - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); -} - -/** - * @brief Disable PLL2 output mapped on ADC domain clock - * @note In order to save power, when of the PLL2 ADC is - * not used, Main PLL2ADC should be 0 - * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_DisableDomain_ADC - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_DisableDomain_ADC(void) -{ - CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN); -} - -/** - * @brief Check if PLL2 output mapped on ADC domain clock is enabled - * @rmtoll PLL2CFGR PLL2REN LL_RCC_PLL2_IsEnabledDomain_ADC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_IsEnabledDomain_ADC(void) -{ - return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2REN) == (RCC_PLL2CFGR_PLL2REN)) ? 1UL : 0UL); -} - -/** - * @brief Enable PLL2 FRACN - * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void) -{ - SET_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); -} - -/** - * @brief Check if PLL2 FRACN is enabled - * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void) -{ - return ((READ_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN) == RCC_PLL2CFGR_PLL2FRACEN) ? 1UL : 0UL); -} - -/** - * @brief Disable PLL2 FRACN - * @rmtoll PLL2CFGR PLL2FRACEN LL_RCC_PLL2FRACN_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void) -{ - CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2FRACEN); -} - -/** - * @brief Set PLL2 FRACN Coefficient - * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_SetFRACN - * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) - */ -__STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN) -{ - MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN, FRACN << RCC_PLL2FRACR_PLL2FRACN_Pos); -} - -/** - * @brief Get PLL2 FRACN Coefficient - * @rmtoll PLL2FRACR PLL2FRACN LL_RCC_PLL2_GetFRACN - * @retval A value between 0 and 8191 (0x1FFF) - */ -__STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_PLL2FRACN) >> RCC_PLL2FRACR_PLL2FRACN_Pos); -} - -/** - * @brief Set PLL2 VCO Input Range - * @note This API shall be called only when PLL2 is disabled. - * @rmtoll PLL2CFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange - * @param InputRange This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 - * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange) -{ - MODIFY_REG(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2RGE, InputRange); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PLL3 PLL3 - * @{ - */ - -/** - * @brief Enable PLL3 - * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLL3ON); -} - -/** - * @brief Disable PLL3 - * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); -} - -/** - * @brief Check if PLL3 Ready - * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == RCC_CR_PLL3RDY) ? 1UL : 0UL); -} - -/** - * @brief Configure PLL3 used for SAI domain clock - * @note PLL3SRC/PLL3M/PLL3N/PLL3PDIV can be written only when PLL3 is disabled. - * @note This can be selected for SAI1 or SAI2 - * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_SAI\n - * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_SAI\n - * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_SAI\n - * PLL3DIVR PLL3P LL_RCC_PLL3_ConfigDomain_SAI - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL3SOURCE_NONE - * @arg @ref LL_RCC_PLL3SOURCE_MSIS - * @arg @ref LL_RCC_PLL3SOURCE_HSI - * @arg @ref LL_RCC_PLL3SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLP parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP) -{ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ - ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3P, ((PLLN - 1UL) << \ - RCC_PLL3DIVR_PLL3N_Pos) | ((PLLP - 1UL) << \ - RCC_PLL3DIVR_PLL3P_Pos)); -} - - -/** - * @brief Configure PLL3 used for 48Mhz domain clock - * @note PLL3 Source, PLLM, PLLN and PLLQ can be written only when PLL3 is disabled. - * @note This can be selected for USB, SDMMC - * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_48M\n - * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_48M\n - * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_48M\n - * PLL3CFGR PLL3Q LL_RCC_PLL3_ConfigDomain_48M - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL3SOURCE_NONE - * @arg @ref LL_RCC_PLL3SOURCE_MSIS - * @arg @ref LL_RCC_PLL3SOURCE_HSI - * @arg @ref LL_RCC_PLL3SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLQ parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) -{ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ - ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3Q, ((PLLN - 1UL) << \ - RCC_PLL3DIVR_PLL3N_Pos) | ((PLLQ - 1UL) << \ - RCC_PLL3DIVR_PLL3Q_Pos)); -} - - -#if defined(LTDC) || defined(HSPI1) - -/** - * @brief Configure PLL3 used for HSPI_LTDC domain clock - * @note PLL3 Source, PLLM, PLLN and PLLR can be written only when PLL3 is disabled. - * @note This can be selected for HSPI and LTDC - * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n - * PLL3CFGR PLL3M LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n - * PLL3CFGR PLL3N LL_RCC_PLL3_ConfigDomain_HSPI_LTDC\n - * PLL3CFGR PLL3R LL_RCC_PLL3_ConfigDomain_HSPI_LTDC - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL3SOURCE_NONE - * @arg @ref LL_RCC_PLL3SOURCE_MSIS - * @arg @ref LL_RCC_PLL3SOURCE_HSI - * @arg @ref LL_RCC_PLL3SOURCE_HSE - * @param PLLM parameter can be a value between 1 and 16 - * @param PLLN parameter can be a value between 4 and 512 - * @param PLLR parameter can be a value between 1 and 128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_ConfigDomain_HSPI_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) -{ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC | RCC_PLL3CFGR_PLL3M, Source | \ - ((PLLM - 1UL) << RCC_PLL3CFGR_PLL3M_Pos)); - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N | RCC_PLL3DIVR_PLL3R, ((PLLN - 1UL) << \ - RCC_PLL3DIVR_PLL3N_Pos) | ((PLLR - 1UL) << \ - RCC_PLL3DIVR_PLL3R_Pos)); -} - -#endif /* LTDC || HSPI1 */ - -/** - * @brief Configure PLL3 clock source - * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_SetSource - * @param PLLSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PLL3SOURCE_NONE - * @arg @ref LL_RCC_PLL3SOURCE_MSIS - * @arg @ref LL_RCC_PLL3SOURCE_HSI - * @arg @ref LL_RCC_PLL3SOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_SetSource(uint32_t PLLSource) -{ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC, PLLSource); -} - -/** - * @brief Get the oscillator used as PLL3 clock source. - * @rmtoll PLL3CFGR PLL3SRC LL_RCC_PLL3_GetSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLL3SOURCE_NONE - * @arg @ref LL_RCC_PLL3SOURCE_MSIS - * @arg @ref LL_RCC_PLL3SOURCE_HSI - * @arg @ref LL_RCC_PLL3SOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3SRC)); -} - -/** - * @brief Set Main PLL3 multiplication factor for VCO - * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_SetN - * @param PLL3N parameter can be a value between 4 and 512 - */ -__STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t PLL3N) -{ - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N, (PLL3N - 1UL) << RCC_PLL3DIVR_PLL3N_Pos); -} - -/** - * @brief Get Main PLL3 multiplication factor for VCO - * @rmtoll PLL3CFGR PLL3N LL_RCC_PLL3_GetN - * @retval Between 4 and 512 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1UL); -} - - -/** - * @brief Set Main PLL3 division factor for PLL3P - * @note Used for SAI1 and SAI2 clock - * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_SetP - * @param PLL3P parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t PLL3P) -{ - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P, (PLL3P - 1UL) << RCC_PLL3DIVR_PLL3P_Pos); -} - -/** - * @brief Get Main PLL3 division factor for PLL3P - * @note Used for SAI1 and SAI2 clock - * @rmtoll PLL3CFGR PLL3P LL_RCC_PLL3_GetP - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1UL); -} - - -/** - * @brief Set Main PLL division factor for PLLQ - * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLLCFGR PLL3Q LL_RCC_PLL3_SetQ - * @param PLL3Q parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t PLL3Q) -{ - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q, (PLL3Q - 1UL) << RCC_PLL3DIVR_PLL3Q_Pos); -} - -/** - * @brief Get Main PLL division factor for PLLQ - * @note Used for PLL48M1CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLL3CFGR PLL3Q LL_RCC_PLL3_GetQ - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1UL); -} - -/** - * @brief Set Main PLL division factor for PLLQ - * @note Used for PLL3CLK selected for USB, SDMMC (48 MHz clock) - * @rmtoll PLL3CFGR PLL3R LL_RCC_PLL3_SetR - * @param PLL3R parameter can be a value between 1 and 128 - */ -__STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t PLL3R) -{ - MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R, (PLL3R - 1UL) << RCC_PLL3DIVR_PLL3R_Pos); -} - -/** - * @brief Get Main PLL3 division factor for PLL3R - * @note Used for PLL3CLK (system clock) - * @rmtoll PLL3DIVR PLL3R LL_RCC_PLL3_GetR - * @retval Between 1 and 128 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1UL); -} - -/** - * @brief Set Division factor for the main PLL and other PLL - * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_SetDivider - * @param PLL3M parameter can be a value between 1 and 16 - */ -__STATIC_INLINE void LL_RCC_PLL3_SetDivider(uint32_t PLL3M) -{ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M, (PLL3M - 1UL) << RCC_PLL3CFGR_PLL3M_Pos); -} - -/** - * @brief Get Division factor for the main PLL and other PLL - * @rmtoll PLL3CFGR PLL3M LL_RCC_PLL3_GetDivider - * @retval Between 1 and 16 - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetDivider(void) -{ - return (uint32_t)((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1UL); -} - -/** - * @brief Enable PLL3 output mapped on SAI domain clock - * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_EnableDomain_SAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_SAI(void) -{ - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); -} - -/** - * @brief Disable PLL3 output mapped on SAI domain clock - * @note In order to save power, when of the PLLSAI2 is - * not used, should be 0 - * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_DisableDomain_SAI - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_SAI(void) -{ - CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN); -} - -/** - * @brief Check if PLL3 output mapped on SAI domain clock is enabled - * @rmtoll PLL3CFGR PLL3PEN LL_RCC_PLL3_IsEnabledDomain_SAI - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_SAI(void) -{ - return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN) == (RCC_PLL3CFGR_PLL3PEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable PLL2 output mapped on 48MHz domain clock - * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_EnableDomain_48M - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_48M(void) -{ - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); -} - -/** - * @brief Disable PLL3 output mapped on 48MHz domain clock - * @note In order to save power, when of the PLL3 is - * not used, should be 0 - * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_DisableDomain_48M - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_48M(void) -{ - CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN); -} - -/** - * @brief Check if PLL3 output mapped on 48M domain clock is enabled - * @rmtoll PLL3CFGR PLL3QEN LL_RCC_PLL3_IsEnabledDomain_48M - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_48M(void) -{ - return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3QEN) == (RCC_PLL3CFGR_PLL3QEN)) ? 1UL : 0UL); -} - -#if defined(LTDC) || defined(HSPI1) - -/** - * @brief Enable PLL3 output mapped on HSPI_LTDC domain clock - * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_EnableDomain_HSPI_LTDC - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_EnableDomain_HSPI_LTDC(void) -{ - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); -} - -/** - * @brief Disable PLL3 output mapped on HSPI_LTDC domain clock - * @note In order to save power, when of the PLL3 is - * not used, should be 0 - * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_DisableDomain_HSPI_LTDC - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_DisableDomain_HSPI_LTDC(void) -{ - CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN); -} - -/** - * @brief Check if PLL3 output mapped on HSPI_LTDC domain clock is enabled - * @rmtoll PLL3CFGR PLL3REN LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_IsEnabledDomain_HSPI_LTDC(void) -{ - return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3REN) == (RCC_PLL3CFGR_PLL3REN)) ? 1UL : 0UL); -} - -#endif /* LTDC || HSPI1 */ - - -/** - * @brief Enable PLL3 FRACN - * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void) -{ - SET_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); -} - -/** - * @brief Check if PLL3 FRACN is enabled - * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void) -{ - return ((READ_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN) == RCC_PLL3CFGR_PLL3FRACEN) ? 1UL : 0UL); -} - -/** - * @brief Disable PLL3 FRACN - * @rmtoll PLL3CFGR PLL3FRACEN LL_RCC_PLL3FRACN_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void) -{ - CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3FRACEN); -} - -/** - * @brief Set PLL3 FRACN Coefficient - * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_SetFRACN - * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF) - */ -__STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN) -{ - MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN, FRACN << RCC_PLL3FRACR_PLL3FRACN_Pos); -} - -/** - * @brief Get PLL3 FRACN Coefficient - * @rmtoll PLL3FRACR PLL3FRACN LL_RCC_PLL3_GetFRACN - * @retval A value between 0 and 8191 (0x1FFF) - */ -__STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void) -{ - return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_PLL3FRACN) >> RCC_PLL3FRACR_PLL3FRACN_Pos); -} - -/** - * @brief Set PLL3 VCO Input Range - * @note This API shall be called only when PLL3 is disabled. - * @rmtoll PLL3CFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange - * @param InputRange This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLINPUTRANGE_4_8 - * @arg @ref LL_RCC_PLLINPUTRANGE_8_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange) -{ - MODIFY_REG(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3RGE, InputRange); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_PRIV Privileged mode - * @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable Secure Privileged mode - * @rmtoll PRIVCFGR SPRIV LL_RCC_EnableSecPrivilegedMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableSecPrivilegedMode(void) -{ - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); -} - -/** - * @brief Disable Secure Privileged mode - * @rmtoll PRIVCFGR SPRIV LL_RCC_DisableSecPrivilegedMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableSecPrivilegedMode(void) -{ - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); -} - -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Check if Secure Privileged mode has been enabled or not - * @rmtoll PRIVCFGR SPRIV LL_RCC_IsEnabledSecPrivilegedMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledSecPrivilegedMode(void) -{ - return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); -} - -/** - * @brief Enable Non Secure Privileged mode - * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnableNSecPrivilegedMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableNSecPrivilegedMode(void) -{ - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); -} - -/** - * @brief Disable Non Secure Privileged mode - * @rmtoll PRIVCFGR NSPRIV LL_RCC_DisableNSecPrivilegedMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableNSecPrivilegedMode(void) -{ - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); -} - -/** - * @brief Check if Non Secure Privileged mode has been enabled or not - * @rmtoll PRIVCFGR NSPRIV LL_RCC_IsEnabledNSecPrivilegedMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledNSecPrivilegedMode(void) -{ - return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); -} - - -/** - * @brief Enable privileged mode - * @note User should use LL_RCC_EnableSecPrivilegedMode() to enable Secure privilege - * User should use LL_RCC_EnableNSecPrivilegedMode() to enable Non-secure privilege - * This API is kept for legacy purpose only - * @rmtoll PRIVCFGR SPRIV LL_RCC_EnablePrivilegedMode - * @rmtoll PRIVCFGR NSPRIV LL_RCC_EnablePrivilegedMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnablePrivilegedMode(void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); -#else - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ -} - -/** - * @brief Disable Privileged mode - * @note User should use LL_RCC_DisableSecPrivilegedMode() to disable Secure privilege - * User should use LL_RCC_DisableNSecPrivilegedMode() to disable Non-secure privilege - * This API is kept for legacy purpose only - * @rmtoll CR PRIV LL_RCC_DisablePrivilegedMode - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisablePrivilegedMode(void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); -#else - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ -} - -/** - * @brief Check if Privileged mode has been enabled or not - * @note User should use LL_RCC_IsEnabledSecPrivilegedMode() to check Secure privilege setting - * User should use LL_RCC_IsEnabledNSecPrivilegedMode() to check Non-secure privilege setting - * This API is kept for legacy purpose only - * @rmtoll CR PRIV LL_RCC_IsEnabledPrivilegedMode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledPrivilegedMode(void) -{ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV) == RCC_PRIVCFGR_SPRIV) ? 1UL : 0UL); -#else - return ((READ_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV) == RCC_PRIVCFGR_NSPRIV) ? 1UL : 0UL); -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); -} - -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); -} - -/** - * @brief Clear MSI ready interrupt flag - * @rmtoll CICR MSISRDYC LL_RCC_ClearFlag_MSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_MSIRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_MSISRDYC); -} - -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); -} - - -/** - * @brief Clear HSI48 ready interrupt flag - * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC); -} - -/** - * @brief Clear PLL1 ready interrupt flag - * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_PLL1RDYC); -} - -/** - * @brief Clear PLL2 ready interrupt flag - * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC); -} - -/** - * @brief Clear PLL3 ready interrupt flag - * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC); -} - -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_CSSC); -} - -/** - * @brief Clear MSIK ready interrupt flag - * @rmtoll CICR MSIKRDYC LL_RCC_ClearFlag_MSIKRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_MSIKRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_MSIKRDYC); -} - -/** - * @brief Clear SHSI ready interrupt flag - * @rmtoll CICR SHSIRDYC LL_RCC_ClearFlag_SHSIRDY - * @retval None - */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -__STATIC_INLINE void LL_RCC_ClearFlag_SHSIRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_SHSIRDYC); -} -#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ - - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == RCC_CIFR_LSIRDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == RCC_CIFR_LSERDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if MSI ready interrupt occurred or not - * @rmtoll CIFR MSISRDYF LL_RCC_IsActiveFlag_MSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSISRDYF) == RCC_CIFR_MSISRDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == RCC_CIFR_HSIRDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == RCC_CIFR_HSERDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if HSI48 ready interrupt occurred or not - * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == RCC_CIFR_HSI48RDYF) ? 1UL : 0UL); -} -/** - * @brief Check if PLL1 ready interrupt occurred or not - * @rmtoll CIFR PLL1RDYF LL_RCC_IsActiveFlag_PLL1RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL1RDYF) == RCC_CIFR_PLL1RDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if PLL2 ready interrupt occurred or not - * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == RCC_CIFR_PLL2RDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if PLL3 ready interrupt occurred or not - * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == RCC_CIFR_PLL3RDYF) ? 1UL : 0UL); -} - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == RCC_CIFR_CSSF) ? 1UL : 0UL); -} - -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIFR MSIKRDYF LL_RCC_IsActiveFlag_MSIKRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_MSIKRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_MSIKRDYF) == RCC_CIFR_MSIKRDYF) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIFR SHSIRDYF LL_RCC_IsActiveFlag_SHSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHSIRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_SHSIRDYF) == RCC_CIFR_SHSIRDYF) ? 1UL : 0UL); -} -#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == RCC_CSR_IWDGRSTF) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Low Power reset is set or not. - * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == RCC_CSR_LPWRRSTF) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag is set or not. - * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == RCC_CSR_OBLRSTF) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == RCC_CSR_PINRSTF) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == RCC_CSR_SFTRSTF) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == RCC_CSR_WWDGRSTF) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag BOR reset is set or not. - * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == RCC_CSR_BORRSTF) ? 1UL : 0UL); -} - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); -} - -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); -} - -/** - * @brief Enable MSI ready interrupt - * @rmtoll CIER MSIRDYIE LL_RCC_EnableIT_MSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_MSIRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_MSISRDYIE); -} - -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); -} - -/** - * @brief Enable HSI48 ready interrupt - * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); -} - -/** - * @brief Enable PLL1 ready interrupt - * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); -} - -/** - * @brief Enable PLL2 ready interrupt - * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); -} - -/** - * @brief Enable PLL3 ready interrupt - * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); -} - -/** - * @brief Enable MSIKRDYIE ready interrupt - * @rmtoll CIER MSIKRDYIE LL_RCC_EnableIT_MSIKRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_MSIKRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable SHSIRDYIE ready interrupt - * @rmtoll CIER SHSIRDYIE LL_RCC_EnableIT_SHSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_SHSIRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE); -} -#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ - -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); -} - -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); -} - -/** - * @brief Disable MSI ready interrupt - * @rmtoll CIER MSISRDYIE LL_RCC_DisableIT_MSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_MSIRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_MSISRDYIE); -} - -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); -} - -/** - * @brief Disable HSI48 ready interrupt - * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE); -} - -/** - * @brief Disable PLL1 ready interrupt - * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE); -} - -/** - * @brief Disable PLL2 ready interrupt - * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE); -} - -/** - * @brief Disable PLL3 ready interrupt - * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE); -} - -/** - * @brief Disable MSIKRDYIE ready interrupt - * @rmtoll CIER MSIKRDYIE LL_RCC_DisableIT_MSIKRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_MSIKRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Disable SHSIRDYIE ready interrupt - * @rmtoll CIER SHSIRDYIE LL_RCC_DisableIT_SHSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_SHSIRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE); -} -#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ - -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if MSI ready interrupt source is enabled or disabled. - * @rmtoll CIER MSIRDYIE LL_RCC_IsEnabledIT_MSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_MSISRDYIE) == RCC_CIER_MSISRDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if HSI48 ready interrupt source is enabled or disabled. - * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnabledIT_HSI48RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSI48RDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL); -} -/** - * @brief Checks if PLL1 ready interrupt source is enabled or disabled. - * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnabledIT_PLL1RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL1RDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if PLL2 ready interrupt source is enabled or disabled. - * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnabledIT_PLL2RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL2RDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if PLL3 ready interrupt source is enabled or disabled. - * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnabledIT_PLL3RDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLL3RDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL); -} - -/** - * @brief Checks if MSIK ready interrupt source is enabled or disabled. - * @rmtoll CIER MSIKRDYIE LL_RCC_IsEnabledIT_MSIKRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_MSIKRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_MSIKRDYIE) == RCC_CIER_MSIKRDYIE) ? 1UL : 0UL); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Checks if SHSI ready interrupt source is enabled or disabled. - * @rmtoll CIER SHSIRDYIE LL_RCC_IsEnabledIT_SHSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_SHSIRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_SHSIRDYIE) == RCC_CIER_SHSIRDYIE) ? 1UL : 0UL); -} -#endif /*(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)*/ - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Security_Services Security Services - * @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure RCC resources security - * @note Only available from secure state when system implements security (TZEN=1) - * @rmtoll SECCFGR HSISEC LL_RCC_ConfigSecure\n - * SECCFGR HSESEC LL_RCC_ConfigSecure\n - * SECCFGR MSISEC LL_RCC_ConfigSecure\n - * SECCFGR LSISEC LL_RCC_ConfigSecure\n - * SECCFGR LSESEC LL_RCC_ConfigSecure\n - * SECCFGR SYSCLKSEC LL_RCC_ConfigSecure\n - * SECCFGR PRESCSEC LL_RCC_ConfigSecure\n - * SECCFGR PLL1SEC LL_RCC_ConfigSecure\n - * SECCFGR PLL2SEC LL_RCC_ConfigSecure\n - * SECCFGR PLL3SEC LL_RCC_ConfigSecure\n - * SECCFGR CLK48MSEC LL_RCC_ConfigSecure\n - * SECCFGR HSI48SEC LL_RCC_ConfigSecure\n - * SECCFGR RMVFSEC LL_RCC_ConfigSecure - * @param SecureConfig This parameter can be one or a combination of the following values: - * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC - * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC - * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC - * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC - * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC - * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC - * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC - * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC - * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC - * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC - * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC - * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC - * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC - * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigSecure(uint32_t SecureConfig) -{ - WRITE_REG(RCC->SECCFGR, SecureConfig); -} -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Get RCC resources security status - * @note Only available from secure state when system implements security (TZEN=1) - * @rmtoll SECCFGR HSISEC LL_RCC_GetConfigSecure\n - * SECCFGR HSESEC LL_RCC_GetConfigSecure\n - * SECCFGR MSISEC LL_RCC_GetConfigSecure\n - * SECCFGR LSISEC LL_RCC_GetConfigSecure\n - * SECCFGR LSESEC LL_RCC_GetConfigSecure\n - * SECCFGR SYSCLKSEC LL_RCC_GetConfigSecure\n - * SECCFGR PRESCSEC LL_RCC_GetConfigSecure\n - * SECCFGR PLL1SEC LL_RCC_GetConfigSecure\n - * SECCFGR PLL2SEC LL_RCC_GetConfigSecure\n - * SECCFGR PLL3SEC LL_RCC_GetConfigSecure\n - * SECCFGR CLK48MSEC LL_RCC_GetConfigSecure\n - * SECCFGR HSI48SEC LL_RCC_GetConfigSecure\n - * SECCFGR RMVFSEC LL_RCC_GetConfigSecure - * @retval Returned value can be one or a combination of the following values: - * @arg @ref LL_RCC_ALL_NSEC & LL_RCC_ALL_SEC - * @arg @ref LL_RCC_HSI_SEC & LL_RCC_HSI_NSEC - * @arg @ref LL_RCC_HSE_SEC & LL_RCC_HSE_NSEC - * @arg @ref LL_RCC_MSI_SEC & LL_RCC_MSI_NSEC - * @arg @ref LL_RCC_LSE_SEC & LL_RCC_LSE_NSEC - * @arg @ref LL_RCC_LSI_SEC & LL_RCC_LSI_NSEC - * @arg @ref LL_RCC_SYSCLK_SEC & LL_RCC_SYSCLK_NSEC - * @arg @ref LL_RCC_PRESCALERS_SEC & LL_RCC_PRESCALERS_NSEC - * @arg @ref LL_RCC_PLL1_SEC & LL_RCC_PLL1_NSEC - * @arg @ref LL_RCC_PLL2_SEC & LL_RCC_PLL2_NSEC - * @arg @ref LL_RCC_PLL3_SEC & LL_RCC_PLL3_NSEC - * @arg @ref LL_RCC_CLK48M_SEC & LL_RCC_CLK48M_NSEC - * @arg @ref LL_RCC_HSI48_SEC & LL_RCC_HSI48_NSEC - * @arg @ref LL_RCC_RESET_FLAGS_SEC & LL_RCC_RESET_FLAGS_NSEC - * @retval None - */ -__STATIC_INLINE uint32_t LL_RCC_GetConfigSecure(void) -{ - return (uint32_t)(READ_BIT(RCC->SECCFGR, RCC_SECURE_MASK)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource); -uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource); -uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource); -uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource); -uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource); -uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource); -uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource); -uint32_t LL_RCC_GetSDMMCKernelClockFreq(uint32_t SDMMCxSource); -uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource); -uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource); -uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource); -uint32_t LL_RCC_GetADCDACClockFreq(uint32_t ADCxSource); -uint32_t LL_RCC_GetADF1ClockFreq(uint32_t ADF1Source); -uint32_t LL_RCC_GetMDF1ClockFreq(uint32_t MDF1Source); -uint32_t LL_RCC_GetDAC1ClockFreq(uint32_t DAC1Source); -uint32_t LL_RCC_GetOCTOSPIClockFreq(uint32_t OCTOSPIxSource); -#if defined(SAES) -uint32_t LL_RCC_GetSAESClockFreq(uint32_t SAESxSource); -#endif /* SAES */ -uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource); -#if defined(DSI) -uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource); -#endif /* DSI */ -#if defined(HSPI1) -uint32_t LL_RCC_GetHSPIClockFreq(uint32_t HSPIxSource); -#endif /* HSPI1 */ -#if defined(LTDC) -uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource); -#endif /* defined(LTDC) */ -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32u5xx_LL_RCC_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h deleted file mode 100644 index 028747fd3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_spi.h +++ /dev/null @@ -1,2744 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_spi.h - * @author MCD Application Team - * @brief Header file of SPI LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_SPI_H -#define STM32U5xx_LL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(SPI1) || defined(SPI2) || defined(SPI3) - -/** @defgroup SPI_LL SPI - * @{ - */ - -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** Legacy definitions for compatibility purpose -@cond 0 - */ -#define LL_SPI_UNDERRUN_BEHAV_LAST_RECEIVED LL_SPI_UDR_CONFIG_LAST_RECEIVED -/** -@endcond - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SPI_LL_Private_Macros SPI Private Macros - * @{ - */ -#if defined(IS_SPI_GRP2_INSTANCE) -#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) -#define IS_LL_SPI_GRP2_INSTANCE(__INSTANCE__) IS_SPI_GRP2_INSTANCE(__INSTANCE__) -#else -#define IS_LL_SPI_GRP1_INSTANCE(__INSTANCE__) IS_SPI_GRP1_INSTANCE(__INSTANCE__) -#endif /* SPI_TRIG_GRP2 */ -/** - * @} - */ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_Exported_Types SPI Exported Types - * @{ - */ - -/** - * @brief SPI Init structures definition - */ -typedef struct -{ - uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetTransferDirection().*/ - - uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_LL_EC_MODE. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetMode().*/ - - uint32_t DataWidth; /*!< Specifies the SPI data width. - This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetDataWidth().*/ - - uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_LL_EC_POLARITY. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetClockPolarity().*/ - - uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_LL_EC_PHASE. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetClockPhase().*/ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) - or by software using the SSI bit. - - This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetNSSMode().*/ - - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure - the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. - The slave clock does not need to be set. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetBaudRatePrescaler().*/ - - uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetTransferBitOrder().*/ - - uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. - This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - - This feature can be modified afterwards using unitary functions - @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ - - uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. - This parameter must be a number between Min_Data = 0x00 - and Max_Data = 0xFFFFFFFF. - - This feature can be modified afterwards using unitary function - @ref LL_SPI_SetCRCPolynomial().*/ - -} LL_SPI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants - * @{ - */ - -/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_SPI_ReadReg function - * @{ - */ -#define LL_SPI_SR_RXP (SPI_SR_RXP) -#define LL_SPI_SR_TXP (SPI_SR_TXP) -#define LL_SPI_SR_DXP (SPI_SR_DXP) -#define LL_SPI_SR_EOT (SPI_SR_EOT) -#define LL_SPI_SR_TXTF (SPI_SR_TXTF) -#define LL_SPI_SR_UDR (SPI_SR_UDR) -#define LL_SPI_SR_CRCE (SPI_SR_CRCE) -#define LL_SPI_SR_MODF (SPI_SR_MODF) -#define LL_SPI_SR_OVR (SPI_SR_OVR) -#define LL_SPI_SR_TIFRE (SPI_SR_TIFRE) -#define LL_SPI_SR_SUSP (SPI_SR_SUSP) -#define LL_SPI_SR_TXC (SPI_SR_TXC) -#define LL_SPI_SR_RXWNE (SPI_SR_RXWNE) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions - * @{ - */ -#define LL_SPI_IER_RXPIE (SPI_IER_RXPIE) -#define LL_SPI_IER_TXPIE (SPI_IER_TXPIE) -#define LL_SPI_IER_DXPIE (SPI_IER_DXPIE) -#define LL_SPI_IER_EOTIE (SPI_IER_EOTIE) -#define LL_SPI_IER_TXTFIE (SPI_IER_TXTFIE) -#define LL_SPI_IER_UDRIE (SPI_IER_UDRIE) -#define LL_SPI_IER_OVRIE (SPI_IER_OVRIE) -#define LL_SPI_IER_CRCEIE (SPI_IER_CRCEIE) -#define LL_SPI_IER_TIFREIE (SPI_IER_TIFREIE) -#define LL_SPI_IER_MODFIE (SPI_IER_MODFIE) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_MODE Mode - * @{ - */ -#define LL_SPI_MODE_MASTER (SPI_CFG2_MASTER) -#define LL_SPI_MODE_SLAVE (0x00000000UL) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_SS_LEVEL SS Level - * @{ - */ -#define LL_SPI_SS_LEVEL_HIGH (SPI_CR1_SSI) -#define LL_SPI_SS_LEVEL_LOW (0x00000000UL) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_SS_IDLENESS SS Idleness - * @{ - */ -#define LL_SPI_SS_IDLENESS_00CYCLE (0x00000000UL) -#define LL_SPI_SS_IDLENESS_01CYCLE (SPI_CFG2_MSSI_0) -#define LL_SPI_SS_IDLENESS_02CYCLE (SPI_CFG2_MSSI_1) -#define LL_SPI_SS_IDLENESS_03CYCLE (SPI_CFG2_MSSI_0 | SPI_CFG2_MSSI_1) -#define LL_SPI_SS_IDLENESS_04CYCLE (SPI_CFG2_MSSI_2) -#define LL_SPI_SS_IDLENESS_05CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) -#define LL_SPI_SS_IDLENESS_06CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) -#define LL_SPI_SS_IDLENESS_07CYCLE (SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) -#define LL_SPI_SS_IDLENESS_08CYCLE (SPI_CFG2_MSSI_3) -#define LL_SPI_SS_IDLENESS_09CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_0) -#define LL_SPI_SS_IDLENESS_10CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1) -#define LL_SPI_SS_IDLENESS_11CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) -#define LL_SPI_SS_IDLENESS_12CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2) -#define LL_SPI_SS_IDLENESS_13CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_0) -#define LL_SPI_SS_IDLENESS_14CYCLE (SPI_CFG2_MSSI_3 | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1) -#define LL_SPI_SS_IDLENESS_15CYCLE (SPI_CFG2_MSSI_3\ - | SPI_CFG2_MSSI_2 | SPI_CFG2_MSSI_1 | SPI_CFG2_MSSI_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_ID_IDLENESS Master Inter-Data Idleness - * @{ - */ -#define LL_SPI_ID_IDLENESS_00CYCLE (0x00000000UL) -#define LL_SPI_ID_IDLENESS_01CYCLE (SPI_CFG2_MIDI_0) -#define LL_SPI_ID_IDLENESS_02CYCLE (SPI_CFG2_MIDI_1) -#define LL_SPI_ID_IDLENESS_03CYCLE (SPI_CFG2_MIDI_0 | SPI_CFG2_MIDI_1) -#define LL_SPI_ID_IDLENESS_04CYCLE (SPI_CFG2_MIDI_2) -#define LL_SPI_ID_IDLENESS_05CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) -#define LL_SPI_ID_IDLENESS_06CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) -#define LL_SPI_ID_IDLENESS_07CYCLE (SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) -#define LL_SPI_ID_IDLENESS_08CYCLE (SPI_CFG2_MIDI_3) -#define LL_SPI_ID_IDLENESS_09CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_0) -#define LL_SPI_ID_IDLENESS_10CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1) -#define LL_SPI_ID_IDLENESS_11CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) -#define LL_SPI_ID_IDLENESS_12CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2) -#define LL_SPI_ID_IDLENESS_13CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_0) -#define LL_SPI_ID_IDLENESS_14CYCLE (SPI_CFG2_MIDI_3 | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1) -#define LL_SPI_ID_IDLENESS_15CYCLE (SPI_CFG2_MIDI_3\ - | SPI_CFG2_MIDI_2 | SPI_CFG2_MIDI_1 | SPI_CFG2_MIDI_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_TXCRCINIT_ALL TXCRC Init All - * @{ - */ -#define LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) -#define LL_SPI_TXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_TCRCINI) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_RXCRCINIT_ALL RXCRC Init All - * @{ - */ -#define LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN (0x00000000UL) -#define LL_SPI_RXCRCINIT_ALL_ONES_PATTERN (SPI_CR1_RCRCINI) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_UDR_CONFIG_REGISTER UDR Config Register - * @{ - */ -#define LL_SPI_UDR_CONFIG_REGISTER_PATTERN (0x00000000UL) -#define LL_SPI_UDR_CONFIG_LAST_RECEIVED (SPI_CFG1_UDRCFG) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_PROTOCOL Protocol - * @{ - */ -#define LL_SPI_PROTOCOL_MOTOROLA (0x00000000UL) -#define LL_SPI_PROTOCOL_TI (SPI_CFG2_SP_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_PHASE Phase - * @{ - */ -#define LL_SPI_PHASE_1EDGE (0x00000000UL) -#define LL_SPI_PHASE_2EDGE (SPI_CFG2_CPHA) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_POLARITY Polarity - * @{ - */ -#define LL_SPI_POLARITY_LOW (0x00000000UL) -#define LL_SPI_POLARITY_HIGH (SPI_CFG2_CPOL) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_NSS_POLARITY NSS Polarity - * @{ - */ -#define LL_SPI_NSS_POLARITY_LOW (0x00000000UL) -#define LL_SPI_NSS_POLARITY_HIGH (SPI_CFG2_SSIOP) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler - * @{ - */ -#define LL_SPI_BAUDRATEPRESCALER_BYPASS (SPI_CFG1_BPASS) -#define LL_SPI_BAUDRATEPRESCALER_DIV2 (0x00000000UL) -#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CFG1_MBR_0) -#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CFG1_MBR_1) -#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) -#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CFG1_MBR_2) -#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_0) -#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1) -#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CFG1_MBR_2 | SPI_CFG1_MBR_1 | SPI_CFG1_MBR_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_BIT_ORDER Bit Order - * @{ - */ -#define LL_SPI_LSB_FIRST (SPI_CFG2_LSBFRST) -#define LL_SPI_MSB_FIRST (0x00000000UL) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode - * @{ - */ -#define LL_SPI_FULL_DUPLEX (0x00000000UL) -#define LL_SPI_SIMPLEX_TX (SPI_CFG2_COMM_0) -#define LL_SPI_SIMPLEX_RX (SPI_CFG2_COMM_1) -#define LL_SPI_HALF_DUPLEX_RX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1) -#define LL_SPI_HALF_DUPLEX_TX (SPI_CFG2_COMM_0|SPI_CFG2_COMM_1|SPI_CR1_HDDIR) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_DATAWIDTH Data Width - * @{ - */ -#define LL_SPI_DATAWIDTH_4BIT (SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_5BIT (SPI_CFG1_DSIZE_2) -#define LL_SPI_DATAWIDTH_6BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_7BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_8BIT (SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_9BIT (SPI_CFG1_DSIZE_3) -#define LL_SPI_DATAWIDTH_10BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_11BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_12BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_13BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) -#define LL_SPI_DATAWIDTH_14BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_15BIT (SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_16BIT (SPI_CFG1_DSIZE_3\ - | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_17BIT (SPI_CFG1_DSIZE_4) -#define LL_SPI_DATAWIDTH_18BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_19BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_20BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_0 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_21BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2) -#define LL_SPI_DATAWIDTH_22BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_23BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_24BIT (SPI_CFG1_DSIZE_4\ - | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_25BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3) -#define LL_SPI_DATAWIDTH_26BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_27BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_28BIT (SPI_CFG1_DSIZE_4\ - | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_29BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2) -#define LL_SPI_DATAWIDTH_30BIT (SPI_CFG1_DSIZE_4\ - | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_0) -#define LL_SPI_DATAWIDTH_31BIT (SPI_CFG1_DSIZE_4\ - | SPI_CFG1_DSIZE_3 | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1) -#define LL_SPI_DATAWIDTH_32BIT (SPI_CFG1_DSIZE_4 | SPI_CFG1_DSIZE_3\ - | SPI_CFG1_DSIZE_2 | SPI_CFG1_DSIZE_1 | SPI_CFG1_DSIZE_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_FIFO_TH FIFO Threshold - * @{ - */ -#define LL_SPI_FIFO_TH_01DATA (0x00000000UL) -#define LL_SPI_FIFO_TH_02DATA (SPI_CFG1_FTHLV_0) -#define LL_SPI_FIFO_TH_03DATA (SPI_CFG1_FTHLV_1) -#define LL_SPI_FIFO_TH_04DATA (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) -#define LL_SPI_FIFO_TH_05DATA (SPI_CFG1_FTHLV_2) -#define LL_SPI_FIFO_TH_06DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) -#define LL_SPI_FIFO_TH_07DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) -#define LL_SPI_FIFO_TH_08DATA (SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) -#define LL_SPI_FIFO_TH_09DATA (SPI_CFG1_FTHLV_3) -#define LL_SPI_FIFO_TH_10DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_0) -#define LL_SPI_FIFO_TH_11DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1) -#define LL_SPI_FIFO_TH_12DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) -#define LL_SPI_FIFO_TH_13DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2) -#define LL_SPI_FIFO_TH_14DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_0) -#define LL_SPI_FIFO_TH_15DATA (SPI_CFG1_FTHLV_3 | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1) -#define LL_SPI_FIFO_TH_16DATA (SPI_CFG1_FTHLV_3\ - | SPI_CFG1_FTHLV_2 | SPI_CFG1_FTHLV_1 | SPI_CFG1_FTHLV_0) -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation - * @{ - */ -#define LL_SPI_CRCCALCULATION_DISABLE (0x00000000UL) /*!< CRC calculation disabled */ -#define LL_SPI_CRCCALCULATION_ENABLE (SPI_CFG1_CRCEN) /*!< CRC calculation enabled */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup SPI_LL_EC_CRC CRC - * @{ - */ -#define LL_SPI_CRC_4BIT (SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_5BIT (SPI_CFG1_CRCSIZE_2) -#define LL_SPI_CRC_6BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_7BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_8BIT (SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_9BIT (SPI_CFG1_CRCSIZE_3) -#define LL_SPI_CRC_10BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_11BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_12BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_13BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) -#define LL_SPI_CRC_14BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_15BIT (SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_16BIT (SPI_CFG1_CRCSIZE_3\ - | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_17BIT (SPI_CFG1_CRCSIZE_4) -#define LL_SPI_CRC_18BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_19BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_20BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_0 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_21BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2) -#define LL_SPI_CRC_22BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_23BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_24BIT (SPI_CFG1_CRCSIZE_4\ - | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_25BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3) -#define LL_SPI_CRC_26BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_27BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_28BIT (SPI_CFG1_CRCSIZE_4\ - | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_29BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2) -#define LL_SPI_CRC_30BIT (SPI_CFG1_CRCSIZE_4\ - | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_0) -#define LL_SPI_CRC_31BIT (SPI_CFG1_CRCSIZE_4\ - | SPI_CFG1_CRCSIZE_3 | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1) -#define LL_SPI_CRC_32BIT (SPI_CFG1_CRCSIZE_4 | SPI_CFG1_CRCSIZE_3\ - | SPI_CFG1_CRCSIZE_2 | SPI_CFG1_CRCSIZE_1 | SPI_CFG1_CRCSIZE_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_NSS_MODE NSS Mode - * @{ - */ -#define LL_SPI_NSS_SOFT (SPI_CFG2_SSM) -#define LL_SPI_NSS_HARD_INPUT (0x00000000UL) -#define LL_SPI_NSS_HARD_OUTPUT (SPI_CFG2_SSOE) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_RX_FIFO RxFIFO Packing LeVel - * @{ - */ -#define LL_SPI_RX_FIFO_0PACKET (0x00000000UL) /* 0 or multiple of 4 packet available is the RxFIFO */ -#define LL_SPI_RX_FIFO_1PACKET (SPI_SR_RXPLVL_0) -#define LL_SPI_RX_FIFO_2PACKET (SPI_SR_RXPLVL_1) -#define LL_SPI_RX_FIFO_3PACKET (SPI_SR_RXPLVL_1 | SPI_SR_RXPLVL_0) -/** - * @} - */ - -/** @defgroup SPI_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger selection - * @brief SPI Autonomous Trigger selection - * @{ - */ -#define LL_SPI_TRIG_GRP1 (0x10000000U) /*!< Trigger Group for SPI1 and SPI2 */ -#if defined(SPI3) -#define LL_SPI_TRIG_GRP2 (0x20000000U) /*!< Trigger Group for SPI3 */ -#endif /* SPI3 */ - -/*!< HW Trigger signal is GPDMA_CH0_TRG */ -#define LL_SPI_GRP1_GPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x00000000U)) -/*!< HW Trigger signal is GPDMA_CH1_TRG */ -#define LL_SPI_GRP1_GPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH2_TRG */ -#define LL_SPI_GRP1_GPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is GPDMA_CH3_TRG */ -#define LL_SPI_GRP1_GPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI4_TRG */ -#define LL_SPI_GRP1_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI9_TRG */ -#define LL_SPI_GRP1_EXTI9_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define LL_SPI_GRP1_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM2_CH1_TRG */ -#define LL_SPI_GRP1_LPTIM2_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ -#define LL_SPI_GRP1_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ -#define LL_SPI_GRP1_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ -#define LL_SPI_GRP1_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ -#define LL_SPI_GRP1_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP1 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) - -#if defined(LL_SPI_TRIG_GRP2) -/*!< HW Trigger signal is LPDMA_CH0_TRG */ -#define LL_SPI_GRP2_LPDMA_CH0_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x00000000U)) -/*!< HW Trigger signal is LPDMA_CH1_TRG */ -#define LL_SPI_GRP2_LPDMA_CH1_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x1U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH2_TRG */ -#define LL_SPI_GRP2_LPDMA_CH2_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x2U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPDMA_CH3_TRG */ -#define LL_SPI_GRP2_LPDMA_CH3_TCF_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x3U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI4_TRG */ -#define LL_SPI_GRP2_EXTI4_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x4U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is EXTI8_TRG */ -#define LL_SPI_GRP2_EXTI8_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x5U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM1_CH1_TRG */ -#define LL_SPI_GRP2_LPTIM1_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x6U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is LPTIM3_CH1_TRG */ -#define LL_SPI_GRP2_LPTIM3_CH1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x7U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP1_TRG */ -#define LL_SPI_GRP2_COMP1_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x8U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is COMP2_TRG */ -#define LL_SPI_GRP2_COMP2_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0x9U << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_ALRA_TRG */ -#define LL_SPI_GRP2_RTC_ALRA_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xAU << SPI_AUTOCR_TRIGSEL_Pos)) -/*!< HW Trigger signal is RTC_WUT_TRG */ -#define LL_SPI_GRP2_RTC_WUT_TRG (uint32_t)(LL_SPI_TRIG_GRP2 | (0xBU << SPI_AUTOCR_TRIGSEL_Pos)) -#endif /* LL_SPI_TRIG_GRP2 */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity - * @brief SPI Autonomous Trigger Polarity - * @{ - */ -#define LL_SPI_TRIG_POLARITY_RISING 0x00000000U /*!< SPI triggered on rising edge */ -#define LL_SPI_TRIG_POLARITY_FALLING SPI_AUTOCR_TRIGPOL /*!< SPI triggered on falling edge */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros - * @{ - */ - -/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in SPI register - * @param __INSTANCE__ SPI Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in SPI register - * @param __INSTANCE__ SPI Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable SPI peripheral - * @rmtoll CR1 SPE LL_SPI_Enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Disable SPI peripheral - * @note When disabling the SPI, follow the procedure described in the Reference Manual. - * @rmtoll CR1 SPE LL_SPI_Disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Check if SPI peripheral is enabled - * @rmtoll CR1 SPE LL_SPI_IsEnabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); -} - -/** - * @brief Swap the MOSI and MISO pin - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG2 IOSWP LL_SPI_EnableIOSwap - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIOSwap(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); -} - -/** - * @brief Restore default function for MOSI and MISO pin - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG2 IOSWP LL_SPI_DisableIOSwap - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIOSwap(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CFG2, SPI_CFG2_IOSWP); -} - -/** - * @brief Check if MOSI and MISO pin are swapped - * @rmtoll CFG2 IOSWP LL_SPI_IsEnabledIOSwap - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOSwap(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CFG2, SPI_CFG2_IOSWP) == (SPI_CFG2_IOSWP)) ? 1UL : 0UL); -} - -/** - * @brief Enable GPIO control - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG2 AFCNTR LL_SPI_EnableGPIOControl - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableGPIOControl(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); -} - -/** - * @brief Disable GPIO control - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG2 AFCNTR LL_SPI_DisableGPIOControl - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableGPIOControl(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR); -} - -/** - * @brief Check if GPIO control is active - * @rmtoll CFG2 AFCNTR LL_SPI_IsEnabledGPIOControl - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledGPIOControl(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CFG2, SPI_CFG2_AFCNTR) == (SPI_CFG2_AFCNTR)) ? 1UL : 0UL); -} - -/** - * @brief Set SPI Mode to Master or Slave - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG2 MASTER LL_SPI_SetMode - * @param SPIx SPI Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_SPI_MODE_MASTER - * @arg @ref LL_SPI_MODE_SLAVE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_MASTER, Mode); -} - -/** - * @brief Get SPI Mode (Master or Slave) - * @rmtoll CFG2 MASTER LL_SPI_GetMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_MODE_MASTER - * @arg @ref LL_SPI_MODE_SLAVE - */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MASTER)); -} - -/** - * @brief Configure the Idleness applied by master between active edge of SS and first send data - * @rmtoll CFG2 MSSI LL_SPI_SetMasterSSIdleness - * @param SPIx SPI Instance - * @param MasterSSIdleness This parameter can be one of the following values: - * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetMasterSSIdleness(SPI_TypeDef *SPIx, uint32_t MasterSSIdleness) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_MSSI, MasterSSIdleness); -} - -/** - * @brief Get the configured Idleness applied by master - * @rmtoll CFG2 MSSI LL_SPI_GetMasterSSIdleness - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_SS_IDLENESS_00CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_01CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_02CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_03CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_04CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_05CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_06CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_07CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_08CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_09CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_10CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_11CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_12CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_13CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_14CYCLE - * @arg @ref LL_SPI_SS_IDLENESS_15CYCLE - */ -__STATIC_INLINE uint32_t LL_SPI_GetMasterSSIdleness(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MSSI)); -} - -/** - * @brief Configure the idleness applied by master between data frame - * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness - * @param SPIx SPI Instance - * @param MasterInterDataIdleness This parameter can be one of the following values: - * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetInterDataIdleness(SPI_TypeDef *SPIx, uint32_t MasterInterDataIdleness) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_MIDI, MasterInterDataIdleness); -} - -/** - * @brief Get the configured inter data idleness - * @rmtoll CFG2 MIDI LL_SPI_SetInterDataIdleness - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_ID_IDLENESS_00CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_01CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_02CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_03CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_04CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_05CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_06CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_07CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_08CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_09CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_10CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_11CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_12CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_13CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_14CYCLE - * @arg @ref LL_SPI_ID_IDLENESS_15CYCLE - */ -__STATIC_INLINE uint32_t LL_SPI_GetInterDataIdleness(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_MIDI)); -} - -/** - * @brief Set transfer size - * @note Count is the number of frame to be transferred - * @rmtoll CR2 TSIZE LL_SPI_SetTransferSize - * @param SPIx SPI Instance - * @param Count 0..0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferSize(SPI_TypeDef *SPIx, uint32_t Count) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_TSIZE, Count); -} - -/** - * @brief Get transfer size - * @note Count is the number of frame to be transferred - * @rmtoll CR2 TSIZE LL_SPI_GetTransferSize - * @param SPIx SPI Instance - * @retval 0..0xFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferSize(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_TSIZE)); -} - -/** - * @brief Lock the AF configuration of associated IOs - * @note Once this bit is set, the AF configuration remains locked until a hardware reset occurs. - * the reset of the IOLock bit is done by hardware. for that, LL_SPI_DisableIOLock can not exist. - * @rmtoll CR1 IOLOCK LL_SPI_EnableIOLock - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIOLock(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_IOLOCK); -} - -/** - * @brief Check if the AF configuration is locked. - * @rmtoll CR1 IOLOCK LL_SPI_IsEnabledIOLock - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIOLock(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_IOLOCK) == (SPI_CR1_IOLOCK)) ? 1UL : 0UL); -} - -/** - * @brief Set Tx CRC Initialization Pattern - * @rmtoll CR1 TCRCINI LL_SPI_SetTxCRCInitPattern - * @param SPIx SPI Instance - * @param TXCRCInitAll This parameter can be one of the following values: - * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN - * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t TXCRCInitAll) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_TCRCINI, TXCRCInitAll); -} - -/** - * @brief Get Tx CRC Initialization Pattern - * @rmtoll CR1 TCRCINI LL_SPI_GetTxCRCInitPattern - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_TXCRCINIT_ALL_ZERO_PATTERN - * @arg @ref LL_SPI_TXCRCINIT_ALL_ONES_PATTERN - */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRCInitPattern(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_TCRCINI)); -} - -/** - * @brief Set Rx CRC Initialization Pattern - * @rmtoll CR1 RCRCINI LL_SPI_SetRxCRCInitPattern - * @param SPIx SPI Instance - * @param RXCRCInitAll This parameter can be one of the following values: - * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN - * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetRxCRCInitPattern(SPI_TypeDef *SPIx, uint32_t RXCRCInitAll) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_RCRCINI, RXCRCInitAll); -} - -/** - * @brief Get Rx CRC Initialization Pattern - * @rmtoll CR1 RCRCINI LL_SPI_GetRxCRCInitPattern - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_RXCRCINIT_ALL_ZERO_PATTERN - * @arg @ref LL_SPI_RXCRCINIT_ALL_ONES_PATTERN - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRCInitPattern(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RCRCINI)); -} - -/** - * @brief Set internal SS input level ignoring what comes from PIN. - * @note This configuration has effect only with config LL_SPI_NSS_SOFT - * @rmtoll CR1 SSI LL_SPI_SetInternalSSLevel - * @param SPIx SPI Instance - * @param SSLevel This parameter can be one of the following values: - * @arg @ref LL_SPI_SS_LEVEL_HIGH - * @arg @ref LL_SPI_SS_LEVEL_LOW - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetInternalSSLevel(SPI_TypeDef *SPIx, uint32_t SSLevel) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_SSI, SSLevel); -} - -/** - * @brief Get internal SS input level - * @rmtoll CR1 SSI LL_SPI_GetInternalSSLevel - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_SS_LEVEL_HIGH - * @arg @ref LL_SPI_SS_LEVEL_LOW - */ -__STATIC_INLINE uint32_t LL_SPI_GetInternalSSLevel(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_SSI)); -} - -/** - * @brief Enable CRC computation on 33/17 bits - * @rmtoll CR1 CRC33_17 LL_SPI_EnableFullSizeCRC - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableFullSizeCRC(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_CRC33_17); -} - -/** - * @brief Disable CRC computation on 33/17 bits - * @rmtoll CR1 CRC33_17 LL_SPI_DisableFullSizeCRC - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableFullSizeCRC(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR1, SPI_CR1_CRC33_17); -} - -/** - * @brief Check if Enable CRC computation on 33/17 bits is enabled - * @rmtoll CR1 CRC33_17 LL_SPI_IsEnabledFullSizeCRC - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledFullSizeCRC(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_CRC33_17) == (SPI_CR1_CRC33_17)) ? 1UL : 0UL); -} - -/** - * @brief Suspend an ongoing transfer for Master configuration - * @rmtoll CR1 CSUSP LL_SPI_SuspendMasterTransfer - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_SuspendMasterTransfer(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_CSUSP); -} - -/** - * @brief Start effective transfer on wire for Master configuration - * @rmtoll CR1 CSTART LL_SPI_StartMasterTransfer - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_StartMasterTransfer(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_CSTART); -} - -/** - * @brief Check if there is an unfinished master transfer - * @rmtoll CR1 CSTART LL_SPI_IsActiveMasterTransfer - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveMasterTransfer(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_CSTART) == (SPI_CR1_CSTART)) ? 1UL : 0UL); -} - -/** - * @brief Enable Master Rx auto suspend in case of overrun - * @rmtoll CR1 MASRX LL_SPI_EnableMasterRxAutoSuspend - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableMasterRxAutoSuspend(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_MASRX); -} - -/** - * @brief Disable Master Rx auto suspend in case of overrun - * @rmtoll CR1 MASRX LL_SPI_DisableMasterRxAutoSuspend - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableMasterRxAutoSuspend(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR1, SPI_CR1_MASRX); -} - -/** - * @brief Check if Master Rx auto suspend is activated - * @rmtoll CR1 MASRX LL_SPI_IsEnabledMasterRxAutoSuspend - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledMasterRxAutoSuspend(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_MASRX) == (SPI_CR1_MASRX)) ? 1UL : 0UL); -} - -/** - * @brief Set Underrun behavior - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG1 UDRCFG LL_SPI_SetUDRConfiguration - * @param SPIx SPI Instance - * @param UDRConfig This parameter can be one of the following values: - * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN - * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetUDRConfiguration(SPI_TypeDef *SPIx, uint32_t UDRConfig) -{ - MODIFY_REG(SPIx->CFG1, SPI_CFG1_UDRCFG, UDRConfig); -} - -/** - * @brief Get Underrun behavior - * @rmtoll CFG1 UDRCFG LL_SPI_GetUDRConfiguration - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_UDR_CONFIG_REGISTER_PATTERN - * @arg @ref LL_SPI_UDR_CONFIG_LAST_RECEIVED - */ -__STATIC_INLINE uint32_t LL_SPI_GetUDRConfiguration(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_UDRCFG)); -} - - -/** - * @brief Set Serial protocol used - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG2 SP LL_SPI_SetStandard - * @param SPIx SPI Instance - * @param Standard This parameter can be one of the following values: - * @arg @ref LL_SPI_PROTOCOL_MOTOROLA - * @arg @ref LL_SPI_PROTOCOL_TI - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_SP, Standard); -} - -/** - * @brief Get Serial protocol used - * @rmtoll CFG2 SP LL_SPI_GetStandard - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_PROTOCOL_MOTOROLA - * @arg @ref LL_SPI_PROTOCOL_TI - */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SP)); -} - -/** - * @brief Set Clock phase - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 CPHA LL_SPI_SetClockPhase - * @param SPIx SPI Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_SPI_PHASE_1EDGE - * @arg @ref LL_SPI_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPHA, ClockPhase); -} - -/** - * @brief Get Clock phase - * @rmtoll CFG2 CPHA LL_SPI_GetClockPhase - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_PHASE_1EDGE - * @arg @ref LL_SPI_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPHA)); -} - -/** - * @brief Set Clock polarity - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 CPOL LL_SPI_SetClockPolarity - * @param SPIx SPI Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_SPI_POLARITY_LOW - * @arg @ref LL_SPI_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_CPOL, ClockPolarity); -} - -/** - * @brief Get Clock polarity - * @rmtoll CFG2 CPOL LL_SPI_GetClockPolarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_POLARITY_LOW - * @arg @ref LL_SPI_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_CPOL)); -} - -/** - * @brief Set NSS polarity - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 SSIOP LL_SPI_SetNSSPolarity - * @param SPIx SPI Instance - * @param NSSPolarity This parameter can be one of the following values: - * @arg @ref LL_SPI_NSS_POLARITY_LOW - * @arg @ref LL_SPI_NSS_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetNSSPolarity(SPI_TypeDef *SPIx, uint32_t NSSPolarity) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSIOP, NSSPolarity); -} - -/** - * @brief Get NSS polarity - * @rmtoll CFG2 SSIOP LL_SPI_GetNSSPolarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_NSS_POLARITY_LOW - * @arg @ref LL_SPI_NSS_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSPolarity(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSIOP)); -} - -/** - * @brief Set Baudrate Prescaler - * @note This configuration can not be changed when SPI is enabled. - * SPI BaudRate = fPCLK/Pescaler. - * @rmtoll CFG1 MBR LL_SPI_SetBaudRatePrescaler\n - * CFG1 BPASS LL_SPI_SetBaudRatePrescaler - * @param SPIx SPI Instance - * @param Baudrate This parameter can be one of the following values: - * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Baudrate) -{ - MODIFY_REG(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS), Baudrate); -} - -/** - * @brief Get Baudrate Prescaler - * @rmtoll CFG1 MBR LL_SPI_GetBaudRatePrescaler\n - * CFG1 BPASS LL_SPI_GetBaudRatePrescaler - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_BAUDRATEPRESCALER_BYPASS - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 - */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG1, (SPI_CFG1_MBR | SPI_CFG1_BPASS))); -} - -/** - * @brief Set Transfer Bit Order - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 LSBFRST LL_SPI_SetTransferBitOrder - * @param SPIx SPI Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_SPI_LSB_FIRST - * @arg @ref LL_SPI_MSB_FIRST - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_LSBFRST, BitOrder); -} - -/** - * @brief Get Transfer Bit Order - * @rmtoll CFG2 LSBFRST LL_SPI_GetTransferBitOrder - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_LSB_FIRST - * @arg @ref LL_SPI_MSB_FIRST - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_LSBFRST)); -} - -/** - * @brief Set Transfer Mode - * @note This configuration can not be changed when SPI is enabled except for half duplex direction - * using LL_SPI_SetHalfDuplexDirection. - * @rmtoll CR1 HDDIR LL_SPI_SetTransferDirection\n - * CFG2 COMM LL_SPI_SetTransferDirection - * @param SPIx SPI Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_SPI_FULL_DUPLEX - * @arg @ref LL_SPI_SIMPLEX_TX - * @arg @ref LL_SPI_SIMPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, TransferDirection & SPI_CR1_HDDIR); - MODIFY_REG(SPIx->CFG2, SPI_CFG2_COMM, TransferDirection & SPI_CFG2_COMM); -} - -/** - * @brief Get Transfer Mode - * @rmtoll CR1 HDDIR LL_SPI_GetTransferDirection\n - * CFG2 COMM LL_SPI_GetTransferDirection - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_FULL_DUPLEX - * @arg @ref LL_SPI_SIMPLEX_TX - * @arg @ref LL_SPI_SIMPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) -{ - uint32_t Hddir = READ_BIT(SPIx->CR1, SPI_CR1_HDDIR); - uint32_t Comm = READ_BIT(SPIx->CFG2, SPI_CFG2_COMM); - return (Hddir | Comm); -} - -/** - * @brief Set direction for Half-Duplex Mode - * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. - * @rmtoll CR1 HDDIR LL_SPI_SetHalfDuplexDirection - * @param SPIx SPI Instance - * @param HalfDuplexDirection This parameter can be one of the following values: - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetHalfDuplexDirection(SPI_TypeDef *SPIx, uint32_t HalfDuplexDirection) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_HDDIR, HalfDuplexDirection & SPI_CR1_HDDIR); -} - -/** - * @brief Get direction for Half-Duplex Mode - * @note In master mode the MOSI pin is used and in slave mode the MISO pin is used for Half-Duplex. - * @rmtoll CR1 HDDIR LL_SPI_GetHalfDuplexDirection - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - */ -__STATIC_INLINE uint32_t LL_SPI_GetHalfDuplexDirection(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_HDDIR) | SPI_CFG2_COMM); -} - -/** - * @brief Set Frame Data Size - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG1 DSIZE LL_SPI_SetDataWidth - * @param SPIx SPI Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_SPI_DATAWIDTH_4BIT - * @arg @ref LL_SPI_DATAWIDTH_5BIT - * @arg @ref LL_SPI_DATAWIDTH_6BIT - * @arg @ref LL_SPI_DATAWIDTH_7BIT - * @arg @ref LL_SPI_DATAWIDTH_8BIT - * @arg @ref LL_SPI_DATAWIDTH_9BIT - * @arg @ref LL_SPI_DATAWIDTH_10BIT - * @arg @ref LL_SPI_DATAWIDTH_11BIT - * @arg @ref LL_SPI_DATAWIDTH_12BIT - * @arg @ref LL_SPI_DATAWIDTH_13BIT - * @arg @ref LL_SPI_DATAWIDTH_14BIT - * @arg @ref LL_SPI_DATAWIDTH_15BIT - * @arg @ref LL_SPI_DATAWIDTH_16BIT - * @arg @ref LL_SPI_DATAWIDTH_17BIT - * @arg @ref LL_SPI_DATAWIDTH_18BIT - * @arg @ref LL_SPI_DATAWIDTH_19BIT - * @arg @ref LL_SPI_DATAWIDTH_20BIT - * @arg @ref LL_SPI_DATAWIDTH_21BIT - * @arg @ref LL_SPI_DATAWIDTH_22BIT - * @arg @ref LL_SPI_DATAWIDTH_23BIT - * @arg @ref LL_SPI_DATAWIDTH_24BIT - * @arg @ref LL_SPI_DATAWIDTH_25BIT - * @arg @ref LL_SPI_DATAWIDTH_26BIT - * @arg @ref LL_SPI_DATAWIDTH_27BIT - * @arg @ref LL_SPI_DATAWIDTH_28BIT - * @arg @ref LL_SPI_DATAWIDTH_29BIT - * @arg @ref LL_SPI_DATAWIDTH_30BIT - * @arg @ref LL_SPI_DATAWIDTH_31BIT - * @arg @ref LL_SPI_DATAWIDTH_32BIT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) -{ - MODIFY_REG(SPIx->CFG1, SPI_CFG1_DSIZE, DataWidth); -} - -/** - * @brief Get Frame Data Size - * @rmtoll CFG1 DSIZE LL_SPI_GetDataWidth - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DATAWIDTH_4BIT - * @arg @ref LL_SPI_DATAWIDTH_5BIT - * @arg @ref LL_SPI_DATAWIDTH_6BIT - * @arg @ref LL_SPI_DATAWIDTH_7BIT - * @arg @ref LL_SPI_DATAWIDTH_8BIT - * @arg @ref LL_SPI_DATAWIDTH_9BIT - * @arg @ref LL_SPI_DATAWIDTH_10BIT - * @arg @ref LL_SPI_DATAWIDTH_11BIT - * @arg @ref LL_SPI_DATAWIDTH_12BIT - * @arg @ref LL_SPI_DATAWIDTH_13BIT - * @arg @ref LL_SPI_DATAWIDTH_14BIT - * @arg @ref LL_SPI_DATAWIDTH_15BIT - * @arg @ref LL_SPI_DATAWIDTH_16BIT - * @arg @ref LL_SPI_DATAWIDTH_17BIT - * @arg @ref LL_SPI_DATAWIDTH_18BIT - * @arg @ref LL_SPI_DATAWIDTH_19BIT - * @arg @ref LL_SPI_DATAWIDTH_20BIT - * @arg @ref LL_SPI_DATAWIDTH_21BIT - * @arg @ref LL_SPI_DATAWIDTH_22BIT - * @arg @ref LL_SPI_DATAWIDTH_23BIT - * @arg @ref LL_SPI_DATAWIDTH_24BIT - * @arg @ref LL_SPI_DATAWIDTH_25BIT - * @arg @ref LL_SPI_DATAWIDTH_26BIT - * @arg @ref LL_SPI_DATAWIDTH_27BIT - * @arg @ref LL_SPI_DATAWIDTH_28BIT - * @arg @ref LL_SPI_DATAWIDTH_29BIT - * @arg @ref LL_SPI_DATAWIDTH_30BIT - * @arg @ref LL_SPI_DATAWIDTH_31BIT - * @arg @ref LL_SPI_DATAWIDTH_32BIT - */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_DSIZE)); -} - -/** - * @brief Set threshold of FIFO that triggers a transfer event - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG1 FTHLV LL_SPI_SetFIFOThreshold - * @param SPIx SPI Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_SPI_FIFO_TH_01DATA - * @arg @ref LL_SPI_FIFO_TH_02DATA - * @arg @ref LL_SPI_FIFO_TH_03DATA - * @arg @ref LL_SPI_FIFO_TH_04DATA - * @arg @ref LL_SPI_FIFO_TH_05DATA - * @arg @ref LL_SPI_FIFO_TH_06DATA - * @arg @ref LL_SPI_FIFO_TH_07DATA - * @arg @ref LL_SPI_FIFO_TH_08DATA - * @arg @ref LL_SPI_FIFO_TH_09DATA - * @arg @ref LL_SPI_FIFO_TH_10DATA - * @arg @ref LL_SPI_FIFO_TH_11DATA - * @arg @ref LL_SPI_FIFO_TH_12DATA - * @arg @ref LL_SPI_FIFO_TH_13DATA - * @arg @ref LL_SPI_FIFO_TH_14DATA - * @arg @ref LL_SPI_FIFO_TH_15DATA - * @arg @ref LL_SPI_FIFO_TH_16DATA - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) -{ - MODIFY_REG(SPIx->CFG1, SPI_CFG1_FTHLV, Threshold); -} - -/** - * @brief Get threshold of FIFO that triggers a transfer event - * @rmtoll CFG1 FTHLV LL_SPI_GetFIFOThreshold - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_FIFO_TH_01DATA - * @arg @ref LL_SPI_FIFO_TH_02DATA - * @arg @ref LL_SPI_FIFO_TH_03DATA - * @arg @ref LL_SPI_FIFO_TH_04DATA - * @arg @ref LL_SPI_FIFO_TH_05DATA - * @arg @ref LL_SPI_FIFO_TH_06DATA - * @arg @ref LL_SPI_FIFO_TH_07DATA - * @arg @ref LL_SPI_FIFO_TH_08DATA - * @arg @ref LL_SPI_FIFO_TH_09DATA - * @arg @ref LL_SPI_FIFO_TH_10DATA - * @arg @ref LL_SPI_FIFO_TH_11DATA - * @arg @ref LL_SPI_FIFO_TH_12DATA - * @arg @ref LL_SPI_FIFO_TH_13DATA - * @arg @ref LL_SPI_FIFO_TH_14DATA - * @arg @ref LL_SPI_FIFO_TH_15DATA - * @arg @ref LL_SPI_FIFO_TH_16DATA - */ -__STATIC_INLINE uint32_t LL_SPI_GetFIFOThreshold(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_FTHLV)); -} - -/** - * @brief Enable CRC - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG1 CRCEN LL_SPI_EnableCRC - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); -} - -/** - * @brief Disable CRC - * @rmtoll CFG1 CRCEN LL_SPI_DisableCRC - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CFG1, SPI_CFG1_CRCEN); -} - -/** - * @brief Check if CRC is enabled - * @rmtoll CFG1 CRCEN LL_SPI_IsEnabledCRC - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CFG1, SPI_CFG1_CRCEN) == SPI_CFG1_CRCEN) ? 1UL : 0UL); -} - -/** - * @brief Set CRC Length - * @note This configuration can not be changed when SPI is enabled. - * @rmtoll CFG1 CRCSIZE LL_SPI_SetCRCWidth - * @param SPIx SPI Instance - * @param CRCLength This parameter can be one of the following values: - * @arg @ref LL_SPI_CRC_4BIT - * @arg @ref LL_SPI_CRC_5BIT - * @arg @ref LL_SPI_CRC_6BIT - * @arg @ref LL_SPI_CRC_7BIT - * @arg @ref LL_SPI_CRC_8BIT - * @arg @ref LL_SPI_CRC_9BIT - * @arg @ref LL_SPI_CRC_10BIT - * @arg @ref LL_SPI_CRC_11BIT - * @arg @ref LL_SPI_CRC_12BIT - * @arg @ref LL_SPI_CRC_13BIT - * @arg @ref LL_SPI_CRC_14BIT - * @arg @ref LL_SPI_CRC_15BIT - * @arg @ref LL_SPI_CRC_16BIT - * @arg @ref LL_SPI_CRC_17BIT - * @arg @ref LL_SPI_CRC_18BIT - * @arg @ref LL_SPI_CRC_19BIT - * @arg @ref LL_SPI_CRC_20BIT - * @arg @ref LL_SPI_CRC_21BIT - * @arg @ref LL_SPI_CRC_22BIT - * @arg @ref LL_SPI_CRC_23BIT - * @arg @ref LL_SPI_CRC_24BIT - * @arg @ref LL_SPI_CRC_25BIT - * @arg @ref LL_SPI_CRC_26BIT - * @arg @ref LL_SPI_CRC_27BIT - * @arg @ref LL_SPI_CRC_28BIT - * @arg @ref LL_SPI_CRC_29BIT - * @arg @ref LL_SPI_CRC_30BIT - * @arg @ref LL_SPI_CRC_31BIT - * @arg @ref LL_SPI_CRC_32BIT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) -{ - MODIFY_REG(SPIx->CFG1, SPI_CFG1_CRCSIZE, CRCLength); -} - -/** - * @brief Get CRC Length - * @rmtoll CFG1 CRCSIZE LL_SPI_GetCRCWidth - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_CRC_4BIT - * @arg @ref LL_SPI_CRC_5BIT - * @arg @ref LL_SPI_CRC_6BIT - * @arg @ref LL_SPI_CRC_7BIT - * @arg @ref LL_SPI_CRC_8BIT - * @arg @ref LL_SPI_CRC_9BIT - * @arg @ref LL_SPI_CRC_10BIT - * @arg @ref LL_SPI_CRC_11BIT - * @arg @ref LL_SPI_CRC_12BIT - * @arg @ref LL_SPI_CRC_13BIT - * @arg @ref LL_SPI_CRC_14BIT - * @arg @ref LL_SPI_CRC_15BIT - * @arg @ref LL_SPI_CRC_16BIT - * @arg @ref LL_SPI_CRC_17BIT - * @arg @ref LL_SPI_CRC_18BIT - * @arg @ref LL_SPI_CRC_19BIT - * @arg @ref LL_SPI_CRC_20BIT - * @arg @ref LL_SPI_CRC_21BIT - * @arg @ref LL_SPI_CRC_22BIT - * @arg @ref LL_SPI_CRC_23BIT - * @arg @ref LL_SPI_CRC_24BIT - * @arg @ref LL_SPI_CRC_25BIT - * @arg @ref LL_SPI_CRC_26BIT - * @arg @ref LL_SPI_CRC_27BIT - * @arg @ref LL_SPI_CRC_28BIT - * @arg @ref LL_SPI_CRC_29BIT - * @arg @ref LL_SPI_CRC_30BIT - * @arg @ref LL_SPI_CRC_31BIT - * @arg @ref LL_SPI_CRC_32BIT - */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG1, SPI_CFG1_CRCSIZE)); -} - -/** - * @brief Set NSS Mode - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 SSM LL_SPI_SetNSSMode\n - * CFG2 SSOE LL_SPI_SetNSSMode - * @param SPIx SPI Instance - * @param NSS This parameter can be one of the following values: - * @arg @ref LL_SPI_NSS_SOFT - * @arg @ref LL_SPI_NSS_HARD_INPUT - * @arg @ref LL_SPI_NSS_HARD_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) -{ - MODIFY_REG(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE, NSS); -} - -/** - * @brief Set NSS Mode - * @rmtoll CFG2 SSM LL_SPI_GetNSSMode\n - * CFG2 SSOE LL_SPI_GetNSSMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_NSS_SOFT - * @arg @ref LL_SPI_NSS_HARD_INPUT - * @arg @ref LL_SPI_NSS_HARD_OUTPUT - */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CFG2, SPI_CFG2_SSM | SPI_CFG2_SSOE)); -} - -/** - * @brief Enable NSS pulse mgt - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 SSOM LL_SPI_EnableNSSPulseMgt - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CFG2, SPI_CFG2_SSOM); -} - -/** - * @brief Disable NSS pulse mgt - * @note This configuration can not be changed when SPI is enabled. - * This bit is not used in SPI TI mode. - * @rmtoll CFG2 SSOM LL_SPI_DisableNSSPulseMgt - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CFG2, SPI_CFG2_SSOM); -} - -/** - * @brief Check if NSS pulse is enabled - * @rmtoll CFG2 SSOM LL_SPI_IsEnabledNSSPulse - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CFG2, SPI_CFG2_SSOM) == SPI_CFG2_SSOM) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if there is enough data in FIFO to read a full packet - * @rmtoll SR RXP LL_SPI_IsActiveFlag_RXP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_RXP) == (SPI_SR_RXP)) ? 1UL : 0UL); -} - -/** - * @brief Check if there is enough space in FIFO to hold a full packet - * @rmtoll SR TXP LL_SPI_IsActiveFlag_TXP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_TXP) == (SPI_SR_TXP)) ? 1UL : 0UL); -} - -/** - * @brief Check if there enough space in FIFO to hold a full packet, AND enough data to read a full packet - * @rmtoll SR DXP LL_SPI_IsActiveFlag_DXP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_DXP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_DXP) == (SPI_SR_DXP)) ? 1UL : 0UL); -} - -/** - * @brief Check that end of transfer event occurred - * @rmtoll SR EOT LL_SPI_IsActiveFlag_EOT - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_EOT(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_EOT) == (SPI_SR_EOT)) ? 1UL : 0UL); -} - -/** - * @brief Check that all required data has been filled in the fifo according to transfer size - * @rmtoll SR TXTF LL_SPI_IsActiveFlag_TXTF - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXTF(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_TXTF) == (SPI_SR_TXTF)) ? 1UL : 0UL); -} - -/** - * @brief Get Underrun error flag - * @rmtoll SR UDR LL_SPI_IsActiveFlag_UDR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); -} - -/** - * @brief Get CRC error flag - * @rmtoll SR CRCE LL_SPI_IsActiveFlag_CRCERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_CRCE) == (SPI_SR_CRCE)) ? 1UL : 0UL); -} - -/** - * @brief Get Mode fault error flag - * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); -} - -/** - * @brief Get Overrun error flag - * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get TI Frame format error flag - * @rmtoll SR TIFRE LL_SPI_IsActiveFlag_FRE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_TIFRE) == (SPI_SR_TIFRE)) ? 1UL : 0UL); -} - -/** - * @brief Check if a suspend operation is done - * @rmtoll SR SUSP LL_SPI_IsActiveFlag_SUSP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_SUSP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_SUSP) == (SPI_SR_SUSP)) ? 1UL : 0UL); -} - -/** - * @brief Check if last TxFIFO or CRC frame transmission is completed - * @rmtoll SR TXC LL_SPI_IsActiveFlag_TXC - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXC(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_TXC) == (SPI_SR_TXC)) ? 1UL : 0UL); -} - -/** - * @brief Check if at least one 32-bit data is available in RxFIFO - * @rmtoll SR RXWNE LL_SPI_IsActiveFlag_RXWNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXWNE(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_RXWNE) == (SPI_SR_RXWNE)) ? 1UL : 0UL); -} - -/** - * @brief Get number of data framed remaining in current TSIZE - * @rmtoll SR CTSIZE LL_SPI_GetRemainingDataFrames - * @param SPIx SPI Instance - * @retval 0..0xFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetRemainingDataFrames(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_CTSIZE) >> SPI_SR_CTSIZE_Pos); -} - -/** - * @brief Get RxFIFO packing Level - * @rmtoll SR RXPLVL LL_SPI_GetRxFIFOPackingLevel - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_0PACKET - * @arg @ref LL_SPI_RX_FIFO_1PACKET - * @arg @ref LL_SPI_RX_FIFO_2PACKET - * @arg @ref LL_SPI_RX_FIFO_3PACKET - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOPackingLevel(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_RXPLVL)); -} - -/** - * @brief Clear End Of Transfer flag - * @rmtoll IFCR EOTC LL_SPI_ClearFlag_EOT - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_EOT(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_EOTC); -} - -/** - * @brief Clear TXTF flag - * @rmtoll IFCR TXTFC LL_SPI_ClearFlag_TXTF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_TXTF(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_TXTFC); -} - -/** - * @brief Clear Underrun error flag - * @rmtoll IFCR UDRC LL_SPI_ClearFlag_UDR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_UDR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_UDRC); -} - -/** - * @brief Clear Overrun error flag - * @rmtoll IFCR OVRC LL_SPI_ClearFlag_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_OVRC); -} - -/** - * @brief Clear CRC error flag - * @rmtoll IFCR CRCEC LL_SPI_ClearFlag_CRCERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_CRCEC); -} - -/** - * @brief Clear Mode fault error flag - * @rmtoll IFCR MODFC LL_SPI_ClearFlag_MODF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_MODFC); -} - -/** - * @brief Clear Frame format error flag - * @rmtoll IFCR TIFREC LL_SPI_ClearFlag_FRE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_TIFREC); -} - -/** - * @brief Clear SUSP flag - * @rmtoll IFCR SUSPC LL_SPI_ClearFlag_SUSP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_SUSP(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IFCR, SPI_IFCR_SUSPC); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Rx Packet available IT - * @rmtoll IER RXPIE LL_SPI_EnableIT_RXP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_RXP(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_RXPIE); -} - -/** - * @brief Enable Tx Packet space available IT - * @rmtoll IER TXPIE LL_SPI_EnableIT_TXP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_TXP(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TXPIE); -} - -/** - * @brief Enable Duplex Packet available IT - * @rmtoll IER DXPIE LL_SPI_EnableIT_DXP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_DXP(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_DXPIE); -} - -/** - * @brief Enable End Of Transfer IT - * @rmtoll IER EOTIE LL_SPI_EnableIT_EOT - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_EOT(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_EOTIE); -} - -/** - * @brief Enable TXTF IT - * @rmtoll IER TXTFIE LL_SPI_EnableIT_TXTF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_TXTF(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TXTFIE); -} - -/** - * @brief Enable Underrun IT - * @rmtoll IER UDRIE LL_SPI_EnableIT_UDR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_UDR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_UDRIE); -} - -/** - * @brief Enable Overrun IT - * @rmtoll IER OVRIE LL_SPI_EnableIT_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_OVR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_OVRIE); -} - -/** - * @brief Enable CRC Error IT - * @rmtoll IER CRCEIE LL_SPI_EnableIT_CRCERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_CRCERR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_CRCEIE); -} - -/** - * @brief Enable TI Frame Format Error IT - * @rmtoll IER TIFREIE LL_SPI_EnableIT_FRE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_FRE(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_TIFREIE); -} - -/** - * @brief Enable MODF IT - * @rmtoll IER MODFIE LL_SPI_EnableIT_MODF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_MODF(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->IER, SPI_IER_MODFIE); -} - -/** - * @brief Disable Rx Packet available IT - * @rmtoll IER RXPIE LL_SPI_DisableIT_RXP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_RXP(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_RXPIE); -} - -/** - * @brief Disable Tx Packet space available IT - * @rmtoll IER TXPIE LL_SPI_DisableIT_TXP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_TXP(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_TXPIE); -} - -/** - * @brief Disable Duplex Packet available IT - * @rmtoll IER DXPIE LL_SPI_DisableIT_DXP - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_DXP(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_DXPIE); -} - -/** - * @brief Disable End Of Transfer IT - * @rmtoll IER EOTIE LL_SPI_DisableIT_EOT - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_EOT(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_EOTIE); -} - -/** - * @brief Disable TXTF IT - * @rmtoll IER TXTFIE LL_SPI_DisableIT_TXTF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_TXTF(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_TXTFIE); -} - -/** - * @brief Disable Underrun IT - * @rmtoll IER UDRIE LL_SPI_DisableIT_UDR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_UDR(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_UDRIE); -} - -/** - * @brief Disable Overrun IT - * @rmtoll IER OVRIE LL_SPI_DisableIT_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_OVR(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_OVRIE); -} - -/** - * @brief Disable CRC Error IT - * @rmtoll IER CRCEIE LL_SPI_DisableIT_CRCERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_CRCERR(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_CRCEIE); -} - -/** - * @brief Disable TI Frame Format Error IT - * @rmtoll IER TIFREIE LL_SPI_DisableIT_FRE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_FRE(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_TIFREIE); -} - -/** - * @brief Disable MODF IT - * @rmtoll IER MODFIE LL_SPI_DisableIT_MODF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_MODF(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->IER, SPI_IER_MODFIE); -} - -/** - * @brief Check if Rx Packet available IT is enabled - * @rmtoll IER RXPIE LL_SPI_IsEnabledIT_RXP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_RXPIE) == (SPI_IER_RXPIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx Packet space available IT is enabled - * @rmtoll IER TXPIE LL_SPI_IsEnabledIT_TXP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_TXPIE) == (SPI_IER_TXPIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Duplex Packet available IT is enabled - * @rmtoll IER DXPIE LL_SPI_IsEnabledIT_DXP - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_DXP(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_DXPIE) == (SPI_IER_DXPIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if End Of Transfer IT is enabled - * @rmtoll IER EOTIE LL_SPI_IsEnabledIT_EOT - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_EOT(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_EOTIE) == (SPI_IER_EOTIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if TXTF IT is enabled - * @rmtoll IER TXTFIE LL_SPI_IsEnabledIT_TXTF - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXTF(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_TXTFIE) == (SPI_IER_TXTFIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Underrun IT is enabled - * @rmtoll IER UDRIE LL_SPI_IsEnabledIT_UDR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_UDR(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_UDRIE) == (SPI_IER_UDRIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Overrun IT is enabled - * @rmtoll IER OVRIE LL_SPI_IsEnabledIT_OVR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_OVR(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_OVRIE) == (SPI_IER_OVRIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if CRC Error IT is enabled - * @rmtoll IER CRCEIE LL_SPI_IsEnabledIT_CRCERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_CRCERR(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_CRCEIE) == (SPI_IER_CRCEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if TI Frame Format Error IT is enabled - * @rmtoll IER TIFREIE LL_SPI_IsEnabledIT_FRE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_FRE(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_TIFREIE) == (SPI_IER_TIFREIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if MODF IT is enabled - * @rmtoll IER MODFIE LL_SPI_IsEnabledIT_MODF - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_MODF(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->IER, SPI_IER_MODFIE) == (SPI_IER_MODFIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_DMA_Management DMA Management - * @{ - */ - -/** - * @brief Enable DMA Rx - * @rmtoll CFG1 RXDMAEN LL_SPI_EnableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); -} - -/** - * @brief Disable DMA Rx - * @rmtoll CFG1 RXDMAEN LL_SPI_DisableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN); -} - -/** - * @brief Check if DMA Rx is enabled - * @rmtoll CFG1 RXDMAEN LL_SPI_IsEnabledDMAReq_RX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CFG1, SPI_CFG1_RXDMAEN) == (SPI_CFG1_RXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Tx - * @rmtoll CFG1 TXDMAEN LL_SPI_EnableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); -} - -/** - * @brief Disable DMA Tx - * @rmtoll CFG1 TXDMAEN LL_SPI_DisableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN); -} - -/** - * @brief Check if DMA Tx is enabled - * @rmtoll CFG1 TXDMAEN LL_SPI_IsEnabledDMAReq_TX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0) - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CFG1, SPI_CFG1_TXDMAEN) == (SPI_CFG1_TXDMAEN)) ? 1UL : 0UL); -} -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll TXDR TXDR LL_SPI_DMA_GetTxRegAddr - * @param SPIx SPI Instance - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetTxRegAddr(const SPI_TypeDef *SPIx) -{ - return (uint32_t) &(SPIx->TXDR); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll RXDR RXDR LL_SPI_DMA_GetRxRegAddr - * @param SPIx SPI Instance - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRxRegAddr(const SPI_TypeDef *SPIx) -{ - return (uint32_t) &(SPIx->RXDR); -} -/** - * @} - */ - -/** @defgroup SPI_LL_EF_DATA_Management DATA_Management - * @{ - */ - -/** - * @brief Read Data Register - * @rmtoll RXDR . LL_SPI_ReceiveData8 - * @param SPIx SPI Instance - * @retval 0..0xFF - */ -__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ -{ - return (*((__IO uint8_t *)&SPIx->RXDR)); -} - -/** - * @brief Read Data Register - * @rmtoll RXDR . LL_SPI_ReceiveData16 - * @param SPIx SPI Instance - * @retval 0..0xFFFF - */ -__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ -{ -#if defined (__GNUC__) - __IO uint16_t *spirxdr = (__IO uint16_t *)(&(SPIx->RXDR)); - return (*spirxdr); -#else - return (*((__IO uint16_t *)&SPIx->RXDR)); -#endif /* __GNUC__ */ -} - -/** - * @brief Read Data Register - * @rmtoll RXDR . LL_SPI_ReceiveData32 - * @param SPIx SPI Instance - * @retval 0..0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_ReceiveData32(SPI_TypeDef *SPIx) /* Derogation MISRAC2012-Rule-8.13 */ -{ - return (*((__IO uint32_t *)&SPIx->RXDR)); -} - -/** - * @brief Write Data Register - * @rmtoll TXDR . LL_SPI_TransmitData8 - * @param SPIx SPI Instance - * @param TxData 0..0xFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) -{ - *((__IO uint8_t *)&SPIx->TXDR) = TxData; -} - -/** - * @brief Write Data Register - * @rmtoll TXDR . LL_SPI_TransmitData16 - * @param SPIx SPI Instance - * @param TxData 0..0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ -#if defined (__GNUC__) - __IO uint16_t *spitxdr = ((__IO uint16_t *)&SPIx->TXDR); - *spitxdr = TxData; -#else - *((__IO uint16_t *)&SPIx->TXDR) = TxData; -#endif /* __GNUC__ */ -} - -/** - * @brief Write Data Register - * @rmtoll TXDR . LL_SPI_TransmitData32 - * @param SPIx SPI Instance - * @param TxData 0..0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData32(SPI_TypeDef *SPIx, uint32_t TxData) -{ - *((__IO uint32_t *)&SPIx->TXDR) = TxData; -} - -/** - * @brief Set polynomial for CRC calcul - * @rmtoll CRCPOLY CRCPOLY LL_SPI_SetCRCPolynomial - * @param SPIx SPI Instance - * @param CRCPoly 0..0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) -{ - WRITE_REG(SPIx->CRCPOLY, CRCPoly); -} - -/** - * @brief Get polynomial for CRC calcul - * @rmtoll CRCPOLY CRCPOLY LL_SPI_GetCRCPolynomial - * @param SPIx SPI Instance - * @retval 0..0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->CRCPOLY)); -} - -/** - * @brief Set the underrun pattern - * @rmtoll UDRDR UDRDR LL_SPI_SetUDRPattern - * @param SPIx SPI Instance - * @param Pattern 0..0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetUDRPattern(SPI_TypeDef *SPIx, uint32_t Pattern) -{ - WRITE_REG(SPIx->UDRDR, Pattern); -} - -/** - * @brief Get the underrun pattern - * @rmtoll UDRDR UDRDR LL_SPI_GetUDRPattern - * @param SPIx SPI Instance - * @retval 0..0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetUDRPattern(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->UDRDR)); -} - -/** - * @brief Get Rx CRC - * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC - * @param SPIx SPI Instance - * @retval 0..0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->RXCRC)); -} - -/** - * @brief Get Tx CRC - * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC - * @param SPIx SPI Instance - * @retval 0..0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_REG(SPIx->TXCRC)); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_AutonomousMode Configuration functions related to Autonomous mode feature - * @{ - */ - -/** - * @brief Enable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_SPI_Enable_SelectedTrigger - * @param SPIx SPI Instance. - * @retval None - */ -__STATIC_INLINE void LL_SPI_Enable_SelectedTrigger(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN); -} - -/** - * @brief Disable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_SPI_Disable_SelectedTrigger - * @param SPIx SPI Instance. - * @retval None - */ -__STATIC_INLINE void LL_SPI_Disable_SelectedTrigger(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN); -} - -/** - * @brief Indicate if selected Trigger is disabled or enabled - * @rmtoll AUTOCR TRIGEN LL_SPI_IsEnabled_SelectedTrigger - * @param SPIx SPI Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled_SelectedTrigger(const SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGEN) == (SPI_AUTOCR_TRIGEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_SPI_SetTriggerPolarity - * @param SPIx SPI Instance. - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_SPI_TRIG_POLARITY_RISING - * @arg @ref LL_SPI_TRIG_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTriggerPolarity(SPI_TypeDef *SPIx, uint32_t Polarity) -{ - MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL, Polarity); -} - -/** - * @brief Get the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_SPI_GetTriggerPolarity - * @param SPIx SPI Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_TRIG_POLARITY_RISING - * @arg @ref LL_SPI_TRIG_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_SPI_GetTriggerPolarity(const SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGPOL)); -} - -/** - * @brief Set the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_SPI_SetSelectedTrigger - * @param SPIx SPI Instance. - * @param Trigger This parameter can be one of the following values: - * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG - * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG - * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG - * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG - * @arg @ref LL_SPI_GRP1_EXTI4_TRG - * @arg @ref LL_SPI_GRP1_EXTI9_TRG - * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG - * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG - * @arg @ref LL_SPI_GRP1_COMP1_TRG - * @arg @ref LL_SPI_GRP1_COMP2_TRG - * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG - * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG - * @arg @ref LL_SPI_GRP2_EXTI4_TRG - * @arg @ref LL_SPI_GRP2_EXTI8_TRG - * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG - * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG - * @arg @ref LL_SPI_GRP2_COMP1_TRG - * @arg @ref LL_SPI_GRP2_COMP2_TRG - * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG - * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetSelectedTrigger(SPI_TypeDef *SPIx, uint32_t Trigger) -{ - MODIFY_REG(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL, (Trigger & SPI_AUTOCR_TRIGSEL_Msk)); -} - -/** - * @brief Get the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_SPI_GetSelectedTrigger - * @param SPIx SPI Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_GRP1_GPDMA_CH0_TCF_TRG - * @arg @ref LL_SPI_GRP1_GPDMA_CH1_TCF_TRG - * @arg @ref LL_SPI_GRP1_GPDMA_CH2_TCF_TRG - * @arg @ref LL_SPI_GRP1_GPDMA_CH3_TCF_TRG - * @arg @ref LL_SPI_GRP1_EXTI4_TRG - * @arg @ref LL_SPI_GRP1_EXTI9_TRG - * @arg @ref LL_SPI_GRP1_LPTIM1_CH1_TRG - * @arg @ref LL_SPI_GRP1_LPTIM2_CH1_TRG - * @arg @ref LL_SPI_GRP1_COMP1_TRG - * @arg @ref LL_SPI_GRP1_COMP2_TRG - * @arg @ref LL_SPI_GRP1_RTC_ALRA_TRG - * @arg @ref LL_SPI_GRP1_RTC_WUT_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH0_TCF_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH1_TCF_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH2_TCF_TRG - * @arg @ref LL_SPI_GRP2_LPDMA_CH3_TCF_TRG - * @arg @ref LL_SPI_GRP2_EXTI4_TRG - * @arg @ref LL_SPI_GRP2_EXTI8_TRG - * @arg @ref LL_SPI_GRP2_LPTIM1_CH1_TRG - * @arg @ref LL_SPI_GRP2_LPTIM3_CH1_TRG - * @arg @ref LL_SPI_GRP2_COMP1_TRG - * @arg @ref LL_SPI_GRP2_COMP2_TRG - * @arg @ref LL_SPI_GRP2_RTC_ALRA_TRG - * @arg @ref LL_SPI_GRP2_RTC_WUT_TRG - */ -__STATIC_INLINE uint32_t LL_SPI_GetSelectedTrigger(const SPI_TypeDef *SPIx) -{ -#if defined(LL_SPI_TRIG_GRP2) - if (IS_LL_SPI_GRP2_INSTANCE(SPIx)) - { - return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP2)); - } - else - { - return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); - } -#else - return (uint32_t)((READ_BIT(SPIx->AUTOCR, SPI_AUTOCR_TRIGSEL) | LL_SPI_TRIG_GRP1)); -#endif /* LL_SPI_TRIG_GRP2 */ -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); -ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); -void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ -/** - * @} - */ -/** - * @} - */ - - -#endif /* defined(SPI1) || defined(SPI2) || defined(SPI3) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_SPI_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h deleted file mode 100644 index 45b5f811d..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_system.h +++ /dev/null @@ -1,1799 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_system.h - * @author MCD Application Team - * @brief Header file of SYSTEM LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL SYSTEM driver contains a set of generic APIs that can be - used by user: - (+) Some of the FLASH features need to be handled in the SYSTEM file. - (+) Access to DBGCMU registers - (+) Access to SYSCFG registers - (+) Access to VREFBUF registers - @endverbatim - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_SYSTEM_H -#define STM32U5xx_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @brief Power-down in Run mode Flash key - */ -#define LL_FLASH_PDKEY1_1 0x04152637U /*!< Flash Bank1 power down key1 */ -#define LL_FLASH_PDKEY1_2 0xFAFBFCFDU /*!< Flash Bank1 power down key2: used with FLASH_PDKEY1 - to unlock the RUN_PD bit in FLASH_ACR */ - -#define LL_FLASH_PDKEY2_1 0x40516273U /*!< Flash Bank2 power down key1 */ -#define LL_FLASH_PDKEY2_2 0xAFBFCFDFU /*!< Flash Bank2 power down key2: used with FLASH_PDKEY2_1 - to unlock the RUN_PD bit in FLASH_ACR */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_CS1 SYSCFG Vdd compensation cell Code selection - * @{ - */ -#define LL_SYSCFG_VDD_CELL_CODE 0U /*VDD I/Os code from the cell - (available in the SYSCFG_CCVR)*/ -#define LL_SYSCFG_VDD_REGISTER_CODE SYSCFG_CCCSR_CS1 /*VDD I/Os code from the SYSCFG compensation - cell code register (SYSCFG_CCCR)*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_CS2 SYSCFG VddIO2 compensation cell Code selection - * @{ - */ -#define LL_SYSCFG_VDDIO2_CELL_CODE 0U /*VDDIO2 I/Os code from the cell - (available in the SYSCFG_CCVR)*/ -#define LL_SYSCFG_VDDIO2_REGISTER_CODE SYSCFG_CCCSR_CS2 /*VDDIO2 I/Os code from the SYSCFG compensation - cell code register (SYSCFG_CCCR)*/ -/** - * @} - */ - -#if defined(SYSCFG_CCCSR_CS3) -/** @defgroup SYSTEM_LL_EC_CS3 SYSCFG VddHSPI compensation cell Code selection - * @{ - */ -#define LL_SYSCFG_VDDHSPI_CELL_CODE 0U /*VDD HSPI I/Os code from the cell - (available in the SYSCFG_CCVR)*/ -#define LL_SYSCFG_VDDHSPI_REGISTER_CODE SYSCFG_CCCSR_CS3 /*VDD HSPI I/Os code from the SYSCFG compensation - cell code register (SYSCFG_CCCR)*/ -/** - * @} - */ -#endif /* SYSCFG_CCCSR_CS3 */ - -/** @defgroup SYSTEM_LL_EC_ERASE_MEMORIES_STATUS SYSCFG MEMORIES ERASE STATUS - * @{ - */ -#define LL_SYSCFG_MEMORIES_ERASE_ON_GOING 0U /*Memory erase on going*/ -#define LL_SYSCFG_MEMORIES_ERASE_ENDED SYSCFG_MESR_MCLR /*Memory erase done */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - -/** @defgroup SYSTEM_LL_EC_FASTMODEPLUS SYSCFG FASTMODEPLUS - * @{ - */ -#define LL_SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ -#define LL_SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ -#define LL_SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ -#define LL_SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK - * @{ - */ -#define LL_SYSCFG_TIMBREAK_ECC SYSCFG_CFGR2_ECCL /*!< Enables and locks the ECC error signal - with Break Input of TIM1/8/15/16/17 */ -#define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CFGR2_PVDL /*!< Enables and locks the PVD connection - with TIM1/8/15/16/17 Break Input and also the PVDE - and PLS bits of the Power Control Interface */ -#define LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK SYSCFG_CFGR2_SPL /*!< Enables and locks the SRAM ECC double error signal - with Break Input of TIM1/8/15/16/17 */ -#define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CFGR2_CLL /*!< Enables and locks the LOCKUP output of CortexM33 - with Break Input of TIM1/15/16/17 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_SECURE_ATTRIBUTES Secure attributes - * @note Only available when system implements security (TZEN=1) - * @{ - */ -#define LL_SYSCFG_CLOCK_SEC SYSCFG_SECCFGR_SYSCFGSEC /*!< SYSCFG clock configuration secure-only access */ -#define LL_SYSCFG_CLOCK_NSEC 0U /*!< SYSCFG clock configuration secure/non-secure access */ -#define LL_SYSCFG_CLASSB_SEC SYSCFG_SECCFGR_CLASSBSEC /*!< Class B configuration secure-only access */ -#define LL_SYSCFG_CLASSB_NSEC 0U /*!< Class B configuration secure/non-secure access */ -#define LL_SYSCFG_FPU_SEC SYSCFG_SECCFGR_FPUSEC /*!< FPU configuration secure-only access */ -#define LL_SYSCFG_FPU_NSEC 0U /*!< FPU configuration secure/non-secure access */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment - * @{ - */ -#define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */ -#define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */ -#define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1FZR1_DBG_TIM2_STOP /*!< The counter clock of TIM2 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1FZR1_DBG_TIM3_STOP /*!< The counter clock of TIM3 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1FZR1_DBG_TIM4_STOP /*!< The counter clock of TIM4 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1FZR1_DBG_TIM5_STOP /*!< The counter clock of TIM5 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1FZR1_DBG_TIM6_STOP /*!< The counter clock of TIM6 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1FZR1_DBG_TIM7_STOP /*!< The counter clock of TIM7 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1FZR1_DBG_WWDG_STOP /*!< The window watchdog counter clock is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1FZR1_DBG_IWDG_STOP /*!< The independent watchdog counter clock is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1FZR1_DBG_I2C1_STOP /*!< The I2C1 SMBus timeout is frozen*/ -#define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1FZR1_DBG_I2C2_STOP /*!< The I2C2 SMBus timeout is frozen*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB1_GRP2_STOP_IP DBGMCU APB1 GRP2 STOP IP - * @{ - */ -#define LL_DBGMCU_APB1_GRP2_I2C4_STOP DBGMCU_APB1FZR2_DBG_I2C4_STOP /*!< The I2C4 SMBus timeout is frozen*/ -#define LL_DBGMCU_APB1_GRP2_LPTIM2_STOP DBGMCU_APB1FZR2_DBG_LPTIM2_STOP /*!< The counter clock of LPTIM2 is stopped when the core is halted*/ -#define LL_DBGMCU_APB1_GRP2_I2C5_STOP DBGMCU_APB1FZR2_DBG_I2C5_STOP /*!< The I2C5 SMBus timeout is frozen*/ -#define LL_DBGMCU_APB1_GRP2_I2C6_STOP DBGMCU_APB1FZR2_DBG_I2C6_STOP /*!< The I2C6 SMBus timeout is frozen*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2FZR_DBG_TIM1_STOP /*!< The counter clock of TIM1 is stopped when the core is halted*/ -#define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2FZR_DBG_TIM8_STOP /*!< The counter clock of TIM8 is stopped when the core is halted*/ -#define LL_DBGMCU_APB2_GRP1_TIM15_STOP DBGMCU_APB2FZR_DBG_TIM15_STOP /*!< The counter clock of TIM15 is stopped when the core is halted*/ -#define LL_DBGMCU_APB2_GRP1_TIM16_STOP DBGMCU_APB2FZR_DBG_TIM16_STOP /*!< The counter clock of TIM16 is stopped when the core is halted*/ -#define LL_DBGMCU_APB2_GRP1_TIM17_STOP DBGMCU_APB2FZR_DBG_TIM17_STOP /*!< The counter clock of TIM17 is stopped when the core is halted*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB3_GRP1_STOP_IP DBGMCU APB3 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_APB3_GRP1_I2C3_STOP DBGMCU_APB3FZR_DBG_I2C3_STOP /*!< The counter clock of I2C3 is stopped when the core is halted*/ -#define LL_DBGMCU_APB3_GRP1_LPTIM1_STOP DBGMCU_APB3FZR_DBG_LPTIM1_STOP /*!< The counter clock of LPTIM1 is stopped when the core is halted*/ -#define LL_DBGMCU_APB3_GRP1_LPTIM3_STOP DBGMCU_APB3FZR_DBG_LPTIM3_STOP /*!< The counter clock of LPTIM3 is stopped when the core is halted*/ -#define LL_DBGMCU_APB3_GRP1_LPTIM4_STOP DBGMCU_APB3FZR_DBG_LPTIM4_STOP /*!< The counter clock of LPTIM4 is stopped when the core is halted*/ -#define LL_DBGMCU_APB3_GRP1_RTC_STOP DBGMCU_APB3FZR_DBG_RTC_STOP /*!< The counter clock of RTC is stopped when the core is halted*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_AHB1_GRP1_STOP_IP DBGMCU AHB1 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP DBGMCU_AHB1FZR_DBG_GPDMA0_STOP /*!< The counter clock of GPDMA0 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP DBGMCU_AHB1FZR_DBG_GPDMA1_STOP /*!< The counter clock of GPDMA1 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP DBGMCU_AHB1FZR_DBG_GPDMA2_STOP /*!< The counter clock of GPDMA2 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP DBGMCU_AHB1FZR_DBG_GPDMA3_STOP /*!< The counter clock of GPDMA3 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP DBGMCU_AHB1FZR_DBG_GPDMA4_STOP /*!< The counter clock of GPDMA4 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP DBGMCU_AHB1FZR_DBG_GPDMA5_STOP /*!< The counter clock of GPDMA5 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP DBGMCU_AHB1FZR_DBG_GPDMA6_STOP /*!< The counter clock of GPDMA6 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP DBGMCU_AHB1FZR_DBG_GPDMA7_STOP /*!< The counter clock of GPDMA7 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP DBGMCU_AHB1FZR_DBG_GPDMA8_STOP /*!< The counter clock of GPDMA8 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP DBGMCU_AHB1FZR_DBG_GPDMA9_STOP /*!< The counter clock of GPDMA9 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP DBGMCU_AHB1FZR_DBG_GPDMA10_STOP /*!< The counter clock of GPDMA10 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP DBGMCU_AHB1FZR_DBG_GPDMA11_STOP /*!< The counter clock of GPDMA11 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP DBGMCU_AHB1FZR_DBG_GPDMA12_STOP /*!< The counter clock of GPDMA12 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP DBGMCU_AHB1FZR_DBG_GPDMA13_STOP /*!< The counter clock of GPDMA13 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP DBGMCU_AHB1FZR_DBG_GPDMA14_STOP /*!< The counter clock of GPDMA14 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP DBGMCU_AHB1FZR_DBG_GPDMA15_STOP /*!< The counter clock of GPDMA15 is stopped when the core is halted*/ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_AHB3_GRP1_STOP_IP DBGMCU AHB3 GRP1 STOP IP - * @{ - */ -#define LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP DBGMCU_AHB3FZR_DBG_LPDMA0_STOP /*!< The counter clock of LPDMA0 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP DBGMCU_AHB3FZR_DBG_LPDMA1_STOP /*!< The counter clock of LPDMA1 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP DBGMCU_AHB3FZR_DBG_LPDMA2_STOP /*!< The counter clock of LPDMA2 is stopped when the core is halted*/ -#define LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP DBGMCU_AHB3FZR_DBG_LPDMA3_STOP /*!< The counter clock of LPDMA3 is stopped when the core is halted*/ -/** - * @} - */ - -#if defined(VREFBUF) -/** @defgroup SYSTEM_LL_EC_VOLTAGE VREFBUF VOLTAGE - * @{ - */ -#define LL_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ -#define LL_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS_0 /*!< Voltage reference scale 1 (VREF_OUT2) */ -#define LL_VREFBUF_VOLTAGE_SCALE2 VREFBUF_CSR_VRS_1 /*!< Voltage reference scale 0 (VREF_OUT3) */ -#define LL_VREFBUF_VOLTAGE_SCALE3 VREFBUF_CSR_VRS_2 /*!< Voltage reference scale 1 (VREF_OUT4) */ -/** - * @} - */ -#endif /* VREFBUF */ - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH zero wait state */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH one wait state */ -#define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH two wait states */ -#define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH three wait states */ -#define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH four wait states */ -#define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait states */ -#define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */ -#define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH Seven wait states */ -#define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH Eight wait states */ -#define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */ -#define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */ -#define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */ -#define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */ -#define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */ -#define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */ -#define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - -/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG - * @{ - */ - -/** - * @brief Enable I/O analog switches supplied by VDD. - * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_EnableAnalogSwitchVdd - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableAnalogSwitchVdd(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); -} - -/** - * @brief Disable I/O analog switches supplied by VDD. - * @note I/O analog switches are supplied by VDDA or booster - * when booster in on. - * Dedicated voltage booster (supplied by VDD) is the recommended - * configuration with low VDDA voltage operation. - * @rmtoll SYSCFG_CFGR1 ANASWVDD LL_SYSCFG_DisableAnalogSwitchVdd - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableAnalogSwitchVdd(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); -} - -/** - * @brief Enable I/O analog switch voltage booster. - * @note When voltage booster is enabled, I/O analog switches are supplied - * by a dedicated voltage booster, from VDD power domain. This is - * the recommended configuration with low VDDA voltage operation. - * @note The I/O analog switch voltage booster is relevant for peripherals - * using I/O in analog input: ADC, COMP, OPAMP. - * However, COMP and OPAMP inputs have a high impedance and - * voltage booster do not impact performance significantly. - * Therefore, the voltage booster is mainly intended for - * usage with ADC. - * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_EnableAnalogBooster - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableAnalogBooster(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Disable I/O analog switch voltage booster. - * @note When voltage booster is enabled, I/O analog switches are supplied - * by a dedicated voltage booster, from VDD power domain. This is - * the recommended configuration with low VDDA voltage operation. - * @note The I/O analog switch voltage booster is relevant for peripherals - * using I/O in analog input: ADC, COMP, OPAMP. - * However, COMP and OPAMP inputs have a high impedance and - * voltage booster do not impact performance significantly. - * Therefore, the voltage booster is mainly intended for - * usage with ADC. - * @rmtoll SYSCFG_CFGR1 BOOSTEN LL_SYSCFG_DisableAnalogBooster - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableAnalogBooster(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Enable the fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_EnableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus) -{ - SET_BIT(SYSCFG->CFGR1, ConfigFastModePlus); -} - -/** - * @brief Disable the fast mode plus driving capability. - * @rmtoll SYSCFG_CFGR1 PBx_FMP LL_SYSCFG_DisableFastModePlus - * @param ConfigFastModePlus This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB6 - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB7 - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB8 - * @arg @ref LL_SYSCFG_FASTMODEPLUS_PB9 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus) -{ - CLEAR_BIT(SYSCFG->CFGR1, ConfigFastModePlus); -} - -/** - * @brief Enable Floating Point Unit Invalid operation Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_EnableIT_FPU_IOC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IOC(void) -{ - SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0); -} - -/** - * @brief Enable Floating Point Unit Divide-by-zero Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_EnableIT_FPU_DZC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_DZC(void) -{ - SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1); -} - -/** - * @brief Enable Floating Point Unit Underflow Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_EnableIT_FPU_UFC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_UFC(void) -{ - SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2); -} - -/** - * @brief Enable Floating Point Unit Overflow Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_EnableIT_FPU_OFC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_OFC(void) -{ - SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3); -} - -/** - * @brief Enable Floating Point Unit Input denormal Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_EnableIT_FPU_IDC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IDC(void) -{ - SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4); -} - -/** - * @brief Enable Floating Point Unit Inexact Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_EnableIT_FPU_IXC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableIT_FPU_IXC(void) -{ - SET_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5); -} - -/** - * @brief Disable Floating Point Unit Invalid operation Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_DisableIT_FPU_IOC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IOC(void) -{ - CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0); -} - -/** - * @brief Disable Floating Point Unit Divide-by-zero Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_DisableIT_FPU_DZC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_DZC(void) -{ - CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1); -} - -/** - * @brief Disable Floating Point Unit Underflow Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_DisableIT_FPU_UFC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_UFC(void) -{ - CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2); -} - -/** - * @brief Disable Floating Point Unit Overflow Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_DisableIT_FPU_OFC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_OFC(void) -{ - CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3); -} - -/** - * @brief Disable Floating Point Unit Input denormal Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_DisableIT_FPU_IDC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IDC(void) -{ - CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4); -} - -/** - * @brief Disable Floating Point Unit Inexact Interrupt - * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_DisableIT_FPU_IXC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableIT_FPU_IXC(void) -{ - CLEAR_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5); -} - -/** - * @brief Check if Floating Point Unit Invalid operation Interrupt source is enabled or disabled. - * @rmtoll SYSCFG_FPUIMR FPU_IE_0 LL_SYSCFG_IsEnabledIT_FPU_IOC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IOC(void) -{ - return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_0) == SYSCFG_FPUIMR_FPU_IE_0) ? 1UL : 0UL); -} - -/** - * @brief Check if Floating Point Unit Divide-by-zero Interrupt source is enabled or disabled. - * @rmtoll SYSCFG_FPUIMR FPU_IE_1 LL_SYSCFG_IsEnabledIT_FPU_DZC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_DZC(void) -{ - return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_1) == SYSCFG_FPUIMR_FPU_IE_1) ? 1UL : 0UL); -} - -/** - * @brief Check if Floating Point Unit Underflow Interrupt source is enabled or disabled. - * @rmtoll SYSCFG_FPUIMR FPU_IE_2 LL_SYSCFG_IsEnabledIT_FPU_UFC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_UFC(void) -{ - return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_2) == SYSCFG_FPUIMR_FPU_IE_2) ? 1UL : 0UL); -} - -/** - * @brief Check if Floating Point Unit Overflow Interrupt source is enabled or disabled. - * @rmtoll SYSCFG_FPUIMR FPU_IE_3 LL_SYSCFG_IsEnabledIT_FPU_OFC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_OFC(void) -{ - return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_3) == SYSCFG_FPUIMR_FPU_IE_3) ? 1UL : 0UL); -} - -/** - * @brief Check if Floating Point Unit Input denormal Interrupt source is enabled or disabled. - * @rmtoll SYSCFG_FPUIMR FPU_IE_4 LL_SYSCFG_IsEnabledIT_FPU_IDC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IDC(void) -{ - return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_4) == SYSCFG_FPUIMR_FPU_IE_4) ? 1UL : 0UL); -} - -/** - * @brief Check if Floating Point Unit Inexact Interrupt source is enabled or disabled. - * @rmtoll SYSCFG_FPUIMR FPU_IE_5 LL_SYSCFG_IsEnabledIT_FPU_IXC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledIT_FPU_IXC(void) -{ - return ((READ_BIT(SYSCFG->FPUIMR, SYSCFG_FPUIMR_FPU_IE_5) == SYSCFG_FPUIMR_FPU_IE_5) ? 1UL : 0UL); -} - -/** - * @brief Set connections to TIM1/8/15/16/17 Break inputs - * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 SPL LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 PVDL LL_SYSCFG_SetTIMBreakInputs\n - * SYSCFG_CFGR2 ECCL LL_SYSCFG_SetTIMBreakInputs - * @param Break This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_ECC - * @arg @ref LL_SYSCFG_TIMBREAK_PVD - * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break) -{ - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL, Break); -} - -/** - * @brief Get connections to TIM1/8/15/16/17 Break inputs - * @rmtoll SYSCFG_CFGR2 CLL LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 SPL LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 PVDL LL_SYSCFG_GetTIMBreakInputs\n - * SYSCFG_CFGR2 ECCL LL_SYSCFG_GetTIMBreakInputs - * @retval Returned value can be can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_ECC - * @arg @ref LL_SYSCFG_TIMBREAK_PVD - * @arg @ref LL_SYSCFG_TIMBREAK_SRAM_ECC_LOCK - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetTIMBreakInputs(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL | SYSCFG_CFGR2_SPL | \ - SYSCFG_CFGR2_PVDL | SYSCFG_CFGR2_ECCL)); -} - - -/** @defgroup SYSTEM_LL_EF_SYSCFG_Secure_Management Secure Management - * @{ - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** - * @brief Configure Secure mode - * @note Only available from secure state when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @param Configuration This parameter shall be the full combination - * of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ConfigSecure(uint32_t Configuration) -{ - WRITE_REG(SYSCFG->SECCFGR, Configuration); -} - -#endif /* __ARM_FEATURE_CMSE && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Get Secure mode configuration - * @note Only available when system implements security (TZEN=1) - * @rmtoll SECCFGR SYSCFGSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR CLASSBSEC LL_SYSCFG_ConfigSecure\n - * SECCFGR FPUSEC LL_SYSCFG_ConfigSecure - * @retval Returned value is the combination of the following values: - * @arg @ref LL_SYSCFG_CLOCK_SEC or LL_SYSCFG_CLOCK_NSEC - * @arg @ref LL_SYSCFG_CLASSB_SEC or LL_SYSCFG_CLASSB_NSEC - * @arg @ref LL_SYSCFG_FPU_SEC or LL_SYSCFG_FPU_NSEC - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetConfigSecure(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->SECCFGR, 0xBU)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_COMPENSATION SYSCFG COMPENSATION - * @{ - */ - -/** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDD - * @rmtoll CCVR PCV1 LL_SYSCFG_GetPMOSVddCompensationValue - * @retval Returned value is the PMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationValue(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV1)); -} - -/** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDD - * @rmtoll CCVR NCV1 LL_SYSCFG_GetNMOSVddCompensationValue - * @retval Returned value is the NMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationValue(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV1)); -} - -/** - * @brief Get the compensation cell value of the GPIO PMOS transistor supplied by VDDIO2 - * @rmtoll CCVR PCV2 LL_SYSCFG_GetPMOSVddIO2CompensationValue - * @retval Returned value is the PMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationValue(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV2)); -} - -/** - * @brief Get the compensation cell value of the GPIO NMOS transistor supplied by VDDIO2 - * @rmtoll CCVR NCV2 LL_SYSCFG_GetNMOSVddIO2CompensationValue - * @retval Returned value is the NMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationValue(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV2)); -} - -#if defined(SYSCFG_CCVR_PCV3) -/** - * @brief Get the compensation cell value of the HSPI IO PMOS transistor supplied by VDD - * @rmtoll CCVR PCV3 LL_SYSCFG_GetPMOSVddHSPICompensationValue - * @retval Returned value is the PMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationValue(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_PCV3)); -} - -/** - * @brief Get the compensation cell value of the HSPI IO NMOS transistor supplied by VDD - * @rmtoll CCVR NCV3 LL_SYSCFG_GetNMOSVddHSPICompensationValue - * @retval Returned value is the NMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationValue(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCVR, SYSCFG_CCVR_NCV3)); -} -#endif /* SYSCFG_CCVR_PCV3 */ - -/** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDD - * @rmtoll CCCR PCC1 LL_SYSCFG_SetPMOSVddCompensationCode - * @param PMOSCode PMOS compensation code - * This code is applied to the PMOS compensation cell when the CS1 bit of the - * SYSCFG_CCCSR is set - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetPMOSVddCompensationCode(uint32_t PMOSCode) -{ - MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC1, PMOSCode << SYSCFG_CCCR_PCC1_Pos); -} - -/** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDD - * @rmtoll CCCR PCC1 LL_SYSCFG_GetPMOSVddCompensationCode - * @retval Returned value is the PMOS compensation cell - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddCompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC1)); -} - -/** - * @brief Set the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 - * @rmtoll CCCR PCC2 LL_SYSCFG_SetPMOSVddIO2CompensationCode - * @param PMOSCode PMOS compensation code - * This code is applied to the PMOS compensation cell when the CS2 bit of the - * SYSCFG_CCCSR is set - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetPMOSVddIO2CompensationCode(uint32_t PMOSCode) -{ - MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC2, PMOSCode << SYSCFG_CCCR_PCC2_Pos); -} - - -/** - * @brief Get the compensation cell code of the GPIO PMOS transistor supplied by VDDIO2 - * @rmtoll CCCR PCC2 LL_SYSCFG_GetPMOSVddIO2CompensationCode - * @retval Returned value is the PMOS compensation - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddIO2CompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC2)); -} - -#if defined(SYSCFG_CCCR_PCC3) -/** - * @brief Set the compensation cell code of the HSPI IO PMOS transistor supplied by VDD - * @rmtoll CCCR PCC3 LL_SYSCFG_SetPMOSVddHSPICompensationCode - * @param PMOSCode PMOS compensation code - * This code is applied to the PMOS compensation cell when the CS3 bit of the - * SYSCFG_CCCSR is set - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetPMOSVddHSPICompensationCode(uint32_t PMOSCode) -{ - MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_PCC3, PMOSCode << SYSCFG_CCCR_PCC3_Pos); -} - -/** - * @brief Get the compensation cell code of the HSPI IO PMOS transistor supplied by VDD - * @rmtoll CCCR PCC3 LL_SYSCFG_GetPMOSVddHSPICompensationCode - * @retval Returned value is the PMOS compensation - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetPMOSVddHSPICompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_PCC3)); -} -#endif /* SYSCFG_CCCR_PCC3 */ - -/** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDD - * @rmtoll CCCR PCC2 LL_SYSCFG_SetNMOSVddCompensationCode - * @param NMOSCode NMOS compensation code - * This code is applied to the NMOS compensation cell when the CS2 bit of the - * SYSCFG_CMPCR is set - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetNMOSVddCompensationCode(uint32_t NMOSCode) -{ - MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC1, NMOSCode << SYSCFG_CCCR_NCC1_Pos); -} - -/** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDD - * @rmtoll CCCR NCC1 LL_SYSCFG_GetNMOSVddCompensationCode - * @retval Returned value is the Vdd compensation cell code for NMOS transistors - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddCompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC1)); -} - -/** - * @brief Set the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 - * @rmtoll CCCR NCC2 LL_SYSCFG_SetNMOSVddIO2CompensationCode - * @param NMOSCode NMOS compensation code - * This code is applied to the NMOS compensation cell when the CS2 bit of the - * SYSCFG_CMPCR is set - * Value between 0 and 15 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetNMOSVddIO2CompensationCode(uint32_t NMOSCode) -{ - MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC2, NMOSCode << SYSCFG_CCCR_NCC2_Pos); -} - - -/** - * @brief Get the compensation cell code of the GPIO NMOS transistor supplied by VDDIO2 - * @rmtoll CCCR NCC2 LL_SYSCFG_GetNMOSVddIO2CompensationCode - * @retval Returned value is the NMOS compensation cell code - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddIO2CompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC2)); -} - -#if defined(SYSCFG_CCCR_NCC3) -/** - * @brief Set the compensation cell code of the HSPI IO NMOS transistor supplied by VDD - * @rmtoll CCCR NCC3 LL_SYSCFG_SetNMOSVddHSPICompensationCode - * @param NMOSCode NMOS compensation code - * This code is applied to the NMOS compensation cell when the CS3 bit of the - * SYSCFG_CCCSR is set - * Value between 0 and 15 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetNMOSVddHSPICompensationCode(uint32_t NMOSCode) -{ - MODIFY_REG(SYSCFG->CCCR, SYSCFG_CCCR_NCC3, NMOSCode << SYSCFG_CCCR_NCC3_Pos); -} - -/** - * @brief Get the compensation cell code of the HSPI IO NMOS transistor supplied by VDD - * @rmtoll CCCR NCC3 LL_SYSCFG_GetNMOSVddHSPICompensationCode - * @retval Returned value is the NMOS compensation cell code - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetNMOSVddHSPICompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCR, SYSCFG_CCCR_NCC3)); -} -#endif /* SYSCFG_CCCR_NCC3 */ - -/** - * @brief Enable the Compensation Cell of GPIO supplied by VDD - * @rmtoll CCCSR EN1 LL_SYSCFG_EnableVddCompensationCell - * @note The vdd compensation cell can be used only when the device supply - * voltage ranges from 1.71 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableVddCompensationCell(void) -{ - SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); -} - -/** - * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 - * @rmtoll CCCSR EN2 LL_SYSCFG_EnableVddIO2CompensationCell - * @note The Vdd I/O compensation cell can be used only when the device supply - * voltage ranges from 1.08 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableVddIO2CompensationCell(void) -{ - SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); -} - -#if defined(SYSCFG_CCCSR_EN3) -/** - * @brief Enable the Compensation Cell of HSPI IO supplied by VDD - * @rmtoll CCCSR EN3 LL_SYSCFG_EnableVddHSPICompensationCell - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableVddHSPICompensationCell(void) -{ - SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); -} -#endif /* SYSCFG_CCCSR_EN3 */ - -/** - * @brief Disable the Compensation Cell of GPIO supplied by VDD - * @rmtoll CCCSR EN1 LL_SYSCFG_DisableVddCompensationCell - * @note The Vdd compensation cell can be used only when the device supply - * voltage ranges from 1.71 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableVddCompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); -} - -/** - * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 - * @rmtoll CCCSR EN2 LL_SYSCFG_DisableVddIO2CompensationCell - * @note The Vdd I/O compensation cell can be used only when the device supply - * voltage ranges from 1.08 to 3.6 V - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableVddIO2CompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); -} - -#if defined(SYSCFG_CCCSR_EN3) -/** - * @brief Disable the Compensation Cell of HSPI IO supplied by VDD - * @rmtoll CCCSR EN3 LL_SYSCFG_DisableVddHSPICompensationCell - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableVddHSPICompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); -} -#endif /* SYSCFG_CCCSR_EN3 */ - -/** - * @brief Check if the Compensation Cell of GPIO supplied by VDD is enable - * @rmtoll CCCSR EN1 LL_SYSCFG_IsEnabled_VddCompensationCell - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddCompensationCell(void) -{ - return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1) == SYSCFG_CCCSR_EN1) ? 1UL : 0UL); -} - -/** - * @brief Check if the Compensation Cell of GPIO supplied by VDDIO2 is enable - * @rmtoll CCCSR EN2 LL_SYSCFG_IsEnabled_VddIO2CompensationCell - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddIO2CompensationCell(void) -{ - return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2) == SYSCFG_CCCSR_EN2) ? 1UL : 0UL); -} - -#if defined(SYSCFG_CCCSR_EN3) -/** - * @brief Check if the Compensation Cell of HSPI IO supplied by VDD is enable - * @rmtoll CCCSR EN3 LL_SYSCFG_IsEnabled_VddHSPICompensationCell - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabled_VddHSPICompensationCell(void) -{ - return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3) == SYSCFG_CCCSR_EN3) ? 1UL : 0UL); -} -#endif /* SYSCFG_CCCSR_EN3 */ - -/** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDD - * @rmtoll CCCSR RDY1 LL_SYSCFG_IsActiveFlag_VddCMPCR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddCMPCR(void) -{ - return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY1) == (SYSCFG_CCCSR_RDY1)) ? 1UL : 0UL); -} - -/** - * @brief Get Compensation Cell ready Flag of GPIO supplied by VDDIO2 - * @rmtoll CCCSR RDY2 LL_SYSCFG_IsActiveFlag_VddIO2CMPCR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddIO2CMPCR(void) -{ - return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY2) == (SYSCFG_CCCSR_RDY2)) ? 1UL : 0UL); -} - -#if defined(SYSCFG_CCCSR_RDY3) -/** - * @brief Get Compensation Cell ready Flag of HSPI IO supplied by VDD - * @rmtoll CCCSR RDY3 LL_SYSCFG_IsActiveFlag_VddHSPICMPCR - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsActiveFlag_VddHSPICMPCR(void) -{ - return ((READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_RDY3) == (SYSCFG_CCCSR_RDY3)) ? 1UL : 0UL); -} -#endif /* SYSCFG_CCCSR_RDY3 */ - -/** - * @brief Set the compensation cell code selection of GPIO supplied by VDD - * @rmtoll CCCSR CS1 LL_SYSCFG_SetVddCellCompensationCode - * @param CompCode: Selects the code to be applied for the Vdd compensation cell - * This parameter can be one of the following values: - * @arg LL_SYSCFG_VDD_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) - * @arg LL_SYSCFG_VDD_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetVddCellCompensationCode(uint32_t CompCode) -{ - SET_BIT(SYSCFG->CCCSR, CompCode); -} - -/** - * @brief Set the compensation cell code selection of GPIO supplied by VDDIO2 - * @rmtoll CCCSR CS2 LL_SYSCFG_SetVddIO2CellCompensationCode - * @param CompCode: Selects the code to be applied for the VddIO compensation cell - * This parameter can be one of the following values: - * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) - * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetVddIO2CellCompensationCode(uint32_t CompCode) -{ - SET_BIT(SYSCFG->CCCSR, CompCode); -} - -#if defined(SYSCFG_CCCSR_CS3) -/** - * @brief Set the compensation cell code selection of HSPI IO supplied by VDD - * @rmtoll CCCSR CS3 LL_SYSCFG_SetVddHSPICellCompensationCode - * @param CompCode: Selects the code to be applied for the VddIO compensation cell - * This parameter can be one of the following values: - * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Select Code from the cell (available in the SYSCFG_CCVR) - * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Select Code from the SYSCFG compensation cell code register (SYSCFG_CCCR) - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetVddHSPICellCompensationCode(uint32_t CompCode) -{ - SET_BIT(SYSCFG->CCCSR, CompCode); -} -#endif /* SYSCFG_CCCSR_CS3 */ - -/** - * @brief Get the compensation cell code selection of GPIO supplied by VDD - * @rmtoll CCCSR CS1 LL_SYSCFG_GetVddCellCompensationCode - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_VDD_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) - * @arg LL_SYSCFG_VDD_REGISTER_CODE: Selected Code is from the SYSCFG compensation cell code register (SYSCFG_CCCR) - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetVddCellCompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS1)); -} - -/** - * @brief Get the compensation cell code selection of GPIO supplied by VDDIO2 - * @rmtoll CCCSR CS2 LL_SYSCFG_GetVddIO2CellCompensationCode - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_VDDIO2_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) - * @arg LL_SYSCFG_VDDIO2_REGISTER_CODE: Selected Code is from the SYSCFG compensation - cell code register (SYSCFG_CCCR) - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetVddIO2CellCompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS2)); -} - -#if defined(SYSCFG_CCCSR_CS3) -/** - * @brief Get the compensation cell code selection of HSPI IO supplied by VDD - * @rmtoll CCCSR CS3 LL_SYSCFG_GetVddHSPICellCompensationCode - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_VDDHSPI_CELL_CODE : Selected Code is from the cell (available in the SYSCFG_CCVR) - * @arg LL_SYSCFG_VDDHSPI_REGISTER_CODE: Selected Code is from the SYSCFG compensation - cell code register (SYSCFG_CCCR) - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetVddHSPICellCompensationCode(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_CS3)); -} -#endif /* SYSCFG_CCCSR_CS3 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU - * @{ - */ - -/** - * @brief Return the device identifier - * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF (ex: device ID is 0x6415) - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @note This field indicates the revision of the device. - * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - -/** - * @brief Enable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode - * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - - -/** - * @brief Enable the Debug Clock Trace - * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_EnableTraceClock - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableTraceClock(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); -} - -/** - * @brief Disable the Debug Clock Trace - * @rmtoll DBGMCU_CR TRACE_CLKEN LL_DBGMCU_DisableTraceClock - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableTraceClock(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN); -} - - -/** - * @brief Check if clock trace is enabled or disabled. - * @rmtoll DBGMCU_CR_TRACE_CLKEN LL_DBGMCU_IsEnabledTraceClock - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledTraceClock(void) -{ - return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_CLKEN) == DBGMCU_CR_TRACE_CLKEN) ? 1UL : 0UL); -} - -/** - * @brief Set Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment - * @param PinAssignment This parameter can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment) -{ - MODIFY_REG(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE, PinAssignment); -} - -/** - * @brief Get Trace pin assignment control - * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n - * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment - * @retval Returned value can be one of the following values: - * @arg @ref LL_DBGMCU_TRACE_NONE - * @arg @ref LL_DBGMCU_TRACE_ASYNCH - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2 - * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4 - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetTracePinAssignment(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->CR, DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE)); -} - -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB1FZR1, Periphs); -} - -/** - * @brief Freeze APB1 peripherals (group2 peripherals) - * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_I2C5_STOP (*) - * @arg @ref LL_DBGMCU_APB1_GRP2_I2C6_STOP (*) - * @retval None - * @note (*) Availability depends on devices. - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB1FZR2, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @rmtoll DBGMCU_APB1FZR1 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB1FZR1, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group2 peripherals) - * @rmtoll DBGMCU_APB1FZR2 DBG_xxxx_STOP LL_DBGMCU_APB1_GRP2_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_I2C4_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_LPTIM2_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB1FZR2, Periphs); -} - -/** - * @brief Freeze APB2 peripherals - * @rmtoll DBGMCU_APB2FZ DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB2FZR, Periphs); -} - -/** - * @brief Unfreeze APB2 peripherals - * @rmtoll DBGMCU_APB2FZR DBG_TIMx_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM15_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM16_STOP - * @arg @ref LL_DBGMCU_APB2_GRP1_TIM17_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB2FZR, Periphs); -} - -/** - * @brief Freeze APB3 peripherals - * @rmtoll DBGMCU_APB3FZ DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APB3FZR, Periphs); -} - -/** - * @brief Unfreeze APB3 peripherals - * @rmtoll DBGMCU_APB3FZR DBG_TIMx_STOP LL_DBGMCU_APB3_GRP1_UnFreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB3_GRP1_I2C3_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM1_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM3_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_LPTIM4_STOP - * @arg @ref LL_DBGMCU_APB3_GRP1_RTC_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB3_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APB3FZR, Periphs); -} - -/** - * @brief Freeze AHB1 peripherals - * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->AHB1FZR, Periphs); -} - -/** - * @brief Unfreeze AHB1 peripherals - * @rmtoll DBGMCU_AHB1FZ DBG_GPDMAx_STOP LL_DBGMCU_AHB1_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA0_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA1_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA2_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA3_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA4_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA5_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA6_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA7_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA8_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA9_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA10_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA11_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA12_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA13_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA14_STOP - * @arg @ref LL_DBGMCU_AHB1_GRP1_GPDMA15_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_AHB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->AHB1FZR, Periphs); -} - -/** - * @brief Freeze AHB3 peripherals - * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->AHB3FZR, Periphs); -} - -/** - * @brief Unfreeze AHB3 peripherals - * @rmtoll DBGMCU_AHB3FZ DBG_LPDMAx_STOP LL_DBGMCU_AHB3_GRP1_FreezePeriph - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA0_STOP - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA1_STOP - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA2_STOP - * @arg @ref LL_DBGMCU_AHB3_GRP1_LPDMA3_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_AHB3_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->AHB3FZR, Periphs); -} - -/** - * @} - */ - -#if defined(VREFBUF) -/** @defgroup SYSTEM_LL_EF_VREFBUF VREFBUF - * @{ - */ - -/** - * @brief Enable Internal voltage reference - * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Enable - * @retval None - */ -__STATIC_INLINE void LL_VREFBUF_Enable(void) -{ - SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); -} - -/** - * @brief Disable Internal voltage reference - * @rmtoll VREFBUF_CSR ENVR LL_VREFBUF_Disable - * @retval None - */ -__STATIC_INLINE void LL_VREFBUF_Disable(void) -{ - CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); -} - -/** - * @brief Enable high impedance (VREF+pin is high impedance) - * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_EnableHIZ - * @retval None - */ -__STATIC_INLINE void LL_VREFBUF_EnableHIZ(void) -{ - SET_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); -} - -/** - * @brief Disable high impedance (VREF+pin is internally connected to the voltage reference buffer output) - * @rmtoll VREFBUF_CSR HIZ LL_VREFBUF_DisableHIZ - * @retval None - */ -__STATIC_INLINE void LL_VREFBUF_DisableHIZ(void) -{ - CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_HIZ); -} - -/** - * @brief Set the Voltage reference scale - * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_SetVoltageScaling - * @param Scale This parameter can be one of the following values: - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 - * @retval None - */ -__STATIC_INLINE void LL_VREFBUF_SetVoltageScaling(uint32_t Scale) -{ - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, Scale); -} - -/** - * @brief Get the Voltage reference scale - * @rmtoll VREFBUF_CSR VRS LL_VREFBUF_GetVoltageScaling - * @retval Returned value can be one of the following values: - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE0 - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE1 - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE2 - * @arg @ref LL_VREFBUF_VOLTAGE_SCALE3 - */ -__STATIC_INLINE uint32_t LL_VREFBUF_GetVoltageScaling(void) -{ - return (uint32_t)(READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRS)); -} - -/** - * @brief Check if Voltage reference buffer is ready - * @rmtoll VREFBUF_CSR VRR LL_VREFBUF_IsVREFReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_VREFBUF_IsVREFReady(void) -{ - return ((READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == VREFBUF_CSR_VRR) ? 1UL : 0UL); -} - -/** - * @brief Get the trimming code for VREFBUF calibration - * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_GetTrimming - * @retval Between 0 and 0x3F - */ -__STATIC_INLINE uint32_t LL_VREFBUF_GetTrimming(void) -{ - return (uint32_t)(READ_BIT(VREFBUF->CCR, VREFBUF_CCR_TRIM)); -} - -/** - * @brief Set the trimming code for VREFBUF calibration (Tune the internal reference buffer voltage) - * @rmtoll VREFBUF_CCR TRIM LL_VREFBUF_SetTrimming - * @param Value Between 0 and 0x3F - * @retval None - */ -__STATIC_INLINE void LL_VREFBUF_SetTrimming(uint32_t Value) -{ - WRITE_REG(VREFBUF->CCR, Value); -} - -/** - * @} - */ -#endif /* VREFBUF */ - -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 - * @arg @ref LL_FLASH_LATENCY_8 - * @arg @ref LL_FLASH_LATENCY_9 - * @arg @ref LL_FLASH_LATENCY_10 - * @arg @ref LL_FLASH_LATENCY_11 - * @arg @ref LL_FLASH_LATENCY_12 - * @arg @ref LL_FLASH_LATENCY_13 - * @arg @ref LL_FLASH_LATENCY_14 - * @arg @ref LL_FLASH_LATENCY_15 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @arg @ref LL_FLASH_LATENCY_2 - * @arg @ref LL_FLASH_LATENCY_3 - * @arg @ref LL_FLASH_LATENCY_4 - * @arg @ref LL_FLASH_LATENCY_5 - * @arg @ref LL_FLASH_LATENCY_6 - * @arg @ref LL_FLASH_LATENCY_7 - * @arg @ref LL_FLASH_LATENCY_8 - * @arg @ref LL_FLASH_LATENCY_9 - * @arg @ref LL_FLASH_LATENCY_10 - * @arg @ref LL_FLASH_LATENCY_11 - * @arg @ref LL_FLASH_LATENCY_12 - * @arg @ref LL_FLASH_LATENCY_13 - * @arg @ref LL_FLASH_LATENCY_14 - * @arg @ref LL_FLASH_LATENCY_15 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @brief Enable Flash Power-down mode during run mode or Low-power run mode - * @note Flash memory can be put in power-down mode only when the code is executed - * from RAM - * @note Flash must not be accessed when power down is enabled - * @note Flash must not be put in power-down while a program or an erase operation - * is on-going - * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableRunPowerDown(void) -{ - /* Following values must be written consecutively to unlock the RUN_PD bit in - FLASH_ACR */ - WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1); - WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2); - WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1); - WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2); - - /*Request to enter flash in power mode */ - SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1 | FLASH_ACR_PDREQ2); -} - -/** - * @brief Enable flash Power-down mode during run mode or Low-power run mode of bank1 - * @note Bank 1 of flash memory can be put in power-down mode only when the code is executed - * from RAM - * @note Bank1 of flash must not be accessed when power down is enabled - * @note Bank1 of flash must not be put in power-down while a program or an erase operation - * is on-going - * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY1_1 LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY1_2 LL_FLASH_EnableRunPowerDown\n - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank1(void) -{ - /* Following values must be written consecutively to unlock the RUN_PD bit in - FLASH_ACR */ - WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_1); - WRITE_REG(FLASH->PDKEY1R, LL_FLASH_PDKEY1_2); - - /*Request to enter flash in power mode */ - SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1); -} - -/** - * @brief Enable flash Power-down mode during run mode or Low-power run mode of Bank2 - * @note Bank 2 of flash memory can be put in power-down mode only when the code is executed - * from RAM - * @note Bank2 of flash must not be accessed when power down is enabled - * @note Bank2 of flash must not be put in power-down while a program or an erase operation - * is on-going - * @rmtoll FLASH_ACR RUN_PD LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY2_1 LL_FLASH_EnableRunPowerDown\n - * FLASH_PDKEYR PDKEY2_2 LL_FLASH_EnableRunPowerDown\n - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableRunPowerDownBank2(void) -{ - /* Following values must be written consecutively to unlock the RUN_PD bit in - FLASH_ACR */ - WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_1); - WRITE_REG(FLASH->PDKEY2R, LL_FLASH_PDKEY2_2); - - /*Request to enter flash in power mode */ - SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2); -} - -/** - * @brief Enable Flash Power-down mode during Sleep or Low-power sleep mode - * @note Flash must not be put in power-down while a program or an erase operation - * is on-going - * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_EnableSleepPowerDown - * @retval None - */ -__STATIC_INLINE void LL_FLASH_EnableSleepPowerDown(void) -{ - SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); -} - -/** - * @brief Disable Flash Power-down mode during Sleep or Low-power sleep mode - * @rmtoll FLASH_ACR SLEEP_PD LL_FLASH_DisableSleepPowerDown - * @retval None - */ -__STATIC_INLINE void LL_FLASH_DisableSleepPowerDown(void) -{ - CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD); -} -/** - * @} - */ - - -/** @defgroup SYSTEM_LL_EF_ERASE_MEMORIE_STATUS ERASE MEMORIE STATUS - * @{ - */ - -/** - * @brief Clear Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_ClearEraseEndStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseEndStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE); -} - -/** - * @brief Get Status of End of Erase for ICACHE and PKA RAMs - * @rmtoll MESR IPMEE LL_SYSCFG_GetEraseEndStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseEndStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_IPMEE)); -} - - -/** - * @brief Clear Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_ClearEraseAfterResetStatus - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_ClearEraseAfterResetStatus(void) -{ - SET_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR); -} - -/** - * @brief Get Status of End of Erase after reset for SRAM2, BKPRAM, ICACHE, DCACHE,PKA rams - * @rmtoll MESR MCLR LL_SYSCFG_GetEraseAfterResetStatus - * @retval Returned value can be one of the following values: - * @arg LL_SYSCFG_MEMORIES_ERASE_ON_GOING : Erase of memories not yet done - * @arg LL_SYSCFG_MEMORIES_ERASE_ENDED: Erase of memories ended - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetEraseAfterResetStatus(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->MESR, SYSCFG_MESR_MCLR)); -} -/** - * @} - */ - -#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) || defined (VREFBUF) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32u5xx_LL_SYSTEM_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h deleted file mode 100644 index 5ff7ced25..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_ucpd.h +++ /dev/null @@ -1,1885 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_ucpd.h - * @author MCD Application Team - * @brief Header file of UCPD LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_UCPD_H -#define STM32U5xx_LL_UCPD_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (UCPD1) - -/** @defgroup UCPD_LL UCPD - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup UCPD_LL_ES_INIT UCPD Exported Init structure - * @{ - */ - -/** - * @brief UCPD Init structures definition - */ -typedef struct -{ - uint32_t psc_ucpdclk; /*!< Specify the prescaler for the UCPD clock. - This parameter can be a value of @ref UCPD_LL_EC_PSC. - This feature can be modified afterwards using function @ref LL_UCPD_SetPSCClk(). - */ - - uint32_t transwin; /*!< Specify the number of cycles (minus 1) of the half bit clock (see HBITCLKDIV) - to achieve a legal tTransitionWindow (set according to peripheral clock to define - an interval of between 12 and 20 us). - This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F - This value can be modified afterwards using function @ref LL_UCPD_SetTransWin(). - */ - - uint32_t IfrGap; /*!< Specify the definition of the clock divider (minus 1) in order to generate - tInterframeGap from the peripheral clock. - This parameter can be a value between Min_Data=0x1 and Max_Data=0x1F - This feature can be modified afterwards using function @ref LL_UCPD_SetIfrGap(). - */ - - uint32_t HbitClockDiv; /*!< Specify the number of cycles (minus one) at UCPD peripheral for a half bit clock - e.g. program 3 for a bit clock that takes 8 cycles of the peripheral clock : - "UCPD1_CLK". - This parameter can be a value between Min_Data=0x0 and Max_Data=0x3F. - This feature can be modified using function @ref LL_UCPD_SetHbitClockDiv(). - */ - -} LL_UCPD_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UCPD_LL_Exported_Constants UCPD Exported Constants - * @{ - */ - -/** @defgroup UCPD_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_ucpd_ReadReg function - * @{ - */ -#define LL_UCPD_SR_TXIS UCPD_SR_TXIS /*!< Transmit interrupt status */ -#define LL_UCPD_SR_TXMSGDISC UCPD_SR_TXMSGDISC /*!< Transmit message discarded interrupt */ -#define LL_UCPD_SR_TXMSGSENT UCPD_SR_TXMSGSENT /*!< Transmit message sent interrupt */ -#define LL_UCPD_SR_TXMSGABT UCPD_SR_TXMSGABT /*!< Transmit message abort interrupt */ -#define LL_UCPD_SR_HRSTDISC UCPD_SR_HRSTDISC /*!< HRST discarded interrupt */ -#define LL_UCPD_SR_HRSTSENT UCPD_SR_HRSTSENT /*!< HRST sent interrupt */ -#define LL_UCPD_SR_TXUND UCPD_SR_TXUND /*!< Tx data underrun condition interrupt */ -#define LL_UCPD_SR_RXNE UCPD_SR_RXNE /*!< Receive data register not empty interrupt */ -#define LL_UCPD_SR_RXORDDET UCPD_SR_RXORDDET /*!< Rx ordered set (4 K-codes) detected interrupt */ -#define LL_UCPD_SR_RXHRSTDET UCPD_SR_RXHRSTDET /*!< Rx Hard Reset detect interrupt */ -#define LL_UCPD_SR_RXOVR UCPD_SR_RXOVR /*!< Rx data overflow interrupt */ -#define LL_UCPD_SR_RXMSGEND UCPD_SR_RXMSGEND /*!< Rx message received */ -#define LL_UCPD_SR_RXERR UCPD_SR_RXERR /*!< Rx error */ -#define LL_UCPD_SR_TYPECEVT1 UCPD_SR_TYPECEVT1 /*!< Type C voltage level event on CC1 */ -#define LL_UCPD_SR_TYPECEVT2 UCPD_SR_TYPECEVT2 /*!< Type C voltage level event on CC2 */ -#define LL_UCPD_SR_TYPEC_VSTATE_CC1 UCPD_SR_TYPEC_VSTATE_CC1 /*!__REG__, (__VALUE__)) - -/** - * @brief Read a value in UCPD register - * @param __INSTANCE__ UCPD Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_UCPD_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UCPD_LL_Exported_Functions UCPD Exported Functions - * @{ - */ - -/** @defgroup UCPD_LL_EF_Configuration Configuration - * @{ - */ - -/** @defgroup UCPD_LL_EF_CFG1 CFG1 register - * @{ - */ -/** - * @brief Enable UCPD peripheral - * @rmtoll CFG1 UCPDEN LL_UCPD_Enable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_Enable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); -} - -/** - * @brief Disable UCPD peripheral - * @note When disabling the UCPD, follow the procedure described in the Reference Manual. - * @rmtoll CFG1 UCPDEN LL_UCPD_Disable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_Disable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN); -} - -/** - * @brief Check if UCPD peripheral is enabled - * @rmtoll CFG1 UCPDEN LL_UCPD_IsEnabled - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnabled(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_UCPDEN) == (UCPD_CFG1_UCPDEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the receiver ordered set detection enable - * @rmtoll CFG1 RXORDSETEN LL_UCPD_SetRxOrderSet - * @param UCPDx UCPD Instance - * @param OrderSet This parameter can be combination of the following values: - * @arg @ref LL_UCPD_ORDERSET_SOP - * @arg @ref LL_UCPD_ORDERSET_SOP1 - * @arg @ref LL_UCPD_ORDERSET_SOP2 - * @arg @ref LL_UCPD_ORDERSET_HARDRST - * @arg @ref LL_UCPD_ORDERSET_CABLERST - * @arg @ref LL_UCPD_ORDERSET_SOP1_DEBUG - * @arg @ref LL_UCPD_ORDERSET_SOP2_DEBUG - * @arg @ref LL_UCPD_ORDERSET_SOP_EXT1 - * @arg @ref LL_UCPD_ORDERSET_SOP_EXT2 - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetRxOrderSet(UCPD_TypeDef *UCPDx, uint32_t OrderSet) -{ - MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_RXORDSETEN, OrderSet); -} - -/** - * @brief Set the prescaler for ucpd clock - * @rmtoll CFG1 UCPDCLK LL_UCPD_SetPSCClk - * @param UCPDx UCPD Instance - * @param Psc This parameter can be one of the following values: - * @arg @ref LL_UCPD_PSC_DIV1 - * @arg @ref LL_UCPD_PSC_DIV2 - * @arg @ref LL_UCPD_PSC_DIV4 - * @arg @ref LL_UCPD_PSC_DIV8 - * @arg @ref LL_UCPD_PSC_DIV16 - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetPSCClk(UCPD_TypeDef *UCPDx, uint32_t Psc) -{ - MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_PSC_UCPDCLK, Psc); -} - -/** - * @brief Set the number of cycles (minus 1) of the half bit clock - * @rmtoll CFG1 TRANSWIN LL_UCPD_SetTransWin - * @param UCPDx UCPD Instance - * @param TransWin a value between Min_Data=0x1 and Max_Data=0x1F - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetTransWin(UCPD_TypeDef *UCPDx, uint32_t TransWin) -{ - MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_TRANSWIN, TransWin << UCPD_CFG1_TRANSWIN_Pos); -} - -/** - * @brief Set the clock divider value to generate an interframe gap - * @rmtoll CFG1 IFRGAP LL_UCPD_SetIfrGap - * @param UCPDx UCPD Instance - * @param IfrGap a value between Min_Data=0x1 and Max_Data=0x1F - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetIfrGap(UCPD_TypeDef *UCPDx, uint32_t IfrGap) -{ - MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_IFRGAP, IfrGap << UCPD_CFG1_IFRGAP_Pos); -} - -/** - * @brief Set the clock divider value to generate an interframe gap - * @rmtoll CFG1 HBITCLKDIV LL_UCPD_SetHbitClockDiv - * @param UCPDx UCPD Instance - * @param HbitClock a value between Min_Data=0x0 and Max_Data=0x3F - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetHbitClockDiv(UCPD_TypeDef *UCPDx, uint32_t HbitClock) -{ - MODIFY_REG(UCPDx->CFG1, UCPD_CFG1_HBITCLKDIV, HbitClock << UCPD_CFG1_HBITCLKDIV_Pos); -} - -/** - * @} - */ - -/** @defgroup UCPD_LL_EF_CFG2 CFG2 register - * @{ - */ - -/** - * @brief Enable Rx Analog Filter - * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxAnalogFilterEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); -} - -/** - * @brief Disable Rx Analog Filter - * @rmtoll CFG2 RXAFILTEN LL_UCPD_RxAnalogFilterDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxAnalogFilterDisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXAFILTEN); -} - -/** - * @brief Enable the wakeup mode - * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_WakeUpEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); -} - -/** - * @brief Disable the wakeup mode - * @rmtoll CFG2 WUPEN LL_UCPD_WakeUpDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_WakeUpDisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_WUPEN); -} - -/** - * @brief Force clock enable - * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ForceClockEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); -} - -/** - * @brief Force clock disable - * @rmtoll CFG2 FORCECLK LL_UCPD_ForceClockDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ForceClockDisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_FORCECLK); -} - -/** - * @brief RxFilter enable - * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxFilterEnable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); -} - -/** - * @brief RxFilter disable - * @rmtoll CFG2 RXFILTDIS LL_UCPD_RxFilterDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxFilterDisable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG2, UCPD_CFG2_RXFILTDIS); -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UCPD_LL_EF_CR CR register - * @{ - */ -/** - * @brief Type C detector for CC2 enable - * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Enable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Enable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); -} - -/** - * @brief Type C detector for CC2 disable - * @rmtoll CR CC2TCDIS LL_UCPD_TypeCDetectionCC2Disable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_TypeCDetectionCC2Disable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_CC2TCDIS); -} - -/** - * @brief Type C detector for CC1 enable - * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Enable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Enable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); -} - -/** - * @brief Type C detector for CC1 disable - * @rmtoll CR CC1TCDIS LL_UCPD_TypeCDetectionCC1Disable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_TypeCDetectionCC1Disable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_CC1TCDIS); -} - -/** - * @brief Source Vconn discharge enable - * @rmtoll CR RDCH LL_UCPD_VconnDischargeEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_VconnDischargeEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_RDCH); -} - -/** - * @brief Source Vconn discharge disable - * @rmtoll CR RDCH LL_UCPD_VconnDischargeDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_VconnDischargeDisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CR, UCPD_CR_RDCH); -} - -/** - * @brief Signal Fast Role Swap request - * @rmtoll CR FRSTX LL_UCPD_VconnDischargeDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SignalFRSTX(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_FRSTX); -} - -/** - * @brief Fast Role swap RX detection enable - * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_FRSDetectionEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); -} - -/** - * @brief Fast Role swap RX detection disable - * @rmtoll CR FRSRXEN LL_UCPD_FRSDetectionDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_FRSDetectionDisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CR, UCPD_CR_FRSRXEN); -} - -/** - * @brief Set cc enable - * @rmtoll CR CC1VCONNEN LL_UCPD_SetccEnable - * @param UCPDx UCPD Instance - * @param CCEnable This parameter can be one of the following values: - * @arg @ref LL_UCPD_CCENABLE_NONE - * @arg @ref LL_UCPD_CCENABLE_CC1 - * @arg @ref LL_UCPD_CCENABLE_CC2 - * @arg @ref LL_UCPD_CCENABLE_CC1CC2 - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetccEnable(UCPD_TypeDef *UCPDx, uint32_t CCEnable) -{ - MODIFY_REG(UCPDx->CR, UCPD_CR_CCENABLE, CCEnable); -} - -/** - * @brief Set UCPD SNK role - * @rmtoll CR ANAMODE LL_UCPD_SetSNKRole - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetSNKRole(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_ANAMODE); -} - -/** - * @brief Set UCPD SRC role - * @rmtoll CR ANAMODE LL_UCPD_SetSRCRole - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetSRCRole(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CR, UCPD_CR_ANAMODE); -} - -/** - * @brief Get UCPD Role - * @rmtoll CR ANAMODE LL_UCPD_GetRole - * @param UCPDx UCPD Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_UCPD_ROLE_SNK - * @arg @ref LL_UCPD_ROLE_SRC - */ -__STATIC_INLINE uint32_t LL_UCPD_GetRole(UCPD_TypeDef const *const UCPDx) -{ - return (uint32_t)(READ_BIT(UCPDx->CR, UCPD_CR_ANAMODE)); -} - -/** - * @brief Set Rp resistor - * @rmtoll CR ANASUBMODE LL_UCPD_SetRpResistor - * @param UCPDx UCPD Instance - * @param Resistor This parameter can be one of the following values: - * @arg @ref LL_UCPD_RESISTOR_DEFAULT - * @arg @ref LL_UCPD_RESISTOR_1_5A - * @arg @ref LL_UCPD_RESISTOR_3_0A - * @arg @ref LL_UCPD_RESISTOR_NONE - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetRpResistor(UCPD_TypeDef *UCPDx, uint32_t Resistor) -{ - MODIFY_REG(UCPDx->CR, UCPD_CR_ANASUBMODE, Resistor); -} - -/** - * @brief Set CC pin - * @rmtoll CR PHYCCSEL LL_UCPD_SetCCPin - * @param UCPDx UCPD Instance - * @param CCPin This parameter can be one of the following values: - * @arg @ref LL_UCPD_CCPIN_CC1 - * @arg @ref LL_UCPD_CCPIN_CC2 - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetCCPin(UCPD_TypeDef *UCPDx, uint32_t CCPin) -{ - MODIFY_REG(UCPDx->CR, UCPD_CR_PHYCCSEL, CCPin); -} - -/** - * @brief Rx enable - * @rmtoll CR PHYRXEN LL_UCPD_RxEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_PHYRXEN); -} - -/** - * @brief Rx disable - * @rmtoll CR PHYRXEN LL_UCPD_RxDisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxDisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CR, UCPD_CR_PHYRXEN); -} - -/** - * @brief Set Rx mode - * @rmtoll CR RXMODE LL_UCPD_SetRxMode - * @param UCPDx UCPD Instance - * @param RxMode This parameter can be one of the following values: - * @arg @ref LL_UCPD_RXMODE_NORMAL - * @arg @ref LL_UCPD_RXMODE_BIST_TEST_DATA - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetRxMode(UCPD_TypeDef *UCPDx, uint32_t RxMode) -{ - MODIFY_REG(UCPDx->CR, UCPD_CR_RXMODE, RxMode); -} - -/** - * @brief Send Hard Reset - * @rmtoll CR TXHRST LL_UCPD_SendHardReset - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SendHardReset(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_TXHRST); -} - -/** - * @brief Send message - * @rmtoll CR TXSEND LL_UCPD_SendMessage - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SendMessage(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CR, UCPD_CR_TXSEND); -} - -/** - * @brief Set Tx mode - * @rmtoll CR TXMODE LL_UCPD_SetTxMode - * @param UCPDx UCPD Instance - * @param TxMode This parameter can be one of the following values: - * @arg @ref LL_UCPD_TXMODE_NORMAL - * @arg @ref LL_UCPD_TXMODE_CABLE_RESET - * @arg @ref LL_UCPD_TXMODE_BIST_CARRIER2 - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetTxMode(UCPD_TypeDef *UCPDx, uint32_t TxMode) -{ - MODIFY_REG(UCPDx->CR, UCPD_CR_TXMODE, TxMode); -} - -/** - * @} - */ - -/** @defgroup UCPD_LL_EF_IT_Management Interrupt Management - * @{ - */ - -/** - * @brief Enable FRS interrupt - * @rmtoll IMR FRSEVTIE LL_UCPD_EnableIT_FRS - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_FRS(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE); -} - -/** - * @brief Enable type c event on CC2 - * @rmtoll IMR TYPECEVT2IE LL_UCPD_EnableIT_TypeCEventCC2 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE); -} - -/** - * @brief Enable type c event on CC1 - * @rmtoll IMR TYPECEVT1IE LL_UCPD_EnableIT_TypeCEventCC1 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE); -} - -/** - * @brief Enable Rx message end interrupt - * @rmtoll IMR RXMSGENDIE LL_UCPD_EnableIT_RxMsgEnd - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_RxMsgEnd(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE); -} - -/** - * @brief Enable Rx overrun interrupt - * @rmtoll IMR RXOVRIE LL_UCPD_EnableIT_RxOvr - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE); -} - -/** - * @brief Enable Rx hard resrt interrupt - * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_RxHRST(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE); -} - -/** - * @brief Enable Rx orderset interrupt - * @rmtoll IMR RXORDDETIE LL_UCPD_EnableIT_RxOrderSet - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_RxOrderSet(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE); -} - -/** - * @brief Enable Rx non empty interrupt - * @rmtoll IMR RXNEIE LL_UCPD_EnableIT_RxNE - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_RxNE(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE); -} - -/** - * @brief Enable TX underrun interrupt - * @rmtoll IMR TXUNDIE LL_UCPD_EnableIT_TxUND - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxUND(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE); -} - -/** - * @brief Enable hard reset sent interrupt - * @rmtoll IMR HRSTSENTIE LL_UCPD_EnableIT_TxHRSTSENT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE); -} - -/** - * @brief Enable hard reset discard interrupt - * @rmtoll IMR HRSTDISCIE LL_UCPD_EnableIT_TxHRSTDISC - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE); -} - -/** - * @brief Enable Tx message abort interrupt - * @rmtoll IMR TXMSGABTIE LL_UCPD_EnableIT_TxMSGABT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGABT(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE); -} - -/** - * @brief Enable Tx message sent interrupt - * @rmtoll IMR TXMSGSENTIE LL_UCPD_EnableIT_TxMSGSENT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGSENT(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE); -} - -/** - * @brief Enable Tx message discarded interrupt - * @rmtoll IMR TXMSGDISCIE LL_UCPD_EnableIT_TxMSGDISC - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxMSGDISC(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE); -} - -/** - * @brief Enable Tx data receive interrupt - * @rmtoll IMR TXISIE LL_UCPD_EnableIT_TxIS - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_EnableIT_TxIS(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->IMR, UCPD_IMR_TXISIE); -} - -/** - * @brief Disable FRS interrupt - * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_FRS(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE); -} - -/** - * @brief Disable type c event on CC2 - * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC2(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE); -} - -/** - * @brief Disable type c event on CC1 - * @rmtoll IMR TYPECEVT1IE LL_UCPD_DisableIT_TypeCEventCC1 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TypeCEventCC1(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE); -} - -/** - * @brief Disable Rx message end interrupt - * @rmtoll IMR RXMSGENDIE LL_UCPD_DisableIT_RxMsgEnd - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_RxMsgEnd(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE); -} - -/** - * @brief Disable Rx overrun interrupt - * @rmtoll IMR RXOVRIE LL_UCPD_DisableIT_RxOvr - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE); -} - -/** - * @brief Disable Rx hard resrt interrupt - * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_RxHRST(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE); -} - -/** - * @brief Disable Rx orderset interrupt - * @rmtoll IMR RXORDDETIE LL_UCPD_DisableIT_RxOrderSet - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_RxOrderSet(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE); -} - -/** - * @brief Disable Rx non empty interrupt - * @rmtoll IMR RXNEIE LL_UCPD_DisableIT_RxNE - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_RxNE(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE); -} - -/** - * @brief Disable TX underrun interrupt - * @rmtoll IMR TXUNDIE LL_UCPD_DisableIT_TxUND - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxUND(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE); -} - -/** - * @brief Disable hard reset sent interrupt - * @rmtoll IMR HRSTSENTIE LL_UCPD_DisableIT_TxHRSTSENT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTSENT(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE); -} - -/** - * @brief Disable hard reset discard interrupt - * @rmtoll IMR HRSTDISCIE LL_UCPD_DisableIT_TxHRSTDISC - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxHRSTDISC(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE); -} - -/** - * @brief Disable Tx message abort interrupt - * @rmtoll IMR TXMSGABTIE LL_UCPD_DisableIT_TxMSGABT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGABT(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE); -} - -/** - * @brief Disable Tx message sent interrupt - * @rmtoll IMR TXMSGSENTIE LL_UCPD_DisableIT_TxMSGSENT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGSENT(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE); -} - -/** - * @brief Disable Tx message discarded interrupt - * @rmtoll IMR TXMSGDISCIE LL_UCPD_DisableIT_TxMSGDISC - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxMSGDISC(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE); -} - -/** - * @brief Disable Tx data receive interrupt - * @rmtoll IMR TXISIE LL_UCPD_DisableIT_TxIS - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_DisableIT_TxIS(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->IMR, UCPD_IMR_TXISIE); -} - -/** - * @brief Check if FRS interrupt enabled - * @rmtoll IMR FRSEVTIE LL_UCPD_DisableIT_FRS - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_FRS(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_FRSEVTIE) == UCPD_IMR_FRSEVTIE) ? 1UL : 0UL); -} - -/** - * @brief Check if type c event on CC2 enabled - * @rmtoll IMR TYPECEVT2IE LL_UCPD_DisableIT_TypeCEventCC2 - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT2IE) == UCPD_IMR_TYPECEVT2IE) ? 1UL : 0UL); -} - -/** - * @brief Check if type c event on CC1 enabled - * @rmtoll IMR2 TYPECEVT1IE LL_UCPD_IsEnableIT_TypeCEventCC1 - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TYPECEVT1IE) == UCPD_IMR_TYPECEVT1IE) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx message end interrupt enabled - * @rmtoll IMR RXMSGENDIE LL_UCPD_IsEnableIT_RxMsgEnd - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxMsgEnd(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXMSGENDIE) == UCPD_IMR_RXMSGENDIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx overrun interrupt enabled - * @rmtoll IMR RXOVRIE LL_UCPD_IsEnableIT_RxOvr - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXOVRIE) == UCPD_IMR_RXOVRIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx hard resrt interrupt enabled - * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxHRST(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXHRSTDETIE) == UCPD_IMR_RXHRSTDETIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx orderset interrupt enabled - * @rmtoll IMR RXORDDETIE LL_UCPD_IsEnableIT_RxOrderSet - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOrderSet(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXORDDETIE) == UCPD_IMR_RXORDDETIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx non empty interrupt enabled - * @rmtoll IMR RXNEIE LL_UCPD_IsEnableIT_RxNE - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxNE(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_RXNEIE) == UCPD_IMR_RXNEIE) ? 1UL : 0UL); -} - -/** - * @brief Check if TX underrun interrupt enabled - * @rmtoll IMR TXUNDIE LL_UCPD_IsEnableIT_TxUND - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxUND(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXUNDIE) == UCPD_IMR_TXUNDIE) ? 1UL : 0UL); -} - -/** - * @brief Check if hard reset sent interrupt enabled - * @rmtoll IMR HRSTSENTIE LL_UCPD_IsEnableIT_TxHRSTSENT - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTSENTIE) == UCPD_IMR_HRSTSENTIE) ? 1UL : 0UL); -} - -/** - * @brief Check if hard reset discard interrupt enabled - * @rmtoll IMR HRSTDISCIE LL_UCPD_IsEnableIT_TxHRSTDISC - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_HRSTDISCIE) == UCPD_IMR_HRSTDISCIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx message abort interrupt enabled - * @rmtoll IMR TXMSGABTIE LL_UCPD_IsEnableIT_TxMSGABT - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGABT(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGABTIE) == UCPD_IMR_TXMSGABTIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx message sent interrupt enabled - * @rmtoll IMR TXMSGSENTIE LL_UCPD_IsEnableIT_TxMSGSENT - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGSENT(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGSENTIE) == UCPD_IMR_TXMSGSENTIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx message discarded interrupt enabled - * @rmtoll IMR TXMSGDISCIE LL_UCPD_IsEnableIT_TxMSGDISC - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxMSGDISC(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXMSGDISCIE) == UCPD_IMR_TXMSGDISCIE) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx data receive interrupt enabled - * @rmtoll IMR TXISIE LL_UCPD_IsEnableIT_TxIS - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_TxIS(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->IMR, UCPD_IMR_TXISIE) == UCPD_IMR_TXISIE) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup UCPD_LL_EF_IT_Clear Interrupt Clear - * @{ - */ - -/** - * @brief Clear FRS interrupt - * @rmtoll ICR FRSEVTIE LL_UCPD_ClearFlag_FRS - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_FRS(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_FRSEVTCF); -} - -/** - * @brief Clear type c event on CC2 - * @rmtoll IIMR TYPECEVT2IE LL_UCPD_ClearFlag_TypeCEventCC2 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC2(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT2CF); -} - -/** - * @brief Clear type c event on CC1 - * @rmtoll IIMR TYPECEVT1IE LL_UCPD_ClearFlag_TypeCEventCC1 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TypeCEventCC1(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_TYPECEVT1CF); -} - -/** - * @brief Clear Rx message end interrupt - * @rmtoll ICR RXMSGENDIE LL_UCPD_ClearFlag_RxMsgEnd - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_RxMsgEnd(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_RXMSGENDCF); -} - -/** - * @brief Clear Rx overrun interrupt - * @rmtoll ICR RXOVRIE LL_UCPD_ClearFlag_RxOvr - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_RXOVRCF); -} - -/** - * @brief Clear Rx hard resrt interrupt - * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_RxHRST(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_RXHRSTDETCF); -} - -/** - * @brief Clear Rx orderset interrupt - * @rmtoll ICR RXORDDETIE LL_UCPD_ClearFlag_RxOrderSet - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_RxOrderSet(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_RXORDDETCF); -} - -/** - * @brief Clear TX underrun interrupt - * @rmtoll ICR TXUNDIE LL_UCPD_ClearFlag_TxUND - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TxUND(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_TXUNDCF); -} - -/** - * @brief Clear hard reset sent interrupt - * @rmtoll ICR HRSTSENTIE LL_UCPD_ClearFlag_TxHRSTSENT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTSENT(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTSENTCF); -} - -/** - * @brief Clear hard reset discard interrupt - * @rmtoll ICR HRSTDISCIE LL_UCPD_ClearFlag_TxHRSTDISC - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TxHRSTDISC(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_HRSTDISCCF); -} - -/** - * @brief Clear Tx message abort interrupt - * @rmtoll ICR TXMSGABTIE LL_UCPD_ClearFlag_TxMSGABT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGABT(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGABTCF); -} - -/** - * @brief Clear Tx message sent interrupt - * @rmtoll ICR TXMSGSENTIE LL_UCPD_ClearFlag_TxMSGSENT - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGSENT(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGSENTCF); -} - -/** - * @brief Clear Tx message discarded interrupt - * @rmtoll ICR TXMSGDISCIE LL_UCPD_ClearFlag_TxMSGDISC - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->ICR, UCPD_ICR_TXMSGDISCCF); -} - -/** - * @} - */ - -/** @defgroup UCPD_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Check if FRS interrupt - * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_FRSEVT) == UCPD_SR_FRSEVT) ? 1UL : 0UL); -} - -/** - * @brief Check if type c event on CC2 - * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT2) == UCPD_SR_TYPECEVT2) ? 1UL : 0UL); -} - -/** - * @brief Check if type c event on CC1 - * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TYPECEVT1) == UCPD_SR_TYPECEVT1) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx message end interrupt - * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_RXMSGEND) == UCPD_SR_RXMSGEND) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx overrun interrupt - * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_RXOVR) == UCPD_SR_RXOVR) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx hard resrt interrupt - * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_RXHRSTDET) == UCPD_SR_RXHRSTDET) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx orderset interrupt - * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_RXORDDET) == UCPD_SR_RXORDDET) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx non empty interrupt - * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_RXNE) == UCPD_SR_RXNE) ? 1UL : 0UL); -} - -/** - * @brief Check if TX underrun interrupt - * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TXUND) == UCPD_SR_TXUND) ? 1UL : 0UL); -} - -/** - * @brief Check if hard reset sent interrupt - * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTSENT) == UCPD_SR_HRSTSENT) ? 1UL : 0UL); -} - -/** - * @brief Check if hard reset discard interrupt - * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_HRSTDISC) == UCPD_SR_HRSTDISC) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx message abort interrupt - * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGABT) == UCPD_SR_TXMSGABT) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx message sent interrupt - * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGSENT) == UCPD_SR_TXMSGSENT) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx message discarded interrupt - * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TXMSGDISC) == UCPD_SR_TXMSGDISC) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx data receive interrupt - * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxIS(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->SR, UCPD_SR_TXIS) == UCPD_SR_TXIS) ? 1UL : 0UL); -} - -/** - * @brief return the vstate value for CC2 - * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC2 - * @param UCPDx UCPD Instance - * @retval val - */ -__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC2(UCPD_TypeDef const *const UCPDx) -{ - return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC2; -} - -/** - * @brief return the vstate value for CC1 - * @rmtoll SR TXIS LL_UCPD_GetTypeCVstateCC1 - * @param UCPDx UCPD Instance - * @retval val - */ -__STATIC_INLINE uint32_t LL_UCPD_GetTypeCVstateCC1(UCPD_TypeDef const *const UCPDx) -{ - return UCPDx->SR & UCPD_SR_TYPEC_VSTATE_CC1; -} - -/** - * @} - */ - - -/** @defgroup UCPD_LL_EF_DMA_Management DMA Management - * @{ - */ - -/** - * @brief Rx DMA Enable - * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMAEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxDMAEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); -} - -/** - * @brief Rx DMA Disable - * @rmtoll CFG1 RXDMAEN LL_UCPD_RxDMADisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_RxDMADisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN); -} - -/** - * @brief Tx DMA Enable - * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMAEnable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_TxDMAEnable(UCPD_TypeDef *UCPDx) -{ - SET_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN); -} - -/** - * @brief Tx DMA Disable - * @rmtoll CFG1 TXDMAEN LL_UCPD_TxDMADisable - * @param UCPDx UCPD Instance - * @retval None - */ -__STATIC_INLINE void LL_UCPD_TxDMADisable(UCPD_TypeDef *UCPDx) -{ - CLEAR_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN); -} - -/** - * @brief Check if DMA Tx is enabled - * @rmtoll CR2 TXDMAEN LL_UCPD_IsEnabledTxDMA - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnabledTxDMA(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_TXDMAEN) == (UCPD_CFG1_TXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Check if DMA Rx is enabled - * @rmtoll CR2 RXDMAEN LL_UCPD_IsEnabledRxDMA - * @param UCPDx UCPD Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_UCPD_IsEnabledRxDMA(UCPD_TypeDef const *const UCPDx) -{ - return ((READ_BIT(UCPDx->CFG1, UCPD_CFG1_RXDMAEN) == (UCPD_CFG1_RXDMAEN)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup UCPD_LL_EF_DATA_Management DATA Management - * @{ - */ - -/** - * @brief write the orderset for Tx message - * @rmtoll TX_ORDSET TXORDSET LL_UCPD_WriteTxOrderSet - * @param UCPDx UCPD Instance - * @param TxOrderSet one of the following value - * @arg @ref LL_UCPD_ORDERED_SET_SOP - * @arg @ref LL_UCPD_ORDERED_SET_SOP1 - * @arg @ref LL_UCPD_ORDERED_SET_SOP2 - * @arg @ref LL_UCPD_ORDERED_SET_HARD_RESET - * @arg @ref LL_UCPD_ORDERED_SET_CABLE_RESET - * @arg @ref LL_UCPD_ORDERED_SET_SOP1_DEBUG - * @arg @ref LL_UCPD_ORDERED_SET_SOP2_DEBUG - * @retval None - */ -__STATIC_INLINE void LL_UCPD_WriteTxOrderSet(UCPD_TypeDef *UCPDx, uint32_t TxOrderSet) -{ - WRITE_REG(UCPDx->TX_ORDSET, TxOrderSet); -} - -/** - * @brief write the Tx paysize - * @rmtoll TX_PAYSZ TXPAYSZ LL_UCPD_WriteTxPaySize - * @param UCPDx UCPD Instance - * @param TxPaySize - * @retval None. - */ -__STATIC_INLINE void LL_UCPD_WriteTxPaySize(UCPD_TypeDef *UCPDx, uint32_t TxPaySize) -{ - WRITE_REG(UCPDx->TX_PAYSZ, TxPaySize); -} - -/** - * @brief Write data - * @rmtoll TXDR DR LL_UCPD_WriteData - * @param UCPDx UCPD Instance - * @param Data Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None. - */ -__STATIC_INLINE void LL_UCPD_WriteData(UCPD_TypeDef *UCPDx, uint8_t Data) -{ - WRITE_REG(UCPDx->TXDR, Data); -} - -/** - * @brief read RX the orderset - * @rmtoll RX_ORDSET RXORDSET LL_UCPD_ReadRxOrderSet - * @param UCPDx UCPD Instance - * @retval RxOrderSet one of the following value - * @arg @ref LL_UCPD_RXORDSET_SOP - * @arg @ref LL_UCPD_RXORDSET_SOP1 - * @arg @ref LL_UCPD_RXORDSET_SOP2 - * @arg @ref LL_UCPD_RXORDSET_SOP1_DEBUG - * @arg @ref LL_UCPD_RXORDSET_SOP2_DEBUG - * @arg @ref LL_UCPD_RXORDSET_CABLE_RESET - * @arg @ref LL_UCPD_RXORDSET_SOPEXT1 - * @arg @ref LL_UCPD_RXORDSET_SOPEXT2 - */ -__STATIC_INLINE uint32_t LL_UCPD_ReadRxOrderSet(UCPD_TypeDef const *const UCPDx) -{ - return READ_BIT(UCPDx->RX_ORDSET, UCPD_RX_ORDSET_RXORDSET); -} - -/** - * @brief Read the Rx paysize - * @rmtoll RX_PAYSZ RXPAYSZ LL_UCPD_ReadRxPaySize - * @param UCPDx UCPD Instance - * @retval RXPaysize. - */ -__STATIC_INLINE uint32_t LL_UCPD_ReadRxPaySize(UCPD_TypeDef const *const UCPDx) -{ - return READ_BIT(UCPDx->RX_PAYSZ, UCPD_RX_PAYSZ_RXPAYSZ); -} - -/** - * @brief Read data - * @rmtoll TXDR RXDATA LL_UCPD_ReadData - * @param UCPDx UCPD Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_UCPD_ReadData(UCPD_TypeDef const *const UCPDx) -{ - return READ_REG(UCPDx->RXDR); -} - -/** - * @brief Set Rx OrderSet Ext1 - * @rmtoll RX_ORDEXT1 RXSOPX1 LL_UCPD_SetRxOrdExt1 - * @param UCPDx UCPD Instance - * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetRxOrdExt1(UCPD_TypeDef *UCPDx, uint32_t SOPExt) -{ - WRITE_REG(UCPDx->RX_ORDEXT1, SOPExt); -} - -/** - * @brief Set Rx OrderSet Ext2 - * @rmtoll RX_ORDEXT2 RXSOPX2 LL_UCPD_SetRxOrdExt2 - * @param UCPDx UCPD Instance - * @param SOPExt Value between Min_Data=0x00000 and Max_Data=0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_UCPD_SetRxOrdExt2(UCPD_TypeDef *UCPDx, uint32_t SOPExt) -{ - WRITE_REG(UCPDx->RX_ORDEXT2, SOPExt); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup UCPD_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx); -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct); -void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -#endif /* defined (UCPD1) */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_UCPD_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h deleted file mode 100644 index 90aa03bc1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usart.h +++ /dev/null @@ -1,4488 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_usart.h - * @author MCD Application Team - * @brief Header file of USART LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_USART_H -#define STM32U5xx_LL_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined(USART1) || defined(USART2) || defined(USART3) || defined(UART4) || defined(UART5) - -/** @defgroup USART_LL USART - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Variables USART Private Variables - * @{ - */ -/* Array used to get the USART prescaler division decimal values versus @ref USART_LL_EC_PRESCALER values */ -static const uint32_t USART_PRESCALER_TAB[] = -{ - 1UL, - 2UL, - 4UL, - 6UL, - 8UL, - 10UL, - 12UL, - 16UL, - 32UL, - 64UL, - 128UL, - 256UL -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_Private_Macros USART Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_ES_INIT USART Exported Init structures - * @{ - */ - -/** - * @brief LL USART Init Structure definition - */ -typedef struct -{ - uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. - This parameter can be a value of @ref USART_LL_EC_PRESCALER. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetPrescaler().*/ - - uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetBaudRate().*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetDataWidth().*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_LL_EC_STOPBITS. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetStopBitsLength().*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_LL_EC_PARITY. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetParity().*/ - - uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_DIRECTION. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetTransferDirection().*/ - - uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetHWFlowCtrl().*/ - - uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. - This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - - This feature can be modified afterwards using unitary - function @ref LL_USART_SetOverSampling().*/ - -} LL_USART_InitTypeDef; - -/** - * @brief LL USART Clock Init Structure definition - */ -typedef struct -{ - uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_CLOCK. - - USART HW configuration can be modified afterwards using unitary functions - @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). - For more details, refer to description of this function. */ - - uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_LL_EC_POLARITY. - - USART HW configuration can be modified afterwards using unitary - functions @ref LL_USART_SetClockPolarity(). - For more details, refer to description of this function. */ - - uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_LL_EC_PHASE. - - USART HW configuration can be modified afterwards using unitary - functions @ref LL_USART_SetClockPhase(). - For more details, refer to description of this function. */ - - uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - - USART HW configuration can be modified afterwards using unitary - functions @ref LL_USART_SetLastClkPulseOutput(). - For more details, refer to description of this function. */ - -} LL_USART_ClockInitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Constants USART Exported Constants - * @{ - */ - -/** @defgroup USART_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_USART_WriteReg function - * @{ - */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ -#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ -#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ -#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_USART_ReadReg function - * @{ - */ -#define LL_USART_ISR_PE USART_ISR_PE /*!< Parity error flag */ -#define LL_USART_ISR_FE USART_ISR_FE /*!< Framing error flag */ -#define LL_USART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ -#define LL_USART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ -#define LL_USART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ -#define LL_USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ -#define LL_USART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ -#define LL_USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ -#define LL_USART_ISR_LBDF USART_ISR_LBDF /*!< LIN break detection flag */ -#define LL_USART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ -#define LL_USART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ -#define LL_USART_ISR_RTOF USART_ISR_RTOF /*!< Receiver timeout flag */ -#define LL_USART_ISR_EOBF USART_ISR_EOBF /*!< End of block flag */ -#define LL_USART_ISR_UDR USART_ISR_UDR /*!< SPI Slave underrun error flag */ -#define LL_USART_ISR_ABRE USART_ISR_ABRE /*!< Auto baud rate error flag */ -#define LL_USART_ISR_ABRF USART_ISR_ABRF /*!< Auto baud rate flag */ -#define LL_USART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ -#define LL_USART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ -#define LL_USART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ -#define LL_USART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ -#define LL_USART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ -#define LL_USART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ -#define LL_USART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ -#define LL_USART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ -#define LL_USART_ISR_TCBGT USART_ISR_TCBGT /*!< Transmission complete before guard time completion flag */ -#define LL_USART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ -#define LL_USART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions - * @{ - */ -#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ -#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ -#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_USART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ -#define LL_USART_CR1_RTOIE USART_CR1_RTOIE /*!< Receiver timeout interrupt enable */ -#define LL_USART_CR1_EOBIE USART_CR1_EOBIE /*!< End of Block interrupt enable */ -#define LL_USART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ -#define LL_USART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ -#define LL_USART_CR2_LBDIE USART_CR2_LBDIE /*!< LIN break detection interrupt enable */ -#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -#define LL_USART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ -#define LL_USART_CR3_TCBGTIE USART_CR3_TCBGTIE /*!< Transmission complete before guard time interrupt enable */ -#define LL_USART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_FIFOTHRESHOLD FIFO Threshold - * @{ - */ -#define LL_USART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ -#define LL_USART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ -#define LL_USART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ -#define LL_USART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ -#define LL_USART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ -#define LL_USART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DIRECTION Communication Direction - * @{ - */ -#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PARITY Parity Control - * @{ - */ -#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_WAKEUP Wakeup - * @{ - */ -#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ -#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_USART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling - * @{ - */ -#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define LL_USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EC_CLOCK Clock Signal - * @{ - */ - -#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ -#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse - * @{ - */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ -#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ -#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ -#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PRESCALER Clock Source Prescaler - * @{ - */ -#define LL_USART_PRESCALER_DIV1 0x00000000U /*!< Input clock not divided */ -#define LL_USART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock divided by 2 */ -#define LL_USART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock divided by 4 */ -#define LL_USART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 6 */ -#define LL_USART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock divided by 8 */ -#define LL_USART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 10 */ -#define LL_USART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 12 */ -#define LL_USART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 16 */ -#define LL_USART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock divided by 32 */ -#define LL_USART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 64 */ -#define LL_USART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock divided by 128 */ -#define LL_USART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock divided by 256 */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_STOPBITS Stop Bits - * @{ - */ -#define LL_USART_STOPBITS_0_5 USART_CR2_STOP_0 /*!< 0.5 stop bit */ -#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_USART_STOPBITS_1_5 (USART_CR2_STOP_0 | USART_CR2_STOP_1) /*!< 1.5 stop bits */ -#define LL_USART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_TXRX TX RX Pins Swap - * @{ - */ -#define LL_USART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ -#define LL_USART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion - * @{ - */ -#define LL_USART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ -#define LL_USART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion - * @{ - */ -#define LL_USART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ -#define LL_USART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_BINARY_LOGIC Binary Data Inversion - * @{ - */ -#define LL_USART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ -#define LL_USART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_BITORDER Bit Order - * @{ - */ -#define LL_USART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ -#define LL_USART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_AUTOBAUD_DETECT_ON Autobaud Detection - * @{ - */ -#define LL_USART_AUTOBAUD_DETECT_ON_STARTBIT 0x00000000U /*!< Measurement of the start bit is used to detect the baud rate */ -#define LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE USART_CR2_ABRMODE_0 /*!< Falling edge to falling edge measurement. Received frame must start with a single bit = 1 -> Frame = Start10xxxxxx */ -#define LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME USART_CR2_ABRMODE_1 /*!< 0x7F frame detection */ -#define LL_USART_AUTOBAUD_DETECT_ON_55_FRAME (USART_CR2_ABRMODE_1 | USART_CR2_ABRMODE_0) /*!< 0x55 frame detection */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_ADDRESS_DETECT Address Length Detection - * @{ - */ -#define LL_USART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ -#define LL_USART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_HWCONTROL Hardware Control - * @{ - */ -#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_IRDA_POWER IrDA Power - * @{ - */ -#define LL_USART_IRDA_POWER_NORMAL 0x00000000U /*!< IrDA normal power mode */ -#define LL_USART_IRDA_POWER_LOW USART_CR3_IRLP /*!< IrDA low power mode */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_LINBREAK_DETECT LIN Break Detection Length - * @{ - */ -#define LL_USART_LINBREAK_DETECT_10B 0x00000000U /*!< 10-bit break detection method selected */ -#define LL_USART_LINBREAK_DETECT_11B USART_CR2_LBDL /*!< 11-bit break detection method selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DE_POLARITY Driver Enable Polarity - * @{ - */ -#define LL_USART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ -#define LL_USART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DMA_REG_DATA DMA Register Data - * @{ - */ -#define LL_USART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ -#define LL_USART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_AUTOCR_TRIGSEL Autonomous Trigger Selection - * @brief USART Autonomous Trigger selection - * @{ - */ -#define LL_USART_GPDMA1_CH0_TCF_TRG 0U /*!< USART GPDMA1 channel0 Internal Trigger */ -#define LL_USART_GPDMA1_CH1_TCF_TRG 1U /*!< USART GPDMA1 channel1 Internal Trigger */ -#define LL_USART_GPDMA1_CH2_TCF_TRG 2U /*!< USART GPDMA1 channel2 Internal Trigger */ -#define LL_USART_GPDMA1_CH3_TCF_TRG 3U /*!< USART GPDMA1 channel3 Internal Trigger */ -#define LL_USART_EXTI_LINE6_TRG 4U /*!< USART EXTI line 6 Internal Trigger */ -#define LL_USART_EXTI_LINE9_TRG 5U /*!< USART EXTI line 9 Internal Trigger */ -#define LL_USART_LPTIM1_OUT_TRG 6U /*!< USART LPTIM1 out Internal Trigger */ -#define LL_USART_LPTIM2_OUT_TRG 7U /*!< USART LPTIM2 out Internal Trigger */ -#define LL_USART_COMP1_OUT_TRG 8U /*!< USART COMP1 out Internal Trigger */ -#define LL_USART_COMP2_OUT_TRG 9U /*!< USART COMP2 out Internal Trigger */ -#define LL_USART_RTC_ALRA_TRG 10U /*!< USART RTC alarm Internal Trigger */ -#define LL_USART_RTC_WUT_TRG 11U /*!< USART RTC wakeup Internal Trigger */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_AUTOCR_TRIGPOL Autonomous Trigger Polarity - * @brief USART Autonomous Trigger Polarity - * @{ - */ -#define LL_USART_TRIG_POLARITY_RISING 0x00000000U /*!< USART triggered on rising edge */ -#define LL_USART_TRIG_POLARITY_FALLING USART_AUTOCR_TRIGPOL /*!< USART triggered on falling edge */ -/** - * @} - */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Macros USART Exported Macros - * @{ - */ - -/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper - * @{ - */ - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_USART_PRESCALER_DIV1 - * @arg @ref LL_USART_PRESCALER_DIV2 - * @arg @ref LL_USART_PRESCALER_DIV4 - * @arg @ref LL_USART_PRESCALER_DIV6 - * @arg @ref LL_USART_PRESCALER_DIV8 - * @arg @ref LL_USART_PRESCALER_DIV10 - * @arg @ref LL_USART_PRESCALER_DIV12 - * @arg @ref LL_USART_PRESCALER_DIV16 - * @arg @ref LL_USART_PRESCALER_DIV32 - * @arg @ref LL_USART_PRESCALER_DIV64 - * @arg @ref LL_USART_PRESCALER_DIV128 - * @arg @ref LL_USART_PRESCALER_DIV256 - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case - */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ - (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_USART_PRESCALER_DIV1 - * @arg @ref LL_USART_PRESCALER_DIV2 - * @arg @ref LL_USART_PRESCALER_DIV4 - * @arg @ref LL_USART_PRESCALER_DIV6 - * @arg @ref LL_USART_PRESCALER_DIV8 - * @arg @ref LL_USART_PRESCALER_DIV10 - * @arg @ref LL_USART_PRESCALER_DIV12 - * @arg @ref LL_USART_PRESCALER_DIV16 - * @arg @ref LL_USART_PRESCALER_DIV32 - * @arg @ref LL_USART_PRESCALER_DIV64 - * @arg @ref LL_USART_PRESCALER_DIV128 - * @arg @ref LL_USART_PRESCALER_DIV256 - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case - */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ - ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_LL_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_LL_EF_Configuration Configuration functions - * @{ - */ - -/** - * @brief USART Enable - * @rmtoll CR1 UE LL_USART_Enable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief USART Disable (all USART prescalers and outputs are disabled) - * @note When USART is disabled, USART prescalers and outputs are stopped immediately, - * and current operations are discarded. The configuration of the USART is kept, but all the status - * flags, in the USARTx_ISR are set to their default values. - * @rmtoll CR1 UE LL_USART_Disable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief Indicate if USART is enabled - * @rmtoll CR1 UE LL_USART_IsEnabled - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)) ? 1UL : 0UL); -} - -/** - * @brief FIFO Mode Enable - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_FIFOEN); -} - -/** - * @brief FIFO Mode Disable - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_FIFOEN); -} - -/** - * @brief Indicate if FIFO Mode is enabled - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)) ? 1UL : 0UL); -} - -/** - * @brief Configure TX FIFO Threshold - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold - * @param USARTx USART Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) -{ - ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); -} - -/** - * @brief Return TX FIFO Threshold Configuration - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); -} - -/** - * @brief Configure RX FIFO Threshold - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold - * @param USARTx USART Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t Threshold) -{ - ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); -} - -/** - * @brief Return RX FIFO Threshold Configuration - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); -} - -/** - * @brief Configure TX and RX FIFOs Threshold - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n - * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold - * @param USARTx USART Instance - * @param TXThreshold This parameter can be one of the following values: - * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 - * @param RXThreshold This parameter can be one of the following values: - * @arg @ref LL_USART_FIFOTHRESHOLD_1_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_1_2 - * @arg @ref LL_USART_FIFOTHRESHOLD_3_4 - * @arg @ref LL_USART_FIFOTHRESHOLD_7_8 - * @arg @ref LL_USART_FIFOTHRESHOLD_8_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) -{ - ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | - (RXThreshold << USART_CR3_RXFTCFG_Pos)); -} - -/** - * @brief USART enabled in STOP Mode. - * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that - * USART clock selection is HSI or LSE in RCC. - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_EnableInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief USART disabled in STOP Mode. - * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_DisableInStopMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_UESM); -} - -/** - * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not - * Wake-up from Stop mode feature is supported by the USARTx instance. - * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledInStopMode(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)) ? 1UL : 0UL); -} - -/** - * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) - * @rmtoll CR1 RE LL_USART_EnableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Receiver Disable - * @rmtoll CR1 RE LL_USART_DisableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Transmitter Enable - * @rmtoll CR1 TE LL_USART_EnableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Transmitter Disable - * @rmtoll CR1 TE LL_USART_DisableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Configure simultaneously enabled/disabled states - * of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_SetTransferDirection\n - * CR1 TE LL_USART_SetTransferDirection - * @param USARTx USART Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) -{ - ATOMIC_MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); -} - -/** - * @brief Return enabled/disabled states of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_GetTransferDirection\n - * CR1 TE LL_USART_GetTransferDirection - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); -} - -/** - * @brief Configure Parity (enabled/disabled and parity mode if enabled). - * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. - * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position - * (9th or 8th bit depending on data width) and parity is checked on the received data. - * @rmtoll CR1 PS LL_USART_SetParity\n - * CR1 PCE LL_USART_SetParity - * @param USARTx USART Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); -} - -/** - * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) - * @rmtoll CR1 PS LL_USART_GetParity\n - * CR1 PCE LL_USART_GetParity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_USART_GetParity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); -} - -/** - * @brief Set Receiver Wake Up method from Mute mode. - * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod - * @param USARTx USART Instance - * @param Method This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); -} - -/** - * @brief Return Receiver Wake Up method from Mute mode - * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); -} - -/** - * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M0 LL_USART_SetDataWidth\n - * CR1 M1 LL_USART_SetDataWidth - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); -} - -/** - * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M0 LL_USART_GetDataWidth\n - * CR1 M1 LL_USART_GetDataWidth - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); -} - -/** - * @brief Allow switch between Mute Mode and Active mode - * @rmtoll CR1 MME LL_USART_EnableMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableMuteMode(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. - * @rmtoll CR1 MME LL_USART_DisableMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableMuteMode(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_MME); -} - -/** - * @brief Indicate if switch between Mute Mode and Active mode is allowed - * @rmtoll CR1 MME LL_USART_IsEnabledMuteMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledMuteMode(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)) ? 1UL : 0UL); -} - -/** - * @brief Set Oversampling to 8-bit or 16-bit mode - * @rmtoll CR1 OVER8 LL_USART_SetOverSampling - * @param USARTx USART Instance - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_OVER8, OverSampling); -} - -/** - * @brief Return Oversampling mode - * @rmtoll CR1 OVER8 LL_USART_GetOverSampling - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_OVER8)); -} - -/** - * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput - * @param USARTx USART Instance - * @param LastBitClockPulse This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); -} - -/** - * @brief Retrieve Clock pulse of the last data bit output configuration - * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); -} - -/** - * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_SetClockPhase - * @param USARTx USART Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); -} - -/** - * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_GetClockPhase - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); -} - -/** - * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_SetClockPolarity - * @param USARTx USART Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); -} - -/** - * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_GetClockPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); -} - -/** - * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function - * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function - * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function - * @rmtoll CR2 CPHA LL_USART_ConfigClock\n - * CR2 CPOL LL_USART_ConfigClock\n - * CR2 LBCL LL_USART_ConfigClock - * @param USARTx USART Instance - * @param Phase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @param LBCPOutput This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); -} - -/** - * @brief Configure Clock source prescaler for baudrate generator and oversampling - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler - * @param USARTx USART Instance - * @param PrescalerValue This parameter can be one of the following values: - * @arg @ref LL_USART_PRESCALER_DIV1 - * @arg @ref LL_USART_PRESCALER_DIV2 - * @arg @ref LL_USART_PRESCALER_DIV4 - * @arg @ref LL_USART_PRESCALER_DIV6 - * @arg @ref LL_USART_PRESCALER_DIV8 - * @arg @ref LL_USART_PRESCALER_DIV10 - * @arg @ref LL_USART_PRESCALER_DIV12 - * @arg @ref LL_USART_PRESCALER_DIV16 - * @arg @ref LL_USART_PRESCALER_DIV32 - * @arg @ref LL_USART_PRESCALER_DIV64 - * @arg @ref LL_USART_PRESCALER_DIV128 - * @arg @ref LL_USART_PRESCALER_DIV256 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); -} - -/** - * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PRESCALER_DIV1 - * @arg @ref LL_USART_PRESCALER_DIV2 - * @arg @ref LL_USART_PRESCALER_DIV4 - * @arg @ref LL_USART_PRESCALER_DIV6 - * @arg @ref LL_USART_PRESCALER_DIV8 - * @arg @ref LL_USART_PRESCALER_DIV10 - * @arg @ref LL_USART_PRESCALER_DIV12 - * @arg @ref LL_USART_PRESCALER_DIV16 - * @arg @ref LL_USART_PRESCALER_DIV32 - * @arg @ref LL_USART_PRESCALER_DIV64 - * @arg @ref LL_USART_PRESCALER_DIV128 - * @arg @ref LL_USART_PRESCALER_DIV256 - */ -__STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->PRESC, USART_PRESC_PRESCALER)); -} - -/** - * @brief Enable Clock output on SCLK pin - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Disable Clock output on SCLK pin - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)) ? 1UL : 0UL); -} - -/** - * @brief Set the length of the stop bits - * @rmtoll CR2 STOP LL_USART_SetStopBitsLength - * @param USARTx USART Instance - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Retrieve the length of the stop bits - * @rmtoll CR2 STOP LL_USART_GetStopBitsLength - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); -} - -/** - * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) - * @note Call of this function is equivalent to following function call sequence : - * - Data Width configuration using @ref LL_USART_SetDataWidth() function - * - Parity Control and mode configuration using @ref LL_USART_SetParity() function - * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function - * @rmtoll CR1 PS LL_USART_ConfigCharacter\n - * CR1 PCE LL_USART_ConfigCharacter\n - * CR1 M0 LL_USART_ConfigCharacter\n - * CR1 M1 LL_USART_ConfigCharacter\n - * CR2 STOP LL_USART_ConfigCharacter - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_7B - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_0_5 - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_1_5 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, - uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Configure TX/RX pins swapping setting. - * @rmtoll CR2 SWAP LL_USART_SetTXRXSwap - * @param USARTx USART Instance - * @param SwapConfig This parameter can be one of the following values: - * @arg @ref LL_USART_TXRX_STANDARD - * @arg @ref LL_USART_TXRX_SWAPPED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXRXSwap(USART_TypeDef *USARTx, uint32_t SwapConfig) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_SWAP, SwapConfig); -} - -/** - * @brief Retrieve TX/RX pins swapping configuration. - * @rmtoll CR2 SWAP LL_USART_GetTXRXSwap - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TXRX_STANDARD - * @arg @ref LL_USART_TXRX_SWAPPED - */ -__STATIC_INLINE uint32_t LL_USART_GetTXRXSwap(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_SWAP)); -} - -/** - * @brief Configure RX pin active level logic - * @rmtoll CR2 RXINV LL_USART_SetRXPinLevel - * @param USARTx USART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_RXINV, PinInvMethod); -} - -/** - * @brief Retrieve RX pin active level logic configuration - * @rmtoll CR2 RXINV LL_USART_GetRXPinLevel - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_RXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_RXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_USART_GetRXPinLevel(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_RXINV)); -} - -/** - * @brief Configure TX pin active level logic - * @rmtoll CR2 TXINV LL_USART_SetTXPinLevel - * @param USARTx USART Instance - * @param PinInvMethod This parameter can be one of the following values: - * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTXPinLevel(USART_TypeDef *USARTx, uint32_t PinInvMethod) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_TXINV, PinInvMethod); -} - -/** - * @brief Retrieve TX pin active level logic configuration - * @rmtoll CR2 TXINV LL_USART_GetTXPinLevel - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TXPIN_LEVEL_STANDARD - * @arg @ref LL_USART_TXPIN_LEVEL_INVERTED - */ -__STATIC_INLINE uint32_t LL_USART_GetTXPinLevel(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_TXINV)); -} - -/** - * @brief Configure Binary data logic. - * @note Allow to define how Logical data from the data register are send/received : - * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) - * @rmtoll CR2 DATAINV LL_USART_SetBinaryDataLogic - * @param USARTx USART Instance - * @param DataLogic This parameter can be one of the following values: - * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBinaryDataLogic(USART_TypeDef *USARTx, uint32_t DataLogic) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_DATAINV, DataLogic); -} - -/** - * @brief Retrieve Binary data configuration - * @rmtoll CR2 DATAINV LL_USART_GetBinaryDataLogic - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_BINARY_LOGIC_POSITIVE - * @arg @ref LL_USART_BINARY_LOGIC_NEGATIVE - */ -__STATIC_INLINE uint32_t LL_USART_GetBinaryDataLogic(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_DATAINV)); -} - -/** - * @brief Configure transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_USART_SetTransferBitOrder - * @param USARTx USART Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_USART_BITORDER_LSBFIRST - * @arg @ref LL_USART_BITORDER_MSBFIRST - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferBitOrder(USART_TypeDef *USARTx, uint32_t BitOrder) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_MSBFIRST, BitOrder); -} - -/** - * @brief Return transfer bit order (either Less or Most Significant Bit First) - * @note MSB First means data is transmitted/received with the MSB first, following the start bit. - * LSB First means data is transmitted/received with data bit 0 first, following the start bit. - * @rmtoll CR2 MSBFIRST LL_USART_GetTransferBitOrder - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_BITORDER_LSBFIRST - * @arg @ref LL_USART_BITORDER_MSBFIRST - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_MSBFIRST)); -} - -/** - * @brief Enable Auto Baud-Rate Detection - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_ABREN); -} - -/** - * @brief Disable Auto Baud-Rate Detection - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_ABREN); -} - -/** - * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_ABREN) == (USART_CR2_ABREN)) ? 1UL : 0UL); -} - -/** - * @brief Set Auto Baud-Rate mode bits - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode - * @param USARTx USART Instance - * @param AutoBaudRateMode This parameter can be one of the following values: - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME - * @retval None - */ -__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t AutoBaudRateMode) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ABRMODE, AutoBaudRateMode); -} - -/** - * @brief Return Auto Baud-Rate mode - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_STARTBIT - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_FALLINGEDGE - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME - * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME - */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); -} - -/** - * @brief Enable Receiver Timeout - * @rmtoll CR2 RTOEN LL_USART_EnableRxTimeout - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRxTimeout(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_RTOEN); -} - -/** - * @brief Disable Receiver Timeout - * @rmtoll CR2 RTOEN LL_USART_DisableRxTimeout - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRxTimeout(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_RTOEN); -} - -/** - * @brief Indicate if Receiver Timeout feature is enabled - * @rmtoll CR2 RTOEN LL_USART_IsEnabledRxTimeout - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledRxTimeout(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_RTOEN) == (USART_CR2_RTOEN)) ? 1UL : 0UL); -} - -/** - * @brief Set Address of the USART node. - * @note This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with address mark detection. - * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. - * (b7-b4 should be set to 0) - * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. - * (This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with 7-bit address mark detection. - * The MSB of the character sent by the transmitter should be equal to 1. - * It may also be used for character detection during normal reception, - * Mute mode inactive (for example, end of block detection in ModBus protocol). - * In this case, the whole received character (8-bit) is compared to the ADD[7:0] - * value and CMF flag is set on match) - * @rmtoll CR2 ADD LL_USART_ConfigNodeAddress\n - * CR2 ADDM7 LL_USART_ConfigNodeAddress - * @param USARTx USART Instance - * @param AddressLen This parameter can be one of the following values: - * @arg @ref LL_USART_ADDRESS_DETECT_4B - * @arg @ref LL_USART_ADDRESS_DETECT_7B - * @param NodeAddress 4 or 7 bit Address of the USART node. - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigNodeAddress(USART_TypeDef *USARTx, uint32_t AddressLen, uint32_t NodeAddress) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, - (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); -} - -/** - * @brief Return 8 bit Address of the USART node as set in ADD field of CR2. - * @note If 4-bit Address Detection is selected in ADDM7, - * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) - * If 7-bit Address Detection is selected in ADDM7, - * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) - * @rmtoll CR2 ADD LL_USART_GetNodeAddress - * @param USARTx USART Instance - * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); -} - -/** - * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) - * @rmtoll CR2 ADDM7 LL_USART_GetNodeAddressLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_ADDRESS_DETECT_4B - * @arg @ref LL_USART_ADDRESS_DETECT_7B - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADDM7)); -} - -/** - * @brief Enable RTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Disable RTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Enable CTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Disable CTS HW Flow Control - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n - * CR3 CTSE LL_USART_SetHWFlowCtrl - * @param USARTx USART Instance - * @param HardwareFlowControl This parameter can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - * @retval None - */ -__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); -} - -/** - * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n - * CR3 CTSE LL_USART_GetHWFlowCtrl - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); -} - -/** - * @brief Enable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_EnableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOneBitSamp(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Disable One bit sampling method - * @rmtoll CR3 ONEBIT LL_USART_DisableOneBitSamp - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOneBitSamp(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_ONEBIT); -} - -/** - * @brief Indicate if One bit sampling method is enabled - * @rmtoll CR3 ONEBIT LL_USART_IsEnabledOneBitSamp - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOneBitSamp(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_ONEBIT) == (USART_CR3_ONEBIT)) ? 1UL : 0UL); -} - -/** - * @brief Enable Overrun detection - * @rmtoll CR3 OVRDIS LL_USART_EnableOverrunDetect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableOverrunDetect(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Disable Overrun detection - * @rmtoll CR3 OVRDIS LL_USART_DisableOverrunDetect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableOverrunDetect(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_OVRDIS); -} - -/** - * @brief Indicate if Overrun detection is enabled - * @rmtoll CR3 OVRDIS LL_USART_IsEnabledOverrunDetect - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS) ? 1UL : 0UL); -} - -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param PrescalerValue This parameter can be one of the following values: - * @arg @ref LL_USART_PRESCALER_DIV1 - * @arg @ref LL_USART_PRESCALER_DIV2 - * @arg @ref LL_USART_PRESCALER_DIV4 - * @arg @ref LL_USART_PRESCALER_DIV6 - * @arg @ref LL_USART_PRESCALER_DIV8 - * @arg @ref LL_USART_PRESCALER_DIV10 - * @arg @ref LL_USART_PRESCALER_DIV12 - * @arg @ref LL_USART_PRESCALER_DIV16 - * @arg @ref LL_USART_PRESCALER_DIV32 - * @arg @ref LL_USART_PRESCALER_DIV64 - * @arg @ref LL_USART_PRESCALER_DIV128 - * @arg @ref LL_USART_PRESCALER_DIV256 - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, - uint32_t OverSampling, - uint32_t BaudRate) -{ - uint32_t usartdiv; - uint32_t brrtemp; - - if (PrescalerValue > LL_USART_PRESCALER_DIV256) - { - /* Do not overstep the size of USART_PRESCALER_TAB */ - } - else if (BaudRate == 0U) - { - /* Can Not divide per 0 */ - } - else if (OverSampling == LL_USART_OVERSAMPLING_8) - { - usartdiv = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); - brrtemp = usartdiv & 0xFFF0U; - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - USARTx->BRR = brrtemp; - } - else - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, (uint8_t)PrescalerValue, BaudRate)); - } -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @note In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param PrescalerValue This parameter can be one of the following values: - * @arg @ref LL_USART_PRESCALER_DIV1 - * @arg @ref LL_USART_PRESCALER_DIV2 - * @arg @ref LL_USART_PRESCALER_DIV4 - * @arg @ref LL_USART_PRESCALER_DIV6 - * @arg @ref LL_USART_PRESCALER_DIV8 - * @arg @ref LL_USART_PRESCALER_DIV10 - * @arg @ref LL_USART_PRESCALER_DIV12 - * @arg @ref LL_USART_PRESCALER_DIV16 - * @arg @ref LL_USART_PRESCALER_DIV32 - * @arg @ref LL_USART_PRESCALER_DIV64 - * @arg @ref LL_USART_PRESCALER_DIV128 - * @arg @ref LL_USART_PRESCALER_DIV256 - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(const USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t PrescalerValue, - uint32_t OverSampling) -{ - uint32_t usartdiv; - uint32_t brrresult = 0x0U; - uint32_t periphclkpresc = (uint32_t)(PeriphClk / (USART_PRESCALER_TAB[(uint8_t)PrescalerValue])); - - usartdiv = USARTx->BRR; - - if (usartdiv == 0U) - { - /* Do not perform a division by 0 */ - } - else if (OverSampling == LL_USART_OVERSAMPLING_8) - { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; - if (usartdiv != 0U) - { - brrresult = (periphclkpresc * 2U) / usartdiv; - } - } - else - { - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = periphclkpresc / usartdiv; - } - } - return (brrresult); -} - -/** - * @brief Set Receiver Time Out Value (expressed in nb of bits duration) - * @rmtoll RTOR RTO LL_USART_SetRxTimeout - * @param USARTx USART Instance - * @param Timeout Value between Min_Data=0x00 and Max_Data=0x00FFFFFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetRxTimeout(USART_TypeDef *USARTx, uint32_t Timeout) -{ - MODIFY_REG(USARTx->RTOR, USART_RTOR_RTO, Timeout); -} - -/** - * @brief Get Receiver Time Out Value (expressed in nb of bits duration) - * @rmtoll RTOR RTO LL_USART_GetRxTimeout - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x00FFFFFF - */ -__STATIC_INLINE uint32_t LL_USART_GetRxTimeout(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_RTO)); -} - -/** - * @brief Set Block Length value in reception - * @rmtoll RTOR BLEN LL_USART_SetBlockLength - * @param USARTx USART Instance - * @param BlockLength Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBlockLength(USART_TypeDef *USARTx, uint32_t BlockLength) -{ - MODIFY_REG(USARTx->RTOR, USART_RTOR_BLEN, BlockLength << USART_RTOR_BLEN_Pos); -} - -/** - * @brief Get Block Length value in reception - * @rmtoll RTOR BLEN LL_USART_GetBlockLength - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->RTOR, USART_RTOR_BLEN) >> USART_RTOR_BLEN_Pos); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_IRDA Configuration functions related to Irda feature - * @{ - */ - -/** - * @brief Enable IrDA mode - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_EnableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Disable IrDA mode - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_DisableIrda - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Indicate if IrDA mode is enabled - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IREN LL_USART_IsEnabledIrda - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_IREN) == (USART_CR3_IREN)) ? 1UL : 0UL); -} - -/** - * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode - * @param USARTx USART Instance - * @param PowerMode This parameter can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_IRDA_POWER_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t PowerMode) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_IRLP, PowerMode); -} - -/** - * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_IRDA_POWER_NORMAL - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_IRLP)); -} - -/** - * @brief Set Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); -} - -/** - * @brief Return Irda prescaler value, used for dividing the USART clock source - * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler - * @param USARTx USART Instance - * @retval Irda prescaler value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_Smartcard Configuration functions related to Smartcard feature - * @{ - */ - -/** - * @brief Enable Smartcard NACK transmission - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Disable Smartcard NACK transmission - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_NACK); -} - -/** - * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_NACK) == (USART_CR3_NACK)) ? 1UL : 0UL); -} - -/** - * @brief Enable Smartcard mode - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_EnableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Disable Smartcard mode - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_DisableSmartcard - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Indicate if Smartcard mode is enabled - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_SCEN) == (USART_CR3_SCEN)) ? 1UL : 0UL); -} - -/** - * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. - * In transmission mode, it specifies the number of automatic retransmission retries, before - * generating a transmission error (FE bit set). - * In reception mode, it specifies the number or erroneous reception trials, before generating a - * reception error (RXNE and PE bits set) - * @rmtoll CR3 SCARCNT LL_USART_SetSmartcardAutoRetryCount - * @param USARTx USART Instance - * @param AutoRetryCount Value between Min_Data=0 and Max_Data=7 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, uint32_t AutoRetryCount) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_SCARCNT, AutoRetryCount << USART_CR3_SCARCNT_Pos); -} - -/** - * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount - * @param USARTx USART Instance - * @retval Smartcard Auto-Retry Count value (Value between Min_Data=0 and Max_Data=7) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_SCARCNT) >> USART_CR3_SCARCNT_Pos); -} - -/** - * @brief Set Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler - * @param USARTx USART Instance - * @param PrescalerValue Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint32_t PrescalerValue) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_PSC, (uint16_t)PrescalerValue); -} - -/** - * @brief Return Smartcard prescaler value, used for dividing the USART clock - * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler - * @param USARTx USART Instance - * @retval Smartcard prescaler value (Value between Min_Data=0 and Max_Data=31) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_PSC)); -} - -/** - * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime - * @param USARTx USART Instance - * @param GuardTime Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint32_t GuardTime) -{ - MODIFY_REG(USARTx->GTPR, USART_GTPR_GT, (uint16_t)(GuardTime << USART_GTPR_GT_Pos)); -} - -/** - * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods - * (GT[7:0] bits : Guard time value) - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime - * @param USARTx USART Instance - * @retval Smartcard Guard time value (Value between Min_Data=0x00 and Max_Data=0xFF) - */ -__STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->GTPR, USART_GTPR_GT) >> USART_GTPR_GT_Pos); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature - * @{ - */ - -/** - * @brief Enable Single Wire Half-Duplex mode - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Disable Single Wire Half-Duplex mode - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_SPI_SLAVE Configuration functions related to SPI Slave feature - * @{ - */ -/** - * @brief Enable SPI Synchronous Slave mode - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_SLVEN); -} - -/** - * @brief Disable SPI Synchronous Slave mode - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_SLVEN); -} - -/** - * @brief Indicate if SPI Synchronous Slave mode is enabled - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_SLVEN) == (USART_CR2_SLVEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable SPI Slave Selection using NSS input pin - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @note SPI Slave Selection depends on NSS input pin - * (The slave is selected when NSS is low and deselected when NSS is high). - * @rmtoll CR2 DIS_NSS LL_USART_EnableSPISlaveSelect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_DIS_NSS); -} - -/** - * @brief Disable SPI Slave Selection using NSS input pin - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @note SPI Slave will be always selected and NSS input pin will be ignored. - * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_DIS_NSS); -} - -/** - * @brief Indicate if SPI Slave Selection depends on NSS input pin - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_DIS_NSS) != (USART_CR2_DIS_NSS)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_LIN Configuration functions related to LIN feature - * @{ - */ - -/** - * @brief Set LIN Break Detection Length - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen - * @param USARTx USART Instance - * @param LINBDLength This parameter can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint32_t LINBDLength) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBDL, LINBDLength); -} - -/** - * @brief Return LIN Break Detection Length - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LINBREAK_DETECT_10B - * @arg @ref LL_USART_LINBREAK_DETECT_11B - */ -__STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBDL)); -} - -/** - * @brief Enable LIN mode - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_EnableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Disable LIN mode - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_DisableLIN - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Indicate if LIN mode is enabled - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_LINEN) == (USART_CR2_LINEN)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature - * @{ - */ - -/** - * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime - * @param USARTx USART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32_t Time) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); -} - -/** - * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime - * @param USARTx USART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); -} - -/** - * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime - * @param USARTx USART Instance - * @param Time Value between Min_Data=0 and Max_Data=31 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t Time) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); -} - -/** - * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime - * @param USARTx USART Instance - * @retval Time value expressed on 5 bits ([4:0] bits) : Value between Min_Data=0 and Max_Data=31 - */ -__STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); -} - -/** - * @brief Enable Driver Enable (DE) Mode - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_EnableDEMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Disable Driver Enable (DE) Mode - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_DisableDEMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DEM); -} - -/** - * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)) ? 1UL : 0UL); -} - -/** - * @brief Select Driver Enable Polarity - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity - * @param USARTx USART Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_DE_POLARITY_HIGH - * @arg @ref LL_USART_DE_POLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_t Polarity) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_DEP, Polarity); -} - -/** - * @brief Return Driver Enable Polarity - * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not - * Driver Enable feature is supported by the USARTx instance. - * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DE_POLARITY_HIGH - * @arg @ref LL_USART_DE_POLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_USART_GetDESignalPolarity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_DEP)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services - * @{ - */ - -/** - * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) - * @note In UART mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Asynchronous Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigAsyncMode\n - * CR2 CLKEN LL_USART_ConfigAsyncMode\n - * CR3 SCEN LL_USART_ConfigAsyncMode\n - * CR3 IREN LL_USART_ConfigAsyncMode\n - * CR3 HDSEL LL_USART_ConfigAsyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) -{ - /* In Asynchronous mode, the following bits must be kept cleared: - - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Synchronous Mode - * @note In Synchronous mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also sets the USART in Synchronous mode. - * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * @note Other remaining configurations items related to Synchronous Mode - * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSyncMode\n - * CR2 CLKEN LL_USART_ConfigSyncMode\n - * CR3 SCEN LL_USART_ConfigSyncMode\n - * CR3 IREN LL_USART_ConfigSyncMode\n - * CR3 HDSEL LL_USART_ConfigSyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) -{ - /* In Synchronous mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); - /* set the UART/USART in Synchronous mode */ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in LIN Mode - * @note In LIN mode, the following bits must be kept cleared: - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also set the UART/USART in LIN mode. - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set LINEN in CR2 using @ref LL_USART_EnableLIN() function - * @note Other remaining configurations items related to LIN Mode - * (as Baud Rate, Word length, LIN Break Detection Length, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigLINMode\n - * CR2 STOP LL_USART_ConfigLINMode\n - * CR2 LINEN LL_USART_ConfigLINMode\n - * CR3 IREN LL_USART_ConfigLINMode\n - * CR3 SCEN LL_USART_ConfigLINMode\n - * CR3 HDSEL LL_USART_ConfigLINMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) -{ - /* In LIN mode, the following bits must be kept cleared: - - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); - /* Set the UART/USART in LIN mode */ - SET_BIT(USARTx->CR2, USART_CR2_LINEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode - * @note In Half Duplex mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * This function also sets the UART/USART in Half Duplex mode. - * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function - * @note Other remaining configurations items related to Half Duplex Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigHalfDuplexMode\n - * CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n - * CR3 HDSEL LL_USART_ConfigHalfDuplexMode\n - * CR3 SCEN LL_USART_ConfigHalfDuplexMode\n - * CR3 IREN LL_USART_ConfigHalfDuplexMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) -{ - /* In Half Duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); - /* set the UART/USART in Half Duplex mode */ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Smartcard Mode - * @note In Smartcard mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also configures Stop bits to 1.5 bits and - * sets the USART in Smartcard mode (SCEN bit). - * Clock Output is also enabled (CLKEN). - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * - Set SCEN in CR3 using @ref LL_USART_EnableSmartcard() function - * @note Other remaining configurations items related to Smartcard Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigSmartcardMode\n - * CR2 STOP LL_USART_ConfigSmartcardMode\n - * CR2 CLKEN LL_USART_ConfigSmartcardMode\n - * CR3 HDSEL LL_USART_ConfigSmartcardMode\n - * CR3 SCEN LL_USART_ConfigSmartcardMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) -{ - /* In Smartcard mode, the following bits must be kept cleared: - - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); - /* Configure Stop bits to 1.5 bits */ - /* Synchronous mode is activated by default */ - SET_BIT(USARTx->CR2, (USART_CR2_STOP_0 | USART_CR2_STOP_1 | USART_CR2_CLKEN)); - /* set the UART/USART in Smartcard mode */ - SET_BIT(USARTx->CR3, USART_CR3_SCEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Irda Mode - * @note In IRDA mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - STOP and CLKEN bits in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not - * IrDA feature is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Configure STOP in CR2 using @ref LL_USART_SetStopBitsLength() function - * - Set IREN in CR3 using @ref LL_USART_EnableIrda() function - * @note Other remaining configurations items related to Irda Mode - * (as Baud Rate, Word length, Power mode, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigIrdaMode\n - * CR2 CLKEN LL_USART_ConfigIrdaMode\n - * CR2 STOP LL_USART_ConfigIrdaMode\n - * CR3 SCEN LL_USART_ConfigIrdaMode\n - * CR3 HDSEL LL_USART_ConfigIrdaMode\n - * CR3 IREN LL_USART_ConfigIrdaMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) -{ - /* In IRDA mode, the following bits must be kept cleared: - - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); - /* set the UART/USART in IRDA mode */ - SET_BIT(USARTx->CR3, USART_CR3_IREN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Multi processor Mode - * (several USARTs connected in a network, one of the USARTs can be the master, - * its TX output connected to the RX inputs of the other slaves USARTs). - * @note In MultiProcessor mode, the following bits must be kept cleared: - * - LINEN bit in the USART_CR2 register, - * - CLKEN bit in the USART_CR2 register, - * - SCEN bit in the USART_CR3 register, - * - IREN bit in the USART_CR3 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear SCEN in CR3 using @ref LL_USART_DisableSmartcard() function - * - Clear IREN in CR3 using @ref LL_USART_DisableIrda() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Multi processor Mode - * (as Baud Rate, Wake Up Method, Node address, ...) should be set using - * dedicated functions - * @rmtoll CR2 LINEN LL_USART_ConfigMultiProcessMode\n - * CR2 CLKEN LL_USART_ConfigMultiProcessMode\n - * CR3 SCEN LL_USART_ConfigMultiProcessMode\n - * CR3 HDSEL LL_USART_ConfigMultiProcessMode\n - * CR3 IREN LL_USART_ConfigMultiProcessMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) -{ - /* In Multi Processor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register. - */ - CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if the USART Parity Error Flag is set or not - * @rmtoll ISR PE LL_USART_IsActiveFlag_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Framing Error Flag is set or not - * @rmtoll ISR FE LL_USART_IsActiveFlag_FE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll ISR NE LL_USART_IsActiveFlag_NE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART OverRun Error Flag is set or not - * @rmtoll ISR ORE LL_USART_IsActiveFlag_ORE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART IDLE line detected Flag is set or not - * @rmtoll ISR IDLE LL_USART_IsActiveFlag_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); -} - -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE_RXFNE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Transmission Complete Flag is set or not - * @rmtoll ISR TC LL_USART_IsActiveFlag_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); -} - -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_LBDF) == (USART_ISR_LBDF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART CTS Flag is set or not - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CTS(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receiver Time Out Flag is set or not - * @rmtoll ISR RTOF LL_USART_IsActiveFlag_RTO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RTOF) == (USART_ISR_RTOF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART End Of Block Flag is set or not - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_EOBF) == (USART_ISR_EOBF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the SPI Slave Underrun error flag is set or not - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_UDR) == (USART_ISR_UDR)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_ABRE) == (USART_ISR_ABRE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABR(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_ABRF) == (USART_ISR_ABRF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Busy Flag is set or not - * @rmtoll ISR BUSY LL_USART_IsActiveFlag_BUSY - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_BUSY(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Character Match Flag is set or not - * @rmtoll ISR CMF LL_USART_IsActiveFlag_CM - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_CM(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Send Break Flag is set or not - * @rmtoll ISR SBKF LL_USART_IsActiveFlag_SBK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not - * @rmtoll ISR RWU LL_USART_IsActiveFlag_RWU - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Transmit Enable Acknowledge Flag is set or not - * @rmtoll ISR TEACK LL_USART_IsActiveFlag_TEACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TEACK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receive Enable Acknowledge Flag is set or not - * @rmtoll ISR REACK LL_USART_IsActiveFlag_REACK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART TX FIFO Empty Flag is set or not - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART RX FIFO Full Flag is set or not - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFF(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)) ? 1UL : 0UL); -} - -/** - * @brief Check if the Smartcard Transmission Complete Before Guard Time Flag is set or not - * @rmtoll ISR TCBGT LL_USART_IsActiveFlag_TCBGT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TCBGT) == (USART_ISR_TCBGT)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART TX FIFO Threshold Flag is set or not - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART RX FIFO Threshold Flag is set or not - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXFT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)) ? 1UL : 0UL); -} - -/** - * @brief Clear Parity Error Flag - * @rmtoll ICR PECF LL_USART_ClearFlag_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_PECF); -} - -/** - * @brief Clear Framing Error Flag - * @rmtoll ICR FECF LL_USART_ClearFlag_FE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_FECF); -} - -/** - * @brief Clear Noise Error detected Flag - * @rmtoll ICR NECF LL_USART_ClearFlag_NE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_NECF); -} - -/** - * @brief Clear OverRun Error Flag - * @rmtoll ICR ORECF LL_USART_ClearFlag_ORE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_ORECF); -} - -/** - * @brief Clear IDLE line detected Flag - * @rmtoll ICR IDLECF LL_USART_ClearFlag_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_IDLECF); -} - -/** - * @brief Clear TX FIFO Empty Flag - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TXFE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_TXFECF); -} - -/** - * @brief Clear Transmission Complete Flag - * @rmtoll ICR TCCF LL_USART_ClearFlag_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_TCCF); -} - -/** - * @brief Clear Smartcard Transmission Complete Before Guard Time Flag - * @rmtoll ICR TCBGTCF LL_USART_ClearFlag_TCBGT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_TCBGTCF); -} - -/** - * @brief Clear LIN Break Detection Flag - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_LBDCF); -} - -/** - * @brief Clear CTS Interrupt Flag - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_CTSCF); -} - -/** - * @brief Clear Receiver Time Out Flag - * @rmtoll ICR RTOCF LL_USART_ClearFlag_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_RTOCF); -} - -/** - * @brief Clear End Of Block Flag - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_EOBCF); -} - -/** - * @brief Clear SPI Slave Underrun Flag - * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not - * SPI Slave mode feature is supported by the USARTx instance. - * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_UDR(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_UDRCF); -} - -/** - * @brief Clear Character Match Flag - * @rmtoll ICR CMCF LL_USART_ClearFlag_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->ICR, USART_ICR_CMCF); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXNE_RXFNE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); -} - -/** - * @brief Enable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_EnableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Enable TX Empty and TX FIFO Not Full Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXE_TXFNF(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); -} - -/** - * @brief Enable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_EnableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Enable Character Match Interrupt - * @rmtoll CR1 CMIE LL_USART_EnableIT_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CM(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Enable Receiver Timeout Interrupt - * @rmtoll CR1 RTOIE LL_USART_EnableIT_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RTOIE); -} - -/** - * @brief Enable End Of Block Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_EOBIE); -} - -/** - * @brief Enable TX FIFO Empty Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXFE(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TXFEIE); -} - -/** - * @brief Enable RX FIFO Full Interrupt - * @rmtoll CR1 RXFFIE LL_USART_EnableIT_RXFF - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_RXFFIE); -} - -/** - * @brief Enable LIN Break Detection Interrupt - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_LBD(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_LBDIE); -} - -/** - * @brief Enable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. - * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Enable CTS Interrupt - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Enable TX FIFO Threshold Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TXFTIE); -} - -/** - * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_TCBGTIE); -} - -/** - * @brief Enable RX FIFO Threshold Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXFT(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_RXFTIE); -} - -/** - * @brief Disable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXNE_RXFNE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); -} - -/** - * @brief Disable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_DisableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Disable TX Empty and TX FIFO Not Full Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXE_TXFNF(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE); -} - -/** - * @brief Disable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_DisableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Disable Character Match Interrupt - * @rmtoll CR1 CMIE LL_USART_DisableIT_CM - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CM(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_CMIE); -} - -/** - * @brief Disable Receiver Timeout Interrupt - * @rmtoll CR1 RTOIE LL_USART_DisableIT_RTO - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RTOIE); -} - -/** - * @brief Disable End Of Block Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_EOBIE); -} - -/** - * @brief Disable TX FIFO Empty Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TXFEIE); -} - -/** - * @brief Disable RX FIFO Full Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_RXFFIE); -} - -/** - * @brief Disable LIN Break Detection Interrupt - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_LBD(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_LBDIE); -} - -/** - * @brief Disable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_ISR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_ISR register. - * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Disable CTS Interrupt - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Disable TX FIFO Threshold Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TXFTIE); -} - -/** - * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_TCBGTIE); -} - -/** - * @brief Disable RX FIFO Threshold Interrupt - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXFT(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_RXFTIE); -} - -/** - * @brief Check if the USART IDLE Interrupt source is enabled or disabled. - * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); -} - -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ - -/** - * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE_RXFNE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); -} - -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ - -/** - * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE_TXFNF(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Parity Error Interrupt is enabled or disabled. - * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Character Match Interrupt is enabled or disabled. - * @rmtoll CR1 CMIE LL_USART_IsEnabledIT_CM - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CM(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Receiver Timeout Interrupt is enabled or disabled. - * @rmtoll CR1 RTOIE LL_USART_IsEnabledIT_RTO - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_RTOIE) == (USART_CR1_RTOIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_EOBIE) == (USART_CR1_EOBIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not - * LIN feature is supported by the USARTx instance. - * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_LBD(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR2, USART_CR2_LBDIE) == (USART_CR2_LBDIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART Error Interrupt is enabled or disabled. - * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. - * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not - * Smartcard feature is supported by the USARTx instance. - * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_TCBGTIE) == (USART_CR3_TCBGTIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFT(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_DMA_Management DMA_Management - * @{ - */ - -/** - * @brief Enable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Disable DMA Mode for reception - * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Check if DMA Mode is enabled for reception - * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) -{ - ATOMIC_SET_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Disable DMA Mode for transmission - * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) -{ - ATOMIC_CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Check if DMA Mode is enabled for transmission - * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_USART_EnableDMADeactOnRxErr - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Disable DMA Disabling on Reception Error - * @rmtoll CR3 DDRE LL_USART_DisableDMADeactOnRxErr - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMADeactOnRxErr(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DDRE); -} - -/** - * @brief Indicate if DMA Disabling on Reception Error is disabled - * @rmtoll CR3 DDRE LL_USART_IsEnabledDMADeactOnRxErr - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMADeactOnRxErr(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)) ? 1UL : 0UL); -} - -/** - * @brief Get the data register address used for DMA transfer - * @rmtoll RDR RDR LL_USART_DMA_GetRegAddr\n - * @rmtoll TDR TDR LL_USART_DMA_GetRegAddr - * @param USARTx USART Instance - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_USART_DMA_REG_DATA_TRANSMIT - * @arg @ref LL_USART_DMA_REG_DATA_RECEIVE - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(const USART_TypeDef *USARTx, uint32_t Direction) -{ - uint32_t data_reg_addr; - - if (Direction == LL_USART_DMA_REG_DATA_TRANSMIT) - { - /* return address of TDR register */ - data_reg_addr = (uint32_t) &(USARTx->TDR); - } - else - { - /* return address of RDR register */ - data_reg_addr = (uint32_t) &(USARTx->RDR); - } - - return data_reg_addr; -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Read Receiver Data register (Receive Data value, 8 bits) - * @rmtoll RDR RDR LL_USART_ReceiveData8 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(const USART_TypeDef *USARTx) -{ - return (uint8_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR) & 0xFFU); -} - -/** - * @brief Read Receiver Data register (Receive Data value, 9 bits) - * @rmtoll RDR RDR LL_USART_ReceiveData9 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(const USART_TypeDef *USARTx) -{ - return (uint16_t)(READ_BIT(USARTx->RDR, USART_RDR_RDR)); -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) - * @rmtoll TDR TDR LL_USART_TransmitData8 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) -{ - USARTx->TDR = Value; -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) - * @rmtoll TDR TDR LL_USART_TransmitData9 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) -{ - USARTx->TDR = (uint16_t)(Value & 0x1FFUL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Execution Execution - * @{ - */ - -/** - * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not - * Auto Baud Rate detection feature is supported by the USARTx instance. - * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_ABRRQ); -} - -/** - * @brief Request Break sending - * @rmtoll RQR SBKRQ LL_USART_RequestBreakSending - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_SBKRQ); -} - -/** - * @brief Put USART in mute mode and set the RWU flag - * @rmtoll RQR MMRQ LL_USART_RequestEnterMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_MMRQ); -} - -/** - * @brief Request a Receive Data and FIFO flush - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @note Allows to discard the received data without reading them, and avoid an overrun - * condition. - * @rmtoll RQR RXFRQ LL_USART_RequestRxDataFlush - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_RXFRQ); -} - -/** - * @brief Request a Transmit data and FIFO flush - * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not - * FIFO mode feature is supported by the USARTx instance. - * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestTxDataFlush(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->RQR, (uint16_t)USART_RQR_TXFRQ); -} - -/** - * @} - */ - -/** @defgroup USART_LL_Autonomous_Mode Configuration functions related to Autonomous mode feature - * @{ - */ - -/** - * @brief Enable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_USART_Enable_SelectedTrigger - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable_SelectedTrigger(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN); -} - -/** - * @brief Disable Selected Trigger - * @rmtoll AUTOCR TRIGEN LL_USART_Disable_SelectedTrigger - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable_SelectedTrigger(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN); -} - -/** - * @brief Indicate if Selected Trigger is disabled or enabled - * @rmtoll AUTOCR TRIGEN LL_USART_IsEnabled_SelectedTrigger - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled_SelectedTrigger(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGEN) == (USART_AUTOCR_TRIGEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable Autonomous Send Idle Frame feature - * @rmtoll AUTOCR IDLEDIS LL_USART_Enable_AutonomousSendIdleFrame - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable_AutonomousSendIdleFrame(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS); -} - -/** - * @brief Disable Autonomous Send Idle Frame feature - * @rmtoll AUTOCR IDLEDIS LL_USART_Disable_AutonomousSendIdleFrame - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable_AutonomousSendIdleFrame(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS); -} - -/** - * @brief Indicate if Autonomous send Idle Frame feature is disabled or enabled - * @rmtoll AUTOCR IDLEDIS LL_USART_IsEnabled_AutonomousSendIdleFrame - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled_AutonomousSendIdleFrame(const USART_TypeDef *USARTx) -{ - return ((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_IDLEDIS) == (USART_AUTOCR_IDLEDIS)) ? 0UL : 1UL); -} - -/** - * @brief Configure the Number of transferred data in bytes - * @rmtoll AUTOCR TDN LL_USART_SetNbTxData - * @param USARTx USART Instance - * @param Nbdata This parameter can be a value between 0 and 0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_USART_SetNbTxData(USART_TypeDef *USARTx, uint32_t Nbdata) -{ - MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TDN, (uint16_t)Nbdata); -} - -/** - * @brief Retrieve the Number of transferred data in bytes - * @rmtoll AUTOCR TDN LL_USART_GetNbTxData - * @param USARTx USART Instance - * @retval Returned value can be a value between 0 and 0xFFFF - */ -__STATIC_INLINE uint32_t LL_USART_GetNbTxData(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TDN)); -} - -/** - * @brief Set the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_USART_SetTriggerPolarity - * @param USARTx USART Instance - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_TRIG_POLARITY_RISING - * @arg @ref LL_USART_TRIG_POLARITY_FALLING - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTriggerPolarity(USART_TypeDef *USARTx, uint32_t Polarity) -{ - MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL, Polarity); -} - -/** - * @brief Get the trigger polarity - * @rmtoll AUTOCR TRIGPOL LL_USART_GetTriggerPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_TRIG_POLARITY_RISING - * @arg @ref LL_USART_TRIG_POLARITY_FALLING - */ -__STATIC_INLINE uint32_t LL_USART_GetTriggerPolarity(const USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGPOL)); -} - -/** - * @brief Set the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_USART_SetSelectedTrigger - * @param USARTx USART Instance - * @param Trigger This parameter can be one of the following values: - * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG - * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG - * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG - * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG - * @arg @ref LL_USART_EXTI_LINE6_TRG - * @arg @ref LL_USART_EXTI_LINE9_TRG - * @arg @ref LL_USART_LPTIM1_OUT_TRG - * @arg @ref LL_USART_LPTIM2_OUT_TRG - * @arg @ref LL_USART_COMP1_OUT_TRG - * @arg @ref LL_USART_COMP2_OUT_TRG - * @arg @ref LL_USART_RTC_ALRA_TRG - * @arg @ref LL_USART_RTC_WUT_TRG - * @retval None - */ -__STATIC_INLINE void LL_USART_SetSelectedTrigger(USART_TypeDef *USARTx, uint32_t Trigger) -{ - MODIFY_REG(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL, (Trigger << USART_AUTOCR_TRIGSEL_Pos)); -} - -/** - * @brief Get the selected trigger - * @rmtoll AUTOCR TRIGSEL LL_USART_GetSelectedTrigger - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_GPDMA1_CH0_TCF_TRG - * @arg @ref LL_USART_GPDMA1_CH1_TCF_TRG - * @arg @ref LL_USART_GPDMA1_CH2_TCF_TRG - * @arg @ref LL_USART_GPDMA1_CH3_TCF_TRG - * @arg @ref LL_USART_EXTI_LINE6_TRG - * @arg @ref LL_USART_EXTI_LINE9_TRG - * @arg @ref LL_USART_LPTIM1_OUT_TRG - * @arg @ref LL_USART_LPTIM2_OUT_TRG - * @arg @ref LL_USART_COMP1_OUT_TRG - * @arg @ref LL_USART_COMP2_OUT_TRG - * @arg @ref LL_USART_RTC_ALRA_TRG - * @arg @ref LL_USART_RTC_WUT_TRG - */ -__STATIC_INLINE uint32_t LL_USART_GetSelectedTrigger(const USART_TypeDef *USARTx) -{ - return (uint32_t)((READ_BIT(USARTx->AUTOCR, USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_USART_DeInit(const USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, const LL_USART_InitTypeDef *USART_InitStruct); -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, const LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_LL_USART_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h deleted file mode 100644 index e644ab255..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_usb.h +++ /dev/null @@ -1,1221 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_usb.h - * @author MCD Application Team - * @brief Header file of USB Low Layer HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_LL_USB_H -#define STM32U5xx_LL_USB_H - -#ifdef __cplusplus -extern "C" { -#endif /* __cplusplus */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal_def.h" - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup USB_LL - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -#ifndef HAL_USB_TIMEOUT -#define HAL_USB_TIMEOUT 0xF000000U -#endif /* define HAL_USB_TIMEOUT */ - -#ifndef HAL_USB_CURRENT_MODE_MAX_DELAY_MS -#define HAL_USB_CURRENT_MODE_MAX_DELAY_MS 200U -#endif /* define HAL_USB_CURRENT_MODE_MAX_DELAY_MS */ - -/** - * @brief USB Mode definition - */ - -typedef enum -{ - USB_DEVICE_MODE = 0, - USB_HOST_MODE = 1, - USB_DRD_MODE = 2 -} USB_ModeTypeDef; - -/** - * @brief URB States definition - */ -typedef enum -{ - URB_IDLE = 0, - URB_DONE, - URB_NOTREADY, - URB_NYET, - URB_ERROR, - URB_STALL -} USB_URBStateTypeDef; - -/** - * @brief Host channel States definition - */ -typedef enum -{ - HC_IDLE = 0, - HC_XFRC, - HC_HALTED, - HC_ACK, - HC_NAK, - HC_NYET, - HC_STALL, - HC_XACTERR, - HC_BBLERR, - HC_DATATGLERR -} USB_HCStateTypeDef; - - -/** - * @brief USB Instance Initialization Structure definition - */ -typedef struct -{ - uint8_t dev_endpoints; /*!< Device Endpoints number. - This parameter depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t Host_channels; /*!< Host Channels number. - This parameter Depends on the used USB core. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t dma_enable; /*!< USB DMA state. - If DMA is not supported this parameter shall be set by default to zero */ - - uint8_t speed; /*!< USB Core speed. - This parameter can be any value of @ref PCD_Speed/HCD_Speed - (HCD_SPEED_xxx, HCD_SPEED_xxx) */ - - uint8_t ep0_mps; /*!< Set the Endpoint 0 Max Packet size. */ - - uint8_t phy_itface; /*!< Select the used PHY interface. - This parameter can be any value of @ref PCD_PHY_Module/HCD_PHY_Module */ - - uint8_t Sof_enable; /*!< Enable or disable the output of the SOF signal. */ - - uint8_t low_power_enable; /*!< Enable or disable the low Power Mode. */ - - uint8_t lpm_enable; /*!< Enable or disable Link Power Management. */ - - uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ - - uint8_t vbus_sensing_enable; /*!< Enable or disable the VBUS Sensing feature. */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - uint8_t use_dedicated_ep1; /*!< Enable or disable the use of the dedicated EP1 interrupt. */ - - uint8_t use_external_vbus; /*!< Enable or disable the use of the external VBUS. */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined (USB_DRD_FS) - uint8_t bulk_doublebuffer_enable; /*!< Enable or disable the double buffer mode on bulk EP */ - - uint8_t iso_singlebuffer_enable; /*!< Enable or disable the Single buffer mode on Isochronous EP */ -#endif /* defined (USB_DRD_FS) */ -} USB_CfgTypeDef; - -typedef struct -{ - uint8_t num; /*!< Endpoint number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t is_stall; /*!< Endpoint stall condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - uint8_t is_iso_incomplete; /*!< Endpoint isoc condition - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - uint8_t type; /*!< Endpoint type - This parameter can be any value of @ref USB_LL_EP_Type */ - - uint8_t data_pid_start; /*!< Initial data PID - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - -#if defined (USB_DRD_FS) - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ -#endif /* defined (USB_DRD_FS) */ - - uint32_t maxpacket; /*!< Endpoint Max packet size - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer */ - - uint32_t xfer_len; /*!< Current transfer length */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - uint8_t even_odd_frame; /*!< IFrame parity - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint16_t tx_fifo_num; /*!< Transmission FIFO number - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address */ - - uint32_t xfer_size; /*!< requested transfer size */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) - uint32_t xfer_len_db; /*!< double buffer transfer length used with bulk double buffer in */ - - uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ -#endif /* defined (USB_DRD_FS) */ -} USB_EPTypeDef; - -typedef struct -{ - uint8_t dev_addr; /*!< USB device address. - This parameter must be a number between Min_Data = 1 and Max_Data = 255 */ -#if defined (USB_DRD_FS) - uint8_t phy_ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ch_dir; /*!< channel direction - This parameter store the physical channel direction IN/OUT/BIDIR */ -#else - uint8_t ch_num; /*!< Host channel number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - - uint8_t ep_is_in; /*!< Endpoint direction - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ -#endif /* defined (USB_DRD_FS) */ - - uint8_t ep_num; /*!< Endpoint number. - This parameter must be a number between Min_Data = 1 and Max_Data = 15 */ - uint8_t speed; /*!< USB Host Channel speed. - This parameter can be any value of @ref HCD_Device_Speed: - (HCD_DEVICE_SPEED_xxx) */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - uint8_t do_ping; /*!< Enable or disable the use of the PING protocol for HS mode. */ - uint8_t do_ssplit; /*!< Enable start split transaction in HS mode. */ - uint8_t do_csplit; /*!< Enable complete split transaction in HS mode. */ - uint8_t ep_ss_schedule; /*!< Enable periodic endpoint start split schedule . */ - uint32_t iso_splt_xactPos; /*!< iso split transfer transaction position. */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - uint8_t hub_port_nbr; /*!< USB HUB port number */ - uint8_t hub_addr; /*!< USB HUB address */ - - uint8_t ep_type; /*!< Endpoint Type. - This parameter can be any value of @ref USB_LL_EP_Type */ - - uint16_t max_packet; /*!< Endpoint Max packet size. - This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */ - - uint8_t data_pid; /*!< Initial data PID. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t *xfer_buff; /*!< Pointer to transfer buffer. */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - uint32_t XferSize; /*!< OTG Channel transfer size. */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - uint32_t xfer_len; /*!< Current transfer length. */ -#if defined (USB_DRD_FS) - uint32_t xfer_len_db; /*!< Current transfer length used in double buffer mode. */ -#endif /* defined (USB_DRD_FS) */ - - uint32_t xfer_count; /*!< Partial transfer length in case of multi packet transfer. */ - - uint8_t toggle_in; /*!< IN transfer current toggle flag. - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ - - uint8_t toggle_out; /*!< OUT transfer current toggle flag - This parameter must be a number between Min_Data = 0 and Max_Data = 1 */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - uint32_t dma_addr; /*!< 32 bits aligned transfer buffer address. */ - uint32_t NyetErrCnt; /*!< Complete Split NYET Host channel error count. */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - uint32_t ErrCnt; /*!< Host channel error count. */ - -#if defined (USB_DRD_FS) - uint16_t pmaadress; /*!< PMA Address - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr0; /*!< PMA Address0 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint16_t pmaaddr1; /*!< PMA Address1 - This parameter can be any value between Min_addr = 0 and Max_addr = 1K */ - - uint8_t doublebuffer; /*!< Double buffer enable - This parameter can be 0 or 1 */ -#endif /* defined (USB_DRD_FS) */ - - USB_URBStateTypeDef urb_state; /*!< URB state. - This parameter can be any value of @ref USB_URBStateTypeDef */ - - USB_HCStateTypeDef state; /*!< Host Channel state. - This parameter can be any value of @ref USB_HCStateTypeDef */ -} USB_HCTypeDef; - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -typedef USB_ModeTypeDef USB_OTG_ModeTypeDef; -typedef USB_CfgTypeDef USB_OTG_CfgTypeDef; -typedef USB_EPTypeDef USB_OTG_EPTypeDef; -typedef USB_URBStateTypeDef USB_OTG_URBStateTypeDef; -typedef USB_HCStateTypeDef USB_OTG_HCStateTypeDef; -typedef USB_HCTypeDef USB_OTG_HCTypeDef; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined (USB_DRD_FS) -typedef USB_ModeTypeDef USB_DRD_ModeTypeDef; -typedef USB_CfgTypeDef USB_DRD_CfgTypeDef; -typedef USB_EPTypeDef USB_DRD_EPTypeDef; -typedef USB_URBStateTypeDef USB_DRD_URBStateTypeDef; -typedef USB_HCStateTypeDef USB_DRD_HCStateTypeDef; -typedef USB_HCTypeDef USB_DRD_HCTypeDef; -#endif /* defined (USB_DRD_FS) */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup PCD_Exported_Constants PCD Exported Constants - * @{ - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @defgroup USB_OTG_CORE VERSION ID - * @{ - */ -#define USB_OTG_CORE_ID_300A 0x4F54300AU -#define USB_OTG_CORE_ID_310A 0x4F54310AU -/** - * @} - */ - -/** @defgroup USB_Core_Mode_ USB Core Mode - * @{ - */ -#define USB_OTG_MODE_DEVICE 0U -#define USB_OTG_MODE_HOST 1U -#define USB_OTG_MODE_DRD 2U -/** - * @} - */ - -/** @defgroup USB_LL_Core_Speed USB Low Layer Core Speed - * @{ - */ -#define USB_OTG_SPEED_HIGH 0U -#define USB_OTG_SPEED_HIGH_IN_FULL 1U -#define USB_OTG_SPEED_FULL 3U -/** - * @} - */ - -/** @defgroup USB_LL_Core_PHY USB Low Layer Core PHY - * @{ - */ -#define USB_OTG_EMBEDDED_PHY 2U -#define USB_OTG_HS_EMBEDDED_PHY 3U -/** - * @} - */ - -/** @defgroup USB_LL_Turnaround_Timeout Turnaround Timeout Value - * @{ - */ -#ifndef USBD_HS_TRDT_VALUE -#define USBD_HS_TRDT_VALUE 9U -#endif /* USBD_HS_TRDT_VALUE */ -#ifndef USBD_FS_TRDT_VALUE -#define USBD_FS_TRDT_VALUE 5U -#define USBD_DEFAULT_TRDT_VALUE 9U -#endif /* USBD_HS_TRDT_VALUE */ -/** - * @} - */ - -/** @defgroup USB_LL_Core_MPS USB Low Layer Core MPS - * @{ - */ -#define USB_OTG_HS_MAX_PACKET_SIZE 512U -#define USB_OTG_FS_MAX_PACKET_SIZE 64U -#define USB_OTG_MAX_EP0_SIZE 64U -/** - * @} - */ - -/** @defgroup USB_LL_Core_PHY_Frequency USB Low Layer Core PHY Frequency - * @{ - */ -#define DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ (0U << 1) -#define DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ (1U << 1) -#define DSTS_ENUMSPD_FS_PHY_48MHZ (3U << 1) -/** - * @} - */ - -/** @defgroup USB_LL_CORE_Frame_Interval USB Low Layer Core Frame Interval - * @{ - */ -#define DCFG_FRAME_INTERVAL_80 0U -#define DCFG_FRAME_INTERVAL_85 1U -#define DCFG_FRAME_INTERVAL_90 2U -#define DCFG_FRAME_INTERVAL_95 3U -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** @defgroup USB_LL_EP0_MPS USB Low Layer EP0 MPS - * @{ - */ -#define EP_MPS_64 0U -#define EP_MPS_32 1U -#define EP_MPS_16 2U -#define EP_MPS_8 3U -/** - * @} - */ - -/** @defgroup USB_LL_EP_Type USB Low Layer EP Type - * @{ - */ -#define EP_TYPE_CTRL 0U -#define EP_TYPE_ISOC 1U -#define EP_TYPE_BULK 2U -#define EP_TYPE_INTR 3U -#define EP_TYPE_MSK 3U -/** - * @} - */ - -/** @defgroup USB_LL_EP_Speed USB Low Layer EP Speed - * @{ - */ -#define EP_SPEED_LOW 0U -#define EP_SPEED_FULL 1U -#define EP_SPEED_HIGH 2U -/** - * @} - */ - -/** @defgroup USB_LL_CH_PID_Type USB Low Layer Channel PID Type - * @{ - */ -#define HC_PID_DATA0 0U -#define HC_PID_DATA2 1U -#define HC_PID_DATA1 2U -#define HC_PID_SETUP 3U -/** - * @} - */ - -/** @defgroup USB_LL Device Speed - * @{ - */ -#define USBD_HS_SPEED 0U -#define USBD_HSINFS_SPEED 1U -#define USBH_HS_SPEED 0U -#define USBD_FS_SPEED 2U -#define USBH_FSLS_SPEED 1U -/** - * @} - */ - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** @defgroup USB_LL_STS_Defines USB Low Layer STS Defines - * @{ - */ -#define STS_GOUT_NAK 1U -#define STS_DATA_UPDT 2U -#define STS_XFER_COMP 3U -#define STS_SETUP_COMP 4U -#define STS_SETUP_UPDT 6U -/** - * @} - */ - -/** @defgroup USB_LL_HCFG_SPEED_Defines USB Low Layer HCFG Speed Defines - * @{ - */ -#define HCFG_30_60_MHZ 0U -#define HCFG_48_MHZ 1U -#define HCFG_6_MHZ 2U -/** - * @} - */ - -/** @defgroup USB_LL_HFIR_Defines USB Low Layer frame interval Defines - * @{ - */ -#define HFIR_6_MHZ 6000U -#define HFIR_60_MHZ 60000U -#define HFIR_48_MHZ 48000U -/** - * @} - */ - -/** @defgroup USB_LL_HPRT0_PRTSPD_SPEED_Defines USB Low Layer HPRT0 PRTSPD Speed Defines - * @{ - */ -#define HPRT0_PRTSPD_HIGH_SPEED 0U -#define HPRT0_PRTSPD_FULL_SPEED 1U -#define HPRT0_PRTSPD_LOW_SPEED 2U -/** - * @} - */ - -#define HCCHAR_CTRL 0U -#define HCCHAR_ISOC 1U -#define HCCHAR_BULK 2U -#define HCCHAR_INTR 3U - -#define GRXSTS_PKTSTS_IN 2U -#define GRXSTS_PKTSTS_IN_XFER_COMP 3U -#define GRXSTS_PKTSTS_DATA_TOGGLE_ERR 5U -#define GRXSTS_PKTSTS_CH_HALTED 7U - -#define CLEAR_INTERRUPT_MASK 0xFFFFFFFFU - -#define HC_MAX_PKT_CNT 256U -#define ISO_SPLT_MPS 188U - -#define HCSPLT_BEGIN 1U -#define HCSPLT_MIDDLE 2U -#define HCSPLT_END 3U -#define HCSPLT_FULL 4U - -#define TEST_J 1U -#define TEST_K 2U -#define TEST_SE0_NAK 3U -#define TEST_PACKET 4U -#define TEST_FORCE_EN 5U - -#define USBx_PCGCCTL *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_PCGCCTL_BASE) -#define USBx_HPRT0 *(__IO uint32_t *)((uint32_t)USBx_BASE + USB_OTG_HOST_PORT_BASE) - -#define USBx_DEVICE ((USB_OTG_DeviceTypeDef *)(USBx_BASE + USB_OTG_DEVICE_BASE)) -#define USBx_INEP(i) ((USB_OTG_INEndpointTypeDef *)(USBx_BASE\ - + USB_OTG_IN_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) - -#define USBx_OUTEP(i) ((USB_OTG_OUTEndpointTypeDef *)(USBx_BASE\ - + USB_OTG_OUT_ENDPOINT_BASE + ((i) * USB_OTG_EP_REG_SIZE))) - -#define USBx_DFIFO(i) *(__IO uint32_t *)(USBx_BASE + USB_OTG_FIFO_BASE + ((i) * USB_OTG_FIFO_SIZE)) - -#define USBx_HOST ((USB_OTG_HostTypeDef *)(USBx_BASE + USB_OTG_HOST_BASE)) -#define USBx_HC(i) ((USB_OTG_HostChannelTypeDef *)(USBx_BASE\ - + USB_OTG_HOST_CHANNEL_BASE\ - + ((i) * USB_OTG_HOST_CHANNEL_SIZE))) - - -#define EP_ADDR_MSK 0xFU -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined (USB_DRD_FS) -#define EP_ADDR_MSK 0x7U - -#ifndef USE_USB_DOUBLE_BUFFER -#define USE_USB_DOUBLE_BUFFER 1U -#endif /* USE_USB_DOUBLE_BUFFER */ - -#define USB_EMBEDDED_PHY 2U - -/*!< USB Speed */ -#define USB_DRD_SPEED_FS 1U -#define USB_DRD_SPEED_LS 2U -#define USB_DRD_SPEED_LSFS 3U - -/*!< Channel Direction */ -#define CH_IN_DIR 1U -#define CH_OUT_DIR 0U - -/*!< Number of used channels in the Application */ -#ifndef USB_DRD_USED_CHANNELS -#define USB_DRD_USED_CHANNELS 8U -#endif /* USB_DRD_USED_CHANNELS */ - -/** - * used for USB_HC_DoubleBuffer API - */ -#define USB_DRD_BULK_DBUFF_ENBALE 1U -#define USB_DRD_BULK_DBUFF_DISABLE 2U -#define USB_DRD_ISOC_DBUFF_ENBALE 3U -#define USB_DRD_ISOC_DBUFF_DISABLE 4U - -/* First available address in PMA */ -#define PMA_START_ADDR (0x10U + (8U *(USB_DRD_USED_CHANNELS - 2U))) -#define PMA_END_ADDR USB_DRD_PMA_SIZE - -/* Exported macro ------------------------------------------------------------*/ -/** - * @} - */ -/******************** Bit definition for USB_COUNTn_RX register *************/ -#define USB_CNTRX_NBLK_MSK (0x1FU << 26) -#define USB_CNTRX_BLSIZE (0x1U << 31) - - -/*Set Channel/Endpoint to the USB Register */ -#define USB_DRD_SET_CHEP(USBx, bEpChNum, wRegValue) (*(__IO uint32_t *)\ - (&(USBx)->CHEP0R + (bEpChNum)) = (uint32_t)(wRegValue)) - -/*Get Channel/Endpoint from the USB Register */ -#define USB_DRD_GET_CHEP(USBx, bEpChNum) (*(__IO uint32_t *)(&(USBx)->CHEP0R + (bEpChNum))) - - -/** - * @brief free buffer used from the application realizing it to the line - * toggles bit SW_BUF in the double buffered endpoint register - * @param USBx USB device. - * @param bEpChNum, bDir - * @retval None - */ -#define USB_DRD_FREE_USER_BUFFER(USBx, bEpChNum, bDir) \ - do { \ - if ((bDir) == 0U) \ - { \ - /* OUT double buffered endpoint */ \ - USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ - } \ - else if ((bDir) == 1U) \ - { \ - /* IN double buffered endpoint */ \ - USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ - } \ - } while(0) - - -/** - * @brief Set the Setup bit in the corresponding channel, when a Setup - transaction is needed. - * @param USBx USB device. - * @param bEpChNum - * @retval None - */ -#define USB_DRD_CHEP_TX_SETUP(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) ; \ - \ - /* Set Setup bit */ \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_SETUP)); \ - } while(0) - - -/** - * @brief Clears bit ERR_RX in the Channel register - * @param USBx USB peripheral instance register address. - * @param bChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_CLEAR_CHEP_RX_ERR(USBx, bChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ - _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRRX) & (~USB_CHEP_VTRX)) | \ - (USB_CHEP_VTTX | USB_CHEP_ERRTX); \ - \ - USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ - } while(0) /* USB_DRD_CLEAR_CHEP_RX_ERR */ - - -/** - * @brief Clears bit ERR_TX in the Channel register - * @param USBx USB peripheral instance register address. - * @param bChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_CLEAR_CHEP_TX_ERR(USBx, bChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bChNum)); \ - _wRegVal = (_wRegVal & USB_CHEP_REG_MASK & (~USB_CHEP_ERRTX) & (~USB_CHEP_VTTX)) | \ - (USB_CHEP_VTRX|USB_CHEP_ERRRX); \ - \ - USB_DRD_SET_CHEP((USBx), (bChNum), _wRegVal); \ - } while(0) /* USB_DRD_CLEAR_CHEP_TX_ERR */ - - -/** - * @brief sets the status for tx transfer (bits STAT_TX[1:0]). - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param wState new state - * @retval None - */ -#define USB_DRD_SET_CHEP_TX_STATUS(USBx, bEpChNum, wState) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_TX_DTOGMASK; \ - /* toggle first bit ? */ \ - if ((USB_CHEP_TX_DTOG1 & (wState)) != 0U) \ - { \ - _wRegVal ^= USB_CHEP_TX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if ((USB_CHEP_TX_DTOG2 & (wState)) != 0U) \ - { \ - _wRegVal ^= USB_CHEP_TX_DTOG2; \ - } \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX| USB_CHEP_VTTX)); \ - } while(0) /* USB_DRD_SET_CHEP_TX_STATUS */ - - -/** - * @brief sets the status for rx transfer (bits STAT_TX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param wState new state - * @retval None - */ -#define USB_DRD_SET_CHEP_RX_STATUS(USBx, bEpChNum, wState) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_RX_DTOGMASK; \ - /* toggle first bit ? */ \ - if ((USB_CHEP_RX_DTOG1 & (wState)) != 0U) \ - { \ - _wRegVal ^= USB_CHEP_RX_DTOG1; \ - } \ - /* toggle second bit ? */ \ - if ((USB_CHEP_RX_DTOG2 & (wState)) != 0U) \ - { \ - _wRegVal ^= USB_CHEP_RX_DTOG2; \ - } \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ - } while(0) /* USB_DRD_SET_CHEP_RX_STATUS */ - - -/** - * @brief gets the status for tx/rx transfer (bits STAT_TX[1:0] - * /STAT_RX[1:0]) - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval status - */ -#define USB_DRD_GET_CHEP_TX_STATUS(USBx, bEpChNum) \ - ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_TX_STTX) - -#define USB_DRD_GET_CHEP_RX_STATUS(USBx, bEpChNum) \ - ((uint16_t)USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_DRD_CHEP_RX_STRX) - - -/** - * @brief set EP_KIND bit. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_SET_CHEP_KIND(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ - \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_KIND)); \ - } while(0) /* USB_DRD_SET_CHEP_KIND */ - - -/** - * @brief clear EP_KIND bit. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_CLEAR_CHEP_KIND(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_EP_KIND_MASK; \ - \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ - } while(0) /* USB_DRD_CLEAR_CHEP_KIND */ - - -/** - * @brief Clears bit CTR_RX / CTR_TX in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_CLEAR_RX_CHEP_CTR(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFF7FFFU & USB_CHEP_REG_MASK); \ - \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTTX)); \ - } while(0) /* USB_CLEAR_RX_CHEP_CTR */ - -#define USB_DRD_CLEAR_TX_CHEP_CTR(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & (0xFFFFFF7FU & USB_CHEP_REG_MASK); \ - \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX)); \ - } while(0) /* USB_CLEAR_TX_CHEP_CTR */ - - -/** - * @brief Toggles DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_RX_DTOG(USBx, bEpChNum) \ - do { \ - uint32_t _wEPVal; \ - \ - _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ - \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX)); \ - } while(0) /* USB_DRD_RX_DTOG */ - -#define USB_DRD_TX_DTOG(USBx, bEpChNum) \ - do { \ - uint32_t _wEPVal; \ - \ - _wEPVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK; \ - \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wEPVal | USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX)); \ - } while(0) /* USB_TX_DTOG */ - - -/** - * @brief Clears DTOG_RX / DTOG_TX bit in the endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_CLEAR_RX_DTOG(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ - \ - if ((_wRegVal & USB_CHEP_DTOG_RX) != 0U) \ - { \ - USB_DRD_RX_DTOG((USBx), (bEpChNum)); \ - } \ - } while(0) /* USB_DRD_CLEAR_RX_DTOG */ - -#define USB_DRD_CLEAR_TX_DTOG(USBx, bEpChNum) \ - do { \ - uint32_t _wRegVal; \ - \ - _wRegVal = USB_DRD_GET_CHEP((USBx), (bEpChNum)); \ - \ - if ((_wRegVal & USB_CHEP_DTOG_TX) != 0U) \ - { \ - USB_DRD_TX_DTOG((USBx), (bEpChNum)); \ - } \ - } while(0) /* USB_DRD_CLEAR_TX_DTOG */ - - -/** - * @brief Sets address in an endpoint register. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param bAddr Address. - * @retval None - */ -#define USB_DRD_SET_CHEP_ADDRESS(USBx, bEpChNum, bAddr) \ - do { \ - uint32_t _wRegVal; \ - \ - /*Read the USB->CHEPx into _wRegVal, Reset(DTOGRX/STRX/DTOGTX/STTX) and set the EpAddress*/ \ - _wRegVal = (USB_DRD_GET_CHEP((USBx), (bEpChNum)) & USB_CHEP_REG_MASK) | (bAddr); \ - \ - /*Set _wRegVal in USB->CHEPx and set Transmit/Receive Valid Transfer (x=bEpChNum)*/ \ - USB_DRD_SET_CHEP((USBx), (bEpChNum), (_wRegVal | USB_CHEP_VTRX | USB_CHEP_VTTX)); \ - } while(0) /* USB_DRD_SET_CHEP_ADDRESS */ - - -/* PMA API Buffer Descriptor Management ------------------------------------------------------------*/ -/* Buffer Descriptor Table TXBD0/RXBD0 --- > TXBD7/RXBD7 8 possible descriptor -* The buffer descriptor is located inside the packet buffer memory (USB_PMA_BUFF) -* TXBD [Reserve |Countx| Address_Tx] -* RXBD [BLSIEZ|NUM_Block |CounRx| Address_Rx] */ - -/* Set TX Buffer Descriptor Address Field */ -#define USB_DRD_SET_CHEP_TX_ADDRESS(USBx, bEpChNum, wAddr) \ - do { \ - /* Reset old Address */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_ADDMSK; \ - \ - /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ - } while(0) /* USB_DRD_SET_CHEP_TX_ADDRESS */ - -/* Set RX Buffer Descriptor Address Field */ -#define USB_DRD_SET_CHEP_RX_ADDRESS(USBx, bEpChNum, wAddr) \ - do { \ - /* Reset old Address */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_RXBD_ADDMSK; \ - \ - /* Bit0 & Bit1 should be =0 PMA must be Word aligned */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)(((uint32_t)(wAddr) >> 2U) << 2U); \ - } while(0) /* USB_SET_CHEP_RX_ADDRESS */ - - -/** - * @brief Sets counter of rx buffer with no. of blocks. - * @param pdwReg Register pointer - * @param wCount Counter. - * @param wNBlocks no. of Blocks. - * @retval None - */ -#define USB_DRD_CALC_BLK32(pdwReg, wCount, wNBlocks) \ - do { \ - /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ - (wNBlocks) =((uint32_t)(wCount) >> 5U); \ - if (((uint32_t)(wCount) % 32U) == 0U) \ - { \ - (wNBlocks)--; \ - } \ - \ - (pdwReg)|= (uint32_t)((((wNBlocks) << 26U)) | USB_CNTRX_BLSIZE); \ - } while(0) /* USB_DRD_CALC_BLK32 */ - -#define USB_DRD_CALC_BLK2(pdwReg, wCount, wNBlocks) \ - do { \ - /* Divide PacketSize by 32 to calculate the Nb of Block32 */ \ - (wNBlocks) = (uint32_t)((uint32_t)(wCount) >> 1U); \ - if (((wCount) & 0x1U) != 0U) \ - { \ - (wNBlocks)++; \ - } \ - (pdwReg) |= (uint32_t)((wNBlocks) << 26U); \ - } while(0) /* USB_DRD_CALC_BLK2 */ - -#define USB_DRD_SET_CHEP_CNT_RX_REG(pdwReg, wCount) \ - do { \ - uint32_t wNBlocks; \ - \ - (pdwReg) &= ~(USB_CNTRX_BLSIZE | USB_CNTRX_NBLK_MSK); \ - \ - if ((wCount) == 0U) \ - { \ - (pdwReg) |= USB_CNTRX_BLSIZE; \ - } \ - else if ((wCount) <= 62U) \ - { \ - USB_DRD_CALC_BLK2((pdwReg), (wCount), wNBlocks); \ - } \ - else \ - { \ - USB_DRD_CALC_BLK32((pdwReg), (wCount), wNBlocks); \ - } \ - } while(0) /* USB_DRD_SET_CHEP_CNT_RX_REG */ - - -/** - * @brief sets counter for the tx/rx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param wCount Counter value. - * @retval None - */ -#define USB_DRD_SET_CHEP_TX_CNT(USBx,bEpChNum, wCount) \ - do { \ - /* Reset old TX_Count value */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD &= USB_PMA_TXBD_COUNTMSK; \ - \ - /* Set the wCount in the dedicated EP_TXBuffer */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->TXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ - } while(0) - -#define USB_DRD_SET_CHEP_RX_DBUF0_CNT(USBx, bEpChNum, wCount) \ - USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD), (wCount)) - -#define USB_DRD_SET_CHEP_RX_CNT(USBx, bEpChNum, wCount) \ - USB_DRD_SET_CHEP_CNT_RX_REG(((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD), (wCount)) - -/** - * @brief gets counter of the tx buffer. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval Counter value - */ -#define USB_DRD_GET_CHEP_TX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->TXBD & 0x03FF0000U) >> 16U) -#define USB_DRD_GET_CHEP_RX_CNT(USBx, bEpChNum) (((USB_DRD_PMA_BUFF + (bEpChNum))->RXBD & 0x03FF0000U) >> 16U) - -#define USB_DRD_GET_EP_TX_CNT USB_GET_CHEP_TX_CNT -#define USB_DRD_GET_CH_TX_CNT USB_GET_CHEP_TX_CNT - -#define USB_DRD_GET_EP_RX_CNT USB_DRD_GET_CHEP_RX_CNT -#define USB_DRD_GET_CH_RX_CNT USB_DRD_GET_CHEP_RX_CNT -/** - * @brief Sets buffer 0/1 address in a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param wBuf0Addr buffer 0 address. - * @retval Counter value - */ -#define USB_DRD_SET_CHEP_DBUF0_ADDR(USBx, bEpChNum, wBuf0Addr) \ - USB_DRD_SET_CHEP_TX_ADDRESS((USBx), (bEpChNum), (wBuf0Addr)) - -#define USB_DRD_SET_CHEP_DBUF1_ADDR(USBx, bEpChNum, wBuf1Addr) \ - USB_DRD_SET_CHEP_RX_ADDRESS((USBx), (bEpChNum), (wBuf1Addr)) - - -/** - * @brief Sets addresses in a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param wBuf0Addr: buffer 0 address. - * @param wBuf1Addr = buffer 1 address. - * @retval None - */ -#define USB_DRD_SET_CHEP_DBUF_ADDR(USBx, bEpChNum, wBuf0Addr, wBuf1Addr) \ - do { \ - USB_DRD_SET_CHEP_DBUF0_ADDR((USBx), (bEpChNum), (wBuf0Addr)); \ - USB_DRD_SET_CHEP_DBUF1_ADDR((USBx), (bEpChNum), (wBuf1Addr)); \ - } while(0) /* USB_DRD_SET_CHEP_DBUF_ADDR */ - - -/** - * @brief Gets buffer 0/1 address of a double buffer endpoint. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @param bDir endpoint dir EP_DBUF_OUT = OUT - * EP_DBUF_IN = IN - * @param wCount: Counter value - * @retval None - */ -#define USB_DRD_SET_CHEP_DBUF0_CNT(USBx, bEpChNum, bDir, wCount) \ - do { \ - if ((bDir) == 0U) \ - { \ - /* OUT endpoint */ \ - USB_DRD_SET_CHEP_RX_DBUF0_CNT((USBx), (bEpChNum), (wCount)); \ - } \ - else \ - { \ - if ((bDir) == 1U) \ - { \ - /* IN endpoint */ \ - USB_DRD_SET_CHEP_TX_CNT((USBx), (bEpChNum), (wCount)); \ - } \ - } \ - } while(0) /* USB_DRD_SET_CHEP_DBUF0_CNT */ - -#define USB_DRD_SET_CHEP_DBUF1_CNT(USBx, bEpChNum, bDir, wCount) \ - do { \ - if ((bDir) == 0U) \ - { \ - /* OUT endpoint */ \ - USB_DRD_SET_CHEP_RX_CNT((USBx), (bEpChNum), (wCount)); \ - } \ - else \ - { \ - if ((bDir) == 1U) \ - { \ - /* IN endpoint */ \ - (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD &= USB_PMA_TXBD_COUNTMSK; \ - (USB_DRD_PMA_BUFF + (bEpChNum))->RXBD |= (uint32_t)((uint32_t)(wCount) << 16U); \ - } \ - } \ - } while(0) /* USB_DRD_SET_CHEP_DBUF1_CNT */ - -#define USB_DRD_SET_CHEP_DBUF_CNT(USBx, bEpChNum, bDir, wCount) \ - do { \ - USB_DRD_SET_CHEP_DBUF0_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ - USB_DRD_SET_CHEP_DBUF1_CNT((USBx), (bEpChNum), (bDir), (wCount)); \ - } while(0) /* USB_DRD_SET_EPCH_DBUF_CNT */ - -/** - * @brief Gets buffer 0/1 rx/tx counter for double buffering. - * @param USBx USB peripheral instance register address. - * @param bEpChNum Endpoint Number. - * @retval None - */ -#define USB_DRD_GET_CHEP_DBUF0_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_TX_CNT((USBx), (bEpChNum))) -#define USB_DRD_GET_CHEP_DBUF1_CNT(USBx, bEpChNum) (USB_DRD_GET_CHEP_RX_CNT((USBx), (bEpChNum))) -#endif /* defined (USB_DRD_FS) */ -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USB_LL_Exported_Macros USB Low Layer Exported Macros - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -#define USB_MASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK &= ~(__INTERRUPT__)) -#define USB_UNMASK_INTERRUPT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->GINTMSK |= (__INTERRUPT__)) - -#define CLEAR_IN_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_INEP(__EPNUM__)->DIEPINT = (__INTERRUPT__)) -#define CLEAR_OUT_EP_INTR(__EPNUM__, __INTERRUPT__) (USBx_OUTEP(__EPNUM__)->DOEPINT = (__INTERRUPT__)) -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USB_LL_Exported_Functions USB Low Layer Exported Functions - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, uint32_t hclk, uint8_t speed); -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode); -HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed); -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num); -HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma); -HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, - uint8_t ch_ep_num, uint16_t len, uint8_t dma); - -void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len); -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep); -HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup); -uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum); -uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx); -uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum); -void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt); - -HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg); -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq); -HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state); -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx); -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, - uint8_t epnum, uint8_t dev_address, uint8_t speed, - uint8_t ep_type, uint16_t mps); -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, - USB_OTG_HCTypeDef *hc, uint8_t dma); - -uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num); -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num); -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); -HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); -HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode); - -HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx); -HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num); - -#if defined (HAL_PCD_MODULE_ENABLED) -HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep); -#endif /* defined (HAL_PCD_MODULE_ENABLED) */ - -HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address); -HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx); -uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx); - -HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg); -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch); -HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc); - -uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx); -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx); -HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t db_state); -HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, uint8_t epnum, - uint8_t dev_address, uint8_t speed, uint8_t ep_type, uint16_t mps); - -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx); -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx); - -void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, - uint16_t wPMABufAddr, uint16_t wNBytes); - -void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, - uint16_t wPMABufAddr, uint16_t wNBytes); -#endif /* defined (USB_DRD_FS) */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ - -#ifdef __cplusplus -} -#endif /* __cplusplus */ - - -#endif /* STM32U5xx_LL_USB_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h deleted file mode 100644 index 88e5b2dec..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Inc/stm32u5xx_ll_utils.h +++ /dev/null @@ -1,356 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_utils.h - * @author MCD Application Team - * @brief Header file of UTILS LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The LL UTILS driver contains a set of generic APIs that can be - used by user: - (+) Device electronic signature - (+) Timing functions - (+) PLL configuration functions - - @endverbatim - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32U5xx_LL_UTILS_H -#define __STM32U5xx_LL_UTILS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -/** @defgroup UTILS_LL UTILS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Constants UTILS Private Constants - * @{ - */ - -/* Max delay can be used in LL_mDelay */ -#define LL_MAX_DELAY 0xFFFFFFFFU - -/** - * @brief Unique device ID register base address - */ -#define UID_BASE_ADDRESS UID_BASE - -/** - * @brief Flash size data register base address - */ -#define FLASHSIZE_BASE_ADDRESS FLASHSIZE_BASE - -/** - * @brief Package data register base address - */ -#define PACKAGE_BASE_ADDRESS PACKAGE_BASE - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Macros UTILS Private Macros - * @{ - */ -/** - * @} - */ -/* Exported types ------------------------------------------------------------*/ -/** @defgroup UTILS_LL_ES_INIT UTILS Exported structures - * @{ - */ - -/** - * @brief UTILS PLL structure definition - */ -typedef struct -{ - uint32_t PLLM; /*!< Division factor for PLL VCO input clock. - This parameter can be a value of @ref RCC_LL_EC_PLL1MBOOST_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ - - uint32_t PLLN; /*!< Multiplication factor for PLL VCO output clock. - This parameter must be a number between Min_Data = 8 and Max_Data = 86 - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ - - uint32_t PLLR; /*!< Division for the main system clock. - This parameter must be a number between Min_Data = 1 and Max_Data = 128 - - This feature can be modified afterwards using unitary function - @ref LL_RCC_PLL1_ConfigDomain_SYS(). */ -} LL_UTILS_PLLInitTypeDef; - -/** - * @brief UTILS System, AHB and APB buses clock configuration structure definition - */ -typedef struct -{ - uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK). - This parameter can be a value of @ref RCC_LL_EC_SYSCLK_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAHBPrescaler(). */ - - uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB1_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB1Prescaler(). */ - - uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB2_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB2Prescaler(). */ - - uint32_t APB3CLKDivider; /*!< The APB3 clock (PCLK3) divider. This clock is derived from the AHB clock (HCLK). - This parameter can be a value of @ref RCC_LL_EC_APB3_DIV - - This feature can be modified afterwards using unitary function - @ref LL_RCC_SetAPB3Prescaler(). */ - -} LL_UTILS_ClkInitTypeDef; - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Constants UTILS Exported Constants - * @{ - */ - -/** @defgroup UTILS_EC_HSE_BYPASS HSE Bypass activation - * @{ - */ -#define LL_UTILS_HSEBYPASS_OFF 0x00000000U /*!< HSE Bypass is not enabled */ -#define LL_UTILS_HSEBYPASS_ON 0x00000001U /*!< HSE Bypass is enabled */ -/** - * @} - */ - -/** @defgroup UTILS_EC_PACKAGETYPE PACKAGE TYPE - * @{ - */ -#define LL_UTILS_PACKAGETYPE_LQFP64 0x00000000U /*!< LQFP64 package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP72_SMPS 0x00000001U /*!< WLCSP72 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100 0x00000002U /*!< LQFP100 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA132 0x00000003U /*!< UFBGA132 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144 0x00000004U /*!< LQFP144 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48 0x00000005U /*!< LQFP48 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169 0x00000007U /*!< UFBGA169 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP64_SMPS 0x00000008U /*!< LQFP64 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLSCP90_SMPS 0x00000009U /*!< WLSCP90 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100_SMPS 0x0000000AU /*!< LQFP100 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA132_SMPS 0x0000000BU /*!< UFBGA132 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_SMPS 0x0000000CU /*!< LQFP144 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP48_SMPS 0x0000000DU /*!< LQFP48 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA169_SMPS 0x0000000FU /*!< UFBGA169 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA64 0x00000012U /*!< UFBGA64 package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA100 0x00000013U /*!< UFBGA100 package type */ -#define LL_UTILS_PACKAGETYPE_LQFP100_DSI_SMPS 0x00000014U /*!< LQFP100 DSI with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_LQFP144_DSI_SMPS 0x00000015U /*!< LQFP144 DSI with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA144_SMPS 0x00000019U /*!< UFBGA144 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP208_SMPS 0x0000001BU /*!< WLCSP208 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_TFBGA216_SMPS 0x0000001CU /*!< TFBGA216 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_UFBGA100_SMPS 0x0000001DU /*!< UFBGA100 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP56_SMPS 0x0000001EU /*!< WLCSP56 with internal SMPS package type */ -#define LL_UTILS_PACKAGETYPE_WLCSP150_SMPS 0x0000001FU /*!< WLCSP150 or WLCSP150 DSI with internal package type */ - -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup UTILS_LL_Exported_Functions UTILS Exported Functions - * @{ - */ - -/** @defgroup UTILS_EF_DEVICE_ELECTRONIC_SIGNATURE DEVICE ELECTRONIC SIGNATURE - * @{ - */ - -/** - * @brief Get Word0 of the unique device identifier (UID based on 96 bits) - * @retval UID[31:0]: X and Y coordinates on the wafer expressed in BCD format - */ -__STATIC_INLINE uint32_t LL_GetUID_Word0(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)UID_BASE_ADDRESS))); -} - -/** - * @brief Get Word1 of the unique device identifier (UID based on 96 bits) - * @retval UID[63:32]: Wafer number (UID[39:32]) & LOT_NUM[23:0] (UID[63:40]) - */ -__STATIC_INLINE uint32_t LL_GetUID_Word1(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 4U)))); -} - -/** - * @brief Get Word2 of the unique device identifier (UID based on 96 bits) - * @retval UID[95:64]: Lot number (ASCII encoded) - LOT_NUM[55:24] - */ -__STATIC_INLINE uint32_t LL_GetUID_Word2(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)(UID_BASE_ADDRESS + 8U)))); -} - -/** - * @brief Get Flash memory size - * @note This bitfield indicates the size of the device Flash memory expressed in - * Kbytes. As an example, 0x040 corresponds to 64 Kbytes. - * @retval FLASH_SIZE[15:0]: Flash memory size - */ -__STATIC_INLINE uint32_t LL_GetFlashSize(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU); -} - -/** - * @brief Get Package type - * @retval Returned value can be one of the following values: - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64 - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100 - * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132 - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144 - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48 - * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169 - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP64_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_WLSCP90_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP100_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA132_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP144_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_LQFP48_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA169_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144 - * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144 - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP144_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_UFBGA144_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_WLCSP208_SMPS - * @arg @ref LL_UTILS_PACKAGETYPE_TFBGA216_SMPS - */ -__STATIC_INLINE uint32_t LL_GetPackageType(void) -{ - return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x1FU); -} - -/** - * @} - */ - -/** @defgroup UTILS_LL_EF_DELAY DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source of the time base. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @note When a RTOS is used, it is recommended to avoid changing the SysTick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks - * @retval None - */ -__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks) -{ - /* Configure the SysTick to have interrupt in 1ms time base */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / Ticks) - 1UL); /* set reload register */ - SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk; /* Enable the Systick Timer */ -} - -void LL_Init1msTick(uint32_t HCLKFrequency); -void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency); -void LL_Init1msTick_LSE(void); -void LL_Init1msTick_LSI(void); -void LL_mDelay(uint32_t Delay); - -/** - * @} - */ - -/** @defgroup LL_UTILS_Aliased_Functions LL UTILS Aliased Functions maintained for legacy purpose - * @{ - */ -#define LL_PLL1_ConfigSystemClock_MSI LL_PLL_ConfigSystemClock_MSI /* for legacy purpose */ -#define LL_PLL1_ConfigSystemClock_HSI LL_PLL_ConfigSystemClock_HSI /* for legacy purpose */ -#define LL_PLL1_ConfigSystemClock_HSE LL_PLL_ConfigSystemClock_HSE /* for legacy purpose */ -/** - * @} - */ - -/** @defgroup UTILS_EF_SYSTEM SYSTEM - * @{ - */ - -void LL_SetSystemCoreClock(uint32_t HCLKFrequency); -ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency); -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32U5xx_LL_UTILS_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.md b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.md deleted file mode 100644 index 9226612ae..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.md +++ /dev/null @@ -1,27 +0,0 @@ -Copyright 2021 STMicroelectronics. -All rights reserved. - -Redistribution and use in source and binary forms, with or without modification, -are permitted provided that the following conditions are met: - -1. Redistributions of source code must retain the above copyright notice, this -list of conditions and the following disclaimer. - -2. Redistributions in binary form must reproduce the above copyright notice, -this list of conditions and the following disclaimer in the documentation and/or -other materials provided with the distribution. - -3. Neither the name of the copyright holder nor the names of its contributors -may be used to endorse or promote products derived from this software without -specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt deleted file mode 100644 index 3edc4d146..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/LICENSE.txt +++ /dev/null @@ -1,6 +0,0 @@ -This software component is provided to you as part of a software package and -applicable license terms are in the Package_license file. If you received this -software component outside of a package or without applicable license terms, -the terms of the BSD-3-Clause license shall apply. -You may obtain a copy of the BSD-3-Clause at: -https://opensource.org/licenses/BSD-3-Clause diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c deleted file mode 100644 index 512e1441e..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal.c +++ /dev/null @@ -1,1057 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal.c - * @author MCD Application Team - * @brief HAL module driver. - * This is the common part of the HAL initialization - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The common HAL driver contains a set of generic and common APIs that can be - used by the PPP peripheral drivers and the user to start using the HAL. - [..] - The HAL contains two APIs' categories: - (+) Common HAL APIs - (+) Services HAL APIs - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup HAL HAL - * @brief HAL module driver - * @{ - */ - -#ifdef HAL_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup HAL_Private_Defines HAL Private Defines - * @{ - */ -/** - * @brief STM32U5xx HAL Driver version number 1.5.0 - */ -#define __STM32U5xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __STM32U5xx_HAL_VERSION_SUB1 (0x05U) /*!< [23:16] sub1 version */ -#define __STM32U5xx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __STM32U5xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define __STM32U5xx_HAL_VERSION ((__STM32U5xx_HAL_VERSION_MAIN << 24U)\ - |(__STM32U5xx_HAL_VERSION_SUB1 << 16U)\ - |(__STM32U5xx_HAL_VERSION_SUB2 << 8U )\ - |(__STM32U5xx_HAL_VERSION_RC)) - -#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms (to be confirmed) */ -/** - * @} - */ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Exported variables --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Variables HAL Exported Variables - * @{ - */ -__IO uint32_t uwTick; -uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */ -HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup HAL_Exported_Functions HAL Exported Functions - * @{ - */ - -/** @defgroup HAL_Exported_Functions_Group1 HAL Initialization and de-initialization Functions - * @brief Initialization and de-initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initializes the Flash interface the NVIC allocation and initial clock - configuration. It initializes the systick also when timeout is needed - and the backup domain when enabled. - (+) De-Initializes common part of the HAL. - (+) Configure The time base source to have 1ms time base with a dedicated - Tick interrupt priority. - (++) SysTick timer is used by default as source of time base, but user - can eventually implement his proper time base source (a general purpose - timer for example or other time source), keeping in mind that Time base - duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and - handled in milliseconds basis. - (++) Time base configuration function (HAL_InitTick ()) is called automatically - at the beginning of the program after reset by HAL_Init() or at any time - when clock is configured, by HAL_RCC_ClockConfig(). - (++) Source of time base is configured to generate interrupts at regular - time intervals. Care must be taken if HAL_Delay() is called from a - peripheral ISR process, the Tick interrupt line must have higher priority - (numerically lower) than the peripheral interrupt. Otherwise the caller - ISR process will be blocked. - (++) functions affecting time base configurations are declared as __weak - to make override possible in case of other implementations in user file. -@endverbatim - * @{ - */ - -/** - * @brief Configure the Flash prefetch, the time base source, NVIC and any required global low - * level hardware by calling the HAL_MspInit() callback function to be optionally defined - * in user file stm32u5xx_hal_msp.c. - * - * @note HAL_Init() function is called at the beginning of program after reset and before - * the clock configuration. - * - * @note In the default implementation the System Timer (SysTick) is used as source of time base. - * The SysTick configuration is based on MSI clock, as MSI is the clock - * used after a system Reset and the NVIC configuration is set to Priority group 4. - * Once done, time base tick starts incrementing: the tick variable counter is incremented - * each 1ms in the SysTick_Handler() interrupt handler. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_Init(void) -{ - /* Configure Flash prefetch */ -#if (PREFETCH_ENABLE != 0U) - __HAL_FLASH_PREFETCH_BUFFER_ENABLE(); -#endif /* PREFETCH_ENABLE */ - - /* Set Interrupt Group Priority */ - HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; - - /* Select HCLK as SysTick clock source */ - HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK); - - /* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */ - if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) - { - return HAL_ERROR; - } - - /* Init the low level hardware */ - HAL_MspInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief This function de-Initializes common part of the HAL and stops the systick. - * This function is optional. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DeInit(void) -{ - /* Reset of all peripherals */ - __HAL_RCC_APB1_FORCE_RESET(); - __HAL_RCC_APB1_RELEASE_RESET(); - - __HAL_RCC_APB2_FORCE_RESET(); - __HAL_RCC_APB2_RELEASE_RESET(); - - __HAL_RCC_AHB1_FORCE_RESET(); - __HAL_RCC_AHB1_RELEASE_RESET(); - - __HAL_RCC_AHB2_FORCE_RESET(); - __HAL_RCC_AHB2_RELEASE_RESET(); - - __HAL_RCC_AHB3_FORCE_RESET(); - __HAL_RCC_AHB3_RELEASE_RESET(); - - /* De-Init the low level hardware */ - HAL_MspDeInit(); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Initializes the MSP. - * @retval None - */ -__weak void HAL_MspInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes the MSP. - * @retval None - */ -__weak void HAL_MspDeInit(void) -{ - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief This function configures the source of the time base. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is reconfigured by HAL_RCC_ClockConfig(). - * @note In the default implementation, SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals. - * Care must be taken if HAL_Delay() is called from a peripheral ISR process, - * The SysTick interrupt must have higher priority (numerically lower) - * than the peripheral interrupt. Otherwise the caller ISR process will be blocked. - * The function is declared as __weak to be overwritten in case of other - * implementation in user file. - * @param TickPriority: Tick interrupt priority. - * @retval HAL status - */ -__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - uint32_t ticknumber = 0U; - uint32_t systicksel; - - /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ - if ((uint32_t)uwTickFreq == 0UL) - { - return HAL_ERROR; - } - - /* Check Clock source to calculate the tickNumber */ - if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) == SysTick_CTRL_CLKSOURCE_Msk) - { - /* HCLK selected as SysTick clock source */ - ticknumber = SystemCoreClock / (1000UL / (uint32_t)uwTickFreq); - } - else - { - systicksel = HAL_SYSTICK_GetCLKSourceConfig(); - switch (systicksel) - { - /* HCLK_DIV8 selected as SysTick clock source */ - case SYSTICK_CLKSOURCE_HCLK_DIV8: - /* Calculate tick value */ - ticknumber = (SystemCoreClock / (8000UL / (uint32_t)uwTickFreq)); - break; - /* LSI selected as SysTick clock source */ - case SYSTICK_CLKSOURCE_LSI: - /* Calculate tick value */ - ticknumber = (LSI_VALUE / (1000UL / (uint32_t)uwTickFreq)); - break; - /* LSE selected as SysTick clock source */ - case SYSTICK_CLKSOURCE_LSE: - /* Calculate tick value */ - ticknumber = (LSE_VALUE / (1000UL / (uint32_t)uwTickFreq)); - break; - default: - /* Nothing to do */ - break; - } - } - - /* Configure the SysTick to have interrupt in 1ms time basis*/ - if (HAL_SYSTICK_Config(ticknumber) > 0U) - { - return HAL_ERROR; - } - - /* Configure the SysTick IRQ priority */ - HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions - * @brief HAL Control functions - * -@verbatim - =============================================================================== - ##### HAL Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Provide a tick value in millisecond - (+) Provide a blocking delay in millisecond - (+) Suspend the time base source interrupt - (+) Resume the time base source interrupt - (+) Get the HAL API driver version - (+) Get the device identifier - (+) Get the device revision identifier - (+) Enable/Disable Debug module during SLEEP mode - (+) Enable/Disable Debug module during STOP mode - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief This function is called to increment a global variable "uwTick" - * used as application time base. - * @note In the default implementation, this variable is incremented each 1ms - * in SysTick ISR. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_IncTick(void) -{ - uwTick += (uint32_t)uwTickFreq; -} - -/** - * @brief Provides a tick value in millisecond. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval tick value - */ -__weak uint32_t HAL_GetTick(void) -{ - return uwTick; -} - -/** - * @brief This function returns a tick priority. - * @retval tick priority - */ -uint32_t HAL_GetTickPrio(void) -{ - return uwTickPrio; -} - -/** - * @brief Set new tick Freq. - * @retval Status - */ -HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq) -{ - HAL_StatusTypeDef status = HAL_OK; - assert_param(IS_TICKFREQ(Freq)); - - if (uwTickFreq != Freq) - { - /* Apply the new tick Freq */ - status = HAL_InitTick(uwTickPrio); - - if (status == HAL_OK) - { - uwTickFreq = Freq; - } - } - - return status; -} - -/** - * @brief Return tick frequency. - * @retval Tick frequency. - * Value of @ref HAL_TickFreqTypeDef. - */ -HAL_TickFreqTypeDef HAL_GetTickFreq(void) -{ - return uwTickFreq; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on variable incremented. - * @note In the default implementation , SysTick timer is the source of time base. - * It is used to generate interrupts at regular time intervals where uwTick - * is incremented. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -__weak void HAL_Delay(uint32_t Delay) -{ - uint32_t tickstart = HAL_GetTick(); - uint32_t wait = Delay; - - /* Add a freq to guarantee minimum wait */ - if (wait < HAL_MAX_DELAY) - { - wait += (uint32_t)(uwTickFreq); - } - - while ((HAL_GetTick() - tickstart) < wait) - { - } -} - -/** - * @brief Suspend Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_SuspendTick() - * is called, the SysTick interrupt will be disabled and so Tick increment - * is suspended. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_SuspendTick(void) -{ - /* Disable SysTick Interrupt */ - SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Resume Tick increment. - * @note In the default implementation , SysTick timer is the source of time base. It is - * used to generate interrupts at regular time intervals. Once HAL_ResumeTick() - * is called, the SysTick interrupt will be enabled and so Tick increment - * is resumed. - * @note This function is declared as __weak to be overwritten in case of other - * implementations in user file. - * @retval None - */ -__weak void HAL_ResumeTick(void) -{ - /* Enable SysTick Interrupt */ - SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; -} - -/** - * @brief Returns the HAL revision - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t HAL_GetHalVersion(void) -{ - return __STM32U5xx_HAL_VERSION; -} - -/** - * @brief Returns the device revision identifier. - * @retval Device revision identifier - */ -uint32_t HAL_GetREVID(void) -{ - return ((DBGMCU->IDCODE & DBGMCU_IDCODE_REV_ID) >> 16); -} - -/** - * @brief Returns the device identifier. - * @retval Device identifier - */ -uint32_t HAL_GetDEVID(void) -{ - return (DBGMCU->IDCODE & DBGMCU_IDCODE_DEV_ID); -} - -/** - * @brief Return the first word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw0(void) -{ - return (READ_REG(*((uint32_t *)UID_BASE))); -} - -/** - * @brief Return the second word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw1(void) -{ - return (READ_REG(*((uint32_t *)(UID_BASE + 4U)))); -} - -/** - * @brief Return the third word of the unique device identifier (UID based on 96 bits) - * @retval Device identifier - */ -uint32_t HAL_GetUIDw2(void) -{ - return (READ_REG(*((uint32_t *)(UID_BASE + 8U)))); -} - -/** - * @} - */ - - -/** @defgroup HAL_Exported_Functions_Group3 HAL Debug functions - * @brief HAL Debug functions - * -@verbatim - =============================================================================== - ##### HAL Debug functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Enable/Disable Debug module during STOP0/STOP1/STOP2 modes - (+) Enable/Disable Debug module during STANDBY mode - -@endverbatim - * @{ - */ - -/** - * @brief Enable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP0/STOP1/STOP2 modes. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Enable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_EnableDBGStandbyMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @brief Disable the Debug Module during STANDBY mode. - * @retval None - */ -void HAL_DBGMCU_DisableDBGStandbyMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); -} - -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group4 HAL SYSCFG configuration functions - * @brief HAL SYSCFG configuration functions - * -@verbatim - =============================================================================== - ##### HAL SYSCFG configuration functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure the Voltage reference buffer - (+) Enable/Disable the Voltage reference buffer - (+) Enable/Disable the I/O analog switch voltage booster - -@endverbatim - * @{ - */ - -/** - * @brief Configure the internal voltage reference buffer voltage scale. - * @param VoltageScaling: specifies the output voltage to achieve - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE0: VREF_OUT1 around 1.5 V. - * This requires VDDA equal to or higher than 1.8 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE1: VREF_OUT1 around 1.8 V. - * This requires VDDA equal to or higher than 2.1 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE2: VREF_OUT1 around 2.048 V. - * This requires VDDA equal to or higher than 2.4 V. - * @arg SYSCFG_VREFBUF_VOLTAGE_SCALE3: VREF_OUT1 around 2.5 V. - * This requires VDDA equal to or higher than 2.8 V. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(VoltageScaling)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_VRS, VoltageScaling); -} - -/** - * @brief Configure the internal voltage reference buffer high impedance mode. - * @param Mode: specifies the high impedance mode - * This parameter can be one of the following values: - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE: VREF+ pin is internally connect to VREFINT output. - * @arg SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE: VREF+ pin is high impedance. - * @retval None - */ -void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(Mode)); - - MODIFY_REG(VREFBUF->CSR, VREFBUF_CSR_HIZ, Mode); -} - -/** - * @brief Tune the Internal Voltage Reference buffer (VREFBUF). - * @retval None - */ -void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_VREFBUF_TRIMMING(TrimmingValue)); - - MODIFY_REG(VREFBUF->CCR, VREFBUF_CCR_TRIM, TrimmingValue); -} - -/** - * @brief Enable the Internal Voltage Reference buffer (VREFBUF). - * @retval HAL_OK/HAL_TIMEOUT - */ -HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void) -{ - uint32_t tickstart; - - SET_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait for VRR bit */ - while (READ_BIT(VREFBUF->CSR, VREFBUF_CSR_VRR) == 0UL) - { - if ((HAL_GetTick() - tickstart) > VREFBUF_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - return HAL_OK; -} - -/** - * @brief Disable the Internal Voltage Reference buffer (VREFBUF). - * - * @retval None - */ -void HAL_SYSCFG_DisableVREFBUF(void) -{ - CLEAR_BIT(VREFBUF->CSR, VREFBUF_CSR_ENVR); -} - -/** - * @brief Enable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Disable the I/O analog switch voltage booster - * - * @retval None - */ -void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_BOOSTEN); -} - -/** - * @brief Enable the I/O analog switch voltage selection - * - * @retval None - */ -void HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); -} - -/** - * @brief Disable the I/O analog switch voltage selection - * - * @retval None - */ -void HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_ANASWVDD); -} - -#if defined(SYSCFG_CFGR1_SRAMCACHED) -/** - * @brief Enable the Cacheability of internal SRAMx by DCACHE2 - * - * @retval None - */ -void HAL_SYSCFG_EnableSRAMCached(void) -{ - SET_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); -} - -/** - * @brief Disable the Cacheability of internal SRAMx by DCACHE2 - * - * @retval None - */ -void HAL_SYSCFG_DisableSRAMCached(void) -{ - CLEAR_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_SRAMCACHED); -} -#endif /* SYSCFG_CFGR1_SRAMCACHED */ - -/** - * @brief Enable the Compensation Cell of GPIO supplied by VDD - * @rmtoll CCCSR EN1 HAL_SYSCFG_EnableVddCompensationCell - * @note The vdd compensation cell can be used only when the device supply - * voltage ranges from 1.71 to 3.6 V - * @retval None - */ -void HAL_SYSCFG_EnableVddCompensationCell(void) -{ - SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); -} - -/** - * @brief Enable the Compensation Cell of GPIO supplied by VDDIO2 - * @rmtoll CCCSR EN2 HAL_SYSCFG_EnableVddIO2CompensationCell - * @note The Vdd I/O compensation cell can be used only when the device supply - * voltage ranges from 1.08 to 3.6 V - * @retval None - */ -void HAL_SYSCFG_EnableVddIO2CompensationCell(void) -{ - SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); -} - -#if defined(SYSCFG_CCCSR_EN3) -/** - * @brief Enable the Compensation Cell of HSPI IO supplied by VDD - * @rmtoll CCCSR EN3 HAL_SYSCFG_EnableVddHSPICompensationCell - * @retval None - */ -void HAL_SYSCFG_EnableVddHSPICompensationCell(void) -{ - SET_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); -} -#endif /* SYSCFG_CCCSR_EN3 */ -/** - * @brief Disable the Compensation Cell of GPIO supplied by VDD - * @rmtoll CCCSR EN1 HAL_SYSCFG_DisableVddCompensationCell - * @note The Vdd compensation cell can be used only when the device supply - * voltage ranges from 1.71 to 3.6 V - * @retval None - */ -void HAL_SYSCFG_DisableVddCompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN1); -} - -/** - * @brief Disable the Compensation Cell of GPIO supplied by VDDIO2 - * @rmtoll CCCSR EN2 HAL_SYSCFG_DisableVddIO2CompensationCell - * @note The Vdd I/O compensation cell can be used only when the device supply - * voltage ranges from 1.08 to 3.6 V - * @retval None - */ -void HAL_SYSCFG_DisableVddIO2CompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN2); -} - -#if defined(SYSCFG_CCCSR_EN3) -/** - * @brief Disable the Compensation Cell of HSPI IO supplied by VDD - * @rmtoll CCCSR EN3 HAL_SYSCFG_DisableVddHSPICompensationCell - * @retval None - */ -void HAL_SYSCFG_DisableVddHSPICompensationCell(void) -{ - CLEAR_BIT(SYSCFG->CCCSR, SYSCFG_CCCSR_EN3); -} -#endif /* SYSCFG_CCCSR_EN3 */ -/** - * @} - */ - -/** @defgroup HAL_Exported_Functions_Group5 HAL SYSCFG lock management functions - * @brief SYSCFG lock management functions. - * -@verbatim - =============================================================================== - ##### SYSCFG lock functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Lock the SYSCFG item(s). - * @note Setting lock(s) depends on privilege mode in secure/non-secure code - * Lock(s) cleared only at system reset - * @param Item Item(s) to set lock on. - * This parameter can be a combination of @ref SYSCFG_Lock_items - * @retval None - */ -void HAL_SYSCFG_Lock(uint32_t Item) -{ - /* Check the parameters */ - assert_param(IS_SYSCFG_LOCK_ITEMS(Item)); - - /* Privilege secure/non-secure locks */ - SYSCFG->CNSLCKR = (0xFFFFU & Item); /* non-secure lock item in 16 lowest bits */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Privilege secure only locks */ - SYSCFG->CSLCKR = ((0xFFFF0000U & Item) >> 16U); /* Secure-only lock item in 16 highest bits */ -#endif /* __ARM_FEATURE_CMSE */ -} - -/** - * @brief Get the lock state of SYSCFG item. - * @note Getting lock(s) depends on privilege mode in secure/non-secure code - * @param pItem pointer to return locked items - * the return value can be a combination of @ref SYSCFG_Lock_items - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SYSCFG_GetLock(uint32_t *pItem) -{ - uint32_t tmp_lock; - - /* Check null pointer */ - if (pItem == NULL) - { - return HAL_ERROR; - } - - /* Get the non-secure lock state */ - tmp_lock = SYSCFG->CNSLCKR; - - /* Get the secure lock state in secure code */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - tmp_lock |= (SYSCFG->CSLCKR << 16U); -#endif /* __ARM_FEATURE_CMSE */ - - /* Return overall lock status */ - *pItem = tmp_lock; - - return HAL_OK; -} - -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - -/** @defgroup HAL_Exported_Functions_Group6 HAL SYSCFG attributes management functions - * @brief SYSCFG attributes management functions. - * -@verbatim - =============================================================================== - ##### SYSCFG attributes functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configure the SYSCFG item attribute(s). - * @note Available attributes are to secure SYSCFG items, so this function is - * only available in secure - * @param Item Item(s) to set attributes on. - * This parameter can be a one or a combination of @ref SYSCFG_Attributes_items - * @param Attributes specifies the secure/non-secure attributes. - * @retval None - */ -void HAL_SYSCFG_ConfigAttributes(uint32_t Item, uint32_t Attributes) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); - assert_param(IS_SYSCFG_ATTRIBUTES(Attributes)); - - tmp = SYSCFG_S->SECCFGR; - - /* Set or reset Item */ - if ((Attributes & SYSCFG_SEC) != 0x00U) - { - tmp |= Item; - } - else - { - tmp &= ~Item; - } - - /* Set secure attributes */ - SYSCFG_S->SECCFGR = tmp; -} - -/** - * @brief Get the attribute of a SYSCFG item. - * @note Available attributes are to secure SYSCFG items, so this function is - * only available in secure - * @param Item Single item to get secure/non-secure attribute from. - * @param pAttributes pointer to return the attribute. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SYSCFG_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) -{ - /* Check null pointer */ - if (pAttributes == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SYSCFG_ITEMS_ATTRIBUTES(Item)); - - /* Get the secure attribute state */ - if ((SYSCFG_S->SECCFGR & Item) != 0U) - { - *pAttributes = SYSCFG_SEC; - } - else - { - *pAttributes = SYSCFG_NSEC; - } - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* __ARM_FEATURE_CMSE */ - -#ifdef SYSCFG_OTGHSPHYCR_EN -/** - * @brief Enable the OTG PHY . - * @param OTGPHYConfig Defines the OTG PHY configuration. - This parameter can be one of @ref SYSCFG_OTG_PHY_Enable - * @retval None - */ - -void HAL_SYSCFG_EnableOTGPHY(uint32_t OTGPHYConfig) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_OTGPHY_CONFIG(OTGPHYConfig)); - - MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_EN, OTGPHYConfig); -} - -/** - * @brief Set the OTG PHY Power Down config. - * @param PowerDownConfig Defines the OTG PHY Power down configuration. - This parameter can be one of @ref SYSCFG_OTG_PHY_PowerDown - * @retval None - */ -void HAL_SYSCFG_SetOTGPHYPowerDownConfig(uint32_t PowerDownConfig) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_OTGPHY_POWERDOWN_CONFIG(PowerDownConfig)); - - MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_PDCTRL, PowerDownConfig); -} - -/** - * @brief Set the OTG PHY reference clock selection. - * @param RefClkSelection Defines the OTG PHY reference clock selection. - This parameter can be one of the @ref SYSCFG_OTG_PHY_RefenceClockSelection - * @retval None - */ -void HAL_SYSCFG_SetOTGPHYReferenceClockSelection(uint32_t RefClkSelection) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_OTGPHY_REFERENCE_CLOCK(RefClkSelection)); - - MODIFY_REG(SYSCFG->OTGHSPHYCR, SYSCFG_OTGHSPHYCR_CLKSEL, RefClkSelection); -} - -/** - * @brief Set the OTG PHY Disconnect Threshold. - * @param DisconnectThreshold Defines the voltage level for the threshold used to detect a disconnect event. - This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_DisconnectThreshold - * @retval None - */ - -void HAL_SYSCFG_SetOTGPHYDisconnectThreshold(uint32_t DisconnectThreshold) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_OTGPHY_DISCONNECT(DisconnectThreshold)); - - MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_COMPDISTUNE, DisconnectThreshold); -} - -/** - * @brief Adjust the voltage level for the threshold used to detect valid high speed data. - * @param SquelchThreshold Defines the voltage level. - This parameter can be onez of the @ref SYSCFG_OTG_PHYTUNER_SquelchThreshold - - * @retval None - */ - -void HAL_SYSCFG_SetOTGPHYSquelchThreshold(uint32_t SquelchThreshold) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_OTGPHY_SQUELCH(SquelchThreshold)); - - MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_SQRXTUNE, SquelchThreshold); -} - -/** - * @brief Set the OTG PHY Current config. - * @param PreemphasisCurrent Defines the current configuration. - This parameter can be one of the @ref SYSCFG_OTG_PHYTUNER_PreemphasisCurrent - - * @retval None - */ - -void HAL_SYSCFG_SetOTGPHYPreemphasisCurrent(uint32_t PreemphasisCurrent) -{ - /* Check the parameter */ - assert_param(IS_SYSCFG_OTGPHY_PREEMPHASIS(PreemphasisCurrent)); - - MODIFY_REG(SYSCFG->OTGHSPHYTUNER2, SYSCFG_OTGHSPHYTUNER2_TXPREEMPAMPTUNE, PreemphasisCurrent); -} - -#endif /* SYSCFG_OTGHSPHYCR_EN */ - -/** - * @} - */ - -#endif /* HAL_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c deleted file mode 100644 index 12f66ec59..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_cortex.c +++ /dev/null @@ -1,832 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_cortex.c - * @author MCD Application Team - * @brief CORTEX HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the CORTEX: - * + Initialization and Configuration functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - - [..] - *** How to configure Interrupts using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to configure the NVIC interrupts (IRQ). - The Cortex-M33 exceptions are managed by CMSIS functions. - - (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. - (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). - (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). - - -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. - The pending IRQ priority will be managed only by the sub priority. - - -@- IRQ priority order (sorted by highest to lowest priority): - (+@) Lowest pre-emption priority - (+@) Lowest sub priority - (+@) Lowest hardware priority (IRQ number) - - [..] - *** How to configure SysTick using CORTEX HAL driver *** - ======================================================== - [..] - Setup SysTick Timer for time base. - - (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which - is a CMSIS function that: - (++) Configures the SysTick Reload register with value passed as function parameter. - (++) Configures the SysTick IRQ priority to the lowest value (0x0F). - (++) Resets the SysTick Counter register. - (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). - (++) Enables the SysTick Interrupt. - (++) Starts the SysTick Counter. - - (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro - __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the - HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined - inside the stm32u5xx_hal_cortex.h file. - - (+) You can change the SysTick IRQ priority by calling the - HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function - call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. - - (+) To adjust the SysTick time base, use the following formula: - - Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) - (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function - (++) Reload Value should not exceed 0xFFFFFF - - [..] - *** How to configure MPU (secure and non secure) using CORTEX HAL driver *** - =========================================================== - [..] - This section provides functions allowing to Enable and configure the MPU secure and non-secure. - - (#) Enable the MPU using HAL_MPU_Enable() function. - (#) Disable the MPU using HAL_MPU_Disable() function. - (#) Enable the MPU using HAL_MPU_Enable_NS() function to address the non secure MPU. - (#) Disable the MPU using HAL_MPU_Disable_NS() function to address the non secure MPU. - (#) Configure the MPU region using HAL_MPU_ConfigRegion() - and HAL_MPU_ConfigRegion_NS() to address the non secure MPU. - (#) Configure the MPU Memory attributes using HAL_MPU_ConfigMemoryAttributes() - and HAL_MPU_ConfigMemoryAttributes_NS() to address the non secure MPU. - - @endverbatim - ****************************************************************************** - - The table below gives the allowed values of the pre-emption priority and subpriority according - to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. - -======================================================================================================================== - NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description -======================================================================================================================== - NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority - | | | 4 bits for subpriority ------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority - | | | 3 bits for subpriority ------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority - | | | 2 bits for subpriority ------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority - | | | 1 bit for subpriority ------------------------------------------------------------------------------------------------------------------------- - NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority - | | | 0 bit for subpriority -======================================================================================================================== - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup CORTEX - * @{ - */ - -#ifdef HAL_CORTEX_MODULE_ENABLED - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/** @defgroup CORTEX_Private_Functions CORTEX Private Functions - * @{ - */ -static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit); -static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup CORTEX_Exported_Functions - * @{ - */ - - -/** @addtogroup CORTEX_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * -@verbatim - ============================================================================== - ##### Initialization and Configuration functions ##### - ============================================================================== - [..] - This section provides the CORTEX HAL driver functions allowing to configure Interrupts - SysTick functionalities - -@endverbatim - * @{ - */ - - -/** - * @brief Set the priority grouping field (pre-emption priority and subpriority) - * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, - * 1 bit for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, - * 0 bit for subpriority - * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. - * The pending IRQ priority will be managed only by the subpriority. - * @retval None - */ -void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - - /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ - NVIC_SetPriorityGrouping(PriorityGroup); -} - -/** - * @brief Set the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @param PreemptPriority: The pre-emption priority for the IRQn channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. - * This parameter can be a value between 0 and 15 - * A lower priority value indicates a higher priority. - * @retval None - */ -void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - uint32_t prioritygroup; - - /* Check the parameters */ - assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); - assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); - - prioritygroup = NVIC_GetPriorityGrouping(); - - NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); -} - -/** - * @brief Enable a device specific interrupt in the NVIC interrupt controller. - * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() - * function should be called before. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @retval None - */ -void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Enable interrupt */ - NVIC_EnableIRQ(IRQn); -} - -/** - * @brief Disable a device specific interrupt in the NVIC interrupt controller. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @retval None - */ -void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) -{ - /* Check the parameters */ - assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); - - /* Disable interrupt */ - NVIC_DisableIRQ(IRQn); -} - -/** - * @brief Initiate a system reset request to reset the MCU. - * @retval None - */ -void HAL_NVIC_SystemReset(void) -{ - /* System Reset */ - NVIC_SystemReset(); -} - -/** - * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): - * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. - * @retval status: - 0 Function succeeded. - * - 1 Function failed. - */ -uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) -{ - if ((TicksNumb - 1UL) > SysTick_LOAD_RELOAD_Msk) - { - /* Reload value impossible */ - return (1UL); - } - - /* Set reload register */ - WRITE_REG(SysTick->LOAD, (uint32_t)(TicksNumb - 1UL)); - - /* Load the SysTick Counter Value */ - WRITE_REG(SysTick->VAL, 0UL); - - /* Enable SysTick IRQ and SysTick Timer */ - SET_BIT(SysTick->CTRL, (SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk)); - - /* Function successful */ - return (0UL); -} -/** - * @} - */ - -/** @addtogroup CORTEX_Exported_Functions_Group2 - * @brief Cortex control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This subsection provides a set of functions allowing to control the CORTEX - (NVIC, SYSTICK, MPU) functionalities. - - -@endverbatim - * @{ - */ - -/** - * @brief Get the priority grouping field from the NVIC Interrupt Controller. - * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) - */ -uint32_t HAL_NVIC_GetPriorityGrouping(void) -{ - /* Get the PRIGROUP[10:8] field value */ - return NVIC_GetPriorityGrouping(); -} - -/** - * @brief Get the priority of an interrupt. - * @param IRQn: External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. - * This parameter can be one of the following values: - * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, - * 4 bits for subpriority - * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, - * 3 bits for subpriority - * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, - * 2 bits for subpriority - * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, - * 1 bit for subpriority - * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, - * 0 bit for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). - * @retval None - */ -void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *const pPreemptPriority, - uint32_t *const pSubPriority) -{ - /* Check the parameters */ - assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); - /* Get priority for Cortex-M system or device specific interrupts */ - NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); -} - -/** - * @brief Set Pending bit of an external interrupt. - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @retval None - */ -void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) -{ - /* Set interrupt pending */ - NVIC_SetPendingIRQ(IRQn); -} - -/** - * @brief Get Pending Interrupt (read the pending register in the NVIC - * and return the pending bit for the specified interrupt). - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) -{ - /* Return 1 if pending else 0 */ - return NVIC_GetPendingIRQ(IRQn); -} - -/** - * @brief Clear the pending bit of an external interrupt. - * @param IRQn External interrupt number. - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @retval None - */ -void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) -{ - /* Clear pending interrupt */ - NVIC_ClearPendingIRQ(IRQn); -} - -/** - * @brief Get active interrupt (read the active register in NVIC and return the active bit). - * @param IRQn External interrupt number - * This parameter can be an enumerator of IRQn_Type enumeration - * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate - * CMSIS device file (stm32u5xxxx.h)) - * @retval status: - 0 Interrupt status is not pending. - * - 1 Interrupt status is pending. - */ -uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) -{ - /* Return 1 if active else 0 */ - return NVIC_GetActive(IRQn); -} - -/** - * @brief Configure the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. - * This parameter can be one of the following values: - * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - * @retval None - */ -void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) -{ - /* Check the parameters */ - assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); - switch (CLKSource) - { - /* Select HCLK as Systick clock source */ - case SYSTICK_CLKSOURCE_HCLK: - SET_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); - break; - /* Select HCLK_DIV8 as Systick clock source */ - case SYSTICK_CLKSOURCE_HCLK_DIV8: - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, (0x00000000U)); - break; - /* Select LSI as Systick clock source */ - case SYSTICK_CLKSOURCE_LSI: - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_0); - break; - /* Select LSE as Systick clock source */ - case SYSTICK_CLKSOURCE_LSE: - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk); - MODIFY_REG(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL, RCC_CCIPR1_SYSTICKSEL_1); - break; - default: - /* Nothing to do */ - break; - } -} - -/** - * @brief Get the SysTick clock source configuration. - * @retval SysTick clock source that can be one of the following values: - * @arg SYSTICK_CLKSOURCE_LSI: LSI clock selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_LSE: LSE clock selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. - * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. - */ -uint32_t HAL_SYSTICK_GetCLKSourceConfig(void) -{ - uint32_t systick_source; - uint32_t systick_rcc_source; - - /* Read SysTick->CTRL register for internal or external clock source */ - if (READ_BIT(SysTick->CTRL, SysTick_CTRL_CLKSOURCE_Msk) != 0U) - { - /* Internal clock source */ - systick_source = SYSTICK_CLKSOURCE_HCLK; - } - else - { - /* External clock source, check the selected one in RCC */ - systick_rcc_source = READ_BIT(RCC->CCIPR1, RCC_CCIPR1_SYSTICKSEL); - - switch (systick_rcc_source) - { - case (0x00000000U): - systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; - break; - - case (RCC_CCIPR1_SYSTICKSEL_0): - systick_source = SYSTICK_CLKSOURCE_LSI; - break; - - case (RCC_CCIPR1_SYSTICKSEL_1): - systick_source = SYSTICK_CLKSOURCE_LSE; - break; - - default: - systick_source = SYSTICK_CLKSOURCE_HCLK_DIV8; - break; - } - } - return systick_source; -} - -/** - * @brief Handle SYSTICK interrupt request. - * @retval None - */ -void HAL_SYSTICK_IRQHandler(void) -{ - HAL_SYSTICK_Callback(); -} - -/** - * @brief SYSTICK callback. - * @retval None - */ -__weak void HAL_SYSTICK_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SYSTICK_Callback could be implemented in the user file - */ -} - - -/** - * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable(uint32_t MPU_Control) -{ - __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ - - /* Enable the MPU */ - MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable the non-secure MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, - * NMI, FAULTMASK and privileged access to the default memory - * This parameter can be one of the following values: - * @arg MPU_HFNMI_PRIVDEF_NONE - * @arg MPU_HARDFAULT_NMI - * @arg MPU_PRIVILEGED_DEFAULT - * @arg MPU_HFNMI_PRIVDEF - * @retval None - */ -void HAL_MPU_Enable_NS(uint32_t MPU_Control) -{ - __DMB(); /* Data Memory Barrier operation to force any outstanding writes to memory before enabling the MPU */ - - /* Enable the MPU */ - MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; - - /* Enable fault exceptions */ - SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Disable the MPU. - * @retval None - */ -void HAL_MPU_Disable(void) -{ - __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ - - /* Disable fault exceptions */ - SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Disable the non-secure MPU. - * @retval None - */ -void HAL_MPU_Disable_NS(void) -{ - __DMB(); /* Force any outstanding transfers to complete before disabling MPU */ - - /* Disable fault exceptions */ - SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; - - /* Disable the MPU */ - MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; - - /* Follow ARM recommendation with */ - /* Data Synchronization and Instruction Synchronization Barriers to ensure MPU configuration */ - __DSB(); /* Ensure that the subsequent instruction is executed only after the write to memory */ - __ISB(); /* Flush and refill pipeline with updated MPU configuration settings */ -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Enable the MPU Region. - * @retval None - * @param RegionNumber Specifies the index of the region to enable. - * this parameter can be a value of @ref CORTEX_MPU_Region_Number - */ -void HAL_MPU_EnableRegion(uint32_t RegionNumber) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); - - /* Set the Region number */ - MPU->RNR = RegionNumber; - - /* Enable the Region */ - SET_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Enable the non-secure MPU Region. - * @retval None - * @param RegionNumber Specifies the index of the region to enable. - * this parameter can be a value of @ref CORTEX_MPU_Region_Number - */ -void HAL_MPU_EnableRegion_NS(uint32_t RegionNumber) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); - - /* Set the Region number */ - MPU_NS->RNR = RegionNumber; - - /* Enable the Region */ - SET_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); -} -#endif /*__ARM_FEATURE_CMSE*/ - -/** - * @brief Disable the MPU Region. - * @retval None - * @param RegionNumber Specifies the index of the region to disable. - * this parameter can be a value of @ref CORTEX_MPU_Region_Number - */ -void HAL_MPU_DisableRegion(uint32_t RegionNumber) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); - - /* Set the Region number */ - MPU->RNR = RegionNumber; - - /* Disable the Region */ - CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Disable the non-secure MPU Region. - * @retval None - * @param RegionNumber Specifies the index of the region to disable. - * this parameter can be a value of @ref CORTEX_MPU_Region_Number - */ -void HAL_MPU_DisableRegion_NS(uint32_t RegionNumber) -{ - /* Check the parameters */ - assert_param(IS_MPU_REGION_NUMBER(RegionNumber)); - - /* Set the Region number */ - MPU_NS->RNR = RegionNumber; - - /* Disable the Region */ - CLEAR_BIT(MPU_NS->RLAR, MPU_RLAR_EN_Msk); -} -#endif /*__ARM_FEATURE_CMSE*/ - -/** - * @brief Initialize and configure the Region and the memory to be protected. - * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion(const MPU_Region_InitTypeDef *const pMPU_RegionInit) -{ - MPU_ConfigRegion(MPU, pMPU_RegionInit); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Initialize and configure the Region and the memory to be protected for non-secure MPU. - * @param pMPU_RegionInit: Pointer to a MPU_Region_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigRegion_NS(const MPU_Region_InitTypeDef *const pMPU_RegionInit) -{ - MPU_ConfigRegion(MPU_NS, pMPU_RegionInit); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Initialize and configure the memory attributes. - * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigMemoryAttributes(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) -{ - MPU_ConfigMemoryAttributes(MPU, pMPU_AttributesInit); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Initialize and configure the memory attributes for non-secure MPU. - * @param pMPU_AttributesInit: Pointer to a MPU_Attributes_InitTypeDef structure that contains - * the initialization and configuration information. - * @retval None - */ -void HAL_MPU_ConfigMemoryAttributes_NS(const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) -{ - MPU_ConfigMemoryAttributes(MPU_NS, pMPU_AttributesInit); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup CORTEX_Private_Functions - * @{ - */ -static void MPU_ConfigRegion(MPU_Type *MPUx, const MPU_Region_InitTypeDef *const pMPU_RegionInit) -{ - /* Check the parameters */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - assert_param(IS_MPU_INSTANCE(MPUx)); -#endif /* __ARM_FEATURE_CMSE */ - assert_param(IS_MPU_REGION_NUMBER(pMPU_RegionInit->Number)); - assert_param(IS_MPU_REGION_ENABLE(pMPU_RegionInit->Enable)); - assert_param(IS_MPU_INSTRUCTION_ACCESS(pMPU_RegionInit->DisableExec)); - assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(pMPU_RegionInit->AccessPermission)); - assert_param(IS_MPU_ACCESS_SHAREABLE(pMPU_RegionInit->IsShareable)); - - /* Follow ARM recommendation with Data Memory Barrier prior to MPU configuration */ - __DMB(); - - /* Set the Region number */ - MPUx->RNR = pMPU_RegionInit->Number; - - /* Disable the Region */ - CLEAR_BIT(MPU->RLAR, MPU_RLAR_EN_Msk); - - MPUx->RBAR = (((uint32_t)pMPU_RegionInit->BaseAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->IsShareable << MPU_RBAR_SH_Pos) | - ((uint32_t)pMPU_RegionInit->AccessPermission << MPU_RBAR_AP_Pos) | - ((uint32_t)pMPU_RegionInit->DisableExec << MPU_RBAR_XN_Pos)); - - MPUx->RLAR = (((uint32_t)pMPU_RegionInit->LimitAddress & 0xFFFFFFE0UL) | - ((uint32_t)pMPU_RegionInit->AttributesIndex << MPU_RLAR_AttrIndx_Pos) | - ((uint32_t)pMPU_RegionInit->Enable << MPU_RLAR_EN_Pos)); -} - - -static void MPU_ConfigMemoryAttributes(MPU_Type *MPUx, const MPU_Attributes_InitTypeDef *const pMPU_AttributesInit) -{ - __IO uint32_t *p_mair; - uint32_t attr_values; - uint32_t attr_number; - - /* Check the parameters */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - assert_param(IS_MPU_INSTANCE(MPUx)); -#endif /* __ARM_FEATURE_CMSE */ - assert_param(IS_MPU_ATTRIBUTES_NUMBER(pMPU_AttributesInit->Number)); - /* No need to check Attributes value as all 0x0..0xFF possible */ - - /* Follow ARM recommendation with Data Memory Barrier prior to MPUx configuration */ - __DMB(); - - if (pMPU_AttributesInit->Number < MPU_ATTRIBUTES_NUMBER4) - { - /* Program MPU_MAIR0 */ - p_mair = &(MPUx->MAIR0); - attr_number = pMPU_AttributesInit->Number; - } - else - { - /* Program MPU_MAIR1 */ - p_mair = &(MPUx->MAIR1); - attr_number = (uint32_t)pMPU_AttributesInit->Number - 4U; - } - - attr_values = *(p_mair); - attr_values &= ~(0xFFUL << (attr_number * 8U)); - *(p_mair) = attr_values | ((uint32_t)pMPU_AttributesInit->Attributes << (attr_number * 8U)); -} -/** - * @} - */ - -#endif /* HAL_CORTEX_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c deleted file mode 100644 index 58db90705..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma.c +++ /dev/null @@ -1,1680 +0,0 @@ -/** - ********************************************************************************************************************** - * @file stm32u5xx_hal_dma.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following functionalities of the Direct Memory Access - * (DMA) peripheral: - * + Initialization/De-Initialization Functions - * + I/O Operation Functions - * + State and Errors Functions - * + DMA Attributes Functions - * - ********************************************************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ********************************************************************************************************************** - @verbatim - ====================================================================================================================== - ##### How to use this driver ##### - ====================================================================================================================== - - [..] - DMA transfer modes are divided to 2 major categories : - (+) Normal transfers (legacy) - (+) Linked-list transfers - - [..] - Normal transfers mode is initialized via the standard module and linked-list mode is configured via the extended - module. - - [..] - Additionally to linked-list capability, all advanced DMA features are managed and configured via the extended - module as extensions to normal mode. - Advanced features are : - (+) Repeated block feature. - (+) Trigger feature. - (+) Data handling feature. - - [..] - DMA Legacy circular transfer, is replaced by circular linked-list configuration. - - - *** Initialization and De-Initialization *** - ============================================ - [..] - For a given channel, enable and configure the peripheral to be connected to the DMA Channel (except for internal - SRAM/FLASH memories: no initialization is necessary) please refer to Reference manual for connection between - peripherals and DMA requests. - - [..] - For a given channel, use HAL_DMA_Init function to program the required configuration for normal transfer through - the following parameters: - - (+) Request : Specifies the DMA channel request - Request parameters : - (++) can be a value of DMA_Request_Selection - - (+) BlkHWRequest : Specifies the Block hardware request mode for DMA channel - (++) can be a value of DMA_Block_Request - - (+) Direction : Specifies the transfer direction for DMA channel - (++) can be a value of DMA_Transfer_Direction - - (+) SrcInc : Specifies the source increment mode for the DMA channel - (++) can be a value of DMA_Source_Increment_Mode - - (+) DestInc : Specifies the destination increment mode for the DMA channel - (++) can be a value of DMA_Destination_Increment_Mode - - (+) SrcDataWidth : Specifies the source data width for the DMA channel - (++) can be a value of DMA_Source_Data_Width - - (+) DestDataWidth : Specifies the destination data width for the DMA channel - (++) can be a value of DMA_Destination_Data_Width - - (+) Priority : Specifies the priority for the DMA channel - (++) can be a value of DMA_Priority_Level - - (+) SrcBurstLength : Specifies the source burst length (number of beats) for the DMA channel - (++) can be a value of between 1 and 64 - - (+) DestBurstLength : Specifies the destination burst length (number of beats) for the DMA channel - (++) can be a value of between 1 and 64 - - (+) TransferAllocatedPort : Specifies the source and destination allocated ports - (++) can be a value of DMA_Transfer_Allocated_Port - - (+) TransferEventMode : Specifies the transfer event mode for the DMA channel - (++) can be a value of DMA_Transfer_Event_Mode - - (+) Mode : Specifies the transfer mode for the DMA channel - (++) can be DMA_NORMAL - - *** Polling mode IO operation *** - ================================= - [..] - (+) Use HAL_DMA_Start() to start a DMA normal transfer after the configuration of source address, destination - address and the size of data to be transferred. - - (+) Use HAL_DMA_PollForTransfer() to poll for selected transfer level. In this case a fixed Timeout can be - configured by User depending on his application. - Transfer level can be : - (++) HAL_DMA_HALF_TRANSFER - (++) HAL_DMA_FULL_TRANSFER - For circular transfer, this API returns an HAL_ERROR with HAL_DMA_ERROR_NOT_SUPPORTED error code. - - (+) Use HAL_DMA_Abort() function to abort any ongoing DMA transfer in blocking mode. - This API returns HAL_ERROR when there is no ongoing transfer or timeout is reached when disabling the DMA - channel. (This API should not be called from an interrupt service routine) - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() - - (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() - - (+) Use HAL_DMA_RegisterCallback() function to register user callbacks from the following list : - (++) XferCpltCallback : transfer complete callback. - (++) XferHalfCpltCallback : half transfer complete callback. - (++) XferErrorCallback : transfer error callback. - (++) XferAbortCallback : transfer abort complete callback. - (++) XferSuspendCallback : transfer suspend complete callback. - - (+) Use HAL_DMA_Start_IT() to start the DMA transfer after the enable of DMA interrupts and the configuration - of source address,destination address and the size of data to be transferred. - - (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() interrupt subroutine to handle any DMA interrupt. - - (+) Use HAL_DMA_Abort_IT() function to abort any on-going DMA transfer in non-blocking mode. - This API will suspend immediately the DMA channel execution. When the transfer is effectively suspended, - an interrupt is generated and HAL_DMA_IRQHandler() will reset the channel and execute the callback - XferAbortCallback. (This API could be called from an interrupt service routine) - - - *** State and errors *** - ======================== - [..] - (+) Use HAL_DMA_GetState() function to get the DMA state. - (+) Use HAL_DMA_GetError() function to get the DMA error code. - - - *** Security and privilege attributes *** - ========================================= - [..] - (+) Use HAL_DMA_ConfigChannelAttributes() function to configure DMA channel security and privilege attributes. - (++) Security : at channel level, at source level and at destination level. - (++) Privilege : at channel level. - (+) Use HAL_DMA_GetConfigChannelAttributes() function to get the DMA channel attributes. - (+) Use HAL_DMA_LockChannelAttributes() function to lock the DMA channel security and privilege attributes - configuration. This API can be called once after each system boot. - If called again, HAL_DMA_ConfigChannelAttributes() API has no effect. - Unlock is done either by a system boot or a by an RCC reset. - (+) Use HAL_DMA_GetLockChannelAttributes() function to get the attributes lock status. - - - *** DMA HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in DMA HAL driver. - - (+) __HAL_DMA_ENABLE : Enable the specified DMA Channel. - (+) __HAL_DMA_DISABLE : Disable the specified DMA Channel. - (+) __HAL_DMA_GET_FLAG : Get the DMA Channel pending flags. - (+) __HAL_DMA_CLEAR_FLAG : Clear the DMA Channel pending flags. - (+) __HAL_DMA_ENABLE_IT : Enable the specified DMA Channel interrupts. - (+) __HAL_DMA_DISABLE_IT : Disable the specified DMA Channel interrupts. - (+) __HAL_DMA_GET_IT_SOURCE : Check whether the specified DMA Channel interrupt has occurred or not. - - [..] - (@) You can refer to the header file of the DMA HAL driver for more useful macros. - - @endverbatim - ********************************************************************************************************************** - */ - -/* Includes ----------------------------------------------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup DMA DMA - * @brief DMA HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private typedef ---------------------------------------------------------------------------------------------------*/ -/* Private constants -------------------------------------------------------------------------------------------------*/ -/* Private macro -----------------------------------------------------------------------------------------------------*/ -/* Private variables -------------------------------------------------------------------------------------------------*/ -/* Private function prototypes ---------------------------------------------------------------------------------------*/ -static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, - uint32_t SrcAddress, - uint32_t DstAddress, - uint32_t SrcDataSize); -static void DMA_Init(DMA_HandleTypeDef const *const hdma); - -/* Exported functions ------------------------------------------------------------------------------------------------*/ - -/** @addtogroup DMA_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @addtogroup DMA_Exported_Functions_Group1 - * -@verbatim - ====================================================================================================================== - ##### Initialization and de-initialization functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to initialize and de-initialize the DMA channel in normal mode. - - [..] - (+) The HAL_DMA_Init() function follows the DMA channel configuration procedures as described in reference manual. - (+) The HAL_DMA_DeInit() function allows to de-initialize the DMA channel. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef and - * create the associated handle. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *const hdma) -{ - /* Get tick number */ - uint32_t tickstart = HAL_GetTick(); - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); - if (hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) - { - assert_param(IS_DMA_REQUEST(hdma->Init.Request)); - } - assert_param(IS_DMA_BLOCK_HW_REQUEST(hdma->Init.BlkHWRequest)); - assert_param(IS_DMA_SOURCE_INC(hdma->Init.SrcInc)); - assert_param(IS_DMA_DESTINATION_INC(hdma->Init.DestInc)); - assert_param(IS_DMA_SOURCE_DATA_WIDTH(hdma->Init.SrcDataWidth)); - assert_param(IS_DMA_DESTINATION_DATA_WIDTH(hdma->Init.DestDataWidth)); - assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); - assert_param(IS_DMA_TCEM_EVENT_MODE(hdma->Init.TransferEventMode)); - assert_param(IS_DMA_MODE(hdma->Init.Mode)); - /* Check DMA channel instance */ - if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) - { - assert_param(IS_DMA_BURST_LENGTH(hdma->Init.SrcBurstLength)); - assert_param(IS_DMA_BURST_LENGTH(hdma->Init.DestBurstLength)); - assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(hdma->Init.TransferAllocatedPort)); - } - - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA channel is effectively disabled */ - while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Initialize the DMA channel registers */ - DMA_Init(hdma); - - /* Update DMA channel operation mode */ - hdma->Mode = hdma->Init.Mode; - - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA channel when it is configured in normal mode. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *const hdma) -{ - - DMA_TypeDef *p_dma_instance; - - uint32_t tickstart = HAL_GetTick(); - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - /* Get DMA instance */ - p_dma_instance = GET_DMA_INSTANCE(hdma); - - /* Disable the selected DMA Channel */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA channel is effectively disabled */ - while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Reset DMA Channel registers */ - hdma->Instance->CLBAR = 0U; - hdma->Instance->CCR = 0U; - hdma->Instance->CTR1 = 0U; - hdma->Instance->CTR2 = 0U; - hdma->Instance->CBR1 = 0U; - hdma->Instance->CSAR = 0U; - hdma->Instance->CDAR = 0U; - hdma->Instance->CLLR = 0U; - - /* Reset 2D Addressing registers */ - if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) - { - hdma->Instance->CTR3 = 0U; - hdma->Instance->CBR2 = 0U; - } - - /* Clear privilege attribute */ - CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Clear secure attribute */ - CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | - DMA_FLAG_TO)); - - /* Clean all callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - hdma->XferSuspendCallback = NULL; - - /* Clean DMA queue */ - hdma->LinkedListQueue = NULL; - - /* Clean DMA parent */ - if (hdma->Parent != NULL) - { - hdma->Parent = NULL; - } - - /* Update DMA channel operation mode */ - hdma->Mode = DMA_NORMAL; - - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group2 - * -@verbatim - ====================================================================================================================== - ##### IO operation functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Configure the source, destination address and data size and Start DMA transfer in normal mode - (+) Abort DMA transfer - (+) Poll for transfer complete - (+) Handle DMA interrupt request - (+) Register and Unregister DMA callbacks - - [..] - (+) The HAL_DMA_Start() function allows to start the DMA channel transfer in normal mode (Blocking mode). - (+) The HAL_DMA_Start_IT() function allows to start the DMA channel transfer in normal mode (Non-blocking mode). - (+) The HAL_DMA_Abort() function allows to abort any on-going transfer (Blocking mode). - (+) The HAL_DMA_Abort_IT() function allows to abort any on-going transfer (Non-blocking mode). - (+) The HAL_DMA_PollForTransfer() function allows to poll on half transfer and transfer complete (Blocking mode). - This API cannot be used for circular transfers. - (+) The HAL_DMA_IRQHandler() function allows to handle any DMA channel interrupt (Non-blocking mode). - (+) The HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback() functions allow respectively to register and - unregister user customized callbacks. - User callbacks are called under HAL_DMA_IRQHandler(). - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA channel transfer in normal mode (Blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for - * the specified DMA Channel. - * @param SrcAddress : The source data address. - * @param DstAddress : The destination data address. - * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *const hdma, - uint32_t SrcAddress, - uint32_t DstAddress, - uint32_t SrcDataSize) -{ - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); - - /* Process locked */ - __HAL_LOCK(hdma); - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source address, destination address, the data size and clear flags */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); - - /* Enable DMA channel */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Starts the DMA channel transfer in normal mode with interrupts enabled (Non-blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param SrcAddress : The source data address. - * @param DstAddress : The destination data address. - * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *const hdma, - uint32_t SrcAddress, - uint32_t DstAddress, - uint32_t SrcDataSize) -{ - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_BLOCK_SIZE(SrcDataSize)); - - /* Process locked */ - __HAL_LOCK(hdma); - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Configure the source address, destination address, the data size and clear flags */ - DMA_SetConfig(hdma, SrcAddress, DstAddress, SrcDataSize); - - /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); - - /* Check half transfer complete callback */ - if (hdma->XferHalfCpltCallback != NULL) - { - /* If Half Transfer complete callback is set, enable the corresponding IT */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); - } - - /* Check Half suspend callback */ - if (hdma->XferSuspendCallback != NULL) - { - /* If Transfer suspend callback is set, enable the corresponding IT */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); - } - - /* Enable DMA channel */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Abort any on-going DMA channel transfer (Blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @note After suspending a DMA channel, a wait until the DMA channel is effectively stopped is added. If a channel - * is suspended while a data transfer is on-going, the current data will be transferred and the channel will be - * effectively suspended only after the transfer of any on-going data is finished. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *const hdma) -{ - /* Get tick number */ - uint32_t tickstart = HAL_GetTick(); - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State != HAL_DMA_STATE_BUSY) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Suspend the channel */ - hdma->Instance->CCR |= DMA_CCR_SUSP; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_SUSPEND; - - /* Check if the DMA Channel is suspended */ - while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - - /* Reset the channel */ - hdma->Instance->CCR |= DMA_CCR_RESET; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ABORT; - - /* Clear all status flags */ - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | - DMA_FLAG_TO)); - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - - /* Clear remaining data size to ensure loading linked-list from memory next start */ - hdma->Instance->CBR1 = 0U; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - } - - return HAL_OK; -} - -/** - * @brief Abort any on-going DMA channel transfer in interrupt mode (Non-blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *const hdma) -{ - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State != HAL_DMA_STATE_BUSY) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - return HAL_ERROR; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ABORT; - - /* Suspend the channel and activate suspend interrupt */ - hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); - } - - return HAL_OK; -} - -/** - * @brief Polling for transfer status (Blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param CompleteLevel : Specifies the DMA level complete. - * @param Timeout : Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *const hdma, - HAL_DMA_LevelCompleteTypeDef CompleteLevel, - uint32_t Timeout) -{ - /* Get tick number */ - uint32_t tickstart = HAL_GetTick(); - uint32_t level_flag; - uint32_t tmp_csr; - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_LEVEL_COMPLETE(CompleteLevel)); - - /* Check DMA channel state */ - if (hdma->State != HAL_DMA_STATE_BUSY) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - /* Polling mode is not supported in circular mode */ - if ((hdma->Mode & DMA_LINKEDLIST_CIRCULAR) == DMA_LINKEDLIST_CIRCULAR) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; - - return HAL_ERROR; - } - - /* Get the level transfer complete flag */ - level_flag = ((CompleteLevel == HAL_DMA_FULL_TRANSFER) ? DMA_FLAG_IDLE : DMA_FLAG_HT); - - /* Get DMA channel status */ - tmp_csr = hdma->Instance->CSR; - - while ((tmp_csr & level_flag) == 0U) - { - /* Check for the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - - /* - If timeout, abort the current transfer. - Note that the Abort function will - - Clear all transfer flags. - - Unlock. - - Set the State. - */ - (void)HAL_DMA_Abort(hdma); - - return HAL_ERROR; - } - } - - /* Get a newer CSR register value */ - tmp_csr = hdma->Instance->CSR; - } - - /* Check trigger overrun flag */ - if ((tmp_csr & DMA_FLAG_TO) != 0U) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TO; - - /* Clear the error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); - } - - /* Check error flags */ - if ((tmp_csr & (DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE)) != 0U) - { - /* Check the data transfer error flag */ - if ((tmp_csr & DMA_FLAG_DTE) != 0U) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DTE; - - /* Clear the error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); - } - - /* Check the update link error flag */ - if ((tmp_csr & DMA_FLAG_ULE) != 0U) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_ULE; - - /* Clear the error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); - } - - /* Check the user setting error flag */ - if ((tmp_csr & DMA_FLAG_USE) != 0U) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_USE; - - /* Clear the error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); - } - - /* Reset the channel */ - hdma->Instance->CCR |= DMA_CCR_RESET; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - /* Clear the transfer level flag */ - if (CompleteLevel == HAL_DMA_HALF_TRANSFER) - { - /* Clear the Half Transfer flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); - } - else if (CompleteLevel == HAL_DMA_FULL_TRANSFER) - { - /* Clear the transfer flags */ - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Handle DMA interrupt request (Non-blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval None. - */ -void HAL_DMA_IRQHandler(DMA_HandleTypeDef *const hdma) -{ - const DMA_TypeDef *p_dma_instance = GET_DMA_INSTANCE(hdma); - uint32_t global_it_flag = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); - uint32_t global_active_flag_ns = IS_DMA_GLOBAL_ACTIVE_FLAG_NS(p_dma_instance, global_it_flag); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t global_active_flag_s = IS_DMA_GLOBAL_ACTIVE_FLAG_S(p_dma_instance, global_it_flag); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Global Interrupt Flag management *********************************************************************************/ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if ((global_active_flag_s == 0U) && (global_active_flag_ns == 0U)) -#else - if (global_active_flag_ns == 0U) -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - { - return; /* the global interrupt flag for the current channel is down , nothing to do */ - } - - /* Data Transfer Error Interrupt management *************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_DTE) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_DTE) != 0U) - { - /* Clear the transfer error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_DTE); - - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_DTE; - } - } - - /* Update Linked-list Error Interrupt management ********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_ULE) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_ULE) != 0U) - { - /* Clear the update linked-list error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_ULE); - - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_ULE; - } - } - - /* User Setting Error Interrupt management **************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_USE) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_USE) != 0U) - { - /* Clear the user setting error flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_USE); - - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_USE; - } - } - - /* Trigger Overrun Interrupt management *****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TO) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TO) != 0U) - { - /* Clear the trigger overrun flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TO); - - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TO; - } - } - - /* Half Transfer Complete Interrupt management **********************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_HT) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != 0U) - { - /* Clear the half transfer flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_HT); - - /* Check half transfer complete callback */ - if (hdma->XferHalfCpltCallback != NULL) - { - /* Half transfer callback */ - hdma->XferHalfCpltCallback(hdma); - } - } - } - - /* Suspend Transfer Interrupt management ****************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_SUSP) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_SUSP) != 0U) - { - /* Clear the block transfer complete flag */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_SUSP); - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_ABORT) - { - /* Disable the suspend transfer interrupt */ - __HAL_DMA_DISABLE_IT(hdma, DMA_IT_SUSP); - - /* Reset the channel internal state and reset the FIFO */ - hdma->Instance->CCR |= DMA_CCR_RESET; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - - /* Clear remaining data size to ensure loading linked-list from memory next start */ - hdma->Instance->CBR1 = 0U; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Check transfer abort callback */ - if (hdma->XferAbortCallback != NULL) - { - /* Transfer abort callback */ - hdma->XferAbortCallback(hdma); - } - - return; - } - else - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_SUSPEND; - - /* Check transfer suspend callback */ - if (hdma->XferSuspendCallback != NULL) - { - /* Transfer suspend callback */ - hdma->XferSuspendCallback(hdma); - } - } - } - } - - /* Transfer Complete Interrupt management ***************************************************************************/ - if ((__HAL_DMA_GET_FLAG(hdma, DMA_FLAG_TC) != 0U)) - { - /* Check if interrupt source is enabled */ - if (__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != 0U) - { - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* If linked-list transfer */ - if (hdma->Instance->CLLR == 0U) - { - if (hdma->Instance->CBR1 == 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - } - } - } - else - { - /* If normal transfer */ - if (hdma->Instance->CBR1 == 0U) - { - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - } - } - - /* Clear TC and HT transfer flags */ - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT)); - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Check transfer complete callback */ - if (hdma->XferCpltCallback != NULL) - { - /* Channel Transfer Complete callback */ - hdma->XferCpltCallback(hdma); - } - } - } - - /* Manage error case ************************************************************************************************/ - if (hdma->ErrorCode != HAL_DMA_ERROR_NONE) - { - /* Reset the channel internal state and reset the FIFO */ - hdma->Instance->CCR |= DMA_CCR_RESET; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - /* Check DMA channel transfer mode */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - /* Update the linked-list queue state */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - /* Check transfer error callback */ - if (hdma->XferErrorCallback != NULL) - { - /* Transfer error callback */ - hdma->XferErrorCallback(hdma); - } - } -} - -/** - * @brief Register callback according to specified ID. - * @note The HAL_DMA_RegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET - * to register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enumeration. - * @param pCallback : Pointer to private callback function. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *const hdma, - HAL_DMA_CallbackIDTypeDef CallbackID, - void (*const pCallback)(DMA_HandleTypeDef *const _hdma)) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Check callback ID */ - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - { - /* Register transfer complete callback */ - hdma->XferCpltCallback = pCallback; - break; - } - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - { - /* Register half transfer callback */ - hdma->XferHalfCpltCallback = pCallback; - break; - } - - case HAL_DMA_XFER_ERROR_CB_ID: - { - /* Register transfer error callback */ - hdma->XferErrorCallback = pCallback; - break; - } - - case HAL_DMA_XFER_ABORT_CB_ID: - { - /* Register abort callback */ - hdma->XferAbortCallback = pCallback; - break; - } - - case HAL_DMA_XFER_SUSPEND_CB_ID: - { - /* Register suspend callback */ - hdma->XferSuspendCallback = pCallback; - break; - } - - default: - { - /* Update error status */ - status = HAL_ERROR; - break; - } - } - } - else - { - /* Update error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister callback according to specified ID. - * @note The HAL_DMA_UnRegisterCallback() may be called before HAL_DMA_Init() in HAL_DMA_STATE_RESET - * to un-register callbacks for HAL_DMA_MSPINIT_CB_ID and HAL_DMA_MSPDEINIT_CB_ID. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param CallbackID : User Callback identifier which could be a value of HAL_DMA_CallbackIDTypeDef enum. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *const hdma, - HAL_DMA_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Check callback ID */ - switch (CallbackID) - { - case HAL_DMA_XFER_CPLT_CB_ID: - { - /* UnRegister transfer complete callback */ - hdma->XferCpltCallback = NULL; - break; - } - - case HAL_DMA_XFER_HALFCPLT_CB_ID: - { - /* UnRegister half transfer callback */ - hdma->XferHalfCpltCallback = NULL; - break; - } - - case HAL_DMA_XFER_ERROR_CB_ID: - { - /* UnRegister transfer error callback */ - hdma->XferErrorCallback = NULL; - break; - } - - case HAL_DMA_XFER_ABORT_CB_ID: - { - /* UnRegister abort callback */ - hdma->XferAbortCallback = NULL; - break; - } - - case HAL_DMA_XFER_SUSPEND_CB_ID: - { - /* UnRegister suspend callback */ - hdma->XferSuspendCallback = NULL; - break; - } - - case HAL_DMA_XFER_ALL_CB_ID: - { - /* UnRegister all available callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - hdma->XferSuspendCallback = NULL; - break; - } - - default: - { - /* Update error status */ - status = HAL_ERROR; - break; - } - } - } - else - { - /* Update error status */ - status = HAL_ERROR; - } - - return status; -} -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group3 - * -@verbatim - ====================================================================================================================== - ##### State and Errors functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Check the DMA state - (+) Get error code - - [..] - (+) The HAL_DMA_GetState() function allows to get the DMA channel state. - (+) The HAL_DMA_DeInit() function allows to get the DMA channel error code. - -@endverbatim - * @{ - */ - -/** - * @brief Returns the DMA channel state. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval DMA state. - */ -HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef const *const hdma) -{ - /* Return the DMA channel state */ - return hdma->State; -} - -/** - * @brief Return the DMA channel error code. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval DMA Error Code. - */ -uint32_t HAL_DMA_GetError(DMA_HandleTypeDef const *const hdma) -{ - /* Return the DMA channel error code */ - return hdma->ErrorCode; -} -/** - * @} - */ - -/** @addtogroup DMA_Exported_Functions_Group4 - * -@verbatim - ====================================================================================================================== - ##### DMA Attributes functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Configure DMA channel secure and privilege attributes. - (+) Get DMA channel secure and privilege attributes. - (+) Lock DMA channel secure and privilege attributes configuration. - (+) Check whether DMA channel secure and privilege attributes configuration is locked or not. - - [..] - (+) The HAL_DMA_ConfigChannelAttributes() function allows to configure DMA channel security and privilege - attributes. - (+) The HAL_DMA_GetConfigChannelAttributes() function allows to get DMA channel security and privilege attributes - configuration. - (+) The HAL_DMA_LockChannelAttributes() function allows to lock the DMA channel security and privilege attributes. - (+) The HAL_DMA_GetLockChannelAttributes() function allows to get the DMA channel security and privilege - attributes lock status. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the DMA channel security and privilege attribute(s). - * @note These attributes cannot be modified when the corresponding lock state is enabled. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for - * the specified DMA Channel. - * @param ChannelAttributes : Specifies the DMA channel secure/privilege attributes. - * This parameter can be a one or a combination of @ref DMA_Channel_Attributes. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_DMA_ConfigChannelAttributes(DMA_HandleTypeDef *const hdma, uint32_t ChannelAttributes) -{ - DMA_TypeDef *p_dma_instance; - uint32_t channel_idx; - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ATTRIBUTES(ChannelAttributes)); - - /* Get DMA instance */ - p_dma_instance = GET_DMA_INSTANCE(hdma); - - /* Get channel index */ - channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); - - /* Check DMA channel privilege attribute management */ - if ((ChannelAttributes & DMA_CHANNEL_ATTR_PRIV_MASK) == DMA_CHANNEL_ATTR_PRIV_MASK) - { - /* Configure DMA channel privilege attribute */ - if ((ChannelAttributes & DMA_CHANNEL_PRIV) == DMA_CHANNEL_PRIV) - { - p_dma_instance->PRIVCFGR |= channel_idx; - } - else - { - p_dma_instance->PRIVCFGR &= (~channel_idx); - } - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Check DMA channel security attribute management */ - if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_MASK) == DMA_CHANNEL_ATTR_SEC_MASK) - { - /* Configure DMA channel security attribute */ - if ((ChannelAttributes & DMA_CHANNEL_SEC) == DMA_CHANNEL_SEC) - { - p_dma_instance->SECCFGR |= channel_idx; - } - else - { - p_dma_instance->SECCFGR &= (~channel_idx); - } - } - - /* Channel source security attribute management */ - if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_SRC_MASK) == DMA_CHANNEL_ATTR_SEC_SRC_MASK) - { - /* Configure DMA channel source security attribute */ - if ((ChannelAttributes & DMA_CHANNEL_SRC_SEC) == DMA_CHANNEL_SRC_SEC) - { - hdma->Instance->CTR1 |= DMA_CTR1_SSEC; - } - else - { - hdma->Instance->CTR1 &= (~DMA_CTR1_SSEC); - } - } - - /* Channel destination security attribute management */ - if ((ChannelAttributes & DMA_CHANNEL_ATTR_SEC_DEST_MASK) == DMA_CHANNEL_ATTR_SEC_DEST_MASK) - { - /* Configure DMA channel destination security attribute */ - if ((ChannelAttributes & DMA_CHANNEL_DEST_SEC) == DMA_CHANNEL_DEST_SEC) - { - hdma->Instance->CTR1 |= DMA_CTR1_DSEC; - } - else - { - hdma->Instance->CTR1 &= (~DMA_CTR1_DSEC); - } - } -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - return HAL_OK; -} - -/** - * @brief Get the DMA channel security and privilege attributes. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information - * for the specified DMA Channel. - * @param pChannelAttributes : Pointer to the returned attributes. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef const *const hdma, - uint32_t *const pChannelAttributes) -{ - const DMA_TypeDef *p_dma_instance; - uint32_t attributes; - uint32_t channel_idx; - - /* Check the DMA peripheral handle and channel attributes parameters */ - if ((hdma == NULL) || (pChannelAttributes == NULL)) - { - return HAL_ERROR; - } - - /* Get DMA instance */ - p_dma_instance = GET_DMA_INSTANCE(hdma); - - /* Get channel index */ - channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); - - /* Get DMA channel privilege attribute */ - attributes = ((p_dma_instance->PRIVCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NPRIV : DMA_CHANNEL_PRIV; - - /* Get DMA channel security attribute */ - attributes |= ((p_dma_instance->SECCFGR & channel_idx) == 0U) ? DMA_CHANNEL_NSEC : DMA_CHANNEL_SEC; - - /* Get DMA channel source security attribute */ - attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_SSEC) == 0U) ? DMA_CHANNEL_SRC_NSEC : DMA_CHANNEL_SRC_SEC; - - /* Get DMA channel destination security attribute */ - attributes |= ((hdma->Instance->CTR1 & DMA_CTR1_DSEC) == 0U) ? DMA_CHANNEL_DEST_NSEC : DMA_CHANNEL_DEST_SEC; - - /* return value */ - *pChannelAttributes = attributes; - - return HAL_OK; -} - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Lock the DMA channel security and privilege attribute(s). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_DMA_LockChannelAttributes(DMA_HandleTypeDef const *const hdma) -{ - DMA_TypeDef *p_dma_instance; - uint32_t channel_idx; - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Get DMA instance */ - p_dma_instance = GET_DMA_INSTANCE(hdma); - - /* Get channel index */ - channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); - - /* Lock the DMA channel privilege and security attributes */ - p_dma_instance->RCFGLOCKR |= channel_idx; - - return HAL_OK; -} -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @brief Get the security and privilege attribute lock state of a DMA channel. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param pLockState : Pointer to lock state (returned value can be DMA_CHANNEL_ATTRIBUTE_UNLOCKED or - * DMA_CHANNEL_ATTRIBUTE_LOCKED). - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMA_GetLockChannelAttributes(DMA_HandleTypeDef const *const hdma, uint32_t *const pLockState) -{ - DMA_TypeDef *p_dma_instance; - uint32_t channel_idx; - - /* Check the DMA peripheral handle and lock state parameters */ - if ((hdma == NULL) || (pLockState == NULL)) - { - return HAL_ERROR; - } - - /* Get DMA instance */ - p_dma_instance = GET_DMA_INSTANCE(hdma); - - /* Get channel index */ - channel_idx = 1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU); - - /* Get channel lock attribute state */ - *pLockState = ((p_dma_instance->RCFGLOCKR & channel_idx) == 0U) ? DMA_CHANNEL_ATTRIBUTE_UNLOCKED : \ - DMA_CHANNEL_ATTRIBUTE_LOCKED; - - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ - - -/* Private functions -------------------------------------------------------------------------------------------------*/ -/** @defgroup DMA_Private_Functions DMA Private Functions - * @brief DMA Private Functions - * @{ - */ - -/** - * @brief Set the DMA channel normal transfer parameters. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param SrcAddress : The source data address. - * @param DstAddress : The destination data address. - * @param SrcDataSize : The length of data to be transferred from source to destination in bytes. - * @retval None. - */ -static void DMA_SetConfig(DMA_HandleTypeDef const *const hdma, - uint32_t SrcAddress, - uint32_t DstAddress, - uint32_t SrcDataSize) -{ - /* Configure the DMA channel data size */ - MODIFY_REG(hdma->Instance->CBR1, DMA_CBR1_BNDT, (SrcDataSize & DMA_CBR1_BNDT)); - - /* Clear all interrupt flags */ - __HAL_DMA_CLEAR_FLAG(hdma, DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | - DMA_FLAG_TO); - - /* Configure DMA channel source address */ - hdma->Instance->CSAR = SrcAddress; - - /* Configure DMA channel destination address */ - hdma->Instance->CDAR = DstAddress; -} - -/** - * @brief Initialize the DMA channel in normal mode according to the specified parameters in the DMA_InitTypeDef. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval None. - */ -static void DMA_Init(DMA_HandleTypeDef const *const hdma) -{ - uint32_t tmpreg; - - /* Prepare DMA Channel Control Register (CCR) value *****************************************************************/ - tmpreg = hdma->Init.Priority; - - /* Write DMA Channel Control Register (CCR) */ - MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); - - /* Prepare DMA Channel Transfer Register (CTR1) value ***************************************************************/ - tmpreg = hdma->Init.DestInc | hdma->Init.DestDataWidth | hdma->Init.SrcInc | hdma->Init.SrcDataWidth; - - /* Add parameters specific to GPDMA */ - if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) - { - tmpreg |= (hdma->Init.TransferAllocatedPort | - (((hdma->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | - (((hdma->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); - } - - /* Write DMA Channel Transfer Register 1 (CTR1) */ - MODIFY_REG(hdma->Instance->CTR1, ~(DMA_CTR1_SSEC | DMA_CTR1_DSEC), tmpreg); - - /* Prepare DMA Channel Transfer Register 2 (CTR2) value *************************************************************/ - tmpreg = hdma->Init.BlkHWRequest | (hdma->Init.Request & DMA_CTR2_REQSEL) | hdma->Init.TransferEventMode; - - /* Memory to Peripheral Transfer */ - if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) - { - tmpreg |= DMA_CTR2_DREQ; - } - } - /* Memory to Memory Transfer */ - else if ((hdma->Init.Direction) == DMA_MEMORY_TO_MEMORY) - { - tmpreg |= DMA_CTR2_SWREQ; - } - else - { - /* Nothing to do */ - } - - /* Write DMA Channel Transfer Register 2 (CTR2) */ - MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TCEM | DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM | - DMA_CTR2_BREQ | DMA_CTR2_DREQ | DMA_CTR2_SWREQ | DMA_CTR2_REQSEL), tmpreg); - - - /* Write DMA Channel Block Register 1 (CBR1) ************************************************************************/ - WRITE_REG(hdma->Instance->CBR1, 0U); - - /* If 2D Addressing is supported by current channel */ - if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) - { - /* Write DMA Channel Transfer Register 3 (CTR3) *******************************************************************/ - WRITE_REG(hdma->Instance->CTR3, 0U); - - /* Write DMA Channel Block Register 2 (CBR2) **********************************************************************/ - WRITE_REG(hdma->Instance->CBR2, 0U); - } - - /* Write DMA Channel linked-list address register (CLLR) ************************************************************/ - WRITE_REG(hdma->Instance->CLLR, 0U); -} -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c deleted file mode 100644 index b8c6ac1ff..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_dma_ex.c +++ /dev/null @@ -1,4711 +0,0 @@ -/** - ********************************************************************************************************************** - * @file stm32u5xx_hal_dma_ex.c - * @author MCD Application Team - * @brief DMA Extension HAL module driver - * This file provides firmware functions to manage the following functionalities of the DMA extension - * peripheral: - * + Linked-List Initialization and De-Initialization Functions - * + Linked-List I/O Operation Functions - * + Linked-List Management Functions - * + Data Handling, Repeated Block and Trigger Configuration Functions - * + Suspend and Resume Operation Functions - * + FIFO Status Function - * - ********************************************************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ********************************************************************************************************************** - @verbatim - ====================================================================================================================== - ##### How to use this driver ##### - ====================================================================================================================== - [..] - Alternatively to the normal programming mode, a DMA channel can be programmed by a list of transfers, known as - linked-list (list of Node items). Each node is defined by its data structure. - Each node specifies a standalone DMA channel. - When enabled, the DMA channel fetch the first linked-list node from SRAM (known as head node). When executed, the - next linked list node will be fetched and executed. This operation is repeated until the end of the whole - linked-list queue. Optionally, the linked-list can be linear where the last linked-list queue node is not linked - to another queue node or circular where the last linked-list node is linked to any linked-list queue node. - - (+) Linear linked-list: - The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node - (tail node) ones. When the last node is completed, the DMA channel remains in idle state and another - transfer can be lunched. - - (+) Circular linked-list: - The DMA channel fetch and execute all DMA linked-list queue from first node (head node) to last node (tail - node). When last node is executed, the DMA channel fetches the first circular node another time and repeat - the same sequence in an infinite loop (Circular transfer). To stop the DMA channel, an abort operation is - required. This linked-list mode replaces the legacy circular transfers. - - [..] - In order to reduce linked-list queue executing time and power consumption, the DMA channel supports executing the - dynamic linked-list format. In fact, the DMA supports the execution of 2 types of linked-list formats : static and - dynamic. - - (+) Static linked-list: - The static linked-list format refers to the full linked-list node where all DMA channel parameters are - fetched and executed independently of the redundancy of information. - - (+) Dynamic linked-list: - The dynamic linked-list format refer to the customized linked-list node where only DMA channel necessary - parameters are fetched and executed (Example: data size = 20 on previous node, and data size = 20 on the - current node => No need to update it). - - For linked-list transfers, the DMA channel can execute the linked-list queue node by node. This feature is named - link step mode. When activated, enabling the DMA channel first time allows to fetch the head node from memory - then it stops. Then, another DMA channel enable is needed to execute the node. After that, keeping enabling the - DMA channel is needed to execute each node until the end of linked-list queue. When the linked-list queue is - circular, enabling the DMA channel in an infinite loop is required to keep the DMA channel running. This feature - is useful for debug purpose or asynchronously executing queue nodes. - - [..] - Each DMA channel transfer (normal or linked-list), is highly configurable according to DMA channel instance - integrated in devices. These configuration can be : - - (+) Repeated block configuration : - If the feature is supported, the DMA channel can performs a repeated block transfers. Named also 2 - dimension addressing transfers, this feature can transfer n iteration of programmed block transfer (Block - transfer is the legacy data size). Additional to the repeat count of a block, DMA channel addresses can - jump after at burst and block level. The jump length is a programmable parameter defined by DMA user. - (++) Jump at burst level : - The DMA channel keep an empty area, between each 2 consecutive bursts transmitted. - (++) Jump at block level : - The DMA channel keep an empty area, between each 2 consecutive blocks transmitted. - - (+) Trigger : - The DMA channel transfers can be conditioned by hardware signals edges (rising or falling) named hardware - triggers. Trigger condition can be applied at : - (++) Single/Burst level : - Each single/burst data transmission is conditioned by a signal trigger hit. - (++) Block level : - Each block data transmission is conditioned by a signal trigger hit. - (++) Repeated block level : - Each repeated block data transmission is conditioned by a signal trigger hit. - (++) Node level : - Each node execution is conditioned by a signal trigger hit. - The DMA channel can report a trigger overrun when detects more than 2 trigger signal edges before - executing the current transfer. - - (+) Data handling : - The data handling feature is a FIFO capability that can be : - (++) Padding pattern : - Padding selected pattern (zero padding or sign extension) when the source data width is smaller - than the destination data width at single level. - (++) Truncation : - Truncate section from the source data single when the source data width is bigger than the - destination data width. - (++) Pack/Unpack : - Pack a set of data when source data width is smaller than the destination data width. - Unpack a set of data when source data width is bigger than the destination data width. - (++) Exchange : - Exchange data at byte and half-word on the destination and at byte level on the source. - - [..] - Each DMA channel transfer (normal or linked-list) when it is active, can be suspended and resumed at run time - application. When trying to suspend an ongoing transfer, the DMA channel isn't suspended instantly but complete - the current ongoing single/burst then it stops. - When the DMA channel is suspended, the current transfer can be resumed instantly. - - [..] - The DMA channel that supports FIFO, can report in real time the number of beats remains on destination (Output) - FIFO level. - - *** Linked-List Initialization and De-Initialization operation *** - ================================================================== - [..] - Differently from normal transfers, DMA channel initialization and de-initialization need less parameters as the - remaining transfer parameters are defined by linked-list nodes. - - (+) Use HAL_DMAEx_List_Init() to initialize a DMA channel in linked-list mode according to programmed fields. - When called, the DMA channel will be ready to execute linked-list queues. - - (+) Use HAL_DMAEx_List_DeInit() to de-initialize a DMA channel in linked-list mode. - When called, the DMA channel will be in reset. It is mandatory to reinitialize it for next transfer. - - *** Linked-List I/O Operation *** - ================================= - [..] - (+) Use HAL_DMAEx_List_Start() to start a DMA transfer in linked-list mode after the configuration of - linked-list queue base address and offset in polling mode (Blocking mode). - - (+) Use HAL_DMAEx_List_Start_IT() to start a DMA transfer in linked-list mode after the configuration of - linked-list queue base address and offset in interrupt mode (Non-blocking mode). - - *** Linked-List Management *** - ============================== - [..] - The linked-list management is a software processing independently of DMA channel hardware. It allows to reset, - build, create, insert, remove, replace, circularize, convert both nodes and queue in order to perform DMA - channel transfers in linked-list mode. - Linked-list APIs and types are adapted to reduce memory footprint. - - *** Linked-list nodes building *** - [..] - At node level, the operations that can be done are building a new linked-list node or get a linked-list node - information from a built node. The linked-list nodes have two forms according to 2 dimensions addressing - capability. The linear addressing nodes contains the information of all DMA channel features except the 2 - dimension addressing features and the 2 dimensions addressing nodes contain the information of all available - features. - - (+) Use HAL_DMAEx_List_BuildNode() to build the DMA linked-list node according to the specified parameters. - Build operation allow to convert the specified parameter in values known by the DMA channel and place them - in memory. - Placing DMA linked-list in SRAM must be done in accordance to product specification to ensure that the - link access port can access to the specified SRAM. - (++) The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte - addressable space. - - (+) Use HAL_DMAEx_List_GetNodeConfig() to get the specified configuration parameter on building node. - This API can be used when need to change few parameter to build new node. - - *** Inserting nodes to linked-list queue *** - [..] - In order to build a sequence of DMA transaction with different configuration, we need to insert built node at - linked-list queue (node present an elementary DMA transaction) in linked-list queue on any position to have the - full flexibility of ordering nodes or extend the sequence of queue transactions. - - (+) Use HAL_DMAEx_List_InsertNode() to insert new built node in any queue position of linked-list queue - according to selecting previous node. When calling this API with previous node parameter is NULL, the - inserted node will be placed at the head of the linked-list queue. - (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. - (++) This API must be called for static queues format. - (++) This API shall be avoided when adding new node at the head or the tail of queue (overhead of - footprint and performance : use HAL_DMAEx_List_InsertNode_Head() or HAL_DMAEx_List_InsertNode_Tail() - instead). - - (+) Use HAL_DMAEx_List_InsertNode_Head() to insert new built node at the head of linked-list queue. The head - node will not be overwritten but will be the second queue node. - (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. - (++) This API must be called for static queues format. - - (+) Use HAL_DMAEx_List_InsertNode_Tail() to insert new built node at the tail of linked-list queue. The tail - node will not be overwritten but will be the penultimate queue node. - (++) This API must be used after HAL_DMAEx_List_BuildNode() otherwise an error will be returned. - (++) This API must be called for static queues format. - - *** Removing nodes from linked-list queue *** - [..] - There is some cases when removing a node from linked-list queue is needed (need to remove an elementary DMA - transaction). Removing node allows to unlink a node from DMA linked-list queue (NOT DELETED), so the removed node - can be reused for another queue or to be added to the same queue without need to rebuild it in next step. - - (+) Use HAL_DMAEx_List_RemoveNode() to remove any yet built and inserted node from linked-list queue according - to selected node. - (++) This API must be called for static queues format. - (++) This API shall be avoided when removing the head or the tail of linked-list queue (overhead of - footprint and performance : use HAL_DMAEx_List_RemoveNode_Head() or HAL_DMAEx_List_RemoveNode_Tail() - instead). - - (+) Use HAL_DMAEx_List_RemoveNode_Head() to remove the head node from linked-list queue. - (++) This API must be called for static queues format. - - (+) Use HAL_DMAEx_List_RemoveNode_Tail() to remove the tail node from linked-list queue. - (++) This API must be called for static queues format. - - *** Replacing nodes on linked-list queue *** - [..] - There is some cases when replacing a node from linked-list queue is needed (need to replace an elementary DMA - transfer, by another one that have not the same configuration). Replacing node allows to unlink the node to be - replaced from DMA linked-list queue (NOT DELETED) and link instead a new node. So the replaced node can be reused - for another queue or to be added to the same queue without need to rebuild it in next step and the new node cannot - be reused except when remove it or replaced in next step. - - (+) Use HAL_DMAEx_List_ReplaceNode() to replace any yet built and inserted node on linked-list queue according - to selected node. - (++) This API must be called for static queues format. - (++) This API shall be avoided when replacing the head or the tail linked-list queue (overhead of - footprint and performance : use HAL_DMAEx_List_ReplaceNode_Head() or - HAL_DMAEx_List_ReplaceNode_Tail() instead). - - (+) Use HAL_DMAEx_List_ReplaceNode_Head() to replace the head node of linked-list queue. - (++) This API must be called for static queues format. - - (+) Use HAL_DMAEx_List_ReplaceNode_Tail() to replace the tail node from linked-list queue. - (++) This API must be called for static queues format. - - *** Reset linked-list queue *** - [..] - After finishing using a linked-list queue, it can be reset and cleared and it's content nodes will be - unlinked (NOT DELETED) and reused on another queue. - - (+) Use HAL_DMAEx_List_ResetQ() to reset a linked-list queue and unlink all it's content nodes. - (++) This API must be called for ready state queues. - (++) This API must be called for static queues format. - - *** Inserting linked-list queue *** - [..] - To ensure the flexibility of building linked-list queue by their targeted functionalities (Example: 3 nodes for - action 1 and 5 nodes for action 2), it is possible to build a queue for action 1 that contains action 1 nodes and - a queue for action 2 that contains action 2 nodes then concatenating the 2 queues. So, there are some cases where - the management of linked-list at queue granularity is needed. - - (+) Use HAL_DMAEx_List_InsertQ() to insert source linked-list queue to a destination linked-list queue - according to selecting previous node. - (++) This API must be called for static queues format. - (++) This API shall be avoided when inserting source linked-list queue at the head or the tail of - destination queue (overhead of footprint and performance : use HAL_DMAEx_List_InsertQ_Head() or - HAL_DMAEx_List_InsertQ_Tail() instead). - - (+) Use HAL_DMAEx_List_InsertQ_Head() to insert a source linked-list queue at the head of linked-list - destination queue. - (++) This API must be called for static queues format. - - (+) Use HAL_DMAEx_List_InsertQ_Tail() to insert a source linked-list queue at the tail of linked-list - destination queue. - (++) This API must be called for static queues format. - - *** Circularizing linked-list queue *** - [..] - In order to perform tasks in infinite loop with DMA channel, it is possible to circularize the linked-list queues. - Circularizing queue allows to link last linked-list queue node to any previous node of the same queue (This node - is named first circular queue). When the first circular node is the head node, all linked-list queue nodes will be - executed in infinite loop. When the first circular node is not the head nodes, all precedent nodes are executed - once and all remaining nodes are executed in an infinite loop. - - (+) Use HAL_DMAEx_List_SetCircularModeConfig() to circularize the linked-list queue according to first - circular node selected. - (++) This API must be called for static queues format. - (++) This API shall be avoided when first circular node is the head linked-list queue node (overhead of - footprint and performance : use HAL_DMAEx_List_SetCircularMode() instead). - - (+) Use HAL_DMAEx_List_SetCircularMode() to circularize the linked-list queue with linking last queue node - with first queue node. - (++) This API must be called for static queues format. - - (+) Use HAL_DMAEx_List_ClearCircularMode() to clear any linked-list queue circular configuration. - (++) This API must be called for static queues format. - - - *** Converting linked-list queue *** - [..] - To have the best DMA channel linked-list queue execution, it is recommended to convert yet build linked-list queue - to dynamic format (Static is the default format). When linked-list queue becomes dynamic, all queue nodes are - optimized and only changed parameters will be updated between nodes. So, the DMA will fetch only changes - parameters instead of the whole node. - - (+) Use HAL_DMAEx_List_ConvertQToDynamic() to convert a linked-list queue to dynamic format. - (++) This API must be called for ready state queues. - (++) This API must be called for static queues format. - (++) This API must be called as the last API before starting the DMA channel in linked-list mode. - - (+) Use HAL_DMAEx_List_ConvertQToStatic() to convert a linked-list queue to static format. - (++) This API must be called for ready state queues. - (++) This API must be called for dynamic queues format. - (++) This API must be called as the first API after the full execution of linked-list queue when the - execution mode is linear (not circular) if it is dynamic and a linked-list queue management is - needed. - (++) This API must be called as the first API after the aborting the execution of the current linked-list - queue when the execution mode is linear (not circular) if it is dynamic and a linked-list queue - management is needed. - - [..] - When converting a circular queue to dynamic format and when the first circular node is the last queue node, it is - recommended to duplicate the last circular node in order to ensure the full optimization when calling - HAL_DMAEx_List_ConvertQToDynamic() API. In this case, updated information are only addresses which allow to reduce - 4 words of update for linear nodes per node execution and 6 words update for 2 dimensions addressing nodes per - node execution. - - - *** Linking linked-list queue to DMA channel *** - [..] - In order to have the possibility of the creation of an infinity queues (limited by available memory size), the - building of linked-list queue is fully independent from DMA channels. It is possible to build all needed queues if - their size is less then available memory at startup time, then linking each time when needed a linked-list queue - to an idle DMA channel. - - (+) Use HAL_DMAEx_List_LinkQ() to link a ready linked-list queue to ready DMA channel. - (++) This API supports the two format of linked-list (Static and dynamic). - (++) This API must be called for ready state queues and DMA channels. - - (+) Use HAL_DMAEx_List_ConvertQToStatic() to unlink a ready linked-list queue to ready DMA channel. - (++) This API supports the two format of linked-list (Static and dynamic). - (++) This API must be called for ready state queues and DMA channels. - - *** User sequence *** - [..] - To use cleanly the DMA linked-list library, ensure to apply the following call sequences : - - (+) Linear transfer : - Linked-list queue building - (++) HAL_DMAEx_List_BuildNode() - (++) HAL_DMAEx_List_InsertNode_Tail() - . - . - . - (++) HAL_DMAEx_List_BuildNode() - (++) HAL_DMAEx_List_InsertNode_Tail() - (++) HAL_DMAEx_List_ConvertQToDynamic() - Linked-list queue execution - (++) HAL_DMAEx_List_Init() - (++) HAL_DMAEx_List_LinkQ() - (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() - (++) HAL_DMAEx_List_UnLinkQ() - (++) HAL_DMAEx_List_DeInit() - - (+) Circular transfer : - Linked-list queue building - (++) HAL_DMAEx_List_BuildNode() - (++) HAL_DMAEx_List_InsertNode_Tail() - . - . - . - (++) HAL_DMAEx_List_BuildNode() - (++) HAL_DMAEx_List_InsertNode_Tail() - (++) HAL_DMAEx_List_SetCircularModeConfig() / HAL_DMAEx_List_SetCircularMode() - (++) HAL_DMAEx_List_ConvertQToDynamic() - Linked-list queue execution - (++) HAL_DMAEx_List_Init() - (++) HAL_DMAEx_List_LinkQ() - (++) HAL_DMAEx_List_Start() / HAL_DMAEx_List_Start_IT() - (++) HAL_DMA_Abort() / HAL_DMA_Abort_IT() - (++) HAL_DMAEx_List_UnLinkQ() - (++) HAL_DMAEx_List_DeInit() - - - *** Data Handling *** - ===================== - [..] - In order to avoid some CPU data processing in several cases, the DMA channel provides some features related to - FIFO capabilities titled data handling. - (++) Padding pattern - Padding selected pattern (zero padding or sign extension) when the source data width is smaller - than the destination data width at single level. - Zero padding (Source : 0xABAB ------> Destination : 0xABAB0000) - Sign bit extension (Source : 0x0ABA ------> Destination : 0x00000ABA) - (Source : 0xFABA ------> Destination : 0xFFFFFABA) - (++) Truncation : - Truncate section from the source data single when the source data width is bigger than the - destination data width. - Left truncation (Source : 0xABABCDCD ------> Destination : 0xCDCD) - Right truncation (Source : 0xABABCDCD ------> Destination : 0xABAB) - (++) Pack/Unpack : - Pack a set of data when source data width is smaller than the destination data width. - Unpack a set of data when source data width is bigger than the destination data width. - Pack (Source : 0xAB, 0xCD ------> Destination : 0xABCD) - UnPack (Source : 0xABCD ------> Destination : 0xAB, 0xCD) - (++) Exchange : - Exchange data at byte and half-word on the destination and at byte level on the source. - Considering source and destination are both word type. Exchange operation can be as follows. - In examples below, one exchange setting is enabled at a time. - Source byte exchange only (Source : 0xAB12CD34 ------> Destination : 0xABCD1234) - Destination byte exchange only (Source : 0xAB12CD34 ------> Destination : 0x12AB34CD) - Destination half-word exchange only (Source : 0xAB12CD34 ------> Destination : 0xCD34AB12) - - (+) Use HAL_DMAEx_ConfigDataHandling() to configure data handling features. Previous elementary explained - can be combined according to application needs. - (++) This API is complementary of normal transfers. - (++) This API must not be called for linked-list transfers as data handling information are configured at - node level. - - *** User sequence *** - [..] - To configure cleanly the DMA channel data handling, ensure to apply the following call sequence : - - (+) Linear transfer : - (++) HAL_DMA_Init() - (++) HAL_DMAEx_ConfigDataHandling() - (++) HAL_DMA_Start() - - *** Repeated Block *** - ====================== - [..] - When available, this feature is used when the data size is higher then 65535 bytes (Maximum block size) or for - scattering / gathering data. - (++) Gather data - Source Destination - 0xAA 0xAA - 0xBB 0xAA - 0xAA ==> 0xAA - 0xCC - 0xAA - (++) Scatter data - Source Destination - 0xAA 0xAA - 0xAA 0xBB - 0xAA ==> 0xAA - 0xBB - 0xAA - - (+) Use HAL_DMAEx_ConfigRepeatBlock() to configure data repeated block feature. Jump addresses and - incrementing or decrementing on source and destination can be combined to have the need application - behavior. - (++) This API is complementary of normal transfers. - (++) This API must not be called for linked-list transfers as repeated block information are configured at - node level. - (++) This API must be called only for DMA channel that supports repeated block feature. - - *** User sequence *** - [..] - To configure cleanly the DMA channel repeated block, ensure to apply the following call sequence : - - (+) Linear transfer : - (++) HAL_DMA_Init() - (++) HAL_DMAEx_ConfigRepeatBlock() - (++) HAL_DMA_Start() - - *** Trigger Configuration *** - ============================= - [..] - When application needs that DMA transfers are conditioned by internal or external events, the trigger feature can - do that. Trigger signals are a set of device signal that are linked to DMA trigger inputs that allows to start the - DMA transfers. - To setup a trigger transfers, three DMA channel parameters are needed: - - (+) Trigger mode - This parameter specifies the trig level. - (++) Block level - (++) Repeated block level - (++) Node level - (++) Single / Burst level - - (+) Trigger polarity - This parameter specifies the DMA trigger sensitivity (Rising or falling). - - (+) Trigger selection - This parameter specifies the DMA trigger hardware signal. - - (+) Use HAL_DMAEx_ConfigTrigger() to configure trigger feature. - (++) This API is complementary to normal transfers APIs. - (++) This API must not be called for linked-list transfers as trigger information are configured at - node level. - - *** User sequence *** - [..] - To configure cleanly the DMA channel trigger, ensure to apply the following call sequence : - (+) Linear transfer : - (++) HAL_DMA_Init() - (++) HAL_DMAEx_ConfigTrigger() - (++) HAL_DMA_Start() - - *** Suspend and resume operation *** - ==================================== - [..] - There are several cases when needs to suspend a DMA current transfer (Example: liberate bandwidth for more - priority DMA channel transfer). Suspending DMA channel (same as abort) is available in polling (blocking mode) and - interrupt (non-blocking mode) modes. When suspended, a DMA channel can be instantly resumed. - - (+) Use HAL_DMAEx_Suspend() to suspend an ongoing DMA channel transfer in polling mode (Blocking mode). - - (+) Use HAL_DMAEx_Suspend_IT() to suspend an ongoing DMA channel transfer in interrupt mode (Non-blocking - mode). - - (+) Use HAL_DMAEx_Resume() to resume a suspended DMA channel transfer execution. - - *** FIFO status *** - =================== - [..] - In several cases, the information of FIFO level is useful to inform at application level how to process remaining - data. When not empty, the DMA channel FIFO cannot be flashed only by reset. - - (+) Use HAL_DMAEx_GetFifoLevel() to get the DMA channel FIFO level (available beats in FIFO). - - @endverbatim - ********************************************************************************************************************** - */ - -/* Includes ----------------------------------------------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup DMAEx DMAEx - * @brief DMA Extended HAL module driver - * @{ - */ - -#ifdef HAL_DMA_MODULE_ENABLED - -/* Private types -----------------------------------------------------------------------------------------------------*/ -/* Private variables -------------------------------------------------------------------------------------------------*/ -/* Private Constants -------------------------------------------------------------------------------------------------*/ -/* Private macros ----------------------------------------------------------------------------------------------------*/ -/* Private function prototypes ---------------------------------------------------------------------------------------*/ -static void DMA_List_Init(DMA_HandleTypeDef const *const hdma); -static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, - DMA_NodeTypeDef *const pNode); -static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, - DMA_NodeTypeDef const *const pNode); -static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, - DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3); -static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, - DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3); -static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, - uint32_t *const cllr_mask, - uint32_t *const cllr_offset); -static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, - DMA_NodeTypeDef const *const pNode, - DMA_NodeInQInfoTypeDef *const NodeInfo); -static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, - DMA_NodeInQInfoTypeDef const *const NodeInfo); -static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, - DMA_NodeTypeDef *const pDestNode); -static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, - uint32_t CurrentNodeAddr, - uint32_t RegisterNumber); -static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, - uint32_t CurrentNodeAddr, - uint32_t RegisterNumber); -static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, - uint32_t LastNode_IsCircular); -static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, - uint32_t operation); -static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, - uint32_t RegisterIdx, - uint32_t RegisterNumber, - uint32_t Format); -static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, - uint32_t FirstUnusedField); -static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList); - -/* Exported functions ------------------------------------------------------------------------------------------------*/ - -/** @addtogroup DMAEx_Exported_Functions - * @{ - */ - -/** @addtogroup DMAEx_Exported_Functions_Group1 - * -@verbatim - ====================================================================================================================== - ##### Linked-List Initialization and De-Initialization Functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to initialize and de-initialize the DMA channel in linked-list mode. - [..] - (+) The HAL_DMAEx_List_Init() function follows the DMA channel linked-list mode configuration procedures as - described in reference manual. - (+) The HAL_DMAEx_List_DeInit() function allows to de-initialize the DMA channel in linked-list mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the DMA channel in linked-list mode according to the specified parameters in the - * DMA_InitLinkedListTypeDef and create the associated handle. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_Init(DMA_HandleTypeDef *const hdma) -{ - /* Get tick number */ - uint32_t tickstart = HAL_GetTick(); - - /* Check the DMA channel handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_PRIORITY(hdma->InitLinkedList.Priority)); - assert_param(IS_DMA_LINK_STEP_MODE(hdma->InitLinkedList.LinkStepMode)); - assert_param(IS_DMA_TCEM_LINKEDLIST_EVENT_MODE(hdma->InitLinkedList.TransferEventMode)); - assert_param(IS_DMA_LINKEDLIST_MODE(hdma->InitLinkedList.LinkedListMode)); - /* Check DMA channel instance */ - if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) - { - assert_param(IS_DMA_LINK_ALLOCATED_PORT(hdma->InitLinkedList.LinkAllocatedPort)); - } - - /* Allocate lock resource */ - __HAL_UNLOCK(hdma); - - /* Change DMA peripheral state */ - hdma->State = HAL_DMA_STATE_BUSY; - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA channel is effectively disabled */ - while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Initialize the DMA channel registers */ - DMA_List_Init(hdma); - - /* Update DMA channel operation mode */ - hdma->Mode = hdma->InitLinkedList.LinkedListMode; - - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitialize the DMA channel when it is configured in linked-list mode. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_DeInit(DMA_HandleTypeDef *const hdma) -{ - - /* Get DMA instance */ - DMA_TypeDef *p_dma_instance; - - /* Get tick number */ - uint32_t tickstart = HAL_GetTick(); - - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - - - /* Get DMA instance */ - p_dma_instance = GET_DMA_INSTANCE(hdma); - - /* Disable the selected DMA Channel */ - __HAL_DMA_DISABLE(hdma); - - /* Check if the DMA channel is effectively disabled */ - while ((hdma->Instance->CCR & DMA_CCR_EN) != 0U) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update error code */ - hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; - - /* Change the DMA state */ - hdma->State = HAL_DMA_STATE_ERROR; - - return HAL_ERROR; - } - } - - /* Reset DMA Channel registers */ - hdma->Instance->CCR = 0U; - hdma->Instance->CLBAR = 0U; - hdma->Instance->CTR1 = 0U; - hdma->Instance->CTR2 = 0U; - hdma->Instance->CBR1 = 0U; - hdma->Instance->CSAR = 0U; - hdma->Instance->CDAR = 0U; - hdma->Instance->CLLR = 0U; - - /* Reset 2D Addressing registers */ - if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) - { - hdma->Instance->CTR3 = 0U; - hdma->Instance->CBR2 = 0U; - } - - - /* Clear privilege attribute */ - CLEAR_BIT(p_dma_instance->PRIVCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); - - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Clear secure attribute */ - CLEAR_BIT(p_dma_instance->SECCFGR, (1UL << (GET_DMA_CHANNEL(hdma) & 0x1FU))); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Clear all flags */ - __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC | DMA_FLAG_HT | DMA_FLAG_DTE | DMA_FLAG_ULE | DMA_FLAG_USE | DMA_FLAG_SUSP | - DMA_FLAG_TO)); - - /* Clean all callbacks */ - hdma->XferCpltCallback = NULL; - hdma->XferHalfCpltCallback = NULL; - hdma->XferErrorCallback = NULL; - hdma->XferAbortCallback = NULL; - hdma->XferSuspendCallback = NULL; - - /* Check the linked-list queue */ - if (hdma->LinkedListQueue != NULL) - { - /* Update the queue state and error code */ - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_READY; - hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Clean DMA queue */ - hdma->LinkedListQueue = NULL; - } - - /* Clean DMA parent */ - if (hdma->Parent != NULL) - { - hdma->Parent = NULL; - } - - /* Update DMA channel operation mode */ - hdma->Mode = DMA_NORMAL; - - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hdma); - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup DMAEx_Exported_Functions_Group2 - * -@verbatim - ====================================================================================================================== - ##### Linked-List IO Operation Functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Configure to start DMA transfer in linked-list mode. - - [..] - (+) The HAL_DMAEx_List_Start() function allows to start the DMA channel transfer in linked-list mode (Blocking - mode). - (+) The HAL_DMAEx_List_Start_IT() function allows to start the DMA channel transfer in linked-list mode - (Non-blocking mode). - (++) It is mandatory to register a linked-list queue to be executed by a DMA channel before starting - transfer otherwise a HAL_ERROR will be returned. - -@endverbatim - * @{ - */ - -/** - * @brief Start the DMA channel transfer in linked-list mode (Blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_Start(DMA_HandleTypeDef *const hdma) -{ - HAL_DMA_StateTypeDef dma_state; - uint32_t ccr_value; - uint32_t cllr_mask; - - /* Check the DMA peripheral handle and the linked-list queue parameters */ - if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - dma_state = hdma->State; - ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; - if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) - { - /* Check DMA channel state is ready */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Process locked */ - __HAL_LOCK(hdma); - - /* Update the DMA channel and the queue states */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the DMA channel and the queue error codes */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); - - /* Update DMA registers for linked-list transfer */ - hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); - hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; - } - - /* Enable DMA channel */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Starts the DMA channel transfer in linked-list mode with interrupts enabled (Non-blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_Start_IT(DMA_HandleTypeDef *const hdma) -{ - HAL_DMA_StateTypeDef dma_state; - uint32_t ccr_value; - uint32_t cllr_mask; - - /* Check the DMA peripheral handle and the linked-list queue parameters */ - if ((hdma == NULL) || (hdma->LinkedListQueue == NULL)) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - dma_state = hdma->State; - ccr_value = hdma->Instance->CCR & DMA_CCR_LSM; - if ((dma_state == HAL_DMA_STATE_READY) || ((dma_state == HAL_DMA_STATE_BUSY) && (ccr_value != 0U))) - { - /* Check DMA channel state is ready */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Process locked */ - __HAL_LOCK(hdma); - - /* Update the DMA channel and the queue states */ - hdma->State = HAL_DMA_STATE_BUSY; - hdma->LinkedListQueue->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the DMA channel and the queue error codes */ - hdma->ErrorCode = HAL_DMA_ERROR_NONE; - hdma->LinkedListQueue->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Enable common interrupts: Transfer Complete and Transfer Errors ITs */ - __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_DTE | DMA_IT_ULE | DMA_IT_USE | DMA_IT_TO)); - - /* Check half transfer complete callback */ - if (hdma->XferHalfCpltCallback != NULL) - { - /* If half transfer complete callback is set, enable the corresponding IT */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT); - } - - /* Check suspend callback */ - if (hdma->XferSuspendCallback != NULL) - { - /* If transfer suspend callback is set, enable the corresponding IT */ - __HAL_DMA_ENABLE_IT(hdma, DMA_IT_SUSP); - } - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(hdma->LinkedListQueue->Head, &cllr_mask, NULL); - - /* Update DMA registers for linked-list transfer */ - hdma->Instance->CLBAR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLBAR_LBA); - hdma->Instance->CLLR = ((uint32_t)hdma->LinkedListQueue->Head & DMA_CLLR_LA) | cllr_mask; - } - - /* Enable DMA channel */ - __HAL_DMA_ENABLE(hdma); - } - else - { - /* Change the error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup DMAEx_Exported_Functions_Group3 - * -@verbatim - ====================================================================================================================== - ##### Linked-List Management Functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Build linked-list node. - (+) Get linked-list node configuration. - (+) Insert node to linked-list queue in any queue position. - (+) Remove any node from linked-list queue. - (+) Replace any node from linked-list queue. - (+) Reset linked-list queue. - (+) Insert linked-list queue in any queue position. - (+) Set circular mode configuration to linked-list queue. - (+) Clear circular mode configuration from linked-list queue. - (+) Convert static linked-list queue to dynamic format. - (+) Convert dynamic linked-list queue to static format. - (+) Link linked-list queue to DMA channel. - (+) Unlink linked-list queue from DMA channel. - - [..] - (+) The HAL_DMAEx_List_BuildNode() function allows to build linked-list node. - Node type can be : - (++) 2 dimensions addressing node. - (++) Linear addressing node. - - (+) The HAL_DMAEx_List_GetNodeConfig() function allows to get the linked-list node configuration from built node. - - (+) The HAL_DMAEx_List_InsertNode() function allows to insert built linked-list node to static linked-list queue - according to selected position. - - (+) The HAL_DMAEx_List_InsertNode_Head() and HAL_DMAEx_List_InsertNode_Tail() functions allow to insert built - linked-list node to the head (respectively the tail) of static linked-list queue. - - (+) The HAL_DMAEx_List_RemoveNode() function allows to remove selected built linked-list node from static - linked-list queue. - - (+) The HAL_DMAEx_List_RemoveNode_Head() and HAL_DMAEx_List_RemoveNode_Tail() functions allow to remove the head - (respectively the tail) built linked-list node from static linked-list queue. - - (+) The HAL_DMAEx_List_ReplaceNode() function allows to replace selected built linked-list node from static - linked-list queue. - - (+) The HAL_DMAEx_List_ReplaceNode_Head() and HAL_DMAEx_List_ReplaceNode_Tail() functions allow to replace the - head (respectively the tail) built linked-list node of static linked-list queue. - - (+) The HAL_DMAEx_List_ResetQ() function allows to reset static linked-list queue and unlink all built linked-list - nodes. - - (+) The HAL_DMAEx_List_InsertQ() function allows to insert static linked-list source queue to static linked-list - destination queue according to selected position. - - (+) The HAL_DMAEx_List_InsertQ_Head() and HAL_DMAEx_List_InsertQ_Tail() functions allow to insert static - linked-list source queue to the head (respectively the tail) of static linked-list destination queue. - - (+) The HAL_DMAEx_List_SetCircularModeConfig() function allows to link the last static linked-list queue node to - the selected first circular node. - - (+) The HAL_DMAEx_List_SetCircularMode() function allows to link the last static linked-list queue node to the - first static linked-list queue node. - - (+) The HAL_DMAEx_List_ClearCircularMode() function allows to unlink the last static linked-list queue node from - any first circular node position. - - (+) The HAL_DMAEx_List_ConvertQToDynamic() function allows to convert the static linked-list queue to dynamic - format. (Optimized queue execution) - - (+) The HAL_DMAEx_List_ConvertQToStatic() function allows to convert the dynamic linked-list queue to static - format. (Not optimized queue execution) - - (+) The HAL_DMAEx_List_LinkQ() function allows to link the (Dynamic / Static) linked-list queue to DMA channel to - be executed. - - (+) The HAL_DMAEx_List_UnLinkQ() function allows to unlink the (Dynamic / Static) linked-list queue from DMA - channel when execution is completed. - -@endverbatim - * @{ - */ - -/** - * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. - * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the - * specified DMA linked-list Node. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @note The DMA linked-list node parameter address should be 32bit aligned and should not exceed the 64 KByte - * addressable space. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, - DMA_NodeTypeDef *const pNode) -{ - /* Check the node configuration and physical node parameters */ - if ((pNodeConfig == NULL) || (pNode == NULL)) - { - return HAL_ERROR; - } - - /* Check node type parameter */ - assert_param(IS_DMA_NODE_TYPE(pNodeConfig->NodeType)); - - /* Check DMA channel basic transfer parameters */ - assert_param(IS_DMA_SOURCE_INC(pNodeConfig->Init.SrcInc)); - assert_param(IS_DMA_DESTINATION_INC(pNodeConfig->Init.DestInc)); - assert_param(IS_DMA_SOURCE_DATA_WIDTH(pNodeConfig->Init.SrcDataWidth)); - assert_param(IS_DMA_DESTINATION_DATA_WIDTH(pNodeConfig->Init.DestDataWidth)); - assert_param(IS_DMA_DATA_ALIGNMENT(pNodeConfig->DataHandlingConfig.DataAlignment)); - assert_param(IS_DMA_REQUEST(pNodeConfig->Init.Request)); - assert_param(IS_DMA_DIRECTION(pNodeConfig->Init.Direction)); - assert_param(IS_DMA_TCEM_EVENT_MODE(pNodeConfig->Init.TransferEventMode)); - assert_param(IS_DMA_BLOCK_HW_REQUEST(pNodeConfig->Init.BlkHWRequest)); - assert_param(IS_DMA_MODE(pNodeConfig->Init.Mode)); - - /* Check DMA channel parameters */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) - { - assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.SrcBurstLength)); - assert_param(IS_DMA_BURST_LENGTH(pNodeConfig->Init.DestBurstLength)); - assert_param(IS_DMA_DATA_EXCHANGE(pNodeConfig->DataHandlingConfig.DataExchange)); - assert_param(IS_DMA_TRANSFER_ALLOCATED_PORT(pNodeConfig->Init.TransferAllocatedPort)); - } - - /* Check DMA channel trigger parameters */ - assert_param(IS_DMA_TRIGGER_POLARITY(pNodeConfig->TriggerConfig.TriggerPolarity)); - if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) - { - assert_param(IS_DMA_TRIGGER_MODE(pNodeConfig->TriggerConfig.TriggerMode)); - assert_param(IS_DMA_TRIGGER_SELECTION(pNodeConfig->TriggerConfig.TriggerSelection)); - } - - /* Check DMA channel repeated block parameters */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - assert_param(IS_DMA_REPEAT_COUNT(pNodeConfig->RepeatBlockConfig.RepeatCount)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset)); - } - - /* Check DMA channel security and privilege attributes parameters */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->SrcSecure)); - assert_param(IS_DMA_ATTRIBUTES(pNodeConfig->DestSecure)); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Build the DMA channel node */ - DMA_List_BuildNode(pNodeConfig, pNode); - - return HAL_OK; -} - -/** - * @brief Get a DMA channel node configuration. - * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the - * specified DMA linked-list Node. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, - DMA_NodeTypeDef const *const pNode) -{ - /* Check the node configuration and physical node parameters */ - if ((pNodeConfig == NULL) || (pNode == NULL)) - { - return HAL_ERROR; - } - - /* Get the DMA channel node configuration */ - DMA_List_GetNodeConfig(pNodeConfig, pNode); - - return HAL_OK; -} - -/** - * @brief Insert new node in any queue position of linked-list queue according to selecting previous node. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers - * configurations. - * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_InsertNode(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pPrevNode, - DMA_NodeTypeDef *const pNewNode) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the new node parameters */ - if ((pQList == NULL) || (pNewNode == NULL)) - { - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pPrevNode, pNewNode) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pPrevNode, pNewNode) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); - - /* Empty queue */ - if (pQList->Head == NULL) - { - /* Add only new node to queue */ - if (pPrevNode == NULL) - { - pQList->Head = pNewNode; - pQList->NodeNumber = 1U; - } - /* Add previous node then new node to queue */ - else - { - pQList->Head = pPrevNode; - pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - pQList->NodeNumber = 2U; - } - } - /* Not empty queue */ - else - { - /* Add new node at the head of queue */ - if (pPrevNode == NULL) - { - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; - pQList->Head = pNewNode; - } - /* Add new node according to selected position */ - else - { - /* Find node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - if (DMA_List_FindNode(pQList, pPrevNode, &node_info) == 0U) - { - /* Selected node is the last queue node */ - if (node_info.currentnode_pos == pQList->NodeNumber) - { - /* Check if queue is circular */ - if (pQList->FirstCircularNode != NULL) - { - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; - } - - pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - } - /* Selected node is not the last queue node */ - else - { - pNewNode->LinkRegisters[cllr_offset] = pPrevNode->LinkRegisters[cllr_offset]; - pPrevNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - } - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; - - return HAL_ERROR; - } - } - - /* Increment queue node number */ - pQList->NodeNumber++; - } - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Insert new node at the head of linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Head(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - - /* Check the queue and the new node parameters */ - if ((pQList == NULL) || (pNewNode == NULL)) - { - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Empty queue */ - if (pQList->Head == NULL) - { - pQList->Head = pNewNode; - } - /* Not empty queue */ - else - { - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); - - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; - pQList->Head = pNewNode; - } - - /* Increment queue node number */ - pQList->NodeNumber++; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Insert new node at the tail of linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_InsertNode_Tail(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the new node parameters */ - if ((pQList == NULL) || (pNewNode == NULL)) - { - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Empty queue */ - if (pQList->Head == NULL) - { - pQList->Head = pNewNode; - } - /* Not empty queue */ - else - { - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); - - /* Find node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Check if queue is circular */ - if (pQList->FirstCircularNode != NULL) - { - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; - } - - ((DMA_NodeTypeDef *)node_info.currentnode_addr)->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - } - - /* Increment queue node number */ - pQList->NodeNumber++; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Remove node from any linked-list queue position. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNode) -{ - uint32_t previousnode_addr; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the node parameters */ - if ((pQList == NULL) || (pNode == NULL)) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNode, NULL, &cllr_offset); - - /* Find node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - if (DMA_List_FindNode(pQList, pNode, &node_info) == 0U) - { - /* Removed node is the head node */ - if (node_info.currentnode_pos == 1U) - { - /* Check if first circular node queue is the first node */ - if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) - { - /* Find last queue node */ - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear last node link */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear first circular node */ - pQList->FirstCircularNode = NULL; - } - - /* Update the queue head node */ - pQList->Head = (DMA_NodeTypeDef *)(((uint32_t)pQList->Head & DMA_CLBAR_LBA) + - (pNode->LinkRegisters[cllr_offset] & DMA_CLLR_LA)); - /* Unlink node to be removed */ - pNode->LinkRegisters[cllr_offset] = 0U; - } - /* Removed node is the last node */ - else if (node_info.currentnode_pos == pQList->NodeNumber) - { - /* Clear CLLR for previous node */ - ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear CLLR for last node */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear first circular node */ - pQList->FirstCircularNode = NULL; - } - /* Removed node is in the middle */ - else - { - /* Store previous node address to be updated later */ - previousnode_addr = node_info.previousnode_addr; - - /* Check if first circular node queue is the current node */ - if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) - { - /* Find last queue node */ - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear last node link */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear first circular node */ - pQList->FirstCircularNode = NULL; - } - - /* Link previous node */ - ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[cllr_offset] = pNode->LinkRegisters[cllr_offset]; - - /* Unlink node to be removed */ - pNode->LinkRegisters[cllr_offset] = 0U; - } - - /* Decrement node number */ - pQList->NodeNumber--; - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; - - return HAL_ERROR; - } - - /* Check if queue is empty */ - if (pQList->NodeNumber == 0U) - { - /* Clean empty queue parameter */ - DMA_List_CleanQueue(pQList); - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Remove the head node from linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Head(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_offset; - uint32_t current_addr; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); - - /* Queue contains only one node */ - if (pQList->NodeNumber == 1U) - { - pQList->Head->LinkRegisters[cllr_offset] = 0U; - pQList->FirstCircularNode = 0U; - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - } - /* Queue contains more then one node */ - else - { - /* Check if first circular node queue is the first node */ - if (pQList->FirstCircularNode == pQList->Head) - { - /* Find last queue node */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear last node link */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear first circular node */ - pQList->FirstCircularNode = NULL; - } - - current_addr = pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA; - pQList->Head->LinkRegisters[cllr_offset] = 0U; - pQList->Head = ((DMA_NodeTypeDef *)(current_addr + ((uint32_t)pQList->Head & DMA_CLBAR_LBA))); - } - - /* Decrement node number */ - pQList->NodeNumber--; - - /* Check if queue is empty */ - if (pQList->NodeNumber == 0U) - { - /* Clean empty queue parameter */ - DMA_List_CleanQueue(pQList); - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Remove the tail node from linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_RemoveNode_Tail(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); - - /* Queue contains only one node */ - if (pQList->NodeNumber == 1U) - { - pQList->Head->LinkRegisters[cllr_offset] = 0U; - pQList->FirstCircularNode = 0U; - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - } - /* Queue contains more then one node */ - else - { - /* Find node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear CLLR for previous node */ - ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear CLLR for last node */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Clear first circular node */ - pQList->FirstCircularNode = NULL; - } - - /* Decrement node number */ - pQList->NodeNumber--; - - /* Check if queue is empty */ - if (pQList->NodeNumber == 0U) - { - /* Clean empty queue parameter */ - DMA_List_CleanQueue(pQList); - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - } - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Replace node in linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pOldNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list old node registers - * configurations. - * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pOldNode, - DMA_NodeTypeDef *const pNewNode) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the nodes parameters */ - if ((pQList == NULL) || (pOldNode == NULL) || (pNewNode == NULL)) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pOldNode, pNewNode) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pOldNode, pNewNode) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); - - /* Find node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - if (DMA_List_FindNode(pQList, pOldNode, &node_info) == 0U) - { - /* Replaced node is the head node */ - if (node_info.currentnode_pos == 1U) - { - pNewNode->LinkRegisters[cllr_offset] = - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; - pQList->Head = pNewNode; - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Check if first circular node queue is the first node */ - if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)node_info.currentnode_addr)) - { - /* Find last queue node */ - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear last node link */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - - /* Set new node as first circular node */ - pQList->FirstCircularNode = pNewNode; - } - } - /* Replaced node is the last */ - else if (node_info.currentnode_pos == pQList->NodeNumber) - { - ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Check if first circular node queue is the last node */ - if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) - { - /* Link first circular node to new node */ - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - - /* Set new node as first circular node */ - pQList->FirstCircularNode = pNewNode; - } - /* Check if first circular node queue is not the last node */ - else if (pQList->FirstCircularNode != NULL) - { - /* Link first circular node to new node */ - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; - } - else - { - /* Prevent MISRA-C2012-Rule-15.7 */ - } - } - /* Replaced node is in the middle */ - else - { - ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - pNewNode->LinkRegisters[cllr_offset] = - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset]; - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Check if first circular node queue is the current node */ - if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) - { - /* Find last node and get its position in selected queue */ - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Link last queue node to new node */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - - /* Set new node as first circular node */ - pQList->FirstCircularNode = pNewNode; - } - } - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; - - return HAL_ERROR; - } - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Replace the head node of linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Head(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode) -{ - uint32_t cllr_offset; - uint32_t cllr_mask; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the new node parameters */ - if ((pQList == NULL) || (pNewNode == NULL)) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pQList->Head, pNewNode, NULL) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pQList->Head, pNewNode, NULL) != 0U) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); - - /* Check if first circular node queue is the first node */ - if (pQList->FirstCircularNode == pQList->Head) - { - /* Find last queue node */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear last node link */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - - /* Set new node as first circular node */ - pQList->FirstCircularNode = pNewNode; - } - - /* Replace head node */ - pNewNode->LinkRegisters[cllr_offset] = pQList->Head->LinkRegisters[cllr_offset]; - pQList->Head->LinkRegisters[cllr_offset] = 0U; - pQList->Head = pNewNode; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Replace the tail node of linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pNewNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list new node registers - * configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ReplaceNode_Tail(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pNewNode) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the new node parameters */ - if ((pQList == NULL) || (pNewNode == NULL)) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pNewNode, &cllr_mask, &cllr_offset); - - /* Find last node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Link previous node to new node */ - ((DMA_NodeTypeDef *)(node_info.previousnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - - /* Clear CLLR for current node */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Check if first circular node queue is the last node */ - if (pQList->FirstCircularNode == ((DMA_NodeTypeDef *)(node_info.currentnode_addr))) - { - /* Link first circular node to new node */ - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pNewNode & DMA_CLLR_LA) | cllr_mask; - - /* Set new node as first circular node */ - pQList->FirstCircularNode = pNewNode; - } - /* Check if first circular node queue is not the last node */ - else if (pQList->FirstCircularNode != NULL) - { - /* Link first circular node to new node */ - pNewNode->LinkRegisters[cllr_offset] = ((uint32_t)pQList->FirstCircularNode & DMA_CLLR_LA) | cllr_mask; - } - else - { - /* Prevent MISRA-C2012-Rule-15.7 */ - } - - /* Check if queue contains one node */ - if (pQList->NodeNumber == 1U) - { - pQList->Head = pNewNode; - } - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Reset the linked-list queue and unlink queue nodes. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ResetQ(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check queue state */ - if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; - - return HAL_ERROR; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Check the queue */ - if (pQList->Head != NULL) - { - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); - - /* Reset selected queue nodes */ - node_info.cllr_offset = cllr_offset; - DMA_List_ResetQueueNodes(pQList, &node_info); - } - - /* Reset head node address */ - pQList->Head = NULL; - - /* Reset node number */ - pQList->NodeNumber = 0U; - - /* Reset first circular node */ - pQList->FirstCircularNode = NULL; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Insert a source linked-list queue to a destination linked-list queue according to selecting previous node. - * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. - * @param pPrevNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list previous node registers - * configurations. - * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_InsertQ(DMA_QListTypeDef *const pSrcQList, - DMA_NodeTypeDef const *const pPrevNode, - DMA_QListTypeDef *const pDestQList) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef src_q_node_info; - DMA_NodeInQInfoTypeDef dest_q_node_info; - - /* Check the source and destination queues and the previous node parameters */ - if ((pSrcQList == NULL) || (pDestQList == NULL)) - { - return HAL_ERROR; - } - - /* Check the source queue */ - if (pSrcQList->Head == NULL) - { - /* Update the queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check the source queue type */ - if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check the destination queue type */ - if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check the source queue circularity */ - if (pSrcQList->FirstCircularNode != NULL) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pPrevNode, pDestQList->Head) != 0U) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the source queue state */ - pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the destination queue state */ - pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); - - /* Empty destination queue */ - if (pDestQList->Head == NULL) - { - pDestQList->Head = pSrcQList->Head; - pDestQList->NodeNumber = pSrcQList->NodeNumber; - } - /* Not empty destination queue */ - else - { - /* Previous node is empty */ - if (pPrevNode == NULL) - { - /* Find node and get its position in selected queue */ - src_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); - - /* Check if first circular node queue is the first node */ - if (pDestQList->FirstCircularNode == pDestQList->Head) - { - /* Find node and get its position in selected queue */ - dest_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); - - /* Link destination queue tail node to new first circular node */ - ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = - ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; - - /* Set the head node of source queue as the first circular node */ - pDestQList->FirstCircularNode = pSrcQList->Head; - } - - /* Link the last node of source queue to the fist node of destination queue */ - ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; - pDestQList->Head = pSrcQList->Head; - pDestQList->NodeNumber += pSrcQList->NodeNumber; - } - /* Previous node is not empty */ - else - { - /* Find node and get its position in selected queue */ - dest_q_node_info.cllr_offset = cllr_offset; - if (DMA_List_FindNode(pDestQList, pPrevNode, &dest_q_node_info) == 0U) - { - /* Selected node is the last destination queue node */ - if (dest_q_node_info.currentnode_pos == pDestQList->NodeNumber) - { - /* Link the first node of source queue to the last node of destination queue */ - ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; - pDestQList->NodeNumber += pSrcQList->NodeNumber; - - /* Check if first circular node queue is not empty */ - if (pDestQList->FirstCircularNode != NULL) - { - /* Find node and get its position in selected queue */ - src_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); - - /* Find first circular node */ - (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); - - /* Link last source queue node to first destination queue */ - ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = - (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; - } - } - /* Selected node is not the last destination queue node */ - else - { - /* Link the first node of source queue to the previous node of destination queue */ - ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; - - /* Find node and get its position in selected queue */ - src_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); - - /* Link the last node of source queue to the next node of destination queue */ - ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - (dest_q_node_info.nextnode_addr & DMA_CLLR_LA) | cllr_mask; - - /* Update queues counter */ - pDestQList->NodeNumber += pSrcQList->NodeNumber; - } - } - else - { - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; - - return HAL_ERROR; - } - } - } - - /* Clean the source queue variable as it is obsolete */ - DMA_List_CleanQueue(pSrcQList); - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the destination queue state */ - pDestQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(src_q_node_info); - UNUSED(dest_q_node_info); - - return HAL_OK; -} - -/** - * @brief Insert a source linked-list queue at the head of destination queue. - * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. - * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Head(DMA_QListTypeDef *const pSrcQList, - DMA_QListTypeDef *const pDestQList) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef src_q_node_info; - DMA_NodeInQInfoTypeDef dest_q_node_info; - - /* Check the source and destination queues and the previous node parameters */ - if ((pSrcQList == NULL) || (pDestQList == NULL)) - { - return HAL_ERROR; - } - - /* Check the source queue */ - if (pSrcQList->Head == NULL) - { - /* Update the queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check the source queue type */ - if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check the destination queue type */ - if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the source queue state */ - pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the destination queue state */ - pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); - - /* Empty destination queue */ - if (pDestQList->Head == NULL) - { - pDestQList->Head = pSrcQList->Head; - pDestQList->NodeNumber = pSrcQList->NodeNumber; - } - /* Not empty destination queue */ - else - { - /* Find node and get its position in selected queue */ - src_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); - - /* Check if first circular node queue is the first node */ - if (pDestQList->FirstCircularNode == pDestQList->Head) - { - /* Find node and get its position in selected queue */ - dest_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); - - /* Link destination queue tail node to new first circular node */ - ((DMA_NodeTypeDef *)dest_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = - ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; - - /* Set the head node of source queue as the first circular node */ - pDestQList->FirstCircularNode = pSrcQList->Head; - } - - /* Link the last node of source queue to the fist node of destination queue */ - ((DMA_NodeTypeDef *)(src_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pDestQList->Head & DMA_CLLR_LA) | cllr_mask; - pDestQList->Head = pSrcQList->Head; - pDestQList->NodeNumber += pSrcQList->NodeNumber; - } - - /* Clean the source queue variable as it is obsolete */ - DMA_List_CleanQueue(pSrcQList); - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the destination queue state */ - pDestQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(src_q_node_info); - UNUSED(dest_q_node_info); - - return HAL_OK; -} - -/** - * @brief Insert a source linked-list queue at the tail of destination queue. - * @param pSrcQList : Pointer to a DMA_QListTypeDef structure that contains source queue information. - * @param pDestQList : Pointer to a DMA_QListTypeDef structure that contains destination queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_InsertQ_Tail(DMA_QListTypeDef *const pSrcQList, - DMA_QListTypeDef *const pDestQList) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef src_q_node_info; - DMA_NodeInQInfoTypeDef dest_q_node_info; - - /* Check the source and destination queues and the previous node parameters */ - if ((pSrcQList == NULL) || (pDestQList == NULL)) - { - return HAL_ERROR; - } - - /* Check the source queue */ - if (pSrcQList->Head == NULL) - { - /* Update the queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check the source queue type */ - if (pSrcQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check the destination queue type */ - if (pDestQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Check nodes base addresses */ - if (DMA_List_CheckNodesBaseAddresses(pSrcQList->Head, pDestQList->Head, NULL) != 0U) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_OUTOFRANGE; - - return HAL_ERROR; - } - - /* Check nodes types compatibility */ - if (DMA_List_CheckNodesTypes(pSrcQList->Head, pDestQList->Head, NULL) != 0U) - { - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the source queue state */ - pSrcQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the source queue error code */ - pSrcQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the destination queue state */ - pDestQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pSrcQList->Head, &cllr_mask, &cllr_offset); - - /* Empty destination queue */ - if (pDestQList->Head == NULL) - { - pDestQList->Head = pSrcQList->Head; - pDestQList->NodeNumber = pSrcQList->NodeNumber; - } - /* Not empty destination queue */ - else - { - /* Find node and get its position in selected queue */ - dest_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pDestQList, NULL, &dest_q_node_info); - - /* Update source queue last node CLLR to link it with destination first node */ - ((DMA_NodeTypeDef *)(dest_q_node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pSrcQList->Head & DMA_CLLR_LA) | cllr_mask; - pDestQList->NodeNumber += pSrcQList->NodeNumber; - - /* Check if first circular node queue is not empty */ - if (pDestQList->FirstCircularNode != NULL) - { - /* Find node and get its position in selected queue */ - src_q_node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pSrcQList, NULL, &src_q_node_info); - - /* Find first circular node */ - (void)DMA_List_FindNode(pDestQList, pDestQList->FirstCircularNode, &dest_q_node_info); - - /* Link last source queue node to first destination queue */ - ((DMA_NodeTypeDef *)src_q_node_info.currentnode_addr)->LinkRegisters[cllr_offset] = - (dest_q_node_info.currentnode_addr & DMA_CLLR_LA) | cllr_mask; - } - } - - /* Clean the source queue variable as it is obsolete */ - DMA_List_CleanQueue(pSrcQList); - - /* Update the destination queue error code */ - pDestQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the destination queue state */ - pDestQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(src_q_node_info); - - return HAL_OK; -} - -/** - * @brief Set circular mode configuration for linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pFirstCircularNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list first circular node - * registers configurations. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_SetCircularModeConfig(DMA_QListTypeDef *const pQList, - DMA_NodeTypeDef *const pFirstCircularNode) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue and the first circular node parameters */ - if ((pQList == NULL) || (pFirstCircularNode == NULL)) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue circular mode */ - if (pQList->FirstCircularNode != NULL) - { - if (pQList->FirstCircularNode == pFirstCircularNode) - { - return HAL_OK; - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pFirstCircularNode, &cllr_mask, &cllr_offset); - - /* Find the first circular node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - if (DMA_List_FindNode(pQList, pFirstCircularNode, &node_info) == 0U) - { - /* Find the last queue node and get its position in selected queue */ - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Set circular mode */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pFirstCircularNode & DMA_CLLR_LA) | cllr_mask; - - /* Update first circular node in queue */ - pQList->FirstCircularNode = pFirstCircularNode; - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NOTFOUND; - - return HAL_ERROR; - } - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Set circular mode for linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_SetCircularMode(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_mask; - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue circular mode */ - if (pQList->FirstCircularNode != NULL) - { - if (pQList->FirstCircularNode == pQList->Head) - { - return HAL_OK; - } - else - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_mask, &cllr_offset); - - /* Find the last queue node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Set circular mode */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = - ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; - - /* Update linked-list circular state */ - pQList->FirstCircularNode = pQList->Head; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Clear circular mode for linked-list queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ClearCircularMode(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_offset; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check queue circular mode */ - if (pQList->FirstCircularNode == NULL) - { - return HAL_OK; - } - - /* Check queue type */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); - - /* Find the last queue node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - - /* Clear circular mode */ - ((DMA_NodeTypeDef *)(node_info.currentnode_addr))->LinkRegisters[cllr_offset] = 0U; - - /* Update linked-list circular configuration */ - pQList->FirstCircularNode = NULL; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - /* Prevent MISRA-C2012-Rule-2.2_b */ - UNUSED(node_info); - - return HAL_OK; -} - -/** - * @brief Convert a linked-list queue to dynamic (Optimized DMA queue execution). - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToDynamic(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_offset; - uint32_t currentnode_addr; - DMA_NodeTypeDef context_node; - DMA_NodeInQInfoTypeDef node_info; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check if queue is dynamic */ - if (pQList->Type == QUEUE_TYPE_DYNAMIC) - { - return HAL_OK; - } - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); - - /* Check queue circularity */ - if (pQList->FirstCircularNode != 0U) - { - /* Find the last queue node and get its position in selected queue */ - node_info.cllr_offset = cllr_offset; - (void)DMA_List_FindNode(pQList, NULL, &node_info); - } - - /* Set current node address */ - currentnode_addr = (uint32_t)pQList->Head; - - /* Store register value */ - DMA_List_FillNode(pQList->Head, &context_node); - - /* Convert all nodes to dyncamic (Bypass head node) */ - for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) - { - /* Update node address */ - MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); - - /* Bypass the first circular node when first circular node isn't the last queue node */ - if (((uint32_t)pQList->FirstCircularNode != 0U) && - ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr) && - ((uint32_t)pQList->FirstCircularNode == currentnode_addr)) - { - /* Copy first circular node to context node */ - DMA_List_FillNode(pQList->FirstCircularNode, &context_node); - } - else - { - /* Convert current node to dynamic */ - DMA_List_ConvertNodeToDynamic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); - } - } - - /* Check if first circular node is the last node queue */ - if (((uint32_t)pQList->FirstCircularNode != 0U) && - ((uint32_t)pQList->FirstCircularNode != node_info.currentnode_addr)) - { - /* Update all queue nodes CLLR */ - DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_ISNOT_CIRCULAR); - } - else - { - /* Update all queue nodes CLLR */ - DMA_List_UpdateDynamicQueueNodesCLLR(pQList, LASTNODE_IS_CIRCULAR); - } - - /* Set queue type */ - pQList->Type = QUEUE_TYPE_DYNAMIC; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Convert a linked-list queue to static (Not optimized DMA queue execution). - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_ConvertQToStatic(DMA_QListTypeDef *const pQList) -{ - uint32_t cllr_offset; - uint32_t currentnode_addr; - DMA_NodeTypeDef context_node; - - /* Check the queue parameter */ - if (pQList == NULL) - { - return HAL_ERROR; - } - - /* Check the queue */ - if (pQList->Head == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_EMPTY; - - return HAL_ERROR; - } - - /* Check if queue is static */ - if (pQList->Type == QUEUE_TYPE_STATIC) - { - return HAL_OK; - } - - /* Set current node address */ - currentnode_addr = (uint32_t)pQList->Head; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_BUSY; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Get CLLR register mask and offset */ - DMA_List_GetCLLRNodeInfo(pQList->Head, NULL, &cllr_offset); - - /* Set all CLLR queue nodes to their default positions */ - DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_POSITION); - - /* Convert all nodes to static (Bypass head node) */ - for (uint32_t node_count = 1U; node_count < pQList->NodeNumber; node_count++) - { - /* Update context node register values */ - DMA_List_FillNode((DMA_NodeTypeDef *)currentnode_addr, &context_node); - - /* Update node address */ - MODIFY_REG(currentnode_addr, DMA_CLLR_LA, (context_node.LinkRegisters[cllr_offset] & DMA_CLLR_LA)); - - /* Convert current node to static */ - DMA_List_ConvertNodeToStatic((uint32_t)&context_node, currentnode_addr, (cllr_offset + 1U)); - } - - /* Set all CLLR queue nodes to their default values */ - DMA_List_UpdateStaticQueueNodesCLLR(pQList, UPDATE_CLLR_VALUE); - - /* Set queue type */ - pQList->Type = QUEUE_TYPE_STATIC; - - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Update the queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Link linked-list queue to a DMA channel. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_LinkQ(DMA_HandleTypeDef *const hdma, - DMA_QListTypeDef *const pQList) -{ - HAL_DMA_StateTypeDef state; - - /* Check the DMA channel handle and the queue parameters */ - if ((hdma == NULL) || (pQList == NULL)) - { - return HAL_ERROR; - } - - /* Get DMA state */ - state = hdma->State; - - /* Check DMA channel state */ - if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - /* Check queue state */ - if (pQList->State == HAL_DMA_QUEUE_STATE_BUSY) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_BUSY; - - return HAL_ERROR; - } - - /* Check linearity compatibility */ - if ((IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) == 0U) && - ((pQList->Head->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR)) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_UNSUPPORTED; - - return HAL_ERROR; - } - - /* Check circularity compatibility */ - if (hdma->Mode == DMA_LINKEDLIST_CIRCULAR) - { - /* Check first circular node */ - if (pQList->FirstCircularNode == NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - } - else - { - /* Check first circular node */ - if (pQList->FirstCircularNode != NULL) - { - /* Update the queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_INVALIDTYPE; - - return HAL_ERROR; - } - } - - /* Register queue to DMA handle */ - hdma->LinkedListQueue = pQList; - - return HAL_OK; -} - -/** - * @brief Unlink linked-list queue from a DMA channel. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_List_UnLinkQ(DMA_HandleTypeDef *const hdma) -{ - HAL_DMA_StateTypeDef state; - - /* Check the DMA channel parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Get DMA state */ - state = hdma->State; - - /* Check DMA channel state */ - if ((hdma->State == HAL_DMA_STATE_BUSY) || (state == HAL_DMA_STATE_SUSPEND)) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - /* Clear queue information from DMA channel handle */ - hdma->LinkedListQueue = NULL; - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup DMAEx_Exported_Functions_Group4 - * -@verbatim - ====================================================================================================================== - ##### Data handling, repeated block and trigger configuration functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Configure DMA channel data handling. - (+) Configure DMA channel repeated block. - (+) Configure DMA channel trigger. - - [..] - (+) The HAL_DMAEx_ConfigDataHandling() function allows to configure DMA channel data handling. - (++) GPDMA data handling : byte-based reordering, packing/unpacking, padding/truncation, sign extension - and left/right alignment. - (++) LPDMA data handling : byte-based padding/truncation, sign extension and left/right alignment. - - (+) The HAL_DMAEx_ConfigTrigger() function allows to configure DMA channel HW triggers. - - (+) The HAL_DMAEx_ConfigRepeatBlock() function allows to configure DMA channel repeated block. - (++) This feature is available only for channel that supports 2 dimensions addressing capability. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the DMA channel data handling according to the specified parameters in the - * DMA_DataHandlingConfTypeDef. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information - * for the specified DMA Channel. - * @param pConfigDataHandling : Pointer to a DMA_DataHandlingConfTypeDef structure that contains the data handling - * configuration. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigDataHandling(DMA_HandleTypeDef *const hdma, - DMA_DataHandlingConfTypeDef const *const pConfigDataHandling) -{ - /* Check the DMA peripheral handle and data handling parameters */ - if ((hdma == NULL) || (pConfigDataHandling == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_DATA_ALIGNMENT(pConfigDataHandling->DataAlignment)); - assert_param(IS_DMA_DATA_EXCHANGE(pConfigDataHandling->DataExchange)); - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - MODIFY_REG(hdma->Instance->CTR1, (DMA_CTR1_DHX | DMA_CTR1_DBX | DMA_CTR1_SBX | DMA_CTR1_PAM), - (pConfigDataHandling->DataAlignment | pConfigDataHandling->DataExchange)); - } - else - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Configure the DMA channel trigger according to the specified parameters in the DMA_TriggerConfTypeDef. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for - * the specified DMA Channel. - * @param pConfigTrigger : Pointer to a DMA_TriggerConfTypeDef structure that contains the trigger configuration. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigTrigger(DMA_HandleTypeDef *const hdma, - DMA_TriggerConfTypeDef const *const pConfigTrigger) -{ - /* Check the DMA peripheral handle and trigger parameters */ - if ((hdma == NULL) || (pConfigTrigger == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_TRIGGER_POLARITY(pConfigTrigger->TriggerPolarity)); - assert_param(IS_DMA_TRIGGER_MODE(pConfigTrigger->TriggerMode)); - assert_param(IS_DMA_TRIGGER_SELECTION(pConfigTrigger->TriggerSelection)); - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - MODIFY_REG(hdma->Instance->CTR2, (DMA_CTR2_TRIGPOL | DMA_CTR2_TRIGSEL | DMA_CTR2_TRIGM), - (pConfigTrigger->TriggerPolarity | pConfigTrigger->TriggerMode | - (pConfigTrigger->TriggerSelection << DMA_CTR2_TRIGSEL_Pos))); - } - else - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Configure the DMA channel repeated block according to the specified parameters in the - * DMA_RepeatBlockConfTypeDef. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information - * for the specified DMA Channel. - * @param pConfigRepeatBlock : Pointer to a DMA_RepeatBlockConfTypeDef structure that contains the repeated block - * configuration. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_ConfigRepeatBlock(DMA_HandleTypeDef *const hdma, - DMA_RepeatBlockConfTypeDef const *const pConfigRepeatBlock) -{ - uint32_t tmpreg1; - uint32_t tmpreg2; - - /* Check the DMA peripheral handle and repeated block parameters */ - if ((hdma == NULL) || (pConfigRepeatBlock == NULL)) - { - return HAL_ERROR; - } - - /* Check parameters */ - assert_param(IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance)); - assert_param(IS_DMA_REPEAT_COUNT(pConfigRepeatBlock->RepeatCount)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->SrcAddrOffset)); - assert_param(IS_DMA_BURST_ADDR_OFFSET(pConfigRepeatBlock->DestAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkSrcAddrOffset)); - assert_param(IS_DMA_BLOCK_ADDR_OFFSET(pConfigRepeatBlock->BlkDestAddrOffset)); - - /* Check DMA channel state */ - if (hdma->State == HAL_DMA_STATE_READY) - { - /* Store repeat block count */ - tmpreg1 = ((pConfigRepeatBlock->RepeatCount - 1U) << DMA_CBR1_BRC_Pos); - - /* Check the sign of single/burst destination address offset value */ - if (pConfigRepeatBlock->DestAddrOffset < 0) - { - /* Store single/burst destination address offset configuration (signed case) */ - tmpreg1 |= DMA_CBR1_DDEC; - tmpreg2 = (uint32_t)(- pConfigRepeatBlock->DestAddrOffset); - tmpreg2 = tmpreg2 << DMA_CTR3_DAO_Pos; - } - else - { - /* Store single/burst destination address offset configuration (unsigned case) */ - tmpreg2 = ((uint32_t)pConfigRepeatBlock->DestAddrOffset << DMA_CTR3_DAO_Pos); - } - - /* Check the sign of single/burst source address offset value */ - if (pConfigRepeatBlock->SrcAddrOffset < 0) - { - /* Store single/burst source address offset configuration (signed case) */ - tmpreg1 |= DMA_CBR1_SDEC; - tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->SrcAddrOffset); - } - else - { - /* Store single/burst source address offset configuration (unsigned case) */ - tmpreg2 |= (uint32_t)pConfigRepeatBlock->SrcAddrOffset; - } - - /* Write DMA Channel Transfer Register 3 (CTR3) */ - WRITE_REG(hdma->Instance->CTR3, tmpreg2); - - /* Check the sign of block destination address offset value */ - if (pConfigRepeatBlock->BlkDestAddrOffset < 0) - { - /* Store block destination address offset configuration (signed case) */ - tmpreg1 |= DMA_CBR1_BRDDEC; - tmpreg2 = (uint32_t)(- pConfigRepeatBlock->BlkDestAddrOffset); - tmpreg2 = tmpreg2 << DMA_CBR2_BRDAO_Pos; - } - else - { - /* Store block destination address offset configuration (unsigned case) */ - tmpreg2 = ((uint32_t)pConfigRepeatBlock->BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos); - } - - /* Check the sign of block source address offset value */ - if (pConfigRepeatBlock->BlkSrcAddrOffset < 0) - { - /* Store block source address offset configuration (signed case) */ - tmpreg1 |= DMA_CBR1_BRSDEC; - tmpreg2 |= (uint32_t)(- pConfigRepeatBlock->BlkSrcAddrOffset); - } - else - { - /* Store block source address offset configuration (unsigned case) */ - tmpreg2 |= (uint32_t)pConfigRepeatBlock->BlkSrcAddrOffset; - } - - /* Write DMA Channel block register 2 (CBR2) */ - WRITE_REG(hdma->Instance->CBR2, tmpreg2); - - /* Write DMA Channel block register 1 (CBR1) */ - WRITE_REG(hdma->Instance->CBR1, tmpreg1); - } - else - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_BUSY; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup DMAEx_Exported_Functions_Group5 - * -@verbatim - ====================================================================================================================== - ##### Suspend and resume operation functions ##### - ====================================================================================================================== - [..] - This section provides functions allowing to : - (+) Suspend any ongoing DMA channel transfer. - (+) Resume any suspended DMA channel transfer. - - [..] - (+) The HAL_DMAEx_Suspend() function allows to suspend any ongoing DMA channel transfer in polling mode (Blocking - mode). - - (+) The HAL_DMAEx_Suspend_IT() function allows to suspend any ongoing DMA channel transfer in interrupt mode - (Non-blocking mode). - - (+) The HAL_DMAEx_Resume() function allows to resume any suspended DMA channel transfer. - -@endverbatim - * @{ - */ - -/** - * @brief Suspend any ongoing DMA channel transfer in polling mode (Blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA channel. - * @note After suspending a DMA channel, a check for wait until the DMA channel is effectively suspended is added. If - * a channel is suspended while a data transfer is ongoing, the current data will be transferred and the - * channel will be effectively suspended only after the transfer of this single/burst data is finished. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_Suspend(DMA_HandleTypeDef *const hdma) -{ - /* Get tick number */ - uint32_t tickstart = HAL_GetTick(); - - /* Check the DMA peripheral handle */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State != HAL_DMA_STATE_BUSY) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Suspend the channel */ - hdma->Instance->CCR |= DMA_CCR_SUSP; - - /* Check if the DMA channel is suspended */ - while ((hdma->Instance->CSR & DMA_CSR_SUSPF) == 0U) - { - /* Check for the timeout */ - if ((HAL_GetTick() - tickstart) > HAL_TIMEOUT_DMA_ABORT) - { - /* Update the DMA channel error code */ - hdma->ErrorCode |= HAL_DMA_ERROR_TIMEOUT; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_ERROR; - - /* Process Unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - } - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_SUSPEND; - } - - return HAL_OK; -} - -/** - * @brief Suspend any ongoing DMA channel transfer in polling mode (Non-blocking mode). - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_Suspend_IT(DMA_HandleTypeDef *const hdma) -{ - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State != HAL_DMA_STATE_BUSY) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Suspend the DMA channel and activate suspend interrupt */ - hdma->Instance->CCR |= (DMA_CCR_SUSP | DMA_CCR_SUSPIE); - } - - return HAL_OK; -} - -/** - * @brief Resume any suspended DMA channel transfer. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_DMAEx_Resume(DMA_HandleTypeDef *const hdma) -{ - /* Check the DMA peripheral handle parameter */ - if (hdma == NULL) - { - return HAL_ERROR; - } - - /* Check DMA channel state */ - if (hdma->State != HAL_DMA_STATE_SUSPEND) - { - /* Update the DMA channel error code */ - hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; - - /* Process unlocked */ - __HAL_UNLOCK(hdma); - - return HAL_ERROR; - } - else - { - /* Resume the DMA channel */ - hdma->Instance->CCR &= (~DMA_CCR_SUSP); - - /* Clear the suspend flag */ - hdma->Instance->CFCR |= DMA_CFCR_SUSPF; - - /* Update the DMA channel state */ - hdma->State = HAL_DMA_STATE_BUSY; - } - - return HAL_OK; -} -/** - * @} - */ - -/** @addtogroup DMAEx_Exported_Functions_Group6 - * -@verbatim - ====================================================================================================================== - ##### Fifo status function ##### - ====================================================================================================================== - [..] - This section provides function allowing to get DMA channel FIFO level. - - [..] - (+) The HAL_DMAEx_GetFifoLevel() function allows to return the number of available write beats in the FIFO, in - units of the programmed destination data. - (++) This API is available only for DMA channels that supports FIFO. - -@endverbatim - * @{ - */ - -/** - * @brief Get and returns the DMA channel FIFO level. - * @param hdma : Pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval Returns the number of available beats in FIFO. - */ -uint32_t HAL_DMAEx_GetFifoLevel(DMA_HandleTypeDef const *const hdma) -{ - return ((hdma->Instance->CSR & DMA_CSR_FIFOL) >> DMA_CSR_FIFOL_Pos); -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions -------------------------------------------------------------------------------------------------*/ -/** @defgroup DMAEx_Private_Functions DMAEx Private Functions - * @brief DMAEx Private Functions - * @{ - */ - -/** - * @brief Initialize the DMA handle according to the specified parameters in the DMA_InitTypeDef. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains the configuration information for the - * specified DMA Channel. - * @retval None. - */ -static void DMA_List_Init(DMA_HandleTypeDef const *const hdma) -{ - uint32_t tmpreg; - - /* Prepare DMA Channel Control Register (CCR) value */ - tmpreg = hdma->InitLinkedList.Priority | hdma->InitLinkedList.LinkStepMode; - - /* Check DMA channel instance */ - if (IS_GPDMA_INSTANCE(hdma->Instance) != 0U) - { - tmpreg |= hdma->InitLinkedList.LinkAllocatedPort; - } - - /* Write DMA Channel Control Register (CCR) */ - MODIFY_REG(hdma->Instance->CCR, DMA_CCR_PRIO | DMA_CCR_LAP | DMA_CCR_LSM, tmpreg); - - /* Write DMA Channel Control Register (CTR1) */ - WRITE_REG(hdma->Instance->CTR1, 0U); - - /* Write DMA Channel Control Register (CTR2) */ - WRITE_REG(hdma->Instance->CTR2, hdma->InitLinkedList.TransferEventMode); - - /* Write DMA Channel Control Register (CBR1) */ - WRITE_REG(hdma->Instance->CBR1, 0U); - - /* Write DMA Channel Control Register (CSAR) */ - WRITE_REG(hdma->Instance->CSAR, 0U); - - /* Write DMA Channel Control Register (CDAR) */ - WRITE_REG(hdma->Instance->CDAR, 0U); - - /* If 2D Addressing is supported by current channel */ - if (IS_DMA_2D_ADDRESSING_INSTANCE(hdma->Instance) != 0U) - { - /* Write DMA Channel Control Register (CTR3) */ - WRITE_REG(hdma->Instance->CTR3, 0U); - - /* Write DMA Channel Control Register (CBR2) */ - WRITE_REG(hdma->Instance->CBR2, 0U); - } - - /* Write DMA Channel linked-list address register (CLLR) */ - WRITE_REG(hdma->Instance->CLLR, 0U); -} - -/** - * @brief Build a DMA channel node according to the specified parameters in the DMA_NodeConfTypeDef. - * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the - * specified DMA linked-list Node. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @retval None. - */ -static void DMA_List_BuildNode(DMA_NodeConfTypeDef const *const pNodeConfig, - DMA_NodeTypeDef *const pNode) -{ - int32_t blockoffset; - - /* Update CTR1 register value ***************************************************************************************/ - /* Prepare DMA channel transfer register (CTR1) value */ - pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] = pNodeConfig->Init.DestInc | - pNodeConfig->Init.DestDataWidth | - pNodeConfig->DataHandlingConfig.DataAlignment | - pNodeConfig->Init.SrcInc | - pNodeConfig->Init.SrcDataWidth; - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* set source channel security attribute */ - if (pNodeConfig->SrcSecure == DMA_CHANNEL_SRC_SEC) - { - pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_SSEC; - } - - /* set destination channel security attribute */ - if (pNodeConfig->DestSecure == DMA_CHANNEL_DEST_SEC) - { - pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= DMA_CTR1_DSEC; - } -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Add parameters related to DMA configuration */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) - { - /* Prepare DMA channel transfer register (CTR1) value */ - pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] |= - (pNodeConfig->Init.TransferAllocatedPort | pNodeConfig->DataHandlingConfig.DataExchange | - (((pNodeConfig->Init.DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) & DMA_CTR1_DBL_1) | - (((pNodeConfig->Init.SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos) & DMA_CTR1_SBL_1)); - } - /*********************************************************************************** CTR1 register value is updated */ - - - /* Update CTR2 register value ***************************************************************************************/ - /* Prepare DMA channel transfer register 2 (CTR2) value */ - pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] = pNodeConfig->Init.TransferEventMode | - (pNodeConfig->Init.Request & (DMA_CTR2_REQSEL | DMA_CTR2_SWREQ)); - - /* Check for memory to peripheral transfer */ - if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_PERIPH) - { - /* Check for GPDMA */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_GPDMA) == DMA_CHANNEL_TYPE_GPDMA) - { - pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_DREQ; - } - } - /* Memory to memory transfer */ - else if ((pNodeConfig->Init.Direction) == DMA_MEMORY_TO_MEMORY) - { - pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= DMA_CTR2_SWREQ; - } - else - { - /* Prevent MISRA-C2012-Rule-15.7 */ - } - - /* Check if trigger feature is active */ - if (pNodeConfig->TriggerConfig.TriggerPolarity != DMA_TRIG_POLARITY_MASKED) - { - /* Prepare DMA channel transfer register 2 (CTR2) value */ - pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] |= - pNodeConfig->TriggerConfig.TriggerMode | pNodeConfig->TriggerConfig.TriggerPolarity | - ((pNodeConfig->TriggerConfig.TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & DMA_CTR2_TRIGSEL); - } - /*********************************************************************************** CTR2 register value is updated */ - - - /* Update CBR1 register value ***************************************************************************************/ - /* Prepare DMA channel block register 1 (CBR1) value */ - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = (pNodeConfig->DataSize & DMA_CBR1_BNDT); - - /* If 2D addressing is supported by the selected DMA channel */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - /* Set the new CBR1 Register value */ - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= - (((pNodeConfig->RepeatBlockConfig.RepeatCount - 1U) << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC); - - /* If the source address offset is negative, set SDEC bit */ - if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_SDEC; - } - else - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_SDEC); - } - - /* If the destination address offset is negative, set DDEC bit */ - if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_DDEC; - } - else - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_DDEC); - } - - /* If the repeated block source address offset is negative, set BRSEC bit */ - if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRSDEC; - } - else - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRSDEC); - } - - /* if the repeated block destination address offset is negative, set BRDEC bit */ - if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] |= DMA_CBR1_BRDDEC; - } - else - { - pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] &= (~DMA_CBR1_BRDDEC); - } - } - /*********************************************************************************** CBR1 register value is updated */ - - - /* Update CSAR register value ***************************************************************************************/ - pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = pNodeConfig->SrcAddress; - /*********************************************************************************** CSAR register value is updated */ - - - /* Update CDAR register value ***************************************************************************************/ - pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pNodeConfig->DstAddress; - /*********************************************************************************** CDAR register value is updated */ - - /* Check if the selected channel is 2D addressing */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - /* Update CTR3 register value *************************************************************************************/ - /* Write new CTR3 Register value : source address offset */ - if (pNodeConfig->RepeatBlockConfig.SrcAddrOffset < 0) - { - blockoffset = (- pNodeConfig->RepeatBlockConfig.SrcAddrOffset); - pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CTR3_SAO); - } - else - { - pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] = - ((uint32_t)pNodeConfig->RepeatBlockConfig.SrcAddrOffset & DMA_CTR3_SAO); - } - - /* Write new CTR3 Register value : destination address offset */ - if (pNodeConfig->RepeatBlockConfig.DestAddrOffset < 0) - { - blockoffset = (- pNodeConfig->RepeatBlockConfig.DestAddrOffset); - pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= (((uint32_t)blockoffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); - } - else - { - pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] |= - (((uint32_t)pNodeConfig->RepeatBlockConfig.DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO); - } - /********************************************************************************* CTR3 register value is updated */ - - - /* Update CBR2 register value *************************************************************************************/ - /* Write new CBR2 Register value : repeated block source address offset */ - if (pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset < 0) - { - blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset); - pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = ((uint32_t)blockoffset & DMA_CBR2_BRSAO); - } - else - { - pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] = - ((uint32_t)pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset & DMA_CBR2_BRSAO); - } - - /* Write new CBR2 Register value : repeated block destination address offset */ - if (pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset < 0) - { - blockoffset = (- pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset); - pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= - (((uint32_t)blockoffset & DMA_CBR2_BRSAO) << DMA_CBR2_BRDAO_Pos); - } - else - { - pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] |= - (((uint32_t)pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset << DMA_CBR2_BRDAO_Pos) & DMA_CBR2_BRDAO); - } - /********************************************************************************* CBR2 register value is updated */ - } - - - /* Update node information value ************************************************************************************/ - /* Set node information */ - pNode->NodeInfo = pNodeConfig->NodeType; - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - pNode->NodeInfo |= (NODE_CLLR_2D_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); - } - else - { - pNode->NodeInfo |= (NODE_CLLR_LINEAR_DEFAULT_OFFSET << NODE_CLLR_IDX_POS); - } - /******************************************************************************** Node information value is updated */ -} - -/** - * @brief Get a DMA channel node configuration. - * @param pNodeConfig : Pointer to a DMA_NodeConfTypeDef structure that contains the configuration information for the - * specified DMA linked-list Node. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @retval None. - */ -static void DMA_List_GetNodeConfig(DMA_NodeConfTypeDef *const pNodeConfig, - DMA_NodeTypeDef const *const pNode) -{ - uint16_t offset; - - /* Get node information *********************************************************************************************/ - pNodeConfig->NodeType = (pNode->NodeInfo & NODE_TYPE_MASK); - /*************************************************************************************** Node type value is updated */ - - - /* Get CTR1 fields values *******************************************************************************************/ - pNodeConfig->Init.SrcInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SINC; - pNodeConfig->Init.DestInc = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DINC; - pNodeConfig->Init.SrcDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SDW_LOG2; - pNodeConfig->Init.DestDataWidth = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; - pNodeConfig->Init.SrcBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & - DMA_CTR1_SBL_1) >> DMA_CTR1_SBL_1_Pos) + 1U; - pNodeConfig->Init.DestBurstLength = ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & - DMA_CTR1_DBL_1) >> DMA_CTR1_DBL_1_Pos) + 1U; - pNodeConfig->Init.TransferAllocatedPort = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & - (DMA_CTR1_SAP | DMA_CTR1_DAP); - pNodeConfig->DataHandlingConfig.DataExchange = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & - (DMA_CTR1_SBX | DMA_CTR1_DBX | DMA_CTR1_DHX); - pNodeConfig->DataHandlingConfig.DataAlignment = pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_PAM; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_SSEC) != 0U) - { - pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_SEC; - } - else - { - pNodeConfig->SrcSecure = DMA_CHANNEL_SRC_NSEC; - } - - if ((pNode->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DSEC) != 0U) - { - pNodeConfig->DestSecure = DMA_CHANNEL_DEST_SEC; - } - else - { - pNodeConfig->DestSecure = DMA_CHANNEL_DEST_NSEC; - } -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - /*********************************************************************************** CTR1 fields values are updated */ - - - /* Get CTR2 fields values *******************************************************************************************/ - if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_SWREQ) != 0U) - { - pNodeConfig->Init.Request = DMA_REQUEST_SW; - pNodeConfig->Init.Direction = DMA_MEMORY_TO_MEMORY; - } - else - { - pNodeConfig->Init.Request = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_REQSEL; - - if ((pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_DREQ) != 0U) - { - pNodeConfig->Init.Direction = DMA_MEMORY_TO_PERIPH; - } - else - { - pNodeConfig->Init.Direction = DMA_PERIPH_TO_MEMORY; - } - } - - pNodeConfig->Init.BlkHWRequest = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_BREQ); - pNodeConfig->TriggerConfig.TriggerMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGM; - pNodeConfig->TriggerConfig.TriggerPolarity = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TRIGPOL; - pNodeConfig->TriggerConfig.TriggerSelection = (pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & - DMA_CTR2_TRIGSEL) >> DMA_CTR2_TRIGSEL_Pos; - pNodeConfig->Init.TransferEventMode = pNode->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET] & DMA_CTR2_TCEM; - /*********************************************************************************** CTR2 fields values are updated */ - - - /* Get CBR1 fields **************************************************************************************************/ - pNodeConfig->DataSize = pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BNDT; - - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - pNodeConfig->RepeatBlockConfig.RepeatCount = - ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRC) >> DMA_CBR1_BRC_Pos) + 1U; - } - else - { - pNodeConfig->RepeatBlockConfig.RepeatCount = 1U; - } - /*********************************************************************************** CBR1 fields values are updated */ - - - /* Get CSAR field ***************************************************************************************************/ - pNodeConfig->SrcAddress = pNode->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET]; - /************************************************************************************** CSAR field value is updated */ - - - /* Get CDAR field ***************************************************************************************************/ - pNodeConfig->DstAddress = pNode->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET]; - /************************************************************************************** CDAR field value is updated */ - - /* Check if the selected channel is 2D addressing */ - if ((pNodeConfig->NodeType & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - /* Get CTR3 field *************************************************************************************************/ - offset = (uint16_t)(pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_SAO); - pNodeConfig->RepeatBlockConfig.SrcAddrOffset = (int32_t)offset; - - offset = (uint16_t)((pNode->LinkRegisters[NODE_CTR3_DEFAULT_OFFSET] & DMA_CTR3_DAO) >> DMA_CTR3_DAO_Pos); - pNodeConfig->RepeatBlockConfig.DestAddrOffset = (int32_t)offset; - - if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_SDEC) != 0U) - { - pNodeConfig->RepeatBlockConfig.SrcAddrOffset *= (-1); - } - - if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_DDEC) != 0U) - { - pNodeConfig->RepeatBlockConfig.DestAddrOffset *= (-1); - } - /************************************************************************************ CTR3 field value is updated */ - - - /* Get CBR2 fields ************************************************************************************************/ - offset = (uint16_t)(pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRSAO); - pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = (int32_t)offset; - - offset = (uint16_t)((pNode->LinkRegisters[NODE_CBR2_DEFAULT_OFFSET] & DMA_CBR2_BRDAO) >> DMA_CBR2_BRDAO_Pos); - pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = (int32_t)offset; - - if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRSDEC) != 0U) - { - pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset *= (-1); - } - - if ((pNode->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] & DMA_CBR1_BRDDEC) != 0U) - { - pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset *= (-1); - } - /************************************************************************************ CBR2 field value is updated */ - } - else - { - /* Get CTR3 field *************************************************************************************************/ - pNodeConfig->RepeatBlockConfig.SrcAddrOffset = 0; - pNodeConfig->RepeatBlockConfig.DestAddrOffset = 0; - /************************************************************************************ CTR3 field value is updated */ - - - /* Get CBR2 fields ************************************************************************************************/ - pNodeConfig->RepeatBlockConfig.BlkSrcAddrOffset = 0; - pNodeConfig->RepeatBlockConfig.BlkDestAddrOffset = 0; - /************************************************************************************ CBR2 field value is updated */ - } -} - -/** - * @brief Check nodes base addresses compatibility. - * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. - * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. - * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @retval Return 0 when nodes addresses are compatible, 1 otherwise. - */ -static uint32_t DMA_List_CheckNodesBaseAddresses(DMA_NodeTypeDef const *const pNode1, - DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3) -{ - uint32_t temp = (((uint32_t)pNode1 | (uint32_t)pNode2 | (uint32_t)pNode3) & DMA_CLBAR_LBA); - uint32_t ref = 0U; - - /* Check node 1 address */ - if ((uint32_t)pNode1 != 0U) - { - ref = (uint32_t)pNode1; - } - /* Check node 2 address */ - else if ((uint32_t)pNode2 != 0U) - { - ref = (uint32_t)pNode2; - } - /* Check node 3 address */ - else if ((uint32_t)pNode3 != 0U) - { - ref = (uint32_t)pNode3; - } - else - { - /* Prevent MISRA-C2012-Rule-15.7 */ - } - - /* Check addresses compatibility */ - if (temp != ((uint32_t)ref & DMA_CLBAR_LBA)) - { - return 1U; - } - - return 0U; -} - -/** - * @brief Check nodes types compatibility. - * @param pNode1 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 1 registers configurations. - * @param pNode2 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 2 registers configurations. - * @param pNode3 : Pointer to a DMA_NodeTypeDef structure that contains linked-list node 3 registers configurations. - * @retval Return 0 when nodes types are compatible, otherwise nodes types are not compatible. - */ -static uint32_t DMA_List_CheckNodesTypes(DMA_NodeTypeDef const *const pNode1, - DMA_NodeTypeDef const *const pNode2, - DMA_NodeTypeDef const *const pNode3) -{ - uint32_t ref = 0U; - - /* Check node 1 parameter */ - if (pNode1 != NULL) - { - ref = pNode1->NodeInfo & NODE_TYPE_MASK; - } - /* Check node 2 parameter */ - else if (pNode2 != NULL) - { - ref = pNode2->NodeInfo & NODE_TYPE_MASK; - } - /* Check node 3 parameter */ - else if (pNode3 != NULL) - { - ref = pNode3->NodeInfo & NODE_TYPE_MASK; - } - else - { - /* Prevent MISRA-C2012-Rule-15.7 */ - } - - /* Check node 2 parameter */ - if (pNode2 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode2->NodeInfo & NODE_TYPE_MASK)) - { - return 2U; - } - } - - /* Check node 3 parameter */ - if (pNode3 != NULL) - { - /* Check node type compatibility */ - if (ref != (pNode3->NodeInfo & NODE_TYPE_MASK)) - { - return 3U; - } - } - - return 0U; -} - -/** - * @brief Check nodes types compatibility. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @param cllr_mask : Pointer to CLLR register mask value. - * @param cllr_offset : Pointer to CLLR register offset value. - * @retval None. - */ -static void DMA_List_GetCLLRNodeInfo(DMA_NodeTypeDef const *const pNode, - uint32_t *const cllr_mask, - uint32_t *const cllr_offset) -{ - /* Check node type */ - if ((pNode->NodeInfo & DMA_CHANNEL_TYPE_2D_ADDR) == DMA_CHANNEL_TYPE_2D_ADDR) - { - /* Update CLLR register mask value */ - if (cllr_mask != NULL) - { - *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_UT3 | - DMA_CLLR_UB2 | DMA_CLLR_ULL; - } - - /* Update CLLR register offset */ - if (cllr_offset != NULL) - { - *cllr_offset = NODE_CLLR_2D_DEFAULT_OFFSET; - } - } - /* Update CLLR and register number for linear addressing node */ - else - { - /* Update CLLR register mask value */ - if (cllr_mask != NULL) - { - *cllr_mask = DMA_CLLR_UT1 | DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | DMA_CLLR_ULL; - } - - /* Update CLLR register offset */ - if (cllr_offset != NULL) - { - *cllr_offset = NODE_CLLR_LINEAR_DEFAULT_OFFSET; - } - } -} - -/** - * @brief Find node in queue. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers configurations. - * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. - * @retval Return 0 when node is found in selected queue, otherwise node is not found. - */ -static uint32_t DMA_List_FindNode(DMA_QListTypeDef const *const pQList, - DMA_NodeTypeDef const *const pNode, - DMA_NodeInQInfoTypeDef *const NodeInfo) -{ - uint32_t node_idx = 0U; - uint32_t currentnode_address = 0U; - uint32_t previousnode_address = 0U; - uint32_t cllr_offset = NodeInfo->cllr_offset; - - /* Find last node in queue */ - if (pNode == NULL) - { - /* Check that previous node is linked to the selected queue */ - while (node_idx < pQList->NodeNumber) - { - /* Get head node address */ - if (node_idx == 0U) - { - currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; - } - /* Calculate nodes addresses */ - else - { - previousnode_address = currentnode_address; - currentnode_address = - ((DMA_NodeTypeDef *)(currentnode_address + - ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; - } - - /* Increment node index */ - node_idx++; - } - } - /* Find selected node node in queue */ - else - { - /* Check that previous node is linked to the selected queue */ - while ((node_idx < pQList->NodeNumber) && (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA))) - { - /* Get head node address */ - if (node_idx == 0U) - { - currentnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; - } - /* Calculate nodes addresses */ - else - { - previousnode_address = currentnode_address; - currentnode_address = - ((DMA_NodeTypeDef *)(currentnode_address + - ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; - } - - /* Increment node index */ - node_idx++; - } - } - - /* Check stored address */ - if (pNode != NULL) - { - if (currentnode_address != ((uint32_t)pNode & DMA_CLLR_LA)) - { - return 1U; - } - } - - /* Update current node position */ - NodeInfo->currentnode_pos = node_idx; - - /* Update previous node address */ - NodeInfo->previousnode_addr = previousnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); - - /* Update current node address */ - NodeInfo->currentnode_addr = currentnode_address | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); - - /* Update next node address */ - if (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] != 0U) - { - NodeInfo->nextnode_addr = (((DMA_NodeTypeDef *)NodeInfo->currentnode_addr)->LinkRegisters[cllr_offset] & - DMA_CLLR_LA) | ((uint32_t)pQList->Head & DMA_CLBAR_LBA); - } - - return 0U; -} - -/** - * @brief Reset queue nodes. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param NodeInfo : Pointer to a DMA_NodeInQInfoTypeDef structure that contains node linked to queue information. - * @retval None. - */ -static void DMA_List_ResetQueueNodes(DMA_QListTypeDef const *const pQList, - DMA_NodeInQInfoTypeDef const *const NodeInfo) -{ - uint32_t node_idx = 0U; - uint32_t currentnode_address = 0U; - uint32_t previousnode_address; - uint32_t cllr_offset = NodeInfo->cllr_offset; - - /* Check that previous node is linked to the selected queue */ - while (node_idx < pQList->NodeNumber) - { - /* Get head node address */ - if (node_idx == 0U) - { - previousnode_address = (uint32_t)pQList->Head & DMA_CLLR_LA; - currentnode_address = (pQList->Head->LinkRegisters[cllr_offset] & DMA_CLLR_LA); - } - /* Calculate nodes addresses */ - else - { - previousnode_address = currentnode_address; - currentnode_address = - ((DMA_NodeTypeDef *)(currentnode_address + - ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] & DMA_CLLR_LA; - } - - /* Reset node */ - ((DMA_NodeTypeDef *)(previousnode_address + - ((uint32_t)pQList->Head & DMA_CLBAR_LBA)))->LinkRegisters[cllr_offset] = 0U; - - /* Increment node index */ - node_idx++; - } -} - -/** - * @brief Fill source node registers values by destination nodes registers values. - * @param pSrcNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list source node registers - * configurations. - * @param pDestNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list destination node registers - * configurations. - * @retval None. - */ -static void DMA_List_FillNode(DMA_NodeTypeDef const *const pSrcNode, - DMA_NodeTypeDef *const pDestNode) -{ - /* Repeat for all register nodes */ - for (uint32_t reg_idx = 0U; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) - { - pDestNode->LinkRegisters[reg_idx] = pSrcNode->LinkRegisters[reg_idx]; - } - - /* Fill node information */ - pDestNode->NodeInfo = pSrcNode->NodeInfo; -} - -/** - * @brief Convert node to dynamic. - * @param ContextNodeAddr : The context node address. - * @param CurrentNodeAddr : The current node address to be converted. - * @param RegisterNumber : The register number to be converted. - * @retval None. - */ -static void DMA_List_ConvertNodeToDynamic(uint32_t ContextNodeAddr, - uint32_t CurrentNodeAddr, - uint32_t RegisterNumber) -{ - uint32_t currentnode_reg_counter = 0U; - uint32_t contextnode_reg_counter = 0U; - uint32_t cllr_idx = RegisterNumber - 1U; - DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; - DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; - uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, - DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL - }; - - /* Update ULL position according to register number */ - update_link[cllr_idx] = update_link[NODE_MAXIMUM_SIZE - 1U]; - - /* Repeat for all node registers */ - while (contextnode_reg_counter != RegisterNumber) - { - /* Check if register values are equal (exception for CSAR, CDAR and CLLR registers) */ - if ((context_node->LinkRegisters[contextnode_reg_counter] == - current_node->LinkRegisters[currentnode_reg_counter]) && - (contextnode_reg_counter != NODE_CSAR_DEFAULT_OFFSET) && - (contextnode_reg_counter != NODE_CDAR_DEFAULT_OFFSET) && - (contextnode_reg_counter != (RegisterNumber - 1U))) - { - /* Format the node according to unused registers */ - DMA_List_FormatNode(current_node, currentnode_reg_counter, RegisterNumber, NODE_DYNAMIC_FORMAT); - - /* Update CLLR index */ - cllr_idx --; - - /* Update CLLR fields */ - current_node->LinkRegisters[cllr_idx] &= ~update_link[contextnode_reg_counter]; - } - else - { - /* Update context node register fields with new values */ - context_node->LinkRegisters[contextnode_reg_counter] = current_node->LinkRegisters[currentnode_reg_counter]; - - /* Update CLLR fields */ - current_node->LinkRegisters[cllr_idx] |= update_link[contextnode_reg_counter]; - - /* Increment current node number register counter */ - currentnode_reg_counter++; - } - - /* Increment context node number register counter */ - contextnode_reg_counter++; - } - - /* Update node information */ - MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((currentnode_reg_counter - 1U) << NODE_CLLR_IDX_POS)); - - /* Clear unused node fields */ - DMA_List_ClearUnusedFields(current_node, currentnode_reg_counter); -} - -/** - * @brief Convert node to static. - * @param ContextNodeAddr : The context node address. - * @param CurrentNodeAddr : The current node address to be converted. - * @param RegisterNumber : The register number to be converted. - * @retval None. - */ -static void DMA_List_ConvertNodeToStatic(uint32_t ContextNodeAddr, - uint32_t CurrentNodeAddr, - uint32_t RegisterNumber) -{ - uint32_t contextnode_reg_counter = 0U; - uint32_t cllr_idx; - uint32_t cllr_mask; - DMA_NodeTypeDef *context_node = (DMA_NodeTypeDef *)ContextNodeAddr; - DMA_NodeTypeDef *current_node = (DMA_NodeTypeDef *)CurrentNodeAddr; - uint32_t update_link[NODE_MAXIMUM_SIZE] = {DMA_CLLR_UT1, DMA_CLLR_UT2, DMA_CLLR_UB1, DMA_CLLR_USA, - DMA_CLLR_UDA, DMA_CLLR_UT3, DMA_CLLR_UB2, DMA_CLLR_ULL - }; - - /* Update ULL position according to register number */ - update_link[RegisterNumber - 1U] = update_link[NODE_MAXIMUM_SIZE - 1U]; - - /* Get context node CLLR information */ - cllr_idx = (context_node->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; - cllr_mask = context_node->LinkRegisters[cllr_idx]; - - /* Repeat for all node registers */ - while (contextnode_reg_counter != RegisterNumber) - { - /* Check if node field is dynamic */ - if ((cllr_mask & update_link[contextnode_reg_counter]) == 0U) - { - /* Format the node according to unused registers */ - DMA_List_FormatNode(current_node, contextnode_reg_counter, RegisterNumber, NODE_STATIC_FORMAT); - - /* Update node field */ - current_node->LinkRegisters[contextnode_reg_counter] = context_node->LinkRegisters[contextnode_reg_counter]; - } - - /* Increment context node number register counter */ - contextnode_reg_counter++; - } - - /* Update node information */ - MODIFY_REG(current_node->NodeInfo, NODE_CLLR_IDX, ((RegisterNumber - 1U) << NODE_CLLR_IDX_POS)); -} - -/** - * @brief Format the node according to unused registers. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @param RegisterIdx : The first register index to be formatted. - * @param RegisterNumber : The number of node registers. - * @param Format : The format type. - * @retval None. - */ -static void DMA_List_FormatNode(DMA_NodeTypeDef *const pNode, - uint32_t RegisterIdx, - uint32_t RegisterNumber, - uint32_t Format) -{ - if (Format == NODE_DYNAMIC_FORMAT) - { - /* Repeat for all registers to be formatted */ - for (uint32_t reg_idx = RegisterIdx; reg_idx < (RegisterNumber - 1U); reg_idx++) - { - pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx + 1U]; - } - } - else - { - /* Repeat for all registers to be formatted */ - for (uint32_t reg_idx = (RegisterNumber - 2U); reg_idx > RegisterIdx; reg_idx--) - { - pNode->LinkRegisters[reg_idx] = pNode->LinkRegisters[reg_idx - 1U]; - } - } -} - -/** - * @brief Clear unused register fields. - * @param pNode : Pointer to a DMA_NodeTypeDef structure that contains linked-list node registers - * configurations. - * @param FirstUnusedField : The first unused field to be cleared. - * @retval None. - */ -static void DMA_List_ClearUnusedFields(DMA_NodeTypeDef *const pNode, - uint32_t FirstUnusedField) -{ - /* Repeat for all unused fields */ - for (uint32_t reg_idx = FirstUnusedField; reg_idx < NODE_MAXIMUM_SIZE; reg_idx++) - { - pNode->LinkRegisters[reg_idx] = 0U; - } -} - -/** - * @brief Update CLLR for all dynamic queue nodes. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param LastNode_IsCircular : The first circular node is the last queue node or not. - * @retval None. - */ -static void DMA_List_UpdateDynamicQueueNodesCLLR(DMA_QListTypeDef const *const pQList, - uint32_t LastNode_IsCircular) -{ - uint32_t previous_cllr_offset; - uint32_t current_cllr_offset = 0U; - uint32_t previousnode_addr; - uint32_t currentnode_addr = (uint32_t)pQList->Head; - uint32_t cllr_mask; - uint32_t node_idx = 0U; - - /* Repeat for all register nodes */ - while (node_idx < pQList->NodeNumber) - { - /* Get head node address */ - if (node_idx == 0U) - { - /* Get current node information */ - current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; - } - /* Calculate nodes addresses */ - else - { - /* Get previous node information */ - previousnode_addr = currentnode_addr; - previous_cllr_offset = current_cllr_offset; - - /* Get current node information */ - currentnode_addr = (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA) + - ((uint32_t)pQList->Head & DMA_CLBAR_LBA); - current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; - - /* Calculate CLLR register value to be updated */ - cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & ~DMA_CLLR_LA) | - (((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] & DMA_CLLR_LA); - - /* Set new CLLR value to previous node */ - ((DMA_NodeTypeDef *)(previousnode_addr))->LinkRegisters[previous_cllr_offset] = cllr_mask; - } - - /* Increment node index */ - node_idx++; - } - - /* Check queue circularity */ - if (pQList->FirstCircularNode != 0U) - { - /* First circular queue is not last queue node */ - if (LastNode_IsCircular == 0U) - { - /* Get CLLR node information */ - DMA_List_GetCLLRNodeInfo(((DMA_NodeTypeDef *)currentnode_addr), &cllr_mask, NULL); - - /* Update CLLR register for last circular node */ - ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = - ((uint32_t)pQList->Head & DMA_CLLR_LA) | cllr_mask; - } - /* First circular queue is last queue node */ - else - { - /* Disable CLLR updating */ - ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] &= ~DMA_CLLR_ULL; - } - } - else - { - /* Clear CLLR register for last node */ - ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] = 0U; - } -} - -/** - * @brief Update CLLR for all static queue nodes. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @param operation : The operation type. - * @retval None. - */ -static void DMA_List_UpdateStaticQueueNodesCLLR(DMA_QListTypeDef const *const pQList, - uint32_t operation) -{ - uint32_t currentnode_addr = (uint32_t)pQList->Head; - uint32_t current_cllr_offset = ((uint32_t)pQList->Head->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; - uint32_t cllr_default_offset; - uint32_t cllr_default_mask; - uint32_t cllr_mask; - uint32_t node_idx = 0U; - - /* Get CLLR node information */ - DMA_List_GetCLLRNodeInfo(pQList->Head, &cllr_default_mask, &cllr_default_offset); - - /* Repeat for all register nodes (Bypass last queue node) */ - while (node_idx < pQList->NodeNumber) - { - if (operation == UPDATE_CLLR_POSITION) - { - /* Get CLLR value */ - cllr_mask = ((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset]; - } - else - { - /* Calculate CLLR value */ - cllr_mask = (((DMA_NodeTypeDef *)currentnode_addr)->LinkRegisters[current_cllr_offset] & DMA_CLLR_LA) | - cllr_default_mask; - } - - /* Set new CLLR value to default position */ - if ((node_idx == (pQList->NodeNumber - 1U)) && (pQList->FirstCircularNode == NULL)) - { - ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = 0U; - } - else - { - ((DMA_NodeTypeDef *)(currentnode_addr))->LinkRegisters[cllr_default_offset] = cllr_mask; - } - - /* Update current node address with next node address */ - currentnode_addr = (currentnode_addr & DMA_CLBAR_LBA) | (cllr_mask & DMA_CLLR_LA); - - /* Update current CLLR offset with next CLLR offset */ - current_cllr_offset = (((DMA_NodeTypeDef *)currentnode_addr)->NodeInfo & NODE_CLLR_IDX) >> NODE_CLLR_IDX_POS; - - /* Increment node index */ - node_idx++; - } -} - -/** - * @brief Clean linked-list queue variable. - * @param pQList : Pointer to a DMA_QListTypeDef structure that contains queue information. - * @retval None. - */ -static void DMA_List_CleanQueue(DMA_QListTypeDef *const pQList) -{ - /* Clear head node */ - pQList->Head = NULL; - - /* Clear first circular queue node */ - pQList->FirstCircularNode = NULL; - - /* Reset node number */ - pQList->NodeNumber = 0U; - - /* Reset queue state */ - pQList->State = HAL_DMA_QUEUE_STATE_RESET; - - /* Reset queue error code */ - pQList->ErrorCode = HAL_DMA_QUEUE_ERROR_NONE; - - /* Reset queue type */ - pQList->Type = QUEUE_TYPE_STATIC; -} -/** - * @} - */ - -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c deleted file mode 100644 index 65d95190e..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_exti.c +++ /dev/null @@ -1,845 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_exti.c - * @author MCD Application Team - * @brief EXTI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (EXTI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### EXTI Peripheral features ##### - ============================================================================== - [..] - (+) Each Exti line can be configured within this driver. - - (+) Exti line can be configured in 3 different modes - (++) Interrupt - (++) Event - (++) Both of them - - (+) Configurable Exti lines can be configured with 3 different triggers - (++) Rising - (++) Falling - (++) Both of them - - (+) When set in interrupt mode, configurable Exti lines have two diffenrents - interrupt pending registers which allow to distinguish which transition - occurs: - (++) Rising edge pending interrupt - (++) Falling - - (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can - be selected through multiplexer. - - ##### How to use this driver ##### - ============================================================================== - [..] - - (#) Configure the EXTI line using HAL_EXTI_SetConfigLine(). - (++) Choose the interrupt line number by setting "Line" member from - EXTI_ConfigTypeDef structure. - (++) Configure the interrupt and/or event mode using "Mode" member from - EXTI_ConfigTypeDef structure. - (++) For configurable lines, configure rising and/or falling trigger - "Trigger" member from EXTI_ConfigTypeDef structure. - (++) For Exti lines linked to gpio, choose gpio port using "GPIOSel" - member from GPIO_InitTypeDef structure. - - (#) Get current Exti configuration of a dedicated line using - HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - (++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter. - - (#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine(). - (++) Provide exiting handle as parameter. - - (#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback(). - (++) Provide exiting handle as first parameter. - (++) Provide which callback will be registered using one value from - EXTI_CallbackIDTypeDef. - (++) Provide callback function pointer. - - (#) Get interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Clear interrupt pending bit using HAL_EXTI_GetPending(). - - (#) Generate software interrupt using HAL_EXTI_GenerateSWI(). - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup EXTI - * @{ - */ - -#ifdef HAL_EXTI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines ------------------------------------------------------------*/ -/** @defgroup EXTI_Private_Constants EXTI Private Constants - * @{ - */ -#define EXTI_MODE_OFFSET 0x04U /* byte offset between IMR/EMR registers */ -#define EXTI_CONFIG_OFFSET 0x08U /* byte offset between Rising/Falling configuration registers */ -#define EXTI_PRIVCFGR_OFFSET 0x04U /* byte offset between PRIVCFGR1/PRIVCFGR2 registers */ -#define EXTI_SECCFGR_OFFSET 0x04U /* byte offset between SECCFGR1/SECCFGR2 registers */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup EXTI_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_Exported_Functions_Group1 - * @brief Configuration functions - * -@verbatim - =============================================================================== - ##### Configuration functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Set configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on EXTI configuration to be set. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - __IO uint32_t *regaddr; - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - uint32_t offset; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_EXTI_LINE(pExtiConfig->Line)); - assert_param(IS_EXTI_MODE(pExtiConfig->Mode)); - - /* Assign line number to handle */ - hexti->Line = pExtiConfig->Line; - - /* compute line register offset and line mask */ - offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1UL << linepos); - - /* Configure triggers for configurable lines */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) - { - assert_param(IS_EXTI_TRIGGER(pExtiConfig->Trigger)); - - /* Configure rising trigger */ - regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = *regaddr; - - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_RISING) != 0U) - { - regval |= maskline; - } - else - { - regval &= ~maskline; - } - - /* Store rising trigger mode */ - *regaddr = regval; - - /* Configure falling trigger */ - regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = *regaddr; - - /* Mask or set line */ - if ((pExtiConfig->Trigger & EXTI_TRIGGER_FALLING) != 0U) - { - regval |= maskline; - } - else - { - regval &= ~maskline; - } - - /* Store falling trigger mode */ - *regaddr = regval; - - /* Configure gpio port selection in case of gpio exti line */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PORT(pExtiConfig->GPIOSel)); - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; - regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); - regval |= (pExtiConfig->GPIOSel << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); - EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; - } - } - - /* Configure interrupt mode : read current mode */ - regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); - regval = *regaddr; - - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_INTERRUPT) != 0U) - { - regval |= maskline; - } - else - { - regval &= ~maskline; - } - - /* Store interrupt mode */ - *regaddr = regval; - - /* Configure event mode : read current mode */ - regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); - regval = *regaddr; - - /* Mask or set line */ - if ((pExtiConfig->Mode & EXTI_MODE_EVENT) != 0U) - { - regval |= maskline; - } - else - { - regval &= ~maskline; - } - - /* Store event mode */ - *regaddr = regval; - - return HAL_OK; -} - - -/** - * @brief Get configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @param pExtiConfig Pointer on structure to store Exti configuration. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) -{ - const __IO uint32_t *regaddr; - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - uint32_t offset; - - /* Check null pointer */ - if ((hexti == NULL) || (pExtiConfig == NULL)) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* Store handle line number to configiguration structure */ - pExtiConfig->Line = hexti->Line; - - /* compute line register offset and line mask */ - offset = ((pExtiConfig->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - linepos = (pExtiConfig->Line & EXTI_PIN_MASK); - maskline = (1UL << linepos); - - /* 1] Get core mode : interrupt */ - regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); - regval = *regaddr; - - /* Check if selected line is enable */ - if ((regval & maskline) != 0U) - { - pExtiConfig->Mode = EXTI_MODE_INTERRUPT; - } - else - { - pExtiConfig->Mode = EXTI_MODE_NONE; - } - - /* Get event mode */ - regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); - regval = *regaddr; - - /* Check if selected line is enable */ - if ((regval & maskline) != 0U) - { - pExtiConfig->Mode |= EXTI_MODE_EVENT; - } - - /* 2] Get trigger for configurable lines : rising */ - if ((pExtiConfig->Line & EXTI_CONFIG) != 0U) - { - regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = *regaddr; - - /* Get default Trigger and GPIOSel configuration */ - pExtiConfig->Trigger = EXTI_TRIGGER_NONE; - pExtiConfig->GPIOSel = 0x00u; - - /* Check if configuration of selected line is enable */ - if ((regval & maskline) != 0U) - { - pExtiConfig->Trigger = EXTI_TRIGGER_RISING; - } - - /* Get falling configuration */ - regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = *regaddr; - - /* Check if configuration of selected line is enable */ - if ((regval & maskline) != 0U) - { - pExtiConfig->Trigger |= EXTI_TRIGGER_FALLING; - } - - /* Get Gpio port selection for gpio lines */ - if ((pExtiConfig->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; - pExtiConfig->GPIOSel = (regval >> (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))) & EXTI_EXTICR1_EXTI0; - } - } - - return HAL_OK; -} - - -/** - * @brief Clear whole configuration of a dedicated Exti line. - * @param hexti Exti handle. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) -{ - __IO uint32_t *regaddr; - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - uint32_t offset; - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_EXTI_LINE(hexti->Line)); - - /* compute line register offset and line mask */ - offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1UL << linepos); - - /* 1] Clear interrupt mode */ - regaddr = (__IO uint32_t *)(&EXTI->IMR1 + (EXTI_MODE_OFFSET * offset)); - regval = (*regaddr & ~maskline); - *regaddr = regval; - - /* 2] Clear event mode */ - regaddr = (__IO uint32_t *)(&EXTI->EMR1 + (EXTI_MODE_OFFSET * offset)); - regval = (*regaddr & ~maskline); - *regaddr = regval; - - /* 3] Clear triggers in case of configurable lines */ - if ((hexti->Line & EXTI_CONFIG) != 0U) - { - regaddr = (__IO uint32_t *)(&EXTI->RTSR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = (*regaddr & ~maskline); - *regaddr = regval; - - regaddr = (__IO uint32_t *)(&EXTI->FTSR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = (*regaddr & ~maskline); - *regaddr = regval; - - /* Get Gpio port selection for gpio lines */ - if ((hexti->Line & EXTI_GPIO) == EXTI_GPIO) - { - assert_param(IS_EXTI_GPIO_PIN(linepos)); - - regval = EXTI->EXTICR[(linepos >> 2U) & 0x03UL]; - regval &= ~(EXTI_EXTICR1_EXTI0 << (EXTI_EXTICR1_EXTI1_Pos * (linepos & 0x03U))); - EXTI->EXTICR[(linepos >> 2U) & 0x03UL] = regval; - } - } - - return HAL_OK; -} - - -/** - * @brief Register callback for a dedicaated Exti line. - * @param hexti Exti handle. - * @param CallbackID User callback identifier. - * This parameter can be one of @arg @ref EXTI_CallbackIDTypeDef values. - * @param pPendingCbfn function pointer to be stored as callback. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, - void (*pPendingCbfn)(void)) -{ - HAL_StatusTypeDef status = HAL_OK; - - switch (CallbackID) - { - case HAL_EXTI_COMMON_CB_ID: - hexti->RisingCallback = pPendingCbfn; - hexti->FallingCallback = pPendingCbfn; - break; - - case HAL_EXTI_RISING_CB_ID: - hexti->RisingCallback = pPendingCbfn; - break; - - case HAL_EXTI_FALLING_CB_ID: - hexti->FallingCallback = pPendingCbfn; - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} - - -/** - * @brief Store line number as handle private field. - * @param hexti Exti handle. - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine) -{ - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - - /* Check null pointer */ - if (hexti == NULL) - { - return HAL_ERROR; - } - else - { - /* Store line number as handle private field */ - hexti->Line = ExtiLine; - - return HAL_OK; - } -} - - -/** - * @} - */ - -/** @addtogroup EXTI_Exported_Functions_Group2 - * @brief EXTI IO functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Handle EXTI interrupt request. - * @param hexti Exti handle. - * @retval none. - */ -void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) -{ - __IO uint32_t *regaddr; - uint32_t regval; - uint32_t maskline; - uint32_t offset; - - /* Compute line register offset and line mask */ - offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); - - /* Get rising edge pending bit */ - regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = (*regaddr & maskline); - - if (regval != 0U) - { - /* Clear pending bit */ - *regaddr = maskline; - - /* Call rising callback */ - if (hexti->RisingCallback != NULL) - { - hexti->RisingCallback(); - } - } - - /* Get falling edge pending bit */ - regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); - regval = (*regaddr & maskline); - - if (regval != 0U) - { - /* Clear pending bit */ - *regaddr = maskline; - - /* Call rising callback */ - if (hexti->FallingCallback != NULL) - { - hexti->FallingCallback(); - } - } -} - - -/** - * @brief Get interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be checked. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING - * @arg @ref EXTI_TRIGGER_FALLING - * @retval 1 if interrupt is pending else 0. - */ -uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - const __IO uint32_t *regaddr; - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - uint32_t offset; - - /* Check the parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* compute line register offset and line mask */ - offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - linepos = (hexti->Line & EXTI_PIN_MASK); - maskline = (1UL << linepos); - - if (Edge != EXTI_TRIGGER_RISING) - { - /* Get falling edge pending bit */ - regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); - } - else - { - /* Get rising edge pending bit */ - regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); - } - - /* return 1 if bit is set else 0 */ - regval = ((*regaddr & maskline) >> linepos); - return regval; -} - - -/** - * @brief Clear interrupt pending bit of a dedicated line. - * @param hexti Exti handle. - * @param Edge Specify which pending edge as to be clear. - * This parameter can be one of the following values: - * @arg @ref EXTI_TRIGGER_RISING - * @arg @ref EXTI_TRIGGER_FALLING - * @retval None. - */ -void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) -{ - __IO uint32_t *regaddr; - uint32_t maskline; - uint32_t offset; - - /* Check the parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - assert_param(IS_EXTI_PENDING_EDGE(Edge)); - - /* compute line register offset and line mask */ - offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); - - if (Edge != EXTI_TRIGGER_RISING) - { - /* Get falling edge pending register address */ - regaddr = (__IO uint32_t *)(&EXTI->FPR1 + (EXTI_CONFIG_OFFSET * offset)); - } - else - { - /* Get falling edge pending register address */ - regaddr = (__IO uint32_t *)(&EXTI->RPR1 + (EXTI_CONFIG_OFFSET * offset)); - } - - /* Clear Pending bit */ - *regaddr = maskline; -} - - -/** - * @brief Generate a software interrupt for a dedicated line. - * @param hexti Exti handle. - * @retval None. - */ -void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) -{ - __IO uint32_t *regaddr; - uint32_t maskline; - uint32_t offset; - - /* Check the parameters */ - assert_param(IS_EXTI_LINE(hexti->Line)); - assert_param(IS_EXTI_CONFIG_LINE(hexti->Line)); - - /* compute line register offset and line mask */ - offset = ((hexti->Line & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - maskline = (1UL << (hexti->Line & EXTI_PIN_MASK)); - - regaddr = (__IO uint32_t *)(&EXTI->SWIER1 + (EXTI_CONFIG_OFFSET * offset)); - *regaddr = maskline; -} - - -/** - * @} - */ - -/** @defgroup EXTI_Exported_Functions_Group3 EXTI line attributes management functions - * @brief EXTI attributes management functions. - * -@verbatim - =============================================================================== - ##### EXTI attributes functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configure the EXTI line attribute(s). - * @note Available attributes are to secure EXTI line and set EXT line as privileged. - * Default state is not secure and unprivileged access allowed. - * @note Secure and non-secure attributes can only be set from the secure - * state when the system implements the security (TZEN=1). - * @note Security and privilege attributes can be set independently. - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @param LineAttributes can be one or a combination of the following values: - * @arg @ref EXTI_LINE_PRIV Privileged-only access - * @arg @ref EXTI_LINE_NPRIV Privileged/Non-privileged access - * @arg @ref EXTI_LINE_SEC Secure-only access - * @arg @ref EXTI_LINE_NSEC Secure/Non-secure access - * @retval None - */ -void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) -{ - __IO uint32_t *regaddr; - uint32_t regval; - uint32_t linepos; - uint32_t maskline; - uint32_t offset; - - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - assert_param(IS_EXTI_LINE_ATTRIBUTES(LineAttributes)); - - /* compute line register offset and line mask */ - offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - linepos = (ExtiLine & EXTI_PIN_MASK); - maskline = (1UL << linepos); - - /* Configure privilege or non-privilege attributes */ - regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); - regval = *regaddr; - - /* Mask or set line */ - if ((LineAttributes & EXTI_LINE_PRIV) == EXTI_LINE_PRIV) - { - regval |= maskline; - } - else if ((LineAttributes & EXTI_LINE_NPRIV) == EXTI_LINE_NPRIV) - { - regval &= ~maskline; - } - else - { - /* do nothing */ - } - - /* Store privilege or non-privilege attribute */ - *regaddr = regval; - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /* Configure secure or non-secure attributes */ - regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); - regval = *regaddr; - - /* Mask or set line */ - if ((LineAttributes & EXTI_LINE_SEC) == EXTI_LINE_SEC) - { - regval |= maskline; - } - else if ((LineAttributes & EXTI_LINE_NSEC) == EXTI_LINE_NSEC) - { - regval &= ~maskline; - } - else - { - /* do nothing */ - } - - /* Store secure or non-secure attribute */ - *regaddr = regval; - -#endif /* __ARM_FEATURE_CMSE */ -} - -/** - * @brief Get the EXTI line attribute(s). - * @note Secure and non-secure attributes are only available from secure state - * when the system implements the security (TZEN=1) - * @param ExtiLine Exti line number. - * This parameter can be from 0 to @ref EXTI_LINE_NB. - * @param pLineAttributes: pointer to return line attributes. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) -{ - const __IO uint32_t *regaddr; - uint32_t linepos; - uint32_t maskline; - uint32_t offset; - uint32_t attributes; - - /* Check null pointer */ - if (pLineAttributes == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_EXTI_LINE(ExtiLine)); - - /* Compute line register offset and line mask */ - offset = ((ExtiLine & EXTI_REG_MASK) >> EXTI_REG_SHIFT); - linepos = (ExtiLine & EXTI_PIN_MASK); - maskline = (1UL << linepos); - - /* Get privilege or non-privilege attribute */ - regaddr = (__IO uint32_t *)(&EXTI->PRIVCFGR1 + (EXTI_PRIVCFGR_OFFSET * offset)); - - if ((*regaddr & maskline) != 0U) - { - attributes = EXTI_LINE_PRIV; - } - else - { - attributes = EXTI_LINE_NPRIV; - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /* Get secure or non-secure attribute */ - regaddr = (__IO uint32_t *)(&EXTI->SECCFGR1 + (EXTI_SECCFGR_OFFSET * offset)); - - if ((*regaddr & maskline) != 0U) - { - attributes |= EXTI_LINE_SEC; - } - else - { - attributes |= EXTI_LINE_NSEC; - } - -#endif /* __ARM_FEATURE_CMSE */ - - /* return value */ - *pLineAttributes = attributes; - - return HAL_OK; -} -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Lock the secure and privilege configuration registers. - * @retval None - */ -void HAL_EXTI_LockAttributes(void) -{ - SET_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); -} - -/** - * @brief Return the secure and privilege configuration registers LOCK status - * @retval 1 if the secure and privilege configuration registers have been locked else 0. - */ -uint32_t HAL_EXTI_GetLockAttributes(void) -{ - return READ_BIT(EXTI->LOCKR, EXTI_LOCKR_LOCK); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_EXTI_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c deleted file mode 100644 index 4e4bf1601..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash.c +++ /dev/null @@ -1,774 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_flash.c - * @author MCD Application Team - * @brief FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the internal FLASH memory: - * + Program operations functions - * + Memory Control functions - * + Peripheral Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### FLASH peripheral features ##### - ============================================================================== - - [..] The Flash memory interface manages CPU AHB C-Bus accesses to the Flash memory. - It implements the erase and program Flash memory operations and the read - and write protection mechanisms. - - [..] The Flash memory interface implements the TrustZone security features (TZ) supported - by ARM Cortex-M33 core (CM33). - - [..] The FLASH main features are: - (+) Flash memory read operations - (+) Flash memory program/erase operations - (+) Read / write protections - (+) Option bytes programming - (+) TrustZone aware - (+) Watermark-based area protection including the secure hide area - (+) Block-based page protection - (+) Error code correction (ECC) : Data in flash are 137-bits word - (9 bits added per quad-word) - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver provides functions and macros to configure and program the FLASH - memory of all STM32U5xx devices. - - (#) Flash Memory IO Programming functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Program functions: quad-words and burst program (8 quad-words) - (++) There are two modes of programming : - (+++) Polling mode using HAL_FLASH_Program() function - (+++) Interrupt mode using HAL_FLASH_Program_IT() function - - (#) Interrupts and flags management functions : - (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler() - (++) Callback functions are called when the flash operations are finished : - HAL_FLASH_EndOfOperationCallback() when everything is ok, otherwise - HAL_FLASH_OperationErrorCallback() - (++) Get error flag status by calling HAL_GetError() - - (#) Option bytes management functions : - (++) Lock and Unlock the option bytes using HAL_FLASH_OB_Unlock() and - HAL_FLASH_OB_Lock() functions - (++) Launch the reload of the option bytes using HAL_FLASH_Launch() function. - In this case, a reset is generated - - [..] - In addition to these functions, this driver includes a set of macros allowing - to handle the following operations: - (+) Set the latency - (+) Enable/Disable the Flash power-down during low-power run and sleep modes - (+) Enable/Disable the Flash interrupts - (+) Monitor the Flash flags status - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASH FLASH - * @brief FLASH HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup FLASH_Private_Variables FLASH Private Variables - * @{ - */ -/** - * @brief Variable used for Program/Erase sectors under interruption - */ -FLASH_ProcessTypeDef pFlash = {.Lock = HAL_UNLOCKED, \ - .ErrorCode = HAL_FLASH_ERROR_NONE, \ - .ProcedureOnGoing = 0U, \ - .Address = 0U, \ - .Bank = FLASH_BANK_1, \ - .Page = 0U, \ - .NbPagesToErase = 0U - }; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASH_Private_Functions FLASH Private Functions - * @{ - */ -static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress); -static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup FLASH_Exported_Functions FLASH Exported Functions - * @{ - */ - -/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions - * @brief Programming operation functions - * -@verbatim - =============================================================================== - ##### Programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the FLASH - program operations. - -@endverbatim - * @{ - */ - -/** - * @brief Program a quad-word or a burst of 8 quad-words at a specified address. - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * This parameter shall be aligned to the Flash word (128 bits) - * @param DataAddress specifies the address of data to be programmed. - * This parameter shall be 32-bit aligned - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) -{ - HAL_StatusTypeDef status; - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Reset error code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Set current operation type */ - pFlash.ProcedureOnGoing = TypeProgram; - - /* Access to SECCR or NSCR depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - - if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) - { - /* Program a quad-word (128-bit) at a specified address */ - FLASH_Program_QuadWord(Address, DataAddress); - } - else - { - /* Program a burst of 8 quad-words at a specified address */ - FLASH_Program_Burst(Address, DataAddress); - } - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - /* If the program operation is completed, disable the PG (and BWR Bit in Burst programming mode) */ - CLEAR_BIT((*reg_cr), (TypeProgram & ~(FLASH_NON_SECURE_MASK))); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - /* return status */ - return status; -} - -/** - * @brief Program a quad-word or a burst of 8 quad-words at a specified address with interrupt enabled. - * @param TypeProgram Indicate the way to program at a specified address. - * This parameter can be a value of @ref FLASH_Type_Program - * @param Address specifies the address to be programmed. - * This parameter shall be aligned to the Flash word (128 bits) - * @param DataAddress specifies the address of data to be programmed. - * This parameter shall be 32-bit aligned - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t DataAddress) -{ - HAL_StatusTypeDef status; - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEPROGRAM(TypeProgram)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Reset error code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } - else - { - /* Set internal variables used by the IRQ handler */ - pFlash.ProcedureOnGoing = TypeProgram; - pFlash.Address = Address; - - /* Access to SECCR or NSCR depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - - /* Enable End of Operation and Error interrupts */ - (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR); - - if ((TypeProgram & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) - { - /* Program a quad-word (128-bit) at a specified address */ - FLASH_Program_QuadWord(Address, DataAddress); - } - else - { - /* Program a burst of 8 quad-words at a specified address */ - FLASH_Program_Burst(Address, DataAddress); - } - } - - return status; -} - -/** - * @brief Handle FLASH interrupt request. - * @retval None - */ -void HAL_FLASH_IRQHandler(void) -{ - uint32_t param = 0U; - uint32_t error; - __IO uint32_t *reg_cr; - __IO uint32_t *reg_sr; - - /* Access to CR and SR registers depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); - - /* Save Flash errors */ - error = (*reg_sr) & FLASH_FLAG_SR_ERRORS; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR); -#endif /* __ARM_FEATURE_CMSE */ - - /* Set parameter of the callback */ - if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES) - { - param = pFlash.Page; - } - else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) - { - param = pFlash.Bank; - } - else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_QUADWORD) - { - param = pFlash.Address; - } - else if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEPROGRAM_BURST) - { - param = pFlash.Address; - } - else - { - /* Empty statement (to be compliant MISRA 15.7) */ - } - - /* Clear operation bit on the on-going procedure */ - CLEAR_BIT((*reg_cr), (pFlash.ProcedureOnGoing & ~(FLASH_NON_SECURE_MASK))); - - /* Check FLASH operation error flags */ - if (error != 0U) - { - /* Save the error code */ - pFlash.ErrorCode |= error; - - /* Clear error programming flags */ - (*reg_sr) = error; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if ((error & FLASH_FLAG_OPTWERR) != 0U) - { - FLASH->NSSR = FLASH_FLAG_OPTWERR; - } -#endif /* __ARM_FEATURE_CMSE */ - - /* Stop the procedure ongoing */ - pFlash.ProcedureOnGoing = 0U; - - /* FLASH error interrupt user callback */ - HAL_FLASH_OperationErrorCallback(param); - } - - /* Check FLASH End of Operation flag */ - if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) - { - /* Clear FLASH End of Operation pending bit */ - (*reg_sr) = FLASH_FLAG_EOP; - - if ((pFlash.ProcedureOnGoing & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_PAGES) - { - /* Nb of pages to erase can be decreased */ - pFlash.NbPagesToErase--; - - /* Check if there are still pages to erase */ - if (pFlash.NbPagesToErase != 0U) - { - /* Increment page number */ - pFlash.Page++; - FLASH_PageErase(pFlash.Page, pFlash.Bank); - } - else - { - /* No more pages to Erase */ - pFlash.ProcedureOnGoing = 0U; - param = 0xFFFFFFFFU; - } - } - else - { - /*Clear the procedure ongoing*/ - pFlash.ProcedureOnGoing = 0U; - } - - /* FLASH EOP interrupt user callback */ - HAL_FLASH_EndOfOperationCallback(param); - } - - if (pFlash.ProcedureOnGoing == 0U) - { - /* Disable End of Operation and Error interrupts */ - (*reg_cr) &= ~(FLASH_IT_EOP | FLASH_IT_OPERR); - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } -} - -/** - * @brief FLASH end of operation interrupt callback. - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page which has been erased - * (if 0xFFFFFFFF, it means that all the selected pages have been erased) - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_FLASH_EndOfOperationCallback could be implemented in the user file - */ -} - -/** - * @brief FLASH operation error interrupt callback. - * @param ReturnValue The value saved in this parameter depends on the ongoing procedure - * Mass Erase: Bank number which has been requested to erase - * Page Erase: Page number which returned an error - * Program: Address which was selected for data program - * @retval None - */ -__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(ReturnValue); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_FLASH_OperationErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions - * @brief Management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the FLASH - memory operations. - -@endverbatim - * @{ - */ - -/** - * @brief Unlock the FLASH control register access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Unlock(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->NSKEYR, FLASH_KEY1); - WRITE_REG(FLASH->NSKEYR, FLASH_KEY2); - - /* verify Flash is unlocked */ - if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) - { - status = HAL_ERROR; - } - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if (status == HAL_OK) - { - if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) - { - /* Authorize the FLASH Registers access */ - WRITE_REG(FLASH->SECKEYR, FLASH_KEY1); - WRITE_REG(FLASH->SECKEYR, FLASH_KEY2); - - /* verify Flash is unlocked */ - if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) - { - status = HAL_ERROR; - } - } - } -#endif /* __ARM_FEATURE_CMSE */ - - return status; -} - -/** - * @brief Lock the FLASH control register access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_Lock(void) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Set the LOCK Bit to lock the FLASH Registers access */ - SET_BIT(FLASH->NSCR, FLASH_NSCR_LOCK); - - /* verify Flash is locked */ - if (READ_BIT(FLASH->NSCR, FLASH_NSCR_LOCK) != 0U) - { - status = HAL_OK; - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if (status == HAL_OK) - { - SET_BIT(FLASH->SECCR, FLASH_SECCR_LOCK); - - /* verify Flash is locked */ - if (READ_BIT(FLASH->SECCR, FLASH_SECCR_LOCK) != 0U) - { - status = HAL_OK; - } - } -#endif /* __ARM_FEATURE_CMSE */ - - return status; -} - -/** - * @brief Unlock the FLASH Option Bytes Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void) -{ - if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U) - { - /* Authorizes the Option Byte register programming */ - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY1); - WRITE_REG(FLASH->OPTKEYR, FLASH_OPTKEY2); - - /* Verify that the Option Bytes are unlocked */ - if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U) - { - return HAL_ERROR; - } - } - - return HAL_OK; -} - -/** - * @brief Lock the FLASH Option Bytes Registers access. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) -{ - /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ - SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK); - - /* Verify that the Option Bytes are locked */ - if (READ_BIT(FLASH->NSCR, FLASH_NSCR_OPTLOCK) != 0U) - { - return HAL_OK; - } - - return HAL_ERROR; -} - -/** - * @brief Launch the option byte loading. - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) -{ - /* Set the bit to force the option byte reloading */ - SET_BIT(FLASH->NSCR, FLASH_NSCR_OBL_LAUNCH); - - /* We should not reach here : Option byte launch generates Option byte reset - so return error */ - return HAL_ERROR; -} - -/** - * @} - */ - -/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief Peripheral Errors functions - * -@verbatim - =============================================================================== - ##### Peripheral Errors functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time Errors of the FLASH peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Get the specific FLASH error flag. - * @retval FLASH_ErrorCode The returned value can be: - * @arg HAL_FLASH_ERROR_NONE: No error set - * @arg HAL_FLASH_ERROR_OP: FLASH Operation error - * @arg HAL_FLASH_ERROR_PROG: FLASH Programming error - * @arg HAL_FLASH_ERROR_WRP: FLASH Write protection error - * @arg HAL_FLASH_ERROR_PGA: FLASH Programming alignment error - * @arg HAL_FLASH_ERROR_SIZ: FLASH Size error - * @arg HAL_FLASH_ERROR_PGS: FLASH Programming sequence error - * @arg HAL_FLASH_ERROR_OPTW: FLASH Option modification error - */ -uint32_t HAL_FLASH_GetError(void) -{ - return pFlash.ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup FLASH_Private_Functions - * @{ - */ - -/** - * @brief Wait for a FLASH operation to complete. - * @param Timeout maximum flash operation timeout - * @retval HAL Status - */ -HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) -{ - /* Wait for the FLASH operation to complete by polling on BUSY and WDW flags to be reset. - Even if the FLASH operation fails, the BUSY & WDW flags will be reset, and an error flag will be set */ - - uint32_t timeout = HAL_GetTick() + Timeout; - uint32_t error; - __IO uint32_t *reg_sr; - - /* Access to SECSR or NSSR registers depends on operation type */ - reg_sr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECSR) : &(FLASH_NS->NSSR); - - while (((*reg_sr) & (FLASH_FLAG_BSY | FLASH_FLAG_WDW)) != 0U) - { - if (Timeout != HAL_MAX_DELAY) - { - if (HAL_GetTick() >= timeout) - { - return HAL_TIMEOUT; - } - } - } - - /* Check FLASH operation error flags */ - error = ((*reg_sr) & FLASH_FLAG_SR_ERRORS); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - error |= (FLASH->NSSR & FLASH_FLAG_OPTWERR); -#endif /* __ARM_FEATURE_CMSE */ - - if (error != 0U) - { - /*Save the error code*/ - pFlash.ErrorCode |= error; - - /* Clear error programming flags */ - (*reg_sr) = error; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if ((error & FLASH_FLAG_OPTWERR) != 0U) - { - FLASH->NSSR = FLASH_FLAG_OPTWERR; - } -#endif /* __ARM_FEATURE_CMSE */ - - return HAL_ERROR; - } - - /* Check FLASH End of Operation flag */ - if (((*reg_sr) & FLASH_FLAG_EOP) != 0U) - { - /* Clear FLASH End of Operation pending bit */ - (*reg_sr) = FLASH_FLAG_EOP; - } - - /* If there is no error flag set */ - return HAL_OK; -} - -/** - * @brief Program a quad-word (128-bit) at a specified address. - * @param Address specifies the address to be programmed. - * @param DataAddress specifies the address of data to be programmed. - * @retval None - */ -static void FLASH_Program_QuadWord(uint32_t Address, uint32_t DataAddress) -{ - uint8_t index = 4; - uint32_t *dest_addr = (uint32_t *)Address; - uint32_t *src_addr = (uint32_t *)DataAddress; - uint32_t primask_bit; - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_PROGRAM_ADDRESS(Address)); - - /* Access to SECCR or NSCR registers depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - - /* Set PG bit */ - SET_BIT((*reg_cr), FLASH_NSCR_PG); - - /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ - primask_bit = __get_PRIMASK(); - __disable_irq(); - - /* Program the quad-word */ - do - { - *dest_addr = *src_addr; - dest_addr++; - src_addr++; - index--; - } while (index != 0U); - - /* Exit critical section: restore previous priority mask */ - __set_PRIMASK(primask_bit); -} - -/** - * @brief Program a burst of 8x quad-words at a specified address. - * @param Address: specifies the address to be programmed. - * @param DataAddress: specifies the address where the data are stored. - * @retval None - */ -static void FLASH_Program_Burst(uint32_t Address, uint32_t DataAddress) -{ - uint8_t burst_index = FLASH_NB_WORDS_IN_BURST; - uint32_t *dest_addr = (uint32_t *)Address; - uint32_t *src_addr = (uint32_t *)DataAddress; - uint32_t primask_bit; - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_MAIN_MEM_ADDRESS(Address)); - - /* Access to SECCR or NSCR registers depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - - /* Set PG and BWR bits */ - SET_BIT((*reg_cr), (FLASH_NSCR_PG | FLASH_NSCR_BWR)); - - /* Enter critical section: Disable interrupts to avoid any interruption during the loop */ - primask_bit = __get_PRIMASK(); - __disable_irq(); - - /* Program the burst */ - do - { - *dest_addr = *src_addr; - dest_addr++; - src_addr++; - burst_index--; - } while (burst_index != 0U); - - /* Exit critical section: restore previous priority mask */ - __set_PRIMASK(primask_bit); -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c deleted file mode 100644 index df267a706..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_flash_ex.c +++ /dev/null @@ -1,1698 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_flash_ex.c - * @author MCD Application Team - * @brief Extended FLASH HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the FLASH extended peripheral: - * + Extended programming operations functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### Flash Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the FLASH interface for STM32U5xx - devices contains the following additional features - - (+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write - capability (RWW) - (+) Dual bank memory organization - (+) Watermark-based secure area including the secure hide areas - (+) Block-based secure pages - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure and program the FLASH memory - of all STM32U5xx devices. It includes: - (#) Flash Memory Erase functions: - (++) Lock and Unlock the FLASH interface using HAL_FLASH_Unlock() and - HAL_FLASH_Lock() functions - (++) Erase function: page Erase and Bank/Mass Erase - (++) There are two modes of erase : - (+++) Polling Mode using HAL_FLASHEx_Erase() - (+++) Interrupt Mode using HAL_FLASHEx_Erase_IT() - - (#) Option Bytes Programming function: Use HAL_FLASHEx_OBProgram() to: - (++) Configure the write protection for each area - (++) Set the Read protection Level - (++) Program the user Option Bytes - (++) Configure the watermark security for each area including the secure hide areas - (++) Configure the boot lock (BOOT_LOCK) - (++) Configure the Boot addresses - - (#) Get Option Bytes Configuration function: Use HAL_FLASHEx_OBGetConfig() to: - (++) Get the value of a write protection area - (++) Know if the read protection is activated - (++) Get the value of the user Option Bytes - (++) Get the configuration of a watermark security area including the secure hide areas - (++) Get the boot lock (BOOT_LOCK) configuration - (++) Get the value of a boot address - - (#) Block-based secure / privilege area configuration function: Use HAL_FLASHEx_ConfigBBAttributes() - (++) Bit-field allowing to secure or un-secure each page - (++) Bit-field allowing to privilege or un-privilege each page - - (#) Get the block-based secure / privilege area configuration function: Use HAL_FLASHEx_GetBBSec() - (++) Return the configuration of the block-based security and privilege for all the pages - - (#) Activation of the secure hide area function: Use HAL_FLASHEx_EnableSecHideProtection() - (++) Deny the access to the secure hide area - - (#) Privilege mode configuration function: Use HAL_FLASHEx_ConfigPrivMode() - (++) FLASH register can be protected against non-privilege accesses - - (#) Get the privilege mode configuration function: Use HAL_FLASHEx_GetPrivMode() - (++) Return if the FLASH registers are protected against non-privilege accesses - - (#) Security inversion configuration function: Use HAL_FLASHEx_ConfigSecInversion() - (++) FLASH secure state can be override - - (#) Get the security inversion configuration function: Use HAL_FLASHEx_GetSecInversion() - (++) Return if FLASH secure state is override - - (#) Enable bank low-power mode function: Use HAL_FLASHEx_EnablePowerDown() - (++) Enable low-power mode for Flash Bank 1 and/or Bank 2 - - (#) Enable low-power read mode function: Use HAL_FLASHEx_ConfigLowPowerRead() - (++) Enable low-power read mode for Flash memory - - (#) Get the low-power read mode configuration function: Use HAL_FLASHEx_GetLowPowerRead() - (++) Return if FLASH is in low-power read mode or normal read mode - - (#) Get Flash operation function: Use HAL_FLASHEx_GetOperation() - (++) Return information about the on-going Flash operation. After a - system reset, return information about the interrupted Flash operation, if any. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup FLASHEx FLASHEx - * @brief FLASH Extended HAL module driver - * @{ - */ - -#ifdef HAL_FLASH_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup FLASHEx_Private_Functions FLASHEx Private Functions - * @{ - */ -static void FLASH_MassErase(uint32_t Banks); -static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset, - FunctionalState WRPLock); -static void FLASH_OB_RDPConfig(uint32_t RDPLevel); -static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, - uint32_t WMHDPEndPage); -static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig); -#endif /* __ARM_FEATURE_CMSE */ -static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr); -static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset, - FunctionalState *WRPLock); -static uint32_t FLASH_OB_GetRDP(void); -static uint32_t FLASH_OB_GetUser(void); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage, - uint32_t *WMHDPEndPage); -static uint32_t FLASH_OB_GetBootLock(void); -#endif /* __ARM_FEATURE_CMSE */ -static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr); -static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2); -/** - * @} - */ - -/* Exported functions -------------------------------------------------------*/ -/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported Functions - * @{ - */ - -/** @defgroup FLASHEx_Exported_Functions_Group1 Extended IO operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### Extended programming operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the Extended FLASH - programming operations Operations. - -@endverbatim - * @{ - */ -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages. - * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @param[out] PageError pointer to variable that contains the configuration - * information on faulty page in case of error (0xFFFFFFFF means that all - * the pages have been correctly erased). - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError) -{ - HAL_StatusTypeDef status; - uint32_t page_index; - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Reset error code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Current operation type */ - pFlash.ProcedureOnGoing = pEraseInit->TypeErase; - - /* Access to SECCR or NSCR depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR); - - if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - FLASH_MassErase(pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - else - { - /*Initialization of PageError variable*/ - *PageError = 0xFFFFFFFFU; - - for (page_index = pEraseInit->Page; page_index < (pEraseInit->Page + pEraseInit->NbPages); page_index++) - { - FLASH_PageErase(page_index, pEraseInit->Banks); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status != HAL_OK) - { - /* In case of error, stop erase procedure and return the faulty page */ - *PageError = page_index; - break; - } - } - } - - /* If the erase operation is completed, disable the associated bits */ - CLEAR_BIT((*reg_cr), (pEraseInit->TypeErase) & (~(FLASH_NON_SECURE_MASK))); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Perform a mass erase or erase the specified FLASH memory pages with interrupt enabled. - * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that - * contains the configuration information for the erasing. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit) -{ - HAL_StatusTypeDef status; - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_TYPEERASE(pEraseInit->TypeErase)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Reset error code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - } - else - { - /* Set internal variables used by the IRQ handler */ - pFlash.ProcedureOnGoing = pEraseInit->TypeErase; - pFlash.Bank = pEraseInit->Banks; - - /* Access to SECCR or NSCR depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH->NSCR); - - /* Enable End of Operation and Error interrupts */ - (*reg_cr) |= (FLASH_IT_EOP | FLASH_IT_OPERR); - - if ((pEraseInit->TypeErase & (~FLASH_NON_SECURE_MASK)) == FLASH_TYPEERASE_MASSERASE) - { - /* Mass erase to be done */ - FLASH_MassErase(pEraseInit->Banks); - } - else - { - /* Erase by page to be done */ - pFlash.NbPagesToErase = pEraseInit->NbPages; - pFlash.Page = pEraseInit->Page; - - /* Erase first page and wait for IT */ - FLASH_PageErase(pEraseInit->Page, pEraseInit->Banks); - } - } - - return status; -} - -/** - * @brief Program Option bytes. - * @param pOBInit pointer to an FLASH_OBInitStruct structure that - * contains the configuration information for the programming. - * - * @note To configure any option bytes, the option lock bit OPTLOCK must be - * cleared with the call of HAL_FLASH_OB_Unlock() function. - * @note New option bytes configuration will be taken into account in two cases: - * - after an option bytes launch through the call of HAL_FLASH_OB_Launch() - * - after a power reset (BOR reset or exit from Standby/Shutdown modes) - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) -{ - HAL_StatusTypeDef status; - - /* Check the parameters */ - assert_param(IS_OPTIONBYTE(pOBInit->OptionType)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Reset error code */ - pFlash.ErrorCode = HAL_FLASH_ERROR_NONE; - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Write protection configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_WRP) != 0U) - { - /* Configure of Write protection on the selected area */ - FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset, pOBInit->WRPLock); - } - - /* Read protection configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U) - { - /* Configure the Read protection level */ - FLASH_OB_RDPConfig(pOBInit->RDPLevel); - } - - /* Read protection key configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_RDPKEY) != 0U) - { - /* Configure the Read protection key */ - FLASH_OB_RDPKeyConfig(pOBInit->RDPKeyType, pOBInit->RDPKey1, pOBInit->RDPKey2); - } - - /* User Configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U) - { - /* Configure the user option bytes */ - FLASH_OB_UserConfig(pOBInit->USERType, pOBInit->USERConfig); - } - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Watermark secure configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_WMSEC) != 0U) - { - /* Configure the watermark-based secure area */ - FLASH_OB_WMSECConfig(pOBInit->WMSecConfig, pOBInit->WMSecStartPage, pOBInit->WMSecEndPage, - pOBInit->WMHDPEndPage); - } - - /* Unique boot entry point configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_BOOT_LOCK) != 0U) - { - /* Configure the unique boot entry point */ - FLASH_OB_BootLockConfig(pOBInit->BootLock); - } -#endif /* __ARM_FEATURE_CMSE */ - - /* Boot address configuration */ - if ((pOBInit->OptionType & OPTIONBYTE_BOOTADDR) != 0U) - { - /* Configure the boot address */ - FLASH_OB_BootAddrConfig(pOBInit->BootAddrConfig, pOBInit->BootAddr); - } - - /* Set OPTSTRT Bit */ - SET_BIT(FLASH->NSCR, FLASH_NSCR_OPTSTRT); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Get the Option bytes configuration. - * @param pOBInit pointer to an FLASH_OBInitStruct structure that contains the - * configuration information. - * @note The fields pOBInit->WRPArea, pOBInit->WMSecConfig and pOBInit->BootAddrConfig - * should indicate which area/address is requested for the WRP, WM Security or - * Boot Address, else no information will be returned - * - * @retval None - */ -void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit) -{ - pOBInit->OptionType = (OPTIONBYTE_RDP | OPTIONBYTE_USER); - - if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB) || - (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK2_AREAB)) - { - pOBInit->OptionType |= OPTIONBYTE_WRP; - /* Get write protection on the selected area */ - FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset), &(pOBInit->WRPLock)); - } - - /* Get Read protection level */ - pOBInit->RDPLevel = FLASH_OB_GetRDP(); - - /* Get the user option bytes */ - pOBInit->USERConfig = FLASH_OB_GetUser(); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Get the configuration of the watermark secure area for the selected area */ - if ((pOBInit->WMSecConfig == OB_WMSEC_AREA1) || (pOBInit->WMSecConfig == OB_WMSEC_AREA2)) - { - pOBInit->OptionType |= OPTIONBYTE_WMSEC; - FLASH_OB_GetWMSEC(&(pOBInit->WMSecConfig), &(pOBInit->WMSecStartPage), &(pOBInit->WMSecEndPage), - &(pOBInit->WMHDPEndPage)); - } - - pOBInit->OptionType |= OPTIONBYTE_BOOT_LOCK; - - /* Get the configuration of the unique boot entry point */ - pOBInit->BootLock = FLASH_OB_GetBootLock(); -#endif /* __ARM_FEATURE_CMSE */ - - /* Get the value of the selected boot address */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1) || - (pOBInit->BootAddrConfig == OB_BOOTADDR_SEC0)) -#else - if ((pOBInit->BootAddrConfig == OB_BOOTADDR_NS0) || (pOBInit->BootAddrConfig == OB_BOOTADDR_NS1)) -#endif /* __ARM_FEATURE_CMSE */ - { - pOBInit->OptionType |= OPTIONBYTE_BOOTADDR; - FLASH_OB_GetBootAddr(pOBInit->BootAddrConfig, &(pOBInit->BootAddr)); - } -} - -/** - * @brief Configure the block-based secure area. - * - * @param pBBAttributes pointer to an FLASH_BBAttributesTypeDef structure that - * contains the configuration information for the programming. - * - * @note The field pBBAttributes->Bank should indicate which area is requested - * for the block-based attributes. - * @note The field pBBAttributes->BBAttributesType should indicate which - * block-base attribute type is requested: Secure or Privilege. - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) -{ - HAL_StatusTypeDef status; - uint8_t index; - __IO uint32_t *reg; - - /* Check the parameters */ - assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); - assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - /* Set the first Block-Based register to write */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) - { - if (pBBAttributes->Bank == FLASH_BANK_1) - { - reg = &(FLASH->SECBB1R1); - } - else - { - reg = &(FLASH->SECBB2R1); - } - } - else -#endif /* __ARM_FEATURE_CMSE */ - { - if (pBBAttributes->Bank == FLASH_BANK_1) - { - reg = &(FLASH->PRIVBB1R1); - } - else - { - reg = &(FLASH->PRIVBB2R1); - } - } - - /* Modify the register values and check that new attributes are taken in account */ - for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) - { - *reg = pBBAttributes->BBAttributes_array[index]; - if ((*reg) != pBBAttributes->BBAttributes_array[index]) - { - status = HAL_ERROR; - } - reg++; - } - - /* ISB instruction is called to be sure next instructions are performed with correct attributes */ - __ISB(); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Return the block-based attributes. - * - * @param pBBAttributes [in/out] pointer to an FLASH_BBAttributesTypeDef structure - * that contains the configuration information. - * @note The field pBBAttributes->Bank should indicate which area is requested - * for the block-based attributes. - * @note The field pBBAttributes->BBAttributesType should indicate which - * block-base attribute type is requested: Secure or Privilege. - * - * @retval None - */ -void HAL_FLASHEx_GetConfigBBAttributes(FLASH_BBAttributesTypeDef *pBBAttributes) -{ - uint8_t index; - __IO uint32_t *reg; - - /* Check the parameters */ - assert_param(IS_FLASH_BANK_EXCLUSIVE(pBBAttributes->Bank)); - assert_param(IS_FLASH_BB_EXCLUSIVE(pBBAttributes->BBAttributesType)); - - /* Set the first Block-Based register to read */ - if (pBBAttributes->BBAttributesType == FLASH_BB_SEC) - { - if (pBBAttributes->Bank == FLASH_BANK_1) - { - reg = &(FLASH->SECBB1R1); - } - else - { - reg = &(FLASH->SECBB2R1); - } - } - else - { - if (pBBAttributes->Bank == FLASH_BANK_1) - { - reg = &(FLASH->PRIVBB1R1); - } - else - { - reg = &(FLASH->PRIVBB2R1); - } - } - - /* Read the register values */ - for (index = 0; index < FLASH_BLOCKBASED_NB_REG; index++) - { - pBBAttributes->BBAttributes_array[index] = (*reg); - reg++; - } -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Activation of the protection of the secure hide area. - * - * @param Banks indicate the bank concerned by the activation - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be protected - * @arg FLASH_BANK_2: Bank2 to be protected - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be protected - * - * @retval None - */ -void HAL_FLASHEx_EnableSecHideProtection(uint32_t Banks) -{ - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - if ((Banks & FLASH_BANK_1) != 0U) - { - SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP1_ACCDIS); - } - - if ((Banks & FLASH_BANK_2) != 0U) - { - SET_BIT(FLASH->SECHDPCR, FLASH_SECHDPCR_HDP2_ACCDIS); - } -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @} - */ - -/** @addtogroup FLASHEx_Exported_Functions_Group2 FLASHEx Exported Functions Group2 - * @{ - */ - -/** - * @brief Configuration of the privilege attribute. - * - * @param PrivMode indicate privilege mode configuration - * This parameter can be one of the following values: - * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged - * or unprivileged access - * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied - * to unprivileged access - * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged - * or unprivileged access - * @arg FLASH_NSPRIV_DENIED: access to non-secure Flash registers is denied - * to unprivilege access - * - * @retval None - */ -void HAL_FLASHEx_ConfigPrivMode(uint32_t PrivMode) -{ - /* Check the parameters */ - assert_param(IS_FLASH_CFGPRIVMODE(PrivMode)); - - MODIFY_REG(FLASH->PRIVCFGR, (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV), PrivMode); -} - -/** - * @brief Return the value of the privilege attribute. - * - * @retval It indicates the privilege mode configuration. - * This return value can be one of the following values: - * @arg FLASH_SPRIV_GRANTED: access to secure Flash registers is granted to privileged - * or unprivileged access - * @arg FLASH_SPRIV_DENIED: access to secure Flash registers is denied - * to unprivileged access - * @arg FLASH_NSPRIV_GRANTED: access to non-secure Flash registers is granted to privileged - * or unprivileged access - * @arg FLASH_NSPRIV_DENIED: access to Flash registers is denied - * to unprivilege accessP - */ -uint32_t HAL_FLASHEx_GetPrivMode(void) -{ - return (FLASH->PRIVCFGR & (FLASH_PRIVCFGR_SPRIV | FLASH_PRIVCFGR_NSPRIV)); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configuration of the security inversion. - * - * @param SecInvState indicate the flash security state configuration - * This parameter can be one of the following values: - * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted - * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigSecInversion(uint32_t SecInvState) -{ - HAL_StatusTypeDef status; - - /* Check the parameters */ - assert_param(IS_FLASH_CFGSECINV(SecInvState)); - - /* Process Locked */ - __HAL_LOCK(&pFlash); - - /* Wait for last operation to be completed */ - status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); - - if (status == HAL_OK) - { - MODIFY_REG(FLASH->SECCR, FLASH_SECCR_INV, SecInvState); - } - - /* Process Unlocked */ - __HAL_UNLOCK(&pFlash); - - return status; -} - -/** - * @brief Return the value of the security inversion. - * - * @retval It indicates the flash security state configuration - * This return value can be one of the following values: - * @arg FLASH_SEC_INV_DISABLE: Security state of Flash is not inverted - * @arg FLASH_SEC_INV_ENABLE: Security state of Flash is inverted - */ -uint32_t HAL_FLASHEx_GetSecInversion(void) -{ - return (FLASH->SECCR & FLASH_SECCR_INV); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Enable the Power-down Mode for Flash Banks - * @param Banks indicate which bank to put in power-down mode - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Flash Bank 1 - * @arg FLASH_BANK_2: Flash Bank 2 - * @arg FLASH_BANK_BOTH: Flash Bank 1 and Bank 2 - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_EnablePowerDown(uint32_t Banks) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - /* Request power-down mode for Bank 1 */ - if ((Banks & FLASH_BANK_1) != 0U) - { - /* Check PD1 and PDREQ1 bits (Bank 1 is not in power-down mode and not being - already under power-down request) */ - if ((FLASH->NSSR & FLASH_NSSR_PD1) != 0U) - { - status = HAL_ERROR; - } - else if ((FLASH->ACR & FLASH_ACR_PDREQ1) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Unlock PDREQ1 bit */ - WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_1); - WRITE_REG(FLASH->PDKEY1R, FLASH_PDKEY1_2); - - /* Set PDREQ1 in FLASH_ACR register */ - SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ1); - - /* Check PD1 bit */ - tickstart = HAL_GetTick(); - while (((FLASH->NSSR & FLASH_NSSR_PD1) != FLASH_NSSR_PD1)) - { - if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /* Request power-down mode for Bank 2 */ - if ((Banks & FLASH_BANK_2) != 0U) - { - /* Check PD2 and PDREQ2 bits (Bank 2 is not in power-down mode and not being - already under power-down request) */ - if ((FLASH->NSSR & FLASH_NSSR_PD2) != 0U) - { - status = HAL_ERROR; - } - else if ((FLASH->ACR & FLASH_ACR_PDREQ2) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Unlock PDREQ2 bit */ - WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_1); - WRITE_REG(FLASH->PDKEY2R, FLASH_PDKEY2_2); - - /* Set PDREQ2 in FLASH_ACR register */ - SET_BIT(FLASH->ACR, FLASH_ACR_PDREQ2); - - /* Check PD2 bit */ - tickstart = HAL_GetTick(); - while (((FLASH->NSSR & FLASH_NSSR_PD2) != FLASH_NSSR_PD2)) - { - if ((HAL_GetTick() - tickstart) > FLASH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - return status; -} - -/** - * @brief Configuration of the Low-Power read Mode. - * - * @param ConfigLPM indicate the Low-Power read Mode configuration. - * This parameter can be one of the following values: - * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode - * @arg FLASH_LPM_DISABLE: Flash is in normal read mode - * - * @retval HAL Status - */ -HAL_StatusTypeDef HAL_FLASHEx_ConfigLowPowerRead(uint32_t ConfigLPM) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_FLASH_CFGLPM(ConfigLPM)); - - /* Set LPM Bit in FLASH_ACR register */ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LPM, ConfigLPM); - - /* Check that low power read mode has been activated */ - if (READ_BIT(FLASH->ACR, FLASH_ACR_LPM) != ConfigLPM) - { - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Return the value of the Low-Power read Mode. - * - * @retval It indicates the flash low-power read mode configuration - * This return value can be one of the following values: - * @arg FLASH_LPM_ENABLE: Flash is in low-power read mode - * @arg FLASH_LPM_DISABLE: Flash is in normal read mode - */ -uint32_t HAL_FLASHEx_GetLowPowerRead(void) -{ - return (FLASH->ACR & FLASH_ACR_LPM); -} - -/** - * @brief Return the on-going Flash Operation. After a system reset, return - * the interrupted Flash operation, if any. - * @param pFlashOperation [out] pointer to a FLASH_OperationTypeDef structure - * that contains the Flash operation information. - * - * @retval None - */ -void HAL_FLASHEx_GetOperation(FLASH_OperationTypeDef *pFlashOperation) -{ - uint32_t opsr_reg = FLASH->OPSR; - - /* Get Flash operation Type */ - pFlashOperation->OperationType = opsr_reg & FLASH_OPSR_CODE_OP; - - /* Get Flash operation memory */ - pFlashOperation->FlashArea = opsr_reg & (FLASH_OPSR_SYSF_OP | FLASH_OPSR_BK_OP); - - /* Get Flash operation address */ - pFlashOperation->Address = opsr_reg & FLASH_OPSR_ADDR_OP; -} - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ - -/** @addtogroup FLASHEx_Private_Functions - * @{ - */ -/** - * @brief Mass erase of FLASH memory. - * @param Banks Banks to be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Bank1 to be erased - * @arg FLASH_BANK_2: Bank2 to be erased - * @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased - * @retval None - */ -static void FLASH_MassErase(uint32_t Banks) -{ - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_BANK(Banks)); - - /* Access to SECCR or NSCR registers depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - - /* Set the Mass Erase Bit for the bank 1 and proceed to erase */ - if ((Banks & FLASH_BANK_1) != 0U) - { - SET_BIT((*reg_cr), FLASH_NSCR_MER1 | FLASH_NSCR_STRT); - } - - /* Set the Mass Erase Bit for the bank 2 and proceed to erase */ - if ((Banks & FLASH_BANK_2) != 0U) - { - SET_BIT((*reg_cr), FLASH_NSCR_MER2 | FLASH_NSCR_STRT); - } -} - -/** - * @brief Erase the specified FLASH memory page. - * @param Page FLASH page to erase - * This parameter must be a value between 0 and (max number of pages in the bank - 1) - * @param Banks Bank(s) where the page will be erased - * This parameter can be one of the following values: - * @arg FLASH_BANK_1: Page in bank 1 to be erased - * @arg FLASH_BANK_2: Page in bank 2 to be erased - * @retval None - */ -void FLASH_PageErase(uint32_t Page, uint32_t Banks) -{ - __IO uint32_t *reg_cr; - - /* Check the parameters */ - assert_param(IS_FLASH_PAGE(Page)); - assert_param(IS_FLASH_BANK_EXCLUSIVE(Banks)); - - /* Access to SECCR or NSCR registers depends on operation type */ - reg_cr = IS_FLASH_SECURE_OPERATION() ? &(FLASH->SECCR) : &(FLASH_NS->NSCR); - - if ((Banks & FLASH_BANK_1) != 0U) - { - CLEAR_BIT((*reg_cr), FLASH_NSCR_BKER); - } - else - { - SET_BIT((*reg_cr), FLASH_NSCR_BKER); - } - - /* Proceed to erase the page */ - MODIFY_REG((*reg_cr), (FLASH_NSCR_PNB | FLASH_NSCR_PER | FLASH_NSCR_STRT), \ - ((Page << FLASH_NSCR_PNB_Pos) | FLASH_NSCR_PER | FLASH_NSCR_STRT)); -} - -/** - * @brief Configure the write protection of the desired pages. - * - * @note When the memory read protection level is selected (RDP level = 1), - * it is not possible to program or erase Flash memory if the CPU debug - * features are connected (JTAG or single wire) or boot code is being - * executed from RAM or System flash, even if WRP is not activated. - * @note To configure the WRP options, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the WRP options, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * - * @param WRPArea specifies the area to be configured. - * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B - * - * @param WRPStartOffset specifies the start page of the write protected area - * This parameter can be page number between 0 and (max number of pages in the bank - 1) - * - * @param WRPEndOffset specifies the end page of the write protected area - * This parameter can be page number between WRPStartOffset and (max number of pages in the bank - 1) - * - * @param WRPLock enables the lock of the write protected area - * This parameter can be set to ENABLE or DISABLE - * - * @retval None - */ -static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRPEndOffset, - FunctionalState WRPLock) -{ - /* Check the parameters */ - assert_param(IS_OB_WRPAREA(WRPArea)); - assert_param(IS_FLASH_PAGE(WRPStartOffset)); - assert_param(IS_FLASH_PAGE(WRPEndOffset)); - assert_param(IS_FUNCTIONAL_STATE(WRPLock)); - - /* Configure the write protected area */ - if (WRPArea == OB_WRPAREA_BANK1_AREAA) - { - FLASH->WRP1AR = (((uint32_t)(~WRPLock) << FLASH_WRP1AR_UNLOCK_Pos) | \ - (WRPEndOffset << FLASH_WRP1AR_WRP1A_PEND_Pos) | \ - WRPStartOffset); - } - else if (WRPArea == OB_WRPAREA_BANK1_AREAB) - { - FLASH->WRP1BR = (((uint32_t)(~WRPLock) << FLASH_WRP1BR_UNLOCK_Pos) | \ - (WRPEndOffset << FLASH_WRP1BR_WRP1B_PEND_Pos) | \ - WRPStartOffset); - } - else if (WRPArea == OB_WRPAREA_BANK2_AREAA) - { - FLASH->WRP2AR = (((uint32_t)(~WRPLock) << FLASH_WRP2AR_UNLOCK_Pos) | \ - (WRPEndOffset << FLASH_WRP2AR_WRP2A_PEND_Pos) | \ - WRPStartOffset); - } - else if (WRPArea == OB_WRPAREA_BANK2_AREAB) - { - FLASH->WRP2BR = (((uint32_t)(~WRPLock) << FLASH_WRP2BR_UNLOCK_Pos) | \ - (WRPEndOffset << FLASH_WRP2BR_WRP2B_PEND_Pos) | \ - WRPStartOffset); - } - else - { - /* Empty statement (to be compliant MISRA 15.7) */ - } -} - -/** - * @brief Set the read protection level. - * - * @note To configure the RDP level, the option lock bit OPTLOCK must be - * cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the RDP level, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible - * to go back to other levels !!! - * - * @param RDPLevel specifies the read protection level. - * This parameter can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_0_5: No debug access to secure area - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - * - * @retval None - */ -static void FLASH_OB_RDPConfig(uint32_t RDPLevel) -{ - /* Check the parameters */ - assert_param(IS_OB_RDP_LEVEL(RDPLevel)); - - /* Configure the RDP level in the option bytes register */ - MODIFY_REG(FLASH->OPTR, FLASH_OPTR_RDP, RDPLevel); -} - -/** - * @brief Set the read protection key. - * @param RDPKeyType specifies the read protection key type. - * This parameter can be one of the following values: - * @arg OB_RDP_KEY_OEM1: OEM1 key - * @arg OB_RDP_KEY_OEM2: OEM2 key - * @param RDPKey1 specifies the RDP key 1. - * @param RDPKey2 specifies the RDP key 2. - * @retval None - */ -static void FLASH_OB_RDPKeyConfig(uint32_t RDPKeyType, uint32_t RDPKey1, uint32_t RDPKey2) -{ - /* Check the parameters */ - assert_param(IS_OB_RDP_KEY_TYPE(RDPKeyType)); - - /* Configure the RDP OEM key */ - if (RDPKeyType == OB_RDP_KEY_OEM1) - { - WRITE_REG(FLASH->OEM1KEYR1, RDPKey1); - WRITE_REG(FLASH->OEM1KEYR2, RDPKey2); - } - else - { - WRITE_REG(FLASH->OEM2KEYR1, RDPKey1); - WRITE_REG(FLASH->OEM2KEYR2, RDPKey2); - } -} - -/** - * @brief Program the FLASH User Option Byte. - * - * @note To configure the user option bytes, the option lock bit OPTLOCK must - * be cleared with the call of the HAL_FLASH_OB_Unlock() function. - * @note To validate the user option bytes, the option bytes must be reloaded - * through the call of the HAL_FLASH_OB_Launch() function. - * @param UserType: The FLASH User Option Bytes to be modified. - * This parameter can be a combination of @ref FLASH_OB_USER_Type - * @param UserConfig The selected User Option Bytes values. - * This parameter can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, - * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, - * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, - * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, - * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, - * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, - * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, - * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, - * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, - * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN - * @retval None - */ -static void FLASH_OB_UserConfig(uint32_t UserType, uint32_t UserConfig) -{ - uint32_t optr_reg_val = 0; - uint32_t optr_reg_mask = 0; - - /* Check the parameters */ - assert_param(IS_OB_USER_TYPE(UserType)); - - if ((UserType & OB_USER_BOR_LEV) != 0U) - { - /* BOR level option byte should be modified */ - assert_param(IS_OB_USER_BOR_LEVEL(UserConfig & FLASH_OPTR_BOR_LEV)); - - /* Set value and mask for BOR level option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_BOR_LEV); - optr_reg_mask |= FLASH_OPTR_BOR_LEV; - } - - if ((UserType & OB_USER_NRST_STOP) != 0U) - { - /* nRST_STOP option byte should be modified */ - assert_param(IS_OB_USER_STOP(UserConfig & FLASH_OPTR_nRST_STOP)); - - /* Set value and mask for nRST_STOP option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STOP); - optr_reg_mask |= FLASH_OPTR_nRST_STOP; - } - - if ((UserType & OB_USER_NRST_STDBY) != 0U) - { - /* nRST_STDBY option byte should be modified */ - assert_param(IS_OB_USER_STANDBY(UserConfig & FLASH_OPTR_nRST_STDBY)); - - /* Set value and mask for nRST_STDBY option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_STDBY); - optr_reg_mask |= FLASH_OPTR_nRST_STDBY; - } - - if ((UserType & OB_USER_NRST_SHDW) != 0U) - { - /* nRST_SHDW option byte should be modified */ - assert_param(IS_OB_USER_SHUTDOWN(UserConfig & FLASH_OPTR_nRST_SHDW)); - - /* Set value and mask for nRST_SHDW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nRST_SHDW); - optr_reg_mask |= FLASH_OPTR_nRST_SHDW; - } - - if ((UserType & OB_USER_SRAM_RST) != 0U) - { - /* SRAM_RST option byte should be modified */ - assert_param(IS_OB_USER_SRAM_RST(UserConfig & FLASH_OPTR_SRAM_RST)); - - /* Set value and mask for SRAM_RST option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM_RST); - optr_reg_mask |= FLASH_OPTR_SRAM_RST; - } - - if ((UserType & OB_USER_IWDG_SW) != 0U) - { - /* IWDG_SW option byte should be modified */ - assert_param(IS_OB_USER_IWDG(UserConfig & FLASH_OPTR_IWDG_SW)); - - /* Set value and mask for IWDG_SW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_SW); - optr_reg_mask |= FLASH_OPTR_IWDG_SW; - } - - if ((UserType & OB_USER_IWDG_STOP) != 0U) - { - /* IWDG_STOP option byte should be modified */ - assert_param(IS_OB_USER_IWDG_STOP(UserConfig & FLASH_OPTR_IWDG_STOP)); - - /* Set value and mask for IWDG_STOP option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STOP); - optr_reg_mask |= FLASH_OPTR_IWDG_STOP; - } - - if ((UserType & OB_USER_IWDG_STDBY) != 0U) - { - /* IWDG_STDBY option byte should be modified */ - assert_param(IS_OB_USER_IWDG_STDBY(UserConfig & FLASH_OPTR_IWDG_STDBY)); - - /* Set value and mask for IWDG_STDBY option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IWDG_STDBY); - optr_reg_mask |= FLASH_OPTR_IWDG_STDBY; - } - - if ((UserType & OB_USER_WWDG_SW) != 0U) - { - /* WWDG_SW option byte should be modified */ - assert_param(IS_OB_USER_WWDG(UserConfig & FLASH_OPTR_WWDG_SW)); - - /* Set value and mask for WWDG_SW option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_WWDG_SW); - optr_reg_mask |= FLASH_OPTR_WWDG_SW; - } - - if ((UserType & OB_USER_SWAP_BANK) != 0U) - { - /* SWAP_BANK option byte should be modified */ - assert_param(IS_OB_USER_SWAP_BANK(UserConfig & FLASH_OPTR_SWAP_BANK)); - - /* Set value and mask for SWAP_BANK option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SWAP_BANK); - optr_reg_mask |= FLASH_OPTR_SWAP_BANK; - } - - if ((UserType & OB_USER_DUALBANK) != 0U) - { - /* DUALBANK option byte should be modified */ - assert_param(IS_OB_USER_DUALBANK(UserConfig & FLASH_OPTR_DUALBANK)); - - /* Set value and mask for DUALBANK option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_DUALBANK); - optr_reg_mask |= FLASH_OPTR_DUALBANK; - } - - if ((UserType & OB_USER_BKPRAM_ECC) != 0U) - { - /* BKPRAM_ECC option byte should be modified */ - assert_param(IS_OB_USER_BKPRAM_ECC(UserConfig & FLASH_OPTR_BKPRAM_ECC)); - - /* Set value and mask for BKPRAM_ECC option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_BKPRAM_ECC); - optr_reg_mask |= FLASH_OPTR_BKPRAM_ECC; - } -#if defined(SRAM3_BASE) - if ((UserType & OB_USER_SRAM3_ECC) != 0U) - { - /* SRAM3_ECC option byte should be modified */ - assert_param(IS_OB_USER_SRAM3_ECC(UserConfig & FLASH_OPTR_SRAM3_ECC)); - - /* Set value and mask for SRAM3_ECC option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM3_ECC); - optr_reg_mask |= FLASH_OPTR_SRAM3_ECC; - } -#endif /* SRAM3_BASE */ - if ((UserType & OB_USER_SRAM2_ECC) != 0U) - { - /* SRAM2_ECC option byte should be modified */ - assert_param(IS_OB_USER_SRAM2_ECC(UserConfig & FLASH_OPTR_SRAM2_ECC)); - - /* Set value and mask for SRAM2_ECC option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_ECC); - optr_reg_mask |= FLASH_OPTR_SRAM2_ECC; - } - - if ((UserType & OB_USER_SRAM2_RST) != 0U) - { - /* SRAM2_RST option byte should be modified */ - assert_param(IS_OB_USER_SRAM2_RST(UserConfig & FLASH_OPTR_SRAM2_RST)); - - /* Set value and mask for SRAM2_RST option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_SRAM2_RST); - optr_reg_mask |= FLASH_OPTR_SRAM2_RST; - } - - if ((UserType & OB_USER_NSWBOOT0) != 0U) - { - /* nSWBOOT0 option byte should be modified */ - assert_param(IS_OB_USER_SWBOOT0(UserConfig & FLASH_OPTR_nSWBOOT0)); - - /* Set value and mask for nSWBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nSWBOOT0); - optr_reg_mask |= FLASH_OPTR_nSWBOOT0; - } - - if ((UserType & OB_USER_NBOOT0) != 0U) - { - /* nBOOT0 option byte should be modified */ - assert_param(IS_OB_USER_BOOT0(UserConfig & FLASH_OPTR_nBOOT0)); - - /* Set value and mask for nBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_nBOOT0); - optr_reg_mask |= FLASH_OPTR_nBOOT0; - } - - if ((UserType & OB_USER_PA15_PUPEN) != 0U) - { - /* PA15_PUPEN option byte should be modified */ - assert_param(IS_OB_USER_PA15_PUPEN(UserConfig & FLASH_OPTR_PA15_PUPEN)); - - /* Set value and mask for nBOOT0 option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_PA15_PUPEN); - optr_reg_mask |= FLASH_OPTR_PA15_PUPEN; - } - - if ((UserType & OB_USER_IO_VDD_HSLV) != 0U) - { - /* IO_VDD_HSLV option byte should be modified */ - assert_param(IS_OB_USER_IO_VDD_HSLV(UserConfig & FLASH_OPTR_IO_VDD_HSLV)); - - /* Set value and mask for IO_VDD_HSLV option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDD_HSLV); - optr_reg_mask |= FLASH_OPTR_IO_VDD_HSLV; - } - - if ((UserType & OB_USER_IO_VDDIO2_HSLV) != 0U) - { - /* IO_VDDIO2_HSLV option byte should be modified */ - assert_param(IS_OB_USER_IO_VDDIO2_HSLV(UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV)); - - /* Set value and mask for IO_VDDIO2_HSLV option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_IO_VDDIO2_HSLV); - optr_reg_mask |= FLASH_OPTR_IO_VDDIO2_HSLV; - } - - if ((UserType & OB_USER_TZEN) != 0U) - { - /* TZEN option byte should be modified */ - assert_param(IS_OB_USER_TZEN(UserConfig & FLASH_OPTR_TZEN)); - - /* Set value and mask for TZEN option byte */ - optr_reg_val |= (UserConfig & FLASH_OPTR_TZEN); - optr_reg_mask |= FLASH_OPTR_TZEN; - } - - /* Configure the option bytes register */ - MODIFY_REG(FLASH->OPTR, optr_reg_mask, optr_reg_val); -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Configure the watermarked-based secure area. - * - * @param WMSecConfig specifies the area to be configured. - * This parameter can be a combination of the following values: - * @arg OB_WMSEC_AREA1 or @arg OB_WMSEC_AREA2: Select Flash Secure Area 1 or Area 2 - * @arg OB_WMSEC_SECURE_AREA_CONFIG: configure Flash Secure Area - * @arg OB_WMSEC_HDP_AREA_CONFIG: configure Flash secure hide Area - * @arg OB_WMSEC_HDP_AREA_ENABLE: enable secure hide Area in Secure Area - * @arg OB_WMSEC_HDP_AREA_DISABLE: disable secure hide Area in Secure Area - * - * @param WMSecStartPage specifies the start page of the secure area - * This parameter can be page number between 0 and (max number of pages in the bank - 1) - * - * @param WMSecEndPage specifies the end page of the secure area - * This parameter can be page number between WMSecStartPage and (max number of pages in the bank - 1) - * - * @param WMHDPEndPage specifies the end page of the secure hide area - * This parameter can be a page number between WMSecStartPage and WMSecEndPage - * - * @retval None - */ -static void FLASH_OB_WMSECConfig(uint32_t WMSecConfig, uint32_t WMSecStartPage, uint32_t WMSecEndPage, - uint32_t WMHDPEndPage) -{ - uint32_t tmp_secwm1 = 0U; - uint32_t tmp_secwm2 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_WMSEC_CONFIG(WMSecConfig)); - assert_param(IS_OB_WMSEC_AREA_EXCLUSIVE(WMSecConfig & 0x3U)); - assert_param(IS_FLASH_PAGE(WMSecStartPage)); - assert_param(IS_FLASH_PAGE(WMSecEndPage)); - assert_param(IS_FLASH_PAGE(WMHDPEndPage)); - - /* Read SECWM registers */ - if ((WMSecConfig & OB_WMSEC_AREA1) != 0U) - { - tmp_secwm1 = FLASH->SECWM1R1; - tmp_secwm2 = FLASH->SECWM1R2; - } - else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U) - { - tmp_secwm1 = FLASH->SECWM2R1; - tmp_secwm2 = FLASH->SECWM2R2; - } - else - { - /* Nothing to do */ - } - - /* Configure Secure Area */ - if ((WMSecConfig & OB_WMSEC_SECURE_AREA_CONFIG) != 0U) - { - tmp_secwm1 = ((WMSecEndPage << FLASH_SECWM1R1_SECWM1_PEND_Pos) | WMSecStartPage); - } - - /* Configure Secure Hide Area */ - if ((WMSecConfig & OB_WMSEC_HDP_AREA_CONFIG) != 0U) - { - tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1_PEND); - tmp_secwm2 |= (WMHDPEndPage << FLASH_SECWM1R2_HDP1_PEND_Pos); - } - - /* Enable Secure Hide Area */ - if ((WMSecConfig & OB_WMSEC_HDP_AREA_ENABLE) != 0U) - { - tmp_secwm2 |= FLASH_SECWM1R2_HDP1EN; - } - - /* Disable Secure Hide Area */ - if ((WMSecConfig & OB_WMSEC_HDP_AREA_DISABLE) != 0U) - { - tmp_secwm2 &= (~FLASH_SECWM1R2_HDP1EN); - } - - /* Write SECWM registers */ - if ((WMSecConfig & OB_WMSEC_AREA1) != 0U) - { - FLASH->SECWM1R1 = tmp_secwm1; - FLASH->SECWM1R2 = tmp_secwm2; - } - else if ((WMSecConfig & OB_WMSEC_AREA2) != 0U) - { - FLASH->SECWM2R1 = tmp_secwm1; - FLASH->SECWM2R2 = tmp_secwm2; - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief Configure the boot lock. - * - * @param BootLockConfig specifies the activation of the BOOT_LOCK. - * This parameter can be one of the following values: - * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated - * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated - * - * @retval None - */ -static void FLASH_OB_BootLockConfig(uint32_t BootLockConfig) -{ - /* Check the parameters */ - assert_param(IS_OB_BOOT_LOCK(BootLockConfig)); - - /* Configure the option bytes register */ - MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_BOOT_LOCK, BootLockConfig); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Configure the boot address. - * - * @param BootAddrConfig specifies the area to be configured. - * This parameter can be one of the following values: - * @arg OB_BOOTADDR_NS0: Non-secure boot address 0 - * @arg OB_BOOTADDR_NS1: Non-secure boot address 1 - * @arg OB_BOOTADDR_SEC0: Secure boot address 0 - * - * @param BootAddr: specifies the address used for the boot - * This parameter can be page number between 0 and 0xFFFFFF00 - * - * @retval None - */ -static void FLASH_OB_BootAddrConfig(uint32_t BootAddrConfig, uint32_t BootAddr) -{ - /* Check the parameters */ - assert_param(IS_OB_BOOTADDR_CONFIG(BootAddrConfig)); - - if (BootAddrConfig == OB_BOOTADDR_NS0) - { - FLASH->NSBOOTADD0R = BootAddr; - } - else if (BootAddrConfig == OB_BOOTADDR_NS1) - { - FLASH->NSBOOTADD1R = BootAddr; - } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - else if (BootAddrConfig == OB_BOOTADDR_SEC0) - { - MODIFY_REG(FLASH->SECBOOTADD0R, FLASH_SECBOOTADD0R_SECBOOTADD0, BootAddr); - } -#endif /* __ARM_FEATURE_CMSE */ - else - { - /* Empty statement (to be compliant MISRA 15.7) */ - } -} - -/** - * @brief Return the FLASH Write Protection Option Bytes value. - * - * @param[in] WRPArea specifies the area to be returned. - * This parameter can be one of the following values: - * @arg OB_WRPAREA_BANK1_AREAA: Flash Bank 1 Area A - * @arg OB_WRPAREA_BANK1_AREAB: Flash Bank 1 Area B - * @arg OB_WRPAREA_BANK2_AREAA: Flash Bank 2 Area A - * @arg OB_WRPAREA_BANK2_AREAB: Flash Bank 2 Area B - * - * @param[out] WRPStartOffset specifies the address where to copied the start page - * of the write protected area - * - * @param[out] WRPEndOffset specifies the address where to copied the end page of - * the write protected area - * - * @param[out] WRPLock specifies the lock status of the write protected area. - * The returned value can be ENABLE or DISABLE - * - * @retval None - */ -static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRPEndOffset, - FunctionalState *WRPLock) -{ - /* Get the configuration of the write protected area */ - if (WRPArea == OB_WRPAREA_BANK1_AREAA) - { - *WRPStartOffset = READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PSTRT); - *WRPEndOffset = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_WRP1A_PEND) >> FLASH_WRP1AR_WRP1A_PEND_Pos); - *WRPLock = (READ_BIT(FLASH->WRP1AR, FLASH_WRP1AR_UNLOCK) != 0U) ? DISABLE : ENABLE; - } - else if (WRPArea == OB_WRPAREA_BANK1_AREAB) - { - *WRPStartOffset = READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PSTRT); - *WRPEndOffset = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_WRP1B_PEND) >> FLASH_WRP1BR_WRP1B_PEND_Pos); - *WRPLock = (READ_BIT(FLASH->WRP1BR, FLASH_WRP1BR_UNLOCK) != 0U) ? DISABLE : ENABLE; - } - else if (WRPArea == OB_WRPAREA_BANK2_AREAA) - { - *WRPStartOffset = READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PSTRT); - *WRPEndOffset = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_WRP2A_PEND) >> FLASH_WRP2AR_WRP2A_PEND_Pos); - *WRPLock = (READ_BIT(FLASH->WRP2AR, FLASH_WRP2AR_UNLOCK) != 0U) ? DISABLE : ENABLE; - } - else if (WRPArea == OB_WRPAREA_BANK2_AREAB) - { - *WRPStartOffset = READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PSTRT); - *WRPEndOffset = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_WRP2B_PEND) >> FLASH_WRP2BR_WRP2B_PEND_Pos); - *WRPLock = (READ_BIT(FLASH->WRP2BR, FLASH_WRP2BR_UNLOCK) != 0U) ? DISABLE : ENABLE; - } - else - { - /* Empty statement (to be compliant MISRA 15.7) */ - } -} - -/** - * @brief Return the FLASH Read Protection level. - * @retval FLASH ReadOut Protection Level. - * This return value can be one of the following values: - * @arg OB_RDP_LEVEL_0: No protection - * @arg OB_RDP_LEVEL_0_5: No debug access to secure area - * @arg OB_RDP_LEVEL_1: Read protection of the memory - * @arg OB_RDP_LEVEL_2: Full chip protection - */ -static uint32_t FLASH_OB_GetRDP(void) -{ - uint32_t rdp_level = READ_BIT(FLASH->OPTR, FLASH_OPTR_RDP); - - if ((rdp_level != OB_RDP_LEVEL_0) && (rdp_level != OB_RDP_LEVEL_0_5) && (rdp_level != OB_RDP_LEVEL_2)) - { - return (OB_RDP_LEVEL_1); - } - else - { - return rdp_level; - } -} - -/** - * @brief Return the FLASH User Option Byte value. - * @retval The FLASH User Option Bytes values. - * The return value can be a combination of @ref FLASH_OB_USER_BOR_LEVEL, - * @ref FLASH_OB_USER_nRST_STOP, @ref FLASH_OB_USER_nRST_STANDBY, - * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_SRAM_RST, - * @ref FLASH_OB_USER_IWDG_SW, @ref FLASH_OB_USER_IWDG_STOP, - * @ref FLASH_OB_USER_IWDG_STANDBY, @ref FLASH_OB_USER_WWDG_SW, - * @ref OB_USER_SWAP_BANK, @ref FLASH_OB_USER_DUALBANK, - * @ref FLASH_OB_USER_BKPRAM_RST, @ref FLASH_OB_USER_SRAM3_ECC, - * @ref FLASH_OB_USER_SRAM2_ECC, @ref FLASH_OB_USER_SRAM2_RST, - * @ref FLASH_OB_USER_nSWBOOT0, @ref FLASH_OB_USER_nBOOT0, - * @ref FLASH_OB_USER_PA15_PUPEN, @ref FLASH_OB_USER_IO_VDD_HSLV, - * @ref FLASH_OB_USER_IO_VDDIO2_HSLV and @ref OB_USER_TZEN - */ -static uint32_t FLASH_OB_GetUser(void) -{ - uint32_t user_config = READ_REG(FLASH->OPTR); - CLEAR_BIT(user_config, FLASH_OPTR_RDP); - - return user_config; -} - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Return the watermarked-based secure area configuration. - * - * @param WMSecConfig [in/out] specifies the area to be returned. - * This parameter can be one of the following values: - * @arg OB_WMSEC_AREA1: select Flash Secure Area 1 - * @arg OB_WMSEC_AREA2: select Flash Secure Area 2 - * When return from the function, this parameter will be a combinaison of the following values: - * @arg OB_WMSEC_AREAA or @arg OB_WMSEC_AREAB: selected Flash Secure Area A or Area B - * @arg OB_WMSEC_HDP_AREA_ENABLE: Secure Hide Area in Secure Area enabled - * @arg OB_WMSEC_HDP_AREA_DISABLE: Secure Hide Area in Secure Area disabled - * - * @param WMSecStartPage [out] specifies the start page of the secure area - * - * @param WMSecEndPage [out] specifies the end page of the secure area - * - * @param WMHDPEndPage [out] specifies the end page of the secure hide area - * - * - * @retval None - */ -static void FLASH_OB_GetWMSEC(uint32_t *WMSecConfig, uint32_t *WMSecStartPage, uint32_t *WMSecEndPage, - uint32_t *WMHDPEndPage) -{ - uint32_t tmp_secwm1 = 0U; - uint32_t tmp_secwm2 = 0U; - - /* Check the parameters */ - assert_param(IS_OB_WMSEC_CONFIG(*WMSecConfig)); - assert_param(IS_FLASH_BANK_EXCLUSIVE((*WMSecConfig) & 0x3U)); - - /* Read SECWM registers */ - if (((*WMSecConfig) & OB_WMSEC_AREA1) != 0U) - { - tmp_secwm1 = FLASH->SECWM1R1; - tmp_secwm2 = FLASH->SECWM1R2; - } - else if (((*WMSecConfig) & OB_WMSEC_AREA2) != 0U) - { - tmp_secwm1 = FLASH->SECWM2R1; - tmp_secwm2 = FLASH->SECWM2R2; - } - else - { - /* Empty statement (to be compliant MISRA 15.7) */ - } - - /* Configuration of secure area */ - *WMSecStartPage = (tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PSTRT); - *WMSecEndPage = ((tmp_secwm1 & FLASH_SECWM1R1_SECWM1_PEND) >> FLASH_SECWM1R1_SECWM1_PEND_Pos); - - /* Configuration of secure hide area */ - *WMHDPEndPage = ((tmp_secwm2 & FLASH_SECWM1R2_HDP1_PEND) >> FLASH_SECWM1R2_HDP1_PEND_Pos); - - if ((tmp_secwm2 & FLASH_SECWM1R2_HDP1EN) == 0U) - { - *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_DISABLE); - } - else - { - *WMSecConfig = ((*WMSecConfig) | OB_WMSEC_HDP_AREA_ENABLE); - } - -} - -/** - * @brief Return the boot lock configuration. - * - * @retval Value of Boot Lock configuration. - * It can be one of the following values: - * @arg OB_BOOT_LOCK_DISABLE: Boot Lock mode deactivated - * @arg OB_BOOT_LOCK_ENABLE: Boot Lock mode activated - */ -static uint32_t FLASH_OB_GetBootLock(void) -{ - return (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_BOOT_LOCK); -} -#endif /* __ARM_FEATURE_CMSE */ - -/** - * @brief Return the boot address. - * - * @param[in] BootAddrConfig specifies the area to be returned. - * This parameter can be one of the following values: - * @arg OB_BOOTADDR_NS0: Non-secure boot address 0 - * @arg OB_BOOTADDR_NS1: Non-secure boot address 1 - * @arg OB_BOOTADDR_SEC0: Secure boot address 0 - * - * @param[out] BootAddr specifies the boot address value - * - * @retval None - */ -static void FLASH_OB_GetBootAddr(uint32_t BootAddrConfig, uint32_t *BootAddr) -{ - if (BootAddrConfig == OB_BOOTADDR_NS0) - { - *BootAddr = (FLASH->NSBOOTADD0R & FLASH_NSBOOTADD0R_NSBOOTADD0); - } - else if (BootAddrConfig == OB_BOOTADDR_NS1) - { - *BootAddr = (FLASH->NSBOOTADD1R & FLASH_NSBOOTADD1R_NSBOOTADD1); - } -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - else if (BootAddrConfig == OB_BOOTADDR_SEC0) - { - *BootAddr = (FLASH->SECBOOTADD0R & FLASH_SECBOOTADD0R_SECBOOTADD0); - } -#endif /* __ARM_FEATURE_CMSE */ - else - { - /* Empty statement (to be compliant MISRA 15.7) */ - } -} - -/** - * @} - */ - -#endif /* HAL_FLASH_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c deleted file mode 100644 index 7208911be..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gpio.c +++ /dev/null @@ -1,989 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_gpio.c - * @author MCD Application Team - * @brief GPIO HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the General Purpose Input/Output (GPIO) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### GPIO Peripheral features ##### - ============================================================================== - [..] - (+) Each port bit of the general-purpose I/O (GPIO) ports can be individually - configured by software in several modes: - (++) Input mode - (++) Analog mode - (++) Output mode - (++) Alternate function mode - (++) External interrupt/event lines - - (+) During and just after reset, the alternate functions and external interrupt - lines are not active and the I/O ports are configured in input floating mode. - - (+) All GPIO pins have weak internal pull-up and pull-down resistors, which can be - activated or not. - - (+) In Output or Alternate mode, each IO can be configured on open-drain or push-pull - type and the IO speed can be selected depending on the VDD value. - - (+) The microcontroller IO pins are connected to onboard peripherals/modules through a - multiplexer that allows only one peripheral alternate function (AF) connected - to an IO pin at a time. In this way, there can be no conflict between peripherals - sharing the same IO pin. - - (+) All ports have external interrupt/event capability. To use external interrupt - lines, the port must be configured in input mode. All available GPIO pins are - connected to the 16 external interrupt/event lines from EXTI0 to EXTI15. - - (+) The external interrupt/event controller consists of up to 39 edge detectors - (16 lines are connected to GPIO) for generating event/interrupt requests (each - input line can be independently configured to select the type (interrupt or event) - and the corresponding trigger event (rising or falling or both). Each line can - also be masked independently. - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Enable the GPIO AHB clock using the following function: __HAL_RCC_GPIOx_CLK_ENABLE(). - - (#) Configure the GPIO pin(s) using HAL_GPIO_Init(). - (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure - (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef - structure. - (++) In case of Output or alternate function mode selection: the speed is - configured through "Speed" member from GPIO_InitTypeDef structure. - (++) In alternate mode is selection, the alternate function connected to the IO - is configured through "Alternate" member from GPIO_InitTypeDef structure. - (++) Analog mode is required when a pin is to be used as ADC channel - or DAC output. - (++) In case of external interrupt/event selection the "Mode" member from - GPIO_InitTypeDef structure select the type (interrupt or event) and - the corresponding trigger event (rising or falling or both). - - (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority - mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using - HAL_NVIC_EnableIRQ(). - - (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin(). - - (#) To set/reset the level of a pin configured in output mode use - HAL_GPIO_WritePin()/HAL_GPIO_TogglePin(). - - (#) To set the level of several pins and reset level of several other pins in - same cycle, use HAL_GPIO_WriteMultipleStatePin(). - - (#) To lock pin configuration until next reset use HAL_GPIO_LockPin(). - - (#) During and just after reset, the alternate functions are not - active and the GPIO pins are configured in input floating mode (except JTAG - pins). - - (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose - (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has - priority over the GPIO function. - - (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as - general purpose PH0 and PH1, respectively, when the HSE oscillator is off. - The HSE has priority over the GPIO function. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @addtogroup GPIO - * @{ - */ - -#ifdef HAL_GPIO_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup GPIO_Private_Defines GPIO Private Defines - * @{ - */ -#define GPIO_MODE (0x00000003U) -#define EXTI_MODE (0x10000000U) -#define GPIO_MODE_IT (0x00010000U) -#define GPIO_MODE_EVT (0x00020000U) -#define RISING_EDGE (0x00100000U) -#define FALLING_EDGE (0x00200000U) -#define GPIO_OUTPUT_TYPE (0x00000010U) -#define GPIO_NUMBER (16U) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup GPIO_Private_Variables GPIO Private Variables - * @{ - */ - -/* LPGPIO Mapping */ -static const LPGPIO_MapTypeDef LPGPIO_Map[GPIO_NUMBER] = -{ - /* LPGPIO Pins Port Pin */ - /* Pin 0:*/ {GPIOA, 1}, - /* Pin 1:*/ {GPIOA, 3}, - /* Pin 2:*/ {GPIOA, 6}, - /* Pin 3:*/ {GPIOB, 1}, - /* Pin 4:*/ {GPIOB, 10}, - /* Pin 5:*/ {GPIOC, 2}, - /* Pin 6:*/ {GPIOD, 13}, - /* Pin 7:*/ {GPIOD, 2}, - /* Pin 8:*/ {GPIOC, 10}, - /* Pin 9:*/ {GPIOB, 0}, - /* Pin 10:*/ {GPIOC, 12}, - /* Pin 11:*/ {GPIOB, 3}, - /* Pin 12:*/ {GPIOB, 4}, - /* Pin 13:*/ {GPIOE, 0}, - /* Pin 14:*/ {GPIOE, 2}, - /* Pin 15:*/ {GPIOE, 3}, -}; - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup GPIO_Exported_Functions - * @{ - */ - -/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the GPIOx/LPGPIOx peripheral according to the specified parameters in the pGPIO_Init. - * @note If GPIOx/LPGPIOx peripheral pin is used in EXTI_MODE and the pin is secure in case - * the system implements the security (TZEN=1), it is up to the secure application to - * insure that the corresponding EXTI line is set secure. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the corresponding - * peripheral for STM32U5 family - * @param pGPIO_Init: pointer to a GPIO_InitTypeDef structure that contains - * the configuration information for the specified GPIO peripheral. - * @retval None - */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *pGPIO_Init) -{ - uint32_t tmp; - uint32_t iocurrent; - uint32_t pin_position; - uint32_t position = 0U; - GPIO_TypeDef *p_gpio; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(pGPIO_Init->Pin)); - assert_param(IS_GPIO_MODE(pGPIO_Init->Mode)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - /* Configure the port pins */ - while (((pGPIO_Init->Pin) >> position) != 0U) - { - /* Get current io position */ - iocurrent = (pGPIO_Init->Pin) & (1UL << position); - - /* Save Pin Position */ - pin_position = position; - - if (iocurrent != 0U) - { - /*--------------------- GPIO Mode Configuration ------------------------*/ - /* In case of Alternate function mode selection */ - if (GPIOx == LPGPIO1) - { - /* MODER configuration */ - tmp = GPIOx->MODER; - tmp &= ~(LPGPIO_MODER_MOD0 << position); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE_OUTPUT_PP) << position); - GPIOx->MODER = tmp; - - /* Save GPIO Port and pin index */ - p_gpio = LPGPIO_Map[position].GPIO_PORT; - pin_position = LPGPIO_Map[position].Pin_Pos; - - /* Configure Alternate function mapped with the current IO */ - tmp = p_gpio->AFR[(pin_position) >> 3U]; - tmp &= ~(0x0FUL << (((pin_position) & 0x07U) * 4U)); - tmp |= ((GPIO_AF11_LPGPIO1 & 0x0FUL) << (((pin_position) & 0x07U) * 4U)); - p_gpio->AFR[(pin_position) >> 3U] = tmp; - - /* Configure IO Direction mode (Alternate) */ - tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); - tmp |= ((GPIO_MODE_AF_PP & 0x0FUL) << (pin_position * GPIO_MODER_MODE1_Pos)); - p_gpio->MODER = tmp; - } - else if ((pGPIO_Init->Mode == GPIO_MODE_AF_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); - assert_param(IS_GPIO_AF(pGPIO_Init->Alternate)); - - /* Configure Alternate function mapped with the current IO */ - tmp = GPIOx->AFR[position >> 3U]; - tmp &= ~(0x0FUL << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); - tmp |= ((pGPIO_Init->Alternate & 0x0FUL) << ((position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); - GPIOx->AFR[position >> 3U] = tmp; - - /* Configure IO Direction mode (Alternate) */ - tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); - p_gpio->MODER = tmp; - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ - tmp = p_gpio->MODER; - tmp &= ~(GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); - tmp |= ((pGPIO_Init->Mode & GPIO_MODE) << (pin_position * GPIO_MODER_MODE1_Pos)); - p_gpio->MODER = tmp; - } - - /* In case of Output or Alternate function mode selection */ - if ((pGPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (pGPIO_Init->Mode == GPIO_MODE_AF_PP) || - (pGPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (pGPIO_Init->Mode == GPIO_MODE_AF_OD)) - { - /* Check the Speed parameter */ - assert_param(IS_GPIO_SPEED(pGPIO_Init->Speed)); - - /* Configure the IO Speed */ - tmp = p_gpio->OSPEEDR; - tmp &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); - tmp |= (pGPIO_Init->Speed << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); - p_gpio->OSPEEDR = tmp; - - /* Configure the IO Output Type */ - tmp = p_gpio->OTYPER; - tmp &= ~(GPIO_OTYPER_OT0 << pin_position); - tmp |= (((pGPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4U) << pin_position); - p_gpio->OTYPER = tmp; - } - - if (pGPIO_Init->Mode != GPIO_MODE_ANALOG) - { - /* Check the Pull parameters */ - assert_param(IS_GPIO_PULL(pGPIO_Init->Pull)); - - /* Activate the Pull-up or Pull down resistor for the current IO */ - tmp = p_gpio->PUPDR; - tmp &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); - tmp |= ((pGPIO_Init->Pull) << (pin_position * GPIO_PUPDR_PUPD1_Pos)); - p_gpio->PUPDR = tmp; - } - - /*--------------------- EXTI Mode Configuration ------------------------*/ - /* Configure the External Interrupt or event for the current IO */ - if ((pGPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) - { - tmp = EXTI->EXTICR[position >> 2U]; - tmp &= ~((0x0FUL) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); - tmp |= (GPIO_GET_INDEX(GPIOx) << (EXTI_EXTICR1_EXTI1_Pos * (position & 0x03U))); - EXTI->EXTICR[position >> 2U] = tmp; - - /* Clear Rising Falling edge configuration */ - tmp = EXTI->RTSR1; - tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & RISING_EDGE) == RISING_EDGE) - { - tmp |= iocurrent; - } - EXTI->RTSR1 = tmp; - - tmp = EXTI->FTSR1; - tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE) - { - tmp |= iocurrent; - } - EXTI->FTSR1 = tmp; - - /* Clear EXTI line configuration */ - tmp = EXTI->EMR1; - tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT) - { - tmp |= iocurrent; - } - EXTI->EMR1 = tmp; - - tmp = EXTI->IMR1; - tmp &= ~((uint32_t)iocurrent); - if ((pGPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT) - { - tmp |= iocurrent; - } - EXTI->IMR1 = tmp; - } - } - position++; - } -} - -/** - * @brief De-initialize the GPIOx peripheral registers to their default reset values. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) -{ - uint32_t tmp; - uint32_t iocurrent; - uint32_t pin_position; - uint32_t position = 0U; - GPIO_TypeDef *p_gpio; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0U) - { - /* Get current io position */ - iocurrent = (GPIO_Pin) & (1UL << position); - - /*Save Pin Position */ - pin_position = position; - - if (iocurrent != 0U) - { - /* In case of LPGPIO port selected */ - if (GPIOx == LPGPIO1) - { - /* Configure LP/IO in Input Mode */ - p_gpio = LPGPIO_Map[pin_position].GPIO_PORT; - pin_position = LPGPIO_Map[position].Pin_Pos; - LPGPIO1->MODER &= ~(1U << pin_position); - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /*------------------------- EXTI Mode Configuration --------------------*/ - /* Clear the External Interrupt or Event for the current IO */ - tmp = EXTI->EXTICR[position >> 2U]; - tmp &= ((0x0FUL) << (8U * (position & 0x03U))); - if (tmp == (GPIO_GET_INDEX(GPIOx) << (8U * (position & 0x03U)))) - { - /* Clear EXTI line configuration */ - EXTI->IMR1 &= ~(iocurrent); - EXTI->EMR1 &= ~(iocurrent); - - /* Clear Rising Falling edge configuration */ - EXTI->RTSR1 &= ~(iocurrent); - EXTI->FTSR1 &= ~(iocurrent); - - tmp = (0x0FUL) << (8U * (position & 0x03U)); - EXTI->EXTICR[position >> 2U] &= ~tmp; - } - } - - /*------------------------- GPIO Mode Configuration --------------------*/ - /* Configure IO in Analog Mode */ - p_gpio->MODER |= (GPIO_MODER_MODE0 << (pin_position * GPIO_MODER_MODE1_Pos)); - - /* Configure the default Alternate Function in current IO */ - p_gpio->AFR[pin_position >> 3U] &= ~(0x0FUL << ((pin_position & 0x07U) * GPIO_AFRL_AFSEL1_Pos)); - - /* Configure the default value for IO Speed */ - p_gpio->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (pin_position * GPIO_OSPEEDR_OSPEED1_Pos)); - - /* Configure the default value IO Output Type */ - p_gpio->OTYPER &= ~(GPIO_OTYPER_OT0 << pin_position); - - /* Deactivate the Pull-up and Pull-down resistor for the current IO */ - p_gpio->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (pin_position * GPIO_PUPDR_PUPD1_Pos)); - } - - position++; - } -} - -/** - * @} - */ - -/** @addtogroup GPIO_Exported_Functions_Group2 - * @brief GPIO/LPGPIO Read, Write, Toggle, Lock and EXTI management functions. - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Read the specified input port pin. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the port bit to read. - * This parameter can be GPIO_PIN_x where x can be (0..15). - * @retval The input port pin value. - */ -GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - GPIO_PinState bitstatus; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - if ((GPIOx->IDR & GPIO_Pin) != 0U) - { - bitstatus = GPIO_PIN_SET; - } - else - { - bitstatus = GPIO_PIN_RESET; - } - - return bitstatus; -} - -/** - * @brief Set or clear the selected data port bit. - * @note This function uses GPIOx_BSRR/LPGPIOx_BSRR and GPIOx_BRR/LPGPIOx_BRR registers to allow atomic read/modify - * accesses. In this way, there is no risk of an IRQ occurring between - * the read and the modify access. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. - * This parameter can be one of the GPIO_PinState enum values: - * @arg GPIO_PIN_RESET: to clear the port pin - * @arg GPIO_PIN_SET: to set the port pin - * @retval None - */ -void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) -{ - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ACTION(PinState)); - - if (PinState != GPIO_PIN_RESET) - { - GPIOx->BSRR = (uint32_t)GPIO_Pin; - } - else - { - GPIOx->BRR = (uint32_t)GPIO_Pin; - } -} - -/** - * @brief Set and clear several pins of a dedicated port in same cycle. - * @note This function uses GPIOx_BSRR and GPIOx_BRR registers to allow atomic read/modify - * accesses. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param PinReset specifies the port bits to be reset - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. - * @param PinSet specifies the port bits to be set - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15) or zero. - * @note Both PinReset and PinSet combinations shall not get any common bit, else - * assert would be triggered. - * @note At least one of the two parameters used to set or reset shall be different from zero. - * @retval None - */ -void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet) -{ - uint32_t tmp; - - /* Check the parameters */ - /* Make sure at least one parameter is different from zero and that there is no common pin */ - assert_param(IS_GPIO_PIN((uint32_t)PinReset | (uint32_t)PinSet)); - assert_param(IS_GPIO_COMMON_PIN(PinReset, PinSet)); - - tmp = (((uint32_t)PinReset << 16) | PinSet); - GPIOx->BSRR = tmp; -} - -/** - * @brief Toggle the specified GPIO pin. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin specifies the pin to be toggled. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t odr; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* get current Output Data Register value */ - odr = GPIOx->ODR; - - /* Set selected pins that were at low level, and reset ones that were high */ - GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); -} - -/** - * @brief Lock GPIO Pins configuration registers. - * @note The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, - * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. - * @note The configuration of the locked GPIO pins can no longer be modified - * until the next reset. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the port bits to be locked. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t iocurrent; - uint32_t pin_locked; - uint32_t pin_position; - uint32_t position = 0U; - GPIO_TypeDef *p_gpio; - __IO uint32_t tmp = GPIO_LCKR_LCKK; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0U) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1UL << position); - - if (iocurrent != 0U) - { - - /* In case of LPGPIO Port */ - if (GPIOx == LPGPIO1) - { - /* Save GPIO Port and pin index */ - p_gpio = LPGPIO_Map[position].GPIO_PORT; - pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos)); - - /* Save gpio pin locked */ - pin_locked = p_gpio->LCKR; - - /* Apply lock key write sequence */ - tmp |= (pin_locked | pin_position); - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Save GPIO Pin pos*/ - pin_position = (1UL << position); - - /* Save gpio pin locked */ - pin_locked = p_gpio->LCKR; - - /* Apply lock key write sequence */ - tmp |= (pin_locked | pin_position); - } - - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - p_gpio->LCKR = tmp; - /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */ - p_gpio->LCKR = pin_position; - /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ - p_gpio->LCKR = tmp; - /* Read LCKK register. This read is mandatory to complete key lock sequence */ - tmp = p_gpio->LCKR; - - /* read again in order to confirm lock is active */ - if ((p_gpio->LCKR & GPIO_LCKR_LCKK) != GPIO_LCKR_LCKK) - { - return HAL_ERROR; - } - } - position++; - } - return HAL_OK; -} - -/** - * @brief Enable speed optimization for several pin of dedicated port. - * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding - * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must - * be kept at reset value. - * @note It must be used only if the I/O supply voltage is below 2.7 V. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_EnableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t iocurrent; - uint32_t pin_position; - uint32_t position = 0U; - GPIO_TypeDef *p_gpio; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0U) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1UL << position); - - if (iocurrent != 0U) - { - /* In case of LPGPIO Port */ - if (GPIOx == LPGPIO1) - { - /* Get GPIO pin position */ - position = POSITION_VAL(GPIO_Pin); - - /* Save GPIO Port and pin index */ - p_gpio = LPGPIO_Map[position].GPIO_PORT; - pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos)); - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Save GPIO pin pos */ - pin_position = (1UL << position); - } - /* Set HSLVR gpio pin */ - SET_BIT(p_gpio->HSLVR, pin_position); - } - position++; - } -} - -/** - * @brief Disable speed optimization for several pin of dedicated port. - * @note Not all I/Os support the HSLV mode. Refer to the I/O structure in the corresponding - * datasheet for the list of I/Os supporting this feature. Other I/Os HSLV configuration must - * be kept at reset value. - * @note It must be used only if the I/O supply voltage is below 2.7 V. - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the port bit to be written. - * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). - * @retval None - */ -void HAL_GPIO_DisableHighSPeedLowVoltage(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) -{ - uint32_t iocurrent; - uint32_t pin_position; - uint32_t position = 0U; - GPIO_TypeDef *p_gpio; - - /* Check the parameters */ - assert_param(IS_GPIO_PIN(GPIO_Pin)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0U) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1UL << position); - - if (iocurrent != 0U) - { - /* In case of LPGPIO Port */ - if (GPIOx == LPGPIO1) - { - /* Get GPIO pin position */ - position = POSITION_VAL(GPIO_Pin); - - /* Save GPIO Port and pin index */ - p_gpio = LPGPIO_Map[position].GPIO_PORT; - pin_position = (1UL << (LPGPIO_Map[position].Pin_Pos)); - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Save GPIO pin pos */ - pin_position = (1UL << position); - } - /* Clear HSLVR gpio pin */ - CLEAR_BIT(p_gpio->HSLVR, pin_position); - } - position++; - } -} - -/** - * @brief Handle EXTI interrupt request. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) -{ - /* EXTI line interrupt detected */ - if (__HAL_GPIO_EXTI_GET_RISING_IT(GPIO_Pin) != 0U) - { - __HAL_GPIO_EXTI_CLEAR_RISING_IT(GPIO_Pin); - HAL_GPIO_EXTI_Rising_Callback(GPIO_Pin); - } - - if (__HAL_GPIO_EXTI_GET_FALLING_IT(GPIO_Pin) != 0U) - { - __HAL_GPIO_EXTI_CLEAR_FALLING_IT(GPIO_Pin); - HAL_GPIO_EXTI_Falling_Callback(GPIO_Pin); - } -} - -/** - * @brief EXTI line rising detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Rising_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Rising_Callback could be implemented in the user file - */ -} - -/** - * @brief EXTI line falling detection callback. - * @param GPIO_Pin: Specifies the port pin connected to corresponding EXTI line. - * @retval None - */ -__weak void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(GPIO_Pin); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_GPIO_EXTI_Falling_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @defgroup GPIO_Exported_Functions_Group3 IO attributes management functions - * @brief GPIO attributes management functions. - * -@verbatim - =============================================================================== - ##### IO attributes functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Configure the GPIO pins attributes. - * @note Available attributes are to secure GPIO pin(s), so this function is - * only available in secure - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the pin(s) to configure the secure attribute - * @param PinAttributes: specifies the pin(s) to be set in secure mode, other being set non secured. - * @retval None - */ -void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes) -{ - uint32_t iocurrent; - uint32_t pin_position; - uint32_t position = 0U; - GPIO_TypeDef *p_gpio; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_PIN(GPIO_Pin)); - assert_param(IS_GPIO_PIN_ATTRIBUTES(PinAttributes)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - /* Configure the port pins */ - while ((GPIO_Pin >> position) != 0U) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1UL << position); - - /* Save pin position */ - pin_position = position; - - if (iocurrent != 0U) - { - /* In case of LPGPIO Port */ - if (GPIOx == LPGPIO1) - { - /* Save GPIO Port and pin index */ - p_gpio = LPGPIO_Map[position].GPIO_PORT; - pin_position = LPGPIO_Map[position].Pin_Pos; - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - } - - /* Configure the IO secure attribute */ - MODIFY_REG(p_gpio->SECCFGR, (GPIO_SECCFGR_SEC0 << pin_position), (PinAttributes << pin_position)); - } - position++; - } -} - -/** - * @brief Get the GPIO pins attributes. - * @note Available attributes are to secure GPIO pin(s), so this function is - * only available in secure - * @param GPIOx or LPGPIOx: where x can be (A..I) for the GPIO and (1) for LPGPIO to select the the corresponding - * peripheral for STM32U5 family - * @param GPIO_Pin: specifies the single pin to get the secure attribute from - * @param pPinAttributes: pointer to return the pin attributes. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, - uint32_t *pPinAttributes) -{ - uint32_t iocurrent; - uint32_t pin_position; - uint32_t position = 0U; - const GPIO_TypeDef *p_gpio; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_GPIO_SINGLE_PIN(GPIO_Pin)); - - /* Check null pointer */ - if (pPinAttributes == NULL) - { - return HAL_ERROR; - } - - /* Get secure attribute of the port pin */ - while ((GPIO_Pin >> position) != 0U) - { - /* Get current io position */ - iocurrent = GPIO_Pin & (1UL << position); - - if (iocurrent != 0U) - { - /* In case of LPGPIO Port */ - if (GPIOx == LPGPIO1) - { - /* Save GPIO Port and pin index */ - p_gpio = LPGPIO_Map[position].GPIO_PORT; - pin_position = LPGPIO_Map[position].Pin_Pos; - } - else - { - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Save GPIO port address */ - p_gpio = GPIOx; - - pin_position = (1UL << position); - } - - /* Get the IO secure attribute */ - if ((p_gpio->SECCFGR & (GPIO_SECCFGR_SEC0 << pin_position)) != 0U) - { - *pPinAttributes = GPIO_PIN_SEC; - } - else - { - *pPinAttributes = GPIO_PIN_NSEC; - } - - break; - } - position++; - } - - return HAL_OK; -} - -/** - * @} - */ - -#endif /* __ARM_FEATURE_CMSE */ - - -/** - * @} - */ - -#endif /* HAL_GPIO_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c deleted file mode 100644 index c8b17c129..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_gtzc.c +++ /dev/null @@ -1,2210 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_gtzc.c - * @author MCD Application Team - * @brief GTZC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of GTZC peripheral: - * + TZSC Initialization and Configuration functions - * + TZSC-MPCWM Initialization and Configuration functions - * + MPCBB Initialization and Configuration functions - * + TZSC, TZSC-MPCWM and MPCBB Lock functions - * + TZIC Initialization and Configuration functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### GTZC main features ##### - ============================================================================== - [..] - (+) Global TrustZone Controller (GTZC) composed of three sub-blocks: - (++) TZSC: TrustZone security controller - This sub-block defines the secure/privileged state of master and slave - peripherals. It also controls the secure/privileged state of subregions - for the watermark memory peripheral controller (MPCWM). - (++) MPCBB: Block-Based memory protection controller - This sub-block defines the secure/privileged state of all blocks - (512-byte pages) of the associated SRAM. - (++) TZIC: TrustZone illegal access controller - This sub-block gathers all illegal access events in the system and - generates a secure interrupt towards NVIC. - - (+) These sub-blocks are used to configure TrustZone system security in - a product having bus agents with programmable-security and privileged - attributes (securable) such as: - (++) on-chip RAM with programmable secure and/or privilege blocks (pages) - (++) AHB and APB peripherals with programmable security and/or privilege access - (++) AHB master granted as secure and/or privilege - (++) off-chip memories with secure and/or privilege areas - - [..] - (+) TZIC accessible only with secure privileged transactions. - (+) Secure and non-secure access supported for privileged and unprivileged - part of TZSC and MPCBB - (+) Set of registers to define product security settings: - (++) Secure and privilege blocks for internal memories - (++) Secure and privilege regions for external memories - (++) Secure and privileged access mode for securable peripherals - - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The GTZC HAL driver can be used as follows: - - (#) Configure or get back securable peripherals attributes using - HAL_GTZC_TZSC_ConfigPeriphAttributes() / HAL_GTZC_TZSC_GetConfigPeriphAttributes() - - (#) Configure or get back MPCWM memories attributes using - HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes() / HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes() - - (#) Lock TZSC sub-block or get lock status using HAL_GTZC_TZSC_Lock() / - HAL_GTZC_TZSC_GetLock() - - (#) Configure or get back MPCBB memories complete configuration using - HAL_GTZC_MPCBB_ConfigMem() / HAL_GTZC_MPCBB_GetConfigMem() - - (#) Configure or get back MPCBB memories attributes using - HAL_GTZC_MPCBB_ConfigMemAttributes() / HAL_GTZC_MPCBB_GetConfigMemAttributes() - - (#) Lock MPCBB configuration or get lock status using HAL_GTZC_MPCBB_Lock() / - HAL_GTZC_MPCBB_GetLock() - - (#) Lock MPCBB super-blocks or get lock status using HAL_GTZC_MPCBB_LockConfig() / - HAL_GTZC_MPCBB_GetLockConfig() - - (#) Illegal access detection can be configured through TZIC sub-block using - following functions: HAL_GTZC_TZIC_DisableIT() / HAL_GTZC_TZIC_EnableIT() - - (#) Illegal access flags can be retrieved through HAL_GTZC_TZIC_GetFlag() and - HAL_GTZC_TZIC_ClearFlag() functions - - (#) Illegal access interrupt service routines are served by HAL_GTZC_IRQHandler() - and user can add his own code using HAL_GTZC_TZIC_Callback() - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup GTZC GTZC - * @brief GTZC HAL module driver - * @{ - */ - -#ifdef HAL_GTZC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ - -/** @defgroup GTZC_Private_Constants GTZC Private Constants - * @{ - */ - -/* Definitions for TZSC_MPCWM */ -#define TZSC_MPCWM1_MEM_SIZE 0x10000000U /* 256MB max size */ -#define TZSC_MPCWM2_MEM_SIZE 0x10000000U /* 256MB max size */ -#define TZSC_MPCWM3_MEM_SIZE 0x10000000U /* 256MB max size */ -#define TZSC_MPCWM4_MEM_SIZE 0x00000800U /* 2KB max size */ -#define TZSC_MPCWM5_MEM_SIZE 0x10000000U /* 256MB max size */ -#if defined (HSPI1) -#define TZSC_MPCWM6_MEM_SIZE 0x10000000U /* 256MB max size */ -#endif /* HSPI1 */ - -/* Definitions for GTZC TZSC & TZIC ALL register values */ -/* TZSC1 / TZIC1 instances */ -#if defined(STM32U599xx) || defined(STM32U595xx) || defined(STM32U5A9xx) || defined (STM32U5A5xx) -#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) -#define TZSC1_SECCFGR2_ALL (0x000007FFUL) -#define TZSC1_SECCFGR3_ALL (0x0FFFFFFFUL) - -#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) -#define TZSC1_PRIVCFGR2_ALL (0x000007FFUL) -#define TZSC1_PRIVCFGR3_ALL (0x0FFFFFFFUL) - -#define TZIC1_IER1_ALL (0x00EFFFFFUL) -#define TZIC1_IER2_ALL (0x000007FFUL) -#define TZIC1_IER3_ALL (0x0FFFFFFFUL) -#define TZIC1_IER4_ALL (0xFF1FC01FUL) - -#define TZIC1_FCR1_ALL (0x00EFFFFFUL) -#define TZIC1_FCR2_ALL (0x000007FFUL) -#define TZIC1_FCR3_ALL (0x0FFFFFFFUL) -#define TZIC1_FCR4_ALL (0xFF1FC01FUL) - -#elif defined(STM32U5F9xx) || defined(STM32U5G9xx) -#define TZSC1_SECCFGR1_ALL (0x00EFFFFFUL) -#define TZSC1_SECCFGR2_ALL (0x00000FFFUL) -#define TZSC1_SECCFGR3_ALL (0x1FFFFFFFUL) - -#define TZSC1_PRIVCFGR1_ALL (0x00EFFFFFUL) -#define TZSC1_PRIVCFGR2_ALL (0x00000FFFUL) -#define TZSC1_PRIVCFGR3_ALL (0x1FFFFFFFUL) - -#define TZIC1_IER1_ALL (0x00EFFFFFUL) -#define TZIC1_IER2_ALL (0x00000FFFUL) -#define TZIC1_IER3_ALL (0x1FFFFFFFUL) -#define TZIC1_IER4_ALL (0xFFDFC01FUL) - -#define TZIC1_FCR1_ALL (0x00EFFFFFUL) -#define TZIC1_FCR2_ALL (0x00000FFFUL) -#define TZIC1_FCR3_ALL (0x1FFFFFFFUL) -#define TZIC1_FCR4_ALL (0xFFDFC01FUL) -#else -#define TZSC1_SECCFGR1_ALL (0x000FFFFFUL) -#define TZSC1_SECCFGR2_ALL (0x000001FFUL) -#define TZSC1_SECCFGR3_ALL (0x007FFFFFUL) - -#define TZSC1_PRIVCFGR1_ALL (0x000FFFFFUL) -#define TZSC1_PRIVCFGR2_ALL (0x000001FFUL) -#define TZSC1_PRIVCFGR3_ALL (0x007FFFFFUL) - -#define TZIC1_IER1_ALL (0x000FFFFFUL) -#define TZIC1_IER2_ALL (0x000001FFUL) -#define TZIC1_IER3_ALL (0x007FFFFFUL) -#define TZIC1_IER4_ALL (0x3F0FC01FUL) - -#define TZIC1_FCR1_ALL (0x000FFFFFUL) -#define TZIC1_FCR2_ALL (0x000001FFUL) -#define TZIC1_FCR3_ALL (0x007FFFFFUL) -#define TZIC1_FCR4_ALL (0x3F0FC01FUL) -#endif /* STM32U599xx || STM32U595xx || STM32U5A9xx || STM32U5A5xx */ - -/* TZSC2 / TZIC2 instances */ -#define TZSC2_SECCFGR1_ALL (0x00001BFFUL) - -#define TZSC2_PRIVCFGR1_ALL (0x00001BFFUL) - -#define TZIC2_IER1_ALL (0x00001BFFUL) -#define TZIC2_IER2_ALL (0x0300C07FUL) - -#define TZIC2_FCR1_ALL (0x00001BFFUL) -#define TZIC2_FCR2_ALL (0x0300C07FUL) - -#define REG_SIZE 32U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup GTZC_Private_Macros GTZC Private Macros - * @{ - */ - -#define IS_ADDRESS_IN(mem, address) \ - ( ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) \ - || ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) ) - -#define IS_ADDRESS_IN_S(mem, address) \ - ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_S(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_S(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) - -#define IS_ADDRESS_IN_NS(mem, address) \ - ( ( (uint32_t)(address) >= (uint32_t)GTZC_BASE_ADDRESS_NS(mem) ) \ - && ( (uint32_t)(address) < ((uint32_t)GTZC_BASE_ADDRESS_NS(mem) + (uint32_t)GTZC_MEM_SIZE(mem) ) ) ) - -#define GTZC_BASE_ADDRESS(mem)\ - ( mem ## _BASE ) - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup GTZC_Exported_Functions GTZC Exported Functions - * @{ - */ - -/** @defgroup GTZC_Exported_Functions_Group1 TZSC Configuration functions - * @brief TZSC Configuration functions - * - @verbatim - ============================================================================== - ##### TZSC Configuration functions ##### - ============================================================================== - [..] - This section provides functions allowing to configure TZSC - TZSC: TrustZone Security Controller -@endverbatim - * @{ - */ - -/** - * @brief Configure TZSC on a single peripheral or on all peripherals. - * @note Secure and non-secure attributes can only be set from the secure - * state when the system implements the security (TZEN=1). - * @note Privilege and non-privilege attributes can only be set from the - * privilege state when TZEN=0 or TZEN=1 - * @note Security and privilege attributes can be set independently. - * @note Default state is non-secure and unprivileged access allowed. - * @param PeriphId Peripheral identifier - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. - * Use GTZC_PERIPH_ALL to select all peripherals. - * @param PeriphAttributes Peripheral attributes, see @ref GTZC_TZSC_PeriphAttributes. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZSC_ConfigPeriphAttributes(uint32_t PeriphId, - uint32_t PeriphAttributes) -{ - uint32_t register_address; - - /* check entry parameters */ - if ((PeriphAttributes > (GTZC_TZSC_PERIPH_SEC | GTZC_TZSC_PERIPH_PRIV)) - || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U))) - { - return HAL_ERROR; - } - - if ((PeriphId & GTZC_PERIPH_ALL) != 0U) - { - /* special case where same attributes are applied to all peripherals */ - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* secure configuration */ - if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) - { - SET_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); - SET_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); - SET_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); - SET_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL); - } - else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) - { - CLEAR_BIT(GTZC_TZSC1->SECCFGR1, TZSC1_SECCFGR1_ALL); - CLEAR_BIT(GTZC_TZSC1->SECCFGR2, TZSC1_SECCFGR2_ALL); - CLEAR_BIT(GTZC_TZSC1->SECCFGR3, TZSC1_SECCFGR3_ALL); - CLEAR_BIT(GTZC_TZSC2->SECCFGR1, TZSC2_SECCFGR1_ALL); - } - else - { - /* do nothing */ - } -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* privilege configuration */ - if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) - { - SET_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); - SET_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); - SET_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); - SET_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL); - } - else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) - { - CLEAR_BIT(GTZC_TZSC1->PRIVCFGR1, TZSC1_PRIVCFGR1_ALL); - CLEAR_BIT(GTZC_TZSC1->PRIVCFGR2, TZSC1_PRIVCFGR2_ALL); - CLEAR_BIT(GTZC_TZSC1->PRIVCFGR3, TZSC1_PRIVCFGR3_ALL); - CLEAR_BIT(GTZC_TZSC2->PRIVCFGR1, TZSC2_PRIVCFGR1_ALL); - } - else - { - /* do nothing */ - } - } - else - { - /* common case where only one peripheral is configured */ - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* secure configuration */ - register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - if ((PeriphAttributes & GTZC_TZSC_PERIPH_SEC) == GTZC_TZSC_PERIPH_SEC) - { - SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NSEC) == GTZC_TZSC_PERIPH_NSEC) - { - CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - else - { - /* do nothing */ - } -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* privilege configuration */ - register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - if ((PeriphAttributes & GTZC_TZSC_PERIPH_PRIV) == GTZC_TZSC_PERIPH_PRIV) - { - SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - else if ((PeriphAttributes & GTZC_TZSC_PERIPH_NPRIV) == GTZC_TZSC_PERIPH_NPRIV) - { - CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - else - { - /* do nothing */ - } - } - return HAL_OK; -} - -/** - * @brief Get TZSC configuration on a single peripheral or on all peripherals. - * @param PeriphId Peripheral identifier. - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. - * Use GTZC_PERIPH_ALL to select all peripherals. - * @param PeriphAttributes Peripheral attribute pointer. - * This parameter can be a value of @ref GTZC_TZSC_PeriphAttributes. - * If PeriphId target a single peripheral, pointer on a single element. - * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array of - * GTZC_TZSC_PERIPH_NUMBER elements is to be provided. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZSC_GetConfigPeriphAttributes(uint32_t PeriphId, - uint32_t *PeriphAttributes) -{ - uint32_t i; - uint32_t reg_value; - uint32_t register_address; - - /* check entry parameters */ - if ((PeriphAttributes == NULL) - || (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZSC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_TZSC_GET_ARRAY_INDEX(PeriphId) != 0U))) - { - return HAL_ERROR; - } - - if ((PeriphId & GTZC_PERIPH_ALL) != 0U) - { - /* get secure configuration: read each register and deploy each bit value - * of corresponding index in the destination array - */ - reg_value = READ_REG(GTZC_TZSC1->SECCFGR1); - for (i = 0U; i < 32U; i++) - { - if (((reg_value & (1UL << i)) >> i) != 0U) - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; - } - else - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; - } - } - - reg_value = READ_REG(GTZC_TZSC1->SECCFGR2); - for (i = 32U; i < 64U; i++) - { - if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; - } - else - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; - } - } - - reg_value = READ_REG(GTZC_TZSC1->SECCFGR3); - for (i = 64U; i < 96U; i++) - { - if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; - } - else - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; - } - } - - reg_value = READ_REG(GTZC_TZSC2->SECCFGR1); - for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++) - { - if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U) - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_SEC; - } - else - { - PeriphAttributes[i] = GTZC_TZSC_PERIPH_NSEC; - } - } - - /* get privilege configuration: read each register and deploy each bit value - * of corresponding index in the destination array - */ - reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR1); - for (i = 0U; i < 32U; i++) - { - if (((reg_value & (1UL << i)) >> i) != 0U) - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; - } - else - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; - } - } - - reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR2); - for (i = 32U; i < 64U; i++) - { - if (((reg_value & (1UL << (i - 32U))) >> (i - 32U)) != 0U) - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; - } - else - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; - } - } - - reg_value = READ_REG(GTZC_TZSC1->PRIVCFGR3); - for (i = 64U; i < 96U; i++) - { - if (((reg_value & (1UL << (i - 64U))) >> (i - 64U)) != 0U) - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; - } - else - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; - } - } - - reg_value = READ_REG(GTZC_TZSC2->PRIVCFGR1); - for (i = 96U; i < GTZC_TZSC_PERIPH_NUMBER; i++) - { - if (((reg_value & (1UL << (i - 96U))) >> (i - 96U)) != 0U) - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_PRIV; - } - else - { - PeriphAttributes[i] |= GTZC_TZSC_PERIPH_NPRIV; - } - } - } - else - { - /* common case where only one peripheral is configured */ - - /* secure configuration */ - register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->SECCFGR1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - - if (((READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) - != 0U) - { - *PeriphAttributes = GTZC_TZSC_PERIPH_SEC; - } - else - { - *PeriphAttributes = GTZC_TZSC_PERIPH_NSEC; - } - - /* privilege configuration */ - register_address = (uint32_t) &(HAL_GTZC_TZSC_GET_INSTANCE(PeriphId)->PRIVCFGR1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - if (((READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId))) >> GTZC_GET_PERIPH_POS(PeriphId)) - != 0U) - { - *PeriphAttributes |= GTZC_TZSC_PERIPH_PRIV; - } - else - { - *PeriphAttributes |= GTZC_TZSC_PERIPH_NPRIV; - } - } - return HAL_OK; -} - -/** - * @} - */ - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - -/** @defgroup GTZC_Exported_Functions_Group2 MPCWM Configuration functions - * @brief MPCWM Configuration functions - * - @verbatim - ============================================================================== - ##### MPCWM Configuration functions ##### - ============================================================================== - [..] - This section provides functions allowing to configure MPCWM - MPCWM is Memory Protection Controller WaterMark -@endverbatim - * @{ - */ - -/** - * @brief Configure a TZSC-MPCWM area. - * @param MemBaseAddress WM identifier. - * @param pMPCWM_Desc TZSC-MPCWM descriptor pointer. - * The structure description is available in @ref GTZC_Exported_Types. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_ConfigMemAttributes(uint32_t MemBaseAddress, - const MPCWM_ConfigTypeDef *pMPCWM_Desc) -{ - uint32_t register_address; - uint32_t reg_value; - uint32_t size; - /* granularity value depends on selected memory */ - uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \ - GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; - - /* check entry parameters */ - if ((pMPCWM_Desc->AreaId > GTZC_TZSC_MPCWM_ID2) || -#if defined (FMC_BANK3) - (((MemBaseAddress == BKPSRAM_BASE) || (MemBaseAddress == FMC_BANK3)) && -#else - ((MemBaseAddress == BKPSRAM_BASE) && -#endif /* FMC_BANK3 */ - (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2)) || - ((pMPCWM_Desc->Offset % granularity) != 0U) || - ((pMPCWM_Desc->Length % granularity) != 0U)) - { - return HAL_ERROR; - } - - /* check descriptor content vs. memory capacity */ - switch (MemBaseAddress) - { - case OCTOSPI1_BASE: - size = TZSC_MPCWM1_MEM_SIZE; - if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) - { - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); - } - else - { - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 - * (Parameter already checked) - */ - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); - } - break; -#if defined (FMC_BANK1) - case FMC_BANK1: - size = TZSC_MPCWM1_MEM_SIZE; - if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) - { - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); - } - else - { - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 - * (Parameter already checked) - */ - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); - } - break; -#endif /* FMC_BANK1 */ -#if defined (FMC_BANK3) - case FMC_BANK3: - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 - * (Parameter already checked) - */ - size = TZSC_MPCWM3_MEM_SIZE; - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); - break; -#endif /* FMC_BANK3 */ - case BKPSRAM_BASE: - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1 - * (Parameter already checked) - */ - size = TZSC_MPCWM4_MEM_SIZE; - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); - break; -#if defined (OCTOSPI2_BASE) - case OCTOSPI2_BASE: - size = TZSC_MPCWM5_MEM_SIZE; - if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) - { - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); - } - else - { - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 - * (Parameter already checked) - */ - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); - } - break; -#endif /* OCTOSPI2_BASE */ -#if defined (HSPI1) - case HSPI1_BASE: - size = TZSC_MPCWM6_MEM_SIZE; - if (pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID1) - { - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); - } - else - { - /* Here pMPCWM_Desc->AreaId == GTZC_TZSC_MPCWM_ID2 - * (Parameter already checked) - */ - register_address = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); - } - break; -#endif /* HSPI1 */ - default: - return HAL_ERROR; - break; - } - - if ((pMPCWM_Desc->Offset > size) || - ((pMPCWM_Desc->Offset + pMPCWM_Desc->Length) > size)) - { - return HAL_ERROR; - } - - /* Write watermark start and length value */ - reg_value = ((pMPCWM_Desc->Offset / granularity) - << GTZC_TZSC_MPCWMR_SUBZ_START_Pos) & GTZC_TZSC_MPCWMR_SUBZ_START_Msk; - reg_value |= ((pMPCWM_Desc->Length / granularity) - << GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk; - MODIFY_REG(*(__IO uint32_t *)register_address, GTZC_TZSC_MPCWMR_SUBZ_START_Msk | \ - GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk, reg_value); - - /* Write watermark configuration value */ - reg_value = (pMPCWM_Desc->Attribute << GTZC_TZSC_MPCWM_CFGR_SEC_Pos) | \ - pMPCWM_Desc->Lock | \ - pMPCWM_Desc->AreaStatus; - MODIFY_REG(*(__IO uint32_t *)(register_address - 4U), (GTZC_TZSC_MPCWM_CFGR_PRIV | GTZC_TZSC_MPCWM_CFGR_SEC | \ - GTZC_TZSC_MPCWM_CFGR_SRLOCK | GTZC_TZSC_MPCWM_CFGR_SREN), \ - reg_value); - - return HAL_OK; -} - -/** - * @brief Get a TZSC-MPCWM area configuration. - * @param MemBaseAddress WM identifier. - * @param pMPCWM_Desc pointer to a TZSC-MPCWM descriptor. - * When the WaterMark memory supports two sub-regions A and B. pMPCWM_Desc argument must point to an array of - * two MPCWM_ConfigTypeDef structures. - * The structure description is available in @ref GTZC_Exported_Types. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAddress, - MPCWM_ConfigTypeDef *pMPCWM_Desc) -{ - uint32_t register_address_regionA; - uint32_t register_address_regionB = 0U; - uint32_t reg_value; - uint32_t granularity = (MemBaseAddress == BKPSRAM_BASE) ? \ - GTZC_TZSC_MPCWM_GRANULARITY_2 : GTZC_TZSC_MPCWM_GRANULARITY_1; - - /* Loading the subregion A & B addresses into their specific variables */ - switch (MemBaseAddress) - { - case OCTOSPI1_BASE: - register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM1AR); - register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM1BR); - break; -#if defined (FMC_BANK1) - case FMC_BANK1: - register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM2AR); - register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM2BR); - break; -#endif /* FMC_BANK1 */ -#if defined (FMC_BANK3) - case FMC_BANK3: - register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM3AR); - break; -#endif /* FMC_BANK3 */ - case BKPSRAM_BASE: - register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM4AR); - break; -#if defined (OCTOSPI2_BASE) - case OCTOSPI2_BASE: - register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM5AR); - register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM5BR); - break; -#endif /* OCTOSPI2_BASE */ -#if defined (HSPI1) - case HSPI1_BASE: - register_address_regionA = (uint32_t) &(GTZC_TZSC1_S->MPCWM6AR); - register_address_regionB = (uint32_t) &(GTZC_TZSC1_S->MPCWM6BR); - break; -#endif /* HSPI1 */ - default: - return HAL_ERROR; - break; - } - - /* read register and update the descriptor for first area*/ - reg_value = READ_REG(*(__IO uint32_t *)register_address_regionA); - pMPCWM_Desc[0].AreaId = GTZC_TZSC_MPCWM_ID1; - pMPCWM_Desc[0].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk) - >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity; - pMPCWM_Desc[0].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk) - >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity; - - /* read configuration register and update the descriptor for first area*/ - reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionA - 4U)); - pMPCWM_Desc[0].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ - GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; - pMPCWM_Desc[0].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; - pMPCWM_Desc[0].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; - - if (register_address_regionB != 0U) - { - /* read register and update the descriptor for second area*/ - reg_value = READ_REG(*(__IO uint32_t *)register_address_regionB); - pMPCWM_Desc[1].AreaId = GTZC_TZSC_MPCWM_ID2; - pMPCWM_Desc[1].Offset = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_START_Msk) - >> GTZC_TZSC_MPCWMR_SUBZ_START_Pos) * granularity; - pMPCWM_Desc[1].Length = ((reg_value & GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Msk) - >> GTZC_TZSC_MPCWMR_SUBZ_LENGTH_Pos) * granularity; - - /* read configuration register and update the descriptor for second area*/ - reg_value = READ_REG(*(__IO uint32_t *)(register_address_regionB - 4U)); - pMPCWM_Desc[1].Attribute = (reg_value & (GTZC_TZSC_MPCWM_CFGR_PRIV | \ - GTZC_TZSC_MPCWM_CFGR_SEC)) >> GTZC_TZSC_MPCWM_CFGR_SEC_Pos; - pMPCWM_Desc[1].Lock = reg_value & GTZC_TZSC_MPCWM_CFGR_SRLOCK; - pMPCWM_Desc[1].AreaStatus = reg_value & GTZC_TZSC_MPCWM_CFGR_SREN; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup GTZC_Exported_Functions_Group3 TZSC Lock functions - * @brief TZSC Lock functions - * - @verbatim - ============================================================================== - ##### TZSC Lock functions ##### - ============================================================================== - [..] - This section provides functions allowing to manage the TZSC (TrustZone - Security Controller) lock. It includes lock enable, and current value read. -@endverbatim - * @{ - */ - -/** - * @brief Lock TZSC configuration. - * @note This function locks the configuration of TZSC_SECCFGRx and TZSC_PRIVCFGRx - * registers until next reset - * @param TZSC_Instance TZSC sub-block instance. - */ -void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSC_Instance) -{ - SET_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); -} - -/** - * @brief Get TZSC configuration lock state. - * @param TZSC_Instance TZSC sub-block instance. - * @retval Lock State (GTZC_TZSC_LOCK_OFF or GTZC_TZSC_LOCK_ON) - */ -uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSC_Instance) -{ - return READ_BIT(TZSC_Instance->CR, GTZC_TZSC_CR_LCK_Msk); -} - -/** - * @} - */ -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** @defgroup GTZC_Exported_Functions_Group4 MPCBB Configuration functions - * @brief MPCBB Configuration functions - * - @verbatim - ============================================================================== - ##### MPCBB Configuration functions ##### - ============================================================================== - [..] - This section provides functions allowing to configure MPCBB - MPCBB is Memory Protection Controller Block Base -@endverbatim - * @{ - */ - -/** - * @brief Set a complete MPCBB configuration on the SRAM passed as parameter. - * @param MemBaseAddress MPCBB identifier. - * @param pMPCBB_desc pointer to MPCBB descriptor. - * The structure description is available in @ref GTZC_Exported_Types. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMem(uint32_t MemBaseAddress, - const MPCBB_ConfigTypeDef *pMPCBB_desc) -{ - GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t mem_size; - uint32_t size_in_superblocks; - uint32_t i; - - /* check entry parameters */ - if ((!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) -#if defined (SRAM3_BASE) - && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) -#endif /* SRAM3_BASE */ - && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) -#if defined (SRAM5_BASE) - && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) -#endif /* SRAM6_BASE */ - ) - || ((pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_ENABLE) - && (pMPCBB_desc->SecureRWIllegalMode != GTZC_MPCBB_SRWILADIS_DISABLE)) - || ((pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_NOT_INVERTED) - && (pMPCBB_desc->InvertSecureState != GTZC_MPCBB_INVSECSTATE_INVERTED))) - { - return HAL_ERROR; - } - - if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB1; - mem_size = GTZC_MEM_SIZE(SRAM1); - } - else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB2; - mem_size = GTZC_MEM_SIZE(SRAM2); - } -#if defined (SRAM3_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB3; - mem_size = GTZC_MEM_SIZE(SRAM3); - } -#endif /* SRAM3_BASE */ - else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB4; - mem_size = GTZC_MEM_SIZE(SRAM4); - } -#if defined (SRAM5_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB5; - mem_size = GTZC_MEM_SIZE(SRAM5); - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB6; - mem_size = GTZC_MEM_SIZE(SRAM6); - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - /* translate mem_size in number of super-blocks */ - size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); - - /* write PRIVCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->PRIVCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i]); - } - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t size_mask; - uint32_t reg_value; - - /* write SECCFGR register information */ - for (i = 0U; i < size_in_superblocks; i++) - { - WRITE_REG(mpcbb_ptr->SECCFGR[i], - pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i]); - } - -#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) - if (size_in_superblocks >= 32U) - { - size_mask = 0xFFFFFFFFU; - MODIFY_REG(mpcbb_ptr->CFGLOCKR2, 0x000FFFFFUL, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1]); - } - else -#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ - { - size_mask = (1UL << (size_in_superblocks & 0x1FU)) - 1U; - } - /* limitation: code not portable with memory > 512K */ - MODIFY_REG(mpcbb_ptr->CFGLOCKR1, size_mask, pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0]); - - /* write InvertSecureState and SecureRWIllegalMode properties */ - reg_value = pMPCBB_desc->InvertSecureState; - reg_value |= pMPCBB_desc->SecureRWIllegalMode; - - /* write configuration and lock register information */ - MODIFY_REG(mpcbb_ptr->CR, - GTZC_MPCBB_CR_INVSECSTATE_Msk | GTZC_MPCBB_CR_SRWILADIS_Msk, reg_value); -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - return HAL_OK; -} - -/** - * @brief Get a complete MPCBB configuration on the SRAM passed as parameter. - * @param MemBaseAddress MPCBB identifier. - * @param pMPCBB_desc pointer to a MPCBB descriptor. - * The structure description is available in @ref GTZC_Exported_Types. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMem(uint32_t MemBaseAddress, - MPCBB_ConfigTypeDef *pMPCBB_desc) -{ - GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t mem_size; - uint32_t size_in_superblocks; - uint32_t i; - - /* check entry parameters */ - if (!(IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - && !(IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) -#if defined (SRAM3_BASE) - && !(IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) -#endif /* SRAM3_BASE */ - && !(IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) -#if defined (SRAM5_BASE) - && !(IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - && !(IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) -#endif /* SRAM6_BASE */ - ) - { - return HAL_ERROR; - } - - /* read InvertSecureState and SecureRWIllegalMode properties */ - /* assume their Position/Mask is identical for all sub-blocks */ - if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB1; - mem_size = GTZC_MEM_SIZE(SRAM1); - } - else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB2; - mem_size = GTZC_MEM_SIZE(SRAM2); - } -#if defined (SRAM3_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB3; - mem_size = GTZC_MEM_SIZE(SRAM3); - } -#endif /* SRAM3_BASE */ - else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB4; - mem_size = GTZC_MEM_SIZE(SRAM4); - } -#if defined (SRAM5_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB5; - mem_size = GTZC_MEM_SIZE(SRAM5); - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) - { - mpcbb_ptr = GTZC_MPCBB6; - mem_size = GTZC_MEM_SIZE(SRAM6); - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - /* translate mem_size in number of super-blocks */ - size_in_superblocks = (mem_size / GTZC_MPCBB_SUPERBLOCK_SIZE); - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - uint32_t reg_value; - - /* read configuration and lock register information */ - reg_value = READ_REG(mpcbb_ptr->CR); - pMPCBB_desc->InvertSecureState = (reg_value & GTZC_MPCBB_CR_INVSECSTATE_Msk); - pMPCBB_desc->SecureRWIllegalMode = (reg_value & GTZC_MPCBB_CR_SRWILADIS_Msk); - - /* limitation: code not portable with memory > 512K */ - pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[0] = READ_REG(mpcbb_ptr->CFGLOCKR1); - -#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) - pMPCBB_desc->AttributeConfig.MPCBB_LockConfig_array[1] = READ_REG(mpcbb_ptr->CFGLOCKR2); -#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ - -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* read SECCFGR / PRIVCFGR registers information */ - for (i = 0U; i < size_in_superblocks; i++) - { - pMPCBB_desc->AttributeConfig.MPCBB_SecConfig_array[i] = mpcbb_ptr->SECCFGR[i]; - pMPCBB_desc->AttributeConfig.MPCBB_PrivConfig_array[i] = mpcbb_ptr->PRIVCFGR[i]; - } - - return HAL_OK; -} - -/** - * @brief Set a MPCBB attribute configuration on the SRAM passed as parameter - * for a number of blocks. - * @param MemAddress MPCBB identifier, and start block to configure - * (must be 512 Bytes aligned). - * @param NbBlocks Number of blocks to configure - * (Block size is 512 Bytes). - * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), - * with each element must be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, - * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_ConfigMemAttributes(uint32_t MemAddress, - uint32_t NbBlocks, - const uint32_t *pMemAttributes) -{ - GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t base_address; - uint32_t end_address; - uint32_t block_start; - uint32_t offset_reg_start; - uint32_t offset_bit_start; - uint32_t i; - uint32_t do_attr_change; - - /* firstly check that MemAddress is well 512 Bytes aligned */ - if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U) - { - return HAL_ERROR; - } - - /* check entry parameters and deduce physical base address */ - end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; - if (((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM1, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB1; - base_address = SRAM1_BASE_NS; - } - else if (((IS_ADDRESS_IN_S(SRAM1, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM1, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB1; - base_address = SRAM1_BASE_S; - } - else if (((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM2, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB2; - base_address = SRAM2_BASE_NS; - } - else if (((IS_ADDRESS_IN_S(SRAM2, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM2, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB2; - base_address = SRAM2_BASE_S; - } -#if defined (SRAM3_BASE) - else if (((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM3, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB3; - base_address = SRAM3_BASE_NS; - } - else if (((IS_ADDRESS_IN_S(SRAM3, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM3, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB3; - base_address = SRAM3_BASE_S; - } -#endif /* SRAM3_BASE */ - else if (((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM4, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB4; - base_address = SRAM4_BASE_NS; - } - else if (((IS_ADDRESS_IN_S(SRAM4, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM4, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB4; - base_address = SRAM4_BASE_S; - } -#if defined (SRAM5_BASE) - else if (((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM5, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB5; - base_address = SRAM5_BASE_NS; - } - else if (((IS_ADDRESS_IN_S(SRAM5, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM5, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB5; - base_address = SRAM5_BASE_S; - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if (((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM6, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB6; - base_address = SRAM6_BASE_NS; - } - else if (((IS_ADDRESS_IN_S(SRAM6, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM6, end_address))) != 0U) - { - mpcbb_ptr = GTZC_MPCBB6; - base_address = SRAM6_BASE_S; - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - /* get start coordinates of the configuration */ - block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; - offset_reg_start = block_start / 32U; - offset_bit_start = block_start % 32U; - - for (i = 0U; i < NbBlocks; i++) - { - /* Indicate change done for protection attributes */ - do_attr_change = 0U; - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* secure configuration */ - if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_SEC) == GTZC_MPCBB_BLOCK_SEC) - { - SET_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)); - do_attr_change = 1U; - } - else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NSEC) == GTZC_MPCBB_BLOCK_NSEC) - { - CLEAR_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)); - do_attr_change = 1U; - } - else - { - /* nothing to do */ - } -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* privilege configuration */ - if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_PRIV) == GTZC_MPCBB_BLOCK_PRIV) - { - SET_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)); - } - else if ((pMemAttributes[i] & GTZC_MPCBB_BLOCK_NPRIV) == GTZC_MPCBB_BLOCK_NPRIV) - { - CLEAR_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)); - } - else - { - /* if no change is done for security and privilege attributes: break the loop */ - if (do_attr_change == 0U) - { - break; - } - } - - offset_bit_start++; - if (offset_bit_start == 32U) - { - offset_bit_start = 0U; - offset_reg_start++; - } - } - - /* an unexpected value in pMemAttributes array leads to error status */ - if (i != NbBlocks) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Get a MPCBB attribute configuration on the SRAM passed as parameter - * for a number of blocks. - * @param MemAddress MPCBB identifier, and start block to get configuration - * (must be 512 Bytes aligned). - * @param NbBlocks Number of blocks to get configuration. - * @param pMemAttributes pointer to an array (containing "NbBlocks" elements), - * with each element will be GTZC_MPCBB_BLOCK_NSEC or GTZC_MPCBB_BLOCK_SEC, - * and GTZC_MPCBB_BLOCK_NPRIV or GTZC_MPCBB_BLOCK_PRIV. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetConfigMemAttributes(uint32_t MemAddress, - uint32_t NbBlocks, - uint32_t *pMemAttributes) -{ - GTZC_MPCBB_TypeDef *mpcbb_ptr; - uint32_t base_address; - uint32_t end_address; - uint32_t block_start; - uint32_t offset_reg_start; - uint32_t offset_bit_start; - uint32_t i; - - /* firstly check that MemAddress is well 512 Bytes aligned */ - if ((MemAddress % GTZC_MPCBB_BLOCK_SIZE) != 0U) - { - return HAL_ERROR; - } - - /* check entry parameters and deduce physical base address */ - end_address = MemAddress + (NbBlocks * GTZC_MPCBB_BLOCK_SIZE) - 1U; - if ((IS_ADDRESS_IN_NS(SRAM1, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM1, end_address))) - { - mpcbb_ptr = GTZC_MPCBB1_NS; - base_address = SRAM1_BASE_NS; - } - else if ((IS_ADDRESS_IN_S(SRAM1, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM1, end_address))) - { - mpcbb_ptr = GTZC_MPCBB1_S; - base_address = SRAM1_BASE_S; - } - else if ((IS_ADDRESS_IN_NS(SRAM2, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM2, end_address))) - { - mpcbb_ptr = GTZC_MPCBB2_NS; - base_address = SRAM2_BASE_NS; - } - else if ((IS_ADDRESS_IN_S(SRAM2, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM2, end_address))) - { - mpcbb_ptr = GTZC_MPCBB2_S; - base_address = SRAM2_BASE_S; - } -#if defined (SRAM3_BASE) - else if ((IS_ADDRESS_IN_NS(SRAM3, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM3, end_address))) - { - mpcbb_ptr = GTZC_MPCBB3_NS; - base_address = SRAM3_BASE_NS; - } - else if ((IS_ADDRESS_IN_S(SRAM3, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM3, end_address))) - { - mpcbb_ptr = GTZC_MPCBB3_S; - base_address = SRAM3_BASE_S; - } -#endif /* SRAM3_BASE */ - else if ((IS_ADDRESS_IN_NS(SRAM4, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM4, end_address))) - { - mpcbb_ptr = GTZC_MPCBB4_NS; - base_address = SRAM4_BASE_NS; - } - else if ((IS_ADDRESS_IN_S(SRAM4, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM4, end_address))) - { - mpcbb_ptr = GTZC_MPCBB4_S; - base_address = SRAM4_BASE_S; - } -#if defined (SRAM5_BASE) - else if ((IS_ADDRESS_IN_NS(SRAM5, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM5, end_address))) - { - mpcbb_ptr = GTZC_MPCBB5_NS; - base_address = SRAM5_BASE_NS; - } - else if ((IS_ADDRESS_IN_S(SRAM5, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM5, end_address))) - { - mpcbb_ptr = GTZC_MPCBB5_S; - base_address = SRAM5_BASE_S; - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if ((IS_ADDRESS_IN_NS(SRAM6, MemAddress)) - && (IS_ADDRESS_IN_NS(SRAM6, end_address))) - { - mpcbb_ptr = GTZC_MPCBB6_NS; - base_address = SRAM6_BASE_NS; - } - else if ((IS_ADDRESS_IN_S(SRAM6, MemAddress)) - && (IS_ADDRESS_IN_S(SRAM6, end_address))) - { - mpcbb_ptr = GTZC_MPCBB6_S; - base_address = SRAM6_BASE_S; - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - /* get start coordinates of the configuration */ - block_start = (MemAddress - base_address) / GTZC_MPCBB_BLOCK_SIZE; - offset_reg_start = block_start / 32U; - offset_bit_start = block_start % 32U; - - for (i = 0U; i < NbBlocks; i++) - { - pMemAttributes[i] = (READ_BIT(mpcbb_ptr->SECCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)) - >> (offset_bit_start % 32U)) | GTZC_ATTR_SEC_MASK; - pMemAttributes[i] |= ((READ_BIT(mpcbb_ptr->PRIVCFGR[offset_reg_start], - 1UL << (offset_bit_start % 32U)) - >> (offset_bit_start % 32U)) << 1U) | GTZC_ATTR_PRIV_MASK; - - offset_bit_start++; - if (offset_bit_start == 32U) - { - offset_bit_start = 0U; - offset_reg_start++; - } - } - - return HAL_OK; -} - -#if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -/** - * @brief Lock MPCBB super-blocks on the SRAM passed as parameter. - * @param MemAddress MPCBB start-address of super-block to configure - * (must be 16KBytes aligned). - * @param NbSuperBlocks Number of super-blocks to configure. - * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), - * with for each element: - * value 0 super-block is unlocked, value 1 super-block is locked - * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and - * GTZC_MPCBB_SUPERBLOCK_LOCKED values). - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_LockConfig(uint32_t MemAddress, - uint32_t NbSuperBlocks, - const uint32_t *pLockAttributes) -{ - __IO uint32_t *reg_mpcbb; - uint32_t base_address; - uint32_t superblock_start; - uint32_t offset_bit_start; - uint32_t i = 0U; - - /* firstly check that MemAddress is well 16KBytes aligned */ - if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) - { - return HAL_ERROR; - } - - /* check entry parameters */ - if ((IS_ADDRESS_IN(SRAM1, MemAddress)) - && (IS_ADDRESS_IN(SRAM1, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM1); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; - } - else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) - && (IS_ADDRESS_IN(SRAM2, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM2); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; - } -#if defined (SRAM3_BASE) - else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) - && (IS_ADDRESS_IN(SRAM3, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM3); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; - } -#endif /* SRAM3_BASE */ - else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) - && (IS_ADDRESS_IN(SRAM4, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM4); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; - } -#if defined (SRAM5_BASE) - else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) - && (IS_ADDRESS_IN(SRAM5, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM5); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) - && (IS_ADDRESS_IN(SRAM6, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM6); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - /* get start coordinates of the configuration */ - superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; - offset_bit_start = superblock_start % 32U; - - /* First 32 super-blocks */ - while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) - { - if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) - { - SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); - } - else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) - { - CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); - } - else - { - break; - } - - offset_bit_start++; - i++; - } - -#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) - if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) - { - /* Point to second configuration lock register */ - reg_mpcbb++; - - /* Remaining super-blocks */ - for (; i < NbSuperBlocks; i++) - { - if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_LOCKED) - { - SET_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); - } - else if (pLockAttributes[i] == GTZC_MPCBB_SUPERBLOCK_UNLOCKED) - { - CLEAR_BIT(*reg_mpcbb, 1UL << (offset_bit_start % 32U)); - } - else - { - break; - } - - offset_bit_start++; - } - } -#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ - - /* an unexpected value in pLockAttributes array leads to an error status */ - if (i != NbSuperBlocks) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Get MPCBB super-blocks lock configuration on the SRAM passed as parameter. - * @param MemAddress MPCBB start-address of super-block to get configuration - * (must be 16KBytes aligned). - * @param NbSuperBlocks Number of super-blocks to get configuration. - * @param pLockAttributes pointer to an array (containing "NbSuperBlocks" elements), - * with for each element: - * value 0 super-block is unlocked, value 1 super-block is locked - * (corresponds to GTZC_MPCBB_SUPERBLOCK_UNLOCKED and - * GTZC_MPCBB_SUPERBLOCK_LOCKED values). - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLockConfig(uint32_t MemAddress, - uint32_t NbSuperBlocks, - uint32_t *pLockAttributes) -{ - __IO uint32_t *reg_mpcbb; - uint32_t base_address; - uint32_t superblock_start; - uint32_t offset_bit_start; - uint32_t i = 0U; - - /* firstly check that MemAddress is well 16KBytes aligned */ - if ((MemAddress % GTZC_MPCBB_SUPERBLOCK_SIZE) != 0U) - { - return HAL_ERROR; - } - - /* check entry parameters */ - if ((IS_ADDRESS_IN(SRAM1, MemAddress)) - && (IS_ADDRESS_IN(SRAM1, (MemAddress - + (NbSuperBlocks * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM1); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB1_S->CFGLOCKR1; - } - else if ((IS_ADDRESS_IN(SRAM2, MemAddress)) - && (IS_ADDRESS_IN(SRAM2, (MemAddress - + (NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM2); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB2_S->CFGLOCKR1; - } -#if defined (SRAM3_BASE) - else if ((IS_ADDRESS_IN(SRAM3, MemAddress)) - && (IS_ADDRESS_IN(SRAM3, (MemAddress - + (NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM3); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB3_S->CFGLOCKR1; - } -#endif /* SRAM3_BASE */ - else if ((IS_ADDRESS_IN(SRAM4, MemAddress)) - && (IS_ADDRESS_IN(SRAM4, (MemAddress - + (NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM4); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB4_S->CFGLOCKR1; - } -#if defined (SRAM5_BASE) - else if ((IS_ADDRESS_IN(SRAM5, MemAddress)) - && (IS_ADDRESS_IN(SRAM5, (MemAddress - + (NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM5); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB5_S->CFGLOCKR1; - } -#endif /* SRAM5_BASE */ - -#if defined (SRAM6_BASE) - else if ((IS_ADDRESS_IN(SRAM6, MemAddress)) - && (IS_ADDRESS_IN(SRAM6, (MemAddress - + (NbSuperBlocks - * GTZC_MPCBB_SUPERBLOCK_SIZE) - - 1U)))) - { - base_address = GTZC_BASE_ADDRESS(SRAM6); - reg_mpcbb = (__IO uint32_t *)>ZC_MPCBB6_S->CFGLOCKR1; - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - /* Get start coordinates of the configuration */ - superblock_start = (MemAddress - base_address) / GTZC_MPCBB_SUPERBLOCK_SIZE; - offset_bit_start = superblock_start % 32U; - - while ((i < NbSuperBlocks) && (i < 32U) && (superblock_start < 32U)) - { - pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) - >> (offset_bit_start % 32U); - offset_bit_start++; - i++; - } - -#if defined (GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk) - if ((NbSuperBlocks > 32U) || (superblock_start >= 32U)) - { - /* Point to second configuration lock register */ - reg_mpcbb++; - - /* Remaining super-blocks */ - for (; i < NbSuperBlocks; i++) - { - pLockAttributes[i] = ((*reg_mpcbb) & (1UL << (offset_bit_start % 32U))) - >> (offset_bit_start % 32U); - offset_bit_start++; - } - } -#endif /* GTZC_MPCBB_CFGLOCKR2_SPLCK32_Msk */ - - return HAL_OK; -} - -/** - * @brief Lock a MPCBB configuration on the SRAM base address passed as parameter. - * @note This functions locks the control register of the MPCBB until next reset. - * @param MemBaseAddress MPCBB identifier. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_Lock(uint32_t MemBaseAddress) -{ - /* check entry parameters */ - if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - { - SET_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } - else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) - { - SET_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#if defined (SRAM3_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - { - SET_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#endif /* SRAM3_BASE*/ - else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) - { - SET_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#if defined (SRAM5_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) - { - SET_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) - { - SET_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Get MPCBB configuration lock state on the SRAM base address passed as parameter. - * @param MemBaseAddress MPCBB identifier. - * @param pLockState pointer to Lock State (GTZC_MPCBB_LOCK_OFF or GTZC_MPCBB_LOCK_ON). - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_MPCBB_GetLock(uint32_t MemBaseAddress, - uint32_t *pLockState) -{ - /* check entry parameters */ - if (IS_GTZC_BASE_ADDRESS(SRAM1, MemBaseAddress)) - { - *pLockState = READ_BIT(GTZC_MPCBB1_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } - else if (IS_GTZC_BASE_ADDRESS(SRAM2, MemBaseAddress)) - { - *pLockState = READ_BIT(GTZC_MPCBB2_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#if defined (SRAM3_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM3, MemBaseAddress)) - { - *pLockState = READ_BIT(GTZC_MPCBB3_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#endif /* SRAM3_BASE */ - else if (IS_GTZC_BASE_ADDRESS(SRAM4, MemBaseAddress)) - { - *pLockState = READ_BIT(GTZC_MPCBB4_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#if defined (SRAM5_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM5, MemBaseAddress)) - { - *pLockState = READ_BIT(GTZC_MPCBB5_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#endif /* SRAM5_BASE */ -#if defined (SRAM6_BASE) - else if (IS_GTZC_BASE_ADDRESS(SRAM6, MemBaseAddress)) - { - *pLockState = READ_BIT(GTZC_MPCBB6_S->CR, GTZC_MPCBB_CR_GLOCK_Msk); - } -#endif /* SRAM6_BASE */ - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup GTZC_Exported_Functions_Group5 TZIC Configuration and Control functions - * @brief TZIC Configuration and Control functions - * - @verbatim - ============================================================================== - ##### TZIC Configuration and Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to configure and control TZIC - TZIC is Trust Zone Interrupt Controller -@endverbatim - * @{ - */ - -/** - * @brief Disable the interrupt associated to a single TZIC peripheral or on all peripherals. - * @param PeriphId Peripheral identifier. - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. - * Use GTZC_PERIPH_ALL to select all peripherals. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZIC_DisableIT(uint32_t PeriphId) -{ - uint32_t register_address; - - /* check entry parameters */ - if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) - { - return HAL_ERROR; - } - - if ((PeriphId & GTZC_PERIPH_ALL) != 0U) - { - /* same configuration is applied to all peripherals */ - WRITE_REG(GTZC_TZIC1->IER1, 0U); - WRITE_REG(GTZC_TZIC1->IER2, 0U); - WRITE_REG(GTZC_TZIC1->IER3, 0U); - WRITE_REG(GTZC_TZIC1->IER4, 0U); - WRITE_REG(GTZC_TZIC2->IER1, 0U); - WRITE_REG(GTZC_TZIC2->IER2, 0U); - } - else - { - /* common case where only one peripheral is configured */ - register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - CLEAR_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - - return HAL_OK; -} - -/** - * @brief Enable the interrupt associated to a single TZIC peripheral or on all peripherals. - * @param PeriphId Peripheral identifier. - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. - * Use GTZC_PERIPH_ALL to select all peripherals. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZIC_EnableIT(uint32_t PeriphId) -{ - uint32_t register_address; - - /* check entry parameters */ - if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) - { - return HAL_ERROR; - } - - if ((PeriphId & GTZC_PERIPH_ALL) != 0U) - { - /* same configuration is applied to all peripherals */ - WRITE_REG(GTZC_TZIC1->IER1, TZIC1_IER1_ALL); - WRITE_REG(GTZC_TZIC1->IER2, TZIC1_IER2_ALL); - WRITE_REG(GTZC_TZIC1->IER3, TZIC1_IER3_ALL); - WRITE_REG(GTZC_TZIC1->IER4, TZIC1_IER4_ALL); - WRITE_REG(GTZC_TZIC2->IER1, TZIC2_IER1_ALL); - WRITE_REG(GTZC_TZIC2->IER2, TZIC2_IER2_ALL); - } - else - { - /* common case where only one peripheral is configured */ - register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->IER1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - - return HAL_OK; -} - -/** - * @brief Get TZIC flag on a single TZIC peripheral or on all peripherals. - * @param PeriphId Peripheral identifier. - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. - * Use GTZC_PERIPH_ALL to select all peripherals. - * @param pFlag Pointer to the flags. - * If PeriphId target a single peripheral, pointer on a single element. - * If all peripherals selected (GTZC_PERIPH_ALL), pointer to an array - * of GTZC_TZIC_PERIPH_NUMBER elements. - * Element content is either GTZC_TZIC_NO_ILA_EVENT - * or GTZC_TZSC_ILA_EVENT_PENDING. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_GTZC_TZIC_GetFlag(uint32_t PeriphId, uint32_t *pFlag) -{ - uint32_t i; - uint32_t reg_value; - uint32_t register_address; - - /* check entry parameters */ - if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) - { - return HAL_ERROR; - } - - if ((PeriphId & GTZC_PERIPH_ALL) != 0U) - { - /* special case where it is applied to all peripherals */ - reg_value = READ_REG(GTZC_TZIC1->SR1); - for (i = 0U; i < REG_SIZE; i++) - { - pFlag[i] = (reg_value & (1UL << i)) >> i; - } - - reg_value = READ_REG(GTZC_TZIC1->SR2); - for (i = REG_SIZE; i < (2U * REG_SIZE); i++) - { - pFlag[i] = (reg_value & (1UL << (i - 32U))) >> (i - 32U); - } - - reg_value = READ_REG(GTZC_TZIC1->SR3); - for (i = 2U * REG_SIZE; i < (3U * REG_SIZE); i++) - { - pFlag[i] = (reg_value & (1UL << (i - 64U))) >> (i - 64U); - } - - reg_value = READ_REG(GTZC_TZIC1->SR4); - for (i = 3U * REG_SIZE; i < (4U * REG_SIZE); i++) - { - pFlag[i] = (reg_value & (1UL << (i - 96U))) >> (i - 96U); - } - - reg_value = READ_REG(GTZC_TZIC2->SR1); - for (i = 4U * REG_SIZE; i < (5U * REG_SIZE); i++) - { - pFlag[i] = (reg_value & (1UL << (i - 128U))) >> (i - 128U); - } - - reg_value = READ_REG(GTZC_TZIC2->SR2); - for (i = 5U * REG_SIZE; i < GTZC_TZIC_PERIPH_NUMBER; i++) - { - pFlag[i] = (reg_value & (1UL << (i - 160U))) >> (i - 160U); - } - } - else - { - /* common case where only one peripheral is concerned */ - register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->SR1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - *pFlag = READ_BIT(*(__IO uint32_t *)register_address, - 1UL << GTZC_GET_PERIPH_POS(PeriphId)) >> GTZC_GET_PERIPH_POS(PeriphId); - } - - return HAL_OK; -} - -/** - * @brief Clear TZIC flag on a single TZIC peripheral or on all peripherals. - * @param PeriphId Peripheral identifier. - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId. - * Use GTZC_PERIPH_ALL to select all peripherals. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_GTZC_TZIC_ClearFlag(uint32_t PeriphId) -{ - uint32_t register_address; - - /* check entry parameters */ - if ((HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) >= GTZC_TZIC_PERIPH_NUMBER) - || (((PeriphId & GTZC_PERIPH_ALL) != 0U) - && (HAL_GTZC_TZIC_GET_ARRAY_INDEX(PeriphId) != 0U))) - { - return HAL_ERROR; - } - - if ((PeriphId & GTZC_PERIPH_ALL) != 0U) - { - /* same configuration is applied to all peripherals */ - WRITE_REG(GTZC_TZIC1->FCR1, TZIC1_FCR1_ALL); - WRITE_REG(GTZC_TZIC1->FCR2, TZIC1_FCR2_ALL); - WRITE_REG(GTZC_TZIC1->FCR3, TZIC1_FCR3_ALL); - WRITE_REG(GTZC_TZIC1->FCR4, TZIC1_FCR4_ALL); - WRITE_REG(GTZC_TZIC2->FCR1, TZIC2_FCR1_ALL); - WRITE_REG(GTZC_TZIC2->FCR2, TZIC2_FCR2_ALL); - } - else - { - /* common case where only one peripheral is configured */ - register_address = (uint32_t) &(HAL_GTZC_TZIC_GET_INSTANCE(PeriphId)->FCR1) - + (4U * GTZC_GET_REG_INDEX_IN_INSTANCE(PeriphId)); - SET_BIT(*(__IO uint32_t *)register_address, 1UL << GTZC_GET_PERIPH_POS(PeriphId)); - } - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup GTZC_Exported_Functions_Group6 IRQ related functions - * @brief IRQ related functions - * - @verbatim - ============================================================================== - ##### TZIC IRQ Handler and Callback functions ##### - ============================================================================== - [..] - This section provides functions allowing to treat ISR and provide user callback - @endverbatim - * @{ - */ - -/** - * @brief This function handles GTZC TZIC interrupt request. - * @retval None. - */ -void HAL_GTZC_IRQHandler(void) -{ - uint32_t position; - uint32_t flag; - uint32_t ier_itsources; - uint32_t sr_flags; - - /*********************************************************************/ - /****************************** TZIC1 ******************************/ - /*********************************************************************/ - - /* Get current IT Flags and IT sources value on 1st register of TZIC1 */ - ier_itsources = READ_REG(GTZC_TZIC1_S->IER1); - sr_flags = READ_REG(GTZC_TZIC1_S->SR1); - - /* Get Mask interrupt and then clear them */ - flag = ier_itsources & sr_flags; - if (flag != 0U) - { - WRITE_REG(GTZC_TZIC1_S->FCR1, flag); - - /* Loop on flag to check, which ones have been raised */ - position = 0U; - while ((flag >> position) != 0U) - { - if ((flag & (1UL << position)) != 0U) - { - HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG1 | position); - } - - /* Position bit to be updated */ - position++; - } - } - - /* Get current IT Flags and IT sources value on 2nd register of TZIC1 */ - ier_itsources = READ_REG(GTZC_TZIC1_S->IER2); - sr_flags = READ_REG(GTZC_TZIC1_S->SR2); - - /* Get Mask interrupt and then clear them */ - flag = ier_itsources & sr_flags; - if (flag != 0U) - { - WRITE_REG(GTZC_TZIC1_S->FCR2, flag); - - /* Loop on flag to check, which ones have been raised */ - position = 0U; - while ((flag >> position) != 0U) - { - if ((flag & (1UL << position)) != 0U) - { - HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG2 | position); - } - - /* Position bit to be updated */ - position++; - } - } - - /* Get current IT Flags and IT sources value on 3rd register of TZIC1 */ - ier_itsources = READ_REG(GTZC_TZIC1_S->IER3); - sr_flags = READ_REG(GTZC_TZIC1_S->SR3); - - /* Get Mask interrupt and then clear them */ - flag = ier_itsources & sr_flags; - if (flag != 0U) - { - WRITE_REG(GTZC_TZIC1_S->FCR3, flag); - - /* Loop on flag to check, which ones have been raised */ - position = 0U; - while ((flag >> position) != 0U) - { - if ((flag & (1UL << position)) != 0U) - { - HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG3 | position); - } - - /* Position bit to be updated */ - position++; - } - } - - /* Get current IT Flags and IT sources value on 4th register of TZIC1 */ - ier_itsources = READ_REG(GTZC_TZIC1_S->IER4); - sr_flags = READ_REG(GTZC_TZIC1_S->SR4); - - /* Get Mask interrupt and then clear them */ - flag = ier_itsources & sr_flags; - if (flag != 0U) - { - WRITE_REG(GTZC_TZIC1_S->FCR4, flag); - - /* Loop on flag to check, which ones have been raised */ - position = 0U; - while ((flag >> position) != 0U) - { - if ((flag & (1UL << position)) != 0U) - { - HAL_GTZC_TZIC_Callback(GTZC1_PERIPH_REG4 | position); - } - - /* Position bit to be updated */ - position++; - } - } - - /*********************************************************************/ - /****************************** TZIC2 ******************************/ - /*********************************************************************/ - - /* Get current IT Flags and IT sources value on 1st register of TZIC2 */ - ier_itsources = READ_REG(GTZC_TZIC2_S->IER1); - sr_flags = READ_REG(GTZC_TZIC2_S->SR1); - - /* Get Mask interrupt and then clear them */ - flag = ier_itsources & sr_flags; - if (flag != 0U) - { - WRITE_REG(GTZC_TZIC2_S->FCR1, flag); - - /* Loop on flag to check, which ones have been raised */ - position = 0U; - while ((flag >> position) != 0U) - { - if ((flag & (1UL << position)) != 0U) - { - HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG1 | position); - } - - /* Position bit to be updated */ - position++; - } - } - - /* Get current IT Flags and IT sources value on 2nd register of TZIC2 */ - ier_itsources = READ_REG(GTZC_TZIC2_S->IER2); - sr_flags = READ_REG(GTZC_TZIC2_S->SR2); - - /* Get Mask interrupt and then clear them */ - flag = ier_itsources & sr_flags; - if (flag != 0U) - { - WRITE_REG(GTZC_TZIC2_S->FCR2, flag); - - /* Loop on flag to check, which ones have been raised */ - position = 0U; - while ((flag >> position) != 0U) - { - if ((flag & (1UL << position)) != 0U) - { - HAL_GTZC_TZIC_Callback(GTZC2_PERIPH_REG2 | position); - } - - /* Position bit to be updated */ - position++; - } - } -} - -/** - * @brief GTZC TZIC sub-block interrupt callback. - * @param PeriphId Peripheral identifier triggering the illegal access. - * This parameter can be a value of @ref GTZC_TZSC_TZIC_PeriphId - * @retval None. - */ -__weak void HAL_GTZC_TZIC_Callback(uint32_t PeriphId) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(PeriphId); - - /* NOTE: This function should not be modified. When the callback is needed, - * the HAL_GTZC_TZIC_Callback is to be implemented in the user file - */ -} - -/** - * @} - */ - -#endif /* defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - -/** - * @} - */ - -#endif /*HAL_GTZC_MODULE_ENABLED*/ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c deleted file mode 100644 index 31582a2dd..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c.c +++ /dev/null @@ -1,7843 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_i2c.c - * @author MCD Application Team - * @brief I2C HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Inter Integrated Circuit (I2C) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral State and Errors functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The I2C HAL driver can be used as follows: - - (#) Declare a I2C_HandleTypeDef handle structure, for example: - I2C_HandleTypeDef hi2c; - - (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API: - (##) Enable the I2Cx interface clock - (##) I2C pins configuration - (+++) Enable the clock for the I2C GPIOs - (+++) Configure I2C pins as alternate function open-drain - (##) NVIC configuration if you need to use interrupt process - (+++) Configure the I2Cx interrupt priority - (+++) Enable the NVIC I2C IRQ Channel - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for - the transmit or receive channel - (+++) Enable the DMAx interface clock using - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx channel - (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on - the DMA Tx or Rx channel - - (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode, - Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure. - - (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware - (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API. - - (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady() - - (#) For I2C IO and IO MEM operations, three operation modes are available within this driver : - - *** Polling mode IO operation *** - ================================= - [..] - (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit() - (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive() - (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit() - (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive() - - *** Polling mode IO MEM operation *** - ===================================== - [..] - (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write() - (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read() - - - *** Interrupt mode IO operation *** - =================================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - - *** Interrupt mode or DMA mode IO sequential operation *** - ========================================================== - [..] - (@) These interfaces allow to manage a sequential transfer with a repeated start condition - when a direction change during transfer - [..] - (+) A specific option field manage the different steps of a sequential transfer - (+) Option field values are defined through I2C_XFEROPTIONS and are listed below: - (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functional is same as associated interfaces in - no sequential mode - (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address - and data to transfer without a final stop condition - (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with - start condition, address and data to transfer without a final stop condition, - an then permit a call the same master sequential interface several times - (like HAL_I2C_Master_Seq_Transmit_IT() then HAL_I2C_Master_Seq_Transmit_IT() - or HAL_I2C_Master_Seq_Transmit_DMA() then HAL_I2C_Master_Seq_Transmit_DMA()) - (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to - transfer - if no direction change and without a final stop condition in both cases - (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address - and with new data to transfer if the direction change or manage only the new data to - transfer - if no direction change and with a final stop condition in both cases - (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition - after several call of the same master sequential interface several times - (link with option I2C_FIRST_AND_NEXT_FRAME). - Usage can, transfer several bytes one by one using - HAL_I2C_Master_Seq_Transmit_IT - or HAL_I2C_Master_Seq_Receive_IT - or HAL_I2C_Master_Seq_Transmit_DMA - or HAL_I2C_Master_Seq_Receive_DMA - with option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME. - Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or - Receive sequence permit to call the opposite interface Receive or Transmit - without stopping the communication and so generate a restart condition. - (++) I2C_OTHER_FRAME: Sequential usage (Master only), this option allow to manage a restart condition after - each call of the same master sequential - interface. - Usage can, transfer several bytes one by one with a restart with slave address between - each bytes using - HAL_I2C_Master_Seq_Transmit_IT - or HAL_I2C_Master_Seq_Receive_IT - or HAL_I2C_Master_Seq_Transmit_DMA - or HAL_I2C_Master_Seq_Receive_DMA - with option I2C_FIRST_FRAME then I2C_OTHER_FRAME. - Then usage of this option I2C_OTHER_AND_LAST_FRAME at the last frame to help automatic - generation of STOP condition. - - (+) Different sequential I2C interfaces are listed below: - (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using - HAL_I2C_Master_Seq_Transmit_IT() or using HAL_I2C_Master_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and - users can add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using - HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() - HAL_I2C_DisableListen_IT() - (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and users can - add their own code to check the Address Match Code and the transmission direction request by master - (Write/Read). - (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_ListenCpltCallback() - (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using - HAL_I2C_Slave_Seq_Transmit_IT() or using HAL_I2C_Slave_Seq_Transmit_DMA() - (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and - users can add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using - HAL_I2C_Slave_Seq_Receive_IT() or using HAL_I2C_Slave_Seq_Receive_DMA() - (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** Interrupt mode IO MEM operation *** - ======================================= - [..] - (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using - HAL_I2C_Mem_Write_IT() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using - HAL_I2C_Mem_Read_IT() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - - *** DMA mode IO operation *** - ============================== - [..] - (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterTxCpltCallback() - (+) Receive in master mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Master_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback() - (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Transmit_DMA() - (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback() - (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using - HAL_I2C_Slave_Receive_DMA() - (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - (+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT() - (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_AbortCpltCallback() - (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro. - This action will inform Master to generate a Stop condition to discard the communication. - - *** DMA mode IO MEM operation *** - ================================= - [..] - (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using - HAL_I2C_Mem_Write_DMA() - (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemTxCpltCallback() - (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using - HAL_I2C_Mem_Read_DMA() - (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and users can - add their own code by customization of function pointer HAL_I2C_MemRxCpltCallback() - (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can - add their own code by customization of function pointer HAL_I2C_ErrorCallback() - - - *** I2C HAL driver macros list *** - ================================== - [..] - Below the list of most used macros in I2C HAL driver. - - (+) __HAL_I2C_ENABLE: Enable the I2C peripheral - (+) __HAL_I2C_DISABLE: Disable the I2C peripheral - (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode - (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not - (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag - (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt - (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt - - *** Callback registration *** - ============================================= - [..] - The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_I2C_RegisterCallback() or HAL_I2C_RegisterAddrCallback() - to register an interrupt callback. - [..] - Function HAL_I2C_RegisterCallback() allows to register following callbacks: - (+) MasterTxCpltCallback : callback for Master transmission end of transfer. - (+) MasterRxCpltCallback : callback for Master reception end of transfer. - (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. - (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. - (+) ListenCpltCallback : callback for end of listen mode. - (+) MemTxCpltCallback : callback for Memory transmission end of transfer. - (+) MemRxCpltCallback : callback for Memory reception end of transfer. - (+) ErrorCallback : callback for error detection. - (+) AbortCpltCallback : callback for abort completion process. - (+) MspInitCallback : callback for Msp Init. - (+) MspDeInitCallback : callback for Msp DeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - For specific callback AddrCallback use dedicated register callbacks : HAL_I2C_RegisterAddrCallback(). - [..] - Use function HAL_I2C_UnRegisterCallback to reset a callback to the default - weak function. - HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) MasterTxCpltCallback : callback for Master transmission end of transfer. - (+) MasterRxCpltCallback : callback for Master reception end of transfer. - (+) SlaveTxCpltCallback : callback for Slave transmission end of transfer. - (+) SlaveRxCpltCallback : callback for Slave reception end of transfer. - (+) ListenCpltCallback : callback for end of listen mode. - (+) MemTxCpltCallback : callback for Memory transmission end of transfer. - (+) MemRxCpltCallback : callback for Memory reception end of transfer. - (+) ErrorCallback : callback for error detection. - (+) AbortCpltCallback : callback for abort completion process. - (+) MspInitCallback : callback for Msp Init. - (+) MspDeInitCallback : callback for Msp DeInit. - [..] - For callback AddrCallback use dedicated register callbacks : HAL_I2C_UnRegisterAddrCallback(). - [..] - By default, after the HAL_I2C_Init() and when the state is HAL_I2C_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_I2C_MasterTxCpltCallback(), HAL_I2C_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_I2C_Init()/ HAL_I2C_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_I2C_Init()/ HAL_I2C_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - Callbacks can be registered/unregistered in HAL_I2C_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_I2C_STATE_READY or HAL_I2C_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_I2C_RegisterCallback() before calling HAL_I2C_DeInit() - or HAL_I2C_Init() function. - [..] - When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - [..] - (@) You can refer to the I2C HAL driver header file for more useful macros - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup I2C I2C - * @brief I2C HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup I2C_Private_Define I2C Private Define - * @{ - */ -#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */ -#define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */ -#define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TC (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */ -#define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */ - -#define MAX_NBYTE_SIZE 255U -#define SLAVE_ADDR_SHIFT 7U -#define SLAVE_ADDR_MSK 0x06U - -/* Private define for @ref PreviousState usage */ -#define I2C_STATE_MSK ((uint32_t)((uint32_t)((uint32_t)HAL_I2C_STATE_BUSY_TX | \ - (uint32_t)HAL_I2C_STATE_BUSY_RX) & \ - (uint32_t)(~((uint32_t)HAL_I2C_STATE_READY)))) -/*!< Mask State define, keep only RX and TX bits */ -#define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) -/*!< Default Value */ -#define I2C_STATE_MASTER_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MASTER)) -/*!< Master Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MASTER_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MASTER)) -/*!< Master Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_SLAVE)) -/*!< Slave Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_SLAVE)) -/*!< Slave Busy RX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_TX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MEM)) -/*!< Memory Busy TX, combinaison of State LSB and Mode enum */ -#define I2C_STATE_MEM_BUSY_RX ((uint32_t)(((uint32_t)HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | \ - (uint32_t)HAL_I2C_MODE_MEM)) -/*!< Memory Busy RX, combinaison of State LSB and Mode enum */ - - -/* Private define to centralize the enable/disable of Interrupts */ -#define I2C_XFER_TX_IT (uint16_t)(0x0001U) /*!< Bit field can be combinated with - @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_RX_IT (uint16_t)(0x0002U) /*!< Bit field can be combinated with - @ref I2C_XFER_LISTEN_IT */ -#define I2C_XFER_LISTEN_IT (uint16_t)(0x8000U) /*!< Bit field can be combinated with @ref I2C_XFER_TX_IT - and @ref I2C_XFER_RX_IT */ - -#define I2C_XFER_ERROR_IT (uint16_t)(0x0010U) /*!< Bit definition to manage addition of global Error - and NACK treatment */ -#define I2C_XFER_CPLT_IT (uint16_t)(0x0020U) /*!< Bit definition to manage only STOP evenement */ -#define I2C_XFER_RELOAD_IT (uint16_t)(0x0040U) /*!< Bit definition to manage only Reload of NBYTE */ - -/* Private define Sequential Transfer Options default/reset value */ -#define I2C_NO_OPTION_FRAME (0xFFFF0000U) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup I2C_Private_Macro - * @{ - */ -#if defined(HAL_DMA_MODULE_ENABLED) -/* Macro to get remaining data to transfer on DMA side */ -#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) (__HAL_DMA_GET_COUNTER(__HANDLE__) + HAL_DMAEx_GetFifoLevel(__HANDLE__)) -#endif /* HAL_DMA_MODULE_ENABLED */ -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** @defgroup I2C_Private_Functions I2C Private Functions - * @{ - */ -#if defined(HAL_DMA_MODULE_ENABLED) -/* Private functions to handle DMA transfer */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma); -static void I2C_DMAError(DMA_HandleTypeDef *hdma); -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma); - -#endif /* HAL_DMA_MODULE_ENABLED */ - -/* Private functions to handle IT transfer */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c); -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags); -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode); - -/* Private functions to handle IT transfer */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart); - -/* Private functions for I2C transfer IRQ handler */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -#if defined(HAL_DMA_MODULE_ENABLED) -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources); -#endif /* HAL_DMA_MODULE_ENABLED */ - -/* Private functions to handle flags during polling transfer */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); -static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart); - -/* Private functions to centralize the enable/disable of Interrupts */ -static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); -static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest); - -/* Private function to treat different error callback */ -static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c); - -/* Private function to flush TXDR register */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c); - -/* Private function to handle start, restart or stop a transfer */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request); - -/* Private function to Convert Specific options */ -static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - deinitialize the I2Cx peripheral: - - (+) User must Implement HAL_I2C_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_I2C_Init() to configure the selected device with - the selected configuration: - (++) Clock Timing - (++) Own Address 1 - (++) Addressing mode (Master, Slave) - (++) Dual Addressing mode - (++) Own Address 2 - (++) Own Address 2 Mask - (++) General call mode - (++) Nostretch mode - - (+) Call the function HAL_I2C_DeInit() to restore the default configuration - of the selected I2Cx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the I2C according to the specified parameters - * in the I2C_InitTypeDef and initialize the associated handle. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1)); - assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode)); - assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode)); - assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2)); - assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks)); - assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode)); - assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode)); - - if (hi2c->State == HAL_I2C_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hi2c->Lock = HAL_UNLOCKED; - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - /* Init the I2C Callback settings */ - hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ - hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ - hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ - hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ - hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ - hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ - hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ - hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ - hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ - - if (hi2c->MspInitCallback == NULL) - { - hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - hi2c->MspInitCallback(hi2c); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ - HAL_I2C_MspInit(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /*---------------------------- I2Cx TIMINGR Configuration ------------------*/ - /* Configure I2Cx: Frequency range */ - hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK; - - /*---------------------------- I2Cx OAR1 Configuration ---------------------*/ - /* Disable Own Address1 before set the Own Address1 configuration */ - hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN; - - /* Configure I2Cx: Own Address1 and ack own address1 mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT) - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1); - } - else /* I2C_ADDRESSINGMODE_10BIT */ - { - hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1); - } - - /*---------------------------- I2Cx CR2 Configuration ----------------------*/ - /* Configure I2Cx: Addressing Master mode */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); - } - else - { - /* Clear the I2C ADD10 bit */ - CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10); - } - /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */ - hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK); - - /*---------------------------- I2Cx OAR2 Configuration ---------------------*/ - /* Disable Own Address2 before set the Own Address2 configuration */ - hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE; - - /* Configure I2Cx: Dual mode and Own Address2 */ - hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | \ - (hi2c->Init.OwnAddress2Masks << 8)); - - /*---------------------------- I2Cx CR1 Configuration ----------------------*/ - /* Configure I2Cx: Generalcall and NoStretch mode */ - hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - return HAL_OK; -} - -/** - * @brief DeInitialize the I2C peripheral. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c) -{ - /* Check the I2C handle allocation */ - if (hi2c == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the I2C Peripheral Clock */ - __HAL_I2C_DISABLE(hi2c); - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - if (hi2c->MspDeInitCallback == NULL) - { - hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - hi2c->MspDeInitCallback(hi2c); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_I2C_MspDeInit(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - hi2c->State = HAL_I2C_STATE_RESET; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Release Lock */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Initialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitialize the I2C MSP. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User I2C Callback - * To be used instead of the weak predefined callback - * @note The HAL_I2C_RegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET - * to register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID - * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID - * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID - * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID - * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID - * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID - * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID - * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_RegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID, - pI2C_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_I2C_STATE_READY == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : - hi2c->MasterTxCpltCallback = pCallback; - break; - - case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : - hi2c->MasterRxCpltCallback = pCallback; - break; - - case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : - hi2c->SlaveTxCpltCallback = pCallback; - break; - - case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : - hi2c->SlaveRxCpltCallback = pCallback; - break; - - case HAL_I2C_LISTEN_COMPLETE_CB_ID : - hi2c->ListenCpltCallback = pCallback; - break; - - case HAL_I2C_MEM_TX_COMPLETE_CB_ID : - hi2c->MemTxCpltCallback = pCallback; - break; - - case HAL_I2C_MEM_RX_COMPLETE_CB_ID : - hi2c->MemRxCpltCallback = pCallback; - break; - - case HAL_I2C_ERROR_CB_ID : - hi2c->ErrorCallback = pCallback; - break; - - case HAL_I2C_ABORT_CB_ID : - hi2c->AbortCpltCallback = pCallback; - break; - - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = pCallback; - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2C_STATE_RESET == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = pCallback; - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an I2C Callback - * I2C callback is redirected to the weak predefined callback - * @note The HAL_I2C_UnRegisterCallback() may be called before HAL_I2C_Init() in HAL_I2C_STATE_RESET - * to un-register callbacks for HAL_I2C_MSPINIT_CB_ID and HAL_I2C_MSPDEINIT_CB_ID. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * This parameter can be one of the following values: - * @arg @ref HAL_I2C_MASTER_TX_COMPLETE_CB_ID Master Tx Transfer completed callback ID - * @arg @ref HAL_I2C_MASTER_RX_COMPLETE_CB_ID Master Rx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_TX_COMPLETE_CB_ID Slave Tx Transfer completed callback ID - * @arg @ref HAL_I2C_SLAVE_RX_COMPLETE_CB_ID Slave Rx Transfer completed callback ID - * @arg @ref HAL_I2C_LISTEN_COMPLETE_CB_ID Listen Complete callback ID - * @arg @ref HAL_I2C_MEM_TX_COMPLETE_CB_ID Memory Tx Transfer callback ID - * @arg @ref HAL_I2C_MEM_RX_COMPLETE_CB_ID Memory Rx Transfer completed callback ID - * @arg @ref HAL_I2C_ERROR_CB_ID Error callback ID - * @arg @ref HAL_I2C_ABORT_CB_ID Abort callback ID - * @arg @ref HAL_I2C_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_I2C_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_UnRegisterCallback(I2C_HandleTypeDef *hi2c, HAL_I2C_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_I2C_STATE_READY == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MASTER_TX_COMPLETE_CB_ID : - hi2c->MasterTxCpltCallback = HAL_I2C_MasterTxCpltCallback; /* Legacy weak MasterTxCpltCallback */ - break; - - case HAL_I2C_MASTER_RX_COMPLETE_CB_ID : - hi2c->MasterRxCpltCallback = HAL_I2C_MasterRxCpltCallback; /* Legacy weak MasterRxCpltCallback */ - break; - - case HAL_I2C_SLAVE_TX_COMPLETE_CB_ID : - hi2c->SlaveTxCpltCallback = HAL_I2C_SlaveTxCpltCallback; /* Legacy weak SlaveTxCpltCallback */ - break; - - case HAL_I2C_SLAVE_RX_COMPLETE_CB_ID : - hi2c->SlaveRxCpltCallback = HAL_I2C_SlaveRxCpltCallback; /* Legacy weak SlaveRxCpltCallback */ - break; - - case HAL_I2C_LISTEN_COMPLETE_CB_ID : - hi2c->ListenCpltCallback = HAL_I2C_ListenCpltCallback; /* Legacy weak ListenCpltCallback */ - break; - - case HAL_I2C_MEM_TX_COMPLETE_CB_ID : - hi2c->MemTxCpltCallback = HAL_I2C_MemTxCpltCallback; /* Legacy weak MemTxCpltCallback */ - break; - - case HAL_I2C_MEM_RX_COMPLETE_CB_ID : - hi2c->MemRxCpltCallback = HAL_I2C_MemRxCpltCallback; /* Legacy weak MemRxCpltCallback */ - break; - - case HAL_I2C_ERROR_CB_ID : - hi2c->ErrorCallback = HAL_I2C_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_I2C_ABORT_CB_ID : - hi2c->AbortCpltCallback = HAL_I2C_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_I2C_STATE_RESET == hi2c->State) - { - switch (CallbackID) - { - case HAL_I2C_MSPINIT_CB_ID : - hi2c->MspInitCallback = HAL_I2C_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_I2C_MSPDEINIT_CB_ID : - hi2c->MspDeInitCallback = HAL_I2C_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register the Slave Address Match I2C Callback - * To be used instead of the weak HAL_I2C_AddrCallback() predefined callback - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pCallback pointer to the Address Match Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_RegisterAddrCallback(I2C_HandleTypeDef *hi2c, pI2C_AddrCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_I2C_STATE_READY == hi2c->State) - { - hi2c->AddrCallback = pCallback; - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief UnRegister the Slave Address Match I2C Callback - * Info Ready I2C Callback is redirected to the weak HAL_I2C_AddrCallback() predefined callback - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_UnRegisterAddrCallback(I2C_HandleTypeDef *hi2c) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_I2C_STATE_READY == hi2c->State) - { - hi2c->AddrCallback = HAL_I2C_AddrCallback; /* Legacy weak AddrCallback */ - } - else - { - /* Update the error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the I2C data - transfers. - - (#) There are two modes of transfer: - (++) Blocking mode : The communication is performed in the polling mode. - The status of all data processing is returned by the same function - after finishing transfer. - (++) No-Blocking mode : The communication is performed using Interrupts - or DMA. These functions return the status of the transfer startup. - The end of the data processing will be indicated through the - dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - - (#) Blocking mode functions are : - (++) HAL_I2C_Master_Transmit() - (++) HAL_I2C_Master_Receive() - (++) HAL_I2C_Slave_Transmit() - (++) HAL_I2C_Slave_Receive() - (++) HAL_I2C_Mem_Write() - (++) HAL_I2C_Mem_Read() - (++) HAL_I2C_IsDeviceReady() - - (#) No-Blocking mode functions with Interrupt are : - (++) HAL_I2C_Master_Transmit_IT() - (++) HAL_I2C_Master_Receive_IT() - (++) HAL_I2C_Slave_Transmit_IT() - (++) HAL_I2C_Slave_Receive_IT() - (++) HAL_I2C_Mem_Write_IT() - (++) HAL_I2C_Mem_Read_IT() - (++) HAL_I2C_Master_Seq_Transmit_IT() - (++) HAL_I2C_Master_Seq_Receive_IT() - (++) HAL_I2C_Slave_Seq_Transmit_IT() - (++) HAL_I2C_Slave_Seq_Receive_IT() - (++) HAL_I2C_EnableListen_IT() - (++) HAL_I2C_DisableListen_IT() - (++) HAL_I2C_Master_Abort_IT() - - (#) No-Blocking mode functions with DMA are : - (++) HAL_I2C_Master_Transmit_DMA() - (++) HAL_I2C_Master_Receive_DMA() - (++) HAL_I2C_Slave_Transmit_DMA() - (++) HAL_I2C_Slave_Receive_DMA() - (++) HAL_I2C_Mem_Write_DMA() - (++) HAL_I2C_Mem_Read_DMA() - (++) HAL_I2C_Master_Seq_Transmit_DMA() - (++) HAL_I2C_Master_Seq_Receive_DMA() - (++) HAL_I2C_Slave_Seq_Transmit_DMA() - (++) HAL_I2C_Slave_Seq_Receive_DMA() - - (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: - (++) HAL_I2C_MasterTxCpltCallback() - (++) HAL_I2C_MasterRxCpltCallback() - (++) HAL_I2C_SlaveTxCpltCallback() - (++) HAL_I2C_SlaveRxCpltCallback() - (++) HAL_I2C_MemTxCpltCallback() - (++) HAL_I2C_MemRxCpltCallback() - (++) HAL_I2C_AddrCallback() - (++) HAL_I2C_ListenCpltCallback() - (++) HAL_I2C_ErrorCallback() - (++) HAL_I2C_AbortCpltCallback() - -@endverbatim - * @{ - */ - -/** - * @brief Transmits in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_WRITE); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receives in master mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - } - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmits in slave mode an amount of data in blocking mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - uint16_t tmpXferCount; - HAL_StatusTypeDef error; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Preload TX data if no stretch enable */ - if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - } - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - return HAL_ERROR; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* If 10bit addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - return HAL_ERROR; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Wait until DIR flag is set Transmitter mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - return HAL_ERROR; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - } - - /* Wait until AF flag is set */ - error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart); - - if (error != HAL_OK) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - - tmpXferCount = hi2c->XferCount; - if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U)) - { - /* Reset ErrorCode to NONE */ - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - else - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - } - else - { - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear AF flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - return HAL_ERROR; - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in blocking mode - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t Timeout) -{ - uint32_t tickstart; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferISR = NULL; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Wait until ADDR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Wait until DIR flag is reset Receiver mode */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - while (hi2c->XferCount > 0U) - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Store Last receive data if any */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - return HAL_ERROR; - } - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* Wait until STOP flag is set */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Clear STOP flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Wait until BUSY flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK) - { - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - return HAL_ERROR; - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - /* Check if the Autonomous mode is enabled */ - if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_IT; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - /* Check if the Autonomous mode is enabled */ - if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_NO_START_READ); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Preload TX data if no stretch enable */ - if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Transmit in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; - - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->TXDR; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - /* Check if the Autonomous mode is enabled */ - if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, - I2C_GENERATE_NO_START_WRITE); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in master mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size) -{ - uint32_t xfermode; - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Master_ISR_DMA; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = I2C_AUTOEND_MODE; - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->RXDR; - - /* Set DMA destination address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address */ - /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - /* Check if the Autonomous mode is enabled */ - if ((hi2c->Instance->AUTOCR & I2C_AUTOCR_TRIGEN) == I2C_AUTOCR_TRIGEN) - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, - I2C_GENERATE_NO_START_READ); - } - else - { - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_READ); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - /* Preload TX data if no stretch enable */ - if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE) - { - /* Preload TX register */ - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - - if (hi2c->XferCount != 0U) - { - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; - - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->TXDR; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, - (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive in slave mode an amount of data in non-blocking mode with DMA - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->RXDR; - - /* Set DMA destination address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Write an amount of data in blocking mode to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - do - { - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - - } while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in blocking mode from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferISR = NULL; - - /* Send Slave Address and Memory Address */ - if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK) - { - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - - /* Send Slave Address */ - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, - I2C_GENERATE_START_READ); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - } - - do - { - /* Wait until RXNE flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE, - I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_NO_STARTSTOP); - } - } - } while (hi2c->XferCount > 0U); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->XferSize = 0U; - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_IT; - hi2c->Devaddress = DevAddress; - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_IT; - hi2c->Devaddress = DevAddress; - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_DMA; - hi2c->Devaddress = DevAddress; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; - - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->TXDR; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param pData Pointer to data buffer - * @param Size Amount of data to be read - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, - uint16_t MemAddSize, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_MEMADD_SIZE(MemAddSize)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MEM; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferISR = I2C_Mem_ISR_DMA; - hi2c->Devaddress = DevAddress; - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Prefetch Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - /* If Memory address size is 16Bit */ - else - { - /* Prefetch Memory Address (MSB part, LSB will be manage through interrupt) */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Prepare Memaddress buffer for LSB part */ - hi2c->Memaddress = I2C_MEM_ADD_LSB(MemAddress); - } - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->RXDR; - - /* Set DMA destination address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and Memory Address */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Checks if target device is ready for communication. - * @note This function is used with Memory devices - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param Trials Number of trials - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, - uint32_t Timeout) -{ - uint32_t tickstart; - - __IO uint32_t I2C_Trials = 0UL; - - FlagStatus tmp1; - FlagStatus tmp2; - - if (hi2c->State == HAL_I2C_STATE_READY) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET) - { - return HAL_BUSY; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - do - { - /* Generate Start */ - hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress); - - /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */ - /* Wait until STOPF flag is set or a NACK flag is set*/ - tickstart = HAL_GetTick(); - - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); - tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - - while ((tmp1 == RESET) && (tmp2 == RESET)) - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - - tmp1 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF); - tmp2 = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF); - } - - /* Check if the NACKF flag has not been set */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - /* Increment Trials */ - I2C_Trials++; - } while (I2C_Trials < Trials); - - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with DMA. - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_WRITE; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_TX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_DMA; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; - - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->TXDR; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and set NBYTES to write */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to write and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_WRITE); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, TXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_READ; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_IT; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with DMA - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, - uint16_t Size, uint32_t XferOptions) -{ - uint32_t xfermode; - uint32_t xferrequest = I2C_GENERATE_START_READ; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY_RX; - hi2c->Mode = HAL_I2C_MODE_MASTER; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Master_ISR_DMA; - - /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - xfermode = hi2c->XferOptions; - } - - /* If transfer direction not change and there is no request to start another frame, - do not generate Restart Condition */ - /* Mean Previous state is same as current state */ - if ((hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) && \ - (IS_I2C_TRANSFER_OTHER_OPTIONS_REQUEST(XferOptions) == 0)) - { - xferrequest = I2C_NO_STARTSTOP; - } - else - { - /* Convert OTHER_xxx XferOptions if any */ - I2C_ConvertOtherXferOptions(hi2c); - - /* Update xfermode accordingly if no reload is necessary */ - if (hi2c->XferCount <= MAX_NBYTE_SIZE) - { - xfermode = hi2c->XferOptions; - } - } - - if (hi2c->XferSize > 0U) - { - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->RXDR; - - /* Set DMA destination address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Send Slave Address and set NBYTES to read */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR and NACK interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - /* Update Transfer ISR function pointer */ - hi2c->XferISR = I2C_Master_ISR_IT; - - /* Send Slave Address */ - /* Set NBYTES to read and generate START condition */ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE, - I2C_GENERATE_START_READ); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, TC, STOP, NACK, RXI interrupt */ - /* possible to enable all of these */ - /* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | - I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort DMA Xfer if any */ - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with DMA - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave RX state to TX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - } - } - else - { - /* Nothing to do */ - } - - hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt; - - /* Set the DMA error callback */ - hi2c->hdmatx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmatx->XferHalfCpltCallback = NULL; - hi2c->hdmatx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; - - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->TXDR; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Reset XferSize */ - hi2c->XferSize = 0; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* Enable ERR, STOP, NACK, ADDR interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - -#if defined(HAL_DMA_MODULE_ENABLED) - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_IT; - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with DMA - * @note This interface allow to manage repeated start condition when a direction change during transfer - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param pData Pointer to data buffer - * @param Size Amount of data to be sent - * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Slave_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, - uint32_t XferOptions) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - FlagStatus tmp; - HAL_StatusTypeDef dmaxferstatus; - - /* Check the parameters */ - assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions)); - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - if ((pData == NULL) || (Size == 0U)) - { - hi2c->ErrorCode = HAL_I2C_ERROR_INVALID_PARAM; - return HAL_ERROR; - } - - /* Disable Interrupts, to prevent preemption during treatment in case of multicall */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */ - /* and then toggle the HAL slave TX state to RX state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Disable associated Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - /* Abort DMA Xfer if any */ - if (hi2c->hdmatx != NULL) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - } - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Abort DMA Xfer if any */ - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - } - } - else - { - /* Nothing to do */ - } - - hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN; - hi2c->Mode = HAL_I2C_MODE_SLAVE; - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - - /* Enable Address Acknowledge */ - hi2c->Instance->CR2 &= ~I2C_CR2_NACK; - - /* Prepare transfer parameters */ - hi2c->pBuffPtr = pData; - hi2c->XferCount = Size; - hi2c->XferSize = hi2c->XferCount; - hi2c->XferOptions = XferOptions; - hi2c->XferISR = I2C_Slave_ISR_DMA; - - if (hi2c->hdmarx != NULL) - { - /* Set the I2C DMA transfer complete callback */ - hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt; - - /* Set the DMA error callback */ - hi2c->hdmarx->XferErrorCallback = I2C_DMAError; - - /* Set the unused DMA callbacks to NULL */ - hi2c->hdmarx->XferHalfCpltCallback = NULL; - hi2c->hdmarx->XferAbortCallback = NULL; - - /* Enable the DMA channel */ - if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] \ - = (uint32_t)&hi2c->Instance->RXDR; - - /* Set DMA destination address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, - hi2c->XferSize); - } - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA_PARAM; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - if (dmaxferstatus == HAL_OK) - { - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Reset XferSize */ - hi2c->XferSize = 0; - } - else - { - /* Update I2C state */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Update I2C error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_DMA; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - - tmp = __HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR); - if ((I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT) && (tmp != RESET)) - { - /* Clear ADDR flag after prepare the transfer parameters */ - /* This action will generate an acknowledge to the Master */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Enable DMA Request */ - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - /* REnable ADDR interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Enable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - - /* Enable the Address Match interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable the Address listen mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c) -{ - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp; - - /* Disable Address listen mode only if a transfer is not ongoing */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK; - hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode); - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Disable the Address Match interrupt */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Abort a master or memory I2C IT or DMA process communication with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress) -{ - HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode; - - if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM)) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - /* Disable Interrupts and Store Previous state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - } - else - { - /* Do nothing */ - } - - /* Set State at HAL_I2C_STATE_ABORT */ - hi2c->State = HAL_I2C_STATE_ABORT; - - /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */ - /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */ - I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Note : The I2C interrupts must be enabled after unlocking current process - to avoid the risk of I2C interrupt handle execution before current - process unlock */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - return HAL_OK; - } - else - { - /* Wrong usage of abort function */ - /* This function should be used only in case of abort monitored by master device */ - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks - * @{ - */ - -/** - * @brief This function handles I2C event interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Get current IT Flags and IT sources value */ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - - /* I2C events treatment -------------------------------------*/ - if (hi2c->XferISR != NULL) - { - hi2c->XferISR(hi2c, itflags, itsources); - } -} - -/** - * @brief This function handles I2C error interrupt request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c) -{ - uint32_t itflags = READ_REG(hi2c->Instance->ISR); - uint32_t itsources = READ_REG(hi2c->Instance->CR1); - uint32_t tmperror; - - /* I2C Bus error interrupt occurred ------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_BERR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - } - - /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_OVR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - } - - /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/ - if ((I2C_CHECK_FLAG(itflags, I2C_FLAG_ARLO) != RESET) && \ - (I2C_CHECK_IT_SOURCE(itsources, I2C_IT_ERRI) != RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - } - - /* Store current volatile hi2c->ErrorCode, misra rule */ - tmperror = hi2c->ErrorCode; - - /* Call the Error Callback in case of Error detected */ - if ((tmperror & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE) - { - I2C_ITError(hi2c, tmperror); - } -} - -/** - * @brief Master Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Master Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MasterRxCpltCallback could be implemented in the user file - */ -} - -/** @brief Slave Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Slave Address Match callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION - * @param AddrMatchCode Address Match Code - * @retval None - */ -__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - UNUSED(TransferDirection); - UNUSED(AddrMatchCode); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AddrCallback() could be implemented in the user file - */ -} - -/** - * @brief Listen Complete callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ListenCpltCallback() could be implemented in the user file - */ -} - -/** - * @brief Memory Tx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemTxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Memory Rx Transfer completed callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_MemRxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief I2C error callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief I2C abort callback. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval None - */ -__weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hi2c); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_I2C_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions - * @brief Peripheral State, Mode and Error functions - * -@verbatim - =============================================================================== - ##### Peripheral State, Mode and Error functions ##### - =============================================================================== - [..] - This subsection permit to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the I2C handle state. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval HAL state - */ -HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c) -{ - /* Return I2C handle state */ - return hi2c->State; -} - -/** - * @brief Returns the I2C Master, Slave, Memory or no mode. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for I2C module - * @retval HAL mode - */ -HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c) -{ - return hi2c->Mode; -} - -/** - * @brief Return the I2C error code. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @retval I2C Error Code - */ -uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c) -{ - return hi2c->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup I2C_Private_Functions - * @{ - */ - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint16_t devaddress; - uint32_t tmpITFlags = ITFlags; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) - { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, - hi2c->XferOptions, I2C_NO_STARTSTOP); - } - else - { - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else - { - /* Nothing to do */ - } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, tmpITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t direction = I2C_GENERATE_START_WRITE; - uint32_t tmpITFlags = ITFlags; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - /* No need to generate STOP, it is automatically done */ - /* Error callback will be send during stop flag treatment */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) - { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - if (hi2c->Memaddress == 0xFFFFFFFFU) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - else - { - /* Write LSB part of Memory Address */ - hi2c->Instance->TXDR = hi2c->Memaddress; - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U)) - { - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable Interrupt related to address step */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT); - - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - direction = I2C_GENERATE_START_READ; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, direction); - } - else - { - hi2c->XferSize = hi2c->XferCount; - - /* Set NBYTES to write and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, direction); - } - } - else - { - /* Nothing to do */ - } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, tmpITFlags); - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t tmpoptions = hi2c->XferOptions; - uint32_t tmpITFlags = ITFlags; - - /* Process locked */ - __HAL_LOCK(hi2c); - - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, tmpITFlags); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_RXI) != RESET)) - { - if (hi2c->XferCount > 0U) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferSize--; - hi2c->XferCount--; - } - - if ((hi2c->XferCount == 0U) && \ - (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_ADDR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, tmpITFlags); - } - else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - /* Write data to TXDR only if XferCount not reach "0" */ - /* A TXIS flag can be set, during STOP treatment */ - /* Check if all Data have already been sent */ - /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */ - if (hi2c->XferCount > 0U) - { - /* Write data to TXDR */ - hi2c->Instance->TXDR = *hi2c->pBuffPtr; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - hi2c->XferCount--; - hi2c->XferSize--; - } - else - { - if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) - { - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - } - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint16_t devaddress; - uint32_t xfermode; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable TC interrupt */ - __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI); - - if (hi2c->XferCount != 0U) - { - /* Recover Slave address */ - devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD); - - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - xfermode = I2C_RELOAD_MODE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - xfermode = hi2c->XferOptions; - } - else - { - xfermode = I2C_AUTOEND_MODE; - } - } - - /* Set the new XferSize in Nbytes register */ - I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, xfermode, I2C_NO_STARTSTOP); - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Call TxCpltCallback() if no stop mode is set */ - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - if (hi2c->XferCount == 0U) - { - if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE) - { - /* Generate a stop condition in case of no transfer option */ - if (hi2c->XferOptions == I2C_NO_OPTION_FRAME) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - } - else - { - /* Call I2C Master Sequential complete process */ - I2C_ITMasterSeqCplt(hi2c); - } - } - } - else - { - /* Wrong size Status regarding TC flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Memory Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t direction = I2C_GENERATE_START_WRITE; - - /* Process Locked */ - __HAL_LOCK(hi2c); - - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set corresponding Error Code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* No need to generate STOP, it is automatically done */ - /* But enable STOP interrupt, to treat it */ - /* Error callback will be send during stop flag treatment */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TXIS) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)) - { - /* Write LSB part of Memory Address */ - hi2c->Instance->TXDR = hi2c->Memaddress; - - /* Reset Memaddress content */ - hi2c->Memaddress = 0xFFFFFFFFU; - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable Interrupt related to address step */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Enable only Error interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - if (hi2c->XferCount != 0U) - { - /* Prepare the new XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, I2C_NO_STARTSTOP); - } - else - { - hi2c->XferSize = hi2c->XferCount; - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, I2C_NO_STARTSTOP); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else - { - /* Wrong size Status regarding TCR flag event */ - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET)) - { - /* Disable Interrupt related to address step */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Enable only Error and NACK interrupt for data transfer */ - I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT); - - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - direction = I2C_GENERATE_START_READ; - } - - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - - /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_RELOAD_MODE, direction); - } - else - { - hi2c->XferSize = hi2c->XferCount; - - /* Set NBYTES to write and generate RESTART */ - I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize, - I2C_AUTOEND_MODE, direction); - } - - /* Update XferCount value */ - hi2c->XferCount -= hi2c->XferSize; - - /* Enable DMA Request */ - if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN; - } - else - { - hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN; - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Master complete process */ - I2C_ITMasterCplt(hi2c, ITFlags); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} - -/** - * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param ITFlags Interrupt flags to handle. - * @param ITSources Interrupt sources enabled. - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, - uint32_t ITSources) -{ - uint32_t tmpoptions = hi2c->XferOptions; - uint32_t treatdmanack = 0U; - HAL_I2C_StateTypeDef tmpstate; - - /* Process locked */ - __HAL_LOCK(hi2c); - - /* Check if STOPF is set */ - if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET)) - { - /* Call I2C Slave complete process */ - I2C_ITSlaveCplt(hi2c, ITFlags); - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0 */ - /* So clear Flag NACKF only */ - if ((I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) || - (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET)) - { - /* Split check of hdmarx, for MISRA compliance */ - if (hi2c->hdmarx != NULL) - { - if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_RXDMAEN) != RESET) - { - if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) - { - treatdmanack = 1U; - } - } - } - - /* Split check of hdmatx, for MISRA compliance */ - if (hi2c->hdmatx != NULL) - { - if (I2C_CHECK_IT_SOURCE(ITSources, I2C_CR1_TXDMAEN) != RESET) - { - if (I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx) == 0U) - { - treatdmanack = 1U; - } - } - } - - if (treatdmanack == 1U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, ITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - /* Store current hi2c->State, solve MISRA2012-Rule-13.5 */ - tmpstate = hi2c->State; - - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - } - else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - } - else - { - /* Do nothing */ - } - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } - } - else - { - /* Only Clear NACK Flag, no DMA treatment is pending */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_ADDR) != RESET) && \ - (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_ADDRI) != RESET)) - { - I2C_ITAddrCplt(hi2c, ITFlags); - } - else - { - /* Nothing to do */ - } - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Master sends target device address followed by internal memory address for write request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TCR flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Master sends target device address followed by internal memory address for read request. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param DevAddress Target device address: The device 7 bits address value - * in datasheet must be shifted to the left before calling the interface - * @param MemAddress Internal memory address - * @param MemAddSize Size of internal memory address - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, - uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, - uint32_t Tickstart) -{ - I2C_TransferConfig(hi2c, DevAddress, (uint8_t)MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* If Memory address size is 8Bit */ - if (MemAddSize == I2C_MEMADD_SIZE_8BIT) - { - /* Send Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - /* If Memory address size is 16Bit */ - else - { - /* Send MSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress); - - /* Wait until TXIS flag is set */ - if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Send LSB of Memory Address */ - hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress); - } - - /* Wait until TC flag is set */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief I2C Address complete process callback. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint8_t transferdirection; - uint16_t slaveaddrcode; - uint16_t ownadd1code; - uint16_t ownadd2code; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(ITFlags); - - /* In case of Listen state, need to inform upper layer of address match code event */ - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) == (uint32_t)HAL_I2C_STATE_LISTEN) - { - transferdirection = I2C_GET_DIR(hi2c); - slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c); - ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c); - ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c); - - /* If 10bits addressing mode is selected */ - if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT) - { - if ((slaveaddrcode & SLAVE_ADDR_MSK) == ((ownadd1code >> SLAVE_ADDR_SHIFT) & SLAVE_ADDR_MSK)) - { - slaveaddrcode = ownadd1code; - hi2c->AddrEventCount++; - if (hi2c->AddrEventCount == 2U) - { - /* Reset Address Event counter */ - hi2c->AddrEventCount = 0U; - - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); -#else - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - else - { - slaveaddrcode = ownadd2code; - - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); -#else - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - /* else 7 bits addressing mode is selected */ - else - { - /* Disable ADDR Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call Slave Addr callback */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AddrCallback(hi2c, transferdirection, slaveaddrcode); -#else - HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - /* Else clear address flag only */ - else - { - /* Clear ADDR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } -} - -/** - * @brief I2C Master sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c) -{ - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* No Generate Stop, to permit restart mode */ - /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); -#else - HAL_I2C_MasterTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - hi2c->XferISR = NULL; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterRxCpltCallback(hi2c); -#else - HAL_I2C_MasterRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } -} - -/** - * @brief I2C Slave sequential complete process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ITSlaveSeqCplt(I2C_HandleTypeDef *hi2c) -{ - uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); - - /* Reset I2C handle mode */ - hi2c->Mode = HAL_I2C_MODE_NONE; - -#if defined(HAL_DMA_MODULE_ENABLED) - /* If a DMA is ongoing, Update handle size context */ - if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - } - else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - } - else - { - /* Do nothing */ - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveTxCpltCallback(hi2c); -#else - HAL_I2C_SlaveTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN) - { - /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - - /* Disable Interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveRxCpltCallback(hi2c); -#else - HAL_I2C_SlaveRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief I2C Master complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint32_t tmperror; - uint32_t tmpITFlags = ITFlags; - __IO uint32_t tmpreg; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Disable Interrupts and Store Previous state */ - if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX; - } - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX; - } - else - { - /* Do nothing */ - } - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Reset handle parameters */ - hi2c->XferISR = NULL; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - - if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set acknowledge error code */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Fetch Last receive data if any */ - if ((hi2c->State == HAL_I2C_STATE_ABORT) && (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET)) - { - /* Read data from RXDR */ - tmpreg = (uint8_t)hi2c->Instance->RXDR; - UNUSED(tmpreg); - } - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Store current volatile hi2c->ErrorCode, misra rule */ - tmperror = hi2c->ErrorCode; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - if ((hi2c->State == HAL_I2C_STATE_ABORT) || (tmperror != HAL_I2C_ERROR_NONE)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - /* hi2c->State == HAL_I2C_STATE_BUSY_TX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_TX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MemTxCpltCallback(hi2c); -#else - HAL_I2C_MemTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterTxCpltCallback(hi2c); -#else - HAL_I2C_MasterTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - /* hi2c->State == HAL_I2C_STATE_BUSY_RX */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - if (hi2c->Mode == HAL_I2C_MODE_MEM) - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MemRxCpltCallback(hi2c); -#else - HAL_I2C_MemRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->MasterRxCpltCallback(hi2c); -#else - HAL_I2C_MasterRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief I2C Slave complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1); - uint32_t tmpITFlags = ITFlags; - uint32_t tmpoptions = hi2c->XferOptions; - HAL_I2C_StateTypeDef tmpstate = hi2c->State; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Disable Interrupts and Store Previous state */ - if ((tmpstate == HAL_I2C_STATE_BUSY_TX) || (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN)) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT); - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX; - } - else if ((tmpstate == HAL_I2C_STATE_BUSY_RX) || (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX; - } - else if (tmpstate == HAL_I2C_STATE_LISTEN) - { - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT); - hi2c->PreviousState = I2C_STATE_NONE; - } - else - { - /* Do nothing */ - } - - /* Disable Address Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - -#if defined(HAL_DMA_MODULE_ENABLED) - /* If a DMA is ongoing, Update handle size context */ - if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_TXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - if (hi2c->hdmatx != NULL) - { - hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmatx); - } - } - else if (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_CR1_RXDMAEN) != RESET) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - if (hi2c->hdmarx != NULL) - { - hi2c->XferCount = (uint16_t)I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx); - } - } - else - { - /* Do nothing */ - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* Store Last receive data if any */ - if (I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_RXNE) != RESET) - { - /* Remove RXNE flag on temporary variable as read done */ - tmpITFlags &= ~I2C_FLAG_RXNE; - - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - } - } - - /* All data are not transferred, so set error code accordingly */ - if (hi2c->XferCount != 0U) - { - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \ - (I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET)) - { - /* Check that I2C transfer finished */ - /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */ - /* Mean XferCount == 0*/ - /* So clear Flag NACKF only */ - if (hi2c->XferCount == 0U) - { - if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME)) - /* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for - Warning[Pa134]: left and right operands are identical */ - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - } - } - else - { - /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - - if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME)) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - } - } - } - - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, hi2c->ErrorCode); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ - if (hi2c->State == HAL_I2C_STATE_LISTEN) - { - /* Call I2C Listen complete process */ - I2C_ITListenCplt(hi2c, tmpITFlags); - } - } - else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME) - { - /* Call the Sequential Complete callback, to inform upper layer of the end of Transfer */ - I2C_ITSlaveSeqCplt(hi2c); - - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ListenCpltCallback(hi2c); -#else - HAL_I2C_ListenCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - /* Call the corresponding callback to inform upper layer of End of Transfer */ - else if (hi2c->State == HAL_I2C_STATE_BUSY_RX) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveRxCpltCallback(hi2c); -#else - HAL_I2C_SlaveRxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->SlaveTxCpltCallback(hi2c); -#else - HAL_I2C_SlaveTxCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } -} - -/** - * @brief I2C Listen complete process. - * @param hi2c I2C handle. - * @param ITFlags Interrupt flags to handle. - * @retval None - */ -static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) -{ - /* Reset handle parameters */ - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->PreviousState = I2C_STATE_NONE; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferISR = NULL; - - /* Store Last receive data if any */ - if (I2C_CHECK_FLAG(ITFlags, I2C_FLAG_RXNE) != RESET) - { - /* Read data from RXDR */ - *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; - - /* Increment Buffer pointer */ - hi2c->pBuffPtr++; - - if ((hi2c->XferSize > 0U)) - { - hi2c->XferSize--; - hi2c->XferCount--; - - /* Set ErrorCode corresponding to a Non-Acknowledge */ - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - } - - /* Disable all Interrupts*/ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Clear NACK Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ListenCpltCallback(hi2c); -#else - HAL_I2C_ListenCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ -} - -/** - * @brief I2C interrupts error process. - * @param hi2c I2C handle. - * @param ErrorCode Error code to handle. - * @retval None - */ -static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) -{ - HAL_I2C_StateTypeDef tmpstate = hi2c->State; - -#if defined(HAL_DMA_MODULE_ENABLED) - uint32_t tmppreviousstate; -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* Reset handle parameters */ - hi2c->Mode = HAL_I2C_MODE_NONE; - hi2c->XferOptions = I2C_NO_OPTION_FRAME; - hi2c->XferCount = 0U; - - /* Set new error code */ - hi2c->ErrorCode |= ErrorCode; - - /* Disable Interrupts */ - if ((tmpstate == HAL_I2C_STATE_LISTEN) || - (tmpstate == HAL_I2C_STATE_BUSY_TX_LISTEN) || - (tmpstate == HAL_I2C_STATE_BUSY_RX_LISTEN)) - { - /* Disable all interrupts, except interrupts related to LISTEN state */ - I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* keep HAL_I2C_STATE_LISTEN if set */ - hi2c->State = HAL_I2C_STATE_LISTEN; - hi2c->XferISR = I2C_Slave_ISR_IT; - } - else - { - /* Disable all interrupts */ - I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* If state is an abort treatment on going, don't change state */ - /* This change will be do later */ - if (hi2c->State != HAL_I2C_STATE_ABORT) - { - /* Set HAL_I2C_STATE_READY */ - hi2c->State = HAL_I2C_STATE_READY; - - /* Check if a STOPF is detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) - { - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - } - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - } - hi2c->XferISR = NULL; - } - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort DMA TX transfer if any */ - tmppreviousstate = hi2c->PreviousState; - - if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \ - (tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX))) - { - if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - } - - if (HAL_DMA_GetState(hi2c->hdmatx) != HAL_DMA_STATE_READY) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK) - { - /* Call Directly XferAbortCallback function in case of error */ - hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx); - } - } - else - { - I2C_TreatErrorCallback(hi2c); - } - } - /* Abort DMA RX transfer if any */ - else if ((hi2c->hdmarx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_RX) || \ - (tmppreviousstate == I2C_STATE_SLAVE_BUSY_RX))) - { - if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN) - { - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - } - - if (HAL_DMA_GetState(hi2c->hdmarx) != HAL_DMA_STATE_READY) - { - /* Set the I2C DMA Abort callback : - will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */ - hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK) - { - /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */ - hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx); - } - } - else - { - I2C_TreatErrorCallback(hi2c); - } - } - else -#endif /* HAL_DMA_MODULE_ENABLED */ - { - I2C_TreatErrorCallback(hi2c); - } -} - -/** - * @brief I2C Error callback treatment. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_TreatErrorCallback(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_ABORT) - { - hi2c->State = HAL_I2C_STATE_READY; - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->AbortCpltCallback(hi2c); -#else - HAL_I2C_AbortCpltCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } - else - { - hi2c->PreviousState = I2C_STATE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - /* Call the corresponding callback to inform upper layer of End of Transfer */ -#if (USE_HAL_I2C_REGISTER_CALLBACKS == 1) - hi2c->ErrorCallback(hi2c); -#else - HAL_I2C_ErrorCallback(hi2c); -#endif /* USE_HAL_I2C_REGISTER_CALLBACKS */ - } -} - -/** - * @brief I2C Tx data register flush process. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c) -{ - /* If a pending TXIS flag is set */ - /* Write a dummy data in TXDR to clear it */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET) - { - hi2c->Instance->TXDR = 0x00U; - } - - /* Flush TX register if not empty */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE); - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief DMA I2C master transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef dmaxferstatus = HAL_OK; - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - if ((hi2c->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; - - /* Set DMA destination address */ - hi2c->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->TXDR; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmatx); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, - hi2c->XferSize); - } - - if (dmaxferstatus != HAL_OK) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } - else - { - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } - } -} - - -/** - * @brief DMA I2C slave transmit process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - uint32_t tmpoptions = hi2c->XferOptions; - - if ((tmpoptions == I2C_NEXT_FRAME) || (tmpoptions == I2C_FIRST_FRAME)) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN; - - /* Last Byte is Transmitted */ - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ - } -} - - -/** - * @brief DMA I2C master receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma) -{ - HAL_StatusTypeDef dmaxferstatus = HAL_OK; - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* If last transfer, enable STOP interrupt */ - if (hi2c->XferCount == 0U) - { - /* Enable STOP interrupt */ - I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT); - } - /* else prepare a new DMA transfer and enable TCReload interrupt */ - else - { - /* Update Buffer pointer */ - hi2c->pBuffPtr += hi2c->XferSize; - - /* Set the XferSize to transfer */ - if (hi2c->XferCount > MAX_NBYTE_SIZE) - { - hi2c->XferSize = MAX_NBYTE_SIZE; - } - else - { - hi2c->XferSize = hi2c->XferCount; - } - - /* Enable the DMA channel */ - if ((hi2c->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hi2c->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hi2c->XferSize; - - /* Set DMA source address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hi2c->Instance->RXDR; - - /* Set DMA destination address */ - hi2c->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hi2c->pBuffPtr; - - dmaxferstatus = HAL_DMAEx_List_Start_IT(hi2c->hdmarx); - } - else - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } - } - else - { - dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, - hi2c->XferSize); - } - - if (dmaxferstatus != HAL_OK) - { - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); - } - else - { - /* Enable TC interrupts */ - I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT); - } - } -} - - -/** - * @brief DMA I2C slave receive process complete callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - uint32_t tmpoptions = hi2c->XferOptions; - - if ((I2C_GET_DMA_REMAIN_DATA(hi2c->hdmarx) == 0U) && \ - (tmpoptions != I2C_NO_OPTION_FRAME)) - { - /* Disable DMA Request */ - hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN; - - /* Call I2C Slave Sequential complete process */ - I2C_ITSlaveSeqCplt(hi2c); - } - else - { - /* No specific action, Master fully manage the generation of STOP condition */ - /* Mean that this generation can arrive at any time, at the end or during DMA process */ - /* So STOP condition should be manage through Interrupt treatment */ - } -} - - -/** - * @brief DMA I2C communication error callback. - * @param hdma DMA handle - * @retval None - */ -static void I2C_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Disable Acknowledge */ - hi2c->Instance->CR2 |= I2C_CR2_NACK; - - /* Call the corresponding callback to inform upper layer of End of Transfer */ - I2C_ITError(hi2c, HAL_I2C_ERROR_DMA); -} - - -/** - * @brief DMA I2C communication abort callback - * (To be called at end of DMA Abort procedure). - * @param hdma DMA handle. - * @retval None - */ -static void I2C_DMAAbort(DMA_HandleTypeDef *hdma) -{ - /* Derogation MISRAC2012-Rule-11.5 */ - I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); - - /* Reset AbortCpltCallback */ - if (hi2c->hdmatx != NULL) - { - hi2c->hdmatx->XferAbortCallback = NULL; - } - if (hi2c->hdmarx != NULL) - { - hi2c->hdmarx->XferAbortCallback = NULL; - } - - I2C_TreatErrorCallback(hi2c); -} - -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief This function handles I2C Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Flag Specifies the I2C flag to check. - * @param Status The actual Flag status (SET or RESET). - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of STOP flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart) -{ - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - return HAL_ERROR; - } - - /* Check for the Timeout */ - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_ERROR; - } - } - } - return HAL_OK; -} - -/** - * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, - uint32_t Tickstart) -{ - HAL_StatusTypeDef status = HAL_OK; - - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK)) - { - /* Check if an error is detected */ - if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK) - { - status = HAL_ERROR; - } - - /* Check if a STOPF is detected */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK)) - { - /* Check if an RXNE is pending */ - /* Store Last receive data if any */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U)) - { - /* Return HAL_OK */ - /* The Reading of data from RXDR will be done in caller function */ - status = HAL_OK; - } - - /* Check a no-acknowledge have been detected */ - if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) - { - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - hi2c->ErrorCode = HAL_I2C_ERROR_AF; - - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - status = HAL_ERROR; - } - else - { - hi2c->ErrorCode = HAL_I2C_ERROR_NONE; - } - } - - /* Check for the Timeout */ - if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) - { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) - { - hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - status = HAL_ERROR; - } - } - } - return status; -} - -/** - * @brief This function handles errors detection during an I2C Communication. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param Timeout Timeout duration - * @param Tickstart Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t itflag = hi2c->Instance->ISR; - uint32_t error_code = 0; - uint32_t tickstart = Tickstart; - uint32_t tmp1; - HAL_I2C_ModeTypeDef tmp2; - - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_AF)) - { - /* Clear NACKF Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - - /* Wait until STOP Flag is set or timeout occurred */ - /* AutoEnd should be initiate after AF */ - while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (status == HAL_OK)) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - tmp1 = (uint32_t)(hi2c->Instance->CR2 & I2C_CR2_STOP); - tmp2 = hi2c->Mode; - - /* In case of I2C still busy, try to regenerate a STOP manually */ - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) != RESET) && \ - (tmp1 != I2C_CR2_STOP) && \ - (tmp2 != HAL_I2C_MODE_SLAVE)) - { - /* Generate Stop */ - hi2c->Instance->CR2 |= I2C_CR2_STOP; - - /* Update Tick with new reference */ - tickstart = HAL_GetTick(); - } - - while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) - { - /* Check for the Timeout */ - if ((HAL_GetTick() - tickstart) > I2C_TIMEOUT_STOPF) - { - error_code |= HAL_I2C_ERROR_TIMEOUT; - - status = HAL_ERROR; - - break; - } - } - } - } - } - - /* In case STOP Flag is detected, clear it */ - if (status == HAL_OK) - { - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - } - - error_code |= HAL_I2C_ERROR_AF; - - status = HAL_ERROR; - } - - /* Refresh Content of Status register */ - itflag = hi2c->Instance->ISR; - - /* Then verify if an additional errors occurs */ - /* Check if a Bus error occurred */ - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_BERR)) - { - error_code |= HAL_I2C_ERROR_BERR; - - /* Clear BERR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR); - - status = HAL_ERROR; - } - - /* Check if an Over-Run/Under-Run error occurred */ - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_OVR)) - { - error_code |= HAL_I2C_ERROR_OVR; - - /* Clear OVR flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR); - - status = HAL_ERROR; - } - - /* Check if an Arbitration Loss error occurred */ - if (HAL_IS_BIT_SET(itflag, I2C_FLAG_ARLO)) - { - error_code |= HAL_I2C_ERROR_ARLO; - - /* Clear ARLO flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO); - - status = HAL_ERROR; - } - - if (status != HAL_OK) - { - /* Flush TX register */ - I2C_Flush_TXDR(hi2c); - - /* Clear Configuration Register 2 */ - I2C_RESET_CR2(hi2c); - - hi2c->ErrorCode |= error_code; - hi2c->State = HAL_I2C_STATE_READY; - hi2c->Mode = HAL_I2C_MODE_NONE; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - } - - return status; -} - -/** - * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). - * @param hi2c I2C handle. - * @param DevAddress Specifies the slave address to be programmed. - * @param Size Specifies the number of bytes to be programmed. - * This parameter must be a value between 0 and 255. - * @param Mode New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_RELOAD_MODE Enable Reload mode . - * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode. - * @arg @ref I2C_SOFTEND_MODE Enable Software end mode. - * @param Request New state of the I2C START condition generation. - * This parameter can be one of the following values: - * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition. - * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0). - * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request. - * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request. - * @retval None - */ -static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, - uint32_t Request) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_TRANSFER_MODE(Mode)); - assert_param(IS_TRANSFER_REQUEST(Request)); - - /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); - - /* update CR2 register */ - MODIFY_REG(hi2c->Instance->CR2, \ - ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | \ - (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | \ - I2C_CR2_START | I2C_CR2_STOP)), tmp); -} - -/** - * @brief Manage the enabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval None - */ -static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - -#if defined(HAL_DMA_MODULE_ENABLED) - if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \ - (hi2c->XferISR != I2C_Slave_ISR_DMA) && \ - (hi2c->XferISR != I2C_Mem_ISR_DMA)) -#endif /* HAL_DMA_MODULE_ENABLED */ - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if (InterruptRequest == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if (InterruptRequest == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - } - -#if defined(HAL_DMA_MODULE_ENABLED) - else - { - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Enable ERR, STOP, NACK and ADDR interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Enable ERR, TC, STOP, NACK and TXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI; - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Enable ERR, TC, STOP, NACK and RXI interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI; - } - - if (InterruptRequest == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if (InterruptRequest == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI); - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* Enable interrupts only at the end */ - /* to avoid the risk of I2C interrupt handle execution before */ - /* all interrupts requested done */ - __HAL_I2C_ENABLE_IT(hi2c, tmpisr); -} - -/** - * @brief Manage the disabling of Interrupts. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2C. - * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition. - * @retval None - */ -static void I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest) -{ - uint32_t tmpisr = 0U; - - if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT) - { - /* Disable TC and TXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_TXI; - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT) - { - /* Disable TC and RXI interrupts */ - tmpisr |= I2C_IT_TCI | I2C_IT_RXI; - - if (((uint32_t)hi2c->State & (uint32_t)HAL_I2C_STATE_LISTEN) != (uint32_t)HAL_I2C_STATE_LISTEN) - { - /* Disable NACK and STOP interrupts */ - tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - } - - if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT) - { - /* Disable ADDR, NACK and STOP interrupts */ - tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI; - } - - if (InterruptRequest == I2C_XFER_ERROR_IT) - { - /* Enable ERR and NACK interrupts */ - tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI; - } - - if (InterruptRequest == I2C_XFER_CPLT_IT) - { - /* Enable STOP interrupts */ - tmpisr |= I2C_IT_STOPI; - } - - if (InterruptRequest == I2C_XFER_RELOAD_IT) - { - /* Enable TC interrupts */ - tmpisr |= I2C_IT_TCI; - } - - /* Disable interrupts only at the end */ - /* to avoid a breaking situation like at "t" time */ - /* all disable interrupts request are not done */ - __HAL_I2C_DISABLE_IT(hi2c, tmpisr); -} - -/** - * @brief Convert I2Cx OTHER_xxx XferOptions to functional XferOptions. - * @param hi2c I2C handle. - * @retval None - */ -static void I2C_ConvertOtherXferOptions(I2C_HandleTypeDef *hi2c) -{ - /* if user set XferOptions to I2C_OTHER_FRAME */ - /* it request implicitly to generate a restart condition */ - /* set XferOptions to I2C_FIRST_FRAME */ - if (hi2c->XferOptions == I2C_OTHER_FRAME) - { - hi2c->XferOptions = I2C_FIRST_FRAME; - } - /* else if user set XferOptions to I2C_OTHER_AND_LAST_FRAME */ - /* it request implicitly to generate a restart condition */ - /* then generate a stop condition at the end of transfer */ - /* set XferOptions to I2C_FIRST_AND_LAST_FRAME */ - else if (hi2c->XferOptions == I2C_OTHER_AND_LAST_FRAME) - { - hi2c->XferOptions = I2C_FIRST_AND_LAST_FRAME; - } - else - { - /* Nothing to do */ - } -} - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c deleted file mode 100644 index ef1b495c3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_i2c_ex.c +++ /dev/null @@ -1,502 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_i2c_ex.c - * @author MCD Application Team - * @brief I2C Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of I2C Extended peripheral: - * + Filter Mode Functions - * + WakeUp Mode Functions - * + FastModePlus Functions - * + Autonomous Mode Functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### I2C peripheral Extended features ##### - ============================================================================== - - [..] Comparing to other previous devices, the I2C interface for STM32U5xx - devices contains the following additional features - - (+) Possibility to disable or enable Analog Noise Filter - (+) Use of a configured Digital Noise Filter - (+) Disable or enable wakeup from Stop mode(s) - (+) Disable or enable Fast Mode Plus - (+) Configure Autonomous mode - - ##### How to use this driver ##### - ============================================================================== - [..] This driver provides functions to configure Noise Filter and Wake Up Feature - (#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter() - (#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter() - (#) Configure the enable or disable of I2C Wake Up Mode using the functions : - (++) HAL_I2CEx_EnableWakeUp() - (++) HAL_I2CEx_DisableWakeUp() - (#) Configure the enable or disable of fast mode plus driving capability using the functions : - (++) HAL_I2CEx_ConfigFastModePlus() - (#) Set or get or clear the autonomous mode configuration using these functions : - (++) HAL_I2CEx_SetConfigAutonomousMode() - (++) HAL_I2CEx_GetConfigAutonomousMode() - (++) HAL_I2CEx_ClearConfigAutonomousMode() - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup I2CEx I2CEx - * @brief I2C Extended HAL module driver - * @{ - */ - -#ifdef HAL_I2C_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** @defgroup I2CEx_Exported_Functions I2C Extended Exported Functions - * @{ - */ - -/** @defgroup I2CEx_Exported_Functions_Group1 Filter Mode Functions - * @brief Filter Mode Functions - * -@verbatim - =============================================================================== - ##### Filter Mode Functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Noise Filters - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Analog noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter New state of the Analog filter. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Reset I2Cx ANOFF bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF); - - /* Set analog filter bit*/ - hi2c->Instance->CR1 |= AnalogFilter; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Configure I2C Digital noise filter. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter) -{ - uint32_t tmpreg; - - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Get the old register value */ - tmpreg = hi2c->Instance->CR1; - - /* Reset I2Cx DNF bits [11:8] */ - tmpreg &= ~(I2C_CR1_DNF); - - /* Set I2Cx DNF coefficient */ - tmpreg |= DigitalFilter << 8U; - - /* Store the new register value */ - hi2c->Instance->CR1 = tmpreg; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @} - */ - -/** @defgroup I2CEx_Exported_Functions_Group2 WakeUp Mode Functions - * @brief WakeUp Mode Functions - * -@verbatim - =============================================================================== - ##### WakeUp Mode Functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Wake Up Feature - -@endverbatim - * @{ - */ - -/** - * @brief Enable I2C wakeup from Stop mode(s). - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_EnableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 |= I2C_CR1_WUPEN; - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Disable I2C wakeup from Stop mode(s). - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_DisableWakeUp(I2C_HandleTypeDef *hi2c) -{ - /* Check the parameters */ - assert_param(IS_I2C_WAKEUP_FROMSTOP_INSTANCE(hi2c->Instance)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - /* Enable wakeup from stop mode */ - hi2c->Instance->CR1 &= ~(I2C_CR1_WUPEN); - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @} - */ - -/** @defgroup I2CEx_Exported_Functions_Group3 Fast Mode Plus Functions - * @brief Fast Mode Plus Functions - * -@verbatim - =============================================================================== - ##### Fast Mode Plus Functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Fast Mode Plus - -@endverbatim - * @{ - */ - -/** - * @brief Configure I2C Fast Mode Plus. - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param FastModePlus New state of the Fast Mode Plus. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ConfigFastModePlus(I2C_HandleTypeDef *hi2c, uint32_t FastModePlus) -{ - /* Check the parameters */ - assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_FASTMODEPLUS(FastModePlus)); - - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Disable the selected I2C peripheral */ - __HAL_I2C_DISABLE(hi2c); - - if (FastModePlus == I2C_FASTMODEPLUS_ENABLE) - { - /* Set I2Cx FMP bit */ - hi2c->Instance->CR1 |= (I2C_CR1_FMP); - } - else - { - /* Reset I2Cx FMP bit */ - hi2c->Instance->CR1 &= ~(I2C_CR1_FMP); - } - - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @} - */ - -/** @defgroup I2CEx_Exported_Functions_Group4 Autonomous Mode Functions - * @brief Autonomous Mode Functions - * -@verbatim - =============================================================================== - ##### Autonomous Mode functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure Autonomous Mode - -@endverbatim - * @{ - */ - -/** - * @brief Set Autonomous Mode configuration - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains - * the configuration information of the autonomous mode for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_SetConfigAutonomousMode(I2C_HandleTypeDef *hi2c, - const I2C_AutonomousModeConfTypeDef *sConfig) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); - assert_param(IS_I2C_TRIG_SOURCE(hi2c->Instance, sConfig->TriggerSelection)); - assert_param(IS_I2C_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); - - /* Disable the selected I2C peripheral to be able to configure AUTOCR */ - __HAL_I2C_DISABLE(hi2c); - - /* I2Cx AUTOCR Configuration */ - WRITE_REG(hi2c->Instance->AUTOCR, - (sConfig->TriggerState | \ - ((sConfig->TriggerSelection) & I2C_AUTOCR_TRIGSEL_Msk) | \ - sConfig->TriggerPolarity)); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Get Autonomous Mode configuration - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @param sConfig Pointer to a I2C_AutonomousModeConfTypeDef structure that contains - * the configuration information of the autonomous mode for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_GetConfigAutonomousMode(const I2C_HandleTypeDef *hi2c, - I2C_AutonomousModeConfTypeDef *sConfig) -{ - uint32_t autocr_tmp; - - /* Check the parameters */ - assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); - - autocr_tmp = hi2c->Instance->AUTOCR; - - sConfig->TriggerState = (autocr_tmp & I2C_AUTOCR_TRIGEN); - if (IS_I2C_GRP2_INSTANCE(hi2c->Instance)) - { - sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP2); - } - else - { - sConfig->TriggerSelection = ((autocr_tmp & I2C_AUTOCR_TRIGSEL) | I2C_TRIG_GRP1); - } - sConfig->TriggerPolarity = (autocr_tmp & I2C_AUTOCR_TRIGPOL); - - return HAL_OK; -} - -/** - * @brief Clear Autonomous Mode configuration - * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains - * the configuration information for the specified I2Cx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_I2CEx_ClearConfigAutonomousMode(I2C_HandleTypeDef *hi2c) -{ - if (hi2c->State == HAL_I2C_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hi2c); - - hi2c->State = HAL_I2C_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_I2C_TRIG_INPUT_INSTANCE(hi2c->Instance)); - - /* Disable the selected I2C peripheral to be able to clear AUTOCR */ - __HAL_I2C_DISABLE(hi2c); - - CLEAR_REG(hi2c->Instance->AUTOCR); - - /* Enable the selected I2C peripheral */ - __HAL_I2C_ENABLE(hi2c); - - hi2c->State = HAL_I2C_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_I2C_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c deleted file mode 100644 index f0741fcce..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_icache.c +++ /dev/null @@ -1,651 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_icache.c - * @author MCD Application Team - * @brief ICACHE HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Instruction Cache (ICACHE). - * + Initialization and Configuration - * + Invalidate functions - * + Monitoring management - * + Memory address remap management - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### ICACHE main features ##### - ============================================================================== - [..] - The Instruction Cache (ICACHE) is introduced on C-AHB code bus of - Cortex-M33 processor to improve performance when fetching instruction - and data from both internal and external memories. It allows close to - zero wait states performance. - - (+) The ICACHE provides two performance counters (Hit and Miss), - cache invalidate maintenance operation, error management and TrustZone - security support. - - (+) The ICACHE provides additionally the possibility to remap input address - falling into up to four memory regions (used to remap aliased code in - external memories to the internal Code region, for execution) - - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The ICACHE HAL driver can be used as follows: - - (#) Optionally configure the Instruction Cache mode with - HAL_ICACHE_ConfigAssociativityMode() if the default configuration - does not suit the application requirements. - - (#) Enable and disable the Instruction Cache with respectively - HAL_ICACHE_Enable() and HAL_ICACHE_Disable(). - Use HAL_ICACHE_IsEnabled() to get the Instruction Cache status. - To ensure a deterministic cache behavior after power on, system reset or after - a call to @ref HAL_ICACHE_Disable(), the application must call - @ref HAL_ICACHE_WaitForInvalidateComplete(). Indeed on power on, system reset - or cache disable, an automatic cache invalidation procedure is launched and the - cache is bypassed until the operation completes. - - (#) Initiate the cache maintenance invalidation procedure with either - HAL_ICACHE_Invalidate() (blocking mode) or HAL_ICACHE_Invalidate_IT() - (interrupt mode). When interrupt mode is used, the callback function - HAL_ICACHE_InvalidateCompleteCallback() is called when the invalidate - procedure is complete. The function HAL_ICACHE_WaitForInvalidateComplete() - may be called to wait for the end of the invalidate procedure automatically - initiated when disabling the Instruction Cache with HAL_ICACHE_Disable(). - The cache operation is bypassed during the invalidation procedure. - - (#) Use the performance monitoring counters for Hit and Miss with the following - functions: HAL_ICACHE_Monitor_Start(), HAL_ICACHE_Monitor_Stop(), - HAL_ICACHE_Monitor_Reset(), HAL_ICACHE_Monitor_GetHitValue() and - HAL_ICACHE_Monitor_GetMissValue() - - (#) Enable and disable up to four regions to remap input address from external - memories to the internal Code region for execution with - HAL_ICACHE_EnableRemapRegion() and HAL_ICACHE_DisableRemapRegion() - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup ICACHE ICACHE - * @brief HAL ICACHE module driver - * @{ - */ -#if defined(ICACHE) && defined (HAL_ICACHE_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup ICACHE_Private_Constants ICACHE Private Constants - * @{ - */ -#define ICACHE_INVALIDATE_TIMEOUT_VALUE 1U /* 1ms */ -#define ICACHE_DISABLE_TIMEOUT_VALUE 1U /* 1ms */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ICACHE_Private_Macros ICACHE Private Macros - * @{ - */ - -#define IS_ICACHE_ASSOCIATIVITY_MODE(__MODE__) (((__MODE__) == ICACHE_1WAY) || \ - ((__MODE__) == ICACHE_2WAYS)) - -#define IS_ICACHE_MONITOR_TYPE(__TYPE__) (((__TYPE__) == ICACHE_MONITOR_HIT_MISS) || \ - ((__TYPE__) == ICACHE_MONITOR_HIT) || \ - ((__TYPE__) == ICACHE_MONITOR_MISS)) - -#define IS_ICACHE_REGION_NUMBER(__NUMBER__) ((__NUMBER__) < 4U) - -#define IS_ICACHE_REGION_SIZE(__SIZE__) (((__SIZE__) == ICACHE_REGIONSIZE_2MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_4MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_8MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_16MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_32MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_64MB) || \ - ((__SIZE__) == ICACHE_REGIONSIZE_128MB)) - -#define IS_ICACHE_REGION_TRAFFIC_ROUTE(__TRAFFICROUTE__) (((__TRAFFICROUTE__) == ICACHE_MASTER1_PORT) || \ - ((__TRAFFICROUTE__) == ICACHE_MASTER2_PORT)) - -#define IS_ICACHE_REGION_OUTPUT_BURST_TYPE(__OUTPUTBURSTTYPE_) (((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_WRAP) || \ - ((__OUTPUTBURSTTYPE_) == ICACHE_OUTPUT_BURST_INCR)) - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ICACHE_Exported_Functions ICACHE Exported Functions - * @{ - */ - -/** @defgroup ICACHE_Exported_Functions_Group1 Initialization and control functions - * @brief Initialization and control functions - * - @verbatim - ============================================================================== - ##### Initialization and control functions ##### - ============================================================================== - [..] - This section provides functions allowing to initialize and control the - Instruction Cache (mode, invalidate procedure, performance counters). - @endverbatim - * @{ - */ - -/** - * @brief Configure the Instruction Cache cache associativity mode selection. - * @param AssociativityMode Associativity mode selection - * This parameter can be one of the following values: - * @arg ICACHE_1WAY 1-way cache (direct mapped cache) - * @arg ICACHE_2WAYS 2-ways set associative cache (default) - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_ConfigAssociativityMode(uint32_t AssociativityMode) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_ICACHE_ASSOCIATIVITY_MODE(AssociativityMode)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - MODIFY_REG(ICACHE->CR, ICACHE_CR_WAYSEL, AssociativityMode); - } - - return status; -} - -/** - * @brief DeInitialize the Instruction Cache. - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_DeInit(void) -{ - /* Reset interrupt enable value */ - WRITE_REG(ICACHE->IER, 0U); - - /* Clear any pending flags */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF | ICACHE_FCR_CERRF); - - /* Disable cache then set default associative mode value */ - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); - WRITE_REG(ICACHE->CR, ICACHE_CR_WAYSEL); - - /* Stop monitor and reset monitor values */ - CLEAR_BIT(ICACHE->CR, ICACHE_MONITOR_HIT_MISS); - SET_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - CLEAR_BIT(ICACHE->CR, (ICACHE_MONITOR_HIT_MISS << 2U)); - - /* Reset regions configuration values */ - WRITE_REG(ICACHE->CRR0, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR1, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR2, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - WRITE_REG(ICACHE->CRR3, ICACHE_REGIONSIZE_2MB << ICACHE_CRRx_RSIZE_Pos); - - return HAL_OK; -} - -/** - * @brief Enable the Instruction Cache. - * @note This function always returns HAL_OK even if there is any ongoing - * cache operation. The Instruction Cache is bypassed until the - * cache operation completes. - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Enable(void) -{ - SET_BIT(ICACHE->CR, ICACHE_CR_EN); - - return HAL_OK; -} - -/** - * @brief Disable the Instruction Cache. - * @note This function waits for the cache being disabled but - * not for the end of the automatic cache invalidation procedure. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_Disable(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Make sure BSYENDF is reset before to disable the instruction cache */ - /* as it automatically starts a cache invalidation procedure */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - CLEAR_BIT(ICACHE->CR, ICACHE_CR_EN); - - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for instruction cache being disabled */ - while (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - if ((HAL_GetTick() - tickstart) > ICACHE_DISABLE_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_TIMEOUT; - break; - } - } - } - - return status; -} - -/** - * @brief Check whether the Instruction Cache is enabled or not. - * @retval Status (0: disabled, 1: enabled) - */ -uint32_t HAL_ICACHE_IsEnabled(void) -{ - return ((READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) ? 1UL : 0UL); -} - -/** - * @brief Invalidate the Instruction Cache. - * @note This function waits for the end of cache invalidation procedure - * and clears the associated BSYENDF flag. - * @retval HAL status (HAL_OK/HAL_ERROR/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate(void) -{ - HAL_StatusTypeDef status; - - /* Check if no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) == 0U) - { - /* Launch cache invalidation */ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - } - - status = HAL_ICACHE_WaitForInvalidateComplete(); - - return status; -} - -/** - * @brief Invalidate the Instruction Cache with interrupt. - * @note This function launches cache invalidation and returns. - * User application shall resort to interrupt generation to check - * the end of the cache invalidation with the BSYENDF flag and the - * HAL_ICACHE_InvalidateCompleteCallback() callback. - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_Invalidate_IT(void) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check no ongoing operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Make sure BSYENDF is reset before to start cache invalidation */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - /* Enable end of cache invalidation interrupt */ - SET_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - - /* Launch cache invalidation */ - SET_BIT(ICACHE->CR, ICACHE_CR_CACHEINV); - } - - return status; -} - -/** - * @brief Wait for the end of the Instruction Cache invalidate procedure. - * @note This function checks and clears the BSYENDF flag when set. - * @retval HAL status (HAL_OK/HAL_TIMEOUT) - */ -HAL_StatusTypeDef HAL_ICACHE_WaitForInvalidateComplete(void) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Check if ongoing invalidation operation */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BUSYF) != 0U) - { - /* Get tick */ - tickstart = HAL_GetTick(); - - /* Wait for end of cache invalidation */ - while (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) - { - if ((HAL_GetTick() - tickstart) > ICACHE_INVALIDATE_TIMEOUT_VALUE) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(ICACHE->SR, ICACHE_SR_BSYENDF) == 0U) - { - status = HAL_TIMEOUT; - break; - } - } - } - } - - /* Clear BSYENDF */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - return status; -} - - -/** - * @brief Start the Instruction Cache performance monitoring. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Start(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - SET_BIT(ICACHE->CR, MonitorType); - - return HAL_OK; -} - -/** - * @brief Stop the Instruction Cache performance monitoring. - * @note Stopping the monitoring does not reset the values. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Stop(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - CLEAR_BIT(ICACHE->CR, MonitorType); - - return HAL_OK; -} - -/** - * @brief Reset the Instruction Cache performance monitoring values. - * @param MonitorType Monitoring type - * This parameter can be one of the following values: - * @arg ICACHE_MONITOR_HIT_MISS Hit & Miss monitoring - * @arg ICACHE_MONITOR_HIT Hit monitoring - * @arg ICACHE_MONITOR_MISS Miss monitoring - * @retval HAL status (HAL_OK) - */ -HAL_StatusTypeDef HAL_ICACHE_Monitor_Reset(uint32_t MonitorType) -{ - /* Check the parameters */ - assert_param(IS_ICACHE_MONITOR_TYPE(MonitorType)); - - /* Force/Release reset */ - SET_BIT(ICACHE->CR, (MonitorType << 2U)); - CLEAR_BIT(ICACHE->CR, (MonitorType << 2U)); - - return HAL_OK; -} - -/** - * @brief Get the Instruction Cache performance Hit monitoring value. - * @note Upon reaching the 32-bit maximum value, monitor does not wrap. - * @retval Hit monitoring value - */ -uint32_t HAL_ICACHE_Monitor_GetHitValue(void) -{ - return (ICACHE->HMONR); -} - -/** - * @brief Get the Instruction Cache performance Miss monitoring value. - * @note Upon reaching the 32-bit maximum value, monitor does not wrap. - * @retval Miss monitoring value - */ -uint32_t HAL_ICACHE_Monitor_GetMissValue(void) -{ - return (ICACHE->MMONR); -} - -/** - * @} - */ - -/** @defgroup ICACHE_Exported_Functions_Group2 IRQ and callback functions - * @brief IRQ and callback functions - * - @verbatim - ============================================================================== - ##### IRQ and callback functions ##### - ============================================================================== - [..] - This section provides functions allowing to handle ICACHE global interrupt - and the associated callback functions. - @endverbatim - * @{ - */ - -/** - * @brief Handle the Instruction Cache interrupt request. - * @note This function should be called under the ICACHE_IRQHandler(). - * @note This function respectively disables the interrupt and clears the - * flag of any pending flag before calling the associated user callback. - * @retval None - */ -void HAL_ICACHE_IRQHandler(void) -{ - /* Get current interrupt flags and interrupt sources value */ - uint32_t itflags = READ_REG(ICACHE->SR); - uint32_t itsources = READ_REG(ICACHE->IER); - - /* Check Instruction cache Error interrupt flag */ - if (((itflags & itsources) & ICACHE_FLAG_ERROR) != 0U) - { - /* Disable error interrupt */ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_ERRIE); - - /* Clear ERR pending flag */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CERRF); - - /* Instruction cache error interrupt user callback */ - HAL_ICACHE_ErrorCallback(); - } - - /* Check Instruction cache BusyEnd interrupt flag */ - if (((itflags & itsources) & ICACHE_FLAG_BUSYEND) != 0U) - { - /* Disable end of cache invalidation interrupt */ - CLEAR_BIT(ICACHE->IER, ICACHE_IER_BSYENDIE); - - /* Clear BSYENDF pending flag */ - WRITE_REG(ICACHE->FCR, ICACHE_FCR_CBSYENDF); - - /* Instruction cache busyend interrupt user callback */ - HAL_ICACHE_InvalidateCompleteCallback(); - } -} - -/** - * @brief Cache invalidation complete callback. - */ -__weak void HAL_ICACHE_InvalidateCompleteCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_ICACHE_InvalidateCompleteCallback() should be implemented in the user file - */ -} - -/** - * @brief Error callback. - */ -__weak void HAL_ICACHE_ErrorCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_ICACHE_ErrorCallback() should be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup ICACHE_Exported_Functions_Group3 Memory remapped regions functions - * @brief Memory remapped regions functions - * - @verbatim - ============================================================================== - ##### Memory remapped regions functions ##### - ============================================================================== - [..] - This section provides functions allowing to manage the remapping of - external memories to internal Code for execution. - @endverbatim - * @{ - */ - -/** - * @brief Configure and enable a region for memory remapping. - * @note The Instruction Cache and the region must be disabled. - * @param Region Region number - This parameter can be a value of @arg @ref ICACHE_Region - * @param pRegionConfig Pointer to structure of ICACHE region configuration parameters - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_EnableRemapRegion(uint32_t Region, const ICACHE_RegionConfigTypeDef *const pRegionConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *p_reg; - uint32_t value; - - /* Check the parameters */ - assert_param(IS_ICACHE_REGION_NUMBER(Region)); - assert_param(IS_ICACHE_REGION_SIZE(pRegionConfig->Size)); - assert_param(IS_ICACHE_REGION_TRAFFIC_ROUTE(pRegionConfig->TrafficRoute)); - assert_param(IS_ICACHE_REGION_OUTPUT_BURST_TYPE(pRegionConfig->OutputBurstType)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Get region control register address */ - p_reg = &(ICACHE->CRR0) + (1U * Region); - - /* Check region is not already enabled */ - if ((*p_reg & ICACHE_CRRx_REN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Region 2MB: BaseAddress size 8 bits, RemapAddress size 11 bits */ - /* Region 4MB: BaseAddress size 7 bits, RemapAddress size 10 bits */ - /* Region 8MB: BaseAddress size 6 bits, RemapAddress size 9 bits */ - /* Region 16MB: BaseAddress size 5 bits, RemapAddress size 8 bits */ - /* Region 32MB: BaseAddress size 4 bits, RemapAddress size 7 bits */ - /* Region 64MB: BaseAddress size 3 bits, RemapAddress size 6 bits */ - /* Region 128MB: BaseAddress size 2 bits, RemapAddress size 5 bits */ - value = ((pRegionConfig->BaseAddress & 0x1FFFFFFFU) >> 21U) & \ - (0xFFU & ~(pRegionConfig->Size - 1U)); - value |= ((pRegionConfig->RemapAddress >> 5U) & \ - ((uint32_t)(0x7FFU & ~(pRegionConfig->Size - 1U)) << ICACHE_CRRx_REMAPADDR_Pos)); - value |= (pRegionConfig->Size << ICACHE_CRRx_RSIZE_Pos) | pRegionConfig->TrafficRoute | \ - pRegionConfig->OutputBurstType; - *p_reg = (value | ICACHE_CRRx_REN); - } - } - - return status; -} - -/** - * @brief Disable the memory remapping for a predefined region. - * @param Region Region number - This parameter can be a value of @arg @ref ICACHE_Region - * @retval HAL status (HAL_OK/HAL_ERROR) - */ -HAL_StatusTypeDef HAL_ICACHE_DisableRemapRegion(uint32_t Region) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *p_reg; - - /* Check the parameters */ - assert_param(IS_ICACHE_REGION_NUMBER(Region)); - - /* Check cache is not enabled */ - if (READ_BIT(ICACHE->CR, ICACHE_CR_EN) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Get region control register address */ - p_reg = &(ICACHE->CRR0) + (1U * Region); - - *p_reg &= ~ICACHE_CRRx_REN; - } - - return status; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ICACHE && HAL_ICACHE_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c deleted file mode 100644 index cca779f42..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_mdf.c +++ /dev/null @@ -1,3593 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_mdf.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Multi-function Digital Filter (MDF) - * peripheral: - * + Initialization and de-initialization - * + Acquisition - * + Clock absence detection - * + Short circuit detection - * + Out-off limit detection - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - *** Initialization and de-initialization *** - ============================================ - [..] - (#) User has first to initialize MDF or ADF instance. - (#) As prerequisite, fill in the HAL_MDF_MspInit() : - (++) Enable MDFz or ADFz clock interface with __HAL_RCC_MDFz_CLK_ENABLE() - or __HAL_RCC_ADFz_CLK_ENABLE(). - (++) Enable the clocks for the used GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (++) Configure these pins in alternate mode using HAL_GPIO_Init(). - (++) If interrupt mode is used, enable and configure MDFz_FLTx or ADFz - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (++) If DMA mode is used, initialize and configure DMA. - (#) Configure the common parameters (only for first MDF or ADF instance init), - serial interface parameters and filter bitstream selection by calling - HAL_MDF_Init() function. - - [..] - (#) User can de-initialize MDF or ADF instance with HAL_MDF_DeInit() function. - - *** Acquisition *** - =================== - [..] - (#) Configure filter parameters and start acquisition using HAL_MDF_AcqStart(), - HAL_MDF_AcqStart_IT() or HAL_MDF_AcqStart_DMA(). - (#) In polling mode : - (++) Use HAL_MDF_PollForAcq() to detect the end of acquisition. - Use HAL_MDF_GetAcqValue to get acquisition value. - (++) Only for MDF instance, use HAL_MDF_PollForSnapshotAcq() to detect - the end of snapshot acquisition. - Use HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value. - (++) Only for ADF instance, use HAL_MDF_PollForSndLvl() to detect and get - new sound level value and ambient noise value. - (++) Only for ADF instance, use HAL_MDF_PollForSad() to detect sound activity. - (#) In interrupt mode : - (++) HAL_MDF_AcqCpltCallback() will be called at the end of acquisition. - Use HAL_MDF_GetAcqValue to get acquisition value or use - HAL_MDF_GetSnapshotAcqValue to get snapshot acquisition value. - (++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new - sound level and ambient noise values are available. - (++) Only for ADF instance, HAL_MDF_SadCallback() will be called when - sound activity detection occurs. - (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun or - saturation occurs. - Use HAL_MDF_GetErrorCode() to get the corresponding error. - (#) In DMA mode : - (++) HAL_MDF_AcqHalfCpltCallback() and HAL_MDF_AcqCpltCallback() will be called - respectively at the half acquisition and at the acquisition complete. - (++) Only for ADF instance, HAL_MDF_SndLvlCallback() will be called when new - sound level and ambient noise values are available. - (++) Only for ADF instance, HAL_MDF_SadCallback() will be called when - sound activity detection occurs. - (++) HAL_MDF_ErrorCallback() will be called if overflow, filter overrun, - saturation or DMA error occurs. - Use HAL_MDF_GetErrorCode() to get the corresponding error. - (#) Use HAL_MDF_GenerateTrgo() to generate pulse on TRGO signal. - (#) During acquisition, use HAL_MDF_SetDelay() and HAL_MDF_GetDelay() to respectively - set and get the delay on data source. - (#) During acquisition, use HAL_MDF_SetGain() and HAL_MDF_GetGain() to respectively - set and get the filter gain. - (#) During acquisition, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset() to respectively - set and get the filter offset error compensation. - (#) During acquisition, only for MDF instance, use HAL_MDF_SetOffset() and HAL_MDF_GetOffset() - to respectively set and get the filter offset error compensation. - (#) Stop acquisition using HAL_MDF_AcqStop(), HAL_MDF_AcqStop_IT() or HAL_MDF_AcqStop_DMA(). - - *** Clock absence detection *** - =============================== - [..] - (#) Clock absence detection is always enabled so no need to start clock absence detection - in polling mode. - Use HAL_MDF_CkabStart_IT() to start clock absence detection in interrupt mode. - (#) In polling mode, use HAL_MDF_PollForCkab() to detect the clock absence. - (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if clock absence detection - occurs. - Use HAL_MDF_GetErrorCode() to get the corresponding error. - (#) Stop clock absence detection in interrupt mode using HAL_MDF_CkabStop_IT(). - - *** Short circuit detection *** - =============================== - [..] - (#) Only for MDF instance, start short circuit detection using HAL_MDF_ScdStart() - or HAL_MDF_ScdStart_IT(). - (#) In polling mode, use HAL_MDF_PollForScd() to detect short circuit. - (#) In interrupt mode, HAL_MDF_ErrorCallback() will be called if short circuit detection - occurs. - Use HAL_MDF_GetErrorCode() to get the corresponding error. - (#) Stop short circuit detection using HAL_MDF_ScdStop() or HAL_MDF_ScdStop_IT(). - - *** Out-off limit detection *** - =============================== - [..] - (#) Only for MDF instance, start out-off limit detection using HAL_MDF_OldStart() - or HAL_MDF_OldStart_IT(). - (#) In polling mode, use HAL_MDF_PollForOld() to detect out-off limit and to get threshold - information. - (#) In interrupt mode, HAL_MDF_OldCallback() will be called if out-off limit detection occurs. - (#) Stop out-off limit detection using HAL_MDF_OldStop() or HAL_MDF_OldStop_IT(). - - *** generic functions *** - ========================= - [..] - (#) HAL_MDF_IRQHandler will be called when MDF or ADF interrupt occurs. - (#) HAL_MDF_ErrorCallback will be called when MDF or ADF error occurs. - (#) Use HAL_MDF_GetState() to get the current MDF or ADF instance state. - (#) Use HAL_MDF_GetErrorCode() to get the current MDF or ADF instance error code. - - *** Callback registration *** - ============================= - [..] - The compilation define USE_HAL_MDF_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - Use functions HAL_MDF_RegisterCallback(), HAL_MDF_RegisterOldCallback() - or HAL_MDF_RegisterSndLvlCallback() to register a user callback. - - [..] - Function HAL_MDF_RegisterCallback() allows to register following callbacks : - (+) AcqCpltCallback : Acquisition complete callback. - (+) AcqHalfCpltCallback : Acquisition half complete callback. - (+) SadCallback : Sound activity detection callback (only for ADF instance). - (+) ErrorCallback : Error callback. - (+) MspInitCallback : MSP init callback. - (+) MspDeInitCallback : MSP de-init callback. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - For MDF instance and for specific out-off limit detection callback use dedicated - register callback : - HAL_MDF_RegisterOldCallback(). - - [..] - For ADF instance and for specific sound level callback use dedicated register callback : - HAL_MDF_RegisterSndLvlCallback(). - - [..] - Use function HAL_MDF_UnRegisterCallback() to reset a callback to the default weak function. - - [..] - HAL_MDF_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. - [..] - This function allows to reset following callbacks : - (+) AcqCpltCallback : Acquisition complete callback. - (+) AcqHalfCpltCallback : Acquisition half complete callback. - (+) SadCallback : Sound activity detection callback (only for ADF instance). - (+) ErrorCallback : Error callback. - (+) MspInitCallback : MSP init callback. - (+) MspDeInitCallback : MSP de-init callback. - - [..] - For MDF instance and for specific out-off limit detection callback use dedicated - unregister callback : - HAL_MDF_UnRegisterOldCallback(). - - [..] - For ADF instance and for specific sound level callback use dedicated unregister callback : - HAL_MDF_UnRegisterSndLvlCallback(). - - [..] - By default, after the call of init function and if the state is RESET - all callbacks are reset to the corresponding legacy weak functions : - examples HAL_MDF_AcqCpltCallback(), HAL_MDF_ErrorCallback(). - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak functions in the init and de-init only when these - callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the init and de-init keep and use - the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the init/de-init. - In that case first register the MspInit/MspDeInit user callbacks using - HAL_MDF_RegisterCallback() before calling init or de-init function. - - [..] - When the compilation define USE_HAL_MDF_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak callbacks are used. - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup MDF MDF - * @brief MDF HAL module driver - * @{ - */ - -#ifdef HAL_MDF_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/** @defgroup MDF_Private_Typedefs MDF Private Typedefs - * @{ - */ -/** - * @} - */ - -/* Private define ------------------------------------------------------------*/ -/** @defgroup MDF_Private_Constants MDF Private Constants - * @{ - */ -#if defined(STM32U535xx) || defined(STM32U545xx) -#define MDF_INSTANCE_NUMBER 3U /* 2 instances for MDF1 and 1 instance for ADF1 */ -#else /* defined(STM32U535xx) || defined(STM32U545xx) */ -#define MDF_INSTANCE_NUMBER 7U /* 6 instances for MDF1 and 1 instance for ADF1 */ -#endif /* defined(STM32U535xx) || defined(STM32U545xx) */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup MDF_Private_Variables MDF Private Variables - * @{ - */ -static uint32_t v_mdf1InstanceCounter = 0U; -static uint32_t v_adf1InstanceCounter = 0U; -static MDF_HandleTypeDef *a_mdfHandle[MDF_INSTANCE_NUMBER] = {NULL}; -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup MDF_Private_Functions MDF Private Functions - * @{ - */ -static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance); -static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig); -static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma); -static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma); -static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ -/** @defgroup MDF_Exported_Functions MDF Exported Functions - * @{ - */ - -/** @defgroup MDF_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and de-initialization functions - * -@verbatim - ============================================================================== - ##### Initialization and de-initialization functions ##### - ============================================================================== - [..] This section provides functions allowing to : - (+) Initialize the MDF or ADF instance. - (+) De-initialize the MDF or ADF instance. - (+) Register and unregister callbacks. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the MDF instance according to the specified parameters - * in the MDF_InitTypeDef structure and initialize the associated handle. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_Init(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check MDF handle */ - if (hmdf == NULL) - { - status = HAL_ERROR; - } - else - { - /* Check parameters */ - assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); - assert_param(IS_MDF_FILTER_BITSTREAM(hmdf->Init.FilterBistream)); - assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.SerialInterface.Activation)); - - /* Check that instance has not been already initialized */ - if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] != NULL) - { - status = HAL_ERROR; - } - else - { -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - /* Reset callback pointers to the weak predefined callbacks */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - hmdf->OldCallback = NULL; - hmdf->SndLvCallback = HAL_MDF_SndLvlCallback; - hmdf->SadCallback = HAL_MDF_SadCallback; - } - else /* MDF instance */ - { - hmdf->OldCallback = HAL_MDF_OldCallback; - hmdf->SndLvCallback = NULL; - hmdf->SadCallback = NULL; - } - hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback; - hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback; - hmdf->ErrorCallback = HAL_MDF_ErrorCallback; - - /* Call MDF MSP init function */ - if (hmdf->MspInitCallback == NULL) - { - hmdf->MspInitCallback = HAL_MDF_MspInit; - } - hmdf->MspInitCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - /* Call MDF MSP init function */ - HAL_MDF_MspInit(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - - /* Configure common parameters only for first MDF or ADF instance */ - if (((v_mdf1InstanceCounter == 0U) && IS_MDF_INSTANCE(hmdf->Instance)) || - ((v_adf1InstanceCounter == 0U) && IS_ADF_INSTANCE(hmdf->Instance))) - { - MDF_TypeDef *mdfBase; - /* Get MDF base according instance */ - mdfBase = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1; - - /* Check clock generator status */ - if ((mdfBase->CKGCR & MDF_CKGCR_CCKACTIVE) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Configure number of interleaved filters for MDF instance */ - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_MDF_INTERLEAVED_FILTERS(hmdf->Init.CommonParam.InterleavedFilters)); - mdfBase->GCR &= ~(MDF_GCR_ILVNB); - mdfBase->GCR |= (hmdf->Init.CommonParam.InterleavedFilters << MDF_GCR_ILVNB_Pos); - } - - /* Configure processing clock divider, output clock divider, - output clock pins and output clock generation trigger */ - assert_param(IS_MDF_PROC_CLOCK_DIVIDER(hmdf->Init.CommonParam.ProcClockDivider)); - assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Activation)); - mdfBase->CKGCR = 0U; - mdfBase->CKGCR |= ((hmdf->Init.CommonParam.ProcClockDivider - 1U) << MDF_CKGCR_PROCDIV_Pos); - if (hmdf->Init.CommonParam.OutputClock.Activation == ENABLE) - { - assert_param(IS_MDF_OUTPUT_CLOCK_PINS(hmdf->Init.CommonParam.OutputClock.Pins)); - assert_param(IS_MDF_OUTPUT_CLOCK_DIVIDER(hmdf->Init.CommonParam.OutputClock.Divider)); - assert_param(IS_FUNCTIONAL_STATE(hmdf->Init.CommonParam.OutputClock.Trigger.Activation)); - mdfBase->CKGCR |= (((hmdf->Init.CommonParam.OutputClock.Divider - 1U) << MDF_CKGCR_CCKDIV_Pos) | - hmdf->Init.CommonParam.OutputClock.Pins | - (hmdf->Init.CommonParam.OutputClock.Pins >> 4U)); - if (hmdf->Init.CommonParam.OutputClock.Trigger.Activation == ENABLE) - { - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source)); - } - else /* ADF instance */ - { - assert_param(IS_ADF_OUTPUT_CLOCK_TRIGGER_SOURCE(hmdf->Init.CommonParam.OutputClock.Trigger.Source)); - } - assert_param(IS_MDF_OUTPUT_CLOCK_TRIGGER_EDGE(hmdf->Init.CommonParam.OutputClock.Trigger.Edge)); - mdfBase->CKGCR |= (hmdf->Init.CommonParam.OutputClock.Trigger.Source | - hmdf->Init.CommonParam.OutputClock.Trigger.Edge | - MDF_CKGCR_CKGMOD); - } - } - - /* Activate clock generator */ - mdfBase->CKGCR |= MDF_CKGCR_CKDEN; - } - } - - /* Configure serial interface */ - if ((status == HAL_OK) && (hmdf->Init.SerialInterface.Activation == ENABLE)) - { - /* Check serial interface status */ - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) - { - status = HAL_ERROR; - } - else - { - /* Configure mode, clock source and threshold */ - assert_param(IS_MDF_SITF_MODE(hmdf->Init.SerialInterface.Mode)); - assert_param(IS_MDF_SITF_CLOCK_SOURCE(hmdf->Init.SerialInterface.ClockSource)); - assert_param(IS_MDF_SITF_THRESHOLD(hmdf->Init.SerialInterface.Threshold)); - hmdf->Instance->SITFCR = 0U; - hmdf->Instance->SITFCR |= ((hmdf->Init.SerialInterface.Threshold << MDF_SITFCR_STH_Pos) | - hmdf->Init.SerialInterface.Mode | hmdf->Init.SerialInterface.ClockSource); - - /* Activate serial interface */ - hmdf->Instance->SITFCR |= MDF_SITFCR_SITFEN; - } - } - - if (status == HAL_OK) - { - /* Configure filter bitstream */ - hmdf->Instance->BSMXCR &= ~(MDF_BSMXCR_BSSEL); - hmdf->Instance->BSMXCR |= hmdf->Init.FilterBistream; - - /* Update instance counter and table */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - v_adf1InstanceCounter++; - } - else /* MDF instance */ - { - v_mdf1InstanceCounter++; - } - a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = hmdf; - - /* Update error code and state */ - hmdf->ErrorCode = MDF_ERROR_NONE; - hmdf->State = HAL_MDF_STATE_READY; - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief De-initialize the MDF instance. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_DeInit(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check MDF handle */ - if (hmdf == NULL) - { - status = HAL_ERROR; - } - else - { - /* Check parameters */ - assert_param(IS_MDF_ALL_INSTANCE(hmdf->Instance)); - - /* Check that instance has not been already deinitialized */ - if (a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] == NULL) - { - status = HAL_ERROR; - } - else - { - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - /* Disable short circuit detector if needed */ - if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != 0U) - { - hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN); - } - - /* Disable out-off limit detector if needed */ - if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) - { - hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN); - } - } - - /* Disable sound activity detector if needed */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); - } - } - - /* Disable filter if needed */ - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) - { - hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); - } - - /* Disable serial interface if needed */ - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) != 0U) - { - hmdf->Instance->SITFCR &= ~(MDF_SITFCR_SITFEN); - } - - /* Disable all interrupts and clear all pending flags */ - hmdf->Instance->DFLTIER = 0U; - hmdf->Instance->DFLTISR = 0xFFFFFFFFU; - - /* Disable clock generator only for last MDF or ADF instance deinitialization */ - if (((v_mdf1InstanceCounter == 1U) && IS_MDF_INSTANCE(hmdf->Instance)) || - ((v_adf1InstanceCounter == 1U) && IS_ADF_INSTANCE(hmdf->Instance))) - { - MDF_TypeDef *p_mdf_base; - /* Get MDF base according instance */ - p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1; - - /* Disable clock generator */ - p_mdf_base->CKGCR &= ~(MDF_CKGCR_CKDEN); - } - - /* Call MDF MSP deinit function */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - if (hmdf->MspDeInitCallback == NULL) - { - hmdf->MspDeInitCallback = HAL_MDF_MspDeInit; - } - hmdf->MspDeInitCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_MspDeInit(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - - /* Update instance counter and table */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - v_adf1InstanceCounter--; - } - else /* MDF instance */ - { - v_mdf1InstanceCounter--; - } - a_mdfHandle[MDF_GetHandleNumberFromInstance(hmdf->Instance)] = (MDF_HandleTypeDef *) NULL; - - /* Update state */ - hmdf->State = HAL_MDF_STATE_RESET; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Initialize the MDF instance MSP. - * @param hmdf MDF handle. - * @retval None. - */ -__weak void HAL_MDF_MspInit(MDF_HandleTypeDef *hmdf) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_MspInit could be implemented in the user file */ -} - -/** - * @brief De-initialize the MDF instance MSP. - * @param hmdf MDF handle. - * @retval None. - */ -__weak void HAL_MDF_MspDeInit(MDF_HandleTypeDef *hmdf) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_MspDeInit could be implemented in the user file */ -} - -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) -/** - * @brief Register a user MDF callback to be used instead of the weak predefined callback. - * @param hmdf MDF handle. - * @param CallbackID ID of the callback to be registered. - * This parameter can be one of the following values: - * @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID. - * @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID. - * @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance). - * @arg @ref HAL_MDF_ERROR_CB_ID error callback ID. - * @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID. - * @param pCallback pointer to the callback function. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_RegisterCallback(MDF_HandleTypeDef *hmdf, - HAL_MDF_CallbackIDTypeDef CallbackID, - pMDF_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pCallback == NULL) - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - else - { - if (hmdf->State == HAL_MDF_STATE_READY) - { - switch (CallbackID) - { - case HAL_MDF_ACQ_COMPLETE_CB_ID : - hmdf->AcqCpltCallback = pCallback; - break; - case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID : - hmdf->AcqHalfCpltCallback = pCallback; - break; - case HAL_MDF_SAD_CB_ID : - hmdf->SadCallback = pCallback; - break; - case HAL_MDF_ERROR_CB_ID : - hmdf->ErrorCallback = pCallback; - break; - case HAL_MDF_MSPINIT_CB_ID : - hmdf->MspInitCallback = pCallback; - break; - case HAL_MDF_MSPDEINIT_CB_ID : - hmdf->MspDeInitCallback = pCallback; - break; - default : - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - break; - } - } - else if (hmdf->State == HAL_MDF_STATE_RESET) - { - switch (CallbackID) - { - case HAL_MDF_MSPINIT_CB_ID : - hmdf->MspInitCallback = pCallback; - break; - case HAL_MDF_MSPDEINIT_CB_ID : - hmdf->MspDeInitCallback = pCallback; - break; - default : - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - break; - } - } - else - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Unregister a user MDF callback. - * MDF callback is redirected to the weak predefined callback. - * @param hmdf MDF handle. - * @param CallbackID ID of the callback to be unregistered. - * This parameter can be one of the following values: - * @arg @ref HAL_MDF_ACQ_COMPLETE_CB_ID acquisition complete callback ID. - * @arg @ref HAL_MDF_ACQ_HALFCOMPLETE_CB_ID acquisition half complete callback ID. - * @arg @ref HAL_MDF_SAD_CB_ID sound activity detector callback ID (only for ADF instance). - * @arg @ref HAL_MDF_ERROR_CB_ID error callback ID. - * @arg @ref HAL_MDF_MSPINIT_CB_ID MSP init callback ID. - * @arg @ref HAL_MDF_MSPDEINIT_CB_ID MSP de-init callback ID. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_UnRegisterCallback(MDF_HandleTypeDef *hmdf, - HAL_MDF_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hmdf->State == HAL_MDF_STATE_READY) - { - switch (CallbackID) - { - case HAL_MDF_ACQ_COMPLETE_CB_ID : - hmdf->AcqCpltCallback = HAL_MDF_AcqCpltCallback; - break; - case HAL_MDF_ACQ_HALFCOMPLETE_CB_ID : - hmdf->AcqHalfCpltCallback = HAL_MDF_AcqHalfCpltCallback; - break; - case HAL_MDF_SAD_CB_ID : - hmdf->SadCallback = HAL_MDF_SadCallback; - break; - case HAL_MDF_ERROR_CB_ID : - hmdf->ErrorCallback = HAL_MDF_ErrorCallback; - break; - case HAL_MDF_MSPINIT_CB_ID : - hmdf->MspInitCallback = HAL_MDF_MspInit; - break; - case HAL_MDF_MSPDEINIT_CB_ID : - hmdf->MspDeInitCallback = HAL_MDF_MspDeInit; - break; - default : - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - break; - } - } - else if (hmdf->State == HAL_MDF_STATE_RESET) - { - switch (CallbackID) - { - case HAL_MDF_MSPINIT_CB_ID : - hmdf->MspInitCallback = HAL_MDF_MspInit; - break; - case HAL_MDF_MSPDEINIT_CB_ID : - hmdf->MspDeInitCallback = HAL_MDF_MspDeInit; - break; - default : - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - break; - } - } - else - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief Register specific MDF out-off limit detector callback - * to be used instead of the weak predefined callback. - * @param hmdf MDF handle. - * @param pCallback pointer to the out-off limit detector callback function. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_RegisterOldCallback(MDF_HandleTypeDef *hmdf, - pMDF_OldCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pCallback == NULL) - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - else - { - if (hmdf->State == HAL_MDF_STATE_READY) - { - hmdf->OldCallback = pCallback; - } - else - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Unregister the specific MDF out-off limit detector callback. - * MDF out-off limit detector callback is redirected to the weak predefined callback. - * @param hmdf MDF handle. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_UnRegisterOldCallback(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hmdf->State == HAL_MDF_STATE_READY) - { - hmdf->OldCallback = HAL_MDF_OldCallback; - } - else - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} - -/** - * @brief Register specific MDF sound level callback - * to be used instead of the weak predefined callback. - * @param hmdf MDF handle. - * @param pCallback pointer to the sound level callback function. - * @retval HAL status. - * @note This function must not be used with MDF instance. - */ -HAL_StatusTypeDef HAL_MDF_RegisterSndLvlCallback(MDF_HandleTypeDef *hmdf, - pMDF_SndLvlCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pCallback == NULL) - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - else - { - if (hmdf->State == HAL_MDF_STATE_READY) - { - hmdf->SndLvCallback = pCallback; - } - else - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Unregister the specific MDF sound level callback. - * MDF sound level callback is redirected to the weak predefined callback. - * @param hmdf MDF handle. - * @retval HAL status. - * @note This function must not be used with MDF instance. - */ -HAL_StatusTypeDef HAL_MDF_UnRegisterSndLvlCallback(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hmdf->State == HAL_MDF_STATE_READY) - { - hmdf->SndLvCallback = HAL_MDF_SndLvlCallback; - } - else - { - /* Update error code and status */ - hmdf->ErrorCode |= MDF_ERROR_INVALID_CALLBACK; - status = HAL_ERROR; - } - - /* Return function status */ - return status; -} -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup MDF_Exported_Functions_Group2 Acquisition functions - * @brief Acquisition functions - * -@verbatim - ============================================================================== - ##### Acquisition functions ##### - ============================================================================== - [..] This section provides functions allowing to : - (+) Start and stop acquisition in polling, interrupt or DMA mode. - (+) Wait and get acquisition values. - (+) Generate pulse on TRGO signal. - (+) Modify and get some filter parameters during acquisition. - (+) Wait and get sound level values for ADF instance. - (+) Detect sound activity for ADF instance. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start acquisition in polling mode. - * @param hmdf MDF handle. - * @param pFilterConfig Filter configuration parameters. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_AcqStart(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pFilterConfig == NULL) - { - status = HAL_ERROR; - } - else - { - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); - } - else - { - assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); - } - if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) && - ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) || - (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) || - (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT))) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - /* Check filter status */ - else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) - { - status = HAL_ERROR; - } - else - { - /* For ADF instance, check SAD status */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* For MDF instance, check OLD status and main filter order */ - assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode)); - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4)) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Configure filter and start acquisition */ - hmdf->Instance->DFLTCR = 0U; - MDF_AcqStart(hmdf, pFilterConfig); - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for available acquisition value. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_PollForAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for available acquisition value */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_RXNEF) != MDF_DFLTISR_RXNEF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - /* Check if data overflow, saturation or reshape filter occurs */ - uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF)); - if (error_flags != 0U) - { - /* Update error code */ - if ((error_flags & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF) - { - hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW; - } - if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF) - { - hmdf->ErrorCode |= MDF_ERROR_SATURATION; - } - if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF) - { - hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN; - } - - /* Clear corresponding flags */ - hmdf->Instance->DFLTISR |= error_flags; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - - if (status == HAL_OK) - { - /* Update state only in asynchronous single shot mode */ - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE) - { - hmdf->State = HAL_MDF_STATE_READY; - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for available snapshot acquisition value. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_PollForSnapshotAcq(MDF_HandleTypeDef *hmdf, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for available snapshot acquisition value */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SSDRF) != MDF_DFLTISR_SSDRF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - /* Check if snapshot overrun, saturation or reshape filter occurs */ - uint32_t error_flags = (hmdf->Instance->DFLTISR & (MDF_DFLTISR_SSOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF)); - if (error_flags != 0U) - { - /* Update error code */ - if ((error_flags & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF) - { - hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW; - } - if ((error_flags & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF) - { - hmdf->ErrorCode |= MDF_ERROR_SATURATION; - } - if ((error_flags & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF) - { - hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN; - } - - /* Clear corresponding flags */ - hmdf->Instance->DFLTISR |= error_flags; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get acquisition value. - * @param hmdf MDF handle. - * @param pValue Acquisition value on 24 MSB. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_GetAcqValue(const MDF_HandleTypeDef *hmdf, int32_t *pValue) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pValue == NULL) - { - status = HAL_ERROR; - } - else - { - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Get acquisition value */ - *pValue = (int32_t) hmdf->Instance->DFLTDR; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get snapshot acquisition value. - * @param hmdf MDF handle. - * @param pSnapshotParam Snapshot parameters. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_GetSnapshotAcqValue(MDF_HandleTypeDef *hmdf, MDF_SnapshotParamTypeDef *pSnapshotParam) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pSnapshotParam == NULL) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - uint32_t snpsdr_value; - - /* Read value of snapshot data register */ - snpsdr_value = hmdf->Instance->SNPSDR; - - /* Clear snapshot data ready flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF; - - /* Store value of decimation counter in snapshot parameter structure */ - pSnapshotParam->DecimationCounter = (snpsdr_value & MDF_SNPSDR_MCICDC); - - /* Check snapshot format */ - if ((hmdf->Instance->DFLTCR & MDF_SNAPSHOT_16BITS) == MDF_SNAPSHOT_16BITS) - { - /* Store value of integrator counter in snapshot parameter structure */ - pSnapshotParam->IntegratorCounter = ((snpsdr_value & MDF_SNPSDR_EXTSDR) >> MDF_SNPSDR_EXTSDR_Pos); - - /* Store snapshot acquisition value (16MSB) in snapshot parameter structure */ - snpsdr_value &= 0xFFFF0000U; - pSnapshotParam->Value = (int32_t) snpsdr_value; - } - else - { - /* Store snapshot acquisition value (23MSB) in snapshot parameter structure */ - snpsdr_value &= 0xFFFFFE00U; - pSnapshotParam->Value = (int32_t) snpsdr_value; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop acquisition in polling mode. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_AcqStop(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - /* Check if state is ready and filter active */ - if (hmdf->State == HAL_MDF_STATE_READY) - { - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE) - { - status = HAL_ERROR; - } - } - else - { - status = HAL_ERROR; - } - } - else - { - /* Disable sound activity detector if needed for ADF instance */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); - } - } - } - - if (status == HAL_OK) - { - /* Disable filter */ - hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); - - /* Clear all potential pending flags */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | - MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF); - } - else - { - hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF | - MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF); - } - - /* Update state */ - hmdf->State = HAL_MDF_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start acquisition in interrupt mode. - * @param hmdf MDF handle. - * @param pFilterConfig Filter configuration parameters. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_AcqStart_IT(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pFilterConfig == NULL) - { - status = HAL_ERROR; - } - else - { - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); - } - else - { - assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); - } - if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) && - ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) || - (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) || - (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT))) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - /* Check filter status */ - else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) - { - status = HAL_ERROR; - } - else - { - /* For ADF instance, check SAD status */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* For MDF instance, check OLD status and main filter order */ - assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode)); - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4)) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT) - { - /* Enable snapshot overrun and data ready interrupts */ - hmdf->Instance->DFLTIER |= (MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SSDRIE); - } - else - { - if ((IS_MDF_INSTANCE(hmdf->Instance)) || (pFilterConfig->SoundActivity.Activation == DISABLE) || - (pFilterConfig->SoundActivity.DataMemoryTransfer != MDF_SAD_NO_MEMORY_TRANSFER)) - { - /* Enable data overflow and fifo threshold interrupts */ - hmdf->Instance->DFLTIER |= (MDF_DFLTIER_DOVRIE | MDF_DFLTIER_FTHIE); - } - } - - if (pFilterConfig->ReshapeFilter.Activation == ENABLE) - { - /* Enable reshape filter overrun interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE; - } - - /* Enable saturation interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE; - - if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE)) - { - /* Enable sound level value ready and sound activity detection interrupts */ - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt)); - hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ? - (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) : - MDF_DFLTIER_SDDETIE; - } - - /* Configure filter and start acquisition */ - hmdf->Instance->DFLTCR = 0U; - MDF_AcqStart(hmdf, pFilterConfig); - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop acquisition in interrupt mode. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_AcqStop_IT(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - /* Check if state is ready and filter active */ - if (hmdf->State == HAL_MDF_STATE_READY) - { - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE) - { - status = HAL_ERROR; - } - } - else - { - status = HAL_ERROR; - } - } - else - { - /* Disable sound activity detector if needed for ADF instance */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); - } - } - } - - if (status == HAL_OK) - { - /* Disable filter */ - hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); - - /* Disable interrupts and clear all potential pending flags */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SATIE | - MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | MDF_DFLTIER_SDLVLIE); - hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | - MDF_DFLTISR_SDDETF | MDF_DFLTISR_SDLVLF); - } - else - { - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_FTHIE | MDF_DFLTIER_DOVRIE | MDF_DFLTIER_SSDRIE | - MDF_DFLTIER_SSOVRIE | MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE); - hmdf->Instance->DFLTISR |= (MDF_DFLTISR_DOVRF | MDF_DFLTISR_SSDRF | MDF_DFLTISR_SSOVRF | - MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF); - } - - /* Update state */ - hmdf->State = HAL_MDF_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start acquisition in DMA mode. - * @param hmdf MDF handle. - * @param pFilterConfig Filter configuration parameters. - * @param pDmaConfig DMA configuration parameters. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_AcqStart_DMA(MDF_HandleTypeDef *hmdf, const MDF_FilterConfigTypeDef *pFilterConfig, - const MDF_DmaConfigTypeDef *pDmaConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if ((pFilterConfig == NULL) || (pDmaConfig == NULL)) - { - status = HAL_ERROR; - } - else - { - assert_param(IS_FUNCTIONAL_STATE(pDmaConfig->MsbOnly)); - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_ADF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); - } - else - { - assert_param(IS_MDF_ACQUISITION_MODE(pFilterConfig->AcquisitionMode)); - } - if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE) && - ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE) || - (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SINGLE) || - (pFilterConfig->AcquisitionMode == MDF_MODE_WINDOW_CONT))) - { - status = HAL_ERROR; - } - else if (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - /* Check filter status */ - else if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != 0U) - { - status = HAL_ERROR; - } - else - { - /* For ADF instance, check SAD status */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* For MDF instance, check OLD status and main filter order */ - assert_param(IS_MDF_CIC_MODE(pFilterConfig->CicMode)); - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - if (((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != 0U) && (pFilterConfig->CicMode >= MDF_ONE_FILTER_SINC4)) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - uint32_t SrcAddress; - - if (pFilterConfig->ReshapeFilter.Activation == ENABLE) - { - /* Enable reshape filter overrun interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_RFOVRIE; - } - - /* Enable saturation interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_SATIE; - - if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE)) - { - /* Enable sound level value ready and sound activity detection interrupts */ - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.SoundLevelInterrupt)); - hmdf->Instance->DFLTIER |= (pFilterConfig->SoundActivity.SoundLevelInterrupt == ENABLE) ? - (MDF_DFLTIER_SDLVLIE | MDF_DFLTIER_SDDETIE) : - MDF_DFLTIER_SDDETIE; - } - - /* Enable MDF DMA requests */ - hmdf->Instance->DFLTCR = MDF_DFLTCR_DMAEN; - - /* Start DMA transfer */ - hmdf->hdma->XferCpltCallback = MDF_DmaXferCpltCallback; - hmdf->hdma->XferHalfCpltCallback = MDF_DmaXferHalfCpltCallback; - hmdf->hdma->XferErrorCallback = MDF_DmaErrorCallback; - SrcAddress = (pDmaConfig->MsbOnly == ENABLE) ? (((uint32_t) &hmdf->Instance->DFLTDR) + 2U) : - (uint32_t) &hmdf->Instance->DFLTDR; - if ((hmdf->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hmdf->hdma->LinkedListQueue != NULL) - { - hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = pDmaConfig->DataLength; - hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = SrcAddress; - hmdf->hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = pDmaConfig->Address; - - status = HAL_DMAEx_List_Start_IT(hmdf->hdma); - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hmdf->hdma, SrcAddress, pDmaConfig->Address, pDmaConfig->DataLength); - } - if (status != HAL_OK) - { - /* Update state */ - hmdf->State = HAL_MDF_STATE_ERROR; - status = HAL_ERROR; - } - else - { - /* Configure filter and start acquisition */ - MDF_AcqStart(hmdf, pFilterConfig); - } - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop acquisition in DMA mode. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_AcqStop_DMA(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check if state is ready and filter active */ - if (hmdf->State == HAL_MDF_STATE_READY) - { - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) != MDF_DFLTCR_DFLTACTIVE) - { - status = HAL_ERROR; - } - } - else - { - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - /* Stop the DMA transfer */ - if (HAL_DMA_Abort(hmdf->hdma) != HAL_OK) - { - /* Update state */ - hmdf->State = HAL_MDF_STATE_ERROR; - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Disable sound activity detector if needed for ADF instance */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) != 0U) - { - hmdf->Instance->SADCR &= ~(MDF_SADCR_SADEN); - } - } - - /* Disable filter */ - hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DFLTEN); - - /* Disable interrupts and clear all potential pending flags */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE | MDF_DFLTIER_SDDETIE | - MDF_DFLTIER_SDLVLIE); - hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF | MDF_DFLTISR_SDDETF | - MDF_DFLTISR_SDLVLF); - } - else - { - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SATIE | MDF_DFLTIER_RFOVRIE); - hmdf->Instance->DFLTISR |= (MDF_DFLTISR_SATF | MDF_DFLTISR_RFOVRF); - } - - /* Disable MDF DMA requests */ - hmdf->Instance->DFLTCR &= ~(MDF_DFLTCR_DMAEN); - - /* Update state */ - hmdf->State = HAL_MDF_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to generate pulse on TRGO signal. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_GenerateTrgo(const MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_READY) - { - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - MDF_TypeDef *p_mdf_base; - - /* Get MDF base according instance */ - p_mdf_base = (IS_ADF_INSTANCE(hmdf->Instance)) ? ADF1 : MDF1; - - /* Check if trigger output control is already active */ - if ((p_mdf_base->GCR & MDF_GCR_TRGO) == MDF_GCR_TRGO) - { - status = HAL_ERROR; - } - else - { - /* Generate pulse on trigger output control signal */ - p_mdf_base->GCR |= MDF_GCR_TRGO; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to set delay to apply on data source in number of samples. - * @param hmdf MDF handle. - * @param Delay Delay to apply on data source in number of samples. - * This parameter must be a number between Min_Data = 0 and Max_Data = 127. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_SetDelay(MDF_HandleTypeDef *hmdf, uint32_t Delay) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_DELAY(Delay)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - /* Check if bitstream delay is already active */ - if ((hmdf->Instance->DLYCR & MDF_DLYCR_SKPBF) == MDF_DLYCR_SKPBF) - { - status = HAL_ERROR; - } - else - { - /* Configure bitstream delay */ - hmdf->Instance->DLYCR |= Delay; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get current delay applied on data source in number of samples. - * @param hmdf MDF handle. - * @param pDelay Current delay applied on data source in number of samples. - * This value is between Min_Data = 0 and Max_Data = 127. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_GetDelay(const MDF_HandleTypeDef *hmdf, uint32_t *pDelay) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pDelay == NULL) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - /* Get current bitstream delay */ - *pDelay = (hmdf->Instance->DLYCR & MDF_DLYCR_SKPDLY); - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to set filter gain. - * @param hmdf MDF handle. - * @param Gain Filter gain in step of around 3db (from -48db to 72dB). - * This parameter must be a number between Min_Data = -16 and Max_Data = 24. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_SetGain(MDF_HandleTypeDef *hmdf, int32_t Gain) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_GAIN(Gain)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - uint32_t register_gain_value; - uint32_t tmp_register; - - if (Gain < 0) - { - int32_t adjust_gain; - - /* adjust gain value to set on register for negative value (offset of -16) */ - adjust_gain = Gain - 16; - register_gain_value = ((uint32_t) adjust_gain & 0x3FU); - } - else - { - /* for positive value, no offset to apply */ - register_gain_value = (uint32_t) Gain; - } - /* Set gain */ - tmp_register = (hmdf->Instance->DFLTCICR & ~(MDF_DFLTCICR_SCALE)); - hmdf->Instance->DFLTCICR = (tmp_register | (register_gain_value << MDF_DFLTCICR_SCALE_Pos)); - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get filter gain. - * @param hmdf MDF handle. - * @param pGain Filter gain in step of around 3db (from -48db to 72dB). - * This parameter is between Min_Data = -16 and Max_Data = 24. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_GetGain(const MDF_HandleTypeDef *hmdf, int32_t *pGain) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pGain == NULL) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - uint32_t register_gain_value; - - /* Get current gain */ - register_gain_value = ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_SCALE) >> MDF_DFLTCICR_SCALE_Pos); - if (register_gain_value > 31U) - { - /* adjust gain value to set on register for negative value (offset of +16) */ - register_gain_value |= 0xFFFFFFC0U; - *pGain = (int32_t) register_gain_value + 16; - } - else - { - /* for positive value, no offset to apply */ - *pGain = (int32_t) register_gain_value; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to set filter offset error compensation. - * @param hmdf MDF handle. - * @param Offset Filter offset error compensation. - * This parameter must be a number between Min_Data = -33554432 and Max_Data = 33554431. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_SetOffset(MDF_HandleTypeDef *hmdf, int32_t Offset) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - assert_param(IS_MDF_OFFSET(Offset)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - /* Set offset */ - hmdf->Instance->OECCR = (uint32_t) Offset; - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to get filter offset error compensation. - * @param hmdf MDF handle. - * @param pOffset Filter offset error compensation. - * This value is between Min_Data = -33554432 and Max_Data = 33554431. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_GetOffset(const MDF_HandleTypeDef *hmdf, int32_t *pOffset) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - if (pOffset == NULL) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - else - { - uint32_t register_offset_value; - - /* Get current offset */ - register_offset_value = hmdf->Instance->OECCR; - if (register_offset_value > 33554431U) - { - /* Negative value */ - register_offset_value |= 0xFC000000U; - *pOffset = (int32_t) register_offset_value; - } - else - { - /* Positive value */ - *pOffset = (int32_t) register_offset_value; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for sound level data. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @param pSoundLevel Sound level. - This parameter can be a value between Min_Data = 0 and Max_Data = 32767. - * @param pAmbientNoise Ambient noise. - This parameter can be a value between Min_Data = 0 and Max_Data = 32767. - * @retval HAL status. - * @note This function must not be used with MDF instance. - */ -HAL_StatusTypeDef HAL_MDF_PollForSndLvl(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pSoundLevel, - uint32_t *pAmbientNoise) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_ADF_INSTANCE(hmdf->Instance)); - if ((pSoundLevel == NULL) || (pAmbientNoise == NULL)) - { - status = HAL_ERROR; - } - /* Check state */ - else if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - /* Check SAD status */ - else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U) - { - status = HAL_ERROR; - } - else - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for available sound level data */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDLVLF) != MDF_DFLTISR_SDLVLF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - if (status == HAL_OK) - { - /* Get sound level */ - *pSoundLevel = hmdf->Instance->SADSDLVR; - - /* Get ambient noise */ - *pAmbientNoise = hmdf->Instance->SADANLVR; - - /* Clear sound level ready flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for sound activity detection. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status. - * @note This function must not be used with MDF instance. - */ -HAL_StatusTypeDef HAL_MDF_PollForSad(MDF_HandleTypeDef *hmdf, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_ADF_INSTANCE(hmdf->Instance)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - status = HAL_ERROR; - } - /* Check SAD status */ - else if ((hmdf->Instance->SADCR & MDF_SADCR_SADACTIVE) == 0U) - { - status = HAL_ERROR; - } - else - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for sound activity detection */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SDDETF) != MDF_DFLTISR_SDDETF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - if (status == HAL_OK) - { - /* Clear sound activity detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief MDF acquisition complete callback. - * @param hmdf MDF handle. - * @retval None. - */ -__weak void HAL_MDF_AcqCpltCallback(MDF_HandleTypeDef *hmdf) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_AcqCpltCallback could be implemented in the user file */ -} - -/** - * @brief MDF acquisition half complete callback. - * @param hmdf MDF handle. - * @retval None. - */ -__weak void HAL_MDF_AcqHalfCpltCallback(MDF_HandleTypeDef *hmdf) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_AcqHalfCpltCallback could be implemented in the user file */ -} - -/** - * @brief MDF sound level callback. - * @param hmdf MDF handle. - * @param SoundLevel Sound level value computed by sound activity detector. - * This parameter can be a value between Min_Data = 0 and Max_Data = 32767. - * @param AmbientNoise Ambient noise value computed by sound activity detector. - * This parameter can be a value between Min_Data = 0 and Max_Data = 32767. - * @retval None. - */ -__weak void HAL_MDF_SndLvlCallback(MDF_HandleTypeDef *hmdf, uint32_t SoundLevel, uint32_t AmbientNoise) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - UNUSED(SoundLevel); - UNUSED(AmbientNoise); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_SndLvlCallback could be implemented in the user file */ -} - -/** - * @brief MDF sound activity detector callback. - * @param hmdf MDF handle. - * @retval None. - */ -__weak void HAL_MDF_SadCallback(MDF_HandleTypeDef *hmdf) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_SadCallback could be implemented in the user file */ -} - -/** - * @} - */ - -/** @defgroup MDF_Exported_Functions_Group3 Clock absence detection functions - * @brief Clock absence detection functions - * -@verbatim - ============================================================================== - ##### Clock absence detection functions ##### - ============================================================================== - [..] This section provides functions allowing to : - (+) Start and stop clock absence detection in interrupt mode. - (+) Detect clock absence. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to poll for the clock absence detection. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_PollForCkab(MDF_HandleTypeDef *hmdf, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check serial interface status and mode */ - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U) - { - status = HAL_ERROR; - } - else - { - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for clock absence detection */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) != MDF_DFLTISR_CKABF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - if (status == HAL_OK) - { - /* Clear clock absence detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start clock absence detection in interrupt mode. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_CkabStart_IT(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check serial interface status and mode */ - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U) - { - status = HAL_ERROR; - } - else - { - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Clear clock absence detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; - - /* Check clock absence detection flag */ - if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF) - { - status = HAL_ERROR; - } - else - { - /* Enable clock absence detection interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_CKABIE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop clock absence detection in interrupt mode. - * @param hmdf MDF handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_MDF_CkabStop_IT(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check serial interface status and mode */ - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFACTIVE) == 0U) - { - status = HAL_ERROR; - } - else - { - if ((hmdf->Instance->SITFCR & MDF_SITFCR_SITFMOD) != MDF_SITF_NORMAL_SPI_MODE) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Disable clock absence detection interrupt */ - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_CKABIE); - - /* Clear potential pending clock absence detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup MDF_Exported_Functions_Group4 Short circuit detection functions - * @brief Short circuit detection functions - * -@verbatim - ============================================================================== - ##### Short circuit detection functions ##### - ============================================================================== - [..] This section provides functions available only for MDF instance - allowing to : - (+) Start and stop short circuit detection in polling and interrupt mode. - (+) Detect short circuit. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start short-circuit detection in polling mode. - * @param hmdf MDF handle. - * @param pScdConfig Short-circuit detector configuration parameters. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_ScdStart(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pScdConfig == NULL) - { - status = HAL_ERROR; - } - else - { - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold)); - assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check short-circuit detector status */ - if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Configure threshold and break signal */ - hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) | - (pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos)); - - /* Enable short-circuit detector */ - hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN; - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the short-circuit detection. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_PollForScd(MDF_HandleTypeDef *hmdf, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check short-circuit detector status */ - if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE) - { - status = HAL_ERROR; - } - else - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for short-circuit detection */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_SCDF) != MDF_DFLTISR_SCDF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - if (status == HAL_OK) - { - /* Clear short-circuit detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF; - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop short-circuit detection in polling mode. - * @param hmdf MDF handle. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_ScdStop(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check short-circuit detector status */ - if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Disable short-circuit detection */ - hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN); - - /* Clear potential pending short-circuit detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start short-circuit detection in interrupt mode. - * @param hmdf MDF handle. - * @param pScdConfig Short-circuit detector configuration parameters. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_ScdStart_IT(MDF_HandleTypeDef *hmdf, const MDF_ScdConfigTypeDef *pScdConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pScdConfig == NULL) - { - status = HAL_ERROR; - } - else - { - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - assert_param(IS_MDF_SCD_THRESHOLD(pScdConfig->Threshold)); - assert_param(IS_MDF_BREAK_SIGNAL(pScdConfig->BreakSignal)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check short-circuit detector status */ - if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) == MDF_SCDCR_SCDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Configure threshold and break signal */ - hmdf->Instance->SCDCR = (((pScdConfig->Threshold - 1U) << MDF_SCDCR_SCDT_Pos) | - (pScdConfig->BreakSignal << MDF_SCDCR_BKSCD_Pos)); - - /* Enable short-circuit detector interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_SCDIE; - - /* Enable short-circuit detector */ - hmdf->Instance->SCDCR |= MDF_SCDCR_SCDEN; - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop short-circuit detection in interrupt mode. - * @param hmdf MDF handle. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_ScdStop_IT(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check short-circuit detector status */ - if ((hmdf->Instance->SCDCR & MDF_SCDCR_SCDACTIVE) != MDF_SCDCR_SCDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Disable short-circuit detection */ - hmdf->Instance->SCDCR &= ~(MDF_SCDCR_SCDEN); - - /* Disable short-circuit detection interrupt */ - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_SCDIE); - - /* Clear potential pending short-circuit detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF; - } - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup MDF_Exported_Functions_Group5 Out-off limit detection functions - * @brief Out-off limit detection functions - * -@verbatim - ============================================================================== - ##### Out-off limit detection functions ##### - ============================================================================== - [..] This section provides functions available only for MDF instance - allowing to : - (+) Start and stop out-off limit detection in polling and interrupt mode. - (+) Detect short circuit and get threshold information. -@endverbatim - * @{ - */ - -/** - * @brief This function allows to start out-off limit detection in polling mode. - * @param hmdf MDF handle. - * @param pOldConfig Out-off limit detector configuration parameters. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_OldStart(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pOldConfig == NULL) - { - status = HAL_ERROR; - } - else - { - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode)); - assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio)); - assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold)); - assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold)); - assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig)); - assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal)); - if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold) - { - status = HAL_ERROR; - } - else - { - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Check out-off limit detector status */ - if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Check filter status */ - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE) - { - /* Check main filter order */ - if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4) - { - status = HAL_ERROR; - } - } - else - { - /* Reset main filter order */ - hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD); - } - - if (status == HAL_OK) - { - /* Configure OLD CIC mode, decimation ratio, event and break signal */ - hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig | - ((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) | - (pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos)); - - /* Configure low and high thresholds */ - hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold; - hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold; - - /* Enable out-off limit detector */ - hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN; - } - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to poll for the out-off limit detection. - * @param hmdf MDF handle. - * @param Timeout Timeout value in milliseconds. - * @param pThresholdInfo Threshold information of out-off limit detection. - * This parameter can be a value of @ref MDF_OldThresholdInfo. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_PollForOld(MDF_HandleTypeDef *hmdf, uint32_t Timeout, uint32_t *pThresholdInfo) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - if (pThresholdInfo == NULL) - { - status = HAL_ERROR; - } - else - { - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Check out-off limit detector status */ - if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE) - { - status = HAL_ERROR; - } - else - { - uint32_t tickstart = HAL_GetTick(); - - /* Wait for out-off limit detection */ - while (((hmdf->Instance->DFLTISR & MDF_DFLTISR_OLDF) != MDF_DFLTISR_OLDF) && (status == HAL_OK)) - { - /* Check the timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - status = HAL_TIMEOUT; - } - } - } - - if (status == HAL_OK) - { - /* Get threshold information */ - if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U) - { - *pThresholdInfo = MDF_OLD_IN_THRESHOLDS; - } - else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF) - { - *pThresholdInfo = MDF_OLD_LOW_THRESHOLD; - } - else - { - *pThresholdInfo = MDF_OLD_HIGH_THRESHOLD; - } - - /* Clear out-off limit detection flags */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF; - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop out-off limit detection in polling mode. - * @param hmdf MDF handle. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_OldStop(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check out-off limit detector status */ - if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Disable out-off limit detection */ - hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN); - - /* Clear potential pending out-off limit detection flags */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to start out-off limit detection in interrupt mode. - * @param hmdf MDF handle. - * @param pOldConfig Out-off limit detector configuration parameters. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_OldStart_IT(MDF_HandleTypeDef *hmdf, const MDF_OldConfigTypeDef *pOldConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - if (pOldConfig == NULL) - { - status = HAL_ERROR; - } - else - { - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - assert_param(IS_MDF_OLD_CIC_MODE(pOldConfig->OldCicMode)); - assert_param(IS_MDF_OLD_DECIMATION_RATIO(pOldConfig->OldDecimationRatio)); - assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->HighThreshold)); - assert_param(IS_MDF_OLD_THRESHOLD(pOldConfig->LowThreshold)); - assert_param(IS_MDF_OLD_EVENT_CONFIG(pOldConfig->OldEventConfig)); - assert_param(IS_MDF_BREAK_SIGNAL(pOldConfig->BreakSignal)); - if (pOldConfig->LowThreshold >= pOldConfig->HighThreshold) - { - status = HAL_ERROR; - } - else - { - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - } - - if (status == HAL_OK) - { - /* Check out-off limit detector status */ - if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) == MDF_OLDCR_OLDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Check filter status */ - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_DFLTACTIVE) == MDF_DFLTCR_DFLTACTIVE) - { - /* Check main filter order */ - if ((hmdf->Instance->DFLTCICR & MDF_DFLTCICR_CICMOD) >= MDF_ONE_FILTER_SINC4) - { - status = HAL_ERROR; - } - } - else - { - /* Reset main filter order */ - hmdf->Instance->DFLTCICR &= ~(MDF_DFLTCICR_CICMOD); - } - - if (status == HAL_OK) - { - /* Configure OLD CIC mode, decimation ratio, event and break signal */ - hmdf->Instance->OLDCR = (pOldConfig->OldCicMode | pOldConfig->OldEventConfig | - ((pOldConfig->OldDecimationRatio - 1U) << MDF_OLDCR_ACICD_Pos) | - (pOldConfig->BreakSignal << MDF_OLDCR_BKOLD_Pos)); - - /* Configure low and high thresholds */ - hmdf->Instance->OLDTHLR = (uint32_t) pOldConfig->LowThreshold; - hmdf->Instance->OLDTHHR = (uint32_t) pOldConfig->HighThreshold; - - /* Enable out-off limit detector interrupt */ - hmdf->Instance->DFLTIER |= MDF_DFLTIER_OLDIE; - - /* Enable out-off limit detector */ - hmdf->Instance->OLDCR |= MDF_OLDCR_OLDEN; - } - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief This function allows to stop out-off limit detection in interrupt mode. - * @param hmdf MDF handle. - * @retval HAL status. - * @note This function must not be used with ADF instance. - */ -HAL_StatusTypeDef HAL_MDF_OldStop_IT(MDF_HandleTypeDef *hmdf) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_MDF_INSTANCE(hmdf->Instance)); - - /* Check state */ - if (hmdf->State != HAL_MDF_STATE_ACQUISITION) - { - if (hmdf->State != HAL_MDF_STATE_READY) - { - status = HAL_ERROR; - } - } - - if (status == HAL_OK) - { - /* Check out-off limit detector status */ - if ((hmdf->Instance->OLDCR & MDF_OLDCR_OLDACTIVE) != MDF_OLDCR_OLDACTIVE) - { - status = HAL_ERROR; - } - else - { - /* Disable out-off limit detection */ - hmdf->Instance->OLDCR &= ~(MDF_OLDCR_OLDEN); - - /* Disable out-off limit detector interrupt */ - hmdf->Instance->DFLTIER &= ~(MDF_DFLTIER_OLDIE); - - /* Clear potential pending out-off limit detection flags */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief MDF out-off limit detector callback. - * @param hmdf MDF handle. - * @param ThresholdInfo Threshold information of out-off limit detection. - * This parameter can be a value of @ref MDF_OldThresholdInfo. - * @retval None. - */ -__weak void HAL_MDF_OldCallback(MDF_HandleTypeDef *hmdf, uint32_t ThresholdInfo) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - UNUSED(ThresholdInfo); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_OldCallback could be implemented in the user file */ -} - -/** - * @} - */ - -/** @defgroup MDF_Exported_Functions_Group6 Generic functions - * @brief Generic functions - * -@verbatim - ============================================================================== - ##### Generic functions ##### - ============================================================================== - [..] This section provides functions allowing to : - (+) Handle MDF interrupt. - (+) Inform user that error occurs. - (+) Get the current MDF instance state. - (+) Get the current MDF instance error code. -@endverbatim - * @{ - */ - -/** - * @brief This function handles the MDF interrupts. - * @param hmdf MDF handle. - * @retval None. - */ -void HAL_MDF_IRQHandler(MDF_HandleTypeDef *hmdf) -{ - uint32_t tmp_reg1; - uint32_t tmp_reg2; - uint32_t interrupts; - - /* Read current flags and interrupts and determine which ones occur */ - tmp_reg1 = hmdf->Instance->DFLTIER; - tmp_reg2 = hmdf->Instance->DFLTISR; - interrupts = (tmp_reg1 & tmp_reg2); - - /* Check if data overflow occurs */ - if ((interrupts & MDF_DFLTISR_DOVRF) == MDF_DFLTISR_DOVRF) - { - /* Clear data overflow flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_DOVRF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if snapshot overrun occurs */ - else if ((interrupts & MDF_DFLTISR_SSOVRF) == MDF_DFLTISR_SSOVRF) - { - /* Clear snapshot overrun flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSOVRF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_ACQUISITION_OVERFLOW; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if RXFIFO threshold occurs */ - else if ((interrupts & MDF_DFLTISR_FTHF) == MDF_DFLTISR_FTHF) - { - /* Call acquisition complete callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->AcqCpltCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_AcqCpltCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - - /* Update state only in asynchronous single shot mode */ - if ((hmdf->Instance->DFLTCR & MDF_DFLTCR_ACQMOD) == MDF_MODE_ASYNC_SINGLE) - { - hmdf->State = HAL_MDF_STATE_READY; - } - } - /* Check if snapshot data ready occurs */ - else if ((interrupts & MDF_DFLTISR_SSDRF) == MDF_DFLTISR_SSDRF) - { - /* Clear snapshot data ready flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SSDRF; - - /* Call acquisition complete callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->AcqCpltCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_AcqCpltCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if reshape filter overrun occurs */ - else if ((interrupts & MDF_DFLTISR_RFOVRF) == MDF_DFLTISR_RFOVRF) - { - /* Clear reshape filter overrun flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_RFOVRF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_RSF_OVERRUN; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if clock absence detection occurs */ - else if ((interrupts & MDF_DFLTISR_CKABF) == MDF_DFLTISR_CKABF) - { - /* Clear clock absence detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_CKABF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_CLOCK_ABSENCE; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if saturation occurs */ - else if ((interrupts & MDF_DFLTISR_SATF) == MDF_DFLTISR_SATF) - { - /* Clear saturation flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SATF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_SATURATION; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if short-circuit detection occurs */ - else if ((interrupts & MDF_DFLTISR_SCDF) == MDF_DFLTISR_SCDF) - { - /* Clear short-circuit detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SCDF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_SHORT_CIRCUIT; - - /* Call error callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if out-off limit detection occurs */ - else if ((interrupts & MDF_DFLTISR_OLDF) == MDF_DFLTISR_OLDF) - { - uint32_t threshold_info; - - /* Get threshold information */ - if ((hmdf->Instance->DFLTISR & (MDF_DFLTISR_THLF | MDF_DFLTISR_THHF)) == 0U) - { - threshold_info = MDF_OLD_IN_THRESHOLDS; - } - else if ((hmdf->Instance->DFLTISR & MDF_DFLTISR_THLF) == MDF_DFLTISR_THLF) - { - threshold_info = MDF_OLD_LOW_THRESHOLD; - } - else - { - threshold_info = MDF_OLD_HIGH_THRESHOLD; - } - - /* Clear out-off limit detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_OLDF; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_OUT_OFF_LIMIT; - - /* Call out-off limit detection callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->OldCallback(hmdf, threshold_info); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_OldCallback(hmdf, threshold_info); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - /* Check if sound activity detection occurs */ - else if ((interrupts & MDF_DFLTISR_SDDETF) == MDF_DFLTISR_SDDETF) - { - /* Clear sound activity detection flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDDETF; - - /* Call sound activity detection callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->SadCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_SadCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - else - { - /* Check if sound level ready occurs */ - if ((interrupts & MDF_DFLTISR_SDLVLF) == MDF_DFLTISR_SDLVLF) - { - uint32_t sound_level; - uint32_t ambient_noise; - - /* Get sound level */ - sound_level = hmdf->Instance->SADSDLVR; - - /* Get ambient noise */ - ambient_noise = hmdf->Instance->SADANLVR; - - /* Clear sound level ready flag */ - hmdf->Instance->DFLTISR |= MDF_DFLTISR_SDLVLF; - - /* Call sound level callback */ -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->SndLvCallback(hmdf, sound_level, ambient_noise); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_SndLvlCallback(hmdf, sound_level, ambient_noise); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ - } - } -} - -/** - * @brief MDF error callback. - * @param hmdf MDF handle. - * @retval None. - */ -__weak void HAL_MDF_ErrorCallback(MDF_HandleTypeDef *hmdf) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hmdf); - - /* NOTE : This function should not be modified, when the function is needed, - the HAL_MDF_ErrorCallback could be implemented in the user file */ -} - -/** - * @brief This function allows to get the current MDF state. - * @param hmdf MDF handle. - * @retval MDF state. - */ -HAL_MDF_StateTypeDef HAL_MDF_GetState(const MDF_HandleTypeDef *hmdf) -{ - /* Return MDF state */ - return hmdf->State; -} - -/** - * @brief This function allows to get the current MDF error. - * @param hmdf MDF handle. - * @retval MDF error code. - */ -uint32_t HAL_MDF_GetError(const MDF_HandleTypeDef *hmdf) -{ - /* Return MDF error code */ - return hmdf->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup MDF_Private_Functions - * @brief Private functions - * @{ - */ - -/** - * @brief This function allows to get the handle number from instance. - * @param pInstance MDF instance. - * @retval Instance number. - */ -static uint32_t MDF_GetHandleNumberFromInstance(const MDF_Filter_TypeDef *const pInstance) -{ - uint32_t handle_number; - - /* Get handle number from instance */ - if (pInstance == MDF1_Filter0) - { - handle_number = 0U; - } - else if (pInstance == MDF1_Filter1) - { - handle_number = 1U; - } -#if !defined(STM32U535xx) && !defined(STM32U545xx) - else if (pInstance == MDF1_Filter2) - { - handle_number = 2U; - } - else if (pInstance == MDF1_Filter3) - { - handle_number = 3U; - } - else if (pInstance == MDF1_Filter4) - { - handle_number = 4U; - } - else if (pInstance == MDF1_Filter5) - { - handle_number = 5U; - } - else /* ADF1_Filter0 */ - { - handle_number = 6U; - } -#else /* !defined(STM32U535xx) && !defined(STM32U545xx) */ - else /* ADF1_Filter0 */ - { - handle_number = 2U; - } -#endif /* !defined(STM32U535xx) && !defined(STM32U545xx) */ - - return handle_number; -} - -/** - * @brief This function allows to configure filter and start acquisition. - * @param hmdf MDF handle. - * @param pFilterConfig Filter configuration parameters. - * @retval None. - */ -static void MDF_AcqStart(MDF_HandleTypeDef *const hmdf, const MDF_FilterConfigTypeDef *const pFilterConfig) -{ - uint32_t register_gain_value; - - /* Configure acquisition mode, discard samples, trigger and fifo threshold */ - assert_param(IS_MDF_DISCARD_SAMPLES(pFilterConfig->DiscardSamples)); - assert_param(IS_MDF_FIFO_THRESHOLD(pFilterConfig->FifoThreshold)); - if ((pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_CONT) || - (pFilterConfig->AcquisitionMode == MDF_MODE_ASYNC_SINGLE)) - { - /* Trigger parameters are not used */ - hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | - (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos)); - } - else - { - /* Trigger parameters are used */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_ADF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source)); - } - else - { - assert_param(IS_MDF_TRIGGER_SOURCE(pFilterConfig->Trigger.Source)); - } - assert_param(IS_MDF_TRIGGER_EDGE(pFilterConfig->Trigger.Edge)); - hmdf->Instance->DFLTCR |= (pFilterConfig->AcquisitionMode | pFilterConfig->FifoThreshold | - pFilterConfig->Trigger.Source | pFilterConfig->Trigger.Edge | - (pFilterConfig->DiscardSamples << MDF_DFLTCR_NBDIS_Pos)); - } - - /* Configure if needed snapshot format only for MDF instance */ - if (IS_MDF_INSTANCE(hmdf->Instance) && (pFilterConfig->AcquisitionMode == MDF_MODE_SYNC_SNAPSHOT)) - { - assert_param(IS_MDF_SNAPSHOT_FORMAT(pFilterConfig->SnapshotFormat)); - hmdf->Instance->DFLTCR |= pFilterConfig->SnapshotFormat; - } - - /* Configure data source, CIC mode, decimation ratio and gain */ - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_ADF_DATA_SOURCE(pFilterConfig->DataSource)); - assert_param(IS_ADF_CIC_MODE(pFilterConfig->CicMode)); - } - else - { - assert_param(IS_MDF_DATA_SOURCE(pFilterConfig->DataSource)); - } - assert_param(IS_MDF_DECIMATION_RATIO(pFilterConfig->DecimationRatio)); - assert_param(IS_MDF_GAIN(pFilterConfig->Gain)); - if (pFilterConfig->Gain < 0) - { - int32_t adjust_gain; - - /* adjust gain value to set on register for negative value (offset of -16) */ - adjust_gain = pFilterConfig->Gain - 16; - register_gain_value = ((uint32_t) adjust_gain & 0x3FU); - } - else - { - /* for positive value, no offset to apply */ - register_gain_value = (uint32_t) pFilterConfig->Gain; - } - hmdf->Instance->DFLTCICR = (pFilterConfig->DataSource | pFilterConfig->CicMode | - ((pFilterConfig->DecimationRatio - 1U) << MDF_DFLTCICR_MCICD_Pos) | - (register_gain_value << MDF_DFLTCICR_SCALE_Pos)); - - /* Configure bitstream delay */ - assert_param(IS_MDF_DELAY(pFilterConfig->Delay)); - hmdf->Instance->DLYCR = pFilterConfig->Delay; - - /* Configure offset compensation only for MDF instance */ - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_MDF_OFFSET(pFilterConfig->Offset)); - hmdf->Instance->OECCR = (uint32_t) pFilterConfig->Offset; - } - - /* Configure reshape filter */ - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->ReshapeFilter.Activation)); - hmdf->Instance->DFLTRSFR = 0U; - if (pFilterConfig->ReshapeFilter.Activation == ENABLE) - { - /* Configure reshape filter decimation ratio */ - assert_param(IS_MDF_RSF_DECIMATION_RATIO(pFilterConfig->ReshapeFilter.DecimationRatio)); - hmdf->Instance->DFLTRSFR |= pFilterConfig->ReshapeFilter.DecimationRatio; - } - else - { - /* Bypass reshape filter */ - hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_RSFLTBYP; - } - - /* Configure high-pass filter */ - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->HighPassFilter.Activation)); - if (pFilterConfig->HighPassFilter.Activation == ENABLE) - { - /* Configure high-pass filter cut-off frequency */ - assert_param(IS_MDF_HPF_CUTOFF_FREQ(pFilterConfig->HighPassFilter.CutOffFrequency)); - hmdf->Instance->DFLTRSFR |= pFilterConfig->HighPassFilter.CutOffFrequency; - } - else - { - /* Bypass high-pass filter */ - hmdf->Instance->DFLTRSFR |= MDF_DFLTRSFR_HPFBYP; - } - - /* Configure integrator only for MDF instance */ - if (IS_MDF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->Integrator.Activation)); - if (pFilterConfig->Integrator.Activation == ENABLE) - { - /* Configure integrator value and output division */ - assert_param(IS_MDF_INTEGRATOR_VALUE(pFilterConfig->Integrator.Value)); - assert_param(IS_MDF_INTEGRATOR_OUTPUT_DIV(pFilterConfig->Integrator.OutputDivision)); - hmdf->Instance->DFLTINTR = (((pFilterConfig->Integrator.Value - 1U) << MDF_DFLTINTR_INTVAL_Pos) | - pFilterConfig->Integrator.OutputDivision); - } - else - { - /* Bypass integrator */ - hmdf->Instance->DFLTINTR = 0U; - } - } - - if (IS_ADF_INSTANCE(hmdf->Instance)) - { - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Activation)); - if (pFilterConfig->SoundActivity.Activation == ENABLE) - { - /* Configure SAD mode, frame size, hysteresis, sound trigger event - and data memory transfer only for ADF instance */ - assert_param(IS_MDF_SAD_MODE(pFilterConfig->SoundActivity.Mode)); - assert_param(IS_MDF_SAD_FRAME_SIZE(pFilterConfig->SoundActivity.FrameSize)); - if (pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) - { - assert_param(IS_FUNCTIONAL_STATE(pFilterConfig->SoundActivity.Hysteresis)); - } - assert_param(IS_MDF_SAD_SOUND_TRIGGER(pFilterConfig->SoundActivity.SoundTriggerEvent)); - assert_param(IS_MDF_SAD_DATA_MEMORY_TRANSFER(pFilterConfig->SoundActivity.DataMemoryTransfer)); - if ((pFilterConfig->SoundActivity.Mode != MDF_SAD_AMBIENT_NOISE_DETECTOR) && - (pFilterConfig->SoundActivity.Hysteresis == ENABLE)) - { - hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize | - MDF_SADCR_HYSTEN | pFilterConfig->SoundActivity.SoundTriggerEvent | - pFilterConfig->SoundActivity.DataMemoryTransfer); - } - else - { - hmdf->Instance->SADCR = (pFilterConfig->SoundActivity.Mode | pFilterConfig->SoundActivity.FrameSize | - pFilterConfig->SoundActivity.SoundTriggerEvent | - pFilterConfig->SoundActivity.DataMemoryTransfer); - } - - /* Configure SAD minimum noise level, hangover window, learning frames, - ambient noise slope control and signal noise threshold only for ADF instance */ - assert_param(IS_MDF_SAD_MIN_NOISE_LEVEL(pFilterConfig->SoundActivity.MinNoiseLevel)); - assert_param(IS_MDF_SAD_HANGOVER_WINDOW(pFilterConfig->SoundActivity.HangoverWindow)); - assert_param(IS_MDF_SAD_LEARNING_FRAMES(pFilterConfig->SoundActivity.LearningFrames)); - assert_param(IS_MDF_SAD_SIGNAL_NOISE_THRESHOLD(pFilterConfig->SoundActivity.SignalNoiseThreshold)); - if (pFilterConfig->SoundActivity.Mode != MDF_SAD_SOUND_DETECTOR) - { - assert_param(IS_MDF_SAD_AMBIENT_NOISE_SLOPE(pFilterConfig->SoundActivity.AmbientNoiseSlope)); - hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) | - pFilterConfig->SoundActivity.HangoverWindow | - pFilterConfig->SoundActivity.LearningFrames | - (pFilterConfig->SoundActivity.AmbientNoiseSlope << MDF_SADCFGR_ANSLP_Pos) | - pFilterConfig->SoundActivity.SignalNoiseThreshold); - } - else - { - hmdf->Instance->SADCFGR = ((pFilterConfig->SoundActivity.MinNoiseLevel << MDF_SADCFGR_ANMIN_Pos) | - pFilterConfig->SoundActivity.HangoverWindow | - pFilterConfig->SoundActivity.LearningFrames | - pFilterConfig->SoundActivity.SignalNoiseThreshold); - } - } - else - { - /* SAD is not used */ - hmdf->Instance->SADCR = 0U; - hmdf->Instance->SADCFGR = 0U; - } - } - - /* Update instance state */ - hmdf->State = HAL_MDF_STATE_ACQUISITION; - - /* Enable sound activity detector if needed only for ADF instance */ - if ((IS_ADF_INSTANCE(hmdf->Instance)) && (pFilterConfig->SoundActivity.Activation == ENABLE)) - { - hmdf->Instance->SADCR |= MDF_SADCR_SADEN; - } - - /* Enable filter */ - hmdf->Instance->DFLTCR |= MDF_DFLTCR_DFLTEN; -} - -/** - * @brief This function handles DMA transfer complete callback. - * @param hdma DMA handle. - * @retval None. - */ -static void MDF_DmaXferCpltCallback(DMA_HandleTypeDef *hdma) -{ - MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Check if DMA in circular mode */ - if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) - { - hmdf->State = HAL_MDF_STATE_READY; - } - -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->AcqCpltCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_AcqCpltCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -} - -/** - * @brief This function handles DMA half transfer complete callback. - * @param hdma DMA handle. - * @retval None. - */ -static void MDF_DmaXferHalfCpltCallback(DMA_HandleTypeDef *hdma) -{ - MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->AcqHalfCpltCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_AcqHalfCpltCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -} - -/** - * @brief This function handles DMA error callback. - * @param hdma DMA handle. - * @retval None. - */ -static void MDF_DmaErrorCallback(DMA_HandleTypeDef *hdma) -{ - MDF_HandleTypeDef *hmdf = (MDF_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Update error code */ - hmdf->ErrorCode |= MDF_ERROR_DMA; - -#if (USE_HAL_MDF_REGISTER_CALLBACKS == 1) - hmdf->ErrorCallback(hmdf); -#else /* USE_HAL_MDF_REGISTER_CALLBACKS */ - HAL_MDF_ErrorCallback(hmdf); -#endif /* USE_HAL_MDF_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -#endif /* HAL_MDF_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c deleted file mode 100644 index 1a4a2077a..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_ospi.c +++ /dev/null @@ -1,3511 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_ospi.c - * @author MCD Application Team - * @brief OSPI HAL module driver. - This file provides firmware functions to manage the following - functionalities of the OctoSPI interface (OSPI). - + Initialization and de-initialization functions - + Hyperbus configuration - + Indirect functional mode management - + Memory-mapped functional mode management - + Auto-polling functional mode management - + Interrupts and flags management - + DMA channel configuration for indirect functional mode - + Errors management and abort functionality - + IO manager configuration - - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - *** Initialization *** - ====================== - [..] - As prerequisite, fill in the HAL_OSPI_MspInit() : - (+) Enable OctoSPI and OctoSPIM clocks interface with __HAL_RCC_OSPIx_CLK_ENABLE(). - (+) Reset OctoSPI Peripheral with __HAL_RCC_OSPIx_FORCE_RESET() and __HAL_RCC_OSPIx_RELEASE_RESET(). - (+) Enable the clocks for the OctoSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE(). - (+) Configure these OctoSPI pins in alternate mode using HAL_GPIO_Init(). - (+) If interrupt or DMA mode is used, enable and configure OctoSPI global - interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - (+) If DMA mode is used, enable the clocks for the OctoSPI DMA channel - with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(), - link it with OctoSPI handle using __HAL_LINKDMA(), enable and configure - DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ(). - [..] - Configure the fifo threshold, the dual-quad mode, the memory type, the - device size, the CS high time, the free running clock, the clock mode, - the wrap size, the clock prescaler, the sample shifting, the hold delay - and the CS boundary using the HAL_OSPI_Init() function. - [..] - When using Hyperbus, configure the RW recovery time, the access time, - the write latency and the latency mode using the HAL_OSPI_HyperbusCfg() - function. - - *** Indirect functional mode *** - ================================ - [..] - In regular mode, configure the command sequence using the HAL_OSPI_Command() - or HAL_OSPI_Command_IT() functions : - (+) Instruction phase : the mode used and if present the size, the instruction - opcode and the DTR mode. - (+) Address phase : the mode used and if present the size, the address - value and the DTR mode. - (+) Alternate-bytes phase : the mode used and if present the size, the - alternate bytes values and the DTR mode. - (+) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase). - (+) Data phase : the mode used and if present the number of bytes and the DTR mode. - (+) Data strobe (DQS) mode : the activation (or not) of this mode - (+) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode. - (+) Flash identifier : in dual-quad mode, indicates which flash is concerned - (+) Operation type : always common configuration - [..] - In Hyperbus mode, configure the command sequence using the HAL_OSPI_HyperbusCmd() - function : - (+) Address space : indicate if the access will be done in register or memory - (+) Address size - (+) Number of data - (+) Data strobe (DQS) mode : the activation (or not) of this mode - [..] - If no data is required for the command (only for regular mode, not for - Hyperbus mode), it is sent directly to the memory : - (+) In polling mode, the output of the function is done when the transfer is complete. - (+) In interrupt mode, HAL_OSPI_CmdCpltCallback() will be called when the transfer is complete. - [..] - For the indirect write mode, use HAL_OSPI_Transmit(), HAL_OSPI_Transmit_DMA() or - HAL_OSPI_Transmit_IT() after the command configuration : - (+) In polling mode, the output of the function is done when the transfer is complete. - (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - (+) In DMA mode, HAL_OSPI_TxHalfCpltCallback() will be called at the half transfer and - HAL_OSPI_TxCpltCallback() will be called when the transfer is complete. - [..] - For the indirect read mode, use HAL_OSPI_Receive(), HAL_OSPI_Receive_DMA() or - HAL_OSPI_Receive_IT() after the command configuration : - (+) In polling mode, the output of the function is done when the transfer is complete. - (+) In interrupt mode, HAL_OSPI_FifoThresholdCallback() will be called when the fifo threshold - is reached and HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. - (+) In DMA mode, HAL_OSPI_RxHalfCpltCallback() will be called at the half transfer and - HAL_OSPI_RxCpltCallback() will be called when the transfer is complete. - - *** Auto-polling functional mode *** - ==================================== - [..] - Configure the command sequence by the same way than the indirect mode - [..] - Configure the auto-polling functional mode using the HAL_OSPI_AutoPolling() - or HAL_OSPI_AutoPolling_IT() functions : - (+) The size of the status bytes, the match value, the mask used, the match mode (OR/AND), - the polling interval and the automatic stop activation. - [..] - After the configuration : - (+) In polling mode, the output of the function is done when the status match is reached. The - automatic stop is activated to avoid an infinite loop. - (+) In interrupt mode, HAL_OSPI_StatusMatchCallback() will be called each time the status match is reached. - - *** Memory-mapped functional mode *** - ===================================== - [..] - Configure the command sequence by the same way than the indirect mode except - for the operation type in regular mode : - (+) Operation type equals to read configuration : the command configuration - applies to read access in memory-mapped mode - (+) Operation type equals to write configuration : the command configuration - applies to write access in memory-mapped mode - (+) Both read and write configuration should be performed before activating - memory-mapped mode - [..] - Configure the memory-mapped functional mode using the HAL_OSPI_MemoryMapped() - functions : - (+) The timeout activation and the timeout period. - [..] - After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on - the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. - - *** Errors management and abort functionality *** - ================================================= - [..] - HAL_OSPI_GetError() function gives the error raised during the last operation. - [..] - HAL_OSPI_Abort() and HAL_OSPI_AbortIT() functions aborts any on-going operation and - flushes the fifo : - (+) In polling mode, the output of the function is done when the transfer - complete bit is set and the busy bit cleared. - (+) In interrupt mode, HAL_OSPI_AbortCpltCallback() will be called when - the transfer complete bit is set. - - *** Control functions *** - ========================= - [..] - HAL_OSPI_GetState() function gives the current state of the HAL OctoSPI driver. - [..] - HAL_OSPI_SetTimeout() function configures the timeout value used in the driver. - [..] - HAL_OSPI_SetFifoThreshold() function configures the threshold on the Fifo of the OSPI Peripheral. - [..] - HAL_OSPI_GetFifoThreshold() function gives the current of the Fifo's threshold - - *** IO manager configuration functions *** - ========================================== - [..] - HAL_OSPIM_Config() function configures the IO manager for the OctoSPI instance. - - *** Callback registration *** - ============================================= - [..] - The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use function HAL_OSPI_RegisterCallback() to register a user callback, - it allows to register following callbacks: - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) FifoThresholdCallback : callback when the fifo threshold is reached. - (+) CmdCpltCallback : callback when a command without data is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. - (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. - (+) StatusMatchCallback : callback when a status match occurs. - (+) TimeOutCallback : callback when the timeout perioed expires. - (+) MspInitCallback : OSPI MspInit. - (+) MspDeInitCallback : OSPI MspDeInit. - [..] - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_OSPI_UnRegisterCallback() to reset a callback to the default - weak (overridden) function. It allows to reset following callbacks: - (+) ErrorCallback : callback when error occurs. - (+) AbortCpltCallback : callback when abort is completed. - (+) FifoThresholdCallback : callback when the fifo threshold is reached. - (+) CmdCpltCallback : callback when a command without data is completed. - (+) RxCpltCallback : callback when a reception transfer is completed. - (+) TxCpltCallback : callback when a transmission transfer is completed. - (+) RxHalfCpltCallback : callback when half of the reception transfer is completed. - (+) TxHalfCpltCallback : callback when half of the transmission transfer is completed. - (+) StatusMatchCallback : callback when a status match occurs. - (+) TimeOutCallback : callback when the timeout perioed expires. - (+) MspInitCallback : OSPI MspInit. - (+) MspDeInitCallback : OSPI MspDeInit. - [..] - This function) takes as parameters the HAL peripheral handle and the Callback ID. - - [..] - By default, after the HAL_OSPI_Init() and if the state is HAL_OSPI_STATE_RESET - all callbacks are reset to the corresponding legacy weak (overridden) functions. - Exception done for MspInit and MspDeInit callbacks that are respectively - reset to the legacy weak (overridden) functions in the HAL_OSPI_Init() - and HAL_OSPI_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_OSPI_Init() and HAL_OSPI_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) - - [..] - Callbacks can be registered/unregistered in READY state only. - Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered - in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used - during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_OSPI_RegisterCallback() before calling HAL_OSPI_DeInit() - or HAL_OSPI_Init() function. - - [..] - When The compilation define USE_HAL_OSPI_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registering feature is not available - and weak (overridden) callbacks are used. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -#if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup OSPI OSPI - * @brief OSPI HAL module driver - * @{ - */ - -#ifdef HAL_OSPI_MODULE_ENABLED - -/** - @cond 0 - */ -/* Private typedef -----------------------------------------------------------*/ - -/* Private define ------------------------------------------------------------*/ -#define OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000) /*!< Indirect write mode */ -#define OSPI_FUNCTIONAL_MODE_INDIRECT_READ ((uint32_t)OCTOSPI_CR_FMODE_0) /*!< Indirect read mode */ -#define OSPI_FUNCTIONAL_MODE_AUTO_POLLING ((uint32_t)OCTOSPI_CR_FMODE_1) /*!< Automatic polling mode */ -#define OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED ((uint32_t)OCTOSPI_CR_FMODE) /*!< Memory-mapped mode */ - -#define OSPI_CFG_STATE_MASK 0x00000004U -#define OSPI_BUSY_STATE_MASK 0x00000008U - -#define OSPI_NB_INSTANCE 2U -#define OSPI_IOM_NB_PORTS 2U -#define OSPI_IOM_PORT_MASK 0x1U - -/* Private macro -------------------------------------------------------------*/ -#define IS_OSPI_FUNCTIONAL_MODE(MODE) (((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \ - ((MODE) == OSPI_FUNCTIONAL_MODE_INDIRECT_READ) || \ - ((MODE) == OSPI_FUNCTIONAL_MODE_AUTO_POLLING) || \ - ((MODE) == OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)) - -/* Private variables ---------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -static void OSPI_DMACplt(DMA_HandleTypeDef *hdma); -static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma); -static void OSPI_DMAError(DMA_HandleTypeDef *hdma); -static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, FlagStatus State, - uint32_t Tickstart, uint32_t Timeout); -static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); -#if defined (OCTOSPIM) -static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg); -#endif /* OCTOSPIM */ -/** - @endcond - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup OSPI_Exported_Functions OSPI Exported Functions - * @{ - */ - -/** @defgroup OSPI_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Initialize the OctoSPI. - (+) De-initialize the OctoSPI. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the OSPI mode according to the specified parameters - * in the OSPI_InitTypeDef and initialize the associated handle. - * @param hospi : OSPI handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Init(OSPI_HandleTypeDef *hospi) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart = HAL_GetTick(); - - /* Check the OSPI handle allocation */ - if (hospi == NULL) - { - status = HAL_ERROR; - /* No error code can be set set as the handler is null */ - } - else - { - /* Check the parameters of the initialization structure */ - assert_param(IS_OSPI_FIFO_THRESHOLD(hospi->Init.FifoThreshold)); - assert_param(IS_OSPI_DUALQUAD_MODE(hospi->Init.DualQuad)); - assert_param(IS_OSPI_MEMORY_TYPE(hospi->Init.MemoryType)); - assert_param(IS_OSPI_DEVICE_SIZE(hospi->Init.DeviceSize)); - assert_param(IS_OSPI_CS_HIGH_TIME(hospi->Init.ChipSelectHighTime)); - assert_param(IS_OSPI_FREE_RUN_CLK(hospi->Init.FreeRunningClock)); - assert_param(IS_OSPI_CLOCK_MODE(hospi->Init.ClockMode)); - assert_param(IS_OSPI_WRAP_SIZE(hospi->Init.WrapSize)); - assert_param(IS_OSPI_CLK_PRESCALER(hospi->Init.ClockPrescaler)); - assert_param(IS_OSPI_SAMPLE_SHIFTING(hospi->Init.SampleShifting)); - assert_param(IS_OSPI_DHQC(hospi->Init.DelayHoldQuarterCycle)); - assert_param(IS_OSPI_CS_BOUNDARY(hospi->Init.ChipSelectBoundary)); - assert_param(IS_OSPI_DLYBYP(hospi->Init.DelayBlockBypass)); - assert_param(IS_OSPI_MAXTRAN(hospi->Init.MaxTran)); - - /* Initialize error code */ - hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - - /* Check if the state is the reset state */ - if (hospi->State == HAL_OSPI_STATE_RESET) - { -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - /* Reset Callback pointers in HAL_OSPI_STATE_RESET only */ - hospi->ErrorCallback = HAL_OSPI_ErrorCallback; - hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; - hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback; - hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback; - hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback; - hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback; - hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback; - hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback; - hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback; - hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback; - - if (hospi->MspInitCallback == NULL) - { - hospi->MspInitCallback = HAL_OSPI_MspInit; - } - - /* Init the low level hardware */ - hospi->MspInitCallback(hospi); -#else - /* Initialization of the low level hardware */ - HAL_OSPI_MspInit(hospi); -#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - - /* Configure the default timeout for the OSPI memory access */ - (void)HAL_OSPI_SetTimeout(hospi, HAL_OSPI_TIMEOUT_DEFAULT_VALUE); - - /* Configure memory type, device size, chip select high time, delay block bypass, - free running clock, clock mode */ - MODIFY_REG(hospi->Instance->DCR1, - (OCTOSPI_DCR1_MTYP | OCTOSPI_DCR1_DEVSIZE | OCTOSPI_DCR1_CSHT | OCTOSPI_DCR1_DLYBYP | - OCTOSPI_DCR1_FRCK | OCTOSPI_DCR1_CKMODE), - (hospi->Init.MemoryType | ((hospi->Init.DeviceSize - 1U) << OCTOSPI_DCR1_DEVSIZE_Pos) | - ((hospi->Init.ChipSelectHighTime - 1U) << OCTOSPI_DCR1_CSHT_Pos) | - hospi->Init.DelayBlockBypass | hospi->Init.ClockMode)); - - /* Configure wrap size */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_WRAPSIZE, hospi->Init.WrapSize); - - /* Configure chip select boundary and maximum transfer */ - hospi->Instance->DCR3 = ((hospi->Init.ChipSelectBoundary << OCTOSPI_DCR3_CSBOUND_Pos) | - (hospi->Init.MaxTran << OCTOSPI_DCR3_MAXTRAN_Pos)); - - /* Configure refresh */ - hospi->Instance->DCR4 = hospi->Init.Refresh; - - /* Configure FIFO threshold */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos)); - - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - - if (status == HAL_OK) - { - /* Configure clock prescaler */ - MODIFY_REG(hospi->Instance->DCR2, OCTOSPI_DCR2_PRESCALER, - ((hospi->Init.ClockPrescaler - 1U) << OCTOSPI_DCR2_PRESCALER_Pos)); - - /* Configure Dual Quad mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_DMM, hospi->Init.DualQuad); - - /* Configure sample shifting and delay hold quarter cycle */ - MODIFY_REG(hospi->Instance->TCR, (OCTOSPI_TCR_SSHIFT | OCTOSPI_TCR_DHQC), - (hospi->Init.SampleShifting | hospi->Init.DelayHoldQuarterCycle)); - - /* Enable OctoSPI */ - __HAL_OSPI_ENABLE(hospi); - - /* Enable free running clock if needed : must be done after OSPI enable */ - if (hospi->Init.FreeRunningClock == HAL_OSPI_FREERUNCLK_ENABLE) - { - SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - } - - /* Initialize the OSPI state */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - hospi->State = HAL_OSPI_STATE_HYPERBUS_INIT; - } - else - { - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Initialize the OSPI MSP. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_MspInit(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_OSPI_MspInit can be implemented in the user file - */ -} - -/** - * @brief De-Initialize the OSPI peripheral. - * @param hospi : OSPI handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_DeInit(OSPI_HandleTypeDef *hospi) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the OSPI handle allocation */ - if (hospi == NULL) - { - status = HAL_ERROR; - /* No error code can be set set as the handler is null */ - } - else - { - /* Disable OctoSPI */ - __HAL_OSPI_DISABLE(hospi); - - /* Disable free running clock if needed : must be done after OSPI disable */ - CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - if (hospi->MspDeInitCallback == NULL) - { - hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; - } - - /* DeInit the low level hardware */ - hospi->MspDeInitCallback(hospi); -#else - /* De-initialize the low-level hardware */ - HAL_OSPI_MspDeInit(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - - /* Reset the driver state */ - hospi->State = HAL_OSPI_STATE_RESET; - } - - return status; -} - -/** - * @brief DeInitialize the OSPI MSP. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_OSPI_MspDeInit can be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup OSPI_Exported_Functions_Group2 Input and Output operation functions - * @brief OSPI Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Handle the interrupts. - (+) Handle the command sequence (regular and Hyperbus). - (+) Handle the Hyperbus configuration. - (+) Transmit data in blocking, interrupt or DMA mode. - (+) Receive data in blocking, interrupt or DMA mode. - (+) Manage the auto-polling functional mode. - (+) Manage the memory-mapped functional mode. - -@endverbatim - * @{ - */ - -/** - * @brief Handle OSPI interrupt request. - * @param hospi : OSPI handle - * @retval None - */ -void HAL_OSPI_IRQHandler(OSPI_HandleTypeDef *hospi) -{ - __IO uint32_t *data_reg = &hospi->Instance->DR; - uint32_t flag = hospi->Instance->SR; - uint32_t itsource = hospi->Instance->CR; - uint32_t currentstate = hospi->State; - - /* OctoSPI fifo threshold interrupt occurred -------------------------------*/ - if (((flag & HAL_OSPI_FLAG_FT) != 0U) && ((itsource & HAL_OSPI_IT_FT) != 0U)) - { - if (currentstate == HAL_OSPI_STATE_BUSY_TX) - { - /* Write a data in the fifo */ - *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; - hospi->pBuffPtr++; - hospi->XferCount--; - } - else if (currentstate == HAL_OSPI_STATE_BUSY_RX) - { - /* Read a data from the fifo */ - *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); - hospi->pBuffPtr++; - hospi->XferCount--; - } - else - { - /* Nothing to do */ - } - - if (hospi->XferCount == 0U) - { - /* All data have been received or transmitted for the transfer */ - /* Disable fifo threshold interrupt */ - __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_FT); - } - - /* Fifo threshold callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->FifoThresholdCallback(hospi); -#else - HAL_OSPI_FifoThresholdCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ - } - /* OctoSPI transfer complete interrupt occurred ----------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TC) != 0U) && ((itsource & HAL_OSPI_IT_TC) != 0U)) - { - if (currentstate == HAL_OSPI_STATE_BUSY_RX) - { - if ((hospi->XferCount > 0U) && ((flag & OCTOSPI_SR_FLEVEL) != 0U)) - { - /* Read the last data received in the fifo */ - *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); - hospi->pBuffPtr++; - hospi->XferCount--; - } - else if (hospi->XferCount == 0U) - { - /* Clear flag */ - hospi->Instance->FCR = HAL_OSPI_FLAG_TC; - - /* Disable the interrupts */ - __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* RX complete callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->RxCpltCallback(hospi); -#else - HAL_OSPI_RxCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - else - { - /* Nothing to do */ - } - } - else - { - /* Clear flag */ - hospi->Instance->FCR = HAL_OSPI_FLAG_TC; - - /* Disable the interrupts */ - __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - if (currentstate == HAL_OSPI_STATE_BUSY_TX) - { - /* TX complete callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->TxCpltCallback(hospi); -#else - HAL_OSPI_TxCpltCallback(hospi); -#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - else if (currentstate == HAL_OSPI_STATE_BUSY_CMD) - { - /* Command complete callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->CmdCpltCallback(hospi); -#else - HAL_OSPI_CmdCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - else if (currentstate == HAL_OSPI_STATE_ABORT) - { - if (hospi->ErrorCode == HAL_OSPI_ERROR_NONE) - { - /* Abort called by the user */ - /* Abort complete callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->AbortCpltCallback(hospi); -#else - HAL_OSPI_AbortCpltCallback(hospi); -#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ - } - else - { - /* Abort due to an error (eg : DMA error) */ - /* Error callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->ErrorCallback(hospi); -#else - HAL_OSPI_ErrorCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - } - else - { - /* Nothing to do */ - } - } - } - /* OctoSPI status match interrupt occurred ---------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_SM) != 0U) && ((itsource & HAL_OSPI_IT_SM) != 0U)) - { - /* Clear flag */ - hospi->Instance->FCR = HAL_OSPI_FLAG_SM; - - /* Check if automatic poll mode stop is activated */ - if ((hospi->Instance->CR & OCTOSPI_CR_APMS) != 0U) - { - /* Disable the interrupts */ - __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - } - - /* Status match callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->StatusMatchCallback(hospi); -#else - HAL_OSPI_StatusMatchCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - /* OctoSPI transfer error interrupt occurred -------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TE) != 0U) && ((itsource & HAL_OSPI_IT_TE) != 0U)) - { - /* Clear flag */ - hospi->Instance->FCR = HAL_OSPI_FLAG_TE; - - /* Disable all interrupts */ - __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); - - /* Set error code */ - hospi->ErrorCode = HAL_OSPI_ERROR_TRANSFER; - - /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer on the OctoSPI side */ - CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - - /* Disable the DMA transfer on the DMA side */ - hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; - if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Error callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->ErrorCallback(hospi); -#else - HAL_OSPI_ErrorCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ - } - } - else - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Error callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->ErrorCallback(hospi); -#else - HAL_OSPI_ErrorCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - } - /* OctoSPI timeout interrupt occurred --------------------------------------*/ - else if (((flag & HAL_OSPI_FLAG_TO) != 0U) && ((itsource & HAL_OSPI_IT_TO) != 0U)) - { - /* Clear flag */ - hospi->Instance->FCR = HAL_OSPI_FLAG_TO; - - /* Timeout callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->TimeOutCallback(hospi); -#else - HAL_OSPI_TimeOutCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - else - { - /* Nothing to do */ - } -} - -/** - * @brief Set the command configuration. - * @param hospi : OSPI handle - * @param cmd : structure that contains the command configuration information - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Command(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t state; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters of the command structure */ - assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); - - if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) - { - assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); - } - - assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) - { - assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize)); - assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); - } - - assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) - { - assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize)); - assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode)); - } - - assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode)); - if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize)); - assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode)); - } - - assert_param(IS_OSPI_DATA_MODE(cmd->DataMode)); - if (cmd->DataMode != HAL_OSPI_DATA_NONE) - { - if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) - { - assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData)); - } - assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode)); - assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles)); - } - - assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode)); - assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); - - /* Check the state of the driver */ - state = hospi->State; - if (((state == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) || - ((state == HAL_OSPI_STATE_READ_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) - || (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG))) || - ((state == HAL_OSPI_STATE_WRITE_CMD_CFG) && ((cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) || - (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG)))) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Initialize error code */ - hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - - /* Configure the registers */ - status = OSPI_ConfigCmd(hospi, cmd); - - if (status == HAL_OK) - { - if (cmd->DataMode == HAL_OSPI_DATA_NONE) - { - /* When there is no data phase, the transfer start as soon as the configuration is done - so wait until TC flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - } - else - { - /* Update the state */ - if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) - { - hospi->State = HAL_OSPI_STATE_CMD_CFG; - } - else if (cmd->OperationType == HAL_OSPI_OPTYPE_READ_CFG) - { - if (hospi->State == HAL_OSPI_STATE_WRITE_CMD_CFG) - { - hospi->State = HAL_OSPI_STATE_CMD_CFG; - } - else - { - hospi->State = HAL_OSPI_STATE_READ_CMD_CFG; - } - } - else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) - { - if (hospi->State == HAL_OSPI_STATE_READ_CMD_CFG) - { - hospi->State = HAL_OSPI_STATE_CMD_CFG; - } - else - { - hospi->State = HAL_OSPI_STATE_WRITE_CMD_CFG; - } - } - else - { - /* Wrap configuration, no state change */ - } - } - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Set the command configuration in interrupt mode. - * @param hospi : OSPI handle - * @param cmd : structure that contains the command configuration information - * @note This function is used only in Indirect Read or Write Modes - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Command_IT(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters of the command structure */ - assert_param(IS_OSPI_OPERATION_TYPE(cmd->OperationType)); - - if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) - { - assert_param(IS_OSPI_FLASH_ID(cmd->FlashId)); - } - - assert_param(IS_OSPI_INSTRUCTION_MODE(cmd->InstructionMode)); - if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) - { - assert_param(IS_OSPI_INSTRUCTION_SIZE(cmd->InstructionSize)); - assert_param(IS_OSPI_INSTRUCTION_DTR_MODE(cmd->InstructionDtrMode)); - } - - assert_param(IS_OSPI_ADDRESS_MODE(cmd->AddressMode)); - if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) - { - assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize)); - assert_param(IS_OSPI_ADDRESS_DTR_MODE(cmd->AddressDtrMode)); - } - - assert_param(IS_OSPI_ALT_BYTES_MODE(cmd->AlternateBytesMode)); - if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) - { - assert_param(IS_OSPI_ALT_BYTES_SIZE(cmd->AlternateBytesSize)); - assert_param(IS_OSPI_ALT_BYTES_DTR_MODE(cmd->AlternateBytesDtrMode)); - } - - assert_param(IS_OSPI_DATA_MODE(cmd->DataMode)); - if (cmd->DataMode != HAL_OSPI_DATA_NONE) - { - assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData)); - assert_param(IS_OSPI_DATA_DTR_MODE(cmd->DataDtrMode)); - assert_param(IS_OSPI_DUMMY_CYCLES(cmd->DummyCycles)); - } - - assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode)); - assert_param(IS_OSPI_SIOO_MODE(cmd->SIOOMode)); - - /* Check the state of the driver */ - if ((hospi->State == HAL_OSPI_STATE_READY) && (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) && - (cmd->DataMode == HAL_OSPI_DATA_NONE) && (hospi->Init.MemoryType != HAL_OSPI_MEMTYPE_HYPERBUS)) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - - if (status == HAL_OK) - { - /* Initialize error code */ - hospi->ErrorCode = HAL_OSPI_ERROR_NONE; - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); - - /* Configure the registers */ - status = OSPI_ConfigCmd(hospi, cmd); - - if (status == HAL_OK) - { - /* Update the state */ - hospi->State = HAL_OSPI_STATE_BUSY_CMD; - - /* Enable the transfer complete and transfer error interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_TE); - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the Hyperbus parameters. - * @param hospi : OSPI handle - * @param cfg : Structure containing the Hyperbus configuration - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_HyperbusCfg(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t state; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters of the hyperbus configuration structure */ - assert_param(IS_OSPI_RW_RECOVERY_TIME(cfg->RWRecoveryTime)); - assert_param(IS_OSPI_ACCESS_TIME(cfg->AccessTime)); - assert_param(IS_OSPI_WRITE_ZERO_LATENCY(cfg->WriteZeroLatency)); - assert_param(IS_OSPI_LATENCY_MODE(cfg->LatencyMode)); - - /* Check the state of the driver */ - state = hospi->State; - if ((state == HAL_OSPI_STATE_HYPERBUS_INIT) || (state == HAL_OSPI_STATE_READY)) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Configure Hyperbus configuration Latency register */ - WRITE_REG(hospi->Instance->HLCR, ((cfg->RWRecoveryTime << OCTOSPI_HLCR_TRWR_Pos) | - (cfg->AccessTime << OCTOSPI_HLCR_TACC_Pos) | - cfg->WriteZeroLatency | cfg->LatencyMode)); - - /* Update the state */ - hospi->State = HAL_OSPI_STATE_READY; - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Set the Hyperbus command configuration. - * @param hospi : OSPI handle - * @param cmd : Structure containing the Hyperbus command - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_HyperbusCmd(OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters of the hyperbus command structure */ - assert_param(IS_OSPI_ADDRESS_SPACE(cmd->AddressSpace)); - assert_param(IS_OSPI_ADDRESS_SIZE(cmd->AddressSize)); - assert_param(IS_OSPI_NUMBER_DATA(cmd->NbData)); - assert_param(IS_OSPI_DQS_MODE(cmd->DQSMode)); - - /* Check the state of the driver */ - if ((hospi->State == HAL_OSPI_STATE_READY) && (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS)) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Re-initialize the value of the functional mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); - - /* Configure the address space in the DCR1 register */ - MODIFY_REG(hospi->Instance->DCR1, OCTOSPI_DCR1_MTYP_0, cmd->AddressSpace); - - /* Configure the CCR and WCCR registers with the address size and the following configuration : - - DQS signal enabled (used as RWDS) - - DTR mode enabled on address and data - - address and data on 8 lines */ - WRITE_REG(hospi->Instance->CCR, (cmd->DQSMode | OCTOSPI_CCR_DDTR | OCTOSPI_CCR_DMODE_2 | - cmd->AddressSize | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADMODE_2)); - WRITE_REG(hospi->Instance->WCCR, (cmd->DQSMode | OCTOSPI_WCCR_DDTR | OCTOSPI_WCCR_DMODE_2 | - cmd->AddressSize | OCTOSPI_WCCR_ADDTR | OCTOSPI_WCCR_ADMODE_2)); - - /* Configure the DLR register with the number of data */ - WRITE_REG(hospi->Instance->DLR, (cmd->NbData - 1U)); - - /* Configure the AR register with the address value */ - WRITE_REG(hospi->Instance->AR, cmd->Address); - - /* Update the state */ - hospi->State = HAL_OSPI_STATE_CMD_CFG; - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hospi : OSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration - * @note This function is used only in Indirect Write Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - __IO uint32_t *data_reg = &hospi->Instance->DR; - - /* Check the data pointer allocation */ - if (pData == NULL) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - else - { - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; - hospi->XferSize = hospi->XferCount; - hospi->pBuffPtr = pData; - - /* Configure CR register with functional mode as indirect write */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - do - { - /* Wait till fifo threshold flag is set to send data */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_FT, SET, tickstart, Timeout); - - if (status != HAL_OK) - { - break; - } - - *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; - hospi->pBuffPtr++; - hospi->XferCount--; - } while (hospi->XferCount > 0U); - - if (status == HAL_OK) - { - /* Wait till transfer complete flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hospi : OSPI handle - * @param pData : pointer to data buffer - * @param Timeout : Timeout duration - * @note This function is used only in Indirect Read Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - __IO uint32_t *data_reg = &hospi->Instance->DR; - uint32_t addr_reg = hospi->Instance->AR; - uint32_t ir_reg = hospi->Instance->IR; - - /* Check the data pointer allocation */ - if (pData == NULL) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - else - { - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; - hospi->XferSize = hospi->XferCount; - hospi->pBuffPtr = pData; - - /* Configure CR register with functional mode as indirect read */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - WRITE_REG(hospi->Instance->IR, ir_reg); - } - } - - do - { - /* Wait till fifo threshold or transfer complete flags are set to read received data */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, (HAL_OSPI_FLAG_FT | HAL_OSPI_FLAG_TC), SET, tickstart, Timeout); - - if (status != HAL_OK) - { - break; - } - - *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); - hospi->pBuffPtr++; - hospi->XferCount--; - } while (hospi->XferCount > 0U); - - if (status == HAL_OK) - { - /* Wait till transfer complete flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Send an amount of data in non-blocking mode with interrupt. - * @param hospi : OSPI handle - * @param pData : pointer to data buffer - * @note This function is used only in Indirect Write Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Transmit_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the data pointer allocation */ - if (pData == NULL) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - else - { - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; - hospi->XferSize = hospi->XferCount; - hospi->pBuffPtr = pData; - - /* Configure CR register with functional mode as indirect write */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); - - /* Update the state */ - hospi->State = HAL_OSPI_STATE_BUSY_TX; - - /* Enable the transfer complete, fifo threshold and transfer error interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Receive an amount of data in non-blocking mode with interrupt. - * @param hospi : OSPI handle - * @param pData : pointer to data buffer - * @note This function is used only in Indirect Read Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Receive_IT(OSPI_HandleTypeDef *hospi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t addr_reg = hospi->Instance->AR; - uint32_t ir_reg = hospi->Instance->IR; - - /* Check the data pointer allocation */ - if (pData == NULL) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - else - { - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - /* Configure counters and size */ - hospi->XferCount = READ_REG(hospi->Instance->DLR) + 1U; - hospi->XferSize = hospi->XferCount; - hospi->pBuffPtr = pData; - - /* Configure CR register with functional mode as indirect read */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); - - /* Update the state */ - hospi->State = HAL_OSPI_STATE_BUSY_RX; - - /* Enable the transfer complete, fifo threshold and transfer error interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - WRITE_REG(hospi->Instance->IR, ir_reg); - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Send an amount of data in non-blocking mode with DMA. - * @param hospi : OSPI handle - * @param pData : pointer to data buffer - * @note This function is used only in Indirect Write Mode - * @note If DMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Transmit_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t data_size = hospi->Instance->DLR + 1U; - DMA_QListTypeDef *p_queue = {NULL}; - uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; - - /* Check the data pointer allocation */ - if (pData == NULL) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - else - { - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - p_queue = hospi->hdma->LinkedListQueue; - if ((p_queue != NULL) && (p_queue->Head != NULL)) - { - data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; - } - else - { - /* Set Error Code */ - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - - /* Return function status */ - status = HAL_ERROR; - } - } - else - { - data_width = hospi->hdma->Init.DestDataWidth; - } - /* Configure counters and size */ - if (data_width == DMA_DEST_DATAWIDTH_BYTE) - { - hospi->XferCount = data_size; - } - else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) - { - if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - else - { - hospi->XferCount = data_size; - } - } - else if (data_width == DMA_DEST_DATAWIDTH_WORD) - { - if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - else - { - hospi->XferCount = data_size; - } - } - else - { - /* Nothing to do */ - } - - if (status == HAL_OK) - { - hospi->XferSize = hospi->XferCount; - hospi->pBuffPtr = pData; - - /* Configure CR register with functional mode as indirect write */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_WRITE); - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); - - /* Update the state */ - hospi->State = HAL_OSPI_STATE_BUSY_TX; - - /* Set the DMA transfer complete callback */ - hospi->hdma->XferCpltCallback = OSPI_DMACplt; - - /* Set the DMA Half transfer complete callback */ - hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; - - /* Set the DMA error callback */ - hospi->hdma->XferErrorCallback = OSPI_DMAError; - - /* Clear the DMA abort callback */ - hospi->hdma->XferAbortCallback = NULL; - - /* Enable the transmit DMA Channel */ - if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hospi->hdma->LinkedListQueue != NULL) - { - /* Enable the DMA channel */ - MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ - (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_INCREMENTED | DMA_DINC_FIXED)); - MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ - DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH); - /* Set DMA data size*/ - p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hospi->XferSize; - /* Set DMA source address */ - p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)pData; - /* Set DMA destination address */ - p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hospi->Instance->DR; - status = HAL_DMAEx_List_Start_IT(hospi->hdma); - } - else - { - /* Set Error Code */ - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - - /* Change OSPI state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Return function status */ - status = HAL_ERROR; - } - } - else - { - /* Configure the direction of the DMA */ - MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \ - (DMA_SINC_INCREMENTED | DMA_DINC_FIXED)); - MODIFY_REG(hospi->hdma->Instance->CTR2, DMA_CTR2_DREQ, DMA_MEMORY_TO_PERIPH); - - status = HAL_DMA_Start_IT(hospi->hdma, (uint32_t)pData, (uint32_t)&hospi->Instance->DR, hospi->XferSize); - } - - if (status == HAL_OK) - { - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Enable the DMA transfer by setting the DMAEN bit */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hospi : OSPI handle - * @param pData : pointer to data buffer. - * @note This function is used only in Indirect Read Mode - * @note If DMA peripheral access is configured as halfword, the number - * of data and the fifo threshold should be aligned on halfword - * @note If DMA peripheral access is configured as word, the number - * of data and the fifo threshold should be aligned on word - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Receive_DMA(OSPI_HandleTypeDef *hospi, uint8_t *pData) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t data_size = hospi->Instance->DLR + 1U; - uint32_t addr_reg = hospi->Instance->AR; - uint32_t ir_reg = hospi->Instance->IR; - DMA_QListTypeDef *p_queue = {NULL}; - uint32_t data_width = DMA_DEST_DATAWIDTH_BYTE; - /* Check the data pointer allocation */ - if (pData == NULL) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - else - { - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - p_queue = hospi->hdma->LinkedListQueue; - if ((p_queue != NULL) && (p_queue->Head != NULL)) - { - data_width = p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET] & DMA_CTR1_DDW_LOG2; - } - else - { - /* Set Error Code */ - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - - /* Return function status */ - status = HAL_ERROR; - } - } - else - { - data_width = hospi->hdma->Init.DestDataWidth; - } - - /* Configure counters and size */ - if (data_width == DMA_DEST_DATAWIDTH_BYTE) - { - hospi->XferCount = data_size; - } - else if (data_width == DMA_DEST_DATAWIDTH_HALFWORD) - { - if (((data_size % 2U) != 0U) || ((hospi->Init.FifoThreshold % 2U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on halfword - => no transfer possible with DMA peripheral access configured as halfword */ - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - else - { - hospi->XferCount = data_size; - } - } - else if (data_width == DMA_DEST_DATAWIDTH_WORD) - { - if (((data_size % 4U) != 0U) || ((hospi->Init.FifoThreshold % 4U) != 0U)) - { - /* The number of data or the fifo threshold is not aligned on word - => no transfer possible with DMA peripheral access configured as word */ - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - status = HAL_ERROR; - } - else - { - hospi->XferCount = data_size; - } - } - else - { - /* Nothing to do */ - } - - if (status == HAL_OK) - { - hospi->XferSize = hospi->XferCount; - hospi->pBuffPtr = pData; - - /* Configure CR register with functional mode as indirect read */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, OSPI_FUNCTIONAL_MODE_INDIRECT_READ); - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_TC); - - /* Update the state */ - hospi->State = HAL_OSPI_STATE_BUSY_RX; - - /* Set the DMA transfer complete callback */ - hospi->hdma->XferCpltCallback = OSPI_DMACplt; - - /* Set the DMA Half transfer complete callback */ - hospi->hdma->XferHalfCpltCallback = OSPI_DMAHalfCplt; - - /* Set the DMA error callback */ - hospi->hdma->XferErrorCallback = OSPI_DMAError; - - /* Clear the DMA abort callback */ - hospi->hdma->XferAbortCallback = NULL; - - /* Enable the transmit DMA Channel */ - if ((hospi->hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hospi->hdma->LinkedListQueue != NULL) - { - /* Enable the DMA channel */ - MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR1_DEFAULT_OFFSET], \ - (DMA_CTR1_SINC | DMA_CTR1_DINC), (DMA_SINC_FIXED | DMA_DINC_INCREMENTED)); - MODIFY_REG(p_queue->Head->LinkRegisters[NODE_CTR2_DEFAULT_OFFSET], \ - DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY); - /* Set DMA data size */ - p_queue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hospi->XferSize; - /* Set DMA source address */ - p_queue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hospi->Instance->DR; - /* Set DMA destination address */ - p_queue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)pData; - - status = HAL_DMAEx_List_Start_IT(hospi->hdma); - } - else - { - /* Set Error Code */ - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - - /* Change OSPI state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Return function status */ - status = HAL_ERROR; - } - } - - - else - { - /* Configure the direction of the DMA */ - MODIFY_REG(hospi->hdma->Instance->CTR1, (DMA_CTR1_SINC | DMA_CTR1_DINC), \ - (DMA_SINC_FIXED | DMA_DINC_INCREMENTED)); - MODIFY_REG(hospi->hdma->Instance->CTR2, DMA_CTR2_DREQ, DMA_PERIPH_TO_MEMORY); - - status = HAL_DMA_Start_IT(hospi->hdma, (uint32_t)&hospi->Instance->DR, (uint32_t)pData, hospi->XferSize); - } - if (status == HAL_OK) - { - /* Enable the transfer error interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TE); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - WRITE_REG(hospi->Instance->IR, ir_reg); - } - } - - /* Enable the DMA transfer by setting the DMAEN bit */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the OSPI Automatic Polling Mode in blocking mode. - * @param hospi : OSPI handle - * @param cfg : structure that contains the polling configuration information. - * @param Timeout : Timeout duration - * @note This function is used only in Automatic Polling Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_AutoPolling(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - uint32_t addr_reg = hospi->Instance->AR; - uint32_t ir_reg = hospi->Instance->IR; -#ifdef USE_FULL_ASSERT - uint32_t dlr_reg = hospi->Instance->DLR; -#endif /* USE_FULL_ASSERT */ - - /* Check the parameters of the autopolling configuration structure */ - assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode)); - assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); - assert_param(IS_OSPI_INTERVAL(cfg->Interval)); - assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); - - /* Check the state */ - if ((hospi->State == HAL_OSPI_STATE_CMD_CFG) && (cfg->AutomaticStop == HAL_OSPI_AUTOMATIC_STOP_ENABLE)) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Configure registers */ - WRITE_REG(hospi->Instance->PSMAR, cfg->Match); - WRITE_REG(hospi->Instance->PSMKR, cfg->Mask); - WRITE_REG(hospi->Instance->PIR, cfg->Interval); - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), - (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - WRITE_REG(hospi->Instance->IR, ir_reg); - } - } - - /* Wait till status match flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_SM, SET, tickstart, Timeout); - - if (status == HAL_OK) - { - /* Clear status match flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_SM); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the OSPI Automatic Polling Mode in non-blocking mode. - * @param hospi : OSPI handle - * @param cfg : structure that contains the polling configuration information. - * @note This function is used only in Automatic Polling Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - uint32_t addr_reg = hospi->Instance->AR; - uint32_t ir_reg = hospi->Instance->IR; -#ifdef USE_FULL_ASSERT - uint32_t dlr_reg = hospi->Instance->DLR; -#endif /* USE_FULL_ASSERT */ - - /* Check the parameters of the autopolling configuration structure */ - assert_param(IS_OSPI_MATCH_MODE(cfg->MatchMode)); - assert_param(IS_OSPI_AUTOMATIC_STOP(cfg->AutomaticStop)); - assert_param(IS_OSPI_INTERVAL(cfg->Interval)); - assert_param(IS_OSPI_STATUS_BYTES_SIZE(dlr_reg + 1U)); - - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - - if (status == HAL_OK) - { - /* Configure registers */ - WRITE_REG(hospi->Instance->PSMAR, cfg->Match); - WRITE_REG(hospi->Instance->PSMKR, cfg->Mask); - WRITE_REG(hospi->Instance->PIR, cfg->Interval); - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_PMM | OCTOSPI_CR_APMS | OCTOSPI_CR_FMODE), - (cfg->MatchMode | cfg->AutomaticStop | OSPI_FUNCTIONAL_MODE_AUTO_POLLING)); - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TE | HAL_OSPI_FLAG_SM); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_BUSY_AUTO_POLLING; - - /* Enable the status match and transfer error interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_SM | HAL_OSPI_IT_TE); - - /* Trig the transfer by re-writing address or instruction register */ - if (hospi->Init.MemoryType == HAL_OSPI_MEMTYPE_HYPERBUS) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - if (READ_BIT(hospi->Instance->CCR, OCTOSPI_CCR_ADMODE) != HAL_OSPI_ADDRESS_NONE) - { - WRITE_REG(hospi->Instance->AR, addr_reg); - } - else - { - WRITE_REG(hospi->Instance->IR, ir_reg); - } - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the Memory Mapped mode. - * @param hospi : OSPI handle - * @param cfg : structure that contains the memory mapped configuration information. - * @note This function is used only in Memory mapped Mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg) -{ - HAL_StatusTypeDef status; - uint32_t tickstart = HAL_GetTick(); - - /* Check the parameters of the memory-mapped configuration structure */ - assert_param(IS_OSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation)); - - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_CMD_CFG) - { - /* Wait till busy flag is reset */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - - if (status == HAL_OK) - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_BUSY_MEM_MAPPED; - - if (cfg->TimeOutActivation == HAL_OSPI_TIMEOUT_COUNTER_ENABLE) - { - assert_param(IS_OSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod)); - - /* Configure register */ - WRITE_REG(hospi->Instance->LPTR, cfg->TimeOutPeriod); - - /* Clear flags related to interrupt */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TO); - - /* Enable the timeout interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TO); - } - - /* Configure CR register with functional mode as memory-mapped */ - MODIFY_REG(hospi->Instance->CR, (OCTOSPI_CR_TCEN | OCTOSPI_CR_FMODE), - (cfg->TimeOutActivation | OSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)); - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Transfer Error callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_OSPI_ErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Abort completed callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_AbortCpltCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_OSPI_AbortCpltCallback could be implemented in the user file - */ -} - -/** - * @brief FIFO Threshold callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_OSPI_FIFOThresholdCallback could be implemented in the user file - */ -} - -/** - * @brief Command completed callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_CmdCpltCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_OSPI_CmdCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_RxCpltCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_OSPI_RxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Transfer completed callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_TxCpltCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_OSPI_TxCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_RxHalfCpltCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_OSPI_RxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_TxHalfCpltCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_OSPI_TxHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Status Match callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_StatusMatchCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_OSPI_StatusMatchCallback could be implemented in the user file - */ -} - -/** - * @brief Timeout callback. - * @param hospi : OSPI handle - * @retval None - */ -__weak void HAL_OSPI_TimeOutCallback(OSPI_HandleTypeDef *hospi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hospi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_OSPI_TimeOutCallback could be implemented in the user file - */ -} - -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User OSPI Callback - * To be used to override the weak predefined callback - * @param hospi : OSPI handle - * @param CallbackID : ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID - * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID - * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID - * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID - * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID - * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID - * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID - * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID - * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID - * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID - * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID - * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID - * @param pCallback : pointer to the Callback function - * @retval status - */ -HAL_StatusTypeDef HAL_OSPI_RegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, - pOSPI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - - if (hospi->State == HAL_OSPI_STATE_READY) - { - switch (CallbackID) - { - case HAL_OSPI_ERROR_CB_ID : - hospi->ErrorCallback = pCallback; - break; - case HAL_OSPI_ABORT_CB_ID : - hospi->AbortCpltCallback = pCallback; - break; - case HAL_OSPI_FIFO_THRESHOLD_CB_ID : - hospi->FifoThresholdCallback = pCallback; - break; - case HAL_OSPI_CMD_CPLT_CB_ID : - hospi->CmdCpltCallback = pCallback; - break; - case HAL_OSPI_RX_CPLT_CB_ID : - hospi->RxCpltCallback = pCallback; - break; - case HAL_OSPI_TX_CPLT_CB_ID : - hospi->TxCpltCallback = pCallback; - break; - case HAL_OSPI_RX_HALF_CPLT_CB_ID : - hospi->RxHalfCpltCallback = pCallback; - break; - case HAL_OSPI_TX_HALF_CPLT_CB_ID : - hospi->TxHalfCpltCallback = pCallback; - break; - case HAL_OSPI_STATUS_MATCH_CB_ID : - hospi->StatusMatchCallback = pCallback; - break; - case HAL_OSPI_TIMEOUT_CB_ID : - hospi->TimeOutCallback = pCallback; - break; - case HAL_OSPI_MSP_INIT_CB_ID : - hospi->MspInitCallback = pCallback; - break; - case HAL_OSPI_MSP_DEINIT_CB_ID : - hospi->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hospi->State == HAL_OSPI_STATE_RESET) - { - switch (CallbackID) - { - case HAL_OSPI_MSP_INIT_CB_ID : - hospi->MspInitCallback = pCallback; - break; - case HAL_OSPI_MSP_DEINIT_CB_ID : - hospi->MspDeInitCallback = pCallback; - break; - default : - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a User OSPI Callback - * OSPI Callback is redirected to the weak predefined callback - * @param hospi : OSPI handle - * @param CallbackID : ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_OSPI_ERROR_CB_ID OSPI Error Callback ID - * @arg @ref HAL_OSPI_ABORT_CB_ID OSPI Abort Callback ID - * @arg @ref HAL_OSPI_FIFO_THRESHOLD_CB_ID OSPI FIFO Threshold Callback ID - * @arg @ref HAL_OSPI_CMD_CPLT_CB_ID OSPI Command Complete Callback ID - * @arg @ref HAL_OSPI_RX_CPLT_CB_ID OSPI Rx Complete Callback ID - * @arg @ref HAL_OSPI_TX_CPLT_CB_ID OSPI Tx Complete Callback ID - * @arg @ref HAL_OSPI_RX_HALF_CPLT_CB_ID OSPI Rx Half Complete Callback ID - * @arg @ref HAL_OSPI_TX_HALF_CPLT_CB_ID OSPI Tx Half Complete Callback ID - * @arg @ref HAL_OSPI_STATUS_MATCH_CB_ID OSPI Status Match Callback ID - * @arg @ref HAL_OSPI_TIMEOUT_CB_ID OSPI Timeout Callback ID - * @arg @ref HAL_OSPI_MSP_INIT_CB_ID OSPI MspInit callback ID - * @arg @ref HAL_OSPI_MSP_DEINIT_CB_ID OSPI MspDeInit callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback(OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (hospi->State == HAL_OSPI_STATE_READY) - { - switch (CallbackID) - { - case HAL_OSPI_ERROR_CB_ID : - hospi->ErrorCallback = HAL_OSPI_ErrorCallback; - break; - case HAL_OSPI_ABORT_CB_ID : - hospi->AbortCpltCallback = HAL_OSPI_AbortCpltCallback; - break; - case HAL_OSPI_FIFO_THRESHOLD_CB_ID : - hospi->FifoThresholdCallback = HAL_OSPI_FifoThresholdCallback; - break; - case HAL_OSPI_CMD_CPLT_CB_ID : - hospi->CmdCpltCallback = HAL_OSPI_CmdCpltCallback; - break; - case HAL_OSPI_RX_CPLT_CB_ID : - hospi->RxCpltCallback = HAL_OSPI_RxCpltCallback; - break; - case HAL_OSPI_TX_CPLT_CB_ID : - hospi->TxCpltCallback = HAL_OSPI_TxCpltCallback; - break; - case HAL_OSPI_RX_HALF_CPLT_CB_ID : - hospi->RxHalfCpltCallback = HAL_OSPI_RxHalfCpltCallback; - break; - case HAL_OSPI_TX_HALF_CPLT_CB_ID : - hospi->TxHalfCpltCallback = HAL_OSPI_TxHalfCpltCallback; - break; - case HAL_OSPI_STATUS_MATCH_CB_ID : - hospi->StatusMatchCallback = HAL_OSPI_StatusMatchCallback; - break; - case HAL_OSPI_TIMEOUT_CB_ID : - hospi->TimeOutCallback = HAL_OSPI_TimeOutCallback; - break; - case HAL_OSPI_MSP_INIT_CB_ID : - hospi->MspInitCallback = HAL_OSPI_MspInit; - break; - case HAL_OSPI_MSP_DEINIT_CB_ID : - hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; - break; - default : - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else if (hospi->State == HAL_OSPI_STATE_RESET) - { - switch (CallbackID) - { - case HAL_OSPI_MSP_INIT_CB_ID : - hospi->MspInitCallback = HAL_OSPI_MspInit; - break; - case HAL_OSPI_MSP_DEINIT_CB_ID : - hospi->MspDeInitCallback = HAL_OSPI_MspDeInit; - break; - default : - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hospi->ErrorCode |= HAL_OSPI_ERROR_INVALID_CALLBACK; - /* update return status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - -/** - * @} - */ - -/** @defgroup OSPI_Exported_Functions_Group3 Peripheral Control and State functions - * @brief OSPI control and State functions - * -@verbatim - =============================================================================== - ##### Peripheral Control and State functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Check in run-time the state of the driver. - (+) Check the error code set during last operation. - (+) Abort any operation. - (+) Manage the Fifo threshold. - (+) Configure the timeout duration used in the driver. - -@endverbatim - * @{ - */ - -/** - * @brief Abort the current transmission. - * @param hospi : OSPI handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Abort(OSPI_HandleTypeDef *hospi) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - uint32_t tickstart = HAL_GetTick(); - - /* Check if the state is in one of the busy or configured states */ - state = hospi->State; - if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U)) - { - /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer on the OctoSPI side */ - CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - - /* Disable the DMA transfer on the DMA side */ - status = HAL_DMA_Abort(hospi->hdma); - if (status != HAL_OK) - { - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - } - } - - if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) - { - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); - - /* Wait until the transfer complete flag is set to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_TC, SET, tickstart, hospi->Timeout); - - if (status == HAL_OK) - { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Wait until the busy flag is reset to go back in idle state */ - status = OSPI_WaitFlagStateUntilTimeout(hospi, HAL_OSPI_FLAG_BUSY, RESET, tickstart, hospi->Timeout); - - if (status == HAL_OK) - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - } - } - } - else - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** - * @brief Abort the current transmission (non-blocking function) - * @param hospi : OSPI handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_Abort_IT(OSPI_HandleTypeDef *hospi) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t state; - - /* Check if the state is in one of the busy or configured states */ - state = hospi->State; - if (((state & OSPI_BUSY_STATE_MASK) != 0U) || ((state & OSPI_CFG_STATE_MASK) != 0U)) - { - /* Disable all interrupts */ - __HAL_OSPI_DISABLE_IT(hospi, (HAL_OSPI_IT_TO | HAL_OSPI_IT_SM | HAL_OSPI_IT_FT | HAL_OSPI_IT_TC | HAL_OSPI_IT_TE)); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_ABORT; - - /* Check if the DMA is enabled */ - if ((hospi->Instance->CR & OCTOSPI_CR_DMAEN) != 0U) - { - /* Disable the DMA transfer on the OctoSPI side */ - CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - - /* Disable the DMA transfer on the DMA side */ - hospi->hdma->XferAbortCallback = OSPI_DMAAbortCplt; - if (HAL_DMA_Abort_IT(hospi->hdma) != HAL_OK) - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Abort callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->AbortCpltCallback(hospi); -#else - HAL_OSPI_AbortCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ - } - } - else - { - if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) - { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Enable the transfer complete interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); - - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); - } - else - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Abort callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->AbortCpltCallback(hospi); -#else - HAL_OSPI_AbortCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - } - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** @brief Set OSPI Fifo threshold. - * @param hospi : OSPI handle. - * @param Threshold : Threshold of the Fifo. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold(OSPI_HandleTypeDef *hospi, uint32_t Threshold) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the state */ - if ((hospi->State & OSPI_BUSY_STATE_MASK) == 0U) - { - /* Synchronize initialization structure with the new fifo threshold value */ - hospi->Init.FifoThreshold = Threshold; - - /* Configure new fifo threshold */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FTHRES, ((hospi->Init.FifoThreshold - 1U) << OCTOSPI_CR_FTHRES_Pos)); - - } - else - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_SEQUENCE; - } - - /* Return function status */ - return status; -} - -/** @brief Get OSPI Fifo threshold. - * @param hospi : OSPI handle. - * @retval Fifo threshold - */ -uint32_t HAL_OSPI_GetFifoThreshold(const OSPI_HandleTypeDef *hospi) -{ - return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FTHRES) >> OCTOSPI_CR_FTHRES_Pos) + 1U); -} - -/** @brief Set OSPI timeout. - * @param hospi : OSPI handle. - * @param Timeout : Timeout for the memory access. - * @retval None - */ -HAL_StatusTypeDef HAL_OSPI_SetTimeout(OSPI_HandleTypeDef *hospi, uint32_t Timeout) -{ - hospi->Timeout = Timeout; - return HAL_OK; -} - -/** - * @brief Return the OSPI error code. - * @param hospi : OSPI handle - * @retval OSPI Error Code - */ -uint32_t HAL_OSPI_GetError(const OSPI_HandleTypeDef *hospi) -{ - return hospi->ErrorCode; -} - -/** - * @brief Return the OSPI handle state. - * @param hospi : OSPI handle - * @retval HAL state - */ -uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi) -{ - /* Return OSPI handle state */ - return hospi->State; -} - -/** - * @} - */ - -#if defined (OCTOSPIM) -/** @defgroup OSPI_Exported_Functions_Group4 IO Manager configuration function - * @brief OSPI IO Manager configuration function - * -@verbatim - =============================================================================== - ##### IO Manager configuration function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Configure the IO manager. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the OctoSPI IO manager. - * @param hospi : OSPI handle - * @param cfg : Configuration of the IO Manager for the instance - * @param Timeout : Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_OSPIM_Config(OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t instance; - uint8_t index; - uint8_t ospi_enabled = 0U; - uint8_t other_instance; - OSPIM_CfgTypeDef IOM_cfg[OSPI_NB_INSTANCE]; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(Timeout); - - /* Check the parameters of the OctoSPI IO Manager configuration structure */ - assert_param(IS_OSPIM_PORT(cfg->ClkPort)); - assert_param(IS_OSPIM_DQS_PORT(cfg->DQSPort)); - assert_param(IS_OSPIM_PORT(cfg->NCSPort)); - assert_param(IS_OSPIM_IO_PORT(cfg->IOLowPort)); - assert_param(IS_OSPIM_IO_PORT(cfg->IOHighPort)); - - if (hospi->Instance == (OCTOSPI_TypeDef *)OCTOSPI1) - { - instance = 0U; - other_instance = 1U; - } - else - { - instance = 1U; - other_instance = 0U; - } - - /**************** Get current configuration of the instances ****************/ - for (index = 0U; index < OSPI_NB_INSTANCE; index++) - { - if (OSPIM_GetConfig(index + 1U, &(IOM_cfg[index])) != HAL_OK) - { - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - } - - if (status == HAL_OK) - { - /********** Disable both OctoSPI to configure OctoSPI IO Manager **********/ - if ((OCTOSPI1->CR & OCTOSPI_CR_EN) != 0U) - { - CLEAR_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); - ospi_enabled |= 0x1U; - } - if ((OCTOSPI2->CR & OCTOSPI_CR_EN) != 0U) - { - CLEAR_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); - ospi_enabled |= 0x2U; - } - - /***************** Deactivation of previous configuration *****************/ - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN); - if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) - { - /* De-multiplexing should be performed */ - CLEAR_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); - - if (other_instance == 1U) - { - SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKSRC); - if (IOM_cfg[other_instance].DQSPort != 0U) - { - SET_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSSRC); - } - if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) - { - SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], \ - OCTOSPIM_PCR_IOLSRC_1); - } - if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) - { - SET_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], \ - OCTOSPIM_PCR_IOHSRC_1); - } - } - } - else - { - if (IOM_cfg[instance].ClkPort != 0U) - { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN); - if (IOM_cfg[instance].DQSPort != 0U) - { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN); - } - if (IOM_cfg[instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) - { - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOLEN); - } - if (IOM_cfg[instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) - { - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], OCTOSPIM_PCR_IOHEN); - } - } - } - - /********************* Deactivation of other instance *********************/ - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) || (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) || - (cfg->NCSPort == IOM_cfg[other_instance].NCSPort) || (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) || - (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) - { - if ((cfg->ClkPort == IOM_cfg[other_instance].ClkPort) && - (cfg->DQSPort == IOM_cfg[other_instance].DQSPort) && - (cfg->IOLowPort == IOM_cfg[other_instance].IOLowPort) && - (cfg->IOHighPort == IOM_cfg[other_instance].IOHighPort)) - { - /* Multiplexing should be performed */ - SET_BIT(OCTOSPIM->CR, OCTOSPIM_CR_MUXEN); - } - else - { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].ClkPort - 1U)], OCTOSPIM_PCR_CLKEN); - if (IOM_cfg[other_instance].DQSPort != 0U) - { - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].DQSPort - 1U)], OCTOSPIM_PCR_DQSEN); - } - CLEAR_BIT(OCTOSPIM->PCR[(IOM_cfg[other_instance].NCSPort - 1U)], OCTOSPIM_PCR_NCSEN); - if (IOM_cfg[other_instance].IOLowPort != HAL_OSPIM_IOPORT_NONE) - { - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], - OCTOSPIM_PCR_IOLEN); - } - if (IOM_cfg[other_instance].IOHighPort != HAL_OSPIM_IOPORT_NONE) - { - CLEAR_BIT(OCTOSPIM->PCR[((IOM_cfg[other_instance].IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], - OCTOSPIM_PCR_IOHEN); - } - } - } - - /******************** Activation of new configuration *********************/ - MODIFY_REG(OCTOSPIM->PCR[(cfg->NCSPort - 1U)], (OCTOSPIM_PCR_NCSEN | OCTOSPIM_PCR_NCSSRC), - (OCTOSPIM_PCR_NCSEN | (instance << OCTOSPIM_PCR_NCSSRC_Pos))); - - if (((cfg->Req2AckTime) >= 1U) && ((cfg->Req2AckTime) <= 256U)) - { - if ((cfg->Req2AckTime - 1U) > ((OCTOSPIM->CR & OCTOSPIM_CR_REQ2ACK_TIME) >> OCTOSPIM_CR_REQ2ACK_TIME_Pos)) - { - MODIFY_REG(OCTOSPIM->CR, OCTOSPIM_CR_REQ2ACK_TIME, ((cfg->Req2AckTime - 1U) << OCTOSPIM_CR_REQ2ACK_TIME_Pos)); - } - else - { - /* Nothing to do */ - } - } - - if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), OCTOSPIM_PCR_CLKEN); - if (cfg->DQSPort != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), OCTOSPIM_PCR_DQSEN); - } - - if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), OCTOSPIM_PCR_IOLEN); - } - else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), OCTOSPIM_PCR_IOHEN); - } - else - { - /* Nothing to do */ - } - - if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0)); - } - else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0)); - } - else - { - /* Nothing to do */ - } - } - else - { - MODIFY_REG(OCTOSPIM->PCR[(cfg->ClkPort - 1U)], (OCTOSPIM_PCR_CLKEN | OCTOSPIM_PCR_CLKSRC), - (OCTOSPIM_PCR_CLKEN | (instance << OCTOSPIM_PCR_CLKSRC_Pos))); - if (cfg->DQSPort != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[(cfg->DQSPort - 1U)], (OCTOSPIM_PCR_DQSEN | OCTOSPIM_PCR_DQSSRC), - (OCTOSPIM_PCR_DQSEN | (instance << OCTOSPIM_PCR_DQSSRC_Pos))); - } - - if ((cfg->IOLowPort & OCTOSPIM_PCR_IOLEN) != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U)))); - } - else if (cfg->IOLowPort != HAL_OSPIM_IOPORT_NONE) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOLowPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U)))); - } - else - { - /* Nothing to do */ - } - - if ((cfg->IOHighPort & OCTOSPIM_PCR_IOLEN) != 0U) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC), - (OCTOSPIM_PCR_IOLEN | OCTOSPIM_PCR_IOLSRC_0 | (instance << (OCTOSPIM_PCR_IOLSRC_Pos + 1U)))); - } - else if (cfg->IOHighPort != HAL_OSPIM_IOPORT_NONE) - { - MODIFY_REG(OCTOSPIM->PCR[((cfg->IOHighPort - 1U)& OSPI_IOM_PORT_MASK)], - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC), - (OCTOSPIM_PCR_IOHEN | OCTOSPIM_PCR_IOHSRC_0 | (instance << (OCTOSPIM_PCR_IOHSRC_Pos + 1U)))); - } - else - { - /* Nothing to do */ - } - } - - /******* Re-enable both OctoSPI after configure OctoSPI IO Manager ********/ - if ((ospi_enabled & 0x1U) != 0U) - { - SET_BIT(OCTOSPI1->CR, OCTOSPI_CR_EN); - } - if ((ospi_enabled & 0x2U) != 0U) - { - SET_BIT(OCTOSPI2->CR, OCTOSPI_CR_EN); - } - } - - /* Return function status */ - return status; -} - -/** - * @} - */ -#endif /* OCTOSPIM */ - -/** - @cond 0 - */ -/** - * @brief DMA OSPI process complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void OSPI_DMACplt(DMA_HandleTypeDef *hdma) -{ - OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent); - hospi->XferCount = 0; - - /* Disable the DMA transfer on the OctoSPI side */ - CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - - /* Disable the DMA channel */ - __HAL_DMA_DISABLE(hdma); - - /* Enable the OSPI transfer complete Interrupt */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); -} - -/** - * @brief DMA OSPI process half complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void OSPI_DMAHalfCplt(DMA_HandleTypeDef *hdma) -{ - OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent); - hospi->XferCount = (hospi->XferCount >> 1); - - if (hospi->State == HAL_OSPI_STATE_BUSY_RX) - { -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->RxHalfCpltCallback(hospi); -#else - HAL_OSPI_RxHalfCpltCallback(hospi); -#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - else - { -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->TxHalfCpltCallback(hospi); -#else - HAL_OSPI_TxHalfCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ - } -} - -/** - * @brief DMA OSPI communication error callback. - * @param hdma : DMA handle - * @retval None - */ -static void OSPI_DMAError(DMA_HandleTypeDef *hdma) -{ - OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent); - hospi->XferCount = 0; - hospi->ErrorCode = HAL_OSPI_ERROR_DMA; - - /* Disable the DMA transfer on the OctoSPI side */ - CLEAR_BIT(hospi->Instance->CR, OCTOSPI_CR_DMAEN); - - /* Abort the OctoSPI */ - if (HAL_OSPI_Abort_IT(hospi) != HAL_OK) - { - /* Disable the interrupts */ - __HAL_OSPI_DISABLE_IT(hospi, HAL_OSPI_IT_TC | HAL_OSPI_IT_FT | HAL_OSPI_IT_TE); - - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Error callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->ErrorCallback(hospi); -#else - HAL_OSPI_ErrorCallback(hospi); -#endif /*(USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } -} - -/** - * @brief DMA OSPI abort complete callback. - * @param hdma : DMA handle - * @retval None - */ -static void OSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma) -{ - OSPI_HandleTypeDef *hospi = (OSPI_HandleTypeDef *)(hdma->Parent); - hospi->XferCount = 0; - - /* Check the state */ - if (hospi->State == HAL_OSPI_STATE_ABORT) - { - /* DMA abort called by OctoSPI abort */ - if (__HAL_OSPI_GET_FLAG(hospi, HAL_OSPI_FLAG_BUSY) != RESET) - { - /* Clear transfer complete flag */ - __HAL_OSPI_CLEAR_FLAG(hospi, HAL_OSPI_FLAG_TC); - - /* Enable the transfer complete interrupts */ - __HAL_OSPI_ENABLE_IT(hospi, HAL_OSPI_IT_TC); - - /* Perform an abort of the OctoSPI */ - SET_BIT(hospi->Instance->CR, OCTOSPI_CR_ABORT); - } - else - { - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Abort callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->AbortCpltCallback(hospi); -#else - HAL_OSPI_AbortCpltCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) */ - } - } - else - { - /* DMA abort called due to a transfer error interrupt */ - /* Update state */ - hospi->State = HAL_OSPI_STATE_READY; - - /* Error callback */ -#if defined (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U) - hospi->ErrorCallback(hospi); -#else - HAL_OSPI_ErrorCallback(hospi); -#endif /* (USE_HAL_OSPI_REGISTER_CALLBACKS) && (USE_HAL_OSPI_REGISTER_CALLBACKS == 1U)*/ - } -} - -/** - * @brief Wait for a flag state until timeout. - * @param hospi : OSPI handle - * @param Flag : Flag checked - * @param State : Value of the flag expected - * @param Timeout : Duration of the timeout - * @param Tickstart : Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef OSPI_WaitFlagStateUntilTimeout(OSPI_HandleTypeDef *hospi, uint32_t Flag, - FlagStatus State, uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is in expected state */ - while ((__HAL_OSPI_GET_FLAG(hospi, Flag)) != State) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - /* New check to avoid false timeout detection in case of preemption */ - if ((hospi->Instance->SR & Flag) != (uint32_t)State) - { - hospi->State = HAL_OSPI_STATE_ERROR; - hospi->ErrorCode |= HAL_OSPI_ERROR_TIMEOUT; - - return HAL_ERROR; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Configure the registers for the regular command mode. - * @param hospi : OSPI handle - * @param cmd : structure that contains the command configuration information - * @retval HAL status - */ -static HAL_StatusTypeDef OSPI_ConfigCmd(OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd) -{ - HAL_StatusTypeDef status = HAL_OK; - __IO uint32_t *ccr_reg; - __IO uint32_t *tcr_reg; - __IO uint32_t *ir_reg; - __IO uint32_t *abr_reg; - - /* Re-initialize the value of the functional mode */ - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_FMODE, 0U); - - /* Configure the flash ID */ - if (hospi->Init.DualQuad == HAL_OSPI_DUALQUAD_DISABLE) - { - MODIFY_REG(hospi->Instance->CR, OCTOSPI_CR_MSEL, cmd->FlashId); - } - - if (cmd->OperationType == HAL_OSPI_OPTYPE_WRITE_CFG) - { - ccr_reg = &(hospi->Instance->WCCR); - tcr_reg = &(hospi->Instance->WTCR); - ir_reg = &(hospi->Instance->WIR); - abr_reg = &(hospi->Instance->WABR); - } - else if (cmd->OperationType == HAL_OSPI_OPTYPE_WRAP_CFG) - { - ccr_reg = &(hospi->Instance->WPCCR); - tcr_reg = &(hospi->Instance->WPTCR); - ir_reg = &(hospi->Instance->WPIR); - abr_reg = &(hospi->Instance->WPABR); - } - else - { - ccr_reg = &(hospi->Instance->CCR); - tcr_reg = &(hospi->Instance->TCR); - ir_reg = &(hospi->Instance->IR); - abr_reg = &(hospi->Instance->ABR); - } - - /* Configure the CCR register with DQS and SIOO modes */ - *ccr_reg = (cmd->DQSMode | cmd->SIOOMode); - - if (cmd->AlternateBytesMode != HAL_OSPI_ALTERNATE_BYTES_NONE) - { - /* Configure the ABR register with alternate bytes value */ - *abr_reg = cmd->AlternateBytes; - - /* Configure the CCR register with alternate bytes communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ABMODE | OCTOSPI_CCR_ABDTR | OCTOSPI_CCR_ABSIZE), - (cmd->AlternateBytesMode | cmd->AlternateBytesDtrMode | cmd->AlternateBytesSize)); - } - - /* Configure the TCR register with the number of dummy cycles */ - MODIFY_REG((*tcr_reg), OCTOSPI_TCR_DCYC, cmd->DummyCycles); - - if (cmd->DataMode != HAL_OSPI_DATA_NONE) - { - if (cmd->OperationType == HAL_OSPI_OPTYPE_COMMON_CFG) - { - /* Configure the DLR register with the number of data */ - hospi->Instance->DLR = (cmd->NbData - 1U); - } - } - - if (cmd->InstructionMode != HAL_OSPI_INSTRUCTION_NONE) - { - if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) - { - if (cmd->DataMode != HAL_OSPI_DATA_NONE) - { - /* ---- Command with instruction, address and data ---- */ - - /* Configure the CCR register with all communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | - OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | - OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), - (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | - cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | - cmd->DataMode | cmd->DataDtrMode)); - } - else - { - /* ---- Command with instruction and address ---- */ - - /* Configure the CCR register with all communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | - OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), - (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | - cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); - - /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && - (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) - { - MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); - } - } - - /* Configure the IR register with the instruction value */ - *ir_reg = cmd->Instruction; - - /* Configure the AR register with the address value */ - hospi->Instance->AR = cmd->Address; - } - else - { - if (cmd->DataMode != HAL_OSPI_DATA_NONE) - { - /* ---- Command with instruction and data ---- */ - - /* Configure the CCR register with all communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE | - OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), - (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize | - cmd->DataMode | cmd->DataDtrMode)); - } - else - { - /* ---- Command with only instruction ---- */ - - /* Configure the CCR register with all communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_IMODE | OCTOSPI_CCR_IDTR | OCTOSPI_CCR_ISIZE), - (cmd->InstructionMode | cmd->InstructionDtrMode | cmd->InstructionSize)); - - /* The DHQC bit is linked with DDTR bit which should be activated */ - if ((hospi->Init.DelayHoldQuarterCycle == HAL_OSPI_DHQC_ENABLE) && - (cmd->InstructionDtrMode == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) - { - MODIFY_REG((*ccr_reg), OCTOSPI_CCR_DDTR, HAL_OSPI_DATA_DTR_ENABLE); - } - } - - /* Configure the IR register with the instruction value */ - *ir_reg = cmd->Instruction; - - } - } - else - { - if (cmd->AddressMode != HAL_OSPI_ADDRESS_NONE) - { - if (cmd->DataMode != HAL_OSPI_DATA_NONE) - { - /* ---- Command with address and data ---- */ - - /* Configure the CCR register with all communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE | - OCTOSPI_CCR_DMODE | OCTOSPI_CCR_DDTR), - (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize | cmd->DataMode | - cmd->DataDtrMode)); - } - else - { - /* ---- Command with only address ---- */ - - /* Configure the CCR register with all communication parameters */ - MODIFY_REG((*ccr_reg), (OCTOSPI_CCR_ADMODE | OCTOSPI_CCR_ADDTR | OCTOSPI_CCR_ADSIZE), - (cmd->AddressMode | cmd->AddressDtrMode | cmd->AddressSize)); - } - - /* Configure the AR register with the instruction value */ - hospi->Instance->AR = cmd->Address; - } - else - { - /* ---- Invalid command configuration (no instruction, no address) ---- */ - status = HAL_ERROR; - hospi->ErrorCode = HAL_OSPI_ERROR_INVALID_PARAM; - } - } - - /* Return function status */ - return status; -} - -#if defined (OCTOSPIM) -/** - * @brief Get the current IOM configuration for an OctoSPI instance. - * @param instance_nb : number of the instance - * @param cfg : configuration of the IO Manager for the instance - * @retval HAL status - */ -static HAL_StatusTypeDef OSPIM_GetConfig(uint8_t instance_nb, OSPIM_CfgTypeDef *cfg) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t reg; - uint32_t value = 0U; - uint32_t index; - - if ((instance_nb == 0U) || (instance_nb > OSPI_NB_INSTANCE) || (cfg == NULL)) - { - /* Invalid parameter -> error returned */ - status = HAL_ERROR; - } - else - { - /* Initialize the structure */ - cfg->ClkPort = 0U; - cfg->DQSPort = 0U; - cfg->NCSPort = 0U; - cfg->IOLowPort = 0U; - cfg->IOHighPort = 0U; - - if (instance_nb == 2U) - { - if ((OCTOSPIM->CR & OCTOSPIM_CR_MUXEN) == 0U) - { - value = (OCTOSPIM_PCR_CLKSRC | OCTOSPIM_PCR_DQSSRC | OCTOSPIM_PCR_NCSSRC - | OCTOSPIM_PCR_IOLSRC_1 | OCTOSPIM_PCR_IOHSRC_1); - } - else - { - value = OCTOSPIM_PCR_NCSSRC; - } - } - - /* Get the information about the instance */ - for (index = 0U; index < OSPI_IOM_NB_PORTS; index ++) - { - reg = OCTOSPIM->PCR[index]; - - if ((reg & OCTOSPIM_PCR_CLKEN) != 0U) - { - /* The clock is enabled on this port */ - if ((reg & OCTOSPIM_PCR_CLKSRC) == (value & OCTOSPIM_PCR_CLKSRC)) - { - /* The clock correspond to the instance passed as parameter */ - cfg->ClkPort = index + 1U; - } - } - - if ((reg & OCTOSPIM_PCR_DQSEN) != 0U) - { - /* The DQS is enabled on this port */ - if ((reg & OCTOSPIM_PCR_DQSSRC) == (value & OCTOSPIM_PCR_DQSSRC)) - { - /* The DQS correspond to the instance passed as parameter */ - cfg->DQSPort = index + 1U; - } - } - - if ((reg & OCTOSPIM_PCR_NCSEN) != 0U) - { - /* The nCS is enabled on this port */ - if ((reg & OCTOSPIM_PCR_NCSSRC) == (value & OCTOSPIM_PCR_NCSSRC)) - { - /* The nCS correspond to the instance passed as parameter */ - cfg->NCSPort = index + 1U; - } - } - - if ((reg & OCTOSPIM_PCR_IOLEN) != 0U) - { - /* The IO Low is enabled on this port */ - if ((reg & OCTOSPIM_PCR_IOLSRC_1) == (value & OCTOSPIM_PCR_IOLSRC_1)) - { - /* The IO Low correspond to the instance passed as parameter */ - if ((reg & OCTOSPIM_PCR_IOLSRC_0) == 0U) - { - cfg->IOLowPort = (OCTOSPIM_PCR_IOLEN | (index + 1U)); - } - else - { - cfg->IOLowPort = (OCTOSPIM_PCR_IOHEN | (index + 1U)); - } - } - } - - if ((reg & OCTOSPIM_PCR_IOHEN) != 0U) - { - /* The IO High is enabled on this port */ - if ((reg & OCTOSPIM_PCR_IOHSRC_1) == (value & OCTOSPIM_PCR_IOHSRC_1)) - { - /* The IO High correspond to the instance passed as parameter */ - if ((reg & OCTOSPIM_PCR_IOHSRC_0) == 0U) - { - cfg->IOHighPort = (OCTOSPIM_PCR_IOLEN | (index + 1U)); - } - else - { - cfg->IOHighPort = (OCTOSPIM_PCR_IOHEN | (index + 1U)); - } - } - } - } - } - - /* Return function status */ - return status; -} -#endif /* OCTOSPIM */ - - -/** @defgroup OSPI_Exported_Functions_Group5 Delay Block function - * @brief Delay block function - * -@verbatim - =============================================================================== - ##### Delay Block function ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to : - (+) Configure the delay block. - -@endverbatim - * @{ - */ - -/** - * @brief Set the Delay Block configuration. - * @param hospi : OSPI handle. - * @param pdlyb_cfg: Pointer to DLYB configuration structure. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_OSPI_DLYB_SetConfig(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Enable OCTOSPI Free Running Clock (mandatory) */ - SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - - /* Update OCTOSPI state */ - hospi->State = HAL_OSPI_STATE_BUSY_CMD; - - if (hospi->Instance == OCTOSPI1) - { - /* Enable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI1); - - /* Set the Delay Block configuration */ - LL_DLYB_SetDelay(DLYB_OCTOSPI1, pdlyb_cfg); - status = HAL_OK; - } - -#if defined (OCTOSPI2) - else if (hospi->Instance == OCTOSPI2) - { - /* Enable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI2); - - /* Set the Delay Block configuration */ - LL_DLYB_SetDelay(DLYB_OCTOSPI2, pdlyb_cfg); - status = HAL_OK; - } -#endif /* OCTOSPI2 */ - - else - { - /* Nothing to do */ - } - - /* Abort the current OCTOSPI operation if exist */ - (void)HAL_OSPI_Abort(hospi); - - /* Disable Free Running Clock */ - CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - - /* Return function status */ - return status; -} - -/** - * @brief Get the Delay Block configuration. - * @param hospi : OSPI handle. - * @param pdlyb_cfg: Pointer to DLYB configuration structure. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_OSPI_DLYB_GetConfig(const OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - if (hospi->Instance == OCTOSPI1) - { - LL_DLYB_GetDelay(DLYB_OCTOSPI1, pdlyb_cfg); - status = HAL_OK; - } -#if defined (OCTOSPI2) - else if (hospi->Instance == OCTOSPI2) - { - LL_DLYB_GetDelay(DLYB_OCTOSPI2, pdlyb_cfg); - status = HAL_OK; - } -#endif /* OCTOSPI2 */ - - else - { - /* Nothing to do */ - } - - /* Return function status */ - return status; -} - -/** - * @brief Get the Delay line length value. - * @param hospi : OSPI handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_OSPI_DLYB_GetClockPeriod(OSPI_HandleTypeDef *hospi, HAL_OSPI_DLYB_CfgTypeDef *pdlyb_cfg) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - /* Enable OCTOSPI Free Running Clock (mandatory) */ - SET_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - - /* Update OCTOSPI state */ - hospi->State = HAL_OSPI_STATE_BUSY_CMD; - - if (hospi->Instance == OCTOSPI1) - { - /* Enable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI1); - - /* try to detect Period */ - if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI1, pdlyb_cfg) == (uint32_t)SUCCESS) - { - status = HAL_OK; - } - - /* Disable the DelayBlock */ - LL_DLYB_Disable(DLYB_OCTOSPI1); - } - -#if defined (OCTOSPI2) - else if (hospi->Instance == OCTOSPI2) - { - /* Enable the DelayBlock */ - LL_DLYB_Enable(DLYB_OCTOSPI2); - - /* try to detect Period */ - if (LL_DLYB_GetClockPeriod(DLYB_OCTOSPI2, pdlyb_cfg) == (uint32_t)SUCCESS) - { - status = HAL_OK; - } - - /* Disable the DelayBlock */ - LL_DLYB_Disable(DLYB_OCTOSPI2); - } -#endif /* OCTOSPI2 */ - - else - { - /* Nothing to do */ - } - - /* Abort the current OctoSPI operation if exist */ - (void)HAL_OSPI_Abort(hospi); - - /* Disable Free Running Clock */ - CLEAR_BIT(hospi->Instance->DCR1, OCTOSPI_DCR1_FRCK); - - /* Return function status */ - return status; -} -/** - @endcond - */ - -/** - * @} - */ - -#endif /* HAL_OSPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c deleted file mode 100644 index 45621b97b..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd.c +++ /dev/null @@ -1,3076 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pcd.c - * @author MCD Application Team - * @brief PCD HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The PCD HAL driver can be used as follows: - - (#) Declare a PCD_HandleTypeDef handle structure, for example: - PCD_HandleTypeDef hpcd; - - (#) Fill parameters of Init structure in HCD handle - - (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...) - - (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API: - (##) Enable the PCD/USB Low Level interface clock using - (+++) __HAL_RCC_USB_CLK_ENABLE(); For USB Device FS peripheral - (+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE(); - (+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode) - - (##) Initialize the related GPIO clocks - (##) Configure PCD pin-out - (##) Configure PCD NVIC interrupt - - (#)Associate the Upper USB device stack to the HAL PCD Driver: - (##) hpcd.pData = pdev; - - (#)Enable PCD transmission and reception: - (##) HAL_PCD_Start(); - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup PCD PCD - * @brief PCD HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup PCD_Private_Macros PCD Private Macros - * @{ - */ -#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b)) -#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b)) -/** - * @} - */ - -/* Private functions prototypes ----------------------------------------------*/ -/** @defgroup PCD_Private_Functions PCD Private Functions - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum); -static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); -static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd); -#if (USE_USB_DOUBLE_BUFFER == 1U) -static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); -static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, PCD_EPTypeDef *ep, uint16_t wEPVal); -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ -#endif /* defined (USB_DRD_FS) */ -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup PCD_Exported_Functions PCD Exported Functions - * @{ - */ - -/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the PCD according to the specified - * parameters in the PCD_InitTypeDef and initialize the associated handle. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd) -{ -#if defined (USB_OTG_FS) - const USB_OTG_GlobalTypeDef *USBx; -#endif /* defined (USB_OTG_FS) */ - uint8_t i; - - /* Check the PCD handle allocation */ - if (hpcd == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance)); - -#if defined (USB_OTG_FS) - USBx = hpcd->Instance; -#endif /* defined (USB_OTG_FS) */ - - if (hpcd->State == HAL_PCD_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hpcd->Lock = HAL_UNLOCKED; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SOFCallback = HAL_PCD_SOFCallback; - hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; - hpcd->ResetCallback = HAL_PCD_ResetCallback; - hpcd->SuspendCallback = HAL_PCD_SuspendCallback; - hpcd->ResumeCallback = HAL_PCD_ResumeCallback; - hpcd->ConnectCallback = HAL_PCD_ConnectCallback; - hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; - hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; - hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; - hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; - hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; - hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; - hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; - - if (hpcd->MspInitCallback == NULL) - { - hpcd->MspInitCallback = HAL_PCD_MspInit; - } - - /* Init the low level hardware */ - hpcd->MspInitCallback(hpcd); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_PCD_MspInit(hpcd); -#endif /* (USE_HAL_PCD_REGISTER_CALLBACKS) */ - } - - hpcd->State = HAL_PCD_STATE_BUSY; - -#if defined (USB_OTG_FS) - /* Disable DMA mode for FS instance */ - if (USBx == USB_OTG_FS) - { - hpcd->Init.dma_enable = 0U; - } -#endif /* defined (USB_OTG_FS) */ - - /* Disable the Interrupts */ - __HAL_PCD_DISABLE(hpcd); - - /*Init the Core (common init.) */ - if (USB_CoreInit(hpcd->Instance, hpcd->Init) != HAL_OK) - { - hpcd->State = HAL_PCD_STATE_ERROR; - return HAL_ERROR; - } - - /* Force Device Mode */ - if (USB_SetCurrentMode(hpcd->Instance, USB_DEVICE_MODE) != HAL_OK) - { - hpcd->State = HAL_PCD_STATE_ERROR; - return HAL_ERROR; - } - - /* Init endpoints structures */ - for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - { - /* Init ep structure */ - hpcd->IN_ep[i].is_in = 1U; - hpcd->IN_ep[i].num = i; -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - hpcd->IN_ep[i].tx_fifo_num = i; -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - /* Control until ep is activated */ - hpcd->IN_ep[i].type = EP_TYPE_CTRL; - hpcd->IN_ep[i].maxpacket = 0U; - hpcd->IN_ep[i].xfer_buff = 0U; - hpcd->IN_ep[i].xfer_len = 0U; - } - - for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - { - hpcd->OUT_ep[i].is_in = 0U; - hpcd->OUT_ep[i].num = i; - /* Control until ep is activated */ - hpcd->OUT_ep[i].type = EP_TYPE_CTRL; - hpcd->OUT_ep[i].maxpacket = 0U; - hpcd->OUT_ep[i].xfer_buff = 0U; - hpcd->OUT_ep[i].xfer_len = 0U; - } - - /* Init Device */ - if (USB_DevInit(hpcd->Instance, hpcd->Init) != HAL_OK) - { - hpcd->State = HAL_PCD_STATE_ERROR; - return HAL_ERROR; - } - - hpcd->USB_Address = 0U; - hpcd->State = HAL_PCD_STATE_READY; - - /* Activate LPM */ - if (hpcd->Init.lpm_enable == 1U) - { - (void)HAL_PCDEx_ActivateLPM(hpcd); - } - - (void)USB_DevDisconnect(hpcd->Instance); - - return HAL_OK; -} - -/** - * @brief DeInitializes the PCD peripheral. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd) -{ - /* Check the PCD handle allocation */ - if (hpcd == NULL) - { - return HAL_ERROR; - } - - hpcd->State = HAL_PCD_STATE_BUSY; - - /* Stop Device */ - if (USB_StopDevice(hpcd->Instance) != HAL_OK) - { - return HAL_ERROR; - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - if (hpcd->MspDeInitCallback == NULL) - { - hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hpcd->MspDeInitCallback(hpcd); -#else - /* DeInit the low level hardware: CLOCK, NVIC.*/ - HAL_PCD_MspDeInit(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - hpcd->State = HAL_PCD_STATE_RESET; - - return HAL_OK; -} - -/** - * @brief Initializes the PCD MSP. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes PCD MSP. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_MspDeInit could be implemented in the user file - */ -} - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) -/** - * @brief Register a User USB PCD Callback - * To be used instead of the weak predefined callback - * @param hpcd USB PCD handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID - * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID - * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID - * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID - * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID - * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID - * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID - * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterCallback(PCD_HandleTypeDef *hpcd, - HAL_PCD_CallbackIDTypeDef CallbackID, - pPCD_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - return HAL_ERROR; - } - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - switch (CallbackID) - { - case HAL_PCD_SOF_CB_ID : - hpcd->SOFCallback = pCallback; - break; - - case HAL_PCD_SETUPSTAGE_CB_ID : - hpcd->SetupStageCallback = pCallback; - break; - - case HAL_PCD_RESET_CB_ID : - hpcd->ResetCallback = pCallback; - break; - - case HAL_PCD_SUSPEND_CB_ID : - hpcd->SuspendCallback = pCallback; - break; - - case HAL_PCD_RESUME_CB_ID : - hpcd->ResumeCallback = pCallback; - break; - - case HAL_PCD_CONNECT_CB_ID : - hpcd->ConnectCallback = pCallback; - break; - - case HAL_PCD_DISCONNECT_CB_ID : - hpcd->DisconnectCallback = pCallback; - break; - - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = pCallback; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hpcd->State == HAL_PCD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = pCallback; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; -} - -/** - * @brief Unregister an USB PCD Callback - * USB PCD callback is redirected to the weak predefined callback - * @param hpcd USB PCD handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_PCD_SOF_CB_ID USB PCD SOF callback ID - * @arg @ref HAL_PCD_SETUPSTAGE_CB_ID USB PCD Setup callback ID - * @arg @ref HAL_PCD_RESET_CB_ID USB PCD Reset callback ID - * @arg @ref HAL_PCD_SUSPEND_CB_ID USB PCD Suspend callback ID - * @arg @ref HAL_PCD_RESUME_CB_ID USB PCD Resume callback ID - * @arg @ref HAL_PCD_CONNECT_CB_ID USB PCD Connect callback ID - * @arg @ref HAL_PCD_DISCONNECT_CB_ID USB PCD Disconnect callback ID - * @arg @ref HAL_PCD_MSPINIT_CB_ID MspDeInit callback ID - * @arg @ref HAL_PCD_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterCallback(PCD_HandleTypeDef *hpcd, HAL_PCD_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - /* Setup Legacy weak Callbacks */ - if (hpcd->State == HAL_PCD_STATE_READY) - { - switch (CallbackID) - { - case HAL_PCD_SOF_CB_ID : - hpcd->SOFCallback = HAL_PCD_SOFCallback; - break; - - case HAL_PCD_SETUPSTAGE_CB_ID : - hpcd->SetupStageCallback = HAL_PCD_SetupStageCallback; - break; - - case HAL_PCD_RESET_CB_ID : - hpcd->ResetCallback = HAL_PCD_ResetCallback; - break; - - case HAL_PCD_SUSPEND_CB_ID : - hpcd->SuspendCallback = HAL_PCD_SuspendCallback; - break; - - case HAL_PCD_RESUME_CB_ID : - hpcd->ResumeCallback = HAL_PCD_ResumeCallback; - break; - - case HAL_PCD_CONNECT_CB_ID : - hpcd->ConnectCallback = HAL_PCD_ConnectCallback; - break; - - case HAL_PCD_DISCONNECT_CB_ID : - hpcd->DisconnectCallback = HAL_PCD_DisconnectCallback; - break; - - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = HAL_PCD_MspInit; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (hpcd->State == HAL_PCD_STATE_RESET) - { - switch (CallbackID) - { - case HAL_PCD_MSPINIT_CB_ID : - hpcd->MspInitCallback = HAL_PCD_MspInit; - break; - - case HAL_PCD_MSPDEINIT_CB_ID : - hpcd->MspDeInitCallback = HAL_PCD_MspDeInit; - break; - - default : - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - return status; -} - -/** - * @brief Register USB PCD Data OUT Stage Callback - * To be used instead of the weak HAL_PCD_DataOutStageCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Data OUT Stage Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataOutStageCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataOutStageCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Data OUT Stage Callback - * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataOutStageCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterDataOutStageCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataOutStageCallback = HAL_PCD_DataOutStageCallback; /* Legacy weak DataOutStageCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD Data IN Stage Callback - * To be used instead of the weak HAL_PCD_DataInStageCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Data IN Stage Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterDataInStageCallback(PCD_HandleTypeDef *hpcd, - pPCD_DataInStageCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataInStageCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Data IN Stage Callback - * USB PCD Data OUT Stage Callback is redirected to the weak HAL_PCD_DataInStageCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterDataInStageCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->DataInStageCallback = HAL_PCD_DataInStageCallback; /* Legacy weak DataInStageCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD Iso OUT incomplete Callback - * To be used instead of the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Iso OUT incomplete Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoOutIncpltCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOOUTIncompleteCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Iso OUT incomplete Callback - * USB PCD Iso OUT incomplete Callback is redirected - * to the weak HAL_PCD_ISOOUTIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoOutIncpltCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOOUTIncompleteCallback = HAL_PCD_ISOOUTIncompleteCallback; /* Legacy weak ISOOUTIncompleteCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD Iso IN incomplete Callback - * To be used instead of the weak HAL_PCD_ISOINIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD Iso IN incomplete Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd, - pPCD_IsoInIncpltCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOINIncompleteCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD Iso IN incomplete Callback - * USB PCD Iso IN incomplete Callback is redirected - * to the weak HAL_PCD_ISOINIncompleteCallback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterIsoInIncpltCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->ISOINIncompleteCallback = HAL_PCD_ISOINIncompleteCallback; /* Legacy weak ISOINIncompleteCallback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD BCD Callback - * To be used instead of the weak HAL_PCDEx_BCD_Callback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD BCD Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterBcdCallback(PCD_HandleTypeDef *hpcd, pPCD_BcdCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->BCDCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD BCD Callback - * USB BCD Callback is redirected to the weak HAL_PCDEx_BCD_Callback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterBcdCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->BCDCallback = HAL_PCDEx_BCD_Callback; /* Legacy weak HAL_PCDEx_BCD_Callback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Register USB PCD LPM Callback - * To be used instead of the weak HAL_PCDEx_LPM_Callback() predefined callback - * @param hpcd PCD handle - * @param pCallback pointer to the USB PCD LPM Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_RegisterLpmCallback(PCD_HandleTypeDef *hpcd, pPCD_LpmCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->LPMCallback = pCallback; - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} - -/** - * @brief Unregister the USB PCD LPM Callback - * USB LPM Callback is redirected to the weak HAL_PCDEx_LPM_Callback() predefined callback - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_UnRegisterLpmCallback(PCD_HandleTypeDef *hpcd) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Process locked */ - __HAL_LOCK(hpcd); - - if (hpcd->State == HAL_PCD_STATE_READY) - { - hpcd->LPMCallback = HAL_PCDEx_LPM_Callback; /* Legacy weak HAL_PCDEx_LPM_Callback */ - } - else - { - /* Update the error code */ - hpcd->ErrorCode |= HAL_PCD_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - /* Release Lock */ - __HAL_UNLOCK(hpcd); - - return status; -} -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions - * @brief Data transfers functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Start the USB device - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd) -{ -#if defined (STM32U575xx) || defined (STM32U585xx) - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - __HAL_LOCK(hpcd); -#if defined (STM32U575xx) || defined (STM32U585xx) - if (hpcd->Init.battery_charging_enable == 1U) - { - /* Enable USB Transceiver */ - USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; - } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - __HAL_PCD_ENABLE(hpcd); - (void)USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Stop the USB device. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd) -{ -#if defined (STM32U575xx) || defined (STM32U585xx) - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - __HAL_LOCK(hpcd); - __HAL_PCD_DISABLE(hpcd); - (void)USB_DevDisconnect(hpcd->Instance); - - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (STM32U575xx) || defined (STM32U585xx) - if (hpcd->Init.battery_charging_enable == 1U) - { - /* Disable USB Transceiver */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Handles PCD interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - USB_OTG_EPTypeDef *ep; - uint32_t i; - uint32_t ep_intr; - uint32_t epint; - uint32_t epnum; - uint32_t fifoemptymsk; - uint32_t RegVal; - - /* ensure that we are in device mode */ - if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE) - { - /* avoid spurious interrupt */ - if (__HAL_PCD_IS_INVALID_INTERRUPT(hpcd)) - { - return; - } - - /* store current frame number */ - hpcd->FrameNumber = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF_Msk) >> USB_OTG_DSTS_FNSOF_Pos; - - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS)) - { - /* incorrect mode, acknowledge the interrupt */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS); - } - - /* Handle RxQLevel Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL)) - { - USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - - RegVal = USBx->GRXSTSP; - - ep = &hpcd->OUT_ep[RegVal & USB_OTG_GRXSTSP_EPNUM]; - - if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT) - { - if ((RegVal & USB_OTG_GRXSTSP_BCNT) != 0U) - { - (void)USB_ReadPacket(USBx, ep->xfer_buff, - (uint16_t)((RegVal & USB_OTG_GRXSTSP_BCNT) >> 4)); - - ep->xfer_buff += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; - ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; - } - } - else if (((RegVal & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_SETUP_UPDT) - { - (void)USB_ReadPacket(USBx, (uint8_t *)hpcd->Setup, 8U); - ep->xfer_count += (RegVal & USB_OTG_GRXSTSP_BCNT) >> 4; - } - else - { - /* ... */ - } - - USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL); - } - - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT)) - { - epnum = 0U; - - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance); - - while (ep_intr != 0U) - { - if ((ep_intr & 0x1U) != 0U) - { - epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, (uint8_t)epnum); - - if ((epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC); - (void)PCD_EP_OutXfrComplete_int(hpcd, epnum); - } - - if ((epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP); - /* Class B setup phase done for previous decoded setup */ - (void)PCD_EP_OutSetupPacket_int(hpcd, epnum); - } - - if ((epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS); - } - - /* Clear OUT Endpoint disable interrupt */ - if ((epint & USB_OTG_DOEPINT_EPDISD) == USB_OTG_DOEPINT_EPDISD) - { - if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == USB_OTG_GINTSTS_BOUTNAKEFF) - { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGONAK; - } - - ep = &hpcd->OUT_ep[epnum]; - - if (ep->is_iso_incomplete == 1U) - { - ep->is_iso_incomplete = 0U; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOOUTIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_EPDISD); - } - - /* Clear Status Phase Received interrupt */ - if ((epint & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - - /* Clear OUT NAK interrupt */ - if ((epint & USB_OTG_DOEPINT_NAK) == USB_OTG_DOEPINT_NAK) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_NAK); - } - } - epnum++; - ep_intr >>= 1U; - } - } - - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT)) - { - /* Read in the device interrupt bits */ - ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance); - - epnum = 0U; - - while (ep_intr != 0U) - { - if ((ep_intr & 0x1U) != 0U) /* In ITR */ - { - epint = USB_ReadDevInEPInterrupt(hpcd->Instance, (uint8_t)epnum); - - if ((epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC) - { - fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC); - - if (hpcd->Init.dma_enable == 1U) - { - hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket; - - /* this is ZLP, so prepare EP0 for next setup */ - if ((epnum == 0U) && (hpcd->IN_ep[epnum].xfer_len == 0U)) - { - /* prepare to rx more setup packets */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataInStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - if ((epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_TOC); - } - if ((epint & USB_OTG_DIEPINT_ITTXFE) == USB_OTG_DIEPINT_ITTXFE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_ITTXFE); - } - if ((epint & USB_OTG_DIEPINT_INEPNE) == USB_OTG_DIEPINT_INEPNE) - { - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_INEPNE); - } - if ((epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD) - { - (void)USB_FlushTxFifo(USBx, epnum); - - ep = &hpcd->IN_ep[epnum]; - - if (ep->is_iso_incomplete == 1U) - { - ep->is_iso_incomplete = 0U; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_ISOINIncompleteCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD); - } - if ((epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE) - { - (void)PCD_WriteEmptyTxFifo(hpcd, epnum); - } - } - epnum++; - ep_intr >>= 1U; - } - } - - /* Handle Resume Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT)) - { - /* Clear the Remote Wake-up Signaling */ - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - - if (hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); -#else - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ResumeCallback(hpcd); -#else - HAL_PCD_ResumeCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT); - } - - /* Handle Suspend Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP)) - { - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); -#else - HAL_PCD_SuspendCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP); - } - - /* Handle LPM Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT)) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT); - - if (hpcd->LPM_State == LPM_L0) - { - hpcd->LPM_State = LPM_L1; - hpcd->BESL = (hpcd->Instance->GLPMCFG & USB_OTG_GLPMCFG_BESL) >> 2U; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); -#else - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); -#else - HAL_PCD_SuspendCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - - /* Handle Reset Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST)) - { - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG; - (void)USB_FlushTxFifo(hpcd->Instance, 0x10U); - - for (i = 0U; i < hpcd->Init.dev_endpoints; i++) - { - USBx_INEP(i)->DIEPINT = 0xFB7FU; - USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - USBx_OUTEP(i)->DOEPINT = 0xFB7FU; - USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - USBx_OUTEP(i)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - } - USBx_DEVICE->DAINTMSK |= 0x10001U; - - if (hpcd->Init.use_dedicated_ep1 != 0U) - { - USBx_DEVICE->DOUTEP1MSK |= USB_OTG_DOEPMSK_STUPM | - USB_OTG_DOEPMSK_XFRCM | - USB_OTG_DOEPMSK_EPDM; - - USBx_DEVICE->DINEP1MSK |= USB_OTG_DIEPMSK_TOM | - USB_OTG_DIEPMSK_XFRCM | - USB_OTG_DIEPMSK_EPDM; - } - else - { - USBx_DEVICE->DOEPMSK |= USB_OTG_DOEPMSK_STUPM | - USB_OTG_DOEPMSK_XFRCM | - USB_OTG_DOEPMSK_EPDM | - USB_OTG_DOEPMSK_OTEPSPRM | - USB_OTG_DOEPMSK_NAKM; - - USBx_DEVICE->DIEPMSK |= USB_OTG_DIEPMSK_TOM | - USB_OTG_DIEPMSK_XFRCM | - USB_OTG_DIEPMSK_EPDM; - } - - /* Set Default Address to 0 */ - USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD; - - /* setup EP0 to receive SETUP packets */ - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, - (uint8_t *)hpcd->Setup); - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST); - } - - /* Handle Enumeration done Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE)) - { - (void)USB_ActivateSetup(hpcd->Instance); - hpcd->Init.speed = USB_GetDevSpeed(hpcd->Instance); - - /* Set USB Turnaround time */ - (void)USB_SetTurnaroundTime(hpcd->Instance, - HAL_RCC_GetHCLKFreq(), - (uint8_t)hpcd->Init.speed); - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ResetCallback(hpcd); -#else - HAL_PCD_ResetCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE); - } - - /* Handle SOF Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF)) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SOFCallback(hpcd); -#else - HAL_PCD_SOFCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF); - } - - /* Handle Global OUT NAK effective Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_BOUTNAKEFF)) - { - USBx->GINTMSK &= ~USB_OTG_GINTMSK_GONAKEFFM; - - for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) - { - if (hpcd->OUT_ep[epnum].is_iso_incomplete == 1U) - { - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)epnum); - } - } - } - - /* Handle Incomplete ISO IN Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR)) - { - for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) - { - RegVal = USBx_INEP(epnum)->DIEPCTL; - - if ((hpcd->IN_ep[epnum].type == EP_TYPE_ISOC) && - ((RegVal & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)) - { - hpcd->IN_ep[epnum].is_iso_incomplete = 1U; - - /* Abort current transaction and disable the EP */ - (void)HAL_PCD_EP_Abort(hpcd, (uint8_t)(epnum | 0x80U)); - } - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR); - } - - /* Handle Incomplete ISO OUT Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT)) - { - for (epnum = 1U; epnum < hpcd->Init.dev_endpoints; epnum++) - { - RegVal = USBx_OUTEP(epnum)->DOEPCTL; - - if ((hpcd->OUT_ep[epnum].type == EP_TYPE_ISOC) && - ((RegVal & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) && - ((RegVal & (0x1U << 16)) == (hpcd->FrameNumber & 0x1U))) - { - hpcd->OUT_ep[epnum].is_iso_incomplete = 1U; - - USBx->GINTMSK |= USB_OTG_GINTMSK_GONAKEFFM; - - if ((USBx->GINTSTS & USB_OTG_GINTSTS_BOUTNAKEFF) == 0U) - { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SGONAK; - break; - } - } - } - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT); - } - - /* Handle Connection event Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT)) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ConnectCallback(hpcd); -#else - HAL_PCD_ConnectCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT); - } - - /* Handle Disconnection event Interrupt */ - if (__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT)) - { - RegVal = hpcd->Instance->GOTGINT; - - if ((RegVal & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DisconnectCallback(hpcd); -#else - HAL_PCD_DisconnectCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - hpcd->Instance->GOTGINT |= RegVal; - } - } -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -/** - * @brief This function handles PCD interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd) -{ - uint32_t wIstr = USB_ReadInterrupts(hpcd->Instance); - - if ((wIstr & USB_ISTR_CTR) == USB_ISTR_CTR) - { - /* servicing of the endpoint correct transfer interrupt */ - /* clear of the CTR flag into the sub */ - (void)PCD_EP_ISR_Handler(hpcd); - - return; - } - - if ((wIstr & USB_ISTR_RESET) == USB_ISTR_RESET) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET); - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ResetCallback(hpcd); -#else - HAL_PCD_ResetCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - (void)HAL_PCD_SetAddress(hpcd, 0U); - - return; - } - - if ((wIstr & USB_ISTR_PMAOVR) == USB_ISTR_PMAOVR) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVR); - - return; - } - - if ((wIstr & USB_ISTR_ERR) == USB_ISTR_ERR) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); - - return; - } - - if ((wIstr & USB_ISTR_WKUP) == USB_ISTR_WKUP) - { - hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPRDY); - hpcd->Instance->CNTR &= ~(USB_CNTR_SUSPEN); - - if (hpcd->LPM_State == LPM_L1) - { - hpcd->LPM_State = LPM_L0; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->LPMCallback(hpcd, PCD_LPM_L0_ACTIVE); -#else - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L0_ACTIVE); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->ResumeCallback(hpcd); -#else - HAL_PCD_ResumeCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP); - - return; - } - - if ((wIstr & USB_ISTR_SUSP) == USB_ISTR_SUSP) - { - /* Force low-power mode in the macrocell */ - hpcd->Instance->CNTR |= USB_CNTR_SUSPEN; - - /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP); - - hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY; - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); -#else - HAL_PCD_SuspendCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - - /* Handle LPM Interrupt */ - if ((wIstr & USB_ISTR_L1REQ) == USB_ISTR_L1REQ) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_L1REQ); - if (hpcd->LPM_State == LPM_L0) - { - /* Force suspend and low-power mode before going to L1 state*/ - hpcd->Instance->CNTR |= USB_CNTR_SUSPRDY; - hpcd->Instance->CNTR |= USB_CNTR_SUSPEN; - - hpcd->LPM_State = LPM_L1; - hpcd->BESL = ((uint32_t)hpcd->Instance->LPMCSR & USB_LPMCSR_BESL) >> 2; -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->LPMCallback(hpcd, PCD_LPM_L1_ACTIVE); -#else - HAL_PCDEx_LPM_Callback(hpcd, PCD_LPM_L1_ACTIVE); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SuspendCallback(hpcd); -#else - HAL_PCD_SuspendCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - return; - } - - if ((wIstr & USB_ISTR_SOF) == USB_ISTR_SOF) - { - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SOFCallback(hpcd); -#else - HAL_PCD_SOFCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - return; - } - - if ((wIstr & USB_ISTR_ESOF) == USB_ISTR_ESOF) - { - /* clear ESOF flag in ISTR */ - __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); - - return; - } -} -#endif /* defined (USB_DRD_FS) */ - -/** - * @brief Data OUT stage callback. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataOutStageCallback could be implemented in the user file - */ -} - -/** - * @brief Data IN stage callback - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DataInStageCallback could be implemented in the user file - */ -} -/** - * @brief Setup stage callback - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SetupStageCallback could be implemented in the user file - */ -} - -/** - * @brief USB Start Of Frame callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SOFCallback could be implemented in the user file - */ -} - -/** - * @brief USB Reset callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResetCallback could be implemented in the user file - */ -} - -/** - * @brief Suspend event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_SuspendCallback could be implemented in the user file - */ -} - -/** - * @brief Resume event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ResumeCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO OUT callback. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Incomplete ISO IN callback. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval None - */ -__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(epnum); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file - */ -} - -/** - * @brief Connection event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_ConnectCallback could be implemented in the user file - */ -} - -/** - * @brief Disconnection event callback. - * @param hpcd PCD handle - * @retval None - */ -__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCD_DisconnectCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions - * @brief management functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the PCD data - transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Connect the USB device - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd) -{ -#if defined (STM32U575xx) || defined (STM32U585xx) - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - __HAL_LOCK(hpcd); - -#if defined (STM32U575xx) || defined (STM32U585xx) - if (hpcd->Init.battery_charging_enable == 1U) - { - /* Enable USB Transceiver */ - USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; - } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - (void)USB_DevConnect(hpcd->Instance); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Disconnect the USB device. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd) -{ -#if defined (STM32U575xx) || defined (STM32U585xx) - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - __HAL_LOCK(hpcd); - (void)USB_DevDisconnect(hpcd->Instance); - -#if defined (STM32U575xx) || defined (STM32U585xx) - if (hpcd->Init.battery_charging_enable == 1U) - { - /* Disable USB Transceiver */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Set the USB Device address. - * @param hpcd PCD handle - * @param address new device address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) -{ - __HAL_LOCK(hpcd); - hpcd->USB_Address = address; - (void)USB_SetDevAddress(hpcd->Instance, address); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} -/** - * @brief Open and configure an endpoint. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param ep_mps endpoint max packet size - * @param ep_type endpoint type - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, - uint16_t ep_mps, uint8_t ep_type) -{ - HAL_StatusTypeDef ret = HAL_OK; - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80U) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 0U; - } - - ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; - ep->type = ep_type; - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - if (ep->is_in != 0U) - { - /* Assign a Tx FIFO */ - ep->tx_fifo_num = ep->num; - } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - /* Set initial data PID. */ - if (ep_type == EP_TYPE_BULK) - { - ep->data_pid_start = 0U; - } - - __HAL_LOCK(hpcd); - (void)USB_ActivateEndpoint(hpcd->Instance, ep); - __HAL_UNLOCK(hpcd); - - return ret; -} - -/** - * @brief Deactivate an endpoint. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if ((ep_addr & 0x80U) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 0U; - } - ep->num = ep_addr & EP_ADDR_MSK; - - __HAL_LOCK(hpcd); - (void)USB_DeactivateEndpoint(hpcd->Instance, ep); - __HAL_UNLOCK(hpcd); - return HAL_OK; -} - - -/** - * @brief Receive an amount of data. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param pBuf pointer to the reception buffer - * @param len amount of data to be received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep; - - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; - ep->xfer_count = 0U; - ep->is_in = 0U; - ep->num = ep_addr & EP_ADDR_MSK; - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - if (hpcd->Init.dma_enable == 1U) - { - ep->dma_addr = (uint32_t)pBuf; - } - - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); -#else - (void)USB_EPStartXfer(hpcd->Instance, ep); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - return HAL_OK; -} - -/** - * @brief Get Received Data Size - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval Data Size - */ -uint32_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef const *hpcd, uint8_t ep_addr) -{ - return hpcd->OUT_ep[ep_addr & EP_ADDR_MSK].xfer_count; -} -/** - * @brief Send an amount of data - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @param pBuf pointer to the transmission buffer - * @param len amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len) -{ - PCD_EPTypeDef *ep; - - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - - /*setup and start the Xfer */ - ep->xfer_buff = pBuf; - ep->xfer_len = len; -#if defined (USB_DRD_FS) - ep->xfer_fill_db = 1U; - ep->xfer_len_db = len; -#endif /* defined (USB_DRD_FS) */ - ep->xfer_count = 0U; - ep->is_in = 1U; - ep->num = ep_addr & EP_ADDR_MSK; - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - if (hpcd->Init.dma_enable == 1U) - { - ep->dma_addr = (uint32_t)pBuf; - } - - (void)USB_EPStartXfer(hpcd->Instance, ep, (uint8_t)hpcd->Init.dma_enable); -#else - (void)USB_EPStartXfer(hpcd->Instance, ep); -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - return HAL_OK; -} - -/** - * @brief Set a STALL condition over an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if (((uint32_t)ep_addr & EP_ADDR_MSK) > hpcd->Init.dev_endpoints) - { - return HAL_ERROR; - } - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - ep->is_in = 0U; - } - - ep->is_stall = 1U; - ep->num = ep_addr & EP_ADDR_MSK; - - __HAL_LOCK(hpcd); - - (void)USB_EPSetStall(hpcd->Instance, ep); - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) - if ((ep_addr & EP_ADDR_MSK) == 0U) - { - (void)USB_EP0_OutStart(hpcd->Instance, (uint8_t)hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup); - } -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Clear a STALL condition over in an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - PCD_EPTypeDef *ep; - - if (((uint32_t)ep_addr & 0x0FU) > hpcd->Init.dev_endpoints) - { - return HAL_ERROR; - } - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 1U; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - ep->is_in = 0U; - } - - ep->is_stall = 0U; - ep->num = ep_addr & EP_ADDR_MSK; - - __HAL_LOCK(hpcd); - (void)USB_EPClearStall(hpcd->Instance, ep); - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Abort an USB EP transaction. - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Abort(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - HAL_StatusTypeDef ret; - PCD_EPTypeDef *ep; - - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr & EP_ADDR_MSK]; - } - - /* Stop Xfer */ - ret = USB_EPStopXfer(hpcd->Instance, ep); - - return ret; -} - -/** - * @brief Flush an endpoint - * @param hpcd PCD handle - * @param ep_addr endpoint address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr) -{ - __HAL_LOCK(hpcd); - - if ((ep_addr & 0x80U) == 0x80U) - { - (void)USB_FlushTxFifo(hpcd->Instance, (uint32_t)ep_addr & EP_ADDR_MSK); - } - else - { - (void)USB_FlushRxFifo(hpcd->Instance); - } - - __HAL_UNLOCK(hpcd); - - return HAL_OK; -} - -/** - * @brief Activate remote wakeup signalling - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return (USB_ActivateRemoteWakeup(hpcd->Instance)); -} - -/** - * @brief De-activate remote wakeup signalling. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd) -{ - return (USB_DeActivateRemoteWakeup(hpcd->Instance)); -} - -/** - * @} - */ - -/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions - * @brief Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral State functions ##### - =============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the PCD handle state. - * @param hpcd PCD handle - * @retval HAL state - */ -PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd) -{ - return hpcd->State; -} - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Set the USB Device high speed test mode. - * @param hpcd PCD handle - * @param testmode USB Device high speed test mode - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCD_SetTestMode(const PCD_HandleTypeDef *hpcd, uint8_t testmode) -{ - const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - - switch (testmode) - { - case TEST_J: - case TEST_K: - case TEST_SE0_NAK: - case TEST_PACKET: - case TEST_FORCE_EN: - USBx_DEVICE->DCTL |= (uint32_t)testmode << 4; - break; - - default: - break; - } - - return HAL_OK; -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @addtogroup PCD_Private_Functions - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Check FIFO for the next packet to be loaded. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - USB_OTG_EPTypeDef *ep; - uint32_t len; - uint32_t len32b; - uint32_t fifoemptymsk; - - ep = &hpcd->IN_ep[epnum]; - - if (ep->xfer_count > ep->xfer_len) - { - return HAL_ERROR; - } - - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - - len32b = (len + 3U) / 4U; - - while (((USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) >= len32b) && - (ep->xfer_count < ep->xfer_len) && (ep->xfer_len != 0U)) - { - /* Write the FIFO */ - len = ep->xfer_len - ep->xfer_count; - - if (len > ep->maxpacket) - { - len = ep->maxpacket; - } - len32b = (len + 3U) / 4U; - - (void)USB_WritePacket(USBx, ep->xfer_buff, (uint8_t)epnum, (uint16_t)len, - (uint8_t)hpcd->Init.dma_enable); - - ep->xfer_buff += len; - ep->xfer_count += len; - } - - if (ep->xfer_len <= ep->xfer_count) - { - fifoemptymsk = (uint32_t)(0x1UL << (epnum & EP_ADDR_MSK)); - USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk; - } - - return HAL_OK; -} - - -/** - * @brief process EP OUT transfer complete interrupt. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_OutXfrComplete_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - USB_OTG_EPTypeDef *ep; - const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); - uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - - if (hpcd->Init.dma_enable == 1U) - { - if ((DoepintReg & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP) /* Class C */ - { - /* StupPktRcvd = 1 this is a setup packet */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - } - else if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) /* Class E */ - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - else if ((DoepintReg & (USB_OTG_DOEPINT_STUP | USB_OTG_DOEPINT_OTEPSPR)) == 0U) - { - /* StupPktRcvd = 1 this is a setup packet */ - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - else - { - ep = &hpcd->OUT_ep[epnum]; - - /* out data packet received over EP */ - ep->xfer_count = ep->xfer_size - (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ); - - if (epnum == 0U) - { - if (ep->xfer_len == 0U) - { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } - else - { - ep->xfer_buff += ep->xfer_count; - } - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - else - { - /* ... */ - } - } - else - { - if (gSNPSiD == USB_OTG_CORE_ID_310A) - { - /* StupPktRcvd = 1 this is a setup packet */ - if ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - else - { - if ((DoepintReg & USB_OTG_DOEPINT_OTEPSPR) == USB_OTG_DOEPINT_OTEPSPR) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPSPR); - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - else - { - if ((epnum == 0U) && (hpcd->OUT_ep[epnum].xfer_len == 0U)) - { - /* this is ZLP, so prepare EP0 for next setup */ - (void)USB_EP0_OutStart(hpcd->Instance, 0U, (uint8_t *)hpcd->Setup); - } - -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, (uint8_t)epnum); -#else - HAL_PCD_DataOutStageCallback(hpcd, (uint8_t)epnum); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - - return HAL_OK; -} - - -/** - * @brief process EP OUT setup packet received interrupt. - * @param hpcd PCD handle - * @param epnum endpoint number - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_OutSetupPacket_int(PCD_HandleTypeDef *hpcd, uint32_t epnum) -{ - const USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); - uint32_t DoepintReg = USBx_OUTEP(epnum)->DOEPINT; - - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && - ((DoepintReg & USB_OTG_DOEPINT_STPKTRX) == USB_OTG_DOEPINT_STPKTRX)) - { - CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STPKTRX); - } - - /* Inform the upper layer that a setup packet is available */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SetupStageCallback(hpcd); -#else - HAL_PCD_SetupStageCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - if ((gSNPSiD > USB_OTG_CORE_ID_300A) && (hpcd->Init.dma_enable == 1U)) - { - (void)USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup); - } - - return HAL_OK; -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -/** - * @brief This function handles PCD Endpoint interrupt request. - * @param hpcd PCD handle - * @retval HAL status - */ -static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) -{ - PCD_EPTypeDef *ep; - uint16_t count; - uint16_t wIstr; - uint16_t wEPVal; - uint16_t TxPctSize; - uint8_t epindex; - -#if (USE_USB_DOUBLE_BUFFER != 1U) - count = 0U; -#endif /* USE_USB_DOUBLE_BUFFER */ - - /* stay in loop while pending interrupts */ - while ((hpcd->Instance->ISTR & USB_ISTR_CTR) != 0U) - { - wIstr = (uint16_t)hpcd->Instance->ISTR; - - /* extract highest priority endpoint number */ - epindex = (uint8_t)(wIstr & USB_ISTR_IDN); - - if (epindex == 0U) - { - /* Decode and service control endpoint interrupt */ - - /* DIR bit = origin of the interrupt */ - if ((wIstr & USB_ISTR_DIR) == 0U) - { - /* DIR = 0 */ - - /* DIR = 0 => IN int */ - /* DIR = 0 implies that (EP_CTR_TX = 1) always */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0); - ep = &hpcd->IN_ep[0]; - - ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - ep->xfer_buff += ep->xfer_count; - - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, 0U); -#else - HAL_PCD_DataInStageCallback(hpcd, 0U); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - if ((hpcd->USB_Address > 0U) && (ep->xfer_len == 0U)) - { - hpcd->Instance->DADDR = ((uint16_t)hpcd->USB_Address | USB_DADDR_EF); - hpcd->USB_Address = 0U; - } - } - else - { - /* DIR = 1 */ - - /* DIR = 1 & CTR_RX => SETUP or OUT int */ - /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */ - ep = &hpcd->OUT_ep[0]; - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if ((wEPVal & USB_EP_SETUP) != 0U) - { - /* Get SETUP Packet */ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, - ep->pmaadress, (uint16_t)ep->xfer_count); - - /* SETUP bit kept frozen while CTR_RX = 1 */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Process SETUP Packet*/ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->SetupStageCallback(hpcd); -#else - HAL_PCD_SetupStageCallback(hpcd); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else if ((wEPVal & USB_EP_VTRX) != 0U) - { - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); - - /* Get Control Data OUT Packet */ - ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); - - ep->xfer_buff += ep->xfer_count; - - /* Process Control Data OUT Packet */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); -#else - HAL_PCD_DataOutStageCallback(hpcd, 0U); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); - } - } - } - } - else - { - /* Decode and service non control endpoints interrupt */ - /* process related endpoint register */ - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, epindex); - - if ((wEPVal & USB_EP_VTRX) != 0U) - { - /* clear int flag */ - PCD_CLEAR_RX_EP_CTR(hpcd->Instance, epindex); - ep = &hpcd->OUT_ep[epindex]; - - /* OUT Single Buffering */ - if (ep->doublebuffer == 0U) - { - count = (uint16_t)PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count); - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else - { - /* manage double buffer bulk out */ - if (ep->type == EP_TYPE_BULK) - { - count = HAL_PCD_EP_DB_Receive(hpcd, ep, wEPVal); - } - else /* manage double buffer iso out */ - { - /* free EP OUT Buffer */ - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); - - if ((PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX) != 0U) - { - /* read from endpoint BUF0Addr buffer */ - count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - else - { - /* read from endpoint BUF1Addr buffer */ - count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - /* multi-packet on the NON control OUT endpoint */ - ep->xfer_count += count; - ep->xfer_buff += count; - - if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) - { - /* RX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataOutStageCallback(hpcd, ep->num); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { - (void)USB_EPStartXfer(hpcd->Instance, ep); - } - } - - if ((wEPVal & USB_EP_VTTX) != 0U) - { - ep = &hpcd->IN_ep[epindex]; - - /* clear int flag */ - PCD_CLEAR_TX_EP_CTR(hpcd->Instance, epindex); - - if (ep->type == EP_TYPE_ISOC) - { - ep->xfer_len = 0U; - -#if (USE_USB_DOUBLE_BUFFER == 1U) - if (ep->doublebuffer != 0U) - { - if ((wEPVal & USB_EP_DTOG_TX) != 0U) - { - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - } - else - { - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataInStageCallback(hpcd, ep->num); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { - /* Manage Single Buffer Transaction */ - if ((wEPVal & USB_EP_KIND) == 0U) - { - /* multi-packet on the NON control IN endpoint */ - TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_len > TxPctSize) - { - ep->xfer_len -= TxPctSize; - } - else - { - ep->xfer_len = 0U; - } - - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataInStageCallback(hpcd, ep->num); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { - /* Transfer is not yet Done */ - ep->xfer_buff += TxPctSize; - ep->xfer_count += TxPctSize; - (void)USB_EPStartXfer(hpcd->Instance, ep); - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - /* Double Buffer bulk IN (bulk transfer Len > Ep_Mps) */ - else - { - (void)HAL_PCD_EP_DB_Transmit(hpcd, ep, wEPVal); - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - } - } - } - } - - return HAL_OK; -} - - -#if (USE_USB_DOUBLE_BUFFER == 1U) -/** - * @brief Manage double buffer bulk out transaction from ISR - * @param hpcd PCD handle - * @param ep current endpoint handle - * @param wEPVal Last snapshot of EPRx register value taken in ISR - * @retval HAL status - */ -static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, - PCD_EPTypeDef *ep, uint16_t wEPVal) -{ - uint16_t count; - - /* Manage Buffer0 OUT */ - if ((wEPVal & USB_EP_DTOG_RX) != 0U) - { - /* Get count of received Data on buffer0 */ - count = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_len >= count) - { - ep->xfer_len -= count; - } - else - { - ep->xfer_len = 0U; - } - - if (ep->xfer_len == 0U) - { - /* set NAK to OUT endpoint since double buffer is enabled */ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); - } - - /* Check if Buffer1 is in blocked state which requires to toggle */ - if ((wEPVal & USB_EP_DTOG_TX) != 0U) - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); - } - - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count); - } - } - /* Manage Buffer 1 DTOG_RX=0 */ - else - { - /* Get count of received data */ - count = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_len >= count) - { - ep->xfer_len -= count; - } - else - { - ep->xfer_len = 0U; - } - - if (ep->xfer_len == 0U) - { - /* set NAK on the current endpoint */ - PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); - } - - /*Need to FreeUser Buffer*/ - if ((wEPVal & USB_EP_DTOG_TX) == 0U) - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); - } - - if (count != 0U) - { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count); - } - } - - return count; -} - - -/** - * @brief Manage double buffer bulk IN transaction from ISR - * @param hpcd PCD handle - * @param ep current endpoint handle - * @param wEPVal Last snapshot of EPRx register value taken in ISR - * @retval HAL status - */ -static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, - PCD_EPTypeDef *ep, uint16_t wEPVal) -{ - uint32_t len; - uint16_t TxPctSize; - - /* Data Buffer0 ACK received */ - if ((wEPVal & USB_EP_DTOG_TX) != 0U) - { - /* multi-packet on the NON control IN endpoint */ - TxPctSize = (uint16_t)PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_len > TxPctSize) - { - ep->xfer_len -= TxPctSize; - } - else - { - ep->xfer_len = 0U; - } - - /* Transfer is completed */ - if (ep->xfer_len == 0U) - { - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataInStageCallback(hpcd, ep->num); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - if ((wEPVal & USB_EP_DTOG_RX) != 0U) - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - } - } - else /* Transfer is not yet Done */ - { - /* need to Free USB Buff */ - if ((wEPVal & USB_EP_DTOG_RX) != 0U) - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - } - - /* Still there is data to Fill in the next Buffer */ - if (ep->xfer_fill_db == 1U) - { - ep->xfer_buff += TxPctSize; - ep->xfer_count += TxPctSize; - - /* Calculate the len of the new buffer to fill */ - if (ep->xfer_len_db >= ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len_db -= len; - } - else if (ep->xfer_len_db == 0U) - { - len = TxPctSize; - ep->xfer_fill_db = 0U; - } - else - { - ep->xfer_fill_db = 0U; - len = ep->xfer_len_db; - ep->xfer_len_db = 0U; - } - - /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); - - /* Copy user buffer to USB PMA */ - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, (uint16_t)len); - } - } - } - else /* Data Buffer1 ACK received */ - { - /* multi-packet on the NON control IN endpoint */ - TxPctSize = (uint16_t)PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num); - - if (ep->xfer_len >= TxPctSize) - { - ep->xfer_len -= TxPctSize; - } - else - { - ep->xfer_len = 0U; - } - - /* Transfer is completed */ - if (ep->xfer_len == 0U) - { - PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); - - /* TX COMPLETE */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataInStageCallback(hpcd, ep->num); -#else - HAL_PCD_DataInStageCallback(hpcd, ep->num); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - - /* need to Free USB Buff */ - if ((wEPVal & USB_EP_DTOG_RX) == 0U) - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - } - } - else /* Transfer is not yet Done */ - { - /* need to Free USB Buff */ - if ((wEPVal & USB_EP_DTOG_RX) == 0U) - { - PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); - } - - /* Still there is data to Fill in the next Buffer */ - if (ep->xfer_fill_db == 1U) - { - ep->xfer_buff += TxPctSize; - ep->xfer_count += TxPctSize; - - /* Calculate the len of the new buffer to fill */ - if (ep->xfer_len_db >= ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len_db -= len; - } - else if (ep->xfer_len_db == 0U) - { - len = TxPctSize; - ep->xfer_fill_db = 0U; - } - else - { - len = ep->xfer_len_db; - ep->xfer_len_db = 0U; - ep->xfer_fill_db = 0; - } - - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); - - /* Copy the user buffer to USB PMA */ - USB_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, (uint16_t)len); - } - } - } - - /*enable endpoint IN*/ - PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); - - return HAL_OK; -} -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - -#endif /* defined (USB_DRD_FS) */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c deleted file mode 100644 index a4a9f4ac5..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pcd_ex.c +++ /dev/null @@ -1,575 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pcd_ex.c - * @author MCD Application Team - * @brief PCD Extended HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Extended features functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup PCDEx PCDEx - * @brief PCD Extended HAL module driver - * @{ - */ - -#ifdef HAL_PCD_MODULE_ENABLED - -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions - * @{ - */ - -/** @defgroup PCDEx_Exported_Functions_Group1 Peripheral Control functions - * @brief PCDEx control functions - * -@verbatim - =============================================================================== - ##### Extended features functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Update FIFO configuration - -@endverbatim - * @{ - */ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -/** - * @brief Set Tx FIFO - * @param hpcd PCD handle - * @param fifo The number of Tx fifo - * @param size Fifo size - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) -{ - uint8_t i; - uint32_t Tx_Offset; - - /* TXn min size = 16 words. (n : Transmit FIFO index) - When a TxFIFO is not used, the Configuration should be as follows: - case 1 : n > m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txm can use the space allocated for Txn. - case2 : n < m and Txn is not used (n,m : Transmit FIFO indexes) - --> Txn should be configured with the minimum space of 16 words - The FIFO is used optimally when used TxFIFOs are allocated in the top - of the FIFO.Ex: use EP1 and EP2 as IN instead of EP1 and EP3 as IN ones. - When DMA is used 3n * FIFO locations should be reserved for internal DMA registers */ - - Tx_Offset = hpcd->Instance->GRXFSIZ; - - if (fifo == 0U) - { - hpcd->Instance->DIEPTXF0_HNPTXFSIZ = ((uint32_t)size << 16) | Tx_Offset; - } - else - { - Tx_Offset += (hpcd->Instance->DIEPTXF0_HNPTXFSIZ) >> 16; - for (i = 0U; i < (fifo - 1U); i++) - { - Tx_Offset += (hpcd->Instance->DIEPTXF[i] >> 16); - } - - /* Multiply Tx_Size by 2 to get higher performance */ - hpcd->Instance->DIEPTXF[fifo - 1U] = ((uint32_t)size << 16) | Tx_Offset; - } - - return HAL_OK; -} - -/** - * @brief Set Rx FIFO - * @param hpcd PCD handle - * @param size Size of Rx fifo - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) -{ - hpcd->Instance->GRXFSIZ = size; - - return HAL_OK; -} - -/** - * @brief Activate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = 1U; - hpcd->LPM_State = LPM_L0; - USBx->GINTMSK |= USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG |= (USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = 0U; - USBx->GINTMSK &= ~USB_OTG_GINTMSK_LPMINTM; - USBx->GLPMCFG &= ~(USB_OTG_GLPMCFG_LPMEN | USB_OTG_GLPMCFG_LPMACK | USB_OTG_GLPMCFG_ENBESL); - - return HAL_OK; -} - - -/** - * @brief Handle BatteryCharging Process. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Enable DCD : Data Contact Detect */ - USBx->GCCFG |= USB_OTG_GCCFG_DCDEN; - - /* Wait for Min DCD Timeout */ - HAL_Delay(300U); - -#if defined (STM32U575xx) || defined (STM32U585xx) - /* Check Detect flag */ - if ((USBx->GCCFG & USB_OTG_GCCFG_DCDET) == USB_OTG_GCCFG_DCDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - /* Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->GCCFG &= ~USB_OTG_GCCFG_DCDEN; - HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_PDEN; - HAL_Delay(50U); - -#if defined (STM32U575xx) || defined (STM32U585xx) - if ((USBx->GCCFG & USB_OTG_GCCFG_PDET) == 0U) -#else - if ((USBx->GCCFG & USB_OTG_GCCFG_CHGDET) == 0U) -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - { - /* Case of Standard Downstream Port */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { - /* start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); - HAL_Delay(50U); - USBx->GCCFG |= USB_OTG_GCCFG_SDEN; - HAL_Delay(50U); - -#if defined (STM32U575xx) || defined (STM32U585xx) - if ((USBx->GCCFG & USB_OTG_GCCFG_SDET) == USB_OTG_GCCFG_SDET) -#else - if ((USBx->GCCFG & USB_OTG_GCCFG_FSVPLUS) == USB_OTG_GCCFG_FSVPLUS) -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - { - /* case Dedicated Charging Port */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { - /* case Charging Downstream Port */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - - /* Battery Charging capability discovery finished */ - (void)HAL_PCDEx_DeActivateBCD(hpcd); - - /* Check for the Timeout, else start USB Device */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } -} - -/** - * @brief Activate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); - USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); - -#if defined (STM32U575xx) || defined (STM32U585xx) - /* Power Down USB transceiver */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - - /* Enable Battery charging */ - USBx->GCCFG |= USB_OTG_GCCFG_BCDEN; -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - hpcd->battery_charging_active = 1U; - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_OTG_GlobalTypeDef *USBx = hpcd->Instance; - - USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); - USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); - -#if defined (STM32U575xx) || defined (STM32U585xx) - /* Disable Battery charging */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - hpcd->battery_charging_active = 0U; - - return HAL_OK; -} - -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ -#if defined (USB_DRD_FS) -/** - * @brief Configure PMA for EP - * @param hpcd Device instance - * @param ep_addr endpoint address - * @param ep_kind endpoint Kind - * USB_SNG_BUF: Single Buffer used - * USB_DBL_BUF: Double Buffer used - * @param pmaadress: EP address in The PMA: In case of single buffer endpoint - * this parameter is 16-bit value providing the address - * in PMA allocated to endpoint. - * In case of double buffer endpoint this parameter - * is a 32-bit value providing the endpoint buffer 0 address - * in the LSB part of 32-bit value and endpoint buffer 1 address - * in the MSB part of 32-bit value. - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, - uint16_t ep_kind, uint32_t pmaadress) -{ - PCD_EPTypeDef *ep; - - /* initialize ep structure*/ - if ((0x80U & ep_addr) == 0x80U) - { - ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; - } - else - { - ep = &hpcd->OUT_ep[ep_addr]; - } - - /* Here we check if the endpoint is single or double Buffer*/ - if (ep_kind == PCD_SNG_BUF) - { - /* Single Buffer */ - ep->doublebuffer = 0U; - /* Configure the PMA */ - ep->pmaadress = (uint16_t)pmaadress; - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else /* USB_DBL_BUF */ - { - /* Double Buffer Endpoint */ - ep->doublebuffer = 1U; - /* Configure the PMA */ - ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); - ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - return HAL_OK; -} - -/** - * @brief Activate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_DRD_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = 1U; - - /* Enable BCD feature */ - USBx->BCDR |= USB_BCDR_BCDEN; - - /* Enable DCD : Data Contact Detect */ - USBx->BCDR &= ~(USB_BCDR_PDEN); - USBx->BCDR &= ~(USB_BCDR_SDEN); - USBx->BCDR |= USB_BCDR_DCDEN; - - return HAL_OK; -} - -/** - * @brief Deactivate BatteryCharging feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) -{ - USB_DRD_TypeDef *USBx = hpcd->Instance; - hpcd->battery_charging_active = 0U; - - /* Disable BCD feature */ - USBx->BCDR &= ~(USB_BCDR_BCDEN); - - return HAL_OK; -} - -/** - * @brief Handle BatteryCharging Process. - * @param hpcd PCD handle - * @retval HAL status - */ -void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) -{ - USB_DRD_TypeDef *USBx = hpcd->Instance; - uint32_t tickstart = HAL_GetTick(); - - /* Wait for Min DCD Timeout */ - HAL_Delay(300U); - - /* Data Pin Contact ? Check Detect flag */ - if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - /* Primary detection: checks if connected to Standard Downstream Port - (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - HAL_Delay(50U); - USBx->BCDR |= (USB_BCDR_PDEN); - HAL_Delay(50U); - - /* If Charger detect ? */ - if ((USBx->BCDR & USB_BCDR_PDET) == USB_BCDR_PDET) - { - /* Start secondary detection to check connection to Charging Downstream - Port or Dedicated Charging Port */ - USBx->BCDR &= ~(USB_BCDR_PDEN); - HAL_Delay(50U); - USBx->BCDR |= (USB_BCDR_SDEN); - HAL_Delay(50U); - - /* If CDP ? */ - if ((USBx->BCDR & USB_BCDR_SDET) == USB_BCDR_SDET) - { - /* Dedicated Downstream Port DCP */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DEDICATED_CHARGING_PORT); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { - /* Charging Downstream Port CDP */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CHARGING_DOWNSTREAM_PORT); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - } - else /* NO */ - { - /* Standard Downstream Port */ -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_STD_DOWNSTREAM_PORT); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - /* Battery Charging capability discovery finished Start Enumeration */ - (void)HAL_PCDEx_DeActivateBCD(hpcd); - - /* Check for the Timeout, else start USB Device */ - if ((HAL_GetTick() - tickstart) > 1000U) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_ERROR); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_ERROR); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - else - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_DISCOVERY_COMPLETED); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } -} - - -/** - * @brief Activate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) -{ - - USB_DRD_TypeDef *USBx = hpcd->Instance; - hpcd->lpm_active = 1U; - hpcd->LPM_State = LPM_L0; - - USBx->LPMCSR |= USB_LPMCSR_LMPEN; - USBx->LPMCSR |= USB_LPMCSR_LPMACK; - - return HAL_OK; -} - -/** - * @brief Deactivate LPM feature. - * @param hpcd PCD handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) -{ - USB_DRD_TypeDef *USBx = hpcd->Instance; - - hpcd->lpm_active = 0U; - - USBx->LPMCSR &= ~(USB_LPMCSR_LMPEN); - USBx->LPMCSR &= ~(USB_LPMCSR_LPMACK); - - return HAL_OK; -} - -#endif /* defined (USB_DRD_FS) */ - -/** - * @brief Send LPM message to user layer callback. - * @param hpcd PCD handle - * @param msg LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_LPM_Callback could be implemented in the user file - */ -} - -/** - * @brief Send BatteryCharging message to user layer callback. - * @param hpcd PCD handle - * @param msg LPM message - * @retval HAL status - */ -__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hpcd); - UNUSED(msg); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PCDEx_BCD_Callback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ -#endif /* HAL_PCD_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c deleted file mode 100644 index a7a6fbda3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr.c +++ /dev/null @@ -1,960 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pwr.c - * @author MCD Application Team - * @brief PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller (PWR) peripheral: - * + Initialization/De-Initialization Functions. - * + Peripheral Control Functions. - * + PWR Attributes Functions. - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### PWR peripheral overview ##### - ============================================================================== - [..] - (#) The Power control (PWR) provides an overview of the supply architecture - for the different power domains and of the supply configuration - controller. - - (#) Domain architecture overview for the U5 devices: - (+) U5 devices have 2 power domains (CD and SRD). - The core domain (CD) contains a CPU (Cortex-M33), a Flash memory and - some peripherals dedicated for general purpose. The SRD domain - contains the system control and low-power peripherals. - - (#) Every entity has low power mode as described below : - (#) The CPU low power modes are : - (+) CPU CRun. - (+) CPU CSleep. - (+) CPU CStop. - (#) The system low power modes are : - (+) Run. - (+) Stop 0. - (+) Stop 1. - (+) Stop 2. - (+) Stop 3. - (+) Standby. - (+) Shutdown. - - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) After startup, power management peripheral is not active by default. Use - __HAL_RCC_PWR_CLK_ENABLE() macro to enable power interface. - - (#) Call HAL_PWR_EnableBkUpAccess() and HAL_PWR_DisableBkUpAccess() functions - to enable/disable access to the backup domain (RCC Backup domain control - register RCC_BDCR, RTC registers, TAMP registers, backup registers and - backup SRAM). - - (#) Call HAL_PWR_ConfigPVD() after setting parameters to be configured (event - mode and voltage threshold) in order to set up the Programmed Voltage - Detector, then use HAL_PWR_EnablePVD() and HAL_PWR_DisablePVD() - functions to start and stop the PVD detection. - (+) PVD level can be one of the following values : - (++) 2V0 - (++) 2V2 - (++) 2V4 - (++) 2V5 - (++) 2V6 - (++) 2V8 - (++) 2V9 - (++) External input analog voltage PVD_IN (compared internally to - VREFINT) - - (#) Call HAL_PWR_EnableWakeUpPin() and HAL_PWR_DisableWakeUpPin() functions - with the right parameter to configure the wake up pin polarity (Low or - High), the wake up pin selection and to enable and disable it. - - (#) Call HAL_PWR_EnterSLEEPMode() function to enter the CPU in Sleep mode. - Wake-up from Sleep mode could be following to an event or an - interrupt according to low power mode intrinsic request called (__WFI() - or __WFE()). - - (#) Call HAL_PWR_EnterSTOPMode() function to enter the whole system to Stop 0 - mode. Wake-up from Stop 0 mode could be following to an event or an - interrupt according to low power mode intrinsic request called (__WFI() - or __WFE()). (Regulator state on U5 devices is managed internally but - regulator parameter is kept for product compatibility). - - (#) Call HAL_PWR_EnterSTANDBYMode() function to enter the whole system in - Standby mode. Wake-up from Standby mode can be following only by an - interrupt. - - (#) Call HAL_PWR_EnableSleepOnExit() and HAL_PWR_DisableSleepOnExit() APIs to - enable and disable the Cortex-M33 re-entry in Sleep mode after an - interruption handling is over. - - (#) Call HAL_PWR_EnableSEVOnPend() and HAL_PWR_DisableSEVOnPend() functions - to configure the Cortex-M33 to wake-up after any pending event / interrupt - even if it's disabled or has insufficient priority to cause exception - entry. - - (#) Call HAL_PWR_PVD_IRQHandler() under PVD_AVD_IRQHandler() function to - handle the PWR PVD interrupt request. - - (#) Call HAL_PWR_ConfigAttributes() function to configure PWR item secure and - privilege attributes and call HAL_PWR_GetConfigAttributes() function to - get the attribute configuration for the selected item. - - *** PWR HAL driver macros list *** - ============================================= - [..] - Below the list of most used macros in PWR HAL driver. - - (+) __HAL_PWR_GET_FLAG() : Get the PWR pending flags. - (+) __HAL_PWR_CLEAR_FLAG() : Clear the PWR pending flags. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup PWR PWR - * @brief PWR HAL module driver - * @{ - */ - -#if defined (HAL_PWR_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup PWR_Private_Defines PWR Private Defines - * @{ - */ - -/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask - * @{ - */ -#define PVD_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVD trigger */ -#define PVD_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVD trigger */ -#define PVD_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVD threshold crossing */ -#define PVD_MODE_EVT (0x08U) /*!< Mask for event yielded by PVD threshold crossing */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWR_Exported_Functions PWR Exported Functions - * @{ - */ - -/** @defgroup PWR_Exported_Functions_Group1 Initialization and De-Initialization Functions - * @brief Initialization and de-Initialization functions - * -@verbatim - =============================================================================== - ##### Initialization and De-Initialization Functions ##### - =============================================================================== - [..] - This section provides functions allowing to deinitialize power peripheral - and to manage backup domain access. - - [..] - After system reset, the backup domain (RCC Backup domain control register - RCC_BDCR, RTC registers, TAMP registers, backup registers and backup SRAM) - is protected against possible unwanted write accesses. - The HAL_PWR_EnableBkUpAccess() function enables the access to the backup - domain. - The HAL_PWR_DisableBkUpAccess() function disables the access to the backup - domain. - -@endverbatim - * @{ - */ - -/** - * @brief Deinitialize the HAL PWR peripheral registers to their default reset - * values. - * @note This functionality is not available in this product. - * The prototype is kept just to maintain compatibility with other - * products. - * @retval None. - */ -void HAL_PWR_DeInit(void) -{ -} - -/** - * @brief Enable access to the backup domain (RCC Backup domain control - * register RCC_BDCR, RTC registers, TAMP registers, backup registers - * and backup SRAM). - * @note After a system reset, the backup domain is protected against - * possible unwanted write accesses. - * @retval None. - */ -void HAL_PWR_EnableBkUpAccess(void) -{ - SET_BIT(PWR->DBPR, PWR_DBPR_DBP); -} - -/** - * @brief Disable access to the backup domain (RCC Backup domain control - * register RCC_BDCR, RTC registers, TAMP registers, backup registers - * and backup SRAM). - * @retval None. - */ -void HAL_PWR_DisableBkUpAccess(void) -{ - CLEAR_BIT(PWR->DBPR, PWR_DBPR_DBP); -} -/** - * @} - */ - - -/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control Functions - * @brief Low power modes configuration functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This section provides functions allowing to control power peripheral. - - *** PVD configuration *** - ========================= - [..] - (+) The PVD can be used to monitor the VDD power supply by comparing it - to a threshold selected by the PVDLS[2:0] bits in the PWR supply - voltage monitoring control register (PWR_SVMCR) and can be enabled by - setting the PVDE bit. - - (+) A PVDO flag is available in the PWR supply voltage monitoring control - register (PWR_SVMCR) to indicate if VDD is higher or lower than the - PVD threshold. This event is internally connected to the EXTI line 16 - and can generate an interrupt if enabled through the EXTI registers. - It is configurable through __HAL_PWR_PVD_EXTI_ENABLE_IT() macro. - - (+) The PVD can remain active in Stop 0, Stop 1, Stop 2 modes, and the PVM - interrupt can wake up from the Stop mode. The PVD is not functional in - Stop 3 mode. - - (+) During Stop 1, Stop 2 and Stop 3 modes, it is possible to set the PVD - in ultra-low-power mode to further reduce the current consumption by - setting the ULPMEN bit in PWR_CR1 register. - - *** Wake-up pin configuration *** - ================================= - [..] - (+) Wake-up pin is used to wake up the system from Stop 3, Standby and - Shutdown mode. - The pin selection is configurable through the WUCR3 register to map - internal signal to wake up pin line. - The pin polarity is configurable through the WUCR2 register to be - active on rising or falling edges. - - (+) There are up to 24 wake-up signals that can be mapped to up to 8 - wake-up lines in the STM32U5 family. - - *** Low Power modes configuration *** - ===================================== - [..] - This section presents 3 principles low-power modes : - (+) Sleep mode : Cortex-M33 is stopped and all PWR domains are remaining - active (powered and clocked). - - (+) Stop 0 mode : Cortex-M33 is stopped, clocks are stopped and the - regulator is running. - - (+) Standby mode : All PWR domains enter DSTANDBY mode and the VCORE - supply regulator is powered off. - - *** Sleep mode *** - ================== - [..] - (+) Entry : - The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode() - function. - - (++) PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. - (++) PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and - clear of pending events before. - (++) PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR: Enter SLEEP mode with WFE instruction and - no clear of pending event before. - - -@@- The Regulator parameter is not used for the STM32U5 family and is - kept as parameter just to maintain compatibility with other families. - - (+) Exit : - According to Sleep entry, any event when entry is __WFE() intrinsic - and any interrupt when entry is __WFI() intrinsic can wake up the - device from Sleep mode. - - *** Stop 0 mode *** - =================== - [..] - The Stop 0 mode is based on the Cortex-M33 Deepsleep mode combined with - the peripheral clock gating. The voltage regulator is configured in main - regulator mode. In Stop 0 mode, all clocks in the VCORE domain are stopped. - The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. - Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or - MSIK for transferring data. All SRAMs and register contents are preserved, - but the SRAMs can be totally or partially switched off to further reduced - consumption. - The BOR is always available in Stop 0 mode. - - (+) Entry: - The Stop mode is entered using the HAL_PWR_EnterSTOPMode() function - with : - - (++) StopEntry: - (+++) PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. - (+++) PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and - clear of pending events before. - (+++) PWR_STOPENTRY_WFE_NO_EVT_CLEAR: Enter STOP mode with WFE instruction and - no clear of pending event before. - - -@@- The Regulator parameter is not used for the STM32U5 family and is - kept as parameter just to maintain compatibility with other families. - - (+) Exit: - Any EXTI line configured in interrupt mode (the corresponding EXTI - interrupt vector must be enabled in the NVIC). The interrupt source - can be external interrupts or peripherals with wakeup capability. - Any peripheral interrupt occurring when the AHB/APB clocks are present - due to an autonomous peripheral clock request (the peripheral vector - must be enabled in the NVIC). - - *** Standby mode *** - ==================== - [..] - The Standby mode is used to achieve the lowest power consumption with BOR. - The internal regulator is switched off so that the VCORE domain is powered - off. - The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and the HSE crystal - oscillators are also switched off. - The RTC can remain active (Standby mode with RTC, Standby mode without - RTC). - The Brownout reset (BOR) always remains active in Standby mode. - The state of each I/O during Standby mode can be selected by software: - I/O with internal pull-up, internal pull-down or floating. - After entering Standby mode, SRAMs and register contents are lost except - for registers and backup SRAM in the Backup domain and Standby circuitry. - Optionally, the full SRAM2 or 8 Kbytes or 56 Kbytes can be retained in - Standby mode, supplied by the low-power regulator (Standby with RAM2 - retention mode). - The BORL (Brownout reset detector low) can be configured in ultra low - power mode to further reduce power consumption during Standby mode. - The device exits Standby mode upon an external reset (NRST pin), an IWDG - reset, WKUP pin event (configurable rising or falling edge), an RTC event - occurs (alarm, periodic wakeup, timestamp), or a tamper detection. - The system clock after wakeup is MSIS up to 4 MHz. - - (++) Entry: - The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() - function. - - (++) Exit: - WKUPx pin edge, RTC event, external Reset in NRST pin, IWDG Reset, - BOR reset. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the voltage threshold detected by the Programmed Voltage - * Detector (PVD). - * @param pConfigPVD : Pointer to a PWR_PVDTypeDef structure that contains the - * PVD configuration information (PVDLevel and EventMode). - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *pConfigPVD) -{ - /* Check the PVD parameter */ - if (pConfigPVD == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PWR_PVD_LEVEL(pConfigPVD->PVDLevel)); - assert_param(IS_PWR_PVD_MODE(pConfigPVD->Mode)); - - /* Set PVDLS[2:0] bits according to PVDLevel value */ - MODIFY_REG(PWR->SVMCR, PWR_SVMCR_PVDLS, pConfigPVD->PVDLevel); - - /* Disable PVD Event/Interrupt */ - __HAL_PWR_PVD_EXTI_DISABLE_EVENT(); - __HAL_PWR_PVD_EXTI_DISABLE_IT(); - __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure the PVD in interrupt mode */ - if ((pConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT) - { - __HAL_PWR_PVD_EXTI_ENABLE_IT(); - } - - /* Configure the PVD in event mode */ - if ((pConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT) - { - __HAL_PWR_PVD_EXTI_ENABLE_EVENT(); - } - - /* Configure the PVD in rising edge */ - if ((pConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE(); - } - - /* Configure the PVD in falling edge */ - if ((pConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE) - { - __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); - } - - return HAL_OK; -} - -/** - * @brief Enable the programmable voltage detector (PVD). - * @retval None. - */ -void HAL_PWR_EnablePVD(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); -} - -/** - * @brief Disable the programmable voltage detector (PVD). - * @retval None. - */ -void HAL_PWR_DisablePVD(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_PVDE); -} - -/** - * @brief Enable the wake up line functionality. - * @note Wake up lines are used to wake up the system from Stop 3, Standby and - * Shutdown modes. - * @param WakeUpPin : Specifies which wake up line to enable. This parameter - * can be one of PWR_WakeUp_Pins_High_Polarity define - * group where every param select the wake up line, the - * wake up source with high polarity detection and the wake - * up selected I/O or can be one of - * PWR_WakeUp_Pins_Low_Polarity define group where every - * param select the wake up line, the wake up source with - * low polarity and the wake up selected I/O or can be one - * of PWR_WakeUp_Pins define group where every param select - * the wake up line, the wake up source with - * high polarity and the first wake up I/O. - * @retval None. - */ -void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) -{ - /* Check the parameter */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); - - /* Specifies the wake up line polarity for the event detection (rising or falling edge) */ - MODIFY_REG(PWR->WUCR2, (PWR_EWUP_MASK & WakeUpPin), (WakeUpPin >> PWR_WUP_POLARITY_SHIFT)); - - /* Specifies the wake up line I/O selection */ - MODIFY_REG(PWR->WUCR3, (3UL << (POSITION_VAL(PWR_EWUP_MASK & WakeUpPin) * 2U)), - (WakeUpPin >> PWR_WUP_SELECT_SIGNAL_SHIFT)); - - /* Enable wake-up line */ - SET_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); -} - -/** - * @brief Disable the wake up line functionality. - * @param WakeUpPin : Specifies the wake up line to disable. - * This parameter can be a combination of all the following - * values : - * @arg @ref PWR_WAKEUP_PIN1 - * @arg @ref PWR_WAKEUP_PIN2 - * @arg @ref PWR_WAKEUP_PIN3 - * @arg @ref PWR_WAKEUP_PIN4 - * @arg @ref PWR_WAKEUP_PIN6 - * @arg @ref PWR_WAKEUP_PIN5 - * @arg @ref PWR_WAKEUP_PIN7 - * @arg @ref PWR_WAKEUP_PIN8 - * @retval None - */ -void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) -{ - /* Check the parameters */ - assert_param(IS_PWR_WAKEUP_PIN(WakeUpPin)); - - /* Disable wake-up pin */ - CLEAR_BIT(PWR->WUCR1, (PWR_EWUP_MASK & WakeUpPin)); -} - -/** - * @brief Enter the CPU in Sleep mode. - * @note In Sleep mode, all I/O pins keep the same state as in Run mode. - * @note CPU clock is off and all peripherals including Cortex-M33 core such - * as NVIC and SysTick can run and wake up the CPU when an interrupt - * or an event occurs. - * @param Regulator : Specifies the regulator state in Sleep mode. - * This parameter can be one of the following values : - * @arg @ref PWR_MAINREGULATOR_ON - * @arg @ref PWR_LOWPOWERREGULATOR_ON - * @note This parameter is not available in this product. - * The parameter is kept just to maintain compatibility with other - * products. - * @param SleepEntry : Specifies if Sleep mode is entered with WFI or WFE - * instruction. - * @arg PWR_SLEEPENTRY_WFI : Enter SLEEP mode with WFI instruction. - * @arg PWR_SLEEPENTRY_WFE : Enter SLEEP mode with WFE instruction and - * clear of pending events before. - * @arg PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR : Enter SLEEP mode with WFE instruction and - * no clear of pending event before. - * @retval None. - */ -void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SleepEntry) -{ - UNUSED(Regulator); - - /* Check the parameter */ - assert_param(IS_PWR_SLEEP_ENTRY(SleepEntry)); - - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Sleep mode entry */ - if (SleepEntry == PWR_SLEEPENTRY_WFI) - { - /* Wait For Interrupt Request */ - __WFI(); - } - else - { - if (SleepEntry != PWR_SLEEPENTRY_WFE_NO_EVT_CLEAR) - { - /* Clear all pending event */ - __SEV(); - __WFE(); - } - - /* Request Wait For Event */ - __WFE(); - } -} - -/** - * @brief Enter the whole system to Stop 0 mode. - * @note In Stop 0 mode, the regulator remains in main regulator mode, - * allowing a very fast wakeup time but with much higher consumption - * comparing to other Stop modes. - * @note Stop 0 offers the largest number of active peripherals and wakeup - * sources, a smaller wakeup time but a higher consumption. - * Stop mode achieves the lowest power consumption while retaining - * the content of SRAM and registers. All clocks in the VCORE domain - * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and - * the HSE crystal oscillators are disabled. The LSE or LSI is still - * running. - * @note The system clock when exiting from Stop mode can be either MSIS up - * to 24 MHz or HSI16, depending on software configuration. - * @param Regulator : Specifies the regulator state in Stop mode. - * This parameter can be one of the following values : - * @arg @ref PWR_MAINREGULATOR_ON - * @arg @ref PWR_LOWPOWERREGULATOR_ON - * @note This parameter is not available in this product. - * The parameter is kept just to maintain compatibility with other - * products. - * @param StopEntry : Specifies if Stop mode is entered with WFI or WFE - * instruction. - * This parameter can be one of the following values : - * @arg PWR_STOPENTRY_WFI : Enter STOP mode with WFI instruction. - * @arg PWR_STOPENTRY_WFE : Enter STOP mode with WFE instruction and - * clear of pending events before. - * @arg PWR_STOPENTRY_WFE_NO_EVT_CLEAR : Enter STOP mode with WFE instruction and - * no clear of pending event before. - * @note In System STOP mode, all I/O pins keep the same state as in Run mode. - * @retval None. - */ -void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t StopEntry) -{ - UNUSED(Regulator); - - /* Check the parameter */ - assert_param(IS_PWR_STOP_ENTRY(StopEntry)); - - /* Select Stop 0 mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, 0U); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry */ - if (StopEntry == PWR_STOPENTRY_WFI) - { - /* Wait For Interrupt Request */ - __WFI(); - } - else - { - if (StopEntry != PWR_STOPENTRY_WFE_NO_EVT_CLEAR) - { - /* Clear all pending event */ - __SEV(); - __WFE(); - } - - /* Request Wait For Event */ - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enter the whole system to Standby mode. - * @note The Standby mode is used to achieve the lowest power consumption - * with BOR. The internal regulator is switched off so that the VCORE - * domain is powered off. The PLL, the MSI (MSIS and MSIK) RC, the - * HSI16 RC and the HSE crystal oscillators are also switched off. - * @note After entering Standby mode, SRAMs and register contents are lost - * except for registers and backup SRAM in the Backup domain and - * Standby circuitry. Optionally, the full SRAM2 or 8 Kbytes or 56 - * Kbytes can be retained in Standby mode, supplied by the low-power - * regulator (Standby with RAM2 retention mode) through - * HAL_PWREx_EnableSRAM2ContentStandbyRetention(). - * @note The state of each I/O during Standby mode can be selected by - * software : I/O with internal pull-up through - * HAL_PWREx_EnableGPIOPullUp() and internal pull-down through - * HAL_PWREx_EnableGPIOPullDown(). - * @retval None. - */ -void HAL_PWR_EnterSTANDBYMode(void) -{ - /* Select Standby mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_2); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Wait For Interrupt Request */ - __WFI(); -} - -/** - * @brief Indicate SLEEP-ON-EXIT feature when returning from handler mode to - * thread mode. - * @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the - * processor re-enters Sleep mode when an interruption handling is over. - * Setting this bit is useful when the processor is expected to run - * only on interruptions handling. - * @retval None. - */ -void HAL_PWR_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex-M33 System Control Register */ - SET_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); -} - -/** - * @brief Disable SLEEP-ON-EXIT feature when returning from handler mode to - * thread mode. - * @note Clears SLEEPONEXIT bit of SCR register. When this bit is set, the - * processor re-enters Sleep mode when an interruption handling is over. - * @retval None. - */ -void HAL_PWR_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex-M33 System Control Register */ - CLEAR_BIT(SCB->SCR, SCB_SCR_SLEEPONEXIT_Msk); -} - -/** - * @brief Enable CORTEX SEV-ON-PEND feature. - * @note Sets SEVONPEND bit of SCR register. When this bit is set, any - * pending event / interrupt even if it's disabled or has insufficient - * priority to cause exception entry wakes up the Cortex-M33. - * @retval None. - */ -void HAL_PWR_EnableSEVOnPend(void) -{ - /* Set SEVONPEND bit of Cortex-M33 System Control Register */ - SET_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); -} - -/** - * @brief Disable CORTEX SEVONPEND feature. - * @note Resets SEVONPEND bit of SCR register. When this bit is reset, only enabled - * pending event / interrupt to cause exception entry wakes up the Cortex-M33. - * @retval None. - */ -void HAL_PWR_DisableSEVOnPend(void) -{ - /* Clear SEVONPEND bit of Cortex-M33 System Control Register */ - CLEAR_BIT(SCB->SCR, SCB_SCR_SEVONPEND_Msk); -} - -/** - * @brief This function handles the PWR PVD interrupt request. - * @note This API should be called under the PVD_AVD_IRQHandler(). - * @retval None. - */ -void HAL_PWR_PVD_IRQHandler(void) -{ - uint32_t rising_flag; - uint32_t falling_flag; - - /* Get pending flags */ - rising_flag = READ_REG(EXTI->RPR1); - falling_flag = READ_REG(EXTI->FPR1); - - /* Check PWR EXTI flags for PVD */ - if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PVD EXTI pending bit */ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); - } -} - -/** - * @brief PWR PVD interrupt callback. - * @retval None. - */ -__weak void HAL_PWR_PVDCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_PWR_PVDCallback can be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup PWR_Exported_Functions_Group3 Attributes Management Functions - * @brief Attributes management functions - * -@verbatim - =============================================================================== - ##### PWR Attributes Functions ##### - =============================================================================== - [..] - When the TrustZone security is activated by the TZEN option bit in the - FLASH_OPTR register, some PWR register fields can be secured against - non-secure access. - The PWR TrustZone security allows the following features to be secured - through the PWR_SECCFGR register : - - (++) Low-power mode. - (++) Wake-up (WKUP) pins. - (++) Voltage detection and monitoring. - (++) VBAT mode. - (++) I/Os pull-up/pull-down configuration. - - Other PWR configuration bits are secure when : - (++) The system clock selection is secure in RCC: the voltage scaling - (VOS) configuration and the regulator booster (BOOSTEN) are secure. - (++) A GPIO is configured as secure: its corresponding bit for pull-up / - pull-down configuration in Standby mode is secure. - (++) The UCPD1 is secure in the GTZC: the PWR_UCPDR register is secure. - - A non-secure access to a secure-protected register bit is denied : - (++) The secured bits are not written (WI) with a non-secure write access. - (++) The secured bits are read as 0 (RAZ) with a non-secure read access. - - [..] - When the TrustZone security is disabled (TZEN = 0), PWR_SECCFGR is RAZ/WI - and all other registers are non-secure. - - [..] - By default, after a reset, all PWR registers can be read or written with - both privileged and unprivileged accesses, except PWR_PRIVCFGR that can be - written with privileged access only. PWR_PRIVCFGR can be read by secure - and non secure, privileged and unprivileged accesses. - The SPRIV bit in PWR_PRIVCFGR can be written with secure privileged access - only. This bit configures the privileged access of all PWR secure - functions (defined by PWR_SECCFGR, GTZC, RCC or GPIO). - When the SPRIV bit is set in PWR_PRIVCFGR: - (++) The PWR secure bits can be written only with privileged access, - including PWR_SECCFGR. - (++) The PWR secure bits can be read only with privileged access except - PWR_SECCFGR and PWR_PRIVCFGR that can be read by privileged or - unprivileged access. - (++) An unprivileged access to a privileged PWR bit or register is - discarded : the bits are read as zero and the write to these bits is - ignored (RAZ/WI). - The NSPRIV bit of PWR_PRIVCFGR can be written with privileged access only, - secure or non-secure. This bit configures the privileged access of all PWR - securable functions that are configured as non-secure (defined by - PWR_SECCFGR, GTZC, RCC or GPIO). - When the NSPRIV bit is set in PWR_PRIVCFGR : - (++) The PWR securable bits that are configured as non-secure, can be - written only with privileged access. - (++) The PWR securable bits that are configured as non-secure, can be read - only with privileged access except PWR_PRIVCFGR that can be read by - privileged or unprivileged accesses. - (++) The VOSRDY and BOOSTRDY bits in PWR_VOSR, PWR_SR, PWR_SVMSR, PWR_BDSR - and PWR_WUSR, can be read with privileged or unprivileged accesses. - (++) An unprivileged access to a privileged PWR bit or register is - discarded : the bits are read as zero and the write to these bits is - ignored (RAZ/WI). - -@endverbatim - * @{ - */ - -/** - * @brief Configure the PWR item attributes. - * @note Available attributes are security and privilege protection. - * @note Security attribute can only be set only by secure access. - * @note Privilege attribute for secure items can be managed only by a secure - * privileged access. - * @note Privilege attribute for nsecure items can be managed by a secure - * privileged access or by a nsecure privileged access. - * @param Item : Specifies the item(s) to set attributes on. - * This parameter can be a combination of @ref PWR_Items. - * @param Attributes : Specifies the available attribute(s). - * This parameter can be one of @ref PWR_Attributes. - * @retval None. - */ -void HAL_PWR_ConfigAttributes(uint32_t Item, uint32_t Attributes) -{ - /* Check the parameters */ - assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); - assert_param(IS_PWR_ATTRIBUTES(Attributes)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Secure item management (TZEN = 1) */ - if ((Attributes & PWR_ITEM_ATTR_SEC_PRIV_MASK) == PWR_ITEM_ATTR_SEC_PRIV_MASK) - { - /* Privilege item management */ - if ((Attributes & PWR_SEC_PRIV) == PWR_SEC_PRIV) - { - SET_BIT(PWR->SECCFGR, Item); - SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); - } - else - { - SET_BIT(PWR->SECCFGR, Item); - CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_SPRIV); - } - } - /* NSecure item management */ - else - { - /* Privilege item management */ - if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) - { - CLEAR_BIT(PWR->SECCFGR, Item); - SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); - } - else - { - CLEAR_BIT(PWR->SECCFGR, Item); - CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); - } - } -#else - /* Prevent unused argument(s) compilation warning */ - UNUSED(Item); - - /* NSecure item management (TZEN = 0) */ - if ((Attributes & PWR_ITEM_ATTR_NSEC_PRIV_MASK) == PWR_ITEM_ATTR_NSEC_PRIV_MASK) - { - /* Privilege item management */ - if ((Attributes & PWR_NSEC_PRIV) == PWR_NSEC_PRIV) - { - SET_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); - } - else - { - CLEAR_BIT(PWR->PRIVCFGR, PWR_PRIVCFGR_NSPRIV); - } - } -#endif /* __ARM_FEATURE_CMSE */ -} - -/** - * @brief Get attribute(s) of a PWR item. - * @param Item : Specifies the item(s) to get attributes of. - * This parameter can be one of @ref PWR_Items. - * @param pAttributes : Pointer to return attribute(s). - * Returned value could be one of @ref PWR_Attributes. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWR_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) -{ - uint32_t attributes; - - /* Check attribute pointer */ - if (pAttributes == NULL) - { - return HAL_ERROR; - } - - /* Check the parameter */ - assert_param(IS_PWR_ITEMS_ATTRIBUTES(Item)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Check item security */ - if ((PWR->SECCFGR & Item) == Item) - { - /* Get Secure privileges attribute */ - attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_SPRIV) == 0U) ? PWR_SEC_NPRIV : PWR_SEC_PRIV; - } - else - { - /* Get Non-Secure privileges attribute */ - attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; - } -#else - /* Get Non-Secure privileges attribute */ - attributes = ((PWR->PRIVCFGR & PWR_PRIVCFGR_NSPRIV) == 0U) ? PWR_NSEC_NPRIV : PWR_NSEC_PRIV; -#endif /* __ARM_FEATURE_CMSE */ - - /* return value */ - *pAttributes = attributes; - - return HAL_OK; -} -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (HAL_PWR_MODULE_ENABLED) */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c deleted file mode 100644 index 0dc86b9ab..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_pwr_ex.c +++ /dev/null @@ -1,2811 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_pwr_ex.c - * @author MCD Application Team - * @brief Extended PWR HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Power Controller extension peripheral : - * + Power Supply Control Functions - * + Low Power Control Functions - * + Voltage Monitoring Functions - * + Memories Retention Functions - * + I/O Pull-Up Pull-Down Configuration Functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Call HAL_PWREx_ControlVoltageScaling() and HAL_PWREx_GetVoltageRange() to - set / get the voltage scaling range. - (+) Voltage scaling can be one of the following values : - (++) voltage output scale 1 : 1V2 - => Used when system clock frequency is up to 160 MHz - (++) voltage output scale 2 : 1V1 - => Used when system clock frequency is up to 100 MHz - (++) voltage output scale 3 : 1V0 - => Used when system clock frequency is up to 50 MHz - (++) voltage output scale 4 : 0V9 - => Used when system clock frequency is up to 24 MHz - - (#) Call HAL_PWREx_EnableFastSoftStart() and HAL_PWREx_DisableFastSoftStart() - to enable / disable the fast software startup for the current regulator. - - (#) Call HAL_PWREx_EnterSTOP1Mode() function to enter the whole system to - Stop 1 mode. Wake-up from Stop 1 mode could be following to an event or - an interrupt according to low power mode intrinsic request called - (__WFI() or __WFE()). (Regulator state on U5 devices is managed - internally but regulator parameter is kept for product compatibility). - - (#) Call HAL_PWREx_EnterSTOP2Mode() function to enter the whole system to - Stop 2 mode. Wake-up from Stop 2 mode could be following to an event or - an interrupt according to low power mode intrinsic request called - (__WFI() or __WFE()). (Regulator state on U5 devices is managed - internally but regulator parameter is kept for product compatibility). - - (#) Call HAL_PWREx_EnterSTOP3Mode() function to enter the whole system to - Stop 3 mode. Wake-up from Stop 3 mode could be following to an event or - an interrupt according to low power mode intrinsic request called - (__WFI() or __WFE()). (Regulator state on U5 devices is managed - internally but regulator parameter is kept for product compatibility). - - (#) Call HAL_PWREx_EnterSHUTDOWNMode() function to enter the whole system in - Shutdown mode. Wake-up from Shutdown mode can be following to an external - reset (NRST pin), a WKUP pin event (configurable rising or falling edge), - or an RTC event occurs (alarm, periodic wakeup, timestamp), or a tamper - detection. - - (#) Call HAL_PWREx_ConfigSRDDomain() to force in Run mode or to enter in Stop - mode Smart Run Domain when the system enters Stop mode (Stop 0/1/2). - - (#) Call HAL_PWREx_EnableUltraLowPowerMode() and - HAL_PWREx_DisableUltraLowPowerMode() to enable / disable the BOR ultra - low power mode. - - (#) Call HAL_PWREx_S3WU_IRQHandler() function to handle the PWR Stop 3 wake - up interrupt request. - - (#) Call HAL_PWREx_EnableBatteryCharging() and - HAL_PWREx_DisableBatteryCharging() to enable / disable the battery - charging capability when VDD alimentation is available. - - (#) Call HAL_PWREx_EnableVddUSB(), HAL_PWREx_EnableVddIO2() and - HAL_PWREx_EnableVddA() to enable respectively VDDUSB, VDDIO2 and VDDA - electrical and logical isolation. - It is recommended to disable VDDUSB, VDDIO2 and VDDA electrical and - logical isolation through HAL_PWREx_DisableVddUSB(), - HAL_PWREx_DisableVddIO2() and HAL_PWREx_DisableVddA(). - - (#) Call HAL_PWREx_ConfigPVM() after setting parameters to be configured - (event mode and PVD type) in order to set up the Peripheral Voltage - Monitor, then use HAL_PWREx_EnableUVM(), HAL_PWREx_EnableIO2VM(), - HAL_PWREx_EnableAVM1() and HAL_PWREx_EnableAVM2() functions to start the - PVM VDDx monitoring and use HAL_PWREx_DisableUVM(), - HAL_PWREx_DisableIO2VM(), HAL_PWREx_DisableAVM1() and - HAL_PWREx_DisableAVM2() to stop the PVM VDDx monitoring. - (+) PVM monitored voltages are : - (++) VDDUSB versus 1V2 - (++) VDDIO2 versus 0V9 - (++) VDDA versus 1V6 - (++) VDDA versus 1V8 - - (#) Call HAL_PWREx_EnableUSBHSTranceiverSupply() and - HAL_PWREx_DisableUSBHSTranceiverSupply() to enable / disable the internal - USB HS transceiver supply. - (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - and STM32U5Gxxx devices - - (#) Call HAL_PWREx_EnableOTGHSPHYLowPowerRetention() and - HAL_PWREx_DisableOTGHSPHYLowPowerRetention() to enable / disable OTG_HS PHY power during - low power modes (Stop2, Stop3 and Standby). - (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - and STM32U5Gxxx devices - - (#) Call HAL_PWREx_EnableVDD11USB() and - HAL_PWREx_DisableVDD11USB() to enable/ disable the VDD11USB. - (+) This feature is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - and STM32U5Gxxx devices - - (#) Call HAL_PWREx_EnableMonitoring() and HAL_PWREx_DisableMonitoring() to - enable / disable the VBAT and temperature monitoring. - - (#) Call HAL_PWREx_EnableUCPDStandbyMode() and - HAL_PWREx_DisableUCPDStandbyMode() to enable / disable the UCPD - configuration memorization in Standby mode. - - (#) Call HAL_PWREx_EnableUCPDDeadBattery() and - HAL_PWREx_DisableUCPDDeadBattery() to enable / disable the dead battery - behavior. - - (#) Call HAL_PWREx_PVD_PVM_IRQHandler() function to handle the PWR PVD and - PVM interrupt request. - - (#) Call HAL_PWREx_EnableSRAM2ContentStandbyRetention() and - HAL_PWREx_DisableSRAM2ContentStandbyRetention() to - enable / disable the SRAM2 content retention in Stop 3 and Standby low - power modes. - - (#) Call HAL_PWREx_EnableRAMsContentStopRetention() and - HAL_PWREx_DisableRAMsContentStopRetention() to - enable / disable the RAMs content retention in Stop mode (Stop 0/1/2/3). - (+) Retained RAM can be one of the following RAMs : - (++) SRAM1 - (++) SRAM2 - (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, - STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) - (++) SRAM4 - (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, - STM32U5Fxxx and STM32U5Gxxx devices) - (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) - (++) ICACHE - (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, - STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) - (++) PKA32RAM - (++) DCACHE1 - (++) FMAC - (++) FDCAN - (++) USB - (++) DCACHE2 (available only for STM32U59xxx, STM32U5Axxx, - STM32U5Fxxx and STM32U5Gxxx devices) - (++) LTDC (available only for STM32U59xxx, STM32U5Axxx, - STM32U5Fxxx and STM32U5Gxxx devices) - (++) GFXMMU (available only for STM32U59xxx, STM32U5Axxx, - STM32U5Fxxx and STM32U5Gxxx devices) - (++) DSI (available only for STM32U59xxx, STM32U5Axxx, - STM32U5Fxxx and STM32U5Gxxx devices) - (++) JPEG (available only for STM32U5Fxxx and STM32U5Gxxx devices) - - (#) Call HAL_PWREx_EnableRAMsContentRunRetention() and - HAL_PWREx_DisableRAMsContentRunRetention() to - enable / disable the RAMs content retention in Run mode. - (+) Retained RAM can be one of the following RAMs : - (++) SRAM1 - (++) SRAM2 - (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, - STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) - (++) SRAM4 - (++) SRAM5 (available only for STM32U59xxx, STM32U5Axxx, - STM32U5Fxxx and STM32U5Gxxx devices) - (++) SRAM6 (available only for STM32U5Fxxx and STM32U5Gxxx devices) - - (#) Call HAL_PWREx_EnableFlashFastWakeUp() and - HAL_PWREx_DisableFlashFastWakeUp() to enable / disable the flash memory - fast wakeup from Stop mode (Stop 0/1). - - (#) Call HAL_PWREx_EnableSRAM4FastWakeUp() and - HAL_PWREx_DisableSRAM4FastWakeUp() to enable / disable the SRAM4 memory - fast wakeup from Stop mode (Stop 0/1/2). - - (#) Call HAL_PWREx_EnableBkupRAMRetention() and - HAL_PWREx_DisableBkupRAMRetention() to enable / disable the Backup RAM - content retention in Standby, Shutdown and VBAT modes. - - (#) Call HAL_PWREx_EnablePullUpPullDownConfig() and - HAL_PWREx_DisablePullUpPullDownConfig() to I/O enable / disable pull-up - and pull-down configuration. - - (#) Call HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() to - apply respectively pull-up and pull-down to selected I/O. - Call HAL_PWREx_DisableGPIOPullUp() and HAL_PWREx_DisableGPIOPullDown() to - disable applied respectively pull-up and pull-down to selected I/O. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup PWREx PWREx - * @brief PWR Extended HAL module driver - * @{ - */ - -#if defined (HAL_PWR_MODULE_ENABLED) - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines - * @{ - */ -#if defined (PWR_PUCRJ_PU0) -/* PORTI pins mask */ -#define PWR_PORTI_AVAILABLE_PINS (0xFFFFU) -/* PORTJ pins mask */ -#define PWR_PORTJ_AVAILABLE_PINS (0x0FFFU) -#else -/* PORTI pins mask */ -#define PWR_PORTI_AVAILABLE_PINS (0x00FFU) -#endif /* defined (PWR_PUCRJ_PU0) */ - -/* Time out value of flags setting */ -#define PWR_FLAG_SETTING_DELAY (0x32U) - -/** @defgroup PWR_PVM_Mode_Mask PWR PVM Mode Mask - * @{ - */ -#define PVM_RISING_EDGE (0x01U) /*!< Mask for rising edge set as PVM trigger */ -#define PVM_FALLING_EDGE (0x02U) /*!< Mask for falling edge set as PVM trigger */ -#define PVM_MODE_IT (0x04U) /*!< Mask for interruption yielded by PVM threshold crossing */ -#define PVM_MODE_EVT (0x08U) /*!< Mask for event yielded by PVM threshold crossing */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions - * @{ - */ - -/** @defgroup PWREx_Exported_Functions_Group1 Power Supply Control Functions - * @brief Power supply control functions - * -@verbatim - =============================================================================== - ##### Power supply control functions ##### - =============================================================================== - [..] - This section provides functions allowing to control power supply. - - [..] - (+) The STM32U5 Series devices embed two regulators : one LDO (linear - voltage regulator) and one SMPS (step down converter) in parallel to - provide the VCORE supply for digital peripherals, SRAM1, SRAM2, SRAM3 - and SRAM4 and embedded Flash memory. - - (+) The SMPS allows the power consumption to be reduced but some - peripherals can be perturbed by the noise generated by the SMPS, - requiring the application to switch to LDO when running this - peripheral in order to reach the best performances. - - (+) The LDO and the SMPS regulators have two modes: Main regulator mode - (used when performance is needed), and Low-power regulator mode. LDO - or SMPS can be used in all voltage scaling ranges, and in all Stop - modes. - - (+) After reset, the regulator is the LDO, in Range 4. Switching to SMPS - provides lower consumption in particular at high VDD voltage. It is - possible to switch from LDO to SMPS, or from SMPS to LDO on the fly in - any range, by configuring the REGSEL bit. It is recommended to switch - first to SMPS before changing the voltage range. - - (+) When exiting the Stop or Standby modes, the regulator is the same than - when entering low power modes. The voltage range is the Range 4. - - (+) Both regulators can provide four different voltages (voltage scaling) - and can operate in Stop modes. - Voltage scaling ranges can be one of the following values : - (++) voltage output scale 1 : 1V2 - => Used when system clock frequency is up to 160 MHz - (++) voltage output scale 2 : 1V1 - => Used when system clock frequency is up to 100 MHz - (++) voltage output scale 3 : 1V0 - => Used when system clock frequency is up to 50 MHz - (++) voltage output scale 4 : 0V9 - => Used when system clock frequency is up to 24 MHz - -@endverbatim - * @{ - */ - -/** - * @brief Configure the main internal regulator output voltage to achieve - * a tradeoff between performance and power consumption. - * @param VoltageScaling : Specifies the regulator output voltage scale. - * This parameter can be one of the following values : - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 : Regulator voltage output scale 1. - * Provides a typical output voltage at 1.2 V. - * Used when system clock frequency is up to 160 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 : Regulator voltage output scale 2. - * Provides a typical output voltage at 1.1 V. - * Used when system clock frequency is up to 100 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE3 : Regulator voltage output scale 3. - * Provides a typical output voltage at 1.0 V. - * Used when system clock frequency is up to 50 MHz. - * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE4 : Regulator voltage output scale 4. - * Provides a typical output voltage at 0.9 V. - * Used when system clock frequency is up to 24 MHz. - * @note Before moving to voltage scaling 2, it is mandatory to ensure that - * the system frequency is between 50 MHz and 100 MHz. - * @note Before moving to voltage scaling 3, it is mandatory to ensure that - * the system frequency is between 24 MHz and 50 MHz. - * @note Before moving to voltage scaling 4, it is mandatory to ensure that - * the system frequency is below 24 MHz. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) -{ - uint32_t timeout; - uint32_t vos_old; - - /* Check the parameter */ - assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); - - /* Get the current voltage scale applied */ - vos_old = READ_BIT(PWR->SVMSR, PWR_SVMSR_ACTVOS); - - /* No change, nothing to do */ - if (vos_old == VoltageScaling) - { - /* Enable USB BOOST after wake up from Stop mode */ - if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3) - { - /* Enable USB BOOST */ - SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); - } - - return HAL_OK; - } - - /* Check voltage scaling level */ - /* - * The Embedded power distribution (EPOD) must be enabled before switching to - * voltage scale 1 / 2 from voltage scale lower. - */ - if (VoltageScaling > PWR_REGULATOR_VOLTAGE_SCALE3) - { - MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), (VoltageScaling | PWR_VOSR_BOOSTEN)); - } - else - { - MODIFY_REG(PWR->VOSR, (PWR_VOSR_VOS | PWR_VOSR_BOOSTEN), VoltageScaling); - } - - /* Wait until VOSRDY is raised */ - timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; - while (HAL_IS_BIT_CLR(PWR->VOSR, PWR_VOSR_VOSRDY) && (timeout != 0U)) - { - timeout--; - } - - /* Check time out */ - if (timeout != 0U) - { - /* Wait until ACTVOSRDY is raised */ - timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; - while ((HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_ACTVOSRDY)) && (timeout != 0U)) - { - timeout--; - } - } - - /* Check time out */ - if (timeout == 0U) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Return Voltage Scaling Range. - * @retval Applied voltage scaling value. - */ -uint32_t HAL_PWREx_GetVoltageRange(void) -{ - return (PWR->SVMSR & PWR_SVMSR_ACTVOS); -} - -/** - * @brief Configure the system Power Supply. - * @param SupplySource : Specifies the Power Supply source to set after a - * system startup. - * This parameter can be one of the following values : - * @arg PWR_LDO_SUPPLY : The LDO regulator supplies the Vcore Power Domains. - * @arg PWR_SMPS_SUPPLY : The SMPS regulator supplies the Vcore Power Domains. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_ConfigSupply(uint32_t SupplySource) -{ - uint32_t timeout; - - /* Check the parameter */ - assert_param(IS_PWR_SUPPLY(SupplySource)); - - /* Set maximum time out */ - timeout = ((PWR_FLAG_SETTING_DELAY * (SystemCoreClock / 1000U)) / 1000U) + 1U; - - /* Configure the LDO as system regulator supply */ - if (SupplySource == PWR_LDO_SUPPLY) - { - /* Set the power supply configuration */ - CLEAR_BIT(PWR->CR3, PWR_CR3_REGSEL); - - /* Wait until system switch on new regulator */ - while (HAL_IS_BIT_SET(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U)) - { - timeout--; - } - } - /* Configure the SMPS as system regulator supply */ - else - { - /* Set the power supply configuration */ - SET_BIT(PWR->CR3, PWR_CR3_REGSEL); - - /* Wait until system switch on new regulator */ - while (HAL_IS_BIT_CLR(PWR->SVMSR, PWR_SVMSR_REGS) && (timeout != 0U)) - { - timeout--; - } - } - - /* Check time out */ - if (timeout == 0U) - { - return HAL_TIMEOUT; - } - - return HAL_OK; -} - -/** - * @brief Get the power supply configuration. - * @retval The supply configured. - */ -uint32_t HAL_PWREx_GetSupplyConfig(void) -{ - return (PWR->SVMSR & PWR_SVMSR_REGS); -} - -/** - * @brief Enable fast soft start for the current regulator. - * @retval None. - */ -void HAL_PWREx_EnableFastSoftStart(void) -{ - SET_BIT(PWR->CR3, PWR_CR3_FSTEN); -} - -/** - * @brief Disable fast soft start for the current regulator. - * @retval None. - */ -void HAL_PWREx_DisableFastSoftStart(void) -{ - CLEAR_BIT(PWR->CR3, PWR_CR3_FSTEN); -} -/** - * @} - */ - - -/** @defgroup PWREx_Exported_Functions_Group2 Low Power Control Functions - * @brief Low power control functions - * -@verbatim - =============================================================================== - ##### Low power control functions ##### - =============================================================================== - [..] - This section provides functions allowing to control low power modes. - - *** Low Power modes configuration *** - ===================================== - [..] - This section presents 4 principles low power modes : - (+) Stop 1 mode : Cortex-M33 is stopped, clocks are stopped and the - regulator is in low power mode. Several peripheral can - operate in this mode. - - (+) Stop 2 mode : Cortex-M33 is stopped, clocks are stopped and the - regulator is in low power mode. Only autonomous - peripherals can operate in this mode. - - (+) Stop 3 mode : Cortex-M33 is stopped, clocks are stopped and the - regulator is in low power mode. No peripheral can - operate in this mode. Only RAMs content is preserved. - - (+) Shutdown mode : All PWR domains enter Shutdown mode and the VCORE - supply regulator is powered off. The SRAMs and - register contents are lost except for registers in the - Backup domain. - - *** Stop 1 mode *** - =================== - [..] - The Stop 1 mode is based on the Cortex-M33 Deepsleep mode combined with - the peripheral clock gating. The voltage regulator is configured in low - power mode. In Stop 1 mode, all clocks in the VCORE domain are stopped. - The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. - Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or - MSIK for transferring data. All SRAMs and register contents are preserved, - but the SRAMs can be totally or partially switched off to further reduced - consumption. - The BOR is always available in Stop 1 mode. - - (+) Entry: - The Stop 1 mode is entered by using the HAL_PWREx_EnterSTOP1Mode() - function. - - (++) PWR_STOPENTRY_WFI: enter Stop 1 mode with WFI instruction. - (++) PWR_STOPENTRY_WFE: enter Stop 1 mode with WFE instruction. - - (+) Exit: - Any EXTI line configured in interrupt mode (the corresponding EXTI - interrupt vector must be enabled in the NVIC). The interrupt source - can be external interrupts or peripherals with wakeup capability. - Any peripheral interrupt occurring when the AHB/APB clocks are present - due to an autonomous peripheral clock request (the peripheral vector - must be enabled in the NVIC) - Any EXTI line configured in event mode. - - *** Stop 2 mode *** - =================== - [..] - The Stop 2 mode is based on the Cortex-M33 Deepsleep mode combined with - peripheral clock gating. In Stop 2 mode, all clocks in the VCORE domain - are stopped. - The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. - Some peripherals with the LPBAM capability can switch on HSI16 or MSIS or - MSIK for transferring data. All SRAMs and register contents are preserved, - but the SRAMs can be totally or partially switched off to further reduce - consumption. - The BOR is always available in Stop 2 mode. - - (+) Entry: - The Stop 2 mode is entered by using the HAL_PWREx_EnterSTOP2Mode() - function. - - (++) PWR_STOPENTRY_WFI: enter Stop 2 mode with WFI instruction. - (++) PWR_STOPENTRY_WFE: enter Stop 2 mode with WFE instruction. - - (+) Exit: - Any EXTI line configured in interrupt mode (the corresponding EXTI - interrupt vector must be enabled in the NVIC). The interrupt source - can be external interrupts or peripherals with wakeup capability. - Any peripheral interrupt occurring when the AHB/APB clocks are present - due to an autonomous peripheral clock request (the peripheral vector - must be enabled in the NVIC) - Any EXTI line configured in event mode. - - *** Stop 3 mode *** - =================== - [..] - The Stop 3 mode is based on the Cortex-M33 Deepsleep mode combined with - peripheral clock gating. In Stop 3 mode, all clocks in the VCORE domain - are stopped. - The PLL, MSIS, MSIK, HSI16 and HSE oscillators are disabled. - All SRAMs and register contents are preserved, but the SRAMs can be - totally or partially switched off to further reduce consumption. - The BOR is always available in Stop 3 mode. - - (+) Entry: - The Stop 3 mode is entered by using the HAL_PWREx_EnterSTOP3Mode() - function. - - (++) PWR_STOPENTRY_WFI: enter Stop 3 mode with WFI instruction. - (++) PWR_STOPENTRY_WFE: enter Stop 3 mode with WFE instruction. - - (+) Exit: - WKUPx pin edge, RTC or TAMP event, external Reset in NRST pin, IWDG - Reset, BOR reset. - - *** Shutdown mode *** - ==================== - [..] - The lowest power consumption is reached in Shutdown mode. It is based on - the Deepsleep mode with the voltage regulator disabled. The VCORE domain - is consequently powered off. - The PLL, HSI16, MSIS, MSIK and HSE oscillators are also switched off. - The SRAMs and register contents are lost except for registers in the - Backup domain. - The BOR is not available in Shutdown mode. - No power voltage monitoring is possible in this mode, therefore the switch - to Backup domain is not supported. - - (+) Entry: - The Shutdown mode is entered by using the HAL_PWREx_EnterSHUTDOWNMode() - function. - - (+) Exit: - WKUPx pin edge, RTC/TAMP event, external Reset in NRST pin. - -@endverbatim - * @{ - */ - -/** - * @brief Enter the whole system to Stop 1 mode. - * @note Stop 1 offers the largest number of active peripherals and wakeup - * sources, a smaller wakeup time but a higher consumption. - * @note Stop mode achieves the lowest power consumption while retaining - * the content of SRAM and registers. All clocks in the VCORE domain - * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and - * the HSE crystal oscillators are disabled. The LSE or LSI is still - * running. - * @note The system clock when exiting from Stop mode can be either MSIS up - * to 24 MHz or HSI16, depending on software configuration. - * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE - * instruction. - * This parameter can be one of the following values : - * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait - * For Interrupt request. - * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait - * For Event request. - * @retval None. - */ -void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Stop 1 mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_0); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry */ - if (STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enter the whole system to Stop 2 mode. - * @note In Stop 2 mode, all clocks in the VCORE domain are stopped. The PLL, - * MSIS, MSIK, HSI16 and HSE oscillators are disabled. - * @note Stop mode achieves the lowest power consumption while retaining - * the content of SRAM and registers. All clocks in the VCORE domain - * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and - * the HSE crystal oscillators are disabled. The LSE or LSI is still - * running. - * @note The system clock when exiting from Stop mode can be either MSIS up - * to 24 MHz or HSI16, depending on software configuration. - * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE - * instruction. - * This parameter can be one of the following values : - * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait - * For Interrupt request. - * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait - * For Event request. - * @retval None. - */ -void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) -{ - /* Check the parameters */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Stop 2 mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_1); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry */ - if (STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enter the whole system to Stop 3 mode. - * @note Stop 3 is the lowest power mode with full retention, but the - * functional peripherals and sources of wakeup are reduced to the same - * ones than in Standby mode. - * @note Stop mode achieves the lowest power consumption while retaining - * the content of SRAM and registers. All clocks in the VCORE domain - * are stopped. The PLL, the MSI (MSIS and MSIK) RC, the HSI16 RC and - * the HSE crystal oscillators are disabled. The LSE or LSI is still - * running. - * @note The system clock when exiting from Stop mode can be either MSIS up - * to 24 MHz or HSI16, depending on software configuration. - * @param STOPEntry : Specifies if Stop mode is entered with WFI or WFE - * instruction. - * This parameter can be one of the following values : - * @arg @ref PWR_STOPENTRY_WFI enter Stop mode with Wait - * For Interrupt request. - * @arg @ref PWR_STOPENTRY_WFE enter Stop mode with Wait - * For Event request. - * @retval None. - */ -void HAL_PWREx_EnterSTOP3Mode(uint8_t STOPEntry) -{ - /* Check the parameter */ - assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); - - /* Set Stop mode 3 */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1)); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* Select Stop mode entry */ - if (STOPEntry == PWR_STOPENTRY_WFI) - { - /* Request Wait For Interrupt */ - __WFI(); - } - else - { - /* Request Wait For Event */ - __SEV(); - __WFE(); - __WFE(); - } - - /* Reset SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Enter the whole system to Shutdown mode. - * @note Shutdown mode allows the lowest power consumption. The internal - * regulator is switched off so that the VCORE domain is powered off. - * The PLL, the HSI16, the MSI (MSIS and MSIK), the LSI and the HSE - * oscillators are also switched off. - * @note The SRAMs and register contents are lost except for registers in the - * Backup domain. The BOR is not available in Shutdown mode. No power - * voltage monitoring is possible in this mode, therefore the switch to - * Backup domain is not supported. - * @retval None. - */ -void HAL_PWREx_EnterSHUTDOWNMode(void) -{ - /* Set Shutdown mode */ - MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, (PWR_CR1_LPMS_1 | PWR_CR1_LPMS_2)); - - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); - - /* This option is used to ensure that store operations are completed */ -#if defined (__CC_ARM) - __force_stores(); -#endif /* (__CC_ARM)*/ - /* Request Wait For Interrupt */ - __WFI(); -} - -/** - * @brief Configure the SRD domain when the System in Stop 0/1/2 mode. - * @param SRDState : Specifies the SRD state. - * This parameter can be one of the following values : - * @arg PWR_SRD_DOMAIN_STOP : SRD in Stop mode when system - * goes to Stop 0/1/2 mode - * @arg PWR_SRD_DOMAIN_RUN : SRD in Run mode when system - * goes to Stop 0/1/2 mode - * @retval None. - */ -void HAL_PWREx_ConfigSRDDomain(uint32_t SRDState) -{ - /* Check the parameter */ - assert_param(IS_PWR_SRD_STATE(SRDState)); - - /* Config the SRD domain */ - MODIFY_REG(PWR->CR2, PWR_CR2_SRDRUN, SRDState); -} - -/** - * @brief Enable BOR ultra-low power mode. - * @note BOR operating can be in discontinuous (ultra-low power) mode in - * Stop 1, Stop 2, Stop 3 and Standby modes and when the regulator is - * in Range 4 (Run, Sleep or Stop 0 mode). - * @retval None. - */ -void HAL_PWREx_EnableUltraLowPowerMode(void) -{ - SET_BIT(PWR->CR1, PWR_CR1_ULPMEN); -} - -/** - * @brief Disable BOR ultra-low power mode. - * @retval None. - */ -void HAL_PWREx_DisableUltraLowPowerMode(void) -{ - CLEAR_BIT(PWR->CR1, PWR_CR1_ULPMEN); -} - -/** - * @brief This function handles the PWR Wake up from Stop 3 interrupt request. - * @note This API should be called under the PWR_S3WU_IRQHandler(). - * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled. - * This parameter can be a combination of @ref PWR_WakeUp_Pins. - * @retval None. - */ -void HAL_PWREx_S3WU_IRQHandler(uint32_t WakeUpPin) -{ - /* Check PWR wake up line 1 */ - if ((WakeUpPin & PWR_WAKEUP_PIN1) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF1) != 0U) - { - /* Clear PWR wake up flag line 1 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF1); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 2 */ - if ((WakeUpPin & PWR_WAKEUP_PIN2) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF2) != 0U) - { - /* Clear PWR wake up flag line 2 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF2); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 3 */ - if ((WakeUpPin & PWR_WAKEUP_PIN3) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF3) != 0U) - { - /* Clear PWR wake up flag line 3 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF3); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 4 */ - if ((WakeUpPin & PWR_WAKEUP_PIN4) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF4) != 0U) - { - /* Clear PWR wake up flag line 4 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF4); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 5 */ - if ((WakeUpPin & PWR_WAKEUP_PIN5) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF5) != 0U) - { - /* Clear PWR wake up flag line 5 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF5); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 6 */ - if ((WakeUpPin & PWR_WAKEUP_PIN6) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF6) != 0U) - { - /* Clear PWR wake up flag line 6 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF6); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 7 */ - if ((WakeUpPin & PWR_WAKEUP_PIN7) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF7) != 0U) - { - /* Clear PWR wake up flag line 7 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF7); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } - - /* Check PWR wake up line 8 */ - if ((WakeUpPin & PWR_WAKEUP_PIN8) != 0U) - { - if (READ_BIT(PWR->WUSR, PWR_WUSR_WUF8) != 0U) - { - /* Clear PWR wake up flag line 8 */ - SET_BIT(PWR->WUSCR, PWR_WUSCR_CWUF8); - - /* PWR S3WU interrupt user callback */ - HAL_PWREx_S3WUCallback(WakeUpPin); - } - } -} - -/** - * @brief PWR S3WU interrupt callback. - * @param WakeUpPin : Specifies the wakeup pin interrupt to be handled. - * This parameter can be a combination of @ref PWR_WakeUp_Pins. - * @retval None. - */ -__weak void HAL_PWREx_S3WUCallback(uint32_t WakeUpPin) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(WakeUpPin); - - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_S3WU_IRQHandler() API can be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup PWREx_Exported_Functions_Group3 Voltage Monitoring Functions - * @brief Voltage monitoring functions - * -@verbatim - =============================================================================== - ##### Voltage Monitoring Functions ##### - =============================================================================== - [..] - This section provides functions allowing voltage monitoring. - - *** PVM configuration *** - ========================= - [..] - (+) The supplies (VDDA, VDDIO2 and VDDUSB) can be independent from VDD and - can be monitored with four peripheral voltage monitoring (PVM): - - (++) The UVM monitors the USB supply VDDUSB. VDDUSBRDY indicates if - the VDDUSB independent power supply is higher or lower than the - VUVM threshold. - (++) The IO2VM monitors the PG[15:2] supply VDDIO2. VDDIO2RDY - indicates if the VDDIO2 independent power supply is higher or - lower than the VIO2VM threshold. - (++) The AVM1 monitors the analog supply VDDA. VDDA1RDY indicates if - the VDDA independent power supply is higher or lower than the - VAVM1 threshold. - (++) The AVM2 monitors the analog supply VDDA. VDDA2RDY indicates if - the VDDA independent power supply is higher or lower than the - VAVM2 threshold. - - (+) Each PVM output is connected to an EXTI line and can generate an - interrupt if enabled through the EXTI registers. The PVMx output - interrupt is generated when the independent power supply drops below - the PVM threshold and/or when it rises above the PVM threshold, - depending on EXTI line rising/falling edge configuration. - - (+) Each PVM can remain active in Stop 0, Stop 1, Stop 2 modes, and the - PVM interrupt can wake up from the Stop mode. The PVM is not - functional in Stop 3 mode. - - *** VBAT charging *** - ===================== - [..] - When VDD is present, it is possible to charge the external battery on VBAT - through an internal resistance. - The VBAT charging is done either through a 5 kOhm resistor or through a 1.5 - kOhm resistor depending on the VBRS bit value in the PWR_BDCR2 register. - The battery charging is enabled by setting VBE bit in the PWR_BDCR2 - register. It is automatically disabled in VBAT mode. - - *** Backup domain monitoring *** - ================================ - [..] - When the Backup domain voltage and temperature monitoring is enabled - (MONEN = 1 in the PWR_BDCR1 register), the Backup domain voltage and the - temperature are monitored. - If the Backup domain voltage monitoring internal tamper is enabled in the - TAMP peripheral (ITAMP1E = 1 in the TAMP_CR1 register), a tamper event is - generated when the Backup domain voltage is above the functional range. - In case the Backup domain voltage is below the functional range, - a Brownout reset is generated, erasing all device including Backup domain. - - *** Backup domain battery *** - ============================= - [..] - (+) To retain the content of the backup registers and supply the RTC - function when VDD is turned off, the VBAT pin can be connected to an - optional backup voltage supplied by a battery or by another source. - The VBAT pin powers the RTC unit, the LSE oscillator and the PC13 to - PC15 I/Os, allowing the RTC to operate even when the main power supply - is turned off. The backup SRAM is optionally powered by VBAT pin when - the BREN bit is set in the PWR Backup domain control register 1 - (PWR_BDCR1). - The switch to the VBAT supply is controlled by the power down reset - embedded in the Reset block. - - (+) After exiting reset, the USB Type-C (dead battery) behavior is enabled, - which may have a pull-down effect on CC1 and CC2 pins. It is - recommended to disable it in all cases, either to stop this pull-down - or to handover control to the UCPD (the UCPD must be initialized - before doing the disable). - -@endverbatim - * @{ - */ - -/** - * @brief Configure the voltage monitor threshold detected by the Peripheral - * voltage monitoring (PVM). - * @param pConfigPVM : Pointer to a PWR_PVMTypeDef structure that contains the - * PVM configuration information (PVMType and EventMode). - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *pConfigPVM) -{ - /* Check the PVM parameter */ - if (pConfigPVM == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_PWR_PVM_TYPE(pConfigPVM->PVMType)); - assert_param(IS_PWR_PVM_MODE(pConfigPVM->Mode)); - - /* Check the peripheral voltage monitor type */ - switch (pConfigPVM->PVMType) - { - case PWR_UVM: /* Independent USB voltage monitor */ - - /* Disable EXTI UVM event and interrupt */ - __HAL_PWR_UVM_EXTI_DISABLE_EVENT(); - __HAL_PWR_UVM_EXTI_DISABLE_IT(); - __HAL_PWR_UVM_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_UVM_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure the UVM in interrupt mode */ - if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_UVM_EXTI_ENABLE_IT(); - } - - /* Configure the UVM in event mode */ - if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_UVM_EXTI_ENABLE_EVENT(); - } - - /* Configure the UVM in rising edge */ - if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_UVM_EXTI_ENABLE_RISING_EDGE(); - } - - /* Configure the UVM in falling edge */ - if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_UVM_EXTI_ENABLE_FALLING_EDGE(); - } - - break; - - case PWR_IO2VM: /* Independent I/Os voltage monitor */ - - /* Disable EXTI IO2VM event and interrupt */ - __HAL_PWR_IO2VM_EXTI_DISABLE_EVENT(); - __HAL_PWR_IO2VM_EXTI_DISABLE_IT(); - __HAL_PWR_IO2VM_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_IO2VM_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure the IO2VM in interrupt mode */ - if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_IO2VM_EXTI_ENABLE_IT(); - } - - /* Configure the IO2VM in event mode */ - if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_IO2VM_EXTI_ENABLE_EVENT(); - } - - /* Configure the IO2VM in rising edge */ - if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_IO2VM_EXTI_ENABLE_RISING_EDGE(); - } - - /* Configure the IO2VM in falling edge */ - if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_IO2VM_EXTI_ENABLE_FALLING_EDGE(); - } - - break; - - case PWR_AVM1: /* VDDA Independent analog supply voltage monitor 1 (1.6V threshold) */ - - /* Disable EXTI AVM1 event and interrupt */ - __HAL_PWR_AVM1_EXTI_DISABLE_EVENT(); - __HAL_PWR_AVM1_EXTI_DISABLE_IT(); - __HAL_PWR_AVM1_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_AVM1_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure the AVM1 in interrupt mode */ - if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_AVM1_EXTI_ENABLE_IT(); - } - - /* Configure the AVM1 in event mode */ - if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_AVM1_EXTI_ENABLE_EVENT(); - } - - /* Configure the AVM1 in rising edge */ - if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_AVM1_EXTI_ENABLE_RISING_EDGE(); - } - - /* Configure the AVM1 in falling edge */ - if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_AVM1_EXTI_ENABLE_FALLING_EDGE(); - } - - break; - - case PWR_AVM2: /* VDDA Independent analog supply voltage monitor 2 (1.8V threshold) */ - - /* Disable EXTI AVM2 event and interrupt */ - __HAL_PWR_AVM2_EXTI_DISABLE_EVENT(); - __HAL_PWR_AVM2_EXTI_DISABLE_IT(); - __HAL_PWR_AVM2_EXTI_DISABLE_RISING_EDGE(); - __HAL_PWR_AVM2_EXTI_DISABLE_FALLING_EDGE(); - - /* Configure the AVM2 in interrupt mode */ - if ((pConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) - { - __HAL_PWR_AVM2_EXTI_ENABLE_IT(); - } - - /* Configure the AVM2 in event mode */ - if ((pConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) - { - __HAL_PWR_AVM2_EXTI_ENABLE_EVENT(); - } - - /* Configure the AVM2 in rising edge */ - if ((pConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) - { - __HAL_PWR_AVM2_EXTI_ENABLE_RISING_EDGE(); - } - - /* Configure the AVM2 in falling edge */ - if ((pConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) - { - __HAL_PWR_AVM2_EXTI_ENABLE_FALLING_EDGE(); - } - - break; - - default: /* No valid voltage monitor selected */ - return HAL_ERROR; - break; - } - - return HAL_OK; -} - -/** - * @brief Enable VDDUSB supply. - * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply - * is present for consumption saving. - * @retval None. - */ -void HAL_PWREx_EnableVddUSB(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_USV); -} - -/** - * @brief Disable VDDUSB supply. - * @retval None. - */ -void HAL_PWREx_DisableVddUSB(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_USV); -} - -/** - * @brief Enable VDDIO2 supply. - * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply - * is present for consumption saving. - * @retval None. - */ -void HAL_PWREx_EnableVddIO2(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); -} - -/** - * @brief Disable VDDIO2 supply. - * @retval None. - */ -void HAL_PWREx_DisableVddIO2(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2SV); -} - -/** - * @brief Enable VDDA supply. - * @note Remove VDDA electrical and logical isolation, once VDDA supply is - * present for consumption saving. - * @retval None. - */ -void HAL_PWREx_EnableVddA(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_ASV); -} - -/** - * @brief Disable VDDA supply. - * @retval None. - */ -void HAL_PWREx_DisableVddA(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_ASV); -} - -/** - * @brief Enable the UVM Voltage Monitoring : VDDUSB versus 1.2 V. - * @retval None. - */ -void HAL_PWREx_EnableUVM(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); -} - -/** - * @brief Disable the UVM Voltage Monitoring : VDDUSB versus 1.2 V. - * @retval None. - */ -void HAL_PWREx_DisableUVM(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_UVMEN); -} - -/** - * @brief Enable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V. - * @retval None. - */ -void HAL_PWREx_EnableIO2VM(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); -} - -/** - * @brief Disable the IO2VM Voltage Monitoring : VDDIO2 versus 0.9 V. - * @retval None. - */ -void HAL_PWREx_DisableIO2VM(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_IO2VMEN); -} - -/** - * @brief Enable the AVM1 Voltage Monitoring : VDDA versus 1.6 V. - * @retval None. - */ -void HAL_PWREx_EnableAVM1(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); -} - -/** - * @brief Disable the AVM1 Voltage Monitoring : VDDA versus 1.6 V. - * @retval None. - */ -void HAL_PWREx_DisableAVM1(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM1EN); -} - -/** - * @brief Enable the AVM2 Voltage Monitoring : VDDA versus 1.8 V. - * @retval None. - */ -void HAL_PWREx_EnableAVM2(void) -{ - SET_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); -} - -/** - * @brief Disable the AVM2 Voltage Monitoring : VDDA versus 1.8 V. - * @retval None. - */ -void HAL_PWREx_DisableAVM2(void) -{ - CLEAR_BIT(PWR->SVMCR, PWR_SVMCR_AVM2EN); -} - -/** - * @brief Enable the VBAT and temperature monitoring. - * @retval None. - */ -void HAL_PWREx_EnableMonitoring(void) -{ - SET_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); -} - -/** - * @brief Disable the VBAT and temperature monitoring. - * @retval None. - */ -void HAL_PWREx_DisableMonitoring(void) -{ - CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_MONEN); -} - -#if defined (PWR_VOSR_USBPWREN) -/** - * @brief Enable the internal USB HS transceiver supply. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_PWREx_EnableUSBHSTranceiverSupply(void) -{ - uint32_t vos; - - /* Get the system applied voltage scaling range */ - vos = HAL_PWREx_GetVoltageRange(); - - /* Check the system applied voltage scaling range */ - if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2)) - { - SET_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disable the internal USB HS transceiver supply. - * @retval HAL status. - */ -void HAL_PWREx_DisableUSBHSTranceiverSupply(void) -{ - CLEAR_BIT(PWR->VOSR, (PWR_VOSR_USBPWREN | PWR_VOSR_USBBOOSTEN)); -} -#endif /* defined (PWR_VOSR_USBPWREN) */ - -#if defined (PWR_CR1_FORCE_USBPWR) -/** - * @brief Enable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). - * @retval None. - */ -void HAL_PWREx_EnableOTGHSPHYLowPowerRetention(void) -{ - /* Set FORCE_USBPWR bit */ - SET_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); -} - -/** - * @brief Disable OTG_HS PHY power during low power modes (Stop2, Stop3 and Standby). - * @retval None. - */ -void HAL_PWREx_DisableOTGHSPHYLowPowerRetention(void) -{ - /* Clear FORCE_USBPWR bit */ - CLEAR_BIT(PWR->CR1, PWR_CR1_FORCE_USBPWR); -} -#endif /* defined (PWR_CR1_FORCE_USBPWR) */ - -#if defined (PWR_VOSR_VDD11USBDIS) -/** - * @brief Enable the VDD11USB. - * @retval None. - */ -void HAL_PWREx_EnableVDD11USB(void) -{ - /* Clear VDD11USBDIS bit */ - CLEAR_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); -} - -/** - * @brief Disable the VDD11USB. - * @retval None. - */ -void HAL_PWREx_DisableVDD11USB(void) -{ - /* Set VDD11USBDIS bit */ - SET_BIT(PWR->VOSR, PWR_VOSR_VDD11USBDIS); -} -#endif /* defined (PWR_VOSR_VDD11USBDIS) */ - -#ifdef UCPD1 -/** - * @brief Enable UCPD configuration memorization in Standby mode. - * @retval None. - */ -void HAL_PWREx_EnableUCPDStandbyMode(void) -{ - SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); -} - -/** - * @brief Disable UCPD configuration memorization in Standby mode. - * @note This function must be called on exiting the Standby mode and before - * any UCPD configuration update. - * @retval None. - */ -void HAL_PWREx_DisableUCPDStandbyMode(void) -{ - CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_STDBY); -} - -/** - * @brief Enable dead battery behavior. - * @note After exiting reset, the USB Type-C (dead battery) behavior is - * enabled, which may have a pull-down effect on CC1 and CC2 pins. - * It is recommended to disable it in all cases, either to stop this - * pull-down or to handover control to the UCPD (the UCPD must be - * initialized before doing the disable). - * @retval None. - */ -void HAL_PWREx_EnableUCPDDeadBattery(void) -{ - CLEAR_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); -} - -/** - * @brief Disable dead battery behavior. - * @note After exiting reset, the USB Type-C (dead battery) behavior is - * enabled, which may have a pull-down effect on CC1 and CC2 pins. - * It is recommended to disable it in all cases, either to stop this - * pull-down or to handover control to the UCPD (the UCPD must be - * initialized before doing the disable). - * @retval None. - */ -void HAL_PWREx_DisableUCPDDeadBattery(void) -{ - SET_BIT(PWR->UCPDR, PWR_UCPDR_UCPD_DBDIS); -} -#endif /* UCPD1 */ - -/** - * @brief Enable the Battery charging. - * @note When VDD is present, charge the external battery through an internal - * resistor. - * @param ResistorValue : Specifies the charging resistor. - * This parameter can be one of the following values : - * @arg PWR_BATTERY_CHARGING_RESISTOR_5 : 5 KOhm resistor. - * @arg PWR_BATTERY_CHARGING_RESISTOR_1_5 : 1.5 KOhm resistor. - * @retval None. - */ -void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorValue) -{ - /* Check the parameter */ - assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorValue)); - - /* Specify the charging resistor */ - MODIFY_REG(PWR->BDCR2, PWR_BDCR2_VBRS, ResistorValue); - - /* Enable the Battery charging */ - SET_BIT(PWR->BDCR2, PWR_BDCR2_VBE); -} - -/** - * @brief Disable the Battery charging. - * @retval None. - */ -void HAL_PWREx_DisableBatteryCharging(void) -{ - CLEAR_BIT(PWR->BDCR2, PWR_BDCR2_VBE); -} - -/** - * @brief This function handles the PWR PVD/PVM interrupt request. - * @note This API should be called under the PVD_PVM_IRQHandler(). - * @retval None. - */ -void HAL_PWREx_PVD_PVM_IRQHandler(void) -{ - uint32_t rising_flag; - uint32_t falling_flag; - - /* Get pending flags */ - rising_flag = READ_REG(EXTI->RPR1); - falling_flag = READ_REG(EXTI->FPR1); - - /* Check PWR exti flags for PVD */ - if (((rising_flag | falling_flag) & PWR_EXTI_LINE_PVD) != 0U) - { - /* PWR PVD interrupt user callback */ - HAL_PWR_PVDCallback(); - - /* Clear PVD exti pending bit */ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_PVD); - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_PVD); - } - - /* Check PWR exti flags for UVM */ - if (((rising_flag | falling_flag) & PWR_EXTI_LINE_UVM) != 0U) - { - /* PWR UVM interrupt user callback */ - HAL_PWREx_UVMCallback(); - - /* Clear UVM exti pending bit */ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_UVM); - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_UVM); - } - - /* Check PWR exti flags for IO2VM */ - if (((rising_flag | falling_flag) & PWR_EXTI_LINE_IO2VM) != 0U) - { - /* PWR IO2VM interrupt user callback */ - HAL_PWREx_IO2VMCallback(); - - /* Clear IO2VM exti pending bit */ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_IO2VM); - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_IO2VM); - } - - /* Check PWR exti flags for AVM1 */ - if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM1) != 0U) - { - /* PWR AVM1 interrupt user callback */ - HAL_PWREx_AVM1Callback(); - - /* Clear AVM1 exti pending bit */ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM1); - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM1); - } - - /* Check PWR exti flags for AVM2 */ - if (((rising_flag | falling_flag) & PWR_EXTI_LINE_AVM2) != 0U) - { - /* PWR AVM2 interrupt user callback */ - HAL_PWREx_AVM2Callback(); - - /* Clear AVM2 exti pending bit */ - WRITE_REG(EXTI->RPR1, PWR_EXTI_LINE_AVM2); - WRITE_REG(EXTI->FPR1, PWR_EXTI_LINE_AVM2); - } -} - -/** - * @brief PWR UVM interrupt callback. - * @retval None. - */ -__weak void HAL_PWREx_UVMCallback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_UVMCallback() API can be implemented in the user file - */ -} - -/** - * @brief PWR IO2VM interrupt callback. - * @retval None. - */ -__weak void HAL_PWREx_IO2VMCallback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_IO2VMCallback() API can be implemented in the user file - */ -} - -/** - * @brief PWR AVM1 interrupt callback. - * @retval None. - */ -__weak void HAL_PWREx_AVM1Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_AVM1Callback() API can be implemented in the user file - */ -} - -/** - * @brief PWR AVM2 interrupt callback. - * @retval None. - */ -__weak void HAL_PWREx_AVM2Callback(void) -{ - /* NOTE : This function should not be modified; when the callback is needed, - HAL_PWREx_AVM2Callback() API can be implemented in the user file - */ -} -/** - * @} - */ - -/** @defgroup PWREx_Exported_Functions_Group4 Memories Retention Functions - * @brief Memories retention functions - * -@verbatim - =============================================================================== - ##### Memories Retention Functions ##### - =============================================================================== - [..] - Several STM32U5 devices RAMs are configurable to keep / lose RAMs content - during Stop mode (Stop 0/1/2/3). - (+) Retained content RAMs in Stop modes are : - (++) SRAM1 - (++) SRAM2 - (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, - STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) - (++) SRAM4 - (++) ICACHE - (++) DMA2DRAM (available only for STM32U575xx, STM32U585xx, STM32U59xxx, - STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) - (++) PKA32RAM - (++) DCACHE - (++) FMAC - (++) FDCAN - (++) USB - - [..] - Several STM32U5 devices RAMs are configurable to keep / lose RAMs content - during Run mode. - (+) Retained content RAMs in Run modes are : - (++) SRAM1 - (++) SRAM2 - (++) SRAM3 (available only for STM32U575xx, STM32U585xx, STM32U59xxx, - STM32U5Axxx, STM32U5Fxxx and STM32U5Gxxx devices) - (++) SRAM4 - - [..] - SRAM2 is configurable to keep / lose its content in Stop 3 and Standby - modes. The SRAM2 retention feature granularity is at pages level. - - [..] - BKPRAM is configurable to keep / lose its content in Standby, Shutdown and - VBAT modes. - -@endverbatim - * @{ - */ - -/** - * @brief Enable SRAM2 page(s) content retention in Stop 3 and Standby mode. - * @note When RRSx bit is set, SRAM2 is powered by the low-power regulator in - * Stop 3 and Standby mode and its content is kept. - * @param SRAM2Pages : Specifies the SRAM2 pages. - * This parameter can be one of the following values : - * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. - * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. - * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. - * @retval None. - */ -void HAL_PWREx_EnableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) -{ - /* Check the parameters */ - assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages)); - - /* Set RRSx bit(s) */ - SET_BIT(PWR->CR1, SRAM2Pages); -} - -/** - * @brief Disable SRAM2 page(s) content retention in Stop 3 and Standby mode. - * @note When RRSx bit is reset, SRAM2 is powered off in Stop 3 and Standby - * mode and its content is lost. - * @param SRAM2Pages : Specifies the SRAM2 pages. - * This parameter can be one of the following values : - * @arg PWR_SRAM2_PAGE1_STANDBY : SRAM2 page 1 retention. - * @arg PWR_SRAM2_PAGE2_STANDBY : SRAM2 page 2 retention. - * @arg PWR_SRAM2_FULL_STANDBY : SRAM2 page 1 and page 2 retention. - * @retval None. - */ -void HAL_PWREx_DisableSRAM2ContentStandbyRetention(uint32_t SRAM2Pages) -{ - /* Check the parameters */ - assert_param(IS_PWR_SRAM2_STANDBY_RETENTION(SRAM2Pages)); - - /* Clear RRSx bit(s) */ - CLEAR_BIT(PWR->CR1, SRAM2Pages); -} - -/** - * @brief Enable RAM page(s) content retention in Stop mode (Stop 0, 1, 2, 3). - * @note When enabling content retention for a given RAM, memory kept powered - * in Stop mode. (Not optimized power consumption) - * @param RAMSelection: Specifies RAM page(s) to be retained in Stop mode. - * This parameter can be one or a combination of the same - * memory @ref PWREx_RAM_Contents_Stop_Retention. - * @retval None. - */ -void HAL_PWREx_EnableRAMsContentStopRetention(uint32_t RAMSelection) -{ - uint32_t dummy; - - /* Check RAM ID */ - switch (RAMSelection & SRAM_ID_MASK) - { - /* SRAM 1 Stop retention */ - case SRAM1_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); - CLEAR_BIT(PWR->CR2, dummy); - -#if defined (PWR_CR4_SRAM1PDS4) - /* Calculate pages mask */ - dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; - CLEAR_BIT(PWR->CR4, dummy); -#endif /* defined (PWR_CR4_SRAM1PDS4) */ - - break; - } - - /* SRAM 2 Stop retention */ - case SRAM2_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); - - break; - } - -#if defined (PWR_CR2_SRAM3PDS1) - /* SRAM 3 Stop retention */ - case SRAM3_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | - PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); - -#if defined (PWR_CR4_SRAM3PDS9) - /* Calculate pages mask */ - dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | - PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; - CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); -#endif /* defined (PWR_CR4_SRAM3PDS9) */ - - break; - } -#endif /* PWR_CR2_SRAM3PDS1 */ - - /* SRAM 4 Stop retention */ - case SRAM4_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); - - break; - } - - /* ICACHE RAM Stop retention */ - case ICACHERAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_ICRAMPDS_Pos); - - break; - } - - /* DCACHE1 RAM Stop retention */ - case DCACHE1RAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, dummy << PWR_CR2_DC1RAMPDS_Pos); - - break; - } - -#if defined (PWR_CR2_DMA2DRAMPDS) - /* DMA2D RAM Stop retention */ - case DMA2DRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); - - break; - } -#endif /* PWR_CR2_DMA2DRAMPDS */ - - /* FMAC, FDCAN and USB RAM Stop retention */ - case PERIPHRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); - - break; - } - -#if defined (PWR_CR2_PKARAMPDS) - /* PKA32 RAM Stop retention */ - case PKARAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); - - break; - } -#endif /* PWR_CR2_PKARAMPDS */ - -#if defined (PWR_CR2_DC2RAMPDS) - /* DCACHE2 RAM Stop retention */ - case DCACHE2RAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_DC2RAMPDS) */ - -#if defined (PWR_CR2_GPRAMPDS) - /* LTDC and GFXMMU RAM Stop retention */ - case GRAPHIPRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_GPRAMPDS) */ - -#if defined (PWR_CR2_DSIRAMPDS) - /* DSI RAM Stop retention */ - case DSIRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_DSIRAMPDS) */ - -#if defined (PWR_CR2_JPEGRAMPDS) - /* JPEG RAM Stop retention */ - case JPEGRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; - CLEAR_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_JPEGRAMPDS) */ - -#if defined (PWR_CR4_SRAM5PDS1) - /* SRAM 5 Stop retention */ - case SRAM5_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); - CLEAR_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); - - break; - } -#endif /* defined (PWR_CR4_SRAM5PDS1) */ - -#if defined (PWR_CR5_SRAM6PDS1) - /* SRAM 6 Stop retention */ - case SRAM6_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); - CLEAR_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); - - break; - } -#endif /* defined (PWR_CR5_SRAM6PDS1) */ - - default: - { - return; - break; - } - } -} - -/** - * @brief Disable RAM page(s) content lost in Stop mode (Stop 0, 1, 2, 3). - * @note When disabling content lost for a given RAM, memory powered down - * in Stop mode. (Optimized power consumption) - * @param RAMSelection: Specifies RAM page(s) to be lost in Stop mode. - * This parameter can be one or a combination of the same - * memory @ref PWREx_RAM_Contents_Stop_Retention. - * @retval None. - */ -void HAL_PWREx_DisableRAMsContentStopRetention(uint32_t RAMSelection) -{ - uint32_t dummy; - - /* Check RAM ID */ - switch (RAMSelection & SRAM_ID_MASK) - { - /* SRAM 1 Stop retention */ - case SRAM1_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM1_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID); - SET_BIT(PWR->CR2, dummy); -#if defined (PWR_CR4_SRAM1PDS4) - /* Calculate pages mask */ - dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID)) >> 0x03U; - SET_BIT(PWR->CR4, dummy); -#endif /* defined (PWR_CR4_SRAM1PDS4) */ - - break; - } - - /* SRAM 2 Stop retention */ - case SRAM2_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM2_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM2_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM2PDS1_Pos)); - - break; - } - -#if defined (PWR_CR2_SRAM3PDS1) - /* SRAM 3 Stop retention */ - case SRAM3_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM3_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & ~SRAM_ID_MASK) & (PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | - PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID); - SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM3PDS1_Pos)); - -#if defined (PWR_CR4_SRAM3PDS9) - /* Calculate pages mask */ - dummy = ((RAMSelection & ~SRAM_ID_MASK) & ~(PAGE01_ID | PAGE02_ID | PAGE03_ID | PAGE04_ID | - PAGE05_ID | PAGE06_ID | PAGE07_ID | PAGE08_ID)) >> 0x08U; - SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM3PDS9_Pos)); -#endif /* defined (PWR_CR4_SRAM3PDS9) */ - - break; - } -#endif /* PWR_CR2_SRAM3PDS1 */ - - /* SRAM 4 Stop retention */ - case SRAM4_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM4_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_SRAM4_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_SRAM4PDS_Pos)); - - break; - } - - /* ICACHE RAM Stop retention */ - case ICACHERAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_ICACHE_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_ICACHE_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_ICRAMPDS_Pos)); - - break; - } - - /* DCACHE1 RAM Stop retention */ - case DCACHE1RAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DCACHE1_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE1_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC1RAMPDS_Pos)); - - break; - } - -#if defined (PWR_CR2_DMA2DRAMPDS) - /* DMA2D RAM Stop retention */ - case DMA2DRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DMA2DRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DMA2DRAM_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_DMA2DRAMPDS_Pos)); - - break; - } -#endif /* PWR_CR2_DMA2DRAMPDS */ - - /* FMAC, FDCAN and USB RAM Stop retention */ - case PERIPHRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_PERIPHRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PERIPHRAM_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_PRAMPDS_Pos)); - - break; - } - -#if defined (PWR_CR2_PKARAMPDS) - /* PKA32 RAM Stop retention */ - case PKARAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_PKA32RAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_PKA32RAM_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_PKARAMPDS_Pos)); - - break; - } -#endif /* PWR_CR2_PKARAMPDS */ - -#if defined (PWR_CR2_DC2RAMPDS) - /* DCACHE2 RAM Stop retention */ - case DCACHE2RAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DCACHE2_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DCACHE2_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_DC2RAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_DC2RAMPDS) */ - -#if defined (PWR_CR2_GPRAMPDS) - /* LTDC and GFXMMU RAM Stop retention */ - case GRAPHIPRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_GRAPHICPRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_GRAPHICPRAM_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_GPRAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_GPRAMPDS) */ - -#if defined (PWR_CR2_DSIRAMPDS) - /* DSI RAM Stop retention */ - case DSIRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_DSIRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_DSIRAM_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_DSIRAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_DSIRAMPDS) */ - -#if defined (PWR_CR2_JPEGRAMPDS) - /* JPEG RAM Stop retention */ - case JPEGRAM_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_JPEGRAM_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = (RAMSelection & PWR_JPEGRAM_FULL_STOP) & ~SRAM_ID_MASK; - SET_BIT(PWR->CR2, (dummy << PWR_CR2_JPEGRAMPDS_Pos)); - - break; - } -#endif /* defined (PWR_CR2_JPEGRAMPDS) */ - -#if defined (PWR_CR4_SRAM5PDS1) - /* SRAM 5 Stop retention */ - case SRAM5_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM5_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = ((RAMSelection & PWR_SRAM5_FULL_STOP) & ~SRAM_ID_MASK); - SET_BIT(PWR->CR4, (dummy << PWR_CR4_SRAM5PDS1_Pos)); - - break; - } -#endif /* defined (PWR_CR4_SRAM5PDS1) */ - -#if defined (PWR_CR5_SRAM6PDS1) - /* SRAM 6 Stop retention */ - case SRAM6_ID: - { - /* Check the parameters */ - assert_param(IS_PWR_SRAM6_STOP_RETENTION(RAMSelection)); - - /* Calculate pages mask */ - dummy = ((RAMSelection & PWR_SRAM6_FULL_STOP) & ~SRAM_ID_MASK); - SET_BIT(PWR->CR5, (dummy << PWR_CR5_SRAM6PDS1_Pos)); - - break; - } -#endif /* defined (PWR_CR5_SRAM6PDS1) */ - - default: - { - return; - break; - } - } -} - -/** - * @brief Enable RAMs full content retention in Run mode. - * @param RAMSelection : Specifies the SRAM content to be retained in Run mode. - * This parameter can be one or a combination of the following values : - * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content retention. - * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content retention. - * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content retention (available only for STM32U575xx, - * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - and STM32U5Gxxx devices). - * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content retention. - * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for - * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - * and STM32U5Gxxx devices). - * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for - * STM32U5Fxxx and STM32U5Gxxx devices). - * @retval None. - */ -void HAL_PWREx_EnableRAMsContentRunRetention(uint32_t RAMSelection) -{ - /* Check the parameters */ - assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection)); - - /* Enable RAM retention in Run mode */ - CLEAR_BIT(PWR->CR1, RAMSelection); -} - -/** - * @brief Disable RAMs full content retention in Run mode. - * @param RAMSelection : Specifies the SRAM content to be lost in Run mode. - * This parameter can be one or a combination of the following values : - * @arg PWR_SRAM1_FULL_RUN : SRAM1 full content lost. - * @arg PWR_SRAM2_FULL_RUN : SRAM2 full content lost. - * @arg PWR_SRAM3_FULL_RUN : SRAM3 full content lost (available only for STM32U575xx, - * STM32U585xx STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - and STM32U5Gxxx devices). - * @arg PWR_SRAM4_FULL_RUN : SRAM4 full content lost. - * @arg PWR_SRAM5_FULL_RUN : SRAM5 full content retention (available only for - * STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - * and STM32U5Gxxx devices). - * @arg PWR_SRAM6_FULL_RUN : SRAM6 full content retention (available only for - * STM32U5Fxxx and STM32U5Gxxx devices). - * @retval None. - */ -void HAL_PWREx_DisableRAMsContentRunRetention(uint32_t RAMSelection) -{ - /* Check the parameters */ - assert_param(IS_PWR_RAM_RUN_RETENTION(RAMSelection)); - - /* Disable RAM retention in Run mode */ - SET_BIT(PWR->CR1, RAMSelection); -} - -/** - * @brief Enable the Backup RAM retention in Standby, Shutdown and VBAT modes. - * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and - * Stop modes. However, its content is lost in Standby, Shutdown and - * VBAT modes. - * @note This bit can be enabled only when LDO regulator is selected as - * source supply. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_EnableBkupRAMRetention(void) -{ - /* - Backup RAM retention in Standby, Shutdown and VBAT should be enabled - when the Vcore is alimented by the LDO regulator - */ - if (HAL_PWREx_GetSupplyConfig() == PWR_LDO_SUPPLY) - { - SET_BIT(PWR->BDCR1, PWR_BDCR1_BREN); - } - /* SMPS regulator selected */ - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief Disable the Backup RAM retention in Standby, Shutdown and VBAT modes. - * @note If BREN is reset, the backup RAM can still be used in Run, Sleep and - * Stop modes. However, its content is lost in Standby, Shutdown and - * VBAT modes. This bit can be writte - * @retval None. - */ -void HAL_PWREx_DisableBkupRAMRetention(void) -{ - CLEAR_BIT(PWR->BDCR1, PWR_BDCR1_BREN); -} - -/** - * @brief Enable the flash memory fast wakeup from Stop 0 and Stop 1 modes. - * @note This feature is used to obtain the best trade-off between low-power - * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. - * When this feature is enabled, the Flash memory remains in normal - * mode in Stop 0 and Stop 1 modes, which offers a faster startup time - * with higher consumption. - * @retval None. - */ -void HAL_PWREx_EnableFlashFastWakeUp(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_FLASHFWU); -} - -/** - * @brief Disable the Flash Power Down in Stop mode. - * @note This feature is used to obtain the best trade-off between low-power - * consumption and wakeup time when exiting the Stop 0 or Stop 1 modes. - * When this feature is disabled, the Flash memory enters low-power - * mode in Stop 0 and Stop 1 modes, which causes a slower startup time - * with lower consumption. - * @retval None. - */ -void HAL_PWREx_DisableFlashFastWakeUp(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_FLASHFWU); -} - -/** - * @brief Enable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes. - * @note This bit is used to obtain the best trade-off between low-power consumption - * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting - * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time - * to SRAM4 during Stop modes. - * @retval None. - */ -void HAL_PWREx_EnableSRAM4FastWakeUp(void) -{ - SET_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); -} - -/** - * @brief Disable the SRAM4 memory fast wakeup from Stop 0, Stop 1 and Stop 2 modes. - * @note This bit is used to obtain the best trade-off between low-power consumption - * and wakeup time. SRAM4 wakeup time increases the wakeup time when exiting - * Stop 0, Stop 1 and Stop 2 modes, and also increases the LPDMA access time - * to SRAM4 during Stop modes. - * @retval None. - */ -void HAL_PWREx_DisableSRAM4FastWakeUp(void) -{ - CLEAR_BIT(PWR->CR2, PWR_CR2_SRAM4FWU); -} -/** - * @} - */ - -/** @defgroup PWREx_Exported_Functions_Group5 I/O Pull-Up Pull-Down Configuration Functions - * @brief I/O pull-up / pull-down configuration functions - * -@verbatim - =============================================================================== - ##### IO Pull-Up Pull-Down Configuration Functions ##### - =============================================================================== - [..] - In Standby and Shutdown mode, pull up and pull down can be configured to - maintain an I/O in the selected state. If the APC bit in the PWR_APCR - register is set, the I/Os can be configured either with a pull-up through - PWR_PUCRx registers (x=A,B,C,D,E,F,G,H,I,J), or with a pull-down through - PWR_PDCRx registers (x=A,B,C,D,E,F,G,H,I,J)), or can be kept in analog state - if none of the PWR_PUCRx or PWR_PDCRx register is set. - (+) Port J is available only for STM32U59xxx, STM32U5Axxx, STM32U5Fxxx - and STM32U5Gxxx devices. - - [..] - The pull-down configuration has highest priority over pull-up - configuration in case both PWR_PUCRx and PWR_PDCRx are set for the same - I/O. - This configuration is lost when exiting the Shutdown but not from Standby - mode. - -@endverbatim - * @{ - */ - -/** - * @brief Enable pull-up and pull-down configuration. - * @note When APC bit is set, the I/O pull-up and pull-down configurations - * defined in PWR_PUCRx and PWR_PDCRx registers are applied in Standby - * and Shutdown modes. - * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the - * corresponding PDy bit of PWR_PDCRx register is also set (pull-down - * configuration priority is higher). HAL_PWREx_EnableGPIOPullUp() and - * HAL_PWREx_EnableGPIOPullDown() API's ensure there is no conflict - * when setting PUy or PDy bit. - * @retval None. - */ -void HAL_PWREx_EnablePullUpPullDownConfig(void) -{ - SET_BIT(PWR->APCR, PWR_APCR_APC); -} - -/** - * @brief Disable pull-up and pull-down configuration. - * @note When APC bit is cleared, the I/O pull-up and pull-down configurations - * defined in PWR_PUCRx and PWR_PDCRx registers are not applied in - * Standby and Shutdown modes. - * @retval None. - */ -void HAL_PWREx_DisablePullUpPullDownConfig(void) -{ - CLEAR_BIT(PWR->APCR, PWR_APCR_APC); -} - -/** - * @brief Enable GPIO pull-up state in Standby and Shutdown modes. - * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O - * in pull-up state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC - * bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. - * @note To avoid any conflict at Standby and Shutdown modes exits, the - * corresponding PDy bit of PWR_PDCRx register is cleared unless it is - * reserved. - * @note Even if a PUy bit to set is reserved, the other PUy bits entered as - * input parameter at the same time are set. - * @param GPIO_Port : Specify the IO port. - * This parameter can be a value of - * @ref PWREx_GPIO_Port. - * @param GPIO_Pin : Specify the I/O pins numbers. - * This parameter can be a value of - * @ref PWREx_GPIO_Pin_Mask. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); - assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); - - /* Check GPIO port */ - switch (GPIO_Port) - { - case PWR_GPIO_A: /* Apply Pull Up to GPIO port A */ - SET_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14)))); - CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15)))); - break; - - case PWR_GPIO_B: /* Apply Pull Up to GPIO port B */ - SET_BIT(PWR->PUCRB, GPIO_Pin); - CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4)))); - break; - - case PWR_GPIO_C: /* Apply Pull Up to GPIO port C */ - SET_BIT(PWR->PUCRC, GPIO_Pin); - CLEAR_BIT(PWR->PDCRC, GPIO_Pin); - break; - - case PWR_GPIO_D: /* Apply Pull Up to GPIO port D */ - SET_BIT(PWR->PUCRD, GPIO_Pin); - CLEAR_BIT(PWR->PDCRD, GPIO_Pin); - break; - - case PWR_GPIO_E: /* Apply Pull Up to GPIO port E */ - SET_BIT(PWR->PUCRE, GPIO_Pin); - CLEAR_BIT(PWR->PDCRE, GPIO_Pin); - break; - -#ifdef PWR_PUCRF_PU0 - case PWR_GPIO_F: /* Apply Pull Up to GPIO port F */ - SET_BIT(PWR->PUCRF, GPIO_Pin); - CLEAR_BIT(PWR->PDCRF, GPIO_Pin); - break; -#endif /* PWR_PUCRF_PU0 */ - - case PWR_GPIO_G: /* Apply Pull Up to GPIO port G */ - SET_BIT(PWR->PUCRG, GPIO_Pin); - CLEAR_BIT(PWR->PDCRG, GPIO_Pin); - break; - - case PWR_GPIO_H: /* Apply Pull Up to GPIO port H */ - SET_BIT(PWR->PUCRH, GPIO_Pin); - CLEAR_BIT(PWR->PDCRH, GPIO_Pin); - break; - -#ifdef PWR_PUCRI_PU0 - case PWR_GPIO_I: /* Apply Pull Up to GPIO port I */ - SET_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif /* PWR_PUCRI_PU0 */ - -#if defined (PWR_PUCRJ_PU0) - case PWR_GPIO_J: /* Apply Pull Up to GPIO port J */ - SET_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); - break; -#endif /* defined (PWR_PUCRJ_PU0) */ - - default: - return HAL_ERROR; - break; - } - - return HAL_OK; -} - -/** - * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. - * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure - * the I/O in pull-up state in Standby and Shutdown modes. - * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as - * input parameter at the same time are reset. - * @param GPIO_Port : Specify the IO port. - * This parameter can be a value of - * @ref PWREx_GPIO_Port. - * @param GPIO_Pin : Specify the I/O pins numbers. - * This parameter can be a value of - * @ref PWREx_GPIO_Pin_Mask. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO_Port, uint32_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); - assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); - - /* Check GPIO port */ - switch (GPIO_Port) - { - case PWR_GPIO_A: /* Disable Pull Up for GPIO port A */ - CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14)))); - break; - - case PWR_GPIO_B: /* Disable Pull Up for GPIO port B */ - CLEAR_BIT(PWR->PUCRB, GPIO_Pin); - break; - - case PWR_GPIO_C: /* Disable Pull Up for GPIO port C */ - CLEAR_BIT(PWR->PUCRC, GPIO_Pin); - break; - - case PWR_GPIO_D: /* Disable Pull Up for GPIO port D */ - CLEAR_BIT(PWR->PUCRD, GPIO_Pin); - break; - - case PWR_GPIO_E: /* Disable Pull Up for GPIO port E */ - CLEAR_BIT(PWR->PUCRE, GPIO_Pin); - break; - -#ifdef PWR_PUCRF_PU0 - case PWR_GPIO_F: /* Disable Pull Up for GPIO port F */ - CLEAR_BIT(PWR->PUCRF, GPIO_Pin); - break; -#endif /* PWR_PUCRF_PU0 */ - - case PWR_GPIO_G: /* Disable Pull Up for GPIO port G */ - CLEAR_BIT(PWR->PUCRG, GPIO_Pin); - break; - - case PWR_GPIO_H: /* Disable Pull Up for GPIO port H */ - CLEAR_BIT(PWR->PUCRH, GPIO_Pin); - break; - -#ifdef PWR_PUCRI_PU0 - case PWR_GPIO_I: /* Disable Pull Up for GPIO port I */ - CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif /* PWR_PUCRI_PU0 */ - -#if defined (PWR_PUCRJ_PU0) - case PWR_GPIO_J: /* Disable Pull Up for GPIO port J */ - CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); - break; -#endif /* defined (PWR_PUCRJ_PU0) */ - - default: - return HAL_ERROR; - break; - } - - return HAL_OK; -} - -/** - * @brief Enable GPIO pull-down state in Standby and Shutdown modes. - * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note This state is effective in Standby and Shutdown modes only if APC bit - * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. - * @note The configuration is lost when exiting the Shutdown mode due to the - * power-on reset, maintained when exiting the Standby mode. - * @note To avoid any conflict at Standby and Shutdown modes exits, the - * corresponding PUy bit of PWR_PUCRx register is cleared unless it is - * reserved. - * @note Even if a PDy bit to set is reserved, the other PDy bits entered as - * input parameter at the same time are set. - * @param GPIO_Port : Specify the IO port. - * This parameter can be a value of - * @ref PWREx_GPIO_Port. - * @param GPIO_Pin : Specify the I/O pins numbers. - * This parameter can be a value of - * @ref PWREx_GPIO_Pin_Mask. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); - assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); - - /* Check GPIO port */ - switch (GPIO_Port) - { - case PWR_GPIO_A: /* Apply Pull Down to GPIO port A */ - SET_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15)))); - CLEAR_BIT(PWR->PUCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_14)))); - break; - - case PWR_GPIO_B: /* Apply Pull Down to GPIO port B */ - SET_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4)))); - CLEAR_BIT(PWR->PUCRB, GPIO_Pin); - break; - - case PWR_GPIO_C: /* Apply Pull Down to GPIO port C */ - SET_BIT(PWR->PDCRC, GPIO_Pin); - CLEAR_BIT(PWR->PUCRC, GPIO_Pin); - break; - - case PWR_GPIO_D: /* Apply Pull Down to GPIO port D */ - SET_BIT(PWR->PDCRD, GPIO_Pin); - CLEAR_BIT(PWR->PUCRD, GPIO_Pin); - break; - - case PWR_GPIO_E: /* Apply Pull Down to GPIO port E */ - SET_BIT(PWR->PDCRE, GPIO_Pin); - CLEAR_BIT(PWR->PUCRE, GPIO_Pin); - break; - -#ifdef PWR_PUCRF_PU0 - case PWR_GPIO_F: /* Apply Pull Down to GPIO port F */ - SET_BIT(PWR->PDCRF, GPIO_Pin); - CLEAR_BIT(PWR->PUCRF, GPIO_Pin); - break; -#endif /* PWR_PUCRF_PU0 */ - - case PWR_GPIO_G: /* Apply Pull Down to GPIO port G */ - SET_BIT(PWR->PDCRG, GPIO_Pin); - CLEAR_BIT(PWR->PUCRG, GPIO_Pin); - break; - - case PWR_GPIO_H: /* Apply Pull Down to GPIO port H */ - SET_BIT(PWR->PDCRH, GPIO_Pin); - CLEAR_BIT(PWR->PUCRH, GPIO_Pin); - break; - -#ifdef PWR_PUCRI_PU0 - case PWR_GPIO_I: /* Apply Pull Down to GPIO port I */ - SET_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PUCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif /* PWR_PUCRI_PU0 */ - -#if defined (PWR_PUCRJ_PU0) - case PWR_GPIO_J: /* Apply Pull Down to GPIO port J */ - SET_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); - CLEAR_BIT(PWR->PUCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); - break; -#endif /* defined (PWR_PUCRJ_PU0) */ - - default: - return HAL_ERROR; - break; - } - - return HAL_OK; -} - -/** - * @brief Disable GPIO pull-down state in Standby and Shutdown modes. - * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O - * in pull-down state in Standby and Shutdown modes. - * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input - * parameter at the same time are reset. - * @param GPIO_Port : Specify the IO port. - * This parameter can be a value of - * @ref PWREx_GPIO_Port. - * @param GPIO_Pin : Specify the I/O pins numbers. - * This parameter can be a value of - * @ref PWREx_GPIO_Pin_Mask. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO_Port, uint32_t GPIO_Pin) -{ - /* Check the parameters */ - assert_param(IS_PWR_GPIO_PORT(GPIO_Port)); - assert_param(IS_PWR_GPIO_PIN_MASK(GPIO_Pin)); - - /* Check GPIO port */ - switch (GPIO_Port) - { - case PWR_GPIO_A: /* Disable Pull Down for GPIO port A */ - CLEAR_BIT(PWR->PDCRA, (GPIO_Pin & (~(PWR_GPIO_BIT_13 | PWR_GPIO_BIT_15)))); - break; - - case PWR_GPIO_B: /* Disable Pull Down for GPIO port B */ - CLEAR_BIT(PWR->PDCRB, (GPIO_Pin & (~(PWR_GPIO_BIT_4)))); - break; - - case PWR_GPIO_C: /* Disable Pull Down for GPIO port C */ - CLEAR_BIT(PWR->PDCRC, GPIO_Pin); - break; - - case PWR_GPIO_D: /* Disable Pull Down for GPIO port D */ - CLEAR_BIT(PWR->PDCRD, GPIO_Pin); - break; - - case PWR_GPIO_E: /* Disable Pull Down for GPIO port E */ - CLEAR_BIT(PWR->PDCRE, GPIO_Pin); - break; - -#ifdef PWR_PUCRF_PU0 - case PWR_GPIO_F: /* Disable Pull Down for GPIO port F */ - CLEAR_BIT(PWR->PDCRF, GPIO_Pin); - break; -#endif /* PWR_PUCRF_PU0 */ - - case PWR_GPIO_G: /* Disable Pull Down for GPIO port G */ - CLEAR_BIT(PWR->PDCRG, GPIO_Pin); - break; - - case PWR_GPIO_H: /* Disable Pull Down for GPIO port H */ - CLEAR_BIT(PWR->PDCRH, GPIO_Pin); - break; - -#ifdef PWR_PUCRI_PU0 - case PWR_GPIO_I: /* Disable Pull Down for GPIO port I */ - CLEAR_BIT(PWR->PDCRI, (GPIO_Pin & PWR_PORTI_AVAILABLE_PINS)); - break; -#endif /* PWR_PUCRI_PU0 */ - -#if defined (PWR_PUCRJ_PU0) - case PWR_GPIO_J: /* Disable Pull Down for GPIO port J */ - CLEAR_BIT(PWR->PDCRJ, (GPIO_Pin & PWR_PORTJ_AVAILABLE_PINS)); - break; -#endif /* defined (PWR_PUCRJ_PU0) */ - - default: - return HAL_ERROR; - break; - } - - return HAL_OK; -} -/** - * @} - */ - -#endif /* defined (HAL_PWR_MODULE_ENABLED) */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c deleted file mode 100644 index 1b47d2327..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc.c +++ /dev/null @@ -1,2285 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_rcc.c - * @author MCD Application Team - * @brief RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Reset and Clock Control (RCC) peripheral: - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### RCC specific features ##### - ============================================================================== - [..] - After reset the device is running from Multiple Speed Internal oscillator - (4 MHz) with Flash 0 wait state. Flash prefetch buffer, D-Cache - and I-Cache are disabled, and all peripherals are off except internal - SRAM, Flash and JTAG. - - (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: - all peripherals mapped on these busses are running at MSI speed. - (+) The clock for all peripherals is switched off, except the SRAM and FLASH. - (+) All GPIOs are in analog mode, except the JTAG pins which - are assigned to be used for debug purpose. - - [..] - Once the device started from reset, the user application has to: - (+) Configure the clock source to be used to drive the System clock - (if the application needs higher frequency/performance) - (+) Configure the System clock frequency and Flash settings - (+) Configure the AHB and APB busses prescalers - (+) Enable the clock for the peripheral(s) to be used - (+) Configure the clock source(s) for peripherals which clocks are not - derived from the System clock (SAIx, SYSTICK, RTC, ADC, USB OTG FS/USB FS/SDMMC1/RNG) - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup RCC RCC - * @brief RCC HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -#define PLLDIVR_RESET_VALUE (0x01010280U) -#define PLL_FRAC_WAIT_VALUE 1U /* PLL Fractional part waiting time before new latch enable : 1 ms */ -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_Private_Macros - * @{ - */ -#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \ - (((__OSCILLATOR__) & ~RCC_OSCILLATORTYPE_ALL) == 0x00U)) - -#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \ - ((__HSE__) == RCC_HSE_BYPASS) || ((__HSE__) == RCC_HSE_BYPASS_DIGITAL)) - -#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \ - ((__LSE__) == RCC_LSE_ON_RTC_ONLY) || ((__LSE__) == RCC_LSE_BYPASS_RTC_ONLY) || \ - ((__LSE__) == RCC_LSE_BYPASS)) - -#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON)) - -#define IS_RCC_HSI_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= (uint32_t)( RCC_ICSCR3_HSITRIM >>\ - RCC_ICSCR3_HSITRIM_Pos)) - -#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON)) - -#define IS_RCC_LSIDIV(__LSIDIV__) (((__LSIDIV__) == RCC_LSI_DIV1) || ((__LSIDIV__) == RCC_LSI_DIV128)) - -#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON)) - -#define IS_RCC_MSICALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 255U) - -#define IS_RCC_HSI48(__HSI48__) (((__HSI48__) == RCC_HSI48_OFF) || ((__HSI48__) == RCC_HSI48_ON)) - -#define IS_RCC_SHSI(__SHSI__) (((__SHSI__) == RCC_SHSI_OFF) || ((__SHSI__) == RCC_SHSI_ON)) - -#define IS_RCC_MSIK(__MSIK__) (((__MSIK__) == RCC_MSIK_OFF) || ((__MSIK__) == RCC_MSIK_ON)) - -#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || \ - ((PLL) == RCC_PLL_ON)) - -#define IS_RCC_PLLMBOOST_VALUE(VALUE) (((VALUE) == RCC_PLLMBOOST_DIV1) || \ - ((VALUE) == RCC_PLLMBOOST_DIV2) || \ - ((VALUE) == RCC_PLLMBOOST_DIV4) || \ - ((VALUE) == RCC_PLLMBOOST_DIV6) || \ - ((VALUE) == RCC_PLLMBOOST_DIV8) || \ - ((VALUE) == RCC_PLLMBOOST_DIV10) || \ - ((VALUE) == RCC_PLLMBOOST_DIV12) || \ - ((VALUE) == RCC_PLLMBOOST_DIV14) || \ - ((VALUE) == RCC_PLLMBOOST_DIV16)) - -#define IS_RCC_PLLCLOCKOUT_VALUE(VALUE) (((VALUE) == RCC_PLL1_DIVP) || \ - ((VALUE) == RCC_PLL1_DIVQ) || \ - ((VALUE) == RCC_PLL1_DIVR)) - -#define IS_RCC_PLLRGE_VALUE(VALUE) (((VALUE) == RCC_PLLVCIRANGE_0) || \ - ((VALUE) == RCC_PLLVCIRANGE_1)) - -#define IS_RCC_PLL_FRACN_VALUE(VALUE) ((VALUE) <= 8191U) - -#define IS_RCC_CLOCKTYPE(CLK) ((1U <= (CLK)) && ((CLK) <= 0x1FU)) - -#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK)) - -#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \ - ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \ - ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \ - ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \ - ((__HCLK__) == RCC_SYSCLK_DIV512)) - -#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \ - ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \ - ((__PCLK__) == RCC_HCLK_DIV16)) - -#define IS_RCC_MCO(__MCOX__) ((__MCOX__) == RCC_MCO1) - -#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_PLL1CLK) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSI) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_LSE) || \ - ((__SOURCE__) == RCC_MCO1SOURCE_HSI48)|| \ - ((__SOURCE__) == RCC_MCO1SOURCE_MSIK)) - -#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \ - ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \ - ((__DIV__) == RCC_MCODIV_16)) - -#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMLOW) || \ - ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || \ - ((__DRIVE__) == RCC_LSEDRIVE_HIGH)) - -#define IS_RCC_ITEM_ATTRIBUTES(ITEM) ((0U < (ITEM)) && ((ITEM) <= 0x1FFFU)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_SEC_PRIV) || \ - ((ATTRIBUTES) == RCC_SEC_NPRIV) || \ - ((ATTRIBUTES) == RCC_NSEC_PRIV) || \ - ((ATTRIBUTES) == RCC_NSEC_NPRIV)) -#else -#define IS_RCC_ATTRIBUTES(ATTRIBUTES) (((ATTRIBUTES) == RCC_NSEC_NPRIV) || ((ATTRIBUTES) == RCC_NSEC_PRIV)) -#endif /* __ARM_FEATURE_CMSE */ -/** - * @} - */ - -/* Private define ------------------------------------------------------------*/ -/** @defgroup RCC_Private_Constants RCC Private Constants - * @{ - */ -#define LSI_TIMEOUT_VALUE 5UL /* 5 ms (LSI maximum timeout is LSI startup time + LSI_VALUE/128 when - LSI prediv is used) */ -#define HSI48_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define SHSI_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define MSIK_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define PLL_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define CLOCKSWITCH_TIMEOUT_VALUE 5000UL /* 5 s */ -#define EPOD_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/** @defgroup RCC_Private_Macros RCC Private Macros - * @{ - */ - -#define MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() - -#define MCO1_GPIO_PORT GPIOA - -#define MCO1_PIN GPIO_PIN_8 - -#define RCC_PLL_OSCSOURCE_CONFIG(__HAL_RCC_PLLSOURCE__) \ - (MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (uint32_t)(__HAL_RCC_PLLSOURCE__))) -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_Private_Functions RCC Private Functions - * @{ - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCC_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * - @verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] - This section provides functions allowing to configure the internal and external oscillators - (HSE, HSI, LSE, MSI, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 - and APB2). - - [..] Internal/external clock and PLL configuration - (+) HSI (high-speed internal): 16 MHz factory-trimmed RC used directly or through - the PLL as System clock source. - - (+) MSI (Multiple Speed Internal): Its frequency is software trimmable from 100KHZ to 48MHZ. - It can be used to generate the clock for the USB FS or USB OTG FS (48 MHz). - The number of flash wait states is automatically adjusted when MSI range is updated with - HAL_RCC_OscConfig() and the MSI is used as System clock source. - - (+) LSI (low-speed internal): 32 KHz low consumption RC used as IWDG and/or RTC - clock source. - - (+) HSE (high-speed external): 4 to 48 MHz crystal oscillator used directly or - through the PLL as System clock source. Can be used also optionally as RTC clock source. - - (+) LSE (low-speed external): 32.768 KHz oscillator used optionally as RTC clock source. - - (+) PLL (clocked by HSI, HSE or MSI) providing up to three independent output clocks: - (++) The first output is used to generate the high speed system clock (up to 80MHz). - (++) The second output is used to generate the clock for the USB FS or USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - (++) The third output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) PLL2 (clocked by HSI, HSE or MSI) providing up to three independent output clocks: - (++) The first output is used to generate SAR ADC1 clock. - (++) The second output is used to generate the clock for the USB Fs or USB OTG FS (48 MHz), - the random analog generator (<=48 MHz) and the SDMMC1 (<= 48 MHz). - (++) The Third output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) PLL3 (clocked by HSI , HSE or MSI) providing up to two independent output clocks: - (++) The first output is used to generate SAR ADC4 clock. - (++) The second output is used to generate an accurate clock to achieve - high-quality audio performance on SAI interface. - - (+) CSS (Clock security system): once enabled, if a HSE clock failure occurs - (HSE used directly or through PLL as System clock source), the System clock - is automatically switched to HSI and an interrupt is generated if enabled. - The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) - exception vector. - - (+) MCO (microcontroller clock output): used to output MSI, LSI, HSI, LSE, HSE or - main PLL clock (through a configurable prescaler) on PA8 pin. - - [..] System, AHB and APB busses clocks configuration - (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, - HSE and main PLL. - The AHB clock (HCLK) is derived from System clock through configurable - prescaler and used to clock the CPU, memory and peripherals mapped - on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived - from AHB clock through configurable prescalers and used to clock - the peripherals mapped on these busses. You can use - "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. - - -@- All the peripheral clocks are derived from the System clock (SYSCLK) except: - - (+@) SAI: the SAI clock can be derived either from a specific PLL (PLL2) or (PLL3) or - from an external clock mapped on the SAI_CKIN pin. - You have to use HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock - divided by 2 to 31. - You have to use __HAL_RCC_RTC_ENABLE() and HAL_RCCEx_PeriphCLKConfig() function - to configure this clock. - (+@) USB FS, USB OTG FS, SDMMC1 and RNG: USB OTG FS or USB FS requires a frequency equal to 48 MHz - to work correctly, while the SDMMC1 and RNG peripherals require a frequency - equal or lower than to 48 MHz. This clock is derived of the main PLL or PLL2 - through PLLQ divider. You have to enable the peripheral clock and use - HAL_RCCEx_PeriphCLKConfig() function to configure this clock. - (+@) IWDG clock which is always the LSI clock. - - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2 is 80 MHz. - The clock source frequency should be adapted depending on the device voltage range - as listed in the Reference Manual "Clock source frequency versus voltage scaling" chapter. - - @endverbatim - - - Table 1. HCLK clock frequency for STM32U5xx devices - +-------------------------------------------------------+----------------------------------------+ - | Latency | HCLK clock frequency (MHz) 0.9V-1.2V | - | |-------------------------------------|---------------------+------------------| - | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 | - | | 1.1 V - 1.2V | 1.0 V - 1.1V | 0.9 V - 1.0V | 0.9V | - |-----------------|------------------|------------------|---------------------|------------------| - |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5 | 0 < HCLK <= 8 | - |-----------------|------------------|------------------|---------------------|------------------| - |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25 | 8 < HCLK <= 16 | - |-----------------|------------------|------------------|---------------------|------------------| - |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5 | 16 < HCLK <= 24 | - |-----------------|------------------|------------------|---------------------|------------------| - |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100 | 37.5 < HCLK <= 50 | - | - |-----------------|------------------|------------------|---------------------|------------------| - |4WS(5 CPU cycles)|128 < HCLK <= 160 | - | - | - | - +-----------------+------------------+------------------+---------------------+------------------+ - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - MSI ON and used as system clock source - * - HSE, HSI, PLL, PLL2 and PLLISAI2 OFF - * - AHB, APB1 and APB2 prescaler set to 1 - * - CSS, MCO1 OFF - * - All interrupts disabled - * - All interrupt and reset flags cleared - * @note This function doesn't modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_RCC_DeInit(void) -{ - uint32_t tickstart; - - tickstart = HAL_GetTick(); - - /* Set MSION bit */ - SET_BIT(RCC->CR, RCC_CR_MSISON); - - /* Insure MSIRDY bit is set before writing default MSIRANGE value */ - while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Set MSIRANGE default value */ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSISRANGE, RCC_MSIRANGE_4); - - /* Set MSITRIM default value */ - WRITE_REG(RCC->ICSCR2, 0x00084210U); - - /* Set MSIKRANGE default value */ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIKRANGE, RCC_MSIKRANGE_4); - - /* Set MSIRGSEL default value */ - MODIFY_REG(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL, 0x0U); - - tickstart = HAL_GetTick(); - - /* Reset CFGR register (MSI is selected as system clock source) */ - CLEAR_REG(RCC->CFGR1); - CLEAR_REG(RCC->CFGR2); - - /* Wait till clock switch is ready */ - while (READ_BIT(RCC->CFGR1, RCC_CFGR1_SWS) != 0U) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset MSIKON, HSECSSON , HSEON, HSEBYP, HSION, HSIKERON, PLL1ON, PLL2ON, PLL3ON bits */ - CLEAR_BIT(RCC->CR, RCC_CR_MSIKON | RCC_CR_MSIPLLSEL | RCC_CR_MSIPLLFAST | RCC_CR_MSIKERON | RCC_CR_CSSON | \ - RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON | RCC_CR_HSI48ON | \ - RCC_CR_HSEON | RCC_CR_SHSION); - - /* Reset HSEBYP & HSEEXT bits */ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP | RCC_CR_HSEEXT); - - tickstart = HAL_GetTick(); - - /* Clear PLL1ON bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON); - - /* Wait till PLL1 is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - tickstart = HAL_GetTick(); - - /* Reset PLL2N bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON); - - /* Wait till PLL2 is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - tickstart = HAL_GetTick(); - - /* Reset PLL3 bit */ - CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON); - - /* Wait till PLL3 is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Reset PLL1CFGR register */ - CLEAR_REG(RCC->PLL1CFGR); - - /* Reset PLL1DIVR register */ - WRITE_REG(RCC->PLL1DIVR, PLLDIVR_RESET_VALUE); - - /* Reset PLL1FRACR register */ - CLEAR_REG(RCC->PLL1FRACR); - - /* Reset PLL2CFGR register */ - CLEAR_REG(RCC->PLL2CFGR); - - /* Reset PLL2DIVR register */ - WRITE_REG(RCC->PLL2DIVR, PLLDIVR_RESET_VALUE); - - /* Reset PLL2FRACR register */ - CLEAR_REG(RCC->PLL2FRACR); - - /* Reset PLL3CFGR register */ - CLEAR_REG(RCC->PLL3CFGR); - - /* Reset PLL3DIVR register */ - WRITE_REG(RCC->PLL3DIVR, PLLDIVR_RESET_VALUE); - - /* Reset PLL3FRACR register */ - CLEAR_REG(RCC->PLL3FRACR); - - /* Disable all interrupts */ - CLEAR_REG(RCC->CIER); - - /* Clear all interrupts flags */ - WRITE_REG(RCC->CICR, 0xFFFFFFFFU); - - /* Reset all CSR flags */ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = MSI_VALUE; - - /* Decreasing the number of wait states because of lower CPU frequency */ - - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLASH_LATENCY_DEFAULT); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLASH_LATENCY_DEFAULT) - { - return HAL_ERROR; - } - - /* Adapt Systick interrupt period */ - return (HAL_InitTick(TICK_INT_PRIORITY)); - -} - -/** - * @brief Initialize the RCC Oscillators according to the specified parameters in the - * RCC_OscInitTypeDef. - * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC Oscillators. - * @note The PLL is not disabled when used as system clock. - * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not - * supported by this function. User should request a transition to LSE Off - * first and then LSE On or LSE Bypass. - * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not - * supported by this function. User should request a transition to HSE Off - * first and then HSE On or HSE Bypass. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_OscConfig(const RCC_OscInitTypeDef *pRCC_OscInitStruct) -{ - uint32_t tickstart; - HAL_StatusTypeDef status; - uint32_t sysclk_source; - uint32_t pll_config; - FlagStatus pwrboosten = RESET; - uint32_t temp1_pllckcfg; - uint32_t temp2_pllckcfg; - - /* Check Null pointer */ - if (pRCC_OscInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_OSCILLATORTYPE(pRCC_OscInitStruct->OscillatorType)); - - sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); - - /*----------------------------- MSI Configuration --------------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) - { - /* Check the parameters */ - assert_param(IS_RCC_MSI(pRCC_OscInitStruct->MSIState)); - assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue)); - assert_param(IS_RCC_MSI_CLOCK_RANGE(pRCC_OscInitStruct->MSIClockRange)); - - /*Check if MSI is used as system clock or as PLL source when PLL is selected as system clock*/ - - if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || - ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) - { - if (pRCC_OscInitStruct->MSIState == RCC_MSI_OFF) - { - return HAL_ERROR; - } - - /* Otherwise, just the calibration and MSI range change are allowed */ - else - { - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device */ - if (pRCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) - { - /* Decrease number of wait states update if necessary */ - /* Only possible when MSI is the System clock source */ - if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) - { - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - } - - /* Selects the Multiple Speed oscillator (MSI) clock range */ - __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ - (pRCC_OscInitStruct->MSIClockRange)); - } - else - { - /* Else, keep current flash latency while decreasing applies */ - /* Selects the Multiple Speed oscillator (MSI) clock range */ - __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ - (pRCC_OscInitStruct->MSIClockRange)); - - if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) - { - if (RCC_SetFlashLatencyFromMSIRange(pRCC_OscInitStruct->MSIClockRange) != HAL_OK) - { - return HAL_ERROR; - } - } - } - - /* Update the SystemCoreClock global variable */ - (void) HAL_RCC_GetHCLKFreq(); - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - if (status != HAL_OK) - { - return status; - } - } - } - else - { - /* Check the MSI State */ - if (pRCC_OscInitStruct->MSIState != RCC_MSI_OFF) - { - /* Enable the Internal High Speed oscillator (MSI) */ - __HAL_RCC_MSI_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - /* Selects the Multiple Speed oscillator (MSI) clock range */ - __HAL_RCC_MSI_RANGE_CONFIG(pRCC_OscInitStruct->MSIClockRange); - /* Adjusts the Multiple Speed oscillator (MSI) calibration value */ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ - (pRCC_OscInitStruct->MSIClockRange)); - - } - else - { - /* Disable the Internal High Speed oscillator (MSI) */ - __HAL_RCC_MSI_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------- HSE Configuration ------------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) - { - /* Check the parameters */ - assert_param(IS_RCC_HSE(pRCC_OscInitStruct->HSEState)); - - /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ - if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || - ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) - { - if (pRCC_OscInitStruct->HSEState == RCC_HSE_OFF) - { - return HAL_ERROR; - } - } - else - { - /* Set the new HSE configuration ---------------------------------------*/ - __HAL_RCC_HSE_CONFIG(pRCC_OscInitStruct->HSEState); - - /* Check the HSE State */ - if (pRCC_OscInitStruct->HSEState != RCC_HSE_OFF) - { - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - tickstart = HAL_GetTick(); - - /* Wait till HSE is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*----------------------------- HSI Configuration --------------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI(pRCC_OscInitStruct->HSIState)); - assert_param(IS_RCC_HSI_CALIBRATION_VALUE(pRCC_OscInitStruct->HSICalibrationValue)); - - /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ - if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || - ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) - { - /* When HSI is used as system clock it will not be disabled */ - if (pRCC_OscInitStruct->HSIState == RCC_HSI_OFF) - { - return HAL_ERROR; - } - /* Otherwise, just the calibration is allowed */ - else - { - /* Adjusts the Internal High Speed oscillator (HSI) calibration value */ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue); - } - } - else - { - /* Check the HSI State */ - if (pRCC_OscInitStruct->HSIState != RCC_HSI_OFF) - { - /* Enable the Internal High Speed oscillator (HSI) */ - __HAL_RCC_HSI_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till HSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Adjusts the Internal High Speed oscillator (HSI) calibration value */ - __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(pRCC_OscInitStruct->HSICalibrationValue); - } - else - { - /* Disable the Internal High Speed oscillator (HSI) */ - __HAL_RCC_HSI_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till HSI is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - /*------------------------------ LSI Configuration -------------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) - { - /* Check the parameters */ - assert_param(IS_RCC_LSI(pRCC_OscInitStruct->LSIState)); - - FlagStatus pwrclkchanged = RESET; - - /* Update LSI configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->DBPR, PWR_DBPR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - /* Check the LSI State */ - if (pRCC_OscInitStruct->LSIState != RCC_LSI_OFF) - { - uint32_t bdcr_temp = RCC->BDCR; - - /* Check LSI division factor */ - assert_param(IS_RCC_LSIDIV(pRCC_OscInitStruct->LSIDiv)); - - if (pRCC_OscInitStruct->LSIDiv != (bdcr_temp & RCC_BDCR_LSIPREDIV)) - { - if (((bdcr_temp & RCC_BDCR_LSIRDY) == RCC_BDCR_LSIRDY) && \ - ((bdcr_temp & RCC_BDCR_LSION) != RCC_BDCR_LSION)) - { - /* If LSIRDY is set while LSION is not enabled, LSIPREDIV can't be updated */ - /* The LSIPREDIV cannot be changed if the LSI is used by the IWDG or by the RTC */ - return HAL_ERROR; - } - - /* Turn off LSI before changing RCC_BDCR_LSIPREDIV */ - if ((bdcr_temp & RCC_BDCR_LSION) == RCC_BDCR_LSION) - { - __HAL_RCC_LSI_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set LSI division factor */ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSIPREDIV, pRCC_OscInitStruct->LSIDiv); - } - - /* Enable the Internal Low Speed oscillator (LSI) */ - __HAL_RCC_LSI_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till LSI is ready */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal Low Speed oscillator (LSI) */ - __HAL_RCC_LSI_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till LSI is disabled */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSIRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - /* Restore clock configuration if changed */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - /*------------------------------ LSE Configuration -------------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSE(pRCC_OscInitStruct->LSEState)); - - /* Update LSE configuration in Backup Domain control register */ - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - /* Enable write access to Backup domain */ - SET_BIT(PWR->DBPR, PWR_DBPR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Set the new LSE configuration -----------------------------------------*/ - if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEON) != 0U) - { - if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSEBYP) != 0U) - { - /* LSE oscillator bypass enable */ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); - } - else - { - /* LSE oscillator enable */ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); - } - } - else - { - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); - } - - /* Check the LSE State */ - if (pRCC_OscInitStruct->LSEState != RCC_LSE_OFF) - { - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Enable LSESYS additionally if requested */ - if ((pRCC_OscInitStruct->LSEState & RCC_BDCR_LSESYSEN) != 0U) - { - SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); - - /* Wait till LSESYS is ready */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Make sure LSESYSEN/LSESYSRDY are reset */ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); - - /* Wait till LSESYSRDY is cleared */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - else - { - tickstart = HAL_GetTick(); - - /* Wait till LSE is disabled */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - if (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN) != 0U) - { - /* Reset LSESYSEN once LSE is disabled */ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); - - /* Wait till LSESYSRDY is cleared */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /* Restore clock configuration if changed */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - /*------------------------------ HSI48 Configuration -----------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48) - { - /* Check the parameters */ - assert_param(IS_RCC_HSI48(pRCC_OscInitStruct->HSI48State)); - - /* Check the HSI48 State */ - if (pRCC_OscInitStruct->HSI48State != RCC_HSI48_OFF) - { - /* Enable the Internal High Speed oscillator (HSI48) */ - __HAL_RCC_HSI48_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal High Speed oscillator (HSI48) */ - __HAL_RCC_HSI48_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till HSI48 is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_HSI48RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > HSI48_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - - /*------------------------------ SHSI Configuration -----------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_SHSI) == RCC_OSCILLATORTYPE_SHSI) - { - /* Check the parameters */ - assert_param(IS_RCC_SHSI(pRCC_OscInitStruct->SHSIState)); - - /* Check the SHSI State */ - if (pRCC_OscInitStruct->SHSIState != RCC_SHSI_OFF) - { - /* Enable the Secure Internal High Speed oscillator (SHSI) */ - __HAL_RCC_SHSI_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till SHSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Secure Internal High Speed oscillator (SHSI) */ - __HAL_RCC_SHSI_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till SHSI is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_SHSIRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > SHSI_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*------------------------------ MSIK Configuration -----------------------*/ - if (((pRCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSIK) == RCC_OSCILLATORTYPE_MSIK) - { - /* Check the parameters */ - assert_param(IS_RCC_MSIK(pRCC_OscInitStruct->MSIKState)); - assert_param(IS_RCC_MSIK_CLOCK_RANGE(pRCC_OscInitStruct->MSIKClockRange)); - assert_param(IS_RCC_MSICALIBRATION_VALUE(pRCC_OscInitStruct->MSICalibrationValue)); - - /* Check the MSIK State */ - if (pRCC_OscInitStruct->MSIKState != RCC_MSIK_OFF) - { - - /* Selects the Multiple Speed of kernel high speed oscillator (MSIK) clock range .*/ - __HAL_RCC_MSIK_RANGE_CONFIG(pRCC_OscInitStruct->MSIKClockRange); - /* Adjusts the Multiple Speed of kernel high speed oscillator (MSIK) calibration value.*/ - __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST((pRCC_OscInitStruct->MSICalibrationValue), \ - (pRCC_OscInitStruct->MSIClockRange)); - - /* Enable the Internal kernel High Speed oscillator (MSIK) */ - __HAL_RCC_MSIK_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till MSIK is ready */ - while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - /* Disable the Internal High Speed Kernel oscillator (MSIK) */ - __HAL_RCC_MSIK_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till MSIK is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_MSIKRDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > MSIK_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - /*-------------------------------- PLL Configuration -----------------------*/ - /* Check the parameters */ - assert_param(IS_RCC_PLL(pRCC_OscInitStruct->PLL.PLLState)); - - if ((pRCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE) - { - FlagStatus pwrclkchanged = RESET; - - /* Check if the PLL is used as system clock or not */ - if (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if ((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON) - { - /* Check the parameters */ - assert_param(IS_RCC_PLLMBOOST_VALUE(pRCC_OscInitStruct->PLL.PLLMBOOST)); - assert_param(IS_RCC_PLLSOURCE(pRCC_OscInitStruct->PLL.PLLSource)); - assert_param(IS_RCC_PLLM_VALUE(pRCC_OscInitStruct->PLL.PLLM)); - assert_param(IS_RCC_PLLN_VALUE(pRCC_OscInitStruct->PLL.PLLN)); - assert_param(IS_RCC_PLLP_VALUE(pRCC_OscInitStruct->PLL.PLLP)); - assert_param(IS_RCC_PLLQ_VALUE(pRCC_OscInitStruct->PLL.PLLQ)); - assert_param(IS_RCC_PLLR_VALUE(pRCC_OscInitStruct->PLL.PLLR)); - - /* Disable the main PLL */ - __HAL_RCC_PLL_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Requires to enable write access to Backup Domain of necessary */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - - /*Disable EPOD to configure PLL1MBOOST*/ - if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) == PWR_VOSR_BOOSTEN) - { - pwrboosten = SET; - } - CLEAR_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); - - /* Configure the main PLL clock source, multiplication and division factors */ - __HAL_RCC_PLL_CONFIG(pRCC_OscInitStruct->PLL.PLLSource, - pRCC_OscInitStruct->PLL.PLLMBOOST, - pRCC_OscInitStruct->PLL.PLLM, - pRCC_OscInitStruct->PLL.PLLN, - pRCC_OscInitStruct->PLL.PLLP, - pRCC_OscInitStruct->PLL.PLLQ, - pRCC_OscInitStruct->PLL.PLLR); - - assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); - - /* Disable PLL1FRACN */ - __HAL_RCC_PLL_FRACN_DISABLE(); - - /* Configure PLL PLL1FRACN */ - __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); - - /* Enable PLL1FRACN */ - __HAL_RCC_PLL_FRACN_ENABLE(); - - assert_param(IS_RCC_PLLRGE_VALUE(pRCC_OscInitStruct->PLL.PLLRGE)); - - /* Select PLL1 input reference frequency range: VCI */ - __HAL_RCC_PLL_VCIRANGE(pRCC_OscInitStruct->PLL.PLLRGE); - - if (pwrboosten == SET) - { - /* Enable the EPOD to reach max frequency */ - SET_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN); - } - - /* Restore clock configuration if changed */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - - /* Enable the main PLL */ - __HAL_RCC_PLL_ENABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Enable PLL System Clock output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR); - - } - else - { - /* Disable the main PLL */ - __HAL_RCC_PLL_DISABLE(); - - tickstart = HAL_GetTick(); - - /* Wait till PLL is disabled */ - while (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Unselect main PLL clock source and disable main PLL outputs to save power */ - RCC->PLL1CFGR &= ~(RCC_PLL1CFGR_PLL1SRC | RCC_PLL1CFGR_PLL1PEN | RCC_PLL1CFGR_PLL1QEN | RCC_PLL1CFGR_PLL1REN); - - } - } - else - { - /* Do not return HAL_ERROR if request repeats the current configuration */ - temp1_pllckcfg = RCC->PLL1CFGR; - temp2_pllckcfg = RCC->PLL1DIVR; - if (((pRCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) || - (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1SRC) != pRCC_OscInitStruct->PLL.PLLSource) || - ((READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1M) >> \ - RCC_PLL1CFGR_PLL1M_Pos) != (pRCC_OscInitStruct->PLL.PLLM - 1U)) || - (READ_BIT(temp1_pllckcfg, RCC_PLL1CFGR_PLL1MBOOST) != pRCC_OscInitStruct->PLL.PLLMBOOST) || - (READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1N) != (pRCC_OscInitStruct->PLL.PLLN - 1U)) || - ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1P) >> \ - RCC_PLL1DIVR_PLL1P_Pos) != (pRCC_OscInitStruct->PLL.PLLP - 1U)) || - ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1Q) >> \ - RCC_PLL1DIVR_PLL1Q_Pos) != (pRCC_OscInitStruct->PLL.PLLQ - 1U)) || - ((READ_BIT(temp2_pllckcfg, RCC_PLL1DIVR_PLL1R) >> \ - RCC_PLL1DIVR_PLL1R_Pos) != (pRCC_OscInitStruct->PLL.PLLR - 1U))) - { - return HAL_ERROR; - } - - /* FRACN1 on-the-fly value update */ - if ((READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_PLL1FRACN) >> \ - RCC_PLL1FRACR_PLL1FRACN_Pos) != (pRCC_OscInitStruct->PLL.PLLFRACN)) - { - assert_param(IS_RCC_PLL_FRACN_VALUE(pRCC_OscInitStruct->PLL.PLLFRACN)); - - /* Disable PLL1FRACN. */ - __HAL_RCC_PLL_FRACN_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait at least 2 CK_REF (PLL1 input source divided by M) period to make sure next latched value - will be taken into account. */ - while ((HAL_GetTick() - tickstart) < PLL_FRAC_WAIT_VALUE) - { - } - - /* Configure PLL PLL1FRACN */ - __HAL_RCC_PLL_FRACN_CONFIG(pRCC_OscInitStruct->PLL.PLLFRACN); - - /* Enable PLL1FRACN to latch the new value. */ - __HAL_RCC_PLL_FRACN_ENABLE(); - } - } - } - return HAL_OK; -} - -/** - * @brief Initialize the CPU, AHB and APB busses clocks according to the specified - * parameters in the pRCC_ClkInitStruct. - * @param pRCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that - * contains the configuration information for the RCC peripheral. - * @param FLatency FLASH Latency - * This parameter can be one of the following values: - * @arg FLASH_LATENCY_0 FLASH 0 Latency cycle - * @arg FLASH_LATENCY_1 FLASH 1 Latency cycle - * @arg FLASH_LATENCY_2 FLASH 2 Latency cycles - * @arg FLASH_LATENCY_3 FLASH 3 Latency cycles - * @arg FLASH_LATENCY_4 FLASH 4 Latency cycles - * @arg FLASH_LATENCY_5 FLASH 5 Latency cycles - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency - * and updated by HAL_RCC_GetHCLKFreq() function called within this function - * - * @note The MSI is used by default as system clock source after - * startup from Reset, wake-up from STANDBY mode. After restart from Reset, - * the MSI frequency is set to its default value 4 MHz. - * @note The HSI can be selected as system clock source after wakeup - * from STOP modes or in case of failure of the HSE used directly or indirectly - * as system clock (if the Clock Security System CSS is enabled). - * @note A switch from one clock source to another occurs only if the target - * clock source is ready (clock stable after startup delay or PLL locked). - * If a clock source which is not yet ready is selected, the switch will - * occur when the clock source is ready. - * @note You can use HAL_RCC_GetClockConfig() function to know which clock is - * currently used as system clock source. - * - * @note Depending on the device voltage range, the software has to set correctly - * HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency - * (for more details refer to section above "Initialization/de-initialization functions") - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *const pRCC_ClkInitStruct, uint32_t FLatency) -{ - HAL_StatusTypeDef status; - uint32_t tickstart; - - /* Check Null pointer */ - if (pRCC_ClkInitStruct == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_CLOCKTYPE(pRCC_ClkInitStruct->ClockType)); - assert_param(IS_FLASH_LATENCY(FLatency)); - - /* To correctly read data from FLASH memory, the number of wait states (LATENCY) - must be correctly programmed according to the frequency of the CPU clock - (HCLK) and the supply voltage of the device */ - - /* Increasing the number of wait states because of higher CPU frequency */ - if (FLatency > __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /* Increasing the BUS frequency divider */ - /*-------------------------- PCLK3 Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) - { - if ((pRCC_ClkInitStruct->APB3CLKDivider) > (RCC->CFGR3 & RCC_CFGR3_PPRE3)) - { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, pRCC_ClkInitStruct->APB3CLKDivider); - } - } - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - if ((pRCC_ClkInitStruct->APB2CLKDivider) > ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) - { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - if ((pRCC_ClkInitStruct->APB1CLKDivider) > (RCC->CFGR2 & RCC_CFGR2_PPRE1)) - { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); - } - } - - /*-------------------------- HCLK Configuration --------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - if ((pRCC_ClkInitStruct->AHBCLKDivider) > (RCC->CFGR2 & RCC_CFGR2_HPRE)) - { - assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); - } - } - - /*------------------------- SYSCLK Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) - { - assert_param(IS_RCC_SYSCLKSOURCE(pRCC_ClkInitStruct->SYSCLKSource)); - FlagStatus pwrclkchanged = RESET; - - /* PLL is selected as System Clock Source */ - if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - tickstart = HAL_GetTick(); - /* Check if EPOD is enabled */ - if (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTEN) != 0U) - { - /* Wait till BOOST is ready */ - while (READ_BIT(PWR->VOSR, PWR_VOSR_BOOSTRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > EPOD_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - - /* Restore clock configuration if changed */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - - /* Check the PLL ready flag */ - if (READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == 0U) - { - return HAL_ERROR; - } - } - else - { - /* HSE is selected as System Clock Source */ - if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - /* Check the HSE ready flag */ - if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - { - return HAL_ERROR; - } - } - /* MSI is selected as System Clock Source */ - else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - /* Check the MSI ready flag */ - if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) - { - return HAL_ERROR; - } - } - /* HSI is selected as System Clock Source */ - else - { - /* Check the HSI ready flag */ - if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - { - return HAL_ERROR; - } - } - } - - MODIFY_REG(RCC->CFGR1, RCC_CFGR1_SW, pRCC_ClkInitStruct->SYSCLKSource); - - tickstart = HAL_GetTick(); - - if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else if (pRCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_MSI) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - else - { - while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI) - { - if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - } - } - } - - /* Decreasing the BUS frequency divider */ - /*-------------------------- HCLK Configuration --------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) - { - if ((pRCC_ClkInitStruct->AHBCLKDivider) < (RCC->CFGR2 & RCC_CFGR2_HPRE)) - { - assert_param(IS_RCC_HCLK(pRCC_ClkInitStruct->AHBCLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_HPRE, pRCC_ClkInitStruct->AHBCLKDivider); - } - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (FLatency < __HAL_FLASH_GET_LATENCY()) - { - /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ - __HAL_FLASH_SET_LATENCY(FLatency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if (__HAL_FLASH_GET_LATENCY() != FLatency) - { - return HAL_ERROR; - } - } - - /*-------------------------- PCLK1 Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) - { - if ((pRCC_ClkInitStruct->APB1CLKDivider) < (RCC->CFGR2 & RCC_CFGR2_PPRE1)) - { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB1CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE1, pRCC_ClkInitStruct->APB1CLKDivider); - } - } - - /*-------------------------- PCLK2 Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) - { - if ((pRCC_ClkInitStruct->APB2CLKDivider) < ((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4)) - { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB2CLKDivider)); - MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PPRE2, ((pRCC_ClkInitStruct->APB2CLKDivider) << 4)); - } - } - - /*-------------------------- PCLK3 Configuration ---------------------------*/ - if (((pRCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK3) == RCC_CLOCKTYPE_PCLK3) - { - if ((pRCC_ClkInitStruct->APB3CLKDivider) < (RCC->CFGR3 & RCC_CFGR3_PPRE3)) - { - assert_param(IS_RCC_PCLK(pRCC_ClkInitStruct->APB3CLKDivider)); - MODIFY_REG(RCC->CFGR3, RCC_CFGR3_PPRE3, (pRCC_ClkInitStruct->APB3CLKDivider)); - } - } - - /* Update the SystemCoreClock global variable */ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; - - /* Configure the source of time base considering new system clocks settings*/ - status = HAL_InitTick(uwTickPrio); - - return status; -} - -/** - * @} - */ - -/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions - * @brief RCC clocks control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to: - - (+) Output clock to MCO pin. - (+) Retrieve current clock frequencies. - (+) Enable the Clock Security System. - -@endverbatim - * @{ - */ - -/** - * @brief Select the clock source to output on MCO pin(PA8). - * @note PA8 should be configured in alternate function mode. - * @param RCC_MCOx specifies the output direction for the clock source. - * For STM32U5xx family this parameter can have only one value: - * @arg @ref RCC_MCO1 Clock source to output on MCO1 pin(PA8). - * @param RCC_MCOSource specifies the clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_MCO1SOURCE_NOCLOCK MCO output disabled, no clock on MCO - * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_PLL1CLK main PLL clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSI48 HSI48 clock selected as MCO source for devices with HSI48 - * @param RCC_MCODiv specifies the MCO prescaler. - * This parameter can be one of the following values: - * @arg @ref RCC_MCODIV_1 no division applied to MCO clock - * @arg @ref RCC_MCODIV_2 division by 2 applied to MCO clock - * @arg @ref RCC_MCODIV_4 division by 4 applied to MCO clock - * @arg @ref RCC_MCODIV_8 division by 8 applied to MCO clock - * @arg @ref RCC_MCODIV_16 division by 16 applied to MCO clock - * @retval None - */ -void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv) -{ - GPIO_InitTypeDef gpio_initstruct; - /* Check the parameters */ - assert_param(IS_RCC_MCO(RCC_MCOx)); - assert_param(IS_RCC_MCODIV(RCC_MCODiv)); - assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource)); - - /* MCO Clock Enable */ - MCO1_CLK_ENABLE(); - - /* Configure the MCO1 pin in alternate function mode */ - gpio_initstruct.Pin = MCO1_PIN; - gpio_initstruct.Mode = GPIO_MODE_AF_PP; - gpio_initstruct.Speed = GPIO_SPEED_FREQ_HIGH; - gpio_initstruct.Pull = GPIO_NOPULL; - gpio_initstruct.Alternate = GPIO_AF0_MCO; - HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio_initstruct); - - /* Mask MCOSEL[] and MCOPRE[] bits then set MCO1 clock source and prescaler */ - MODIFY_REG(RCC->CFGR1, (RCC_CFGR1_MCOSEL | RCC_CFGR1_MCOPRE), (RCC_MCOSource | RCC_MCODiv)); -} - -/** - * @brief Return the SYSCLK frequency. - * @note The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note If SYSCLK source is MSI, function returns values based on MSI - * Value as defined by the MSI range. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**), - * HSI_VALUE(*) or MSI Value multiplied/divided by the PLL factors. - * @note (*) HSI_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (**) HSE_VALUE is a constant defined in stm32u5xx_hal_conf.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * @note The result of this function could be not correct when using fractional - * value for HSE crystal. - * @note This function can be used by the user application to compute the - * baudrate for the communication peripherals or configure other parameters. - * @note Each time SYSCLK changes, this function must be called to update the - * right SYSCLK value. Otherwise, any configuration based on this function will be incorrect. - * @retval SYSCLK frequency - */ -uint32_t HAL_RCC_GetSysClockFreq(void) -{ - uint32_t msirange = 0U; - uint32_t pllsource; - uint32_t pllr; - uint32_t pllm; - uint32_t pllfracen; - uint32_t sysclockfreq = 0U; - uint32_t sysclk_source; - uint32_t pll_oscsource; - float_t fracn1; - float_t pllvco; - - sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); - pll_oscsource = __HAL_RCC_GET_PLL_OSCSOURCE(); - - if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || - ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_oscsource == RCC_PLLSOURCE_MSI))) - { - /* MSI or PLL with MSI source used as system clock source */ - - /* Get SYSCLK source */ - if (READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) - { - /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; - } - else - { - /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; - } - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) - { - /* MSI used as system clock source */ - sysclockfreq = msirange; - } - } - else if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI) - { - /* HSI used as system clock source */ - sysclockfreq = HSI_VALUE; - } - else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) - { - /* HSE used as system clock source */ - sysclockfreq = HSE_VALUE; - } - else - { - /* Nothing to do */ - } - - if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) - { - /* PLL used as system clock source - PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); - pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; - pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ - RCC_PLL1FRACR_PLL1FRACN_Pos)); - - switch (pllsource) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pllvco = ((float_t)HSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1U); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1U); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - default: - pllvco = ((float_t) msirange / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1U); - break; - } - - pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); - sysclockfreq = (uint32_t)(float_t)((float_t)pllvco / (float_t)pllr); - } - - return sysclockfreq; -} - -/** - * @brief Return the HCLK frequency. - * @note Each time HCLK changes, this function must be called to update the - * right HCLK value. Otherwise, any configuration based on this function will be incorrect. - * - * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency. - * @retval HCLK frequency in Hz - */ -uint32_t HAL_RCC_GetHCLKFreq(void) -{ - SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos]; - return SystemCoreClock; -} - -/** - * @brief Return the PCLK1 frequency. - * @note Each time PCLK1 changes, this function must be called to update the - * right PCLK1 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK1 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK1Freq(void) -{ - /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE1) >> RCC_CFGR2_PPRE1_Pos]); -} - -/** - * @brief Return the PCLK2 frequency. - * @note Each time PCLK2 changes, this function must be called to update the - * right PCLK2 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK2 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK2Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR2 & RCC_CFGR2_PPRE2) >> RCC_CFGR2_PPRE2_Pos]); -} - -/** - * @brief Return the PCLK3 frequency. - * @note Each time PCLK3 changes, this function must be called to update the - * right PCLK3 value. Otherwise, any configuration based on this function will be incorrect. - * @retval PCLK3 frequency in Hz - */ -uint32_t HAL_RCC_GetPCLK3Freq(void) -{ - /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/ - return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR3 & RCC_CFGR3_PPRE3) >> RCC_CFGR3_PPRE3_Pos]); -} -/** - * @brief Get the pRCC_OscInitStruct according to the internal - * RCC configuration registers. - * @param pRCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that - * will be configured. - * @retval None - */ -void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *pRCC_OscInitStruct) -{ - uint32_t regval; - uint32_t reg1val; - uint32_t reg2val; - - /* Check the parameters */ - assert_param(pRCC_OscInitStruct != (void *)NULL); - - /* Set all possible values for the Oscillator type parameter ---------------*/ - pRCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_MSI | \ - RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_HSI48; - - /* Get Control register */ - regval = RCC->CR; - - /* Get the HSE configuration -----------------------------------------------*/ - pRCC_OscInitStruct->HSEState = (regval & (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_HSEEXT)); - - /* Get the MSI configuration -----------------------------------------------*/ - pRCC_OscInitStruct->MSIState = regval & RCC_CR_MSISON; - - reg1val = RCC->ICSCR1; - reg2val = RCC->ICSCR2; - - pRCC_OscInitStruct->MSIClockRange = (uint32_t)((reg1val & RCC_ICSCR1_MSISRANGE)); - if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_12) - { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM3) >> \ - RCC_ICSCR2_MSITRIM3_Pos); - } - else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_8) - { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM2) >> \ - RCC_ICSCR2_MSITRIM2_Pos); - } - else if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_4) - { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM1) >> \ - RCC_ICSCR2_MSITRIM1_Pos); - } - else /*if (pRCC_OscInitStruct->MSIClockRange >= RCC_MSIRANGE_0)*/ - { - pRCC_OscInitStruct->MSICalibrationValue = (uint32_t)((reg2val & RCC_ICSCR2_MSITRIM0) >> \ - RCC_ICSCR2_MSITRIM0_Pos); - } - - - /* Get the HSI configuration -----------------------------------------------*/ - pRCC_OscInitStruct->HSIState = regval & RCC_CR_HSION; - pRCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR3 & RCC_ICSCR3_HSITRIM) >> RCC_ICSCR3_HSITRIM_Pos); - - /* Get BDCR register */ - regval = RCC->BDCR; - - /* Get the LSE configuration -----------------------------------------------*/ - pRCC_OscInitStruct->LSEState = (regval & (RCC_BDCR_LSEON | RCC_BDCR_LSEBYP | RCC_BDCR_LSESYSEN)); - - /* Get the LSI configuration -----------------------------------------------*/ - pRCC_OscInitStruct->LSIState = regval & RCC_BDCR_LSION; - - /* Get Control register */ - regval = RCC->CR; - - /* Get the HSI48 configuration ---------------------------------------------*/ - pRCC_OscInitStruct->HSI48State = regval & RCC_CR_HSI48ON; - - /* Get the PLL configuration -----------------------------------------------*/ - if ((regval & RCC_CR_PLL1ON) == RCC_CR_PLL1ON) - { - pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON; - } - else - { - pRCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF; - } - - reg1val = RCC->PLL1CFGR; - reg2val = RCC->PLL1DIVR; - - pRCC_OscInitStruct->PLL.PLLSource = (uint32_t)(reg1val & RCC_PLL1CFGR_PLL1SRC); - pRCC_OscInitStruct->PLL.PLLM = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLN = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1N) >> RCC_PLL1DIVR_PLL1N_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLQ = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLR = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLP = (uint32_t)(((reg2val & RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + 1U); - pRCC_OscInitStruct->PLL.PLLRGE = (uint32_t)((reg1val & RCC_PLL1CFGR_PLL1RGE)); - pRCC_OscInitStruct->PLL.PLLFRACN = (uint32_t)(((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ - RCC_PLL1FRACR_PLL1FRACN_Pos)); - pRCC_OscInitStruct->PLL.PLLMBOOST = (uint32_t)(((reg1val & RCC_PLL1CFGR_PLL1MBOOST) >> \ - RCC_PLL1CFGR_PLL1MBOOST_Pos)); -} - -/** - * @brief Configure the pRCC_ClkInitStruct according to the internal - * RCC configuration registers. - * @param pRCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that - * will be configured. - * @param pFLatency Pointer on the Flash Latency. - * @retval None - */ -void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *pRCC_ClkInitStruct, uint32_t *pFLatency) -{ - /* Check the parameters */ - assert_param(pRCC_ClkInitStruct != (void *)NULL); - assert_param(pFLatency != (void *)NULL); - - /* Set all possible values for the Clock type parameter --------------------*/ - pRCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | \ - RCC_CLOCKTYPE_PCLK2 | RCC_CLOCKTYPE_PCLK3; - - /* Get the SYSCLK configuration --------------------------------------------*/ - pRCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR1 & RCC_CFGR1_SW); - - /* Get the HCLK configuration ----------------------------------------------*/ - pRCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_HPRE); - - /* Get the APB1 configuration ----------------------------------------------*/ - pRCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR2 & RCC_CFGR2_PPRE1); - - /* Get the APB2 configuration ----------------------------------------------*/ - pRCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR2 & RCC_CFGR2_PPRE2) >> 4); - - /* Get the APB3 configuration ----------------------------------------------*/ - pRCC_ClkInitStruct->APB3CLKDivider = (uint32_t)(RCC->CFGR3 & RCC_CFGR3_PPRE3); - - /* Get the Flash Wait State (Latency) configuration ------------------------*/ - *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); -} - -/** - * @brief Get and clear reset flags - * @note Once reset flags are retrieved, this API is clearing them in order - * to isolate next reset reason. - * @retval can be a combination of @ref RCC_Reset_Flag - */ -uint32_t HAL_RCC_GetResetSource(void) -{ - uint32_t reset; - - /* Get all reset flags */ - reset = RCC->CSR & RCC_RESET_FLAG_ALL; - - /* Clear Reset flags */ - RCC->CSR |= RCC_CSR_RMVF; - - return reset; -} - -/** - * @brief Enable the Clock Security System. - * @note If a failure is detected on the HSE oscillator clock, this oscillator - * is automatically disabled and an interrupt is generated to inform the - * software about the failure (Clock Security System Interrupt, CSSI), - * allowing the MCU to perform rescue operations. The CSSI is linked to - * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector. - * @note The Clock Security System can only be cleared by reset. - * @retval None - */ -void HAL_RCC_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Handle the RCC Clock Security System interrupt request. - * @note This API should be called under the NMI_Handler(). - * @retval None - */ -void HAL_RCC_NMI_IRQHandler(void) -{ - /* Check RCC CSSF interrupt flag */ - if (__HAL_RCC_GET_IT(RCC_IT_CSS)) - { - /* Clear RCC CSS pending bit */ - __HAL_RCC_CLEAR_IT(RCC_IT_CSS); - - /* RCC Clock Security System interrupt user callback */ - HAL_RCC_CSSCallback(); - } -} - -/** - * @brief RCC Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCC_CSSCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_RCC_CSSCallback should be implemented in the user file - */ -} - -/** - * @} - */ -/** @defgroup RCC_Exported_Functions_Group3 Attributes management functions - * @brief Attributes management functions. - * -@verbatim - =============================================================================== - ##### RCC attributes functions ##### - =============================================================================== -@endverbatim - * @{ - */ -/** - * @brief Configure the RCC item attribute(s). - * @note Available attributes are to secure items and set RCC as privileged. - * @param Item Item(s) to set attributes on. - * This parameter can be a one or a combination of @ref RCC_items - * @param Attributes specifies the RCC secure/privilege attributes. - * This parameter can be a value of @ref RCC_attributes - * @retval None - */ -void HAL_RCC_ConfigAttributes(uint32_t Item, uint32_t Attributes) -{ - /* Check the parameters */ - assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); - assert_param(IS_RCC_ATTRIBUTES(Attributes)); - - switch (Attributes) - { -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Secure Privilege attribute */ - case RCC_SEC_PRIV: - SET_BIT(RCC->SECCFGR, Item); - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); - break; - /* Secure Non-Privilege attribute */ - case RCC_SEC_NPRIV: - SET_BIT(RCC->SECCFGR, Item); - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_SPRIV); - break; - /* Non-secure Privilege attribute */ - case RCC_NSEC_PRIV: - CLEAR_BIT(RCC->SECCFGR, Item); - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); - break; - /* Non-secure Non-Privilege attribute */ - case RCC_NSEC_NPRIV: - CLEAR_BIT(RCC->SECCFGR, Item); - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); - break; -#else - /* Non-secure Privilege attribute */ - case RCC_NSEC_PRIV: - SET_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); - break; - /* Non-secure Non-Privilege attribute */ - case RCC_NSEC_NPRIV: - CLEAR_BIT(RCC->PRIVCFGR, RCC_PRIVCFGR_NSPRIV); - break; -#endif /* __ARM_FEATURE_CMSE */ - default: - /* Nothing to do */ - break; - } -} -/** - * @} - */ - -/** - * @brief Get the attribute of a RCC item. - * @note Secure and non-secure attributes are only available from secure state - * when the system implements the security (TZEN=1) - * @param Item Single item to get secure/non-secure and privilege/non-privilege attribute from. - * This parameter can be a one value of @ref RCC_items except RCC_ALL. - * @param pAttributes pointer to return the attributes. - * @retval HAL Status. - */ -HAL_StatusTypeDef HAL_RCC_GetConfigAttributes(uint32_t Item, uint32_t *pAttributes) -{ - uint32_t attributes; - - /* Check null pointer */ - if (pAttributes == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_RCC_ITEM_ATTRIBUTES(Item)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - - /* Check item security */ - if ((RCC->SECCFGR & Item) == Item) - { - /* Get Secure privileges attribute */ - attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_SPRIV) == 0U) ? RCC_SEC_NPRIV : RCC_SEC_PRIV; - } - else - { - /* Get Non-Secure privileges attribute */ - attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; - } -#else - /* Get Non-Secure privileges attribute */ - attributes = ((RCC->PRIVCFGR & RCC_PRIVCFGR_NSPRIV) == 0U) ? RCC_NSEC_NPRIV : RCC_NSEC_PRIV; -#endif /* __ARM_FEATURE_CMSE */ - - /* return value */ - *pAttributes = attributes; - - return HAL_OK; -} -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup RCC_Private_Functions - * @{ - */ -/** - * @brief Update number of Flash wait states in line with MSI range and current - voltage range. - * @param msirange MSI range value from RCC_MSIRANGE_0 to RCC_MSIRANGE_15 - * @retval HAL status - */ -static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t msirange) -{ - uint32_t vos; - uint32_t latency; /* default value 0WS */ - - if (__HAL_RCC_PWR_IS_CLK_ENABLED()) - { - vos = HAL_PWREx_GetVoltageRange(); - } - else - { - __HAL_RCC_PWR_CLK_ENABLE(); - vos = HAL_PWREx_GetVoltageRange(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - - if ((vos == PWR_REGULATOR_VOLTAGE_SCALE1) || (vos == PWR_REGULATOR_VOLTAGE_SCALE2)) - { - - if (msirange < RCC_MSIRANGE_1) - { - /* MSI = 48Mhz */ - latency = FLASH_LATENCY_1; /* 1WS */ - } - else - { - /* MSI < 48Mhz */ - latency = FLASH_LATENCY_0; /* 0WS */ - } - } - else - { - if (msirange < RCC_MSIRANGE_1) - { - /* MSI = 48Mhz */ - if (vos == PWR_REGULATOR_VOLTAGE_SCALE3) - { - latency = FLASH_LATENCY_3; /* 3WS */ - } - else - { - return HAL_ERROR; - } - } - else - { - if (msirange > RCC_MSIRANGE_2) - { - if (vos == PWR_REGULATOR_VOLTAGE_SCALE4) - { - if (msirange > RCC_MSIRANGE_3) - { - latency = FLASH_LATENCY_0; /* 1WS */ - } - else - { - latency = FLASH_LATENCY_1; /* 0WS */ - } - } - else - { - latency = FLASH_LATENCY_0; /* 0WS */ - } - } - else - { - if (msirange == RCC_MSIRANGE_1) - { - if (vos == PWR_REGULATOR_VOLTAGE_SCALE3) - { - latency = FLASH_LATENCY_1; /* 1WS */ - } - else - { - latency = FLASH_LATENCY_2; /* 2WS */ - } - } - else - { - latency = FLASH_LATENCY_1; /* 1WS */ - } - } - } - } - - __HAL_FLASH_SET_LATENCY(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - if ((FLASH->ACR & FLASH_ACR_LATENCY) != latency) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @} - */ -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c deleted file mode 100644 index 1b4e04338..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_rcc_ex.c +++ /dev/null @@ -1,4321 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_rcc_ex.c - * @author MCD Application Team - * @brief Extended RCC HAL module driver. - * This file provides firmware functions to manage the following - * functionalities RCC extended peripheral: - * + Extended Peripheral Control functions - * + Extended Clock management functions - * + Extended Clock Recovery System Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup RCCEx RCCEx - * @brief RCC Extended HAL module driver - * @{ - */ - -#ifdef HAL_RCC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup RCCEx_Private_Constants RCCEx Private Constants - * @{ - */ -#define PLL1_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define PLL2_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ -#define PLL3_TIMEOUT_VALUE 2UL /* 2 ms (minimum Tick + 1) */ - -/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ -#if defined (STM32U585xx) || defined (STM32U575xx) -#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the LSE CSS interrupt Line */ -#else -#define RCC_EXTI_LINE_LSECSS EXTI_IMR1_IM24 /*!< External interrupt line 24 connected to the LSE CSS interrupt Line */ -#endif /* STM32U585xx || STM32U575xx */ - -/* Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. */ -#define RCC_EXTI_LINE_MSIPLLUNLCK EXTI_IMR1_IM23 /*!< External interrupt line 23 connected to the MSI PLL UNLOCK interrupt Line */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCCEx_Private_Macros - * @{ - */ - -#define IS_RCC_PLL2CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) - -#define IS_RCC_PLL3CLOCKOUT_VALUE(VALUE) ((0x00010000U <= (VALUE)) && ((VALUE) <= 0x00070000U)) - -#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LSCOSOURCE_LSE)) - -#define IS_RCC_MSIPLLMODE_SELECT(__SOURCE__) (((__SOURCE__) == RCC_MSISPLL_MODE_SEL) || \ - ((__SOURCE__) == RCC_MSIKPLL_MODE_SEL)) - -#define IS_RCC_PERIPHCLOCK(__SELECTION__) ((((__SELECTION__) & RCC_PERIPHCLOCK_ALL) != 0x00u) && \ - (((__SELECTION__) & ~RCC_PERIPHCLOCK_ALL) == 0x00u)) - -#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE)) - -#if defined(USART2) -#define IS_RCC_USART2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE)) -#endif /* USART2 */ - -#define IS_RCC_USART3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART3CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_USART3CLKSOURCE_LSE)) - -#define IS_RCC_UART4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_UART4CLKSOURCE_LSE)) - -#define IS_RCC_UART5CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_UART5CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_UART5CLKSOURCE_LSE)) - -#if defined(USART6) -#define IS_RCC_USART6CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USART6CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_USART6CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_USART6CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_USART6CLKSOURCE_LSE)) -#endif /* USART6 */ - -#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK3) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_LPUART1CLKSOURCE_MSIK)) - -#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_I2C1CLKSOURCE_MSIK)) - -#define IS_RCC_I2C2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_I2C2CLKSOURCE_MSIK)) - -#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK3) || \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK ) || \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI ) || \ - ((__SOURCE__) == RCC_I2C3CLKSOURCE_MSIK)) - -#define IS_RCC_I2C4CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C4CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_I2C4CLKSOURCE_MSIK)) - -#if defined(I2C5) -#define IS_RCC_I2C5CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C5CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C5CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C5CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_I2C5CLKSOURCE_MSIK)) -#endif /* I2C5 */ - -#if defined(I2C6) -#define IS_RCC_I2C6CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_I2C6CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_I2C6CLKSOURCE_SYSCLK)|| \ - ((__SOURCE__) == RCC_I2C6CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_I2C6CLKSOURCE_MSIK)) -#endif /* I2C6 */ - -#define IS_RCC_SAI1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL3) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI)) - -#if defined(SAI2) -#define IS_RCC_SAI2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL3) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_SAI2CLKSOURCE_HSI)) -#endif /* SAI2 */ - -#define IS_RCC_LPTIM1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_MSIK) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM1CLKSOURCE_LSE)) - -#define IS_RCC_LPTIM2CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) - -#define IS_RCC_LPTIM34CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_LPTIM34CLKSOURCE_MSIK) || \ - ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_LPTIM34CLKSOURCE_LSE)) - -#define IS_RCC_FDCAN1CLK(__SOURCE__) \ - (((__SOURCE__) == RCC_FDCAN1CLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_FDCAN1CLKSOURCE_PLL2)) - -#define IS_RCC_SDMMCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SDMMCCLKSOURCE_CLK48) || \ - ((__SOURCE__) == RCC_SDMMCCLKSOURCE_PLL1)) - -#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48_DIV2) || \ - ((__SOURCE__) == RCC_RNGCLKSOURCE_HSI)) - -#if defined(SAES) -#define IS_RCC_SAESCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI) || \ - ((__SOURCE__) == RCC_SAESCLKSOURCE_SHSI_DIV2)) -#endif /* SAES */ - -#define IS_RCC_ADCDACCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADCDACCLKSOURCE_HCLK) || \ - ((__SOURCE__) == RCC_ADCDACCLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_ADCDACCLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_ADCDACCLKSOURCE_HSI) || \ - ((__SOURCE__) == RCC_ADCDACCLKSOURCE_MSIK)) - -#define IS_RCC_MDF1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_MDF1CLKSOURCE_HCLK) || \ - ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_MDF1CLKSOURCE_PLL3) || \ - ((__SOURCE__) == RCC_MDF1CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_MDF1CLKSOURCE_MSIK)) - -#define IS_RCC_ADF1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_ADF1CLKSOURCE_HCLK) || \ - ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_ADF1CLKSOURCE_PLL3) || \ - ((__SOURCE__) == RCC_ADF1CLKSOURCE_PIN) || \ - ((__SOURCE__) == RCC_ADF1CLKSOURCE_MSIK)) - -#define IS_RCC_OSPICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_OSPICLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_MSIK) || \ - ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL1) ||\ - ((__SOURCE__) == RCC_OSPICLKSOURCE_PLL2)) - -#if defined(HSPI1) -#define IS_RCC_HSPICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_HSPICLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_HSPICLKSOURCE_PLL3)) -#endif /* HSPI1 */ - -#define IS_RCC_ICLKCLKSOURCE(__SOURCE__)\ - (((__SOURCE__) == RCC_ICLK_CLKSOURCE_HSI48)|| \ - ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL2) || \ - ((__SOURCE__) == RCC_ICLK_CLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_ICLK_CLKSOURCE_MSIK)) - -#define IS_RCC_SPI1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SPI1CLKSOURCE_PCLK2) || \ - ((__SOURCE__) == RCC_SPI1CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_SPI1CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_SPI1CLKSOURCE_MSIK)) - -#define IS_RCC_SPI2CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SPI2CLKSOURCE_PCLK1) || \ - ((__SOURCE__) == RCC_SPI2CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_SPI2CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_SPI2CLKSOURCE_MSIK)) - -#define IS_RCC_SPI3CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_SPI3CLKSOURCE_PCLK3) || \ - ((__SOURCE__) == RCC_SPI3CLKSOURCE_SYSCLK) || \ - ((__SOURCE__) == RCC_SPI3CLKSOURCE_HSI)|| \ - ((__SOURCE__) == RCC_SPI3CLKSOURCE_MSIK)) - -#define IS_RCC_DAC1CLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DAC1CLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_DAC1CLKSOURCE_LSI)) - -#define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \ - ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV32)) - -#if defined(LTDC) - -#define IS_RCC_LTDCCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL3) || \ - ((__SOURCE__) == RCC_LTDCCLKSOURCE_PLL2)) - -#endif /* LTDC */ - -#if defined(DSI) - -#define IS_RCC_DSICLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_DSICLKSOURCE_PLL3) || \ - ((__SOURCE__) == RCC_DSICLKSOURCE_DSIPHY)) - -#endif /* DSI */ - -#if defined(USB_OTG_HS) - -#define IS_RCC_USBPHYCLKSOURCE(__SOURCE__) \ - (((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE) || \ - ((__SOURCE__) == RCC_USBPHYCLKSOURCE_HSE_DIV2) || \ - ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1) || \ - ((__SOURCE__) == RCC_USBPHYCLKSOURCE_PLL1_DIV2)) - -#endif /* USB_OTG_HS */ - -#if defined(CRS) - -#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ - ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ - ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) - -#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \ - ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128)) - -#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \ - ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING)) - -#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFFU)) - -#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFFU)) - -#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x7FU)) - -#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ - ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) - -#endif /* CRS */ - -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCCEx_Private_Functions RCCEx Private Functions - * @{ - */ -static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); -static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *Pll2); -static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *Pll3); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions - * @{ - */ - -/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Extended Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the RCC Clocks - frequencies. - [..] - (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to - select the RTC clock source; in this case the Backup domain will be reset in - order to modify the RTC Clock source, as consequence RTC registers (including - the backup registers) are set to their reset values. - -@endverbatim - * @{ - */ -/** - * @brief Initialize the RCC extended peripherals clocks according to the specified - * parameters in the RCC_PeriphCLKInitTypeDef. - * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * contains a field PeriphClockSelection which can be a combination of the following values: - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock - * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock - * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock - * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock - * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock - * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock - * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock - * @arg @ref RCC_PERIPHCLK_DSI DSI peripheral clock - * @arg @ref RCC_PERIPHCLK_USBPHY USBPHY peripheral clock - * - * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select - * the RTC clock source: in this case the access to Backup domain is enabled. - * - * @retval HAL status - * - * (*) value not defined in all devices. - */ -HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(const RCC_PeriphCLKInitTypeDef *pPeriphClkInit) -{ - uint32_t tmpregister; - uint32_t tickstart; - HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ - HAL_StatusTypeDef status = HAL_OK; /* Final status */ - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(pPeriphClkInit->PeriphClockSelection)); - - /*-------------------------- USART1 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) - { - /* Check the parameters */ - assert_param(IS_RCC_USART1CLKSOURCE(pPeriphClkInit->Usart1ClockSelection)); - - /* Configure the USART1 clock source */ - __HAL_RCC_USART1_CONFIG(pPeriphClkInit->Usart1ClockSelection); - } - -#if defined(USART2) - /*-------------------------- USART2 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) - { - /* Check the parameters */ - assert_param(IS_RCC_USART2CLKSOURCE(pPeriphClkInit->Usart2ClockSelection)); - - /* Configure the USART2 clock source */ - __HAL_RCC_USART2_CONFIG(pPeriphClkInit->Usart2ClockSelection); - } -#endif /* USART2 */ - - /*-------------------------- USART3 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) - { - /* Check the parameters */ - assert_param(IS_RCC_USART3CLKSOURCE(pPeriphClkInit->Usart3ClockSelection)); - - /* Configure the USART3 clock source */ - __HAL_RCC_USART3_CONFIG(pPeriphClkInit->Usart3ClockSelection); - } - - /*-------------------------- UART4 clock source configuration --------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) - { - /* Check the parameters */ - assert_param(IS_RCC_UART4CLKSOURCE(pPeriphClkInit->Uart4ClockSelection)); - - /* Configure the UART4 clock source */ - __HAL_RCC_UART4_CONFIG(pPeriphClkInit->Uart4ClockSelection); - } - - /*-------------------------- UART5 clock source configuration --------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) - { - /* Check the parameters */ - assert_param(IS_RCC_UART5CLKSOURCE(pPeriphClkInit->Uart5ClockSelection)); - - /* Configure the UART5 clock source */ - __HAL_RCC_UART5_CONFIG(pPeriphClkInit->Uart5ClockSelection); - } -#if defined(USART6) - /*-------------------------- USART6 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) - { - /* Check the parameters */ - assert_param(IS_RCC_USART6CLKSOURCE(pPeriphClkInit->Usart6ClockSelection)); - - /* Configure the USART6 clock source */ - __HAL_RCC_USART6_CONFIG(pPeriphClkInit->Usart6ClockSelection); - } -#endif /* USART6 */ - - /*-------------------------- LPUART1 clock source configuration ------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) - { - /* Check the parameters */ - assert_param(IS_RCC_LPUART1CLKSOURCE(pPeriphClkInit->Lpuart1ClockSelection)); - - /* Configure the LPUART1 clock source */ - __HAL_RCC_LPUART1_CONFIG(pPeriphClkInit->Lpuart1ClockSelection); - } - - /*-------------------------- I2C1 clock source configuration ---------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C1CLKSOURCE(pPeriphClkInit->I2c1ClockSelection)); - - /* Configure the I2C1 clock source */ - __HAL_RCC_I2C1_CONFIG(pPeriphClkInit->I2c1ClockSelection); - } - - /*-------------------------- I2C2 clock source configuration ---------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C2CLKSOURCE(pPeriphClkInit->I2c2ClockSelection)); - - /* Configure the I2C2 clock source */ - __HAL_RCC_I2C2_CONFIG(pPeriphClkInit->I2c2ClockSelection); - } - - /*-------------------------- I2C3 clock source configuration ---------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C3CLKSOURCE(pPeriphClkInit->I2c3ClockSelection)); - - /* Configure the I2C3 clock source */ - __HAL_RCC_I2C3_CONFIG(pPeriphClkInit->I2c3ClockSelection); - } - - /*-------------------------- I2C4 clock source configuration ---------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C4CLKSOURCE(pPeriphClkInit->I2c4ClockSelection)); - - /* Configure the I2C4 clock source */ - __HAL_RCC_I2C4_CONFIG(pPeriphClkInit->I2c4ClockSelection); - } - -#if defined(I2C5) - /*-------------------------- I2C5 clock source configuration ---------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C5) == RCC_PERIPHCLK_I2C5) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C5CLKSOURCE(pPeriphClkInit->I2c5ClockSelection)); - - /* Configure the I2C5 clock source */ - __HAL_RCC_I2C5_CONFIG(pPeriphClkInit->I2c5ClockSelection); - } -#endif /* I2C5 */ - -#if defined(I2C6) - /*-------------------------- I2C6 clock source configuration ---------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C6) == RCC_PERIPHCLK_I2C6) - { - /* Check the parameters */ - assert_param(IS_RCC_I2C6CLKSOURCE(pPeriphClkInit->I2c6ClockSelection)); - - /* Configure the I2C6 clock source */ - __HAL_RCC_I2C6_CONFIG(pPeriphClkInit->I2c6ClockSelection); - } -#endif /* I2C6 */ - - /*-------------------------- LPTIM1 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) - { - assert_param(IS_RCC_LPTIM1CLK(pPeriphClkInit->Lptim1ClockSelection)); - __HAL_RCC_LPTIM1_CONFIG(pPeriphClkInit->Lptim1ClockSelection); - } - - /*-------------------------- LPTIM2 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) - { - assert_param(IS_RCC_LPTIM2CLK(pPeriphClkInit->Lptim2ClockSelection)); - __HAL_RCC_LPTIM2_CONFIG(pPeriphClkInit->Lptim2ClockSelection); - } - - /*-------------------------- LPTIM34 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM34) == (RCC_PERIPHCLK_LPTIM34)) - { - assert_param(IS_RCC_LPTIM34CLK(pPeriphClkInit->Lptim34ClockSelection)); - __HAL_RCC_LPTIM34_CONFIG(pPeriphClkInit->Lptim34ClockSelection); - } - - /*-------------------------- SAI1 clock source configuration ---------------------*/ - if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI1CLK(pPeriphClkInit->Sai1ClockSelection)); - - switch (pPeriphClkInit->Sai1ClockSelection) - { - case RCC_SAI1CLKSOURCE_PLL1: /* PLL is used as clock source for SAI1*/ - /* Enable SAI Clock output generated from System PLL */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); - /* SAI1 clock source config set later after clock selection check */ - break; - - case RCC_SAI1CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI1*/ - /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - /* SAI1 clock source config set later after clock selection check */ - break; - - case RCC_SAI1CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI1*/ - /* PLL3 P input clock, parameters M, N & P configuration clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - /* SAI1 clock source config set later after clock selection check */ - break; - - case RCC_SAI1CLKSOURCE_PIN: /* External clock is used as source of SAI1 clock*/ - /* SAI1 clock source configuration done later after clock selection check */ - break; - - case RCC_SAI1CLKSOURCE_HSI: /* HSI is used as source of SAI1 clock*/ - /* SAI1 clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if (ret == HAL_OK) - { - /* Set the source of SAI1 clock*/ - __HAL_RCC_SAI1_CONFIG(pPeriphClkInit->Sai1ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#if defined(SAI2) - /*-------------------------- SAI2 clock source configuration ---------------------*/ - if ((((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2)) - { - /* Check the parameters */ - assert_param(IS_RCC_SAI2CLK(pPeriphClkInit->Sai2ClockSelection)); - - switch (pPeriphClkInit->Sai2ClockSelection) - { - case RCC_SAI2CLKSOURCE_PLL1: /* PLL is used as clock source for SAI2*/ - /* Enable SAI Clock output generated from System PLL */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PLL2: /* PLL2 is used as clock source for SAI2*/ - /* PLL2 P input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PLL3: /* PLL3 is used as clock source for SAI2*/ - /* PLL3 P input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - /* SAI2 clock source config set later after clock selection check */ - break; - - case RCC_SAI2CLKSOURCE_PIN: /* External clock is used as source of SAI2 clock*/ - /* SAI2 clock source configuration done later after clock selection check */ - break; - case RCC_SAI2CLKSOURCE_HSI: /* HSI is used as source of SAI2 clock*/ - /* SAI2 clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if (ret == HAL_OK) - { - /* Set the source of SAI2 clock*/ - __HAL_RCC_SAI2_CONFIG(pPeriphClkInit->Sai2ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } -#endif /* SAI2 */ - - /*-------------------------- ADCDAC clock source configuration ----------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADCDAC) == RCC_PERIPHCLK_ADCDAC) - { - /* Check the parameters */ - assert_param(IS_RCC_ADCDACCLKSOURCE(pPeriphClkInit->AdcDacClockSelection)); - - switch (pPeriphClkInit->AdcDacClockSelection) - { - case RCC_ADCDACCLKSOURCE_PLL2: - /* PLL2 input clock, parameters M, N,P, & R configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - break; - - case RCC_ADCDACCLKSOURCE_SYSCLK: - case RCC_ADCDACCLKSOURCE_HCLK: - case RCC_ADCDACCLKSOURCE_HSE: - case RCC_ADCDACCLKSOURCE_HSI: - case RCC_ADCDACCLKSOURCE_MSIK: - break; - default: - ret = HAL_ERROR; - break; - } - - if (ret == HAL_OK) - { - /* Configure the ADC1 interface clock source */ - __HAL_RCC_ADCDAC_CONFIG(pPeriphClkInit->AdcDacClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - - /*-------------------------- MDF1 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_MDF1) == RCC_PERIPHCLK_MDF1) - { - /* Check the parameters */ - assert_param(IS_RCC_MDF1CLKSOURCE(pPeriphClkInit->Mdf1ClockSelection)); - - switch (pPeriphClkInit->Mdf1ClockSelection) - { - case RCC_MDF1CLKSOURCE_PLL1: - /* Enable PLL1 Clock output generated from System PLL */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); - break; - case RCC_MDF1CLKSOURCE_PLL3: - /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - break; - case RCC_MDF1CLKSOURCE_HCLK: - break; - case RCC_MDF1CLKSOURCE_PIN: - break; - case RCC_MDF1CLKSOURCE_MSIK: - break; - default: - ret = HAL_ERROR; - break; - } - if (ret == HAL_OK) - { - /* Configure the MDF1 interface clock source */ - __HAL_RCC_MDF1_CONFIG(pPeriphClkInit->Mdf1ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - - /*-------------------------- ADF1 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADF1) == RCC_PERIPHCLK_ADF1) - { - /* Check the parameters */ - assert_param(IS_RCC_ADF1CLKSOURCE(pPeriphClkInit->Adf1ClockSelection)); - switch (pPeriphClkInit->Adf1ClockSelection) - { - case RCC_ADF1CLKSOURCE_PLL1: - /* Enable PLL1 Clock output generated from System PLL */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); - break; - case RCC_ADF1CLKSOURCE_PLL3: - /* PLL3 Q input clock, parameters M, N & Q configuration and clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - break; - case RCC_ADF1CLKSOURCE_HCLK: - break; - case RCC_ADF1CLKSOURCE_PIN: - break; - case RCC_ADF1CLKSOURCE_MSIK: - break; - default: - ret = HAL_ERROR; - break; - } - if (ret == HAL_OK) - { - /* Configure the ADF1 interface clock source */ - __HAL_RCC_ADF1_CONFIG(pPeriphClkInit->Adf1ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - - /*-------------------------- RTC clock source configuration ----------------------*/ - if ((pPeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) - { - FlagStatus pwrclkchanged = RESET; - /* Check for RTC Parameters used to output RTCCLK */ - assert_param(IS_RCC_RTCCLKSOURCE(pPeriphClkInit->RTCClockSelection)); - /* Enable Power Clock */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - /* Enable write access to Backup domain */ - SET_BIT(PWR->DBPR, PWR_DBPR_DBP); - - /* Wait for Backup domain Write protection disable */ - tickstart = HAL_GetTick(); - - while (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - - if (ret == HAL_OK) - { - /* Reset the Backup domain only if the RTC Clock source selection is modified from default */ - tmpregister = READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL); - - if ((tmpregister != RCC_RTCCLKSOURCE_NO_CLK) && (tmpregister != pPeriphClkInit->RTCClockSelection)) - { - /* Store the content of BDCR register before the reset of Backup Domain */ - tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); - /* RTC Clock selection can be changed only if the Backup Domain is reset */ - __HAL_RCC_BACKUPRESET_FORCE(); - __HAL_RCC_BACKUPRESET_RELEASE(); - /* Restore the Content of BDCR register */ - RCC->BDCR = tmpregister; - } - - /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ - if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSEON)) - { - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till LSE is ready */ - while (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) - { - ret = HAL_TIMEOUT; - break; - } - } - } - - if (ret == HAL_OK) - { - /* Apply new RTC clock source selection */ - __HAL_RCC_RTC_CONFIG(pPeriphClkInit->RTCClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - else - { - /* set overall return value */ - status = ret; - } - - /* Restore clock configuration if changed */ - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } - } - - /*-------------------------------------- ICLK Configuration -----------------------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ICLK) == RCC_PERIPHCLK_ICLK) - { - /* Check the parameters */ - assert_param(IS_RCC_ICLKCLKSOURCE(pPeriphClkInit->IclkClockSelection)); - - switch (pPeriphClkInit->IclkClockSelection) - { - case RCC_ICLK_CLKSOURCE_PLL2: - /* PLL2 input clock, parameters M, N,P,Q & R configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - break; - case RCC_ICLK_CLKSOURCE_PLL1: - /* Enable ICLK Clock output generated from System PLL */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - break; - case RCC_ICLK_CLKSOURCE_HSI48: - break; - case RCC_ICLK_CLKSOURCE_MSIK: - break; - default: - ret = HAL_ERROR; - break; - } - if (ret == HAL_OK) - { - /* Configure the CLK48 source */ - __HAL_RCC_CLK48_CONFIG(pPeriphClkInit->IclkClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - - /*------------------------------ RNG Configuration -------------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) - { - - /* Check the parameters */ - assert_param(IS_RCC_RNGCLKSOURCE(pPeriphClkInit->RngClockSelection)); - - switch (pPeriphClkInit->RngClockSelection) - { - case RCC_RNGCLKSOURCE_HSI48_DIV2: /* HSI48/2 is used as clock source for RNG*/ - /* RNG clock source configuration done later after clock selection check */ - break; - case RCC_RNGCLKSOURCE_HSI: /* HSI is used as clock source for RNG*/ - /* RNG clock source configuration done later after clock selection check */ - break; - case RCC_RNGCLKSOURCE_HSI48: - /* HSI48 oscillator is used as source of RNG clock */ - /* RNG clock source configuration done later after clock selection check */ - break; - default: - ret = HAL_ERROR; - break; - } - if (ret == HAL_OK) - { - /* Set the source of RNG clock*/ - __HAL_RCC_RNG_CONFIG(pPeriphClkInit->RngClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#if defined(SAES) - /*-------------------------- SAES clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAES) == RCC_PERIPHCLK_SAES) - { - /* Check the parameters */ - assert_param(IS_RCC_SAESCLKSOURCE(pPeriphClkInit->SaesClockSelection)); - - /* Configure the SAES clock source */ - __HAL_RCC_SAES_CONFIG(pPeriphClkInit->SaesClockSelection); - } -#endif /* SAES */ - - /*-------------------------- SDMMC1/2 clock source configuration -------------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC) == (RCC_PERIPHCLK_SDMMC)) - { - /* Check the parameters */ - assert_param(IS_RCC_SDMMCCLKSOURCE(pPeriphClkInit->SdmmcClockSelection)); - - if (pPeriphClkInit->SdmmcClockSelection == RCC_SDMMCCLKSOURCE_PLL1) - { - /* Enable PLL1 P CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); - } - - /* Configure the SDMMC1/2 clock source */ - __HAL_RCC_SDMMC_CONFIG(pPeriphClkInit->SdmmcClockSelection); - } - - /*-------------------------- SPI1 clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI1) == RCC_PERIPHCLK_SPI1) - { - /* Check the parameters */ - assert_param(IS_RCC_SPI1CLKSOURCE(pPeriphClkInit->Spi1ClockSelection)); - - /* Configure the SPI1 clock source */ - __HAL_RCC_SPI1_CONFIG(pPeriphClkInit->Spi1ClockSelection); - } - - /*-------------------------- SPI2 clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI2) == RCC_PERIPHCLK_SPI2) - { - /* Check the parameters */ - assert_param(IS_RCC_SPI2CLKSOURCE(pPeriphClkInit->Spi2ClockSelection)); - - /* Configure the SPI2 clock source */ - __HAL_RCC_SPI2_CONFIG(pPeriphClkInit->Spi2ClockSelection); - } - - /*-------------------------- SPI3 clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPI3) == RCC_PERIPHCLK_SPI3) - { - /* Check the parameters */ - assert_param(IS_RCC_SPI3CLKSOURCE(pPeriphClkInit->Spi3ClockSelection)); - - /* Configure the SPI3 clock source */ - __HAL_RCC_SPI3_CONFIG(pPeriphClkInit->Spi3ClockSelection); - } - - /*-------------------------- OctoSPIx clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_OSPI) == RCC_PERIPHCLK_OSPI) - { - /* Check the parameters */ - assert_param(IS_RCC_OSPICLKSOURCE(pPeriphClkInit->OspiClockSelection)); - - if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL1) - { - /* Enable PLL1 Q CLK output */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - } - if (pPeriphClkInit->OspiClockSelection == RCC_OSPICLKSOURCE_PLL2) - { - /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - } - if (ret == HAL_OK) - { - /* Configure the OctoSPI clock source */ - __HAL_RCC_OSPI_CONFIG(pPeriphClkInit->OspiClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#if defined(HSPI1) - /*-------------------------- HSPIx kernel clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_HSPI) == RCC_PERIPHCLK_HSPI) - { - - /* Check the parameters */ - assert_param(IS_RCC_HSPICLKSOURCE(pPeriphClkInit->HspiClockSelection)); - - switch (pPeriphClkInit->HspiClockSelection) - { - case RCC_HSPICLKSOURCE_SYSCLK: /* SYSCLK is used as clock source for HSPI kernel clock*/ - /* HSPI kernel clock source config set later after clock selection check */ - break; - - case RCC_HSPICLKSOURCE_PLL1: /* PLL1 is used as clock source for HSPI kernel clock*/ - /* Enable 48M2 Clock output generated from System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* HSPI kernel clock source config set later after clock selection check */ - break; - - case RCC_HSPICLKSOURCE_PLL2: /* PLL2 is used as clock source for HSPI kernel clock*/ - /* PLL2 input clock, parameters M, N & Q configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - /* HSPI kernel clock source config set later after clock selection check */ - break; - - case RCC_HSPICLKSOURCE_PLL3: /* PLL3 is used as clock source for HSPI kernel clock*/ - /* PLL3 input clock, parameters M, N & R configuration and clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - /* HSPI kernel clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if (ret == HAL_OK) - { - /* Set the source of HSPI kernel clock*/ - __HAL_RCC_HSPI_CONFIG(pPeriphClkInit->HspiClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } -#endif /* defined(HSPI1) */ - - /*-------------------------- FDCAN1 kernel clock source configuration -------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FDCAN1) == (RCC_PERIPHCLK_FDCAN1)) - { - assert_param(IS_RCC_FDCAN1CLK(pPeriphClkInit->Fdcan1ClockSelection)); - - switch (pPeriphClkInit->Fdcan1ClockSelection) - { - case RCC_FDCAN1CLKSOURCE_HSE: /* HSE is used as source of FDCAN1 kernel clock*/ - /* FDCAN1 kernel clock source config set later after clock selection check */ - break; - case RCC_FDCAN1CLKSOURCE_PLL1: /* PLL1 is used as clock source for FDCAN1 kernel clock*/ - /* Enable 48M2 Clock output generated from System PLL */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ); - /* FDCAN1 kernel clock source config set later after clock selection check */ - break; - case RCC_FDCAN1CLKSOURCE_PLL2: /* PLL2 is used as clock source for FDCAN1 kernel clock*/ - /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - /* FDCAN1 kernel clock source config set later after clock selection check */ - break; - default: - ret = HAL_ERROR; - break; - } - if (ret == HAL_OK) - { - /* Set the source of FDCAN1 kernel clock*/ - __HAL_RCC_FDCAN1_CONFIG(pPeriphClkInit->Fdcan1ClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - - /*-------------------------- DAC1 clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DAC1) == RCC_PERIPHCLK_DAC1) - { - - /* Check the parameters */ - assert_param(IS_RCC_DAC1CLKSOURCE(pPeriphClkInit->Dac1ClockSelection)); - - /* Configure the DAC1 clock source */ - __HAL_RCC_DAC1_CONFIG(pPeriphClkInit->Dac1ClockSelection); - } - -#if defined(LTDC) - - /*-------------------------- LTDC clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) - { - - /* Check the parameters */ - assert_param(IS_RCC_LTDCCLKSOURCE(pPeriphClkInit->LtdcClockSelection)); - - switch (pPeriphClkInit->LtdcClockSelection) - { - case RCC_LTDCCLKSOURCE_PLL2: /* PLL2 is used as clock source for LTDC clock*/ - /* PLL2 input clock, parameters M, N & P configuration and clock output (PLL2ClockOut) */ - ret = RCCEx_PLL2_Config(&(pPeriphClkInit->PLL2)); - /* LTDC clock source config set later after clock selection check */ - break; - - case RCC_LTDCCLKSOURCE_PLL3: /* PLL3 is used as clock source for LTDC clock*/ - /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - /* LTDC clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if (ret == HAL_OK) - { - /* Set the source of LTDC clock*/ - __HAL_RCC_LTDC_CONFIG(pPeriphClkInit->LtdcClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#endif /* defined(LTDC) */ - -#if defined(DSI) - - /*-------------------------- DSI clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DSI) == RCC_PERIPHCLK_DSI) - { - - /* Check the parameters */ - assert_param(IS_RCC_DSICLKSOURCE(pPeriphClkInit->DsiClockSelection)); - - if (pPeriphClkInit->DsiClockSelection == RCC_DSICLKSOURCE_PLL3) - { - /* PLL3 is used as clock source for DSI clock*/ - /* PLL3 input clock, parameters M, N & P configuration and clock output (PLL3ClockOut) */ - ret = RCCEx_PLL3_Config(&(pPeriphClkInit->PLL3)); - } - - if (ret == HAL_OK) - { - /* Set the source of DSI clock*/ - __HAL_RCC_DSI_CONFIG(pPeriphClkInit->DsiClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#endif /* defined(DSI) */ - -#if defined(USB_OTG_HS) - - /*-------------------------- USB PHY clock source configuration ----------------*/ - if (((pPeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USBPHY) == RCC_PERIPHCLK_USBPHY) - { - - /* Check the parameters */ - assert_param(IS_RCC_USBPHYCLKSOURCE(pPeriphClkInit->UsbPhyClockSelection)); - - switch (pPeriphClkInit->UsbPhyClockSelection) - { - case RCC_USBPHYCLKSOURCE_HSE: /* HSE is used as clock source for USB PHY clock*/ - case RCC_USBPHYCLKSOURCE_HSE_DIV2: /* HSE div 2 is used as clock source for USB PHY clock*/ - /* USB-PHY clock source config set later after clock selection check */ - break; - - case RCC_USBPHYCLKSOURCE_PLL1: /* PLL1 P divider clock selected as USB PHY clock */ - case RCC_USBPHYCLKSOURCE_PLL1_DIV2: /* PLL1 P divider clock div 2 selected as USB PHY clock */ - /* Enable P Clock output generated from System PLL . */ - __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP); - /* USB-PHY clock source config set later after clock selection check */ - break; - - default: - ret = HAL_ERROR; - break; - } - - if (ret == HAL_OK) - { - /* Set the source of USBPHY clock*/ - __HAL_RCC_USBPHY_CONFIG(pPeriphClkInit->UsbPhyClockSelection); - } - else - { - /* set overall return value */ - status = ret; - } - } - -#endif /* defined(USB_OTG_HS) */ - - return status; -} - - -/** - * @brief Get the RCC_ClkInitStruct according to the internal RCC configuration registers. - * @param pPeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that - * returns the configuration information for the Extended Peripherals - * clocks(USART1, USART2, USART3, UART4, UART5, LPUART, I2C1, I2C2, I2C3, LPTIM1, LPTIM2, SAI1, SAI2, - * ADC1, ADC2, MDF1, MDF2, RTC, CLK48, SDMMC1, I2C4, SPI12, SPI3, OSPI, FDCAN1, DAC1). - * @retval None - */ -void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *pPeriphClkInit) -{ - /* Set all possible values for the extended clock type parameter------------*/ -#if (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) - pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ - RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ - RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_LTDC | \ - RCC_PERIPHCLK_DSI | RCC_PERIPHCLK_USBPHY; -#elif (defined(STM32U595xx) || defined(STM32U5A5xx)) - pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_USART6 | \ - RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \ - RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_I2C5 | RCC_PERIPHCLK_I2C6 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | RCC_PERIPHCLK_ADCDAC | \ - RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | \ - RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | \ - RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | \ - RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | \ - RCC_PERIPHCLK_DAC1 | RCC_PERIPHCLK_HSPI | RCC_PERIPHCLK_USBPHY; -#elif (defined(STM32U585xx) || defined(STM32U575xx)) - pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \ - RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | \ - RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | \ - RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 | \ - RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | RCC_PERIPHCLK_ADF1 | \ - RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | RCC_PERIPHCLK_SDMMC | \ - RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | RCC_PERIPHCLK_SPI1 | \ - RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_OSPI | \ - RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; - -#else - pPeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART3 | RCC_PERIPHCLK_UART4 | \ - RCC_PERIPHCLK_UART5 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | \ - RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_LPTIM1 | \ - RCC_PERIPHCLK_LPTIM34 | RCC_PERIPHCLK_LPTIM2 | \ - RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_MDF1 | \ - RCC_PERIPHCLK_ADF1 | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_ICLK | \ - RCC_PERIPHCLK_SDMMC | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_I2C4 | \ - RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3 | \ - RCC_PERIPHCLK_OSPI | RCC_PERIPHCLK_FDCAN1 | RCC_PERIPHCLK_DAC1; -#endif /* (defined(STM32U599xx) || defined(STM32U5A9xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx)) */ - -#if defined(SAES) - pPeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAES; -#endif /* SAES */ - - /* Get the PLL2 Clock configuration -----------------------------------------------*/ - pPeriphClkInit->PLL2.PLL2Source = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC) >> RCC_PLL2CFGR_PLL2SRC_Pos); - pPeriphClkInit->PLL2.PLL2M = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; - pPeriphClkInit->PLL2.PLL2N = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) >> RCC_PLL2DIVR_PLL2N_Pos) + 1U; - pPeriphClkInit->PLL2.PLL2P = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + 1U; - pPeriphClkInit->PLL2.PLL2Q = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + 1U; - pPeriphClkInit->PLL2.PLL2R = (uint32_t)((RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + 1U; - pPeriphClkInit->PLL2.PLL2RGE = (uint32_t)((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2RGE) >> RCC_PLL2CFGR_PLL2RGE_Pos); - pPeriphClkInit->PLL2.PLL2FRACN = (uint32_t)((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ - RCC_PLL2FRACR_PLL2FRACN_Pos); - - /* Get the PLL3 Clock configuration -----------------------------------------------*/ - pPeriphClkInit->PLL3.PLL3Source = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC) >> RCC_PLL3CFGR_PLL3SRC_Pos); - pPeriphClkInit->PLL3.PLL3M = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U; - pPeriphClkInit->PLL3.PLL3N = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) >> RCC_PLL3DIVR_PLL3N_Pos) + 1U; - pPeriphClkInit->PLL3.PLL3P = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + 1U; - pPeriphClkInit->PLL3.PLL3Q = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + 1U; - pPeriphClkInit->PLL3.PLL3R = (uint32_t)((RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + 1U; - pPeriphClkInit->PLL3.PLL3RGE = (uint32_t)((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3RGE) >> RCC_PLL3CFGR_PLL3RGE_Pos); - pPeriphClkInit->PLL3.PLL3FRACN = (uint32_t)((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ - RCC_PLL3FRACR_PLL3FRACN_Pos); - - /* Get the USART1 clock source ---------------------------------------------*/ - pPeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); - -#if defined(USART2) - /* Get the USART2 clock source ---------------------------------------------*/ - pPeriphClkInit->Usart2ClockSelection = __HAL_RCC_GET_USART2_SOURCE(); -#endif /* USART2 */ - - /* Get the USART3 clock source ---------------------------------------------*/ - pPeriphClkInit->Usart3ClockSelection = __HAL_RCC_GET_USART3_SOURCE(); - - /* Get the UART4 clock source ----------------------------------------------*/ - pPeriphClkInit->Uart4ClockSelection = __HAL_RCC_GET_UART4_SOURCE(); - - /* Get the UART5 clock source ----------------------------------------------*/ - pPeriphClkInit->Uart5ClockSelection = __HAL_RCC_GET_UART5_SOURCE(); - - /* Get the LPUART1 clock source --------------------------------------------*/ - pPeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); - -#if defined(USART6) - /* Get the UART6 clock source ---------------------------------------------*/ - pPeriphClkInit->Usart6ClockSelection = __HAL_RCC_GET_USART6_SOURCE(); -#endif /* defined(USART6) */ - - /* Get the I2C1 clock source -----------------------------------------------*/ - pPeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); - - /* Get the I2C2 clock source -----------------------------------------------*/ - pPeriphClkInit->I2c2ClockSelection = __HAL_RCC_GET_I2C2_SOURCE(); - - /* Get the I2C3 clock source -----------------------------------------------*/ - pPeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); - - /* Get the I2C4 clock source -----------------------------------------------*/ - pPeriphClkInit->I2c4ClockSelection = __HAL_RCC_GET_I2C4_SOURCE(); - -#if defined(I2C5) - /* Get the clock source ---------------------------------------------*/ - pPeriphClkInit->I2c5ClockSelection = __HAL_RCC_GET_I2C5_SOURCE(); -#endif /* defined(I2C5) */ - -#if defined(I2C6) - /* Get the clock source ---------------------------------------------*/ - pPeriphClkInit->I2c6ClockSelection = __HAL_RCC_GET_I2C6_SOURCE(); -#endif /* defined(I2C6) */ - - /* Get the LPTIM1 clock source ---------------------------------------------*/ - pPeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); - - /* Get the LPTIM2 clock source ---------------------------------------------*/ - pPeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); - - /* Get the LPTIM34 clock source --------------------------------------------*/ - pPeriphClkInit->Lptim34ClockSelection = __HAL_RCC_GET_LPTIM34_SOURCE(); - - /* Get the FDCAN1 clock source ---------------------------------------------*/ - pPeriphClkInit->Fdcan1ClockSelection = __HAL_RCC_GET_FDCAN1_SOURCE(); - - /* Get the MDF1 clock source -----------------------------------------------*/ - pPeriphClkInit->Mdf1ClockSelection = __HAL_RCC_GET_MDF1_SOURCE(); - - /* Get the ADF1 clock source -----------------------------------------------*/ - pPeriphClkInit->Adf1ClockSelection = __HAL_RCC_GET_ADF1_SOURCE(); - -#if defined(SAES) - /* Get the SAES clock source -----------------------------------------------*/ - pPeriphClkInit->SaesClockSelection = __HAL_RCC_GET_SAES_SOURCE(); -#endif /* SAES */ - - /* Get the SAI1 clock source -----------------------------------------------*/ - pPeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); - -#if defined(SAI2) - /* Get the SAI2 clock source -----------------------------------------------*/ - pPeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE(); -#endif /* SAI2 */ - - /* Get the CLK48 clock source ----------------------------------------------*/ - pPeriphClkInit->IclkClockSelection = __HAL_RCC_GET_ICLK_SOURCE(); - - /* Get the SDMMC clock source ----------------------------------------------*/ - pPeriphClkInit->SdmmcClockSelection = __HAL_RCC_GET_SDMMC_SOURCE(); - - /* Get the ADCDAC clock source ---------------------------------------------*/ - pPeriphClkInit->AdcDacClockSelection = __HAL_RCC_GET_ADCDAC_SOURCE(); - - /* Get the DAC1 clock source -----------------------------------------------*/ - pPeriphClkInit->Dac1ClockSelection = __HAL_RCC_GET_DAC1_SOURCE(); - - /* Get the OSPI clock source -----------------------------------------------*/ - pPeriphClkInit->OspiClockSelection = __HAL_RCC_GET_OSPI_SOURCE(); - - /* Get the SPI1 clock source -----------------------------------------------*/ - pPeriphClkInit->Spi1ClockSelection = __HAL_RCC_GET_SPI1_SOURCE(); - - /* Get the SPI2 clock source -----------------------------------------------*/ - pPeriphClkInit->Spi2ClockSelection = __HAL_RCC_GET_SPI2_SOURCE(); - - /* Get the SPI3 clock source -----------------------------------------------*/ - pPeriphClkInit->Spi3ClockSelection = __HAL_RCC_GET_SPI3_SOURCE(); - - /* Get the RTC clock source ------------------------------------------------*/ - pPeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); - - /* Get the RNG clock source ------------------------------------------------*/ - pPeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); - -#if defined(HSPI1) - /* Get the HSPI kernel clock source ------------------------------------------------*/ - pPeriphClkInit->HspiClockSelection = __HAL_RCC_GET_HSPI_SOURCE(); -#endif /* defined(HSPI1) */ - -#if defined(LTDC) - /* Get the LTDC clock source ------------------------------------------------*/ - pPeriphClkInit->LtdcClockSelection = __HAL_RCC_GET_LTDC_SOURCE(); -#endif /* defined(LTDC) */ - -#if defined(DSI) - /* Get the DSI clock source ------------------------------------------------*/ - pPeriphClkInit->DsiClockSelection = __HAL_RCC_GET_DSI_SOURCE(); -#endif /* defined(DSI) */ - -#if defined(USB_OTG_HS) - /* Get the USB PHY clock source ------------------------------------------------*/ - pPeriphClkInit->UsbPhyClockSelection = __HAL_RCC_GET_USBPHY_SOURCE(); -#endif /* defined(USB_OTG_HS) */ -} - -/** - * @brief Returns the PLL1 clock frequencies :PLL1_P_Frequency,PLL1_R_Frequency and PLL1_Q_Frequency - * @note The PLL1 clock frequencies computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note The function returns values based on HSE_VALUE, HSI_VALUE or MSI Value multiplied/divided by the PLL - * factors. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time PLL1CLK changes, this function must be called to update the - * right PLL1CLK value. Otherwise, any configuration based on this function will be incorrect. - * @param PLL1_Clocks structure. - * @retval None - */ -void HAL_RCCEx_GetPLL1ClockFreq(PLL1_ClocksTypeDef *PLL1_Clocks) -{ - uint32_t pll1source; - uint32_t pll1m; - uint32_t pll1n; - uint32_t pll1fracen; - float_t fracn1; - float_t pll1vco; - - pll1n = (RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N); - pll1source = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); - pll1m = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M) >> RCC_PLL1CFGR_PLL1M_Pos) + 1U; - pll1fracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN) >> RCC_PLL1CFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pll1fracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN) >> \ - RCC_PLL1FRACR_PLL1FRACN_Pos)); - - switch (pll1source) - { - - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pll1vco = ((float_t)HSI_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ - ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); - break; - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll1vco = ((float_t)HSE_VALUE / (float_t)pll1m) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + \ - (fracn1 / (float_t)0x2000) + (float_t)1); - break; - default: - pll1vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll1m) * \ - ((float_t)pll1n + (fracn1 / (float_t)0x2000) + (float_t)1); - break; - } - - if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVP) != 0U) - { - PLL1_Clocks->PLL1_P_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ - RCC_PLL1DIVR_PLL1P) >> RCC_PLL1DIVR_PLL1P_Pos) + \ - (float_t)1)); - } - else - { - PLL1_Clocks->PLL1_P_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVQ) != 0U) - { - PLL1_Clocks->PLL1_Q_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ - RCC_PLL1DIVR_PLL1Q) >> RCC_PLL1DIVR_PLL1Q_Pos) + \ - (float_t)1)); - } - else - { - PLL1_Clocks->PLL1_Q_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLLCLKOUT_CONFIG(RCC_PLL1_DIVR) != 0U) - { - PLL1_Clocks->PLL1_R_Frequency = (uint32_t)(float_t)(pll1vco / ((float_t)(uint32_t)((RCC->PLL1DIVR & \ - RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + \ - (float_t)1)); - } - else - { - PLL1_Clocks->PLL1_R_Frequency = 0U; - } - -} - -/** - * @brief Returns the PLL2 clock frequencies :PLL2_P_Frequency,PLL2_R_Frequency and PLL2_Q_Frequency - * @note The PLL2 clock frequencies computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL - * factors. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time PLL2CLK changes, this function must be called to update the - * right PLL2CLK value. Otherwise, any configuration based on this function will be incorrect. - * @param PLL2_Clocks structure. - * @retval None - */ -void HAL_RCCEx_GetPLL2ClockFreq(PLL2_ClocksTypeDef *PLL2_Clocks) -{ - uint32_t pll2source; - uint32_t pll2m; - uint32_t pll2n; - uint32_t pll2fracen; - float_t fracn2; - float_t pll2vco; - - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL2M) * PLL2N - PLL2xCLK = PLL2_VCO / PLL2x */ - pll2n = (RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N); - pll2source = (RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2SRC); - pll2m = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2M) >> RCC_PLL2CFGR_PLL2M_Pos) + 1U; - pll2fracen = ((RCC->PLL2CFGR & RCC_PLL2CFGR_PLL2FRACEN) >> RCC_PLL2CFGR_PLL2FRACEN_Pos); - fracn2 = (float_t)(uint32_t)(pll2fracen * ((RCC->PLL2FRACR & RCC_PLL2FRACR_PLL2FRACN) >> \ - RCC_PLL2FRACR_PLL2FRACN_Pos)); - - switch (pll2source) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pll2vco = ((float_t)HSI_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ - (fracn2 / (float_t)0x2000) + (float_t)1); - break; - - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll2m) * \ - ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll2vco = ((float_t)HSE_VALUE / (float_t)pll2m) * ((float_t)(uint32_t)(RCC->PLL2DIVR & RCC_PLL2DIVR_PLL2N) + \ - (fracn2 / (float_t)0x2000) + (float_t)1); - break; - - default: - pll2vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t) pll2m) \ - * ((float_t)pll2n + (fracn2 / (float_t)0x2000) + (float_t)1); - break; - } - if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVP) != 0U) - { - PLL2_Clocks->PLL2_P_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ - RCC_PLL2DIVR_PLL2P) >> RCC_PLL2DIVR_PLL2P_Pos) + \ - (float_t)1)); - } - else - { - PLL2_Clocks->PLL2_P_Frequency = 0U; - } - if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVQ) != 0U) - { - PLL2_Clocks->PLL2_Q_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ - RCC_PLL2DIVR_PLL2Q) >> RCC_PLL2DIVR_PLL2Q_Pos) + \ - (float_t)1)); - } - else - { - PLL2_Clocks->PLL2_Q_Frequency = 0U; - } - if (__HAL_RCC_GET_PLL2CLKOUT_CONFIG(RCC_PLL2_DIVR) != 0U) - { - PLL2_Clocks->PLL2_R_Frequency = (uint32_t)(float_t)(pll2vco / ((float_t)(uint32_t)((RCC->PLL2DIVR & \ - RCC_PLL2DIVR_PLL2R) >> RCC_PLL2DIVR_PLL2R_Pos) + \ - (float_t)1)); - } - else - { - PLL2_Clocks->PLL2_R_Frequency = 0U; - } -} - -/** - * @brief Returns the PLL3 clock frequencies :PLL3_P_Frequency,PLL3_R_Frequency and PLL3_Q_Frequency - * @note The PLL3 clock frequencies computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * @note The function returns values based on HSE_VALUE, HSI_VALUE or CSI Value multiplied/divided by the PLL - * factors. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * - * @note Each time PLL3CLK changes, this function must be called to update the - * right PLL3CLK value. Otherwise, any configuration based on this function will be incorrect. - * @param PLL3_Clocks structure. - * @retval None - */ -void HAL_RCCEx_GetPLL3ClockFreq(PLL3_ClocksTypeDef *PLL3_Clocks) -{ - uint32_t pll3source; - uint32_t pll3m; - uint32_t pll3n; - uint32_t pll3fracen; - float_t fracn3; - float_t pll3vco; - - /* PLL3_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLL3M) * PLL3N - PLL3xCLK = PLL3_VCO / PLLxR - */ - - pll3n = (RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N); - pll3source = (RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3SRC); - pll3m = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3M) >> RCC_PLL3CFGR_PLL3M_Pos) + 1U; - pll3fracen = ((RCC->PLL3CFGR & RCC_PLL3CFGR_PLL3FRACEN) >> RCC_PLL3CFGR_PLL3FRACEN_Pos); - fracn3 = (float_t)(uint32_t)(pll3fracen * ((RCC->PLL3FRACR & RCC_PLL3FRACR_PLL3FRACN) >> \ - RCC_PLL3FRACR_PLL3FRACN_Pos)); - - switch (pll3source) - { - case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - pll3vco = ((float_t)HSI_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ - (fracn3 / (float_t)0x2000) + (float_t)1); - - break; - case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ - pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ - ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); - break; - - case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pll3vco = ((float_t)HSE_VALUE / (float_t)pll3m) * ((float_t)(uint32_t)(RCC->PLL3DIVR & RCC_PLL3DIVR_PLL3N) + \ - (fracn3 / (float_t)0x2000) + (float_t)1); - break; - - default: - pll3vco = ((float_t)MSIRangeTable[(__HAL_RCC_GET_MSI_RANGE() >> RCC_ICSCR1_MSISRANGE_Pos)] / (float_t)pll3m) * \ - ((float_t)pll3n + (fracn3 / (float_t)0x2000) + (float_t)1); - break; - } - - if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVP) != 0U) - { - PLL3_Clocks->PLL3_P_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ - RCC_PLL3DIVR_PLL3P) >> RCC_PLL3DIVR_PLL3P_Pos) + \ - (float_t)1)); - } - else - { - PLL3_Clocks->PLL3_P_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVQ) != 0U) - { - PLL3_Clocks->PLL3_Q_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ - RCC_PLL3DIVR_PLL3Q) >> RCC_PLL3DIVR_PLL3Q_Pos) + \ - (float_t)1)); - } - else - { - PLL3_Clocks->PLL3_Q_Frequency = 0U; - } - - if (__HAL_RCC_GET_PLL3CLKOUT_CONFIG(RCC_PLL3_DIVR) != 0U) - { - PLL3_Clocks->PLL3_R_Frequency = (uint32_t)(float_t)(pll3vco / ((float_t)(uint32_t)((RCC->PLL3DIVR & \ - RCC_PLL3DIVR_PLL3R) >> RCC_PLL3DIVR_PLL3R_Pos) + \ - (float_t)1)); - } - else - { - PLL3_Clocks->PLL3_R_Frequency = 0U; - } - -} - -/** - * @brief Return the peripheral clock frequency for peripherals - * @note Return 0 if peripheral clock identifier not managed by this API - * @param PeriphClk Peripheral clock identifier - * This parameter can be one of the following values: - * @arg @ref RCC_PERIPHCLK_USART1 USART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART2 USART2 peripheral clock - * @arg @ref RCC_PERIPHCLK_USART3 USART3 peripheral clock - * @arg @ref RCC_PERIPHCLK_UART4 UART4 peripheral clock - * @arg @ref RCC_PERIPHCLK_UART5 UART5 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C1 I2C1 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C2 I2C2 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C4 I2C4 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI2 SPI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM2 LPTIM2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI1 SPI1 peripheral clock - * @arg @ref RCC_PERIPHCLK_FDCAN1 FDCAN1 peripheral clock - * @arg @ref RCC_PERIPHCLK_ICLK ICLK peripheral clock - * @arg @ref RCC_PERIPHCLK_MDF1 MDF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI1 SAI1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAI2 SAI2 peripheral clock - * @arg @ref RCC_PERIPHCLK_SAES SAES peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_RNG RNG peripheral clock - * @arg @ref RCC_PERIPHCLK_SDMMC SDMMC peripheral clock - * @arg @ref RCC_PERIPHCLK_USART6 USART6 peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_LTDC LTDC peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_OSPI OSPI peripheral clock - * @arg @ref RCC_PERIPHCLK_HSPI HSPI peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_I2C5 I2C5 peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_I2C6 I2C6 peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_USBPHY USB_OTG_HS peripheral clock (*) - * @arg @ref RCC_PERIPHCLK_LPUART1 LPUART1 peripheral clock - * @arg @ref RCC_PERIPHCLK_SPI3 SPI3 peripheral clock - * @arg @ref RCC_PERIPHCLK_I2C3 I2C3 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM34 LPTIM34 peripheral clock - * @arg @ref RCC_PERIPHCLK_LPTIM1 LPTIM1 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADCDAC ADC1 ADC2 ADC4 DAC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_DAC1 DAC1 peripheral clock - * @arg @ref RCC_PERIPHCLK_ADF1 ADF1 peripheral clock - * @arg @ref RCC_PERIPHCLK_RTC RTC peripheral clock - * @retval Frequency in Hz - * - * (*) value not defined in all devices. - */ -uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint64_t PeriphClk) -{ - PLL1_ClocksTypeDef pll1_clocks; - PLL2_ClocksTypeDef pll2_clocks; - PLL3_ClocksTypeDef pll3_clocks; - - uint32_t frequency; - uint32_t srcclk; - - /* Check the parameters */ - assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); - - if (PeriphClk == RCC_PERIPHCLK_RTC) - { - /* Get the current RTC source */ - srcclk = __HAL_RCC_GET_RTC_SOURCE(); - - /* Check if LSE is ready and if RTC clock selection is LSE */ - if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_RTCCLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if RTC clock selection is LSI */ - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_RTCCLKSOURCE_LSI)) - { - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) - { - frequency = LSI_VALUE / 128U; - } - else - { - frequency = LSI_VALUE; - } - } - /* Check if HSE is ready and if RTC clock selection is HSI_DIV32*/ - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_RTCCLKSOURCE_HSE_DIV32)) - { - frequency = HSE_VALUE / 32U; - } - /* Clock not enabled for RTC*/ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_SAI1) - { - srcclk = __HAL_RCC_GET_SAI1_SOURCE(); - - switch (srcclk) - { - case RCC_SAI1CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - break; - - case RCC_SAI1CLKSOURCE_PIN: - - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; - - case RCC_SAI1CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - default : - { - frequency = 0U; - break; - } - } - } -#if defined(SAI2) - else if (PeriphClk == RCC_PERIPHCLK_SAI2) - { - srcclk = __HAL_RCC_GET_SAI2_SOURCE(); - - switch (srcclk) - { - case RCC_SAI2CLKSOURCE_PLL1: /* PLL1P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PLL2: /* PLL2P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PLL3: /* PLLI3P is the clock source for SAI1 */ - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_P_Frequency; - break; - - case RCC_SAI2CLKSOURCE_PIN: - - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; - - case RCC_SAI2CLKSOURCE_HSI: /* HSI is the clock source for SAI1 */ - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - default : - - frequency = 0U; - break; - } - } -#endif /* SAI2 */ -#if defined(SAES) - else if (PeriphClk == RCC_PERIPHCLK_SAES) - { - /* Get the current SAES source */ - srcclk = __HAL_RCC_GET_SAES_SOURCE(); - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI)) - { - frequency = HSI_VALUE; - } - else if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY) && (srcclk == RCC_SAESCLKSOURCE_SHSI_DIV2)) - { - frequency = HSI_VALUE >> 1U; - } - /* Clock not enabled for SAES */ - else - { - frequency = 0U; - } - } -#endif /* SAES */ - else if (PeriphClk == RCC_PERIPHCLK_ICLK) - { - srcclk = __HAL_RCC_GET_ICLK_SOURCE(); - - switch (srcclk) - { - case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - - case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - - case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default : - - frequency = 0U; - break; - } - } - else if (PeriphClk == RCC_PERIPHCLK_SDMMC) - { - srcclk = __HAL_RCC_GET_SDMMC_SOURCE(); - if (srcclk == RCC_SDMMCCLKSOURCE_CLK48) - { - srcclk = __HAL_RCC_GET_ICLK_SOURCE(); - - switch (srcclk) - { - case RCC_ICLK_CLKSOURCE_PLL1: /* PLL1Q */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - } - case RCC_ICLK_CLKSOURCE_PLL2: /* PLL2Q */ - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - } - case RCC_ICLK_CLKSOURCE_HSI48: /* HSI48 */ - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) - { - frequency = HSI48_VALUE; - } - else - { - frequency = 0U; - } - break; - } - case RCC_ICLK_CLKSOURCE_MSIK: /* MSIK frequency range in HZ */ - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - } - default : - { - frequency = 0U; - break; - } - } - } - else if (srcclk == RCC_SDMMCCLKSOURCE_PLL1) - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - } - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_USART1) - { - /* Get the current USART1 source */ - srcclk = __HAL_RCC_GET_USART1_SOURCE(); - - if (srcclk == RCC_USART1CLKSOURCE_PCLK2) - { - frequency = HAL_RCC_GetPCLK2Freq(); - } - else if (srcclk == RCC_USART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART1 */ - else - { - frequency = 0U; - } - } -#if defined(USART2) - else if (PeriphClk == RCC_PERIPHCLK_USART2) - { - /* Get the current USART2 source */ - srcclk = __HAL_RCC_GET_USART2_SOURCE(); - - if (srcclk == RCC_USART2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_USART2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART2CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART2CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART2 */ - else - { - frequency = 0U; - } - } -#endif /* USART2 */ - else if (PeriphClk == RCC_PERIPHCLK_USART3) - { - /* Get the current USART3 source */ - srcclk = __HAL_RCC_GET_USART3_SOURCE(); - - if (srcclk == RCC_USART3CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_USART3CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART3CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART3CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for USART3 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_UART4) - { - /* Get the current UART4 source */ - srcclk = __HAL_RCC_GET_UART4_SOURCE(); - - if (srcclk == RCC_UART4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_UART4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART4CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART4CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART4 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_UART5) - { - /* Get the current UART5 source */ - srcclk = __HAL_RCC_GET_UART5_SOURCE(); - - if (srcclk == RCC_UART5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_UART5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_UART5CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_UART5CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART5 */ - else - { - frequency = 0U; - } - } -#if defined(USART6) - else if (PeriphClk == RCC_PERIPHCLK_USART6) - { - /* Get the current USART6 source */ - srcclk = __HAL_RCC_GET_USART6_SOURCE(); - - if (srcclk == RCC_USART6CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_USART6CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_USART6CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_USART6CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for UART5 */ - else - { - frequency = 0U; - } - } -#endif /* USART6 */ - else if (PeriphClk == RCC_PERIPHCLK_LPUART1) - { - /* Get the current LPUART1 source */ - srcclk = __HAL_RCC_GET_LPUART1_SOURCE(); - - if (srcclk == RCC_LPUART1CLKSOURCE_PCLK3) - { - frequency = HAL_RCC_GetPCLK3Freq(); - } - else if (srcclk == RCC_LPUART1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPUART1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_LPUART1CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for LPUART1 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_ADCDAC) - { - srcclk = __HAL_RCC_GET_ADCDAC_SOURCE(); - - if (srcclk == RCC_ADCDACCLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if (srcclk == RCC_ADCDACCLKSOURCE_PLL2) - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_R_Frequency; - } - else if (srcclk == RCC_ADCDACCLKSOURCE_HCLK) - { - frequency = HAL_RCC_GetHCLKFreq(); - } - else if (srcclk == RCC_ADCDACCLKSOURCE_MSIK) - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_ADCDACCLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for ADC */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_MDF1) - { - /* Get the current MDF1 source */ - srcclk = __HAL_RCC_GET_MDF1_SOURCE(); - - switch (srcclk) - { - case RCC_MDF1CLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_MDF1CLKSOURCE_PLL3: - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_Q_Frequency; - break; - - case RCC_MDF1CLKSOURCE_HCLK: - - frequency = HAL_RCC_GetHCLKFreq(); - break; - - case RCC_MDF1CLKSOURCE_PIN: - - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; - - case RCC_MDF1CLKSOURCE_MSIK: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default: - - frequency = 0U; - break; - } - } - else if (PeriphClk == RCC_PERIPHCLK_ADF1) - { - /* Get the current ADF1 source */ - srcclk = __HAL_RCC_GET_ADF1_SOURCE(); - - switch (srcclk) - { - case RCC_ADF1CLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - break; - - case RCC_ADF1CLKSOURCE_PLL3: - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_Q_Frequency; - break; - - case RCC_ADF1CLKSOURCE_HCLK: - - frequency = HAL_RCC_GetHCLKFreq(); - break; - - case RCC_ADF1CLKSOURCE_PIN: - - frequency = EXTERNAL_SAI1_CLOCK_VALUE; - break; - - case RCC_ADF1CLKSOURCE_MSIK: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default: - - frequency = 0U; - break; - } - } - else if (PeriphClk == RCC_PERIPHCLK_I2C1) - { - /* Get the current I2C1 source */ - srcclk = __HAL_RCC_GET_I2C1_SOURCE(); - - if (srcclk == RCC_I2C1CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C1CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C1CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for I2C1 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_I2C2) - { - /* Get the current I2C2 source */ - srcclk = __HAL_RCC_GET_I2C2_SOURCE(); - - if (srcclk == RCC_I2C2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C2CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C2CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C2CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for I2C2 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_I2C3) - { - /* Get the current I2C3 source */ - srcclk = __HAL_RCC_GET_I2C3_SOURCE(); - - switch (srcclk) - { - case RCC_I2C3CLKSOURCE_PCLK3: - { - frequency = HAL_RCC_GetPCLK3Freq(); - break; - } - case RCC_I2C3CLKSOURCE_HSI: - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - } - case RCC_I2C3CLKSOURCE_SYSCLK: - { - frequency = HAL_RCC_GetSysClockFreq(); - break; - } - case RCC_I2C3CLKSOURCE_MSIK: - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - } - default: - { - frequency = 0U; - break; - } - } - } - else if (PeriphClk == RCC_PERIPHCLK_I2C4) - { - /* Get the current I2C4 source */ - srcclk = __HAL_RCC_GET_I2C4_SOURCE(); - - if (srcclk == RCC_I2C4CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C4CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C4CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C4CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for I2C4 */ - else - { - frequency = 0U; - } - } -#if defined (I2C5) - else if (PeriphClk == RCC_PERIPHCLK_I2C5) - { - /* Get the current I2C5 source */ - srcclk = __HAL_RCC_GET_I2C5_SOURCE(); - - if (srcclk == RCC_I2C5CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C5CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C5CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C5CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for I2C5 */ - else - { - frequency = 0U; - } - } -#endif /* I2C5 */ -#if defined (I2C6) - else if (PeriphClk == RCC_PERIPHCLK_I2C6) - { - /* Get the current I2C6 source */ - srcclk = __HAL_RCC_GET_I2C6_SOURCE(); - - if (srcclk == RCC_I2C6CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if (srcclk == RCC_I2C6CLKSOURCE_SYSCLK) - { - frequency = HAL_RCC_GetSysClockFreq(); - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_I2C6CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) && (srcclk == RCC_I2C6CLKSOURCE_MSIK)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - /* Clock not enabled for I2C6 */ - else - { - frequency = 0U; - } - } -#endif /* I2C6 */ - else if (PeriphClk == RCC_PERIPHCLK_LPTIM34) - { - /* Get the current LPTIM34 source */ - srcclk = __HAL_RCC_GET_LPTIM34_SOURCE(); - - if (srcclk == RCC_LPTIM34CLKSOURCE_MSIK) - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSI)) - { - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) - { - frequency = LSI_VALUE / 128U; - } - else - { - frequency = LSI_VALUE; - } - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM34CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM34 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) - { - /* Get the current LPTIM1 source */ - srcclk = __HAL_RCC_GET_LPTIM1_SOURCE(); - - if (srcclk == RCC_LPTIM1CLKSOURCE_MSIK) - { - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSI)) - { - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) - { - frequency = LSI_VALUE / 128U; - } - else - { - frequency = LSI_VALUE; - } - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM1 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) - { - /* Get the current LPTIM2 source */ - srcclk = __HAL_RCC_GET_LPTIM2_SOURCE(); - - if (srcclk == RCC_LPTIM2CLKSOURCE_PCLK1) - { - frequency = HAL_RCC_GetPCLK1Freq(); - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSI)) - { - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) - { - frequency = LSI_VALUE / 128U; - } - else - { - frequency = LSI_VALUE; - } - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_LPTIM2CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Clock not enabled for LPTIM2 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_FDCAN1) - { - /* Get the current FDCAN1 kernel source */ - srcclk = __HAL_RCC_GET_FDCAN1_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_FDCAN1CLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL1) /* PLL1 ? */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - } - else if (srcclk == RCC_FDCAN1CLKSOURCE_PLL2) /* PLL2 ? */ - { - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_P_Frequency; - } - /* Clock not enabled for FDCAN1 */ - else - { - frequency = 0U; - } - } - else if (PeriphClk == RCC_PERIPHCLK_SPI1) - { - /* Get the current SPI1 kernel source */ - srcclk = __HAL_RCC_GET_SPI1_SOURCE(); - switch (srcclk) - { - case RCC_SPI1CLKSOURCE_PCLK2: - - frequency = HAL_RCC_GetPCLK2Freq(); - break; - - case RCC_SPI1CLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_SPI1CLKSOURCE_HSI: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_SPI1CLKSOURCE_MSIK: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default: - - frequency = 0U; - break; - } - } - else if (PeriphClk == RCC_PERIPHCLK_SPI2) - { - /* Get the current SPI2 kernel source */ - srcclk = __HAL_RCC_GET_SPI2_SOURCE(); - switch (srcclk) - { - case RCC_SPI2CLKSOURCE_PCLK1: - - frequency = HAL_RCC_GetPCLK1Freq(); - break; - - case RCC_SPI2CLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_SPI2CLKSOURCE_HSI: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_SPI2CLKSOURCE_MSIK: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default: - - frequency = 0U; - break; - } - } - else if (PeriphClk == RCC_PERIPHCLK_SPI3) - { - /* Get the current SPI3 kernel source */ - srcclk = __HAL_RCC_GET_SPI3_SOURCE(); - switch (srcclk) - { - case RCC_SPI3CLKSOURCE_PCLK3: - - frequency = HAL_RCC_GetPCLK3Freq(); - break; - - case RCC_SPI3CLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_SPI3CLKSOURCE_HSI: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) - { - frequency = HSI_VALUE; - } - else - { - frequency = 0U; - } - break; - - case RCC_SPI3CLKSOURCE_MSIK: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default: - - frequency = 0U; - break; - } - } - else if (PeriphClk == RCC_PERIPHCLK_OSPI) - { - /* Get the current OSPI kernel source */ - srcclk = __HAL_RCC_GET_OSPI_SOURCE(); - - switch (srcclk) - { - case RCC_OSPICLKSOURCE_PLL2: - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - - case RCC_OSPICLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - - case RCC_OSPICLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_OSPICLKSOURCE_MSIK: - - if (HAL_IS_BIT_SET(RCC->CR, RCC_CR_MSIKRDY)) - { - frequency = MSIRangeTable[(__HAL_RCC_GET_MSIK_RANGE() >> RCC_ICSCR1_MSIKRANGE_Pos)]; - } - else - { - frequency = 0U; - } - break; - - default: - - frequency = 0U; - break; - } - } -#if defined(HSPI1) - - else if (PeriphClk == RCC_PERIPHCLK_HSPI) - { - /* Get the current HSPI kernel source */ - srcclk = __HAL_RCC_GET_HSPI_SOURCE(); - - switch (srcclk) - { - case RCC_HSPICLKSOURCE_SYSCLK: - - frequency = HAL_RCC_GetSysClockFreq(); - break; - - case RCC_HSPICLKSOURCE_PLL1: - - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_Q_Frequency; - break; - - case RCC_HSPICLKSOURCE_PLL2: - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_Q_Frequency; - break; - case RCC_HSPICLKSOURCE_PLL3: - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_R_Frequency; - break; - - default: - - frequency = 0U; - break; - } - } -#endif /* defined(HSPI1) */ - else if (PeriphClk == RCC_PERIPHCLK_DAC1) - { - /* Get the current DAC1 kernel source */ - srcclk = __HAL_RCC_GET_DAC1_SOURCE(); - - /* Check if LSE is ready and if DAC1 clock selection is LSE */ - if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSERDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSE)) - { - frequency = LSE_VALUE; - } - /* Check if LSI is ready and if DAC1 clock selection is LSI */ - else if ((HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIRDY)) && (srcclk == RCC_DAC1CLKSOURCE_LSI)) - { - if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSIPREDIV)) - { - frequency = LSI_VALUE / 128U; - } - else - { - frequency = LSI_VALUE; - } - } - /* Clock not enabled for DAC1*/ - else - { - frequency = 0U; - } - - } - else if (PeriphClk == RCC_PERIPHCLK_RNG) - { - /* Get the current RNG kernel source */ - srcclk = __HAL_RCC_GET_RNG_SOURCE(); - - /* Check if HSI48 is ready and if RNG clock selection is HSI48 */ - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48)) - { - frequency = HSI48_VALUE; - } - - /* Check if HSI48 is ready and if RNG clock selection is HSI48_DIV2 */ - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSI48RDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI48_DIV2)) - { - frequency = HSI48_VALUE >> 1U ; - } - - /* Check if HSI is ready and if RNG clock selection is HSI */ - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSIRDY)) && (srcclk == RCC_RNGCLKSOURCE_HSI)) - { - frequency = HSI_VALUE; - } - /* Clock not enabled for RNG */ - else - { - frequency = 0U; - } - } -#if defined(LTDC) - else if (PeriphClk == RCC_PERIPHCLK_LTDC) - { - /* Get the current LTDC kernel source */ - srcclk = __HAL_RCC_GET_LTDC_SOURCE(); - - switch (srcclk) - { - case RCC_LTDCCLKSOURCE_PLL3: /* PLL3R is the clock source for LTDC */ - - HAL_RCCEx_GetPLL3ClockFreq(&pll3_clocks); - frequency = pll3_clocks.PLL3_R_Frequency; - break; - - case RCC_LTDCCLKSOURCE_PLL2: /* PLL2R is the clock source for LTDC */ - - HAL_RCCEx_GetPLL2ClockFreq(&pll2_clocks); - frequency = pll2_clocks.PLL2_R_Frequency; - break; - - default: - - frequency = 0U; - break; - } - } -#endif /* defined(LTDC) */ - -#if defined(USB_OTG_HS) - - else if (PeriphClk == RCC_PERIPHCLK_USBPHY) - { - /* Get the current USB_OTG_HS kernel source */ - srcclk = __HAL_RCC_GET_USBPHY_SOURCE(); - - if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE)) - { - frequency = HSE_VALUE; - } - else if ((HAL_IS_BIT_SET(RCC->CR, RCC_CR_HSERDY)) && (srcclk == RCC_USBPHYCLKSOURCE_HSE_DIV2)) - { - frequency = HSE_VALUE >> 1U ; - } - else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1) /* PLL1P */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = pll1_clocks.PLL1_P_Frequency; - } - else if (srcclk == RCC_USBPHYCLKSOURCE_PLL1_DIV2) /* PLL1P_DIV2 */ - { - HAL_RCCEx_GetPLL1ClockFreq(&pll1_clocks); - frequency = (pll1_clocks.PLL1_P_Frequency) / 2U; - } - /* Clock not enabled for USB_OTG_HS */ - else - { - frequency = 0U; - } - } -#endif /* defined(USB_OTG_HS) */ - - else - { - frequency = 0; - } - return (frequency); -} - - -/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions - * @brief Extended Clock management functions - * -@verbatim - =============================================================================== - ##### Extended clock management functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the - activation or deactivation of MSI PLL-mode, PLL2, PLL3, LSE CSS, - Low speed clock output and clock after wake-up from STOP mode. -@endverbatim - * @{ - */ - -/** - * @brief Enable PLL2. - * @param PLL2Init pointer to an RCC_PLL2InitTypeDef structure that - * contains the configuration information for the PLL2 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL2(const RCC_PLL2InitTypeDef *PLL2Init) -{ - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLL2 Parameters used to output PLL2CLK */ - assert_param(IS_RCC_PLLSOURCE(PLL2Init->PLL2Source)); - assert_param(IS_RCC_PLLM_VALUE(PLL2Init->PLL2M)); - assert_param(IS_RCC_PLLN_VALUE(PLL2Init->PLL2N)); - assert_param(IS_RCC_PLLP_VALUE(PLL2Init->PLL2P)); - assert_param(IS_RCC_PLLQ_VALUE(PLL2Init->PLL2Q)); - assert_param(IS_RCC_PLLR_VALUE(PLL2Init->PLL2R)); - assert_param(IS_RCC_PLL2CLOCKOUT_VALUE(PLL2Init->PLL2ClockOut)); - - /* Disable the PLL2 */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is ready to be updated */ - while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if (status == HAL_OK) - { - /* Make sure PLL2Source is ready */ - status = RCCEx_PLLSource_Enable(PLL2Init->PLL2Source); - - if (status == HAL_OK) - { - /* Configure the PLL2 clock source, multiplication factor N, */ - /* and division factors M, P, Q and R */ - __HAL_RCC_PLL2_CONFIG(PLL2Init->PLL2Source, PLL2Init->PLL2M, PLL2Init->PLL2N, - PLL2Init->PLL2P, PLL2Init->PLL2Q, PLL2Init->PLL2R); - - /* Disable PLL2FRACN */ - __HAL_RCC_PLL2FRACN_DISABLE(); - - /* Configure PLL PLL2FRACN */ - __HAL_RCC_PLL2FRACN_CONFIG(PLL2Init->PLL2FRACN); - - /* Enable PLL2FRACN */ - __HAL_RCC_PLL2FRACN_ENABLE(); - - /* Select PLL2 input reference frequency range: VCI */ - __HAL_RCC_PLL2_VCIRANGE(PLL2Init->PLL2RGE); - - /* Configure the PLL2 Clock output(s) */ - __HAL_RCC_PLL2CLKOUT_ENABLE(PLL2Init->PLL2ClockOut); - - /* Enable the PLL2 again by setting PLL2ON to 1*/ - __HAL_RCC_PLL2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is ready */ - while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - } - - return status; -} - -/** - * @brief Disable PLL2. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLL2(void) -{ - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the PLL2 */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is ready */ - while (READ_BIT(RCC->CR, RCC_CR_PLL2RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - /* To save power disable the PLL2 Source, FRACN and Clock outputs */ - CLEAR_BIT(RCC->PLL2CFGR, RCC_PLL2CFGR_PLL2PEN | RCC_PLL2CFGR_PLL2QEN | RCC_PLL2CFGR_PLL2REN | RCC_PLL2CFGR_PLL2SRC | \ - RCC_PLL2CFGR_PLL2FRACEN); - - return status; -} - -/** - * @brief Enable PLL3. - * @param PLL3Init pointer to an RCC_PLL3InitTypeDef structure that - * contains the configuration information for the PLL3 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnablePLL3(const RCC_PLL3InitTypeDef *PLL3Init) -{ - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - - /* check for PLL3 Parameters used to output PLL3CLK */ - assert_param(IS_RCC_PLLSOURCE(PLL3Init->PLL3Source)); - assert_param(IS_RCC_PLLM_VALUE(PLL3Init->PLL3M)); - assert_param(IS_RCC_PLLN_VALUE(PLL3Init->PLL3N)); - assert_param(IS_RCC_PLLP_VALUE(PLL3Init->PLL3P)); - assert_param(IS_RCC_PLL3CLOCKOUT_VALUE(PLL3Init->PLL3ClockOut)); - - /* Disable the PLL3 */ - __HAL_RCC_PLL3_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL3 is ready to be updated */ - while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - if (status == HAL_OK) - { - /* Make sure PLL3Source is ready */ - status = RCCEx_PLLSource_Enable(PLL3Init->PLL3Source); - - if (status == HAL_OK) - { - /* Configure the PLL3 clock source, multiplication factor N, */ - /* and division factors M and P */ - __HAL_RCC_PLL3_CONFIG(PLL3Init->PLL3Source, PLL3Init->PLL3M, PLL3Init->PLL3N, PLL3Init->PLL3P, PLL3Init->PLL3Q, \ - PLL3Init->PLL3R); - - /* Disable PLL3FRACN . */ - __HAL_RCC_PLL3FRACN_DISABLE(); - - /* Configure PLL PLL3FRACN */ - __HAL_RCC_PLL3FRACN_CONFIG(PLL3Init->PLL3FRACN); - - /* Enable PLL3FRACN . */ - __HAL_RCC_PLL3FRACN_ENABLE(); - - /* Select PLL3 input reference frequency range: VCI */ - __HAL_RCC_PLL3_VCIRANGE(PLL3Init->PLL3RGE); - - /* Configure the PLL3 Clock output(s) */ - __HAL_RCC_PLL3CLKOUT_ENABLE(PLL3Init->PLL3ClockOut); - - /* Enable the PLL3 again by setting PLL3ON to 1*/ - __HAL_RCC_PLL3_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL3 is ready */ - while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - } - - return status; -} - -/** - * @brief Disable PLL3. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisablePLL3(void) -{ - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - - /* Disable the PLL3 */ - __HAL_RCC_PLL3_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL3 is ready */ - while (READ_BIT(RCC->CR, RCC_CR_PLL3RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - - /* To save power disable the PLL3 Source and Clock outputs */ - CLEAR_BIT(RCC->PLL3CFGR, RCC_PLL3CFGR_PLL3PEN | RCC_PLL3CFGR_PLL3QEN | RCC_PLL3CFGR_PLL3REN | RCC_PLL3CFGR_PLL3SRC | \ - RCC_PLL3CFGR_PLL3FRACEN); - - return status; -} - -/** - * @brief Select which MSI output clock uses the PLL mode. - * @note Prior to disable PLL-mode (MSIPLLEN = 0) before call HAL_RCCEx_EnableMSIPLLModeSelection. - * @note The MSI kernel clock output uses the same oscillator source than the MSI system - * clock output, then the PLL mode is applied to the both clocks outputs. - * @param MSIPLLModeSelection specifies which MSI output clock uses the PLL mode. - * This parameter can be one of the following values: - * @arg @ref RCC_MSISPLL_MODE_SEL PLL mode applied to MSIS (MSI system) clock output - * @arg @ref RCC_MSIKPLL_MODE_SEL PLL mode applied to MSIK (MSI kernel) clock output - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLModeSelection(uint32_t MSIPLLModeSelection) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - assert_param(IS_RCC_MSIPLLMODE_SELECT(MSIPLLModeSelection)); - if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == 0U) - { - /* This bit is used only if PLL mode is disabled (MSIPLLEN = 0) */ - if (MSIPLLModeSelection == RCC_MSISPLL_MODE_SEL) - { - SET_BIT(RCC->CR, RCC_CR_MSIPLLSEL); - } - else - { - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLSEL); - } - status = HAL_OK; - } - - return status; -} - -/** - * @brief Enable the fast PLL mode start-up of the MSI clock - * @note Prior to enable PLL-mode (MSIPLLEN = 1) before call HAL_RCCEx_EnableMSIPLLFastStartup. - * @note The fast start-up feature is not active the first time the PLL mode is selected. The - * fast start-up is active when the MSI in PLL mode returns from switch off. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_EnableMSIPLLFastStartup(void) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) - { - /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */ - SET_BIT(RCC->CR, RCC_CR_MSIPLLFAST); - status = HAL_OK; - } - - return status; -} - -/** - * @brief Disable the fast PLL mode start-up of the MSI clock - * @note the MSI fast startup mode disabled only when PLL-mode is enabled - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RCCEx_DisableMSIPLLFastStartup(void) -{ - HAL_StatusTypeDef status = HAL_ERROR; - - if (READ_BIT(RCC->CR, RCC_CR_MSIPLLEN) == RCC_CR_MSIPLLEN) - { - /* This bit is used only if PLL mode is selected (MSIPLLEN = 1) */ - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLFAST); - status = HAL_OK; - } - return status; -} - -/** - * @brief Configure the oscillator clock source for wakeup from Stop and CSS backup clock. - * @param WakeUpClk Wakeup clock - * This parameter can be one of the following values: - * @arg @ref RCC_STOP_WAKEUPCLOCK_MSI MSI oscillator selection - * @arg @ref RCC_STOP_WAKEUPCLOCK_HSI HSI oscillator selection - * @note This function shall not be called after the Clock Security System on HSE has been - * enabled. - * @retval None - */ -void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk) -{ - assert_param(IS_RCC_STOP_WAKEUPCLOCK(WakeUpClk)); - - __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(WakeUpClk); -} - -/** - * @brief Configure the oscillator Kernel clock source for wakeup from Stop - * @param WakeUpClk: Kernel Wakeup clock - * This parameter can be one of the following values: - * @arg RCC_STOP_KERWAKEUPCLOCK_MSI: MSI oscillator selection - * @arg RCC_STOP_KERWAKEUPCLOCK_HSI: HSI oscillator selection - * @retval None - */ -void HAL_RCCEx_KerWakeUpStopCLKConfig(uint32_t WakeUpClk) -{ - assert_param(IS_RCC_STOP_KERWAKEUPCLOCK(WakeUpClk)); - - __HAL_RCC_KERWAKEUPSTOP_CLK_CONFIG(WakeUpClk); -} - -/** - * @brief Configure the MSI range after standby mode. - * @note After Standby its frequency can be selected between 3 possible values (1, 3.072 or 4 MHz). - * @param MSIRange MSI range - * This parameter can be one of the following values: - * @arg @ref RCC_MSIRANGE_4 Range 4 around 4 MHz (reset value) - * @arg @ref RCC_MSIRANGE_5 Range 5 around 2 MHz - * @arg @ref RCC_MSIRANGE_6 Range 6 around 1.33 MHz - * @arg @ref RCC_MSIRANGE_7 Range 7 around 1 MHz - * @arg @ref RCC_MSIRANGE_8 Range 8 around 3.072 MHz - * @retval None - */ -void HAL_RCCEx_StandbyMSIRangeConfig(uint32_t MSIRange) -{ - assert_param(IS_RCC_MSI_STANDBY_CLOCK_RANGE(MSIRange)); - - __HAL_RCC_MSI_STANDBY_RANGE_CONFIG(MSIRange); -} - -/** - * @brief Configure the MSIK range after standby mode. - * @note After Standby its frequency can be selected between 5 possible values (1, 1.33, 2, 3.072 or 4 MHz). - * @param MSIKRange MSIK range - * This parameter can be one of the following values: - * @arg @ref RCC_MSIKRANGE_4 Range 4 around 4 MHz (reset value) - * @arg @ref RCC_MSIKRANGE_5 Range 5 around 2 MHz - * @arg @ref RCC_MSIKRANGE_6 Range 6 around 1.33 MHz - * @arg @ref RCC_MSIKRANGE_7 Range 7 around 1 MHz - * @arg @ref RCC_MSIKRANGE_8 Range 8 around 3.072 MHz - * @retval None - */ -void HAL_RCCEx_StandbyMSIKRangeConfig(uint32_t MSIKRange) -{ - assert_param(IS_RCC_MSIK_STANDBY_CLOCK_RANGE(MSIKRange)); - - __HAL_RCC_MSIK_STANDBY_RANGE_CONFIG(MSIKRange); -} - -/** - * @brief Enable the LSE Clock Security System. - * @note Prior to enable the LSE Clock Security System, LSE oscillator is to be enabled - * with HAL_RCC_OscConfig() and the LSE oscillator clock is to be selected as RTC - * clock with HAL_RCCEx_PeriphCLKConfig(). - * @retval None - */ -void HAL_RCCEx_EnableLSECSS(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); -} - -/** - * @brief Disable the LSE Clock Security System. - * @note LSE Clock Security System can only be disabled after a LSE failure detection. - * @retval None - */ -void HAL_RCCEx_DisableLSECSS(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); -} - -/** - * @brief Enable the LSE Clock Security System Interrupt & corresponding EXTI line. - * @note LSE Clock Security System Interrupt is mapped on EXTI line - * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. - * @retval None - */ -void HAL_RCCEx_EnableLSECSS_IT(void) -{ - /* Enable LSE CSS */ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON) ; - - /* Enable IT on LSECSS EXTI Line */ - SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_LSECSS); - /* Enable the RCC LSECSS EXTI Interrupt Rising Edge */ - SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_LSECSS); -} - -/** - * @brief Handle the RCC LSE Clock Security System interrupt request. - * @note LSECSS EXTI is not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. - * @retval None - */ -void HAL_RCCEx_LSECSS_IRQHandler(void) -{ - uint32_t falling_edge_flag; - uint32_t rising_edge_flag; - - if (READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) != 0U) - { - /* Read Falling Edge flag on LSECSS EXTI interrupt */ - falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); - - /* Read Rising Edge flag on LSECSS EXTI interrupt */ - rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); - - /* Check Rising/falling Edge flag on LSECSS EXTI interrupt */ - if ((falling_edge_flag == RCC_EXTI_LINE_LSECSS) || \ - (rising_edge_flag == RCC_EXTI_LINE_LSECSS)) - { - if (rising_edge_flag == RCC_EXTI_LINE_LSECSS) - { - /* Clear the RCC LSECSS EXTI Rising Edge flag */ - WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_LSECSS); - } - if (falling_edge_flag == RCC_EXTI_LINE_LSECSS) - { - /* Clear the RCC LSECSS EXTI Falling Edge flag */ - WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_LSECSS); - } - } - /* RCC LSECSS interrupt user callback */ - HAL_RCCEx_LSECSS_Callback(); - } -} - -/** - * @brief RCCEx LSE Clock Security System interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_LSECSS_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_LSECSS_Callback should be implemented in the user file - */ -} - -/** - * @brief Enable the MSI PLL Unlock Interrupt & corresponding EXTI line. - * @note MSI PLL Unlock Interrupt is mapped on EXTI line - * Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. - * @retval None - */ -void HAL_RCCEx_EnableMSIPLLUNLCK_IT(void) -{ - /* Enable IT on MSI PLL Unlock EXTI Line */ - SET_BIT(EXTI->IMR1, RCC_EXTI_LINE_MSIPLLUNLCK); - /* Enable the RCC MSI PLL UNLOCK EXTI Interrupt Rising Edge */ - SET_BIT(EXTI->RTSR1, RCC_EXTI_LINE_MSIPLLUNLCK); -} - -/** - * @brief Handle the RCC MSI PLL Unlock interrupt request. - * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. - * @retval None - */ -void HAL_RCCEx_MSIPLLUNLCK_IRQHandler(void) -{ - uint32_t rising_edge_flag = READ_BIT(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); - uint32_t falling_edge_flag = READ_BIT(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); - - /* Check Rising/falling Edge flag on MSI PLL UNLOCK EXTI interrupt */ - if ((rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) || \ - (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK)) - { - if (rising_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) - { - /* Clear the RCC MSI PLL UNLOCK EXTI Rising Edge flag */ - WRITE_REG(EXTI->RPR1, RCC_EXTI_LINE_MSIPLLUNLCK); - } - if (falling_edge_flag == RCC_EXTI_LINE_MSIPLLUNLCK) - { - /* Clear the RCC MSI PLL UNLOCK EXTI Falling Edge flag */ - WRITE_REG(EXTI->FPR1, RCC_EXTI_LINE_MSIPLLUNLCK); - } - /* RCC MSI PLL Unlock interrupt user callback */ - HAL_RCCEx_MSIPLLUNLCK_Callback(); - } -} - -/** - * @brief RCCEx RCC MSI PLL Unlock interrupt callback. - * @note Not available in STM32U575/585 rev. X and and STM32U59x/5Ax rev. B/Y devices. - * @retval none - */ -__weak void HAL_RCCEx_MSIPLLUNLCK_Callback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_MSIPLLUNLCK_Callback should be implemented in the user file - */ -} - -/** - * @brief Select the Low Speed clock source to output on LSCO pin (PA2). - * @param LSCOSource specifies the Low Speed clock source to output. - * This parameter can be one of the following values: - * @arg @ref RCC_LSCOSOURCE_LSI LSI clock selected as LSCO source - * @arg @ref RCC_LSCOSOURCE_LSE LSE clock selected as LSCO source - * @retval None - */ -void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) -{ - FlagStatus pwrclkchanged = RESET; - FlagStatus backupchanged = RESET; - - /* Check the parameters */ - assert_param(IS_RCC_LSCOSOURCE(LSCOSource)); - - /* Update LSCOSEL clock source in Backup Domain control register */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, LSCOSource | RCC_BDCR_LSCOEN); - - if (backupchanged == SET) - { - HAL_PWR_DisableBkUpAccess(); - } - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } -} - -/** - * @brief Disable the Low Speed clock output. - * @retval None - */ -void HAL_RCCEx_DisableLSCO(void) -{ - FlagStatus pwrclkchanged = RESET; - FlagStatus backupchanged = RESET; - - /* Update LSCOEN bit in Backup Domain control register */ - if (__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - pwrclkchanged = SET; - } - if (HAL_IS_BIT_CLR(PWR->DBPR, PWR_DBPR_DBP)) - { - /* Enable access to the backup domain */ - HAL_PWR_EnableBkUpAccess(); - backupchanged = SET; - } - - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); - - /* Restore previous configuration */ - if (backupchanged == SET) - { - /* Disable access to the backup domain */ - HAL_PWR_DisableBkUpAccess(); - } - if (pwrclkchanged == SET) - { - __HAL_RCC_PWR_CLK_DISABLE(); - } -} - -/** - * @brief Enable the PLL-mode of the MSI. - * @note Prior to enable the PLL-mode of the MSI for automatic hardware - * calibration LSE oscillator is to be enabled with HAL_RCC_OscConfig(). - * @retval None - */ -void HAL_RCCEx_EnableMSIPLLMode(void) -{ - SET_BIT(RCC->CR, RCC_CR_MSIPLLEN); -} - -/** - * @brief Disable the PLL-mode of the MSI. - * @note PLL-mode of the MSI is automatically reset when LSE oscillator is disabled. - * @retval None - */ -void HAL_RCCEx_DisableMSIPLLMode(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_MSIPLLEN); -} -/** - * @} - */ - -#if defined(CRS) - -/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions - * @brief Extended Clock Recovery System Control functions - * -@verbatim - =============================================================================== - ##### Extended Clock Recovery System Control functions ##### - =============================================================================== - [..] - For devices with Clock Recovery System feature (CRS), RCC Extension HAL driver can be used as follows: - - (#) In System clock config, HSI48 needs to be enabled - - (#) Enable CRS clock in IP MSP init which will use CRS functions - - (#) Call CRS functions as follows: - (##) Prepare synchronization configuration necessary for HSI48 calibration - (+++) Default values can be set for frequency Error Measurement (reload and error limit) - and also HSI48 oscillator smooth trimming. - (+++) Macro __HAL_RCC_CRS_RELOADVALUE_CALCULATE can be also used to calculate - directly reload value with target and synchronization frequencies values - (##) Call function HAL_RCCEx_CRSConfig which - (+++) Resets CRS registers to their default values. - (+++) Configures CRS registers with synchronization configuration - (+++) Enables automatic calibration and frequency error counter feature - Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the - periodic USB SOF will not be generated by the host. No SYNC signal will therefore be - provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock - precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs - should be used as SYNC signal. - - (##) A polling function is provided to wait for complete synchronization - (+++) Call function HAL_RCCEx_CRSWaitSynchronization() - (+++) According to CRS status, user can decide to adjust again the calibration or continue - application if synchronization is OK - - (#) User can retrieve information related to synchronization in calling function - HAL_RCCEx_CRSGetSynchronizationInfo() - - (#) Regarding synchronization status and synchronization information, user can try a new calibration - in changing synchronization configuration and call again HAL_RCCEx_CRSConfig. - Note: When the SYNC event is detected during the downcounting phase (before reaching the zero value), - it means that the actual frequency is lower than the target (and so, that the TRIM value should be - incremented), while when it is detected during the upcounting phase it means that the actual frequency - is higher (and that the TRIM value should be decremented). - - (#) In interrupt mode, user can resort to the available macros (__HAL_RCC_CRS_XXX_IT). Interrupts will go - through CRS Handler (CRS_IRQn/CRS_IRQHandler) - (++) Call function HAL_RCCEx_CRSConfig() - (++) Enable CRS_IRQn (thanks to NVIC functions) - (++) Enable CRS interrupt (__HAL_RCC_CRS_ENABLE_IT) - (++) Implement CRS status management in the following user callbacks called from - HAL_RCCEx_CRS_IRQHandler(): - (+++) HAL_RCCEx_CRS_SyncOkCallback() - (+++) HAL_RCCEx_CRS_SyncWarnCallback() - (+++) HAL_RCCEx_CRS_ExpectedSyncCallback() - (+++) HAL_RCCEx_CRS_ErrorCallback() - - (#) To force a SYNC EVENT, user can use the function HAL_RCCEx_CRSSoftwareSynchronizationGenerate(). - This function can be called before calling HAL_RCCEx_CRSConfig (for instance in Systick handler) - -@endverbatim - * @{ - */ - -/** - * @brief Start automatic synchronization for polling mode - * @param pInit Pointer on RCC_CRSInitTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *const pInit) -{ - uint32_t value; - - /* Check the parameters */ - assert_param(IS_RCC_CRS_SYNC_DIV(pInit->Prescaler)); - assert_param(IS_RCC_CRS_SYNC_SOURCE(pInit->Source)); - assert_param(IS_RCC_CRS_SYNC_POLARITY(pInit->Polarity)); - assert_param(IS_RCC_CRS_RELOADVALUE(pInit->ReloadValue)); - assert_param(IS_RCC_CRS_ERRORLIMIT(pInit->ErrorLimitValue)); - assert_param(IS_RCC_CRS_HSI48CALIBRATION(pInit->HSI48CalibrationValue)); - - /* CONFIGURATION */ - - /* Before configuration, reset CRS registers to their default values*/ - __HAL_RCC_CRS_FORCE_RESET(); - __HAL_RCC_CRS_RELEASE_RESET(); - - /* Set the SYNCDIV[2:0] bits according to Prescaler value */ - /* Set the SYNCSRC[1:0] bits according to Source value */ - /* Set the SYNCSPOL bit according to Polarity value */ - value = (pInit->Prescaler | pInit->Source | pInit->Polarity); - /* Set the RELOAD[15:0] bits according to ReloadValue value */ - value |= pInit->ReloadValue; - /* Set the FELIM[7:0] bits according to ErrorLimitValue value */ - value |= (pInit->ErrorLimitValue << CRS_CFGR_FELIM_Pos); - WRITE_REG(CRS->CFGR, value); - - /* Adjust HSI48 oscillator smooth trimming */ - /* Set the TRIM[5:0] bits according to RCC_CRS_HSI48CalibrationValue value */ - MODIFY_REG(CRS->CR, CRS_CR_TRIM, (pInit->HSI48CalibrationValue << CRS_CR_TRIM_Pos)); - - /* START AUTOMATIC SYNCHRONIZATION*/ - - /* Enable Automatic trimming & Frequency error counter */ - SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN | CRS_CR_CEN); -} - -/** - * @brief Generate the software synchronization event - * @retval None - */ -void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void) -{ - SET_BIT(CRS->CR, CRS_CR_SWSYNC); -} - -/** - * @brief Return synchronization info - * @param pSynchroInfo Pointer on RCC_CRSSynchroInfoTypeDef structure - * @retval None - */ -void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo) -{ - /* Check the parameter */ - assert_param(pSynchroInfo != (void *) NULL); - - /* Get the reload value */ - pSynchroInfo->ReloadValue = (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); - - /* Get HSI48 oscillator smooth trimming */ - pSynchroInfo->HSI48CalibrationValue = (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); - - /* Get Frequency error capture */ - pSynchroInfo->FreqErrorCapture = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); - - /* Get Frequency error direction */ - pSynchroInfo->FreqErrorDirection = (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); -} - -/** - * @brief Wait for CRS Synchronization status. - * @param Timeout Duration of the timeout - * @note Timeout is based on the maximum time to receive a SYNC event based on synchronization - * frequency. - * @note If Timeout set to HAL_MAX_DELAY, HAL_TIMEOUT will be never returned. - * @retval Combination of Synchronization status - * This parameter can be a combination of the following values: - * @arg @ref RCC_CRS_TIMEOUT - * @arg @ref RCC_CRS_SYNCOK - * @arg @ref RCC_CRS_SYNCWARN - * @arg @ref RCC_CRS_SYNCERR - * @arg @ref RCC_CRS_SYNCMISS - * @arg @ref RCC_CRS_TRIMOVF - */ -uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout) -{ - uint32_t crsstatus = RCC_CRS_NONE; - uint32_t tickstart; - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait for CRS flag or timeout detection */ - do - { - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - crsstatus = RCC_CRS_TIMEOUT; - } - } - /* Check CRS SYNCOK flag */ - if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCOK)) - { - /* CRS SYNC event OK */ - crsstatus |= RCC_CRS_SYNCOK; - - /* Clear CRS SYNC event OK bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCOK); - } - - /* Check CRS SYNCWARN flag */ - if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCWARN)) - { - /* CRS SYNC warning */ - crsstatus |= RCC_CRS_SYNCWARN; - - /* Clear CRS SYNCWARN bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCWARN); - } - - /* Check CRS TRIM overflow flag */ - if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_TRIMOVF)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_TRIMOVF; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_TRIMOVF); - } - - /* Check CRS Error flag */ - if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCERR)) - { - /* CRS SYNC Error */ - crsstatus |= RCC_CRS_SYNCERR; - - /* Clear CRS Error bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCERR); - } - - /* Check CRS SYNC Missed flag */ - if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_SYNCMISS)) - { - /* CRS SYNC Missed */ - crsstatus |= RCC_CRS_SYNCMISS; - - /* Clear CRS SYNC Missed bit */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_SYNCMISS); - } - - /* Check CRS Expected SYNC flag */ - if (__HAL_RCC_CRS_GET_FLAG(RCC_CRS_FLAG_ESYNC)) - { - /* frequency error counter reached a zero value */ - __HAL_RCC_CRS_CLEAR_FLAG(RCC_CRS_FLAG_ESYNC); - } - } while (RCC_CRS_NONE == crsstatus); - - return crsstatus; -} - -/** - * @brief Handle the Clock Recovery System interrupt request. - * @retval None - */ -void HAL_RCCEx_CRS_IRQHandler(void) -{ - uint32_t crserror = RCC_CRS_NONE; - /* Get current IT flags and IT sources values */ - uint32_t itflags = READ_REG(CRS->ISR); - uint32_t itsources = READ_REG(CRS->CR); - - /* Check CRS SYNCOK flag */ - if (((itflags & RCC_CRS_FLAG_SYNCOK) != 0U) && ((itsources & RCC_CRS_IT_SYNCOK) != 0U)) - { - /* Clear CRS SYNC event OK flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); - - /* user callback */ - HAL_RCCEx_CRS_SyncOkCallback(); - } - /* Check CRS SYNCWARN flag */ - else if (((itflags & RCC_CRS_FLAG_SYNCWARN) != 0U) && ((itsources & RCC_CRS_IT_SYNCWARN) != 0U)) - { - /* Clear CRS SYNCWARN flag */ - WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); - - /* user callback */ - HAL_RCCEx_CRS_SyncWarnCallback(); - } - /* Check CRS Expected SYNC flag */ - else if (((itflags & RCC_CRS_FLAG_ESYNC) != 0U) && ((itsources & RCC_CRS_IT_ESYNC) != 0U)) - { - /* frequency error counter reached a zero value */ - WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); - - /* user callback */ - HAL_RCCEx_CRS_ExpectedSyncCallback(); - } - /* Check CRS Error flags */ - else - { - if (((itflags & RCC_CRS_FLAG_ERR) != 0U) && ((itsources & RCC_CRS_IT_ERR) != 0U)) - { - if ((itflags & RCC_CRS_FLAG_SYNCERR) != 0U) - { - crserror |= RCC_CRS_SYNCERR; - } - if ((itflags & RCC_CRS_FLAG_SYNCMISS) != 0U) - { - crserror |= RCC_CRS_SYNCMISS; - } - if ((itflags & RCC_CRS_FLAG_TRIMOVF) != 0U) - { - crserror |= RCC_CRS_TRIMOVF; - } - - /* Clear CRS Error flags */ - WRITE_REG(CRS->ICR, CRS_ICR_ERRC); - - /* user error callback */ - HAL_RCCEx_CRS_ErrorCallback(crserror); - } - } -} - -/** - * @brief RCCEx Clock Recovery System SYNCOK interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncOkCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncOkCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System SYNCWARN interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_SyncWarnCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_SyncWarnCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Expected SYNC interrupt callback. - * @retval none - */ -__weak void HAL_RCCEx_CRS_ExpectedSyncCallback(void) -{ - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ExpectedSyncCallback should be implemented in the user file - */ -} - -/** - * @brief RCCEx Clock Recovery System Error interrupt callback. - * @param Error Combination of Error status. - * This parameter can be a combination of the following values: - * @arg @ref RCC_CRS_SYNCERR - * @arg @ref RCC_CRS_SYNCMISS - * @arg @ref RCC_CRS_TRIMOVF - * @retval none - */ -__weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(Error); - - /* NOTE : This function should not be modified, when the callback is needed, - the @ref HAL_RCCEx_CRS_ErrorCallback should be implemented in the user file - */ -} - -/** - * @} - */ - -#endif /* CRS */ - -/** - * @} - */ - -/** @addtogroup RCCEx_Private_Functions - * @{ - */ -/** - * @brief Configure the PLL 1 source clock. - * @param PllSource PLL1 source clock it can be : - * RCC_PLLSOURCE_NONE - * RCC_PLLSOURCE_MSI - * RCC_PLLSOURCE_HSI - * RCC_PLLSOURCE_HSE - * - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) -{ - uint32_t tickstart; - HAL_StatusTypeDef status = HAL_OK; - - switch (PllSource) - { - case RCC_PLLSOURCE_MSI: - /* Check whether MSI in not ready and enable it */ - if (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) - { - /* Enable the Internal Multi Speed oscillator (MSI). */ - __HAL_RCC_MSI_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_MSISRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - break; - - case RCC_PLLSOURCE_HSI: - /* Check whether HSI in not ready and enable it */ - if (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - { - /* Enable the Internal High Speed oscillator (HSI) */ - __HAL_RCC_HSI_ENABLE(); - - /* Get timeout */ - tickstart = HAL_GetTick(); - - /* Wait till MSI is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - break; - - case RCC_PLLSOURCE_HSE: - /* Check whether HSE in not ready and enable it */ - if (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - { - /* Enable the External High Speed oscillator (HSE) */ - SET_BIT(RCC->CR, RCC_CR_HSEON); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till HSE is ready */ - while (READ_BIT(RCC->CR, RCC_CR_HSERDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) - { - status = HAL_TIMEOUT; - break; - } - } - } - break; - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Configure the PLL2 VCI ranges, multiplication and division factors and enable it - * @param pll2: Pointer to an RCC_PLL2InitTypeDef structure that - * contains the configuration parameters as well as VCI clock ranges. - * @note PLL2 is temporary disabled to apply new parameters - * - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLL2_Config(const RCC_PLL2InitTypeDef *pll2) -{ - - uint32_t tickstart; - assert_param(IS_RCC_PLLSOURCE(pll2->PLL2Source)); - assert_param(IS_RCC_PLLM_VALUE(pll2->PLL2M)); - assert_param(IS_RCC_PLLN_VALUE(pll2->PLL2N)); - assert_param(IS_RCC_PLLP_VALUE(pll2->PLL2P)); - assert_param(IS_RCC_PLLQ_VALUE(pll2->PLL2Q)); - assert_param(IS_RCC_PLLR_VALUE(pll2->PLL2R)); - - /* Disable PLL2 */ - __HAL_RCC_PLL2_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure PLL2 multiplication and division factors */ - __HAL_RCC_PLL2_CONFIG(pll2->PLL2Source, - pll2->PLL2M, - pll2->PLL2N, - pll2->PLL2P, - pll2->PLL2Q, - pll2->PLL2R); - - /* Select PLL2 input reference frequency range: VCI */ - __HAL_RCC_PLL2_VCIRANGE(pll2->PLL2RGE); - - /* Configure the PLL2 Clock output(s) */ - __HAL_RCC_PLL2CLKOUT_ENABLE(pll2->PLL2ClockOut); - - /* Disable PLL2FRACN */ - __HAL_RCC_PLL2FRACN_DISABLE(); - - /* Configures PLL2 clock Fractional Part Of The Multiplication Factor */ - __HAL_RCC_PLL2FRACN_CONFIG(pll2->PLL2FRACN); - - /* Enable PLL2FRACN */ - __HAL_RCC_PLL2FRACN_ENABLE(); - - /* Enable PLL2 */ - __HAL_RCC_PLL2_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL2 is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL2RDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > PLL2_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; - -} - -/** - * @brief Configure the PLL3 VCI ranges, multiplication and division factors and enable it - * @param pll3: Pointer to an RCC_PLL3InitTypeDef structure that - * contains the configuration parameters as well as VCI clock ranges. - * @note PLL3 is temporary disabled to apply new parameters - * @retval HAL status - */ -static HAL_StatusTypeDef RCCEx_PLL3_Config(const RCC_PLL3InitTypeDef *pll3) -{ - uint32_t tickstart; - assert_param(IS_RCC_PLLSOURCE(pll3->PLL3Source)); - assert_param(IS_RCC_PLLM_VALUE(pll3->PLL3M)); - assert_param(IS_RCC_PLLN_VALUE(pll3->PLL3N)); - assert_param(IS_RCC_PLLP_VALUE(pll3->PLL3P)); - assert_param(IS_RCC_PLLQ_VALUE(pll3->PLL3Q)); - assert_param(IS_RCC_PLLR_VALUE(pll3->PLL3R)); - - /* Disable PLL3 */ - __HAL_RCC_PLL3_DISABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) != 0U) - { - if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - - /* Configure PLL3 multiplication and division factors */ - __HAL_RCC_PLL3_CONFIG(pll3->PLL3Source, - pll3->PLL3M, - pll3->PLL3N, - pll3->PLL3P, - pll3->PLL3Q, - pll3->PLL3R); - - /* Select PLL3 input reference frequency range: VCI */ - __HAL_RCC_PLL3_VCIRANGE(pll3->PLL3RGE); - - /* Configure the PLL3 Clock output(s) */ - __HAL_RCC_PLL3CLKOUT_ENABLE(pll3->PLL3ClockOut); - - /* Disable PLL3FRACN */ - __HAL_RCC_PLL3FRACN_DISABLE(); - - /* Configures PLL3 clock Fractional Part Of The Multiplication Factor */ - __HAL_RCC_PLL3FRACN_CONFIG(pll3->PLL3FRACN); - - /* Enable PLL3FRACN */ - __HAL_RCC_PLL3FRACN_ENABLE(); - - /* Enable PLL3 */ - __HAL_RCC_PLL3_ENABLE(); - - /* Get Start Tick*/ - tickstart = HAL_GetTick(); - - /* Wait till PLL3 is ready */ - while (__HAL_RCC_GET_FLAG(RCC_FLAG_PLL3RDY) == 0U) - { - if ((HAL_GetTick() - tickstart) > PLL3_TIMEOUT_VALUE) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @} - */ - -#endif /* HAL_RCC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c deleted file mode 100644 index 58e66052e..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi.c +++ /dev/null @@ -1,3753 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_spi.c - * @author MCD Application Team - * @brief SPI HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Serial Peripheral Interface (SPI) peripheral: - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - The SPI HAL driver can be used as follows: - - (#) Declare a SPI_HandleTypeDef handle structure, for example: - SPI_HandleTypeDef hspi; - - (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit() API: - (##) Enable the SPIx interface clock - (##) SPI pins configuration - (+++) Enable the clock for the SPI GPIOs - (+++) Configure these SPI pins as alternate function push-pull - (##) NVIC configuration if you need to use interrupt process or DMA process - (+++) Configure the SPIx interrupt priority - (+++) Enable the NVIC SPI IRQ handle - (##) DMA Configuration if you need to use DMA process - (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Stream/Channel - (+++) Enable the DMAx clock - (+++) Configure the DMA handle parameters - (+++) Configure the DMA Tx or Rx Stream/Channel - (+++) Associate the initialized hdma_tx handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx - or Rx Stream/Channel - - (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS - management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. - - (#) Initialize the SPI registers by calling the HAL_SPI_Init() API: - (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc) - by calling the customized HAL_SPI_MspInit() API. - [..] - Callback registration: - - (#) The compilation flag USE_HAL_SPI_REGISTER_CALLBACKS when set to 1UL - allows the user to configure dynamically the driver callbacks. - Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. - - Function HAL_SPI_RegisterCallback() allows to register following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) SuspendCallback : SPI Suspend callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - - (#) Use function HAL_SPI_UnRegisterCallback to reset a callback to the default - weak function. - HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxCpltCallback : SPI Tx Completed callback - (+) RxCpltCallback : SPI Rx Completed callback - (+) TxRxCpltCallback : SPI TxRx Completed callback - (+) TxHalfCpltCallback : SPI Tx Half Completed callback - (+) RxHalfCpltCallback : SPI Rx Half Completed callback - (+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback - (+) ErrorCallback : SPI Error callback - (+) AbortCpltCallback : SPI Abort callback - (+) SuspendCallback : SPI Suspend callback - (+) MspInitCallback : SPI Msp Init callback - (+) MspDeInitCallback : SPI Msp DeInit callback - - By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the HAL_SPI_Init()/ HAL_SPI_DeInit() only when - these callbacks are null (not registered beforehand). - If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - - Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - Then, the user first registers the MspInit/MspDeInit user callbacks - using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() - or HAL_SPI_Init() function. - - When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or not defined, - the callback registering feature is not available and weak callbacks are used. - - SuspendCallback restriction: - SuspendCallback is called only when MasterReceiverAutoSusp is enabled and - EOT interrupt is activated. SuspendCallback is used in relation with functions - HAL_SPI_Transmit_IT, HAL_SPI_Receive_IT and HAL_SPI_TransmitReceive_IT. - - [..] - Circular mode restriction: - (+) The DMA circular mode cannot be used when the SPI is configured in these modes: - (++) Master 2Lines RxOnly - (++) Master 1Line Rx - (+) The CRC feature is not managed when the DMA circular mode is enabled - (+) The functions HAL_SPI_DMAPause()/ HAL_SPI_DMAResume() are not supported. Return always - HAL_ERROR with ErrorCode set to HAL_SPI_ERROR_NOT_SUPPORTED. - Those functions are maintained for backward compatibility reasons. - - @endverbatim - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup SPI SPI - * @brief SPI HAL module driver - * @{ - */ -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/** @defgroup SPI_Private_Constants SPI Private Constants - * @{ - */ -#define SPI_DEFAULT_TIMEOUT 100UL -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup SPI_Private_Functions SPI Private Functions - * @{ - */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma); -static void SPI_DMAError(DMA_HandleTypeDef *hdma); -static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, - FlagStatus FlagStatus, uint32_t Timeout, uint32_t Tickstart); -static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi); -static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi); -static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi); -static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi); -static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi); -static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi); -static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi); -static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi); -static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi); - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SPI_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This subsection provides a set of functions allowing to initialize and - de-initialize the SPIx peripheral: - - (+) User must implement HAL_SPI_MspInit() function in which he configures - all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). - - (+) Call the function HAL_SPI_Init() to configure the selected device with - the selected configuration: - (++) Mode - (++) Direction - (++) Data Size - (++) Clock Polarity and Phase - (++) NSS Management - (++) BaudRate Prescaler - (++) FirstBit - (++) TIMode - (++) CRC Calculation - (++) CRC Polynomial if CRC enabled - (++) CRC Length, used only with Data8 and Data16 - (++) FIFO reception threshold - (++) FIFO transmission threshold - - (+) Call the function HAL_SPI_DeInit() to restore the default configuration - of the selected SPIx peripheral. - -@endverbatim - * @{ - */ - -/** - * @brief Initialize the SPI according to the specified parameters - * in the SPI_InitTypeDef and initialize the associated handle. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi) -{ - uint32_t crc_length; - uint32_t packet_length; - - /* Check the SPI handle allocation */ - if (hspi == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - assert_param(IS_SPI_MODE(hspi->Init.Mode)); - assert_param(IS_SPI_DIRECTION(hspi->Init.Direction)); - if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) - { - assert_param(IS_SPI_LIMITED_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_LIMITED_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); - } - else - { - assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize)); - assert_param(IS_SPI_FIFOTHRESHOLD(hspi->Init.FifoThreshold)); - } - assert_param(IS_SPI_NSS(hspi->Init.NSS)); - assert_param(IS_SPI_NSSP(hspi->Init.NSSPMode)); - assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler)); - assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit)); - assert_param(IS_SPI_TIMODE(hspi->Init.TIMode)); - if (hspi->Init.TIMode == SPI_TIMODE_DISABLE) - { - assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity)); - assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase)); - } -#if (USE_SPI_CRC != 0UL) - assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation)); - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - if (IS_SPI_LIMITED_INSTANCE(hspi->Instance)) - { - assert_param(IS_SPI_LIMITED_CRC_LENGTH(hspi->Init.CRCLength)); - } - else - { - assert_param(IS_SPI_CRC_LENGTH(hspi->Init.CRCLength)); - } - assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial)); - assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.TxCRCInitializationPattern)); - assert_param(IS_SPI_CRC_INITIALIZATION_PATTERN(hspi->Init.RxCRCInitializationPattern)); - } -#else - hspi->Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; -#endif /* USE_SPI_CRC */ - - assert_param(IS_SPI_RDY_MASTER_MANAGEMENT(hspi->Init.ReadyMasterManagement)); - assert_param(IS_SPI_RDY_POLARITY(hspi->Init.ReadyPolarity)); - assert_param(IS_SPI_MASTER_RX_AUTOSUSP(hspi->Init.MasterReceiverAutoSusp)); - - /* Verify that the SPI instance supports Data Size higher than 16bits */ - if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.DataSize > SPI_DATASIZE_16BIT)) - { - return HAL_ERROR; - } - - /* Verify that the SPI instance supports requested data packing */ - packet_length = SPI_GetPacketSize(hspi); - if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (packet_length > SPI_LOWEND_FIFO_SIZE)) || - ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (packet_length > SPI_HIGHEND_FIFO_SIZE))) - { - return HAL_ERROR; - } -#if (USE_SPI_CRC != 0UL) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Verify that the SPI instance supports CRC Length higher than 16bits */ - if ((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (hspi->Init.CRCLength > SPI_CRC_LENGTH_16BIT)) - { - return HAL_ERROR; - } - - /* Align the CRC Length on the data size */ - if (hspi->Init.CRCLength == SPI_CRC_LENGTH_DATASIZE) - { - crc_length = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) << SPI_CFG1_CRCSIZE_Pos; - } - else - { - crc_length = hspi->Init.CRCLength; - } - - /* Verify that the CRC Length is higher than DataSize */ - if ((hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) > (crc_length >> SPI_CFG1_CRCSIZE_Pos)) - { - return HAL_ERROR; - } - } - else - { - crc_length = hspi->Init.DataSize << SPI_CFG1_CRCSIZE_Pos; - } -#endif /* USE_SPI_CRC */ - - if (hspi->State == HAL_SPI_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - hspi->Lock = HAL_UNLOCKED; - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - /* Init the SPI Callback settings */ - hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ - hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ - hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ - hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ - hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ - hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ - - if (hspi->MspInitCallback == NULL) - { - hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - hspi->MspInitCallback(hspi); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC... */ - HAL_SPI_MspInit(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disable the selected SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - -#if (USE_SPI_CRC == 0) - /* Keep the default value of CRCSIZE in case of CRC is not used */ - crc_length = hspi->Instance->CFG1 & SPI_CFG1_CRCSIZE; -#endif /* USE_SPI_CRC */ - - /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/ - /* Configure : SPI Mode, Communication Mode, Clock polarity and phase, NSS management, - Communication speed, First bit, CRC calculation state, CRC Length */ - - /* SPIx NSS Software Management Configuration */ - if ((hspi->Init.NSS == SPI_NSS_SOFT) && (((hspi->Init.Mode == SPI_MODE_MASTER) && \ - (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_LOW)) || \ - ((hspi->Init.Mode == SPI_MODE_SLAVE) && \ - (hspi->Init.NSSPolarity == SPI_NSS_POLARITY_HIGH)))) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_SSI); - } - - /* SPIx Master Rx Auto Suspend Configuration */ - if (((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) && (hspi->Init.DataSize >= SPI_DATASIZE_8BIT)) - { - MODIFY_REG(hspi->Instance->CR1, SPI_CR1_MASRX, hspi->Init.MasterReceiverAutoSusp); - } - else - { - CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_MASRX); - } - - /* SPIx CFG1 Configuration */ - WRITE_REG(hspi->Instance->CFG1, (hspi->Init.BaudRatePrescaler | hspi->Init.CRCCalculation | crc_length | - hspi->Init.FifoThreshold | hspi->Init.DataSize)); - - /* SPIx CFG2 Configuration */ - WRITE_REG(hspi->Instance->CFG2, (hspi->Init.NSSPMode | hspi->Init.TIMode | - hspi->Init.NSSPolarity | hspi->Init.NSS | - hspi->Init.CLKPolarity | hspi->Init.CLKPhase | - hspi->Init.FirstBit | hspi->Init.Mode | - hspi->Init.MasterInterDataIdleness | hspi->Init.Direction | - hspi->Init.MasterSSIdleness | hspi->Init.IOSwap | - hspi->Init.ReadyMasterManagement | hspi->Init.ReadyPolarity)); - -#if (USE_SPI_CRC != 0UL) - /*---------------------------- SPIx CRCPOLY Configuration ------------------*/ - /* Configure : CRC Polynomial */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Initialize TXCRC Pattern Initial Value */ - if (hspi->Init.TxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); - } - else - { - CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_TCRCINI); - } - - /* Initialize RXCRC Pattern Initial Value */ - if (hspi->Init.RxCRCInitializationPattern == SPI_CRC_INITIALIZATION_ALL_ONE_PATTERN) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); - } - else - { - CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_RCRCINI); - } - - /* Enable 33/17 bits CRC computation */ - if (((IS_SPI_LIMITED_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_16BIT)) || - ((IS_SPI_FULL_INSTANCE(hspi->Instance)) && (crc_length == SPI_CRC_LENGTH_32BIT))) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - else - { - CLEAR_BIT(hspi->Instance->CR1, SPI_CR1_CRC33_17); - } - - /* Write CRC polynomial in SPI Register */ - WRITE_REG(hspi->Instance->CRCPOLY, hspi->Init.CRCPolynomial); - } -#endif /* USE_SPI_CRC */ - - /* Insure that Underrun configuration is managed only by Salve */ - if (hspi->Init.Mode == SPI_MODE_SLAVE) - { -#if (USE_SPI_CRC != 0UL) - MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, SPI_CFG1_UDRCFG); -#endif /* USE_SPI_CRC */ - } - -#if defined(SPI_I2SCFGR_I2SMOD) - /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */ - CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD); -#endif /* SPI_I2SCFGR_I2SMOD */ - - /* Insure that AFCNTR is managed only by Master */ - if ((hspi->Init.Mode & SPI_MODE_MASTER) == SPI_MODE_MASTER) - { - /* Alternate function GPIOs control */ - MODIFY_REG(hspi->Instance->CFG2, SPI_CFG2_AFCNTR, (hspi->Init.MasterKeepIOState)); - } - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_READY; - - return HAL_OK; -} - -/** - * @brief De-Initialize the SPI peripheral. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi) -{ - /* Check the SPI handle allocation */ - if (hspi == NULL) - { - return HAL_ERROR; - } - - /* Check SPI Instance parameter */ - assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance)); - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Disable the SPI Peripheral Clock */ - __HAL_SPI_DISABLE(hspi); - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - if (hspi->MspDeInitCallback == NULL) - { - hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - hspi->MspDeInitCallback(hspi); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ - HAL_SPI_MspDeInit(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->State = HAL_SPI_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspInit should be implemented in the user file - */ -} - -/** - * @brief De-Initialize the SPI MSP. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_MspDeInit should be implemented in the user file - */ -} - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) -/** - * @brief Register a User SPI Callback - * To be used instead of the weak predefined callback - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI. - * @param CallbackID ID of the callback to be registered - * @param pCallback pointer to the Callback function - * @note The HAL_SPI_RegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET - * to register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, - pSPI_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hspi->ErrorCode |= HAL_SPI_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (HAL_SPI_STATE_READY == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_TX_COMPLETE_CB_ID : - hspi->TxCpltCallback = pCallback; - break; - - case HAL_SPI_RX_COMPLETE_CB_ID : - hspi->RxCpltCallback = pCallback; - break; - - case HAL_SPI_TX_RX_COMPLETE_CB_ID : - hspi->TxRxCpltCallback = pCallback; - break; - - case HAL_SPI_TX_HALF_COMPLETE_CB_ID : - hspi->TxHalfCpltCallback = pCallback; - break; - - case HAL_SPI_RX_HALF_COMPLETE_CB_ID : - hspi->RxHalfCpltCallback = pCallback; - break; - - case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : - hspi->TxRxHalfCpltCallback = pCallback; - break; - - case HAL_SPI_ERROR_CB_ID : - hspi->ErrorCallback = pCallback; - break; - - case HAL_SPI_ABORT_CB_ID : - hspi->AbortCpltCallback = pCallback; - break; - - case HAL_SPI_SUSPEND_CB_ID : - hspi->SuspendCallback = pCallback; - break; - - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = pCallback; - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SPI_STATE_RESET == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = pCallback; - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an SPI Callback - * SPI callback is redirected to the weak predefined callback - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI. - * @param CallbackID ID of the callback to be unregistered - * @note The HAL_SPI_UnRegisterCallback() may be called before HAL_SPI_Init() in HAL_SPI_STATE_RESET - * to un-register callbacks for HAL_SPI_MSPINIT_CB_ID and HAL_SPI_MSPDEINIT_CB_ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_SPI_STATE_READY == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_TX_COMPLETE_CB_ID : - hspi->TxCpltCallback = HAL_SPI_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_SPI_RX_COMPLETE_CB_ID : - hspi->RxCpltCallback = HAL_SPI_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_SPI_TX_RX_COMPLETE_CB_ID : - hspi->TxRxCpltCallback = HAL_SPI_TxRxCpltCallback; /* Legacy weak TxRxCpltCallback */ - break; - - case HAL_SPI_TX_HALF_COMPLETE_CB_ID : - hspi->TxHalfCpltCallback = HAL_SPI_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_SPI_RX_HALF_COMPLETE_CB_ID : - hspi->RxHalfCpltCallback = HAL_SPI_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID : - hspi->TxRxHalfCpltCallback = HAL_SPI_TxRxHalfCpltCallback; /* Legacy weak TxRxHalfCpltCallback */ - break; - - case HAL_SPI_ERROR_CB_ID : - hspi->ErrorCallback = HAL_SPI_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_SPI_ABORT_CB_ID : - hspi->AbortCpltCallback = HAL_SPI_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_SPI_SUSPEND_CB_ID : - hspi->SuspendCallback = HAL_SPI_SuspendCallback; /* Legacy weak SuspendCallback */ - break; - - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_SPI_STATE_RESET == hspi->State) - { - switch (CallbackID) - { - case HAL_SPI_MSPINIT_CB_ID : - hspi->MspInitCallback = HAL_SPI_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_SPI_MSPDEINIT_CB_ID : - hspi->MspDeInitCallback = HAL_SPI_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_INVALID_CALLBACK); - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group2 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to manage the SPI - data transfers. - - [..] The SPI supports master and slave mode : - - (#) There are two modes of transfer: - (##) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (##) No-Blocking mode: The communication is performed using Interrupts - or DMA, These APIs return the HAL status. - The end of the data processing will be indicated through the - dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected - - (#) APIs provided for these 2 transfer modes (Blocking mode or Non blocking mode using either Interrupt or DMA) - exist for 1Line (simplex) and 2Lines (full duplex) modes. - -@endverbatim - * @{ - */ - -/** - * @brief Transmit an amount of data in blocking mode. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be sent - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ -#if defined (__GNUC__) - __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); -#endif /* __GNUC__ */ - - uint32_t tickstart; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (const uint8_t *)pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = (uint16_t) 0UL; - hspi->RxXferCount = (uint16_t) 0UL; - hspi->TxISR = NULL; - hspi->RxISR = NULL; - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - else - { - SPI_2LINES_TX(hspi); - } - - /* Set the number of data at current transfer */ - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - /* Transmit data in 32 Bit mode */ - if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) - { - /* Transmit data in 32 Bit mode */ - while (hspi->TxXferCount > 0UL) - { - /* Wait until TXP flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - /* Transmit data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Transmit data in 16 Bit mode */ - while (hspi->TxXferCount > 0UL) - { - /* Wait until TXP flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) - { - if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)2UL; - } - else - { -#if defined (__GNUC__) - *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - } - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - /* Transmit data in 8 Bit mode */ - else - { - while (hspi->TxXferCount > 0UL) - { - /* Wait until TXP flag is set to send data */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) - { - if ((hspi->TxXferCount > 3UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_03DATA)) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount -= (uint16_t)4UL; - } - else if ((hspi->TxXferCount > 1UL) && (hspi->Init.FifoThreshold > SPI_FIFO_THRESHOLD_01DATA)) - { -#if defined (__GNUC__) - *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount -= (uint16_t)2UL; - } - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - } - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - - /* Wait for Tx (and CRC) data to be sent */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData : pointer to data buffer - * @param Size : amount of data to be received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint32_t tickstart; -#if defined (__GNUC__) - __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); -#endif /* __GNUC__ */ - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = (uint16_t) 0UL; - hspi->TxXferCount = (uint16_t) 0UL; - hspi->RxISR = NULL; - hspi->TxISR = NULL; - - /* Configure communication direction: 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else - { - SPI_2LINES_RX(hspi); - } - - /* Set the number of data at current transfer */ - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - /* Receive data in 32 Bit mode */ - if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) - { - /* Transfer loop */ - while (hspi->RxXferCount > 0UL) - { - /* Check the RXWNE/EOT flag */ - if ((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - /* Receive data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Transfer loop */ - while (hspi->RxXferCount > 0UL) - { - /* Check the RXP flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - /* Receive data in 8 Bit mode */ - else - { - /* Transfer loop */ - while (hspi->RxXferCount > 0UL) - { - /* Check the RXP flag */ - if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - } - else - { - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - } - -#if (USE_SPI_CRC != 0UL) - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait for crc data to be received */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - } -#endif /* USE_SPI_CRC */ - - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } -} - -/** - * @brief Transmit and Receive an amount of data in blocking mode. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size : amount of data to be sent and received - * @param Timeout: Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size, uint32_t Timeout) -{ -#if defined (__GNUC__) - __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); -#endif /* __GNUC__ */ - - uint32_t tickstart; - uint32_t fifo_length; - uint16_t initial_TxXferCount; - uint16_t initial_RxXferCount; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - /* Init tickstart for timeout management*/ - tickstart = HAL_GetTick(); - - initial_TxXferCount = Size; - initial_RxXferCount = Size; - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferCount = Size; - hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (const uint8_t *)pTxData; - hspi->TxXferCount = Size; - hspi->TxXferSize = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = NULL; - hspi->TxISR = NULL; - - /* Set Full-Duplex mode */ - SPI_2LINES(hspi); - - /* Initialize FIFO length */ - if (IS_SPI_FULL_INSTANCE(hspi->Instance)) - { - fifo_length = SPI_HIGHEND_FIFO_SIZE; - } - else - { - fifo_length = SPI_LOWEND_FIFO_SIZE; - } - - /* Set the number of data at current transfer */ - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - - __HAL_SPI_ENABLE(hspi); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - /* Transmit and Receive data in 32 Bit mode */ - if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) - { - /* Adapt fifo length to 32bits data width */ - fifo_length = (fifo_length / 4UL); - - while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) - { - /* Check TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && - (initial_RxXferCount < (initial_TxXferCount + fifo_length))) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount --; - initial_TxXferCount = hspi->TxXferCount; - } - - /* Check RXWNE/EOT flag */ - if (((hspi->Instance->SR & (SPI_FLAG_RXWNE | SPI_FLAG_EOT)) != 0UL) && (initial_RxXferCount > 0UL)) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount --; - initial_RxXferCount = hspi->RxXferCount; - } - - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - /* Transmit and Receive data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - /* Adapt fifo length to 16bits data width */ - fifo_length = (fifo_length / 2UL); - - while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) - { - /* Check the TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && - (initial_RxXferCount < (initial_TxXferCount + fifo_length))) - { -#if defined (__GNUC__) - *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } - - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } - - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - /* Transmit and Receive data in 8 Bit mode */ - else - { - while ((initial_TxXferCount > 0UL) || (initial_RxXferCount > 0UL)) - { - /* Check the TXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (initial_TxXferCount > 0UL) && - (initial_RxXferCount < (initial_TxXferCount + fifo_length))) - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - initial_TxXferCount = hspi->TxXferCount; - } - - /* Check the RXP flag */ - if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXP)) && (initial_RxXferCount > 0UL)) - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - initial_RxXferCount = hspi->RxXferCount; - } - - /* Timeout management */ - if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_TIMEOUT); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_TIMEOUT; - } - } - } - - /* Wait for Tx/Rx (and CRC) data to be sent/received */ - if (SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_EOT, RESET, Timeout, tickstart) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Call standard close procedure with error check */ - SPI_CloseTransfer(hspi); - - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - return HAL_ERROR; - } - else - { - return HAL_OK; - } -} - -/** - * @brief Transmit an amount of data in non-blocking mode with Interrupt. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size : amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) -{ - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - - if ((pData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (const uint8_t *)pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->pRxBuffPtr = NULL; - hspi->RxXferSize = (uint16_t) 0UL; - hspi->RxXferCount = (uint16_t) 0UL; - hspi->RxISR = NULL; - - /* Set the function for IT treatment */ - if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) - { - hspi->TxISR = SPI_TxISR_32BIT; - } - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->TxISR = SPI_TxISR_16BIT; - } - else - { - hspi->TxISR = SPI_TxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - else - { - SPI_2LINES_TX(hspi); - } - - /* Set the number of data at current transfer */ - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - /* Enable EOT, TXP, FRE, MODF and UDR interrupts */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size : amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->pTxBuffPtr = NULL; - hspi->TxXferSize = (uint16_t) 0UL; - hspi->TxXferCount = (uint16_t) 0UL; - hspi->TxISR = NULL; - - /* Set the function for IT treatment */ - if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) - { - hspi->RxISR = SPI_RxISR_32BIT; - } - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->RxISR = SPI_RxISR_16BIT; - } - else - { - hspi->RxISR = SPI_RxISR_8BIT; - } - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else - { - SPI_2LINES_RX(hspi); - } - - /* Note : The SPI must be enabled after unlocking current process - to avoid the risk of SPI interrupt handle execution before current - process unlock */ - - /* Set the number of data at current transfer */ - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - /* Enable EOT, RXP, OVR, FRE and MODF interrupts */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - return HAL_OK; -} - -/** - * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size : amount of data to be sent and received - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size) -{ - uint32_t tmp_TxXferCount; -#if defined (__GNUC__) - __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); -#endif /* __GNUC__ */ - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (const uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - tmp_TxXferCount = hspi->TxXferCount; - - /* Set the function for IT treatment */ - if ((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (IS_SPI_FULL_INSTANCE(hspi->Instance))) - { - hspi->TxISR = SPI_TxISR_32BIT; - hspi->RxISR = SPI_RxISR_32BIT; - } - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { - hspi->RxISR = SPI_RxISR_16BIT; - hspi->TxISR = SPI_TxISR_16BIT; - } - else - { - hspi->RxISR = SPI_RxISR_8BIT; - hspi->TxISR = SPI_TxISR_8BIT; - } - - /* Set Full-Duplex mode */ - SPI_2LINES(hspi); - - /* Set the number of data at current transfer */ - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - /* Fill in the TxFIFO */ - while ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXP)) && (tmp_TxXferCount != 0UL)) - { - /* Transmit data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - /* Transmit data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { -#if defined (__GNUC__) - *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - /* Transmit data in 8 Bit mode */ - else - { - *((__IO uint8_t *)&hspi->Instance->TXDR) = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - tmp_TxXferCount = hspi->TxXferCount; - } - } - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - /* Enable EOT, DXP, UDR, OVR, FRE and MODF interrupts */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Start Master transfer */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - return HAL_OK; -} - - - - -/** - * @brief Transmit an amount of data in non-blocking mode with DMA. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size : amount of data to be sent - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_TXONLY(hspi->Init.Direction)); - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (const uint8_t *)pData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->pRxBuffPtr = NULL; - hspi->TxISR = NULL; - hspi->RxISR = NULL; - hspi->RxXferSize = (uint16_t)0UL; - hspi->RxXferCount = (uint16_t)0UL; - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_TX(hspi); - } - else - { - SPI_2LINES_TX(hspi); - } - - /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmatx->Init.SrcDataWidth != DMA_SRC_DATAWIDTH_WORD) && \ - (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_BYTE))) - { - /* Restriction the DMA data received is not allowed in this mode */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; - } - - /* Adjust XferCount according to DMA alignment / Data size */ - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) - { - hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; - } - if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) - { - hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; - } - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) - { - hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; - } - } - else - { - /* Adjustment done */ - } - - /* Set the SPI TxDMA Half transfer complete callback */ - hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt; - - /* Set the SPI TxDMA transfer complete callback */ - hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA AbortCpltCallback */ - hspi->hdmatx->XferAbortCallback = NULL; - - /* Clear TXDMAEN bit*/ - CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); - - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - hspi->TxXferCount = Size; - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - hspi->TxXferCount = Size * 2U; - } - else - { - hspi->TxXferCount = Size * 4U; - } - - /* Enable the Tx DMA Stream/Channel */ - if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hspi->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; - - /* Set DMA source address */ - hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; - - /* Set DMA destination address */ - hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - - status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); - } - - /* Check status */ - if (status != HAL_OK) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; - } - - /* Set the number of data at current transfer */ - if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) - { - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); - } - else - { - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - } - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); - - /* Enable the SPI Error Interrupt Bit */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in non-blocking mode with DMA. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pData: pointer to data buffer - * @param Size : amount of data to be sent - * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE_2LINES_RXONLY(hspi->Init.Direction)); - - - if (hspi->State != HAL_SPI_STATE_READY) - { - __HAL_UNLOCK(hspi); - return HAL_BUSY; - } - - if ((pData == NULL) || (Size == 0UL)) - { - __HAL_UNLOCK(hspi); - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pRxBuffPtr = (uint8_t *)pData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /*Init field not used in handle to zero */ - hspi->RxISR = NULL; - hspi->TxISR = NULL; - hspi->TxXferSize = (uint16_t) 0UL; - hspi->TxXferCount = (uint16_t) 0UL; - - /* Configure communication direction : 1Line */ - if (hspi->Init.Direction == SPI_DIRECTION_1LINE) - { - SPI_1LINE_RX(hspi); - } - else - { - SPI_2LINES_RX(hspi); - } - - /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ - (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) - { - /* Restriction the DMA data received is not allowed in this mode */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; - } - - /* Clear RXDMAEN bit */ - CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); - - /* Adjust XferCount according to DMA alignment / Data size */ - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) - { - hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; - } - if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) - { - hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; - } - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) - { - hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; - } - } - else - { - /* Adjustment done */ - } - - /* Set the SPI RxDMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt; - - /* Set the SPI Rx DMA transfer complete callback */ - hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt; - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA AbortCpltCallback */ - hspi->hdmarx->XferAbortCallback = NULL; - - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - hspi->RxXferCount = Size; - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - hspi->RxXferCount = Size * 2U; - } - else - { - hspi->RxXferCount = Size * 4U; - } - - /* Enable the Rx DMA Stream/Channel */ - if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hspi->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; - - /* Set DMA source address */ - hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; - - /* Set DMA destination address */ - hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - - status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); - } - - /* Check status */ - if (status != HAL_OK) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; - } - - /* Set the number of data at current transfer */ - if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) - { - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); - } - else - { - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - } - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); - - /* Enable the SPI Error Interrupt Bit */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_FRE | SPI_IT_MODF)); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. - * @param hspi : pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param pTxData: pointer to transmission data buffer - * @param pRxData: pointer to reception data buffer - * @param Size : amount of data to be sent - * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, - uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check Direction parameter */ - assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - - if (hspi->State != HAL_SPI_STATE_READY) - { - return HAL_BUSY; - } - - if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0UL)) - { - return HAL_ERROR; - } - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set the transaction information */ - hspi->State = HAL_SPI_STATE_BUSY_TX_RX; - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (const uint8_t *)pTxData; - hspi->TxXferSize = Size; - hspi->TxXferCount = Size; - hspi->pRxBuffPtr = (uint8_t *)pRxData; - hspi->RxXferSize = Size; - hspi->RxXferCount = Size; - - /* Init field not used in handle to zero */ - hspi->RxISR = NULL; - hspi->TxISR = NULL; - - /* Set Full-Duplex mode */ - SPI_2LINES(hspi); - - /* Reset the Tx/Rx DMA bits */ - CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); - - /* Packing mode management is enabled by the DMA settings */ - if (((hspi->Init.DataSize > SPI_DATASIZE_16BIT) && (hspi->hdmarx->Init.DestDataWidth != DMA_DEST_DATAWIDTH_WORD) && \ - (IS_SPI_FULL_INSTANCE(hspi->Instance))) || \ - ((hspi->Init.DataSize > SPI_DATASIZE_8BIT) && (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_BYTE))) - { - /* Restriction the DMA data received is not allowed in this mode */ - /* Unlock the process */ - __HAL_UNLOCK(hspi); - return HAL_ERROR; - } - - /* Adjust XferCount according to DMA alignment / Data size */ - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_HALFWORD) - { - hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; - } - if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) - { - hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 3UL) >> 2UL; - } - if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_HALFWORD) - { - hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; - } - if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) - { - hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 3UL) >> 2UL; - } - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - if (hspi->hdmatx->Init.SrcDataWidth == DMA_SRC_DATAWIDTH_WORD) - { - hspi->TxXferCount = (hspi->TxXferCount + (uint16_t) 1UL) >> 1UL; - } - if (hspi->hdmarx->Init.DestDataWidth == DMA_DEST_DATAWIDTH_WORD) - { - hspi->RxXferCount = (hspi->RxXferCount + (uint16_t) 1UL) >> 1UL; - } - } - else - { - /* Adjustment done */ - } - - /* Set the SPI Tx/Rx DMA Half transfer complete callback */ - hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt; - hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt; - - /* Set the DMA error callback */ - hspi->hdmarx->XferErrorCallback = SPI_DMAError; - - /* Set the DMA AbortCallback */ - hspi->hdmarx->XferAbortCallback = NULL; - - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - hspi->RxXferCount = Size; - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - hspi->RxXferCount = Size * 2U; - } - else - { - hspi->RxXferCount = Size * 4U; - } - /* Enable the Rx DMA Stream/Channel */ - if ((hspi->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hspi->hdmarx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->RxXferCount; - - /* Set DMA source address */ - hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->RXDR; - - /* Set DMA destination address */ - hspi->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)hspi->pRxBuffPtr; - - status = HAL_DMAEx_List_Start_IT(hspi->hdmarx); - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->RXDR, (uint32_t)hspi->pRxBuffPtr, - hspi->RxXferCount); - } - - /* Check status */ - if (status != HAL_OK) - { - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; - } - - /* Enable Rx DMA Request */ - SET_BIT(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN); - - /* Set the SPI Tx DMA transfer complete callback as NULL because the communication closing - is performed in DMA reception complete callback */ - hspi->hdmatx->XferHalfCpltCallback = NULL; - hspi->hdmatx->XferCpltCallback = NULL; - hspi->hdmatx->XferAbortCallback = NULL; - - /* Set the DMA error callback */ - hspi->hdmatx->XferErrorCallback = SPI_DMAError; - - if (hspi->Init.DataSize <= SPI_DATASIZE_8BIT) - { - hspi->TxXferCount = Size; - } - else if (hspi->Init.DataSize <= SPI_DATASIZE_16BIT) - { - hspi->TxXferCount = Size * 2U; - } - else - { - hspi->TxXferCount = Size * 4U; - } - - /* Enable the Tx DMA Stream/Channel */ - if ((hspi->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if (hspi->hdmatx->LinkedListQueue != NULL) - { - /* Set DMA data size */ - hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = hspi->TxXferCount; - - /* Set DMA source address */ - hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)hspi->pTxBuffPtr; - - /* Set DMA destination address */ - hspi->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)&hspi->Instance->TXDR; - - status = HAL_DMAEx_List_Start_IT(hspi->hdmatx); - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->TXDR, - hspi->TxXferCount); - } - - /* Check status */ - if (status != HAL_OK) - { - /* Abort Rx DMA Channel already started */ - (void)HAL_DMA_Abort(hspi->hdmarx); - - /* Update SPI error code */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_ERROR; - } - - if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) - { - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, 0UL); - } - else - { - MODIFY_REG(hspi->Instance->CR2, SPI_CR2_TSIZE, Size); - } - - /* Enable Tx DMA Request */ - SET_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN); - - /* Enable the SPI Error Interrupt Bit */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_OVR | SPI_IT_UDR | SPI_IT_FRE | SPI_IT_MODF)); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - if (((hspi->Instance->AUTOCR & SPI_AUTOCR_TRIGEN) == 0U) && (hspi->Init.Mode == SPI_MODE_MASTER)) - { - /* Master transfer start */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSTART); - } - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfer (blocking mode). - * @param hspi SPI handle. - * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), - * started in Interrupt or DMA mode. - * @note This procedure performs following operations : - * + Disable SPI Interrupts (depending of transfer direction) - * + Disable the DMA transfer in the peripheral register (if enabled) - * + Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * + Set handle State to READY. - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) -{ - HAL_StatusTypeDef errorcode; - - __IO uint32_t count; - - /* Lock the process */ - __HAL_LOCK(hspi); - - /* Set hspi->state to aborting to avoid any interaction */ - hspi->State = HAL_SPI_STATE_ABORT; - - /* Initialized local variable */ - errorcode = HAL_OK; - count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); - - /* If master communication on going, make sure current frame is done before closing the connection */ - if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) - { - /* Disable EOT interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); - do - { - count--; - if (count == 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); - - /* Request a Suspend transfer */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); - do - { - count--; - if (count == 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); - - /* Clear SUSP flag */ - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - do - { - count--; - if (count == 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); - } - - /* Disable the SPI DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) - { - if (hspi->hdmatx != NULL) - { - /* Abort the SPI DMA Tx Stream/Channel : use blocking DMA Abort API (no callback) */ - hspi->hdmatx->XferAbortCallback = NULL; - - /* Abort DMA Tx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort(hspi->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - } - } - } - - /* Disable the SPI DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) - { - if (hspi->hdmarx != NULL) - { - /* Abort the SPI DMA Rx Stream/Channel : use blocking DMA Abort API (no callback) */ - hspi->hdmarx->XferAbortCallback = NULL; - - /* Abort DMA Rx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort(hspi->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - hspi->ErrorCode = HAL_SPI_ERROR_ABORT; - } - } - } - } - - /* Proceed with abort procedure */ - SPI_AbortTransfer(hspi); - - /* Check error during Abort procedure */ - if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) - { - /* return HAL_Error in case of error during Abort procedure */ - errorcode = HAL_ERROR; - } - else - { - /* Reset errorCode */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - } - - /* Restore hspi->state to ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Unlock the process */ - __HAL_UNLOCK(hspi); - - return errorcode; -} - -/** - * @brief Abort ongoing transfer (Interrupt mode). - * @param hspi SPI handle. - * @note This procedure could be used for aborting any ongoing transfer (Tx and Rx), - * started in Interrupt or DMA mode. - * @note This procedure performs following operations : - * + Disable SPI Interrupts (depending of transfer direction) - * + Disable the DMA transfer in the peripheral register (if enabled) - * + Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * + Set handle State to READY - * + At abort completion, call user abort complete callback. - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) -{ - HAL_StatusTypeDef errorcode; - __IO uint32_t count; - uint32_t dma_tx_abort_done = 1UL; - uint32_t dma_rx_abort_done = 1UL; - - /* Set hspi->state to aborting to avoid any interaction */ - hspi->State = HAL_SPI_STATE_ABORT; - - /* Initialized local variable */ - errorcode = HAL_OK; - count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24UL / 1000UL); - - /* If master communication on going, make sure current frame is done before closing the connection */ - if (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)) - { - /* Disable EOT interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); - do - { - count--; - if (count == 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - } while (HAL_IS_BIT_SET(hspi->Instance->IER, SPI_IT_EOT)); - - /* Request a Suspend transfer */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CSUSP); - do - { - count--; - if (count == 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - } while (HAL_IS_BIT_SET(hspi->Instance->CR1, SPI_CR1_CSTART)); - - /* Clear SUSP flag */ - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - do - { - count--; - if (count == 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - break; - } - } while (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_SUSP)); - } - - /* If DMA Tx and/or DMA Rx Handles are associated to SPI Handle, DMA Abort complete callbacks should be initialized - before any call to DMA Abort functions */ - - if (hspi->hdmatx != NULL) - { - if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN)) - { - /* Set DMA Abort Complete callback if SPI DMA Tx request if enabled */ - hspi->hdmatx->XferAbortCallback = SPI_DMATxAbortCallback; - - dma_tx_abort_done = 0UL; - - /* Abort DMA Tx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(hspi->hdmatx) == HAL_DMA_ERROR_NO_XFER) - { - dma_tx_abort_done = 1UL; - hspi->hdmatx->XferAbortCallback = NULL; - } - } - } - else - { - hspi->hdmatx->XferAbortCallback = NULL; - } - } - - if (hspi->hdmarx != NULL) - { - if (HAL_IS_BIT_SET(hspi->Instance->CFG1, SPI_CFG1_RXDMAEN)) - { - /* Set DMA Abort Complete callback if SPI DMA Rx request if enabled */ - hspi->hdmarx->XferAbortCallback = SPI_DMARxAbortCallback; - - dma_rx_abort_done = 0UL; - - /* Abort DMA Rx Handle linked to SPI Peripheral */ - if (HAL_DMA_Abort_IT(hspi->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(hspi->hdmarx) == HAL_DMA_ERROR_NO_XFER) - { - dma_rx_abort_done = 1UL; - hspi->hdmarx->XferAbortCallback = NULL; - } - } - } - else - { - hspi->hdmarx->XferAbortCallback = NULL; - } - } - - /* If no running DMA transfer, finish cleanup and call callbacks */ - if ((dma_tx_abort_done == 1UL) && (dma_rx_abort_done == 1UL)) - { - /* Proceed with abort procedure */ - SPI_AbortTransfer(hspi); - - /* Check error during Abort procedure */ - if (HAL_IS_BIT_SET(hspi->ErrorCode, HAL_SPI_ERROR_ABORT)) - { - /* return HAL_Error in case of error during Abort procedure */ - errorcode = HAL_ERROR; - } - else - { - /* Reset errorCode */ - hspi->ErrorCode = HAL_SPI_ERROR_NONE; - } - - /* Restore hspi->state to ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->AbortCpltCallback(hspi); -#else - HAL_SPI_AbortCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - - return errorcode; -} - -/** - * @brief Pause the DMA Transfer. - * This API is not supported, it is maintained for backward compatibility. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL_ERROR - */ -HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi) -{ - /* Set error code to not supported */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); - - return HAL_ERROR; -} - -/** - * @brief Resume the DMA Transfer. - * This API is not supported, it is maintained for backward compatibility. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL_ERROR - */ -HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi) -{ - /* Set error code to not supported */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); - - return HAL_ERROR; -} - -/** - * @brief Stop the DMA Transfer. - * This API is not supported, it is maintained for backward compatibility. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL_ERROR - */ -HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) -{ - /* Set error code to not supported */ - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_NOT_SUPPORTED); - - return HAL_ERROR; -} - -/** - * @brief Handle SPI interrupt request. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval None - */ -void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) -{ - uint32_t itsource = hspi->Instance->IER; - uint32_t itflag = hspi->Instance->SR; - uint32_t trigger = itsource & itflag; - uint32_t cfg1 = hspi->Instance->CFG1; - uint32_t handled = 0UL; - - HAL_SPI_StateTypeDef State = hspi->State; -#if defined (__GNUC__) - __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); -#endif /* __GNUC__ */ - - /* SPI in SUSPEND mode ----------------------------------------------------*/ - if (HAL_IS_BIT_SET(itflag, SPI_FLAG_SUSP) && HAL_IS_BIT_SET(itsource, SPI_FLAG_EOT)) - { - /* Clear the Suspend flag */ - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - - /* Suspend on going, Call the Suspend callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->SuspendCallback(hspi); -#else - HAL_SPI_SuspendCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } - - /* SPI in mode Transmitter and Receiver ------------------------------------*/ - if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && \ - HAL_IS_BIT_SET(trigger, SPI_FLAG_DXP)) - { - hspi->TxISR(hspi); - hspi->RxISR(hspi); - handled = 1UL; - } - - /* SPI in mode Receiver ----------------------------------------------------*/ - if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_OVR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_RXP) && \ - HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) - { - hspi->RxISR(hspi); - handled = 1UL; - } - - /* SPI in mode Transmitter -------------------------------------------------*/ - if (HAL_IS_BIT_CLR(trigger, SPI_FLAG_UDR) && HAL_IS_BIT_SET(trigger, SPI_FLAG_TXP) && \ - HAL_IS_BIT_CLR(trigger, SPI_FLAG_DXP)) - { - hspi->TxISR(hspi); - handled = 1UL; - } - - if (handled != 0UL) - { - return; - } - - /* SPI End Of Transfer: DMA or IT based transfer */ - if (HAL_IS_BIT_SET(trigger, SPI_FLAG_EOT)) - { - /* Clear EOT/TXTF/SUSP flag */ - __HAL_SPI_CLEAR_EOTFLAG(hspi); - __HAL_SPI_CLEAR_TXTFFLAG(hspi); - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - - /* Disable EOT interrupt */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_EOT); - - /* For the IT based receive extra polling maybe required for last packet */ - if (HAL_IS_BIT_CLR(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) - { - /* Pooling remaining data */ - while (hspi->RxXferCount != 0UL) - { - /* Receive data in 32 Bit mode */ - if (hspi->Init.DataSize > SPI_DATASIZE_16BIT) - { - *((uint32_t *)hspi->pRxBuffPtr) = *((__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - } - /* Receive data in 16 Bit mode */ - else if (hspi->Init.DataSize > SPI_DATASIZE_8BIT) - { -#if defined (__GNUC__) - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = *((__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - } - /* Receive data in 8 Bit mode */ - else - { - *((uint8_t *)hspi->pRxBuffPtr) = *((__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - } - - hspi->RxXferCount--; - } - } - - /* Call SPI Standard close procedure */ - SPI_CloseTransfer(hspi); - - hspi->State = HAL_SPI_STATE_READY; - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - return; - } - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - /* Call appropriate user callback */ - if (State == HAL_SPI_STATE_BUSY_TX_RX) - { - hspi->TxRxCpltCallback(hspi); - } - else if (State == HAL_SPI_STATE_BUSY_RX) - { - hspi->RxCpltCallback(hspi); - } - else if (State == HAL_SPI_STATE_BUSY_TX) - { - hspi->TxCpltCallback(hspi); - } -#else - /* Call appropriate user callback */ - if (State == HAL_SPI_STATE_BUSY_TX_RX) - { - HAL_SPI_TxRxCpltCallback(hspi); - } - else if (State == HAL_SPI_STATE_BUSY_RX) - { - HAL_SPI_RxCpltCallback(hspi); - } - else if (State == HAL_SPI_STATE_BUSY_TX) - { - HAL_SPI_TxCpltCallback(hspi); - } -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - else - { - /* End of the appropriate call */ - } - - return; - } - - /* SPI in Error Treatment --------------------------------------------------*/ - if ((trigger & (SPI_FLAG_MODF | SPI_FLAG_OVR | SPI_FLAG_FRE | SPI_FLAG_UDR)) != 0UL) - { - /* SPI Overrun error interrupt occurred ----------------------------------*/ - if ((trigger & SPI_FLAG_OVR) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - /* SPI Mode Fault error interrupt occurred -------------------------------*/ - if ((trigger & SPI_FLAG_MODF) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); - __HAL_SPI_CLEAR_MODFFLAG(hspi); - } - - /* SPI Frame error interrupt occurred ------------------------------------*/ - if ((trigger & SPI_FLAG_FRE) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); - __HAL_SPI_CLEAR_FREFLAG(hspi); - } - - /* SPI Underrun error interrupt occurred ------------------------------------*/ - if ((trigger & SPI_FLAG_UDR) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); - __HAL_SPI_CLEAR_UDRFLAG(hspi); - } - - if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Disable all interrupts */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_RXP | SPI_IT_TXP | SPI_IT_MODF | - SPI_IT_OVR | SPI_IT_FRE | SPI_IT_UDR)); - - /* Disable the SPI DMA requests if enabled */ - if (HAL_IS_BIT_SET(cfg1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN)) - { - /* Disable the SPI DMA requests */ - CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); - - /* Abort the SPI DMA Rx channel */ - if (hspi->hdmarx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ - hspi->hdmarx->XferAbortCallback = SPI_DMAAbortOnError; - if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmarx)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - } - } - /* Abort the SPI DMA Tx channel */ - if (hspi->hdmatx != NULL) - { - /* Set the SPI DMA Abort callback : - will lead to call HAL_SPI_ErrorCallback() at end of DMA abort procedure */ - hspi->hdmatx->XferAbortCallback = SPI_DMAAbortOnError; - if (HAL_OK != HAL_DMA_Abort_IT(hspi->hdmatx)) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_ABORT); - } - } - } - else - { - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Call user error callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - } - return; - } -} - -/** - * @brief Tx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Tx and Rx Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxHalfCpltCallback should be implemented in the user file - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_RxHalfCpltCallback() should be implemented in the user file - */ -} - -/** - * @brief Tx and Rx Half Transfer callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_TxRxHalfCpltCallback() should be implemented in the user file - */ -} - -/** - * @brief SPI error callback. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -__weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_ErrorCallback should be implemented in the user file - */ - /* NOTE : The ErrorCode parameter in the hspi handle is updated by the SPI processes - and user can use HAL_SPI_GetError() API to check the latest error occurred - */ -} - -/** - * @brief SPI Abort Complete callback. - * @param hspi SPI handle. - * @retval None - */ -__weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief SPI Suspend callback. - * @param hspi SPI handle. - * @retval None - */ -__weak void HAL_SPI_SuspendCallback(SPI_HandleTypeDef *hspi) /* Derogation MISRAC2012-Rule-8.13 */ -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hspi); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_SPI_SuspendCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions - * @brief SPI control functions - * -@verbatim - =============================================================================== - ##### Peripheral State and Errors functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the SPI. - (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral - (+) HAL_SPI_GetError() check in run-time Errors occurring during communication -@endverbatim - * @{ - */ - -/** - * @brief Return the SPI handle state. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI state - */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) -{ - /* Return SPI handle state */ - return hspi->State; -} - -/** - * @brief Return the SPI error code. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval SPI error code in bitmap format - */ -uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) -{ - /* Return SPI ErrorCode */ - return hspi->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup SPI_Private_Functions - * @brief Private functions - * @{ - */ - -/** - * @brief DMA SPI transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hspi->State != HAL_SPI_STATE_ABORT) - { - if (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR) - { -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->TxCpltCallback(hspi); -#else - HAL_SPI_TxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { - /* Enable EOT interrupt */ - __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); - } - } -} - -/** - * @brief DMA SPI receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hspi->State != HAL_SPI_STATE_ABORT) - { - if (hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) - { -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->RxCpltCallback(hspi); -#else - HAL_SPI_RxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { - /* Enable EOT interrupt */ - __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); - } - } -} - -/** - * @brief DMA SPI transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hspi->State != HAL_SPI_STATE_ABORT) - { - if ((hspi->hdmarx->Mode == DMA_LINKEDLIST_CIRCULAR) && - (hspi->hdmatx->Mode == DMA_LINKEDLIST_CIRCULAR)) - { -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->TxRxCpltCallback(hspi); -#else - HAL_SPI_TxRxCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } - else - { - /* Enable EOT interrupt */ - __HAL_SPI_ENABLE_IT(hspi, SPI_IT_EOT); - } - } -} - -/** - * @brief DMA SPI half transmit process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) - ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->TxHalfCpltCallback(hspi); -#else - HAL_SPI_TxHalfCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI half receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) - ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->RxHalfCpltCallback(hspi); -#else - HAL_SPI_RxHalfCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI half transmit receive process complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) /* Derogation MISRAC2012-Rule-8.13 */ -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *) - ((DMA_HandleTypeDef *)hdma)->Parent; /* Derogation MISRAC2012-Rule-8.13 */ - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->TxRxHalfCpltCallback(hspi); -#else - HAL_SPI_TxRxHalfCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI communication error callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains - * the configuration information for the specified DMA module. - * @retval None - */ -static void SPI_DMAError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* if DMA error is FIFO error ignore it */ - if (HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_NONE) - { - /* Call SPI standard close procedure */ - SPI_CloseTransfer(hspi); - - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - hspi->State = HAL_SPI_STATE_READY; -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA SPI communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - hspi->RxXferCount = (uint16_t) 0UL; - hspi->TxXferCount = (uint16_t) 0UL; - - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->ErrorCallback(hspi); -#else - HAL_SPI_ErrorCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - hspi->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (hspi->hdmarx != NULL) - { - if (hspi->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* Call the Abort procedure */ - SPI_AbortTransfer(hspi); - - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->AbortCpltCallback(hspi); -#else - HAL_SPI_AbortCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA SPI Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - hspi->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (hspi->hdmatx != NULL) - { - if (hspi->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* Call the Abort procedure */ - SPI_AbortTransfer(hspi); - - /* Restore hspi->State to Ready */ - hspi->State = HAL_SPI_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_SPI_REGISTER_CALLBACKS == 1UL) - hspi->AbortCpltCallback(hspi); -#else - HAL_SPI_AbortCpltCallback(hspi); -#endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ -} - -/** - * @brief Manage the receive 8-bit in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_8BIT(SPI_HandleTypeDef *hspi) -{ - /* Receive data in 8 Bit mode */ - *((uint8_t *)hspi->pRxBuffPtr) = (*(__IO uint8_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint8_t); - hspi->RxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->RxXferCount == 0UL) - { - /* Disable RXP interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); - } -} - - -/** - * @brief Manage the 16-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_16BIT(SPI_HandleTypeDef *hspi) -{ - /* Receive data in 16 Bit mode */ -#if defined (__GNUC__) - __IO uint16_t *prxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->RXDR)); - - *((uint16_t *)hspi->pRxBuffPtr) = *prxdr_16bits; -#else - *((uint16_t *)hspi->pRxBuffPtr) = (*(__IO uint16_t *)&hspi->Instance->RXDR); -#endif /* __GNUC__ */ - hspi->pRxBuffPtr += sizeof(uint16_t); - hspi->RxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->RxXferCount == 0UL) - { - /* Disable RXP interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); - } -} - - -/** - * @brief Manage the 32-bit receive in Interrupt context. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_RxISR_32BIT(SPI_HandleTypeDef *hspi) -{ - /* Receive data in 32 Bit mode */ - *((uint32_t *)hspi->pRxBuffPtr) = (*(__IO uint32_t *)&hspi->Instance->RXDR); - hspi->pRxBuffPtr += sizeof(uint32_t); - hspi->RxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->RxXferCount == 0UL) - { - /* Disable RXP interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXP); - } -} - - -/** - * @brief Handle the data 8-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_8BIT(SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 8 Bit mode */ - *(__IO uint8_t *)&hspi->Instance->TXDR = *((const uint8_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint8_t); - hspi->TxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->TxXferCount == 0UL) - { - /* Disable TXP interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); - } -} - -/** - * @brief Handle the data 16-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_16BIT(SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 16 Bit mode */ -#if defined (__GNUC__) - __IO uint16_t *ptxdr_16bits = (__IO uint16_t *)(&(hspi->Instance->TXDR)); - - *ptxdr_16bits = *((const uint16_t *)hspi->pTxBuffPtr); -#else - *((__IO uint16_t *)&hspi->Instance->TXDR) = *((const uint16_t *)hspi->pTxBuffPtr); -#endif /* __GNUC__ */ - hspi->pTxBuffPtr += sizeof(uint16_t); - hspi->TxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->TxXferCount == 0UL) - { - /* Disable TXP interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); - } -} - -/** - * @brief Handle the data 32-bit transmit in Interrupt mode. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_TxISR_32BIT(SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 32 Bit mode */ - *((__IO uint32_t *)&hspi->Instance->TXDR) = *((const uint32_t *)hspi->pTxBuffPtr); - hspi->pTxBuffPtr += sizeof(uint32_t); - hspi->TxXferCount--; - - /* Disable IT if no more data excepted */ - if (hspi->TxXferCount == 0UL) - { - /* Disable TXP interrupts */ - __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXP); - } -} - -/** - * @brief Abort Transfer and clear flags. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -static void SPI_AbortTransfer(SPI_HandleTypeDef *hspi) -{ - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Disable ITs */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ - SPI_IT_FRE | SPI_IT_MODF)); - - /* Clear the Status flags in the SR register */ - __HAL_SPI_CLEAR_EOTFLAG(hspi); - __HAL_SPI_CLEAR_TXTFFLAG(hspi); - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); - - /* Clear the Error flags in the SR register */ - __HAL_SPI_CLEAR_OVRFLAG(hspi); - __HAL_SPI_CLEAR_UDRFLAG(hspi); - __HAL_SPI_CLEAR_FREFLAG(hspi); - __HAL_SPI_CLEAR_MODFFLAG(hspi); - __HAL_SPI_CLEAR_SUSPFLAG(hspi); - -#if (USE_SPI_CRC != 0U) - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); -#endif /* USE_SPI_CRC */ - - hspi->TxXferCount = (uint16_t)0UL; - hspi->RxXferCount = (uint16_t)0UL; -} - - -/** - * @brief Close Transfer and clear flags. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval HAL_ERROR: if any error detected - * HAL_OK: if nothing detected - */ -static void SPI_CloseTransfer(SPI_HandleTypeDef *hspi) -{ - uint32_t itflag = hspi->Instance->SR; - - __HAL_SPI_CLEAR_EOTFLAG(hspi); - __HAL_SPI_CLEAR_TXTFFLAG(hspi); - - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Disable ITs */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_EOT | SPI_IT_TXP | SPI_IT_RXP | SPI_IT_DXP | SPI_IT_UDR | SPI_IT_OVR | \ - SPI_IT_FRE | SPI_IT_MODF)); - - /* Disable Tx DMA Request */ - CLEAR_BIT(hspi->Instance->CFG1, SPI_CFG1_TXDMAEN | SPI_CFG1_RXDMAEN); - - /* Report UnderRun error for non RX Only communication */ - if (hspi->State != HAL_SPI_STATE_BUSY_RX) - { - if ((itflag & SPI_FLAG_UDR) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_UDR); - __HAL_SPI_CLEAR_UDRFLAG(hspi); - } - } - - /* Report OverRun error for non TX Only communication */ - if (hspi->State != HAL_SPI_STATE_BUSY_TX) - { - if ((itflag & SPI_FLAG_OVR) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR); - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - -#if (USE_SPI_CRC != 0UL) - /* Check if CRC error occurred */ - if (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - if ((itflag & SPI_FLAG_CRCERR) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - } - } -#endif /* USE_SPI_CRC */ - } - - /* SPI Mode Fault error interrupt occurred -------------------------------*/ - if ((itflag & SPI_FLAG_MODF) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF); - __HAL_SPI_CLEAR_MODFFLAG(hspi); - } - - /* SPI Frame error interrupt occurred ------------------------------------*/ - if ((itflag & SPI_FLAG_FRE) != 0UL) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE); - __HAL_SPI_CLEAR_FREFLAG(hspi); - } - - hspi->TxXferCount = (uint16_t)0UL; - hspi->RxXferCount = (uint16_t)0UL; -} - -/** - * @brief Handle SPI Communication Timeout. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param Flag: SPI flag to check - * @param Status: flag state to check - * @param Timeout: Timeout duration - * @param Tickstart: Tick start value - * @retval HAL status - */ -static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(const SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, - uint32_t Timeout, uint32_t Tickstart) -{ - /* Wait until flag is set */ - while ((__HAL_SPI_GET_FLAG(hspi, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if ((((HAL_GetTick() - Tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) - { - return HAL_TIMEOUT; - } - } - return HAL_OK; -} - -/** - * @brief Compute configured packet size from fifo perspective. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval Packet size occupied in the fifo - */ -static uint32_t SPI_GetPacketSize(const SPI_HandleTypeDef *hspi) -{ - uint32_t fifo_threashold = (hspi->Init.FifoThreshold >> SPI_CFG1_FTHLV_Pos) + 1UL; - uint32_t data_size = (hspi->Init.DataSize >> SPI_CFG1_DSIZE_Pos) + 1UL; - - /* Convert data size to Byte */ - data_size = (data_size + 7UL) / 8UL; - - return data_size * fifo_threashold; -} - -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c deleted file mode 100644 index e46eb9502..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_spi_ex.c +++ /dev/null @@ -1,346 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_spi_ex.c - * @author MCD Application Team - * @brief Extended SPI HAL module driver. - * This file provides firmware functions to manage the following - * SPI peripheral extended functionalities : - * + IO operation functions - * + Peripheral Control functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup SPIEx SPIEx - * @brief SPI Extended HAL module driver - * @{ - */ -#ifdef HAL_SPI_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private defines -----------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup SPIEx_Exported_Functions SPIEx Exported Functions - * @{ - */ - -/** @defgroup SPIEx_Exported_Functions_Group1 IO operation functions - * @brief Data transfers functions - * -@verbatim - ============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] - This subsection provides a set of extended functions to manage the SPI - data transfers. - - (#) SPIEx function: - (++) HAL_SPIEx_FlushRxFifo() - (++) HAL_SPIEx_FlushRxFifo() - (++) HAL_SPIEx_EnableLockConfiguration() - (++) HAL_SPIEx_ConfigureUnderrun() - -@endverbatim - * @{ - */ - -/** - * @brief Flush the RX fifo. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPI module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi) -{ - uint8_t count = 0; - uint32_t itflag = hspi->Instance->SR; - __IO uint32_t tmpreg; - - while (((hspi->Instance->SR & SPI_FLAG_FRLVL) != SPI_RX_FIFO_0PACKET) || ((itflag & SPI_FLAG_RXWNE) != 0UL)) - { - count += (uint8_t)4UL; - tmpreg = hspi->Instance->RXDR; - UNUSED(tmpreg); /* To avoid GCC warning */ - - if (IS_SPI_FULL_INSTANCE(hspi->Instance)) - { - if (count > SPI_HIGHEND_FIFO_SIZE) - { - return HAL_TIMEOUT; - } - } - else - { - if (count > SPI_LOWEND_FIFO_SIZE) - { - return HAL_TIMEOUT; - } - } - } - return HAL_OK; -} - - -/** - * @brief Enable the Lock for the AF configuration of associated IOs - * and write protect the Content of Configuration register 2 - * when SPI is enabled - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval None - */ -HAL_StatusTypeDef HAL_SPIEx_EnableLockConfiguration(SPI_HandleTypeDef *hspi) -{ - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hspi); - - if (hspi->State != HAL_SPI_STATE_READY) - { - errorcode = HAL_BUSY; - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; - } - - /* Check if the SPI is disabled to edit IOLOCK bit */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); - } - else - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - SET_BIT(hspi->Instance->CR1, SPI_CR1_IOLOCK); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Configure the UNDERRUN condition and behavior of slave transmitter. - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @param UnderrunDetection : Detection of underrun condition at slave transmitter - * This parameter is not supported in this SPI version. - * It is kept in order to not break the compatibility. - * @param UnderrunBehaviour : Behavior of slave transmitter at underrun condition - * This parameter can be a value of @ref SPI_Underrun_Behaviour. - * @retval None - */ -HAL_StatusTypeDef HAL_SPIEx_ConfigureUnderrun(SPI_HandleTypeDef *hspi, uint32_t UnderrunDetection, - uint32_t UnderrunBehaviour) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(UnderrunDetection); - - HAL_StatusTypeDef errorcode = HAL_OK; - - /* Process Locked */ - __HAL_LOCK(hspi); - - /* Check State and Insure that Underrun configuration is managed only by Salve */ - if ((hspi->State != HAL_SPI_STATE_READY) || (hspi->Init.Mode != SPI_MODE_SLAVE)) - { - errorcode = HAL_BUSY; - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; - } - - /* Check the parameters */ - assert_param(IS_SPI_UNDERRUN_BEHAVIOUR(UnderrunBehaviour)); - - /* Check if the SPI is disabled to edit CFG1 register */ - if ((hspi->Instance->CR1 & SPI_CR1_SPE) != SPI_CR1_SPE) - { - /* Configure Underrun fields */ - MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); - } - else - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - - /* Configure Underrun fields */ - MODIFY_REG(hspi->Instance->CFG1, SPI_CFG1_UDRCFG, UnderrunBehaviour); - - /* Enable SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - } - - - hspi->State = HAL_SPI_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; -} - -/** - * @brief Set Autonomous Mode configuration - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPIx peripheral. - * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information of the autonomous mode for the specified SPIx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPIEx_SetConfigAutonomousMode(SPI_HandleTypeDef *hspi, - const SPI_AutonomousModeConfTypeDef *sConfig) -{ - if (hspi->State == HAL_SPI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hspi); - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); - assert_param(IS_SPI_TRIG_SOURCE(hspi->Instance, sConfig->TriggerSelection)); - assert_param(IS_SPI_AUTO_MODE_TRG_POL(sConfig->TriggerPolarity)); - - /* Disable the selected SPI peripheral to be able to configure AUTOCR */ - __HAL_SPI_DISABLE(hspi); - - /* SPIx AUTOCR Configuration */ - WRITE_REG(hspi->Instance->AUTOCR, (sConfig->TriggerState | ((sConfig->TriggerSelection) & SPI_AUTOCR_TRIGSEL_Msk) | - sConfig->TriggerPolarity)); - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Get Autonomous Mode configuration - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPIx peripheral. - * @param sConfig Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information of the autonomous mode for the specified SPIx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPIEx_GetConfigAutonomousMode(const SPI_HandleTypeDef *hspi, - SPI_AutonomousModeConfTypeDef *sConfig) -{ - uint32_t autocr_tmp; - - /* Check the parameters */ - assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); - - autocr_tmp = hspi->Instance->AUTOCR; - - sConfig->TriggerState = (autocr_tmp & SPI_AUTOCR_TRIGEN); -#if defined(SPI_TRIG_GRP2) - if (IS_SPI_GRP2_INSTANCE(hspi->Instance)) - { - sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP2); - } - else - { - sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); - } -#else - sConfig->TriggerSelection = ((autocr_tmp & SPI_AUTOCR_TRIGSEL) | SPI_TRIG_GRP1); -#endif /* SPI_TRIG_GRP2 */ - sConfig->TriggerPolarity = (autocr_tmp & SPI_AUTOCR_TRIGPOL); - - return HAL_OK; -} - -/** - * @brief Clear Autonomous Mode configuration - * @param hspi Pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for the specified SPIx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_SPIEx_ClearConfigAutonomousMode(SPI_HandleTypeDef *hspi) -{ - if (hspi->State == HAL_SPI_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(hspi); - - hspi->State = HAL_SPI_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_SPI_AUTONOMOUS_INSTANCE(hspi->Instance)); - - /* Disable the selected SPI peripheral to be able to clear AUTOCR */ - __HAL_SPI_DISABLE(hspi); - - CLEAR_REG(hspi->Instance->AUTOCR); - - /* Enable the selected SPI peripheral */ - __HAL_SPI_ENABLE(hspi); - - hspi->State = HAL_SPI_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - - return HAL_OK; - } - else - { - return HAL_ERROR; - } -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_SPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c deleted file mode 100644 index 97eadff42..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim.c +++ /dev/null @@ -1,8262 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_tim.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer (TIM) peripheral: - * + TIM Time Base Initialization - * + TIM Time Base Start - * + TIM Time Base Start Interruption - * + TIM Time Base Start DMA - * + TIM Output Compare/PWM Initialization - * + TIM Output Compare/PWM Channel Configuration - * + TIM Output Compare/PWM Start - * + TIM Output Compare/PWM Start Interruption - * + TIM Output Compare/PWM Start DMA - * + TIM Input Capture Initialization - * + TIM Input Capture Channel Configuration - * + TIM Input Capture Start - * + TIM Input Capture Start Interruption - * + TIM Input Capture Start DMA - * + TIM One Pulse Initialization - * + TIM One Pulse Channel Configuration - * + TIM One Pulse Start - * + TIM Encoder Interface Initialization - * + TIM Encoder Interface Start - * + TIM Encoder Interface Start Interruption - * + TIM Encoder Interface Start DMA - * + Commutation Event configuration with Interruption and DMA - * + TIM OCRef clear configuration - * + TIM External Clock configuration - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### TIMER Generic features ##### - ============================================================================== - [..] The Timer features include: - (#) 16-bit up, down, up/down auto-reload counter. - (#) 16-bit programmable prescaler allowing dividing (also on the fly) the - counter clock frequency either by any factor between 1 and 65536. - (#) Up to 4 independent channels for: - (++) Input Capture - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to interconnect - several timers together. - (#) Supports incremental encoder for positioning purposes - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Time Base : HAL_TIM_Base_MspInit() - (++) Input Capture : HAL_TIM_IC_MspInit() - (++) Output Compare : HAL_TIM_OC_MspInit() - (++) PWM generation : HAL_TIM_PWM_MspInit() - (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit() - (++) Encoder mode output : HAL_TIM_Encoder_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - Initialization function of this driver: - (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base - (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare: - to use the Timer to generate an Output Compare signal. - (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a - PWM signal. - (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an - external signal. - (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer - in One Pulse Mode. - (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface. - - (#) Activate the TIM peripheral using one of the start functions depending from the feature used: - (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT() - (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT() - (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT() - (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT() - (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT() - (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT(). - - (#) The DMA Burst is managed with the two following functions: - HAL_TIM_DMABurst_WriteStart() - HAL_TIM_DMABurst_ReadStart() - - *** Callback registration *** - ============================================= - - [..] - The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_TIM_RegisterCallback() to register a callback. - HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, - the Callback ID and a pointer to the user callback function. - - [..] - Use function HAL_TIM_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - - [..] - These functions allow to register/unregister following callbacks: - (+) Base_MspInitCallback : TIM Base Msp Init Callback. - (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. - (+) IC_MspInitCallback : TIM IC Msp Init Callback. - (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback. - (+) OC_MspInitCallback : TIM OC Msp Init Callback. - (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback. - (+) PWM_MspInitCallback : TIM PWM Msp Init Callback. - (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback. - (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback. - (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback. - (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback. - (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback. - (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback. - (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback. - (+) PeriodElapsedCallback : TIM Period Elapsed Callback. - (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback. - (+) TriggerCallback : TIM Trigger Callback. - (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback. - (+) IC_CaptureCallback : TIM Input Capture Callback. - (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback. - (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback. - (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback. - (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback. - (+) ErrorCallback : TIM Error Callback. - (+) CommutationCallback : TIM Commutation Callback. - (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback. - (+) BreakCallback : TIM Break Callback. - (+) Break2Callback : TIM Break2 Callback. - (+) EncoderIndexCallback : TIM Encoder Index Callback. - (+) DirectionChangeCallback : TIM Direction Change Callback - (+) IndexErrorCallback : TIM Index Error Callback. - (+) TransitionErrorCallback : TIM Transition Error Callback - - [..] -By default, after the Init and when the state is HAL_TIM_STATE_RESET -all interrupt callbacks are set to the corresponding weak functions: - examples HAL_TIM_TriggerCallback(), HAL_TIM_ErrorCallback(). - - [..] - Exception done for MspInit and MspDeInit functions that are reset to the legacy weak - functionalities in the Init / DeInit only when these callbacks are null - (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit - keep and use the user MspInit / MspDeInit callbacks(registered beforehand) - - [..] - Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. - Exception done MspInit / MspDeInit that can be registered / unregistered - in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, - thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_TIM_RegisterCallback() before calling DeInit or Init function. - - [..] - When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup TIM TIM - * @brief TIM HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @addtogroup TIM_Private_Constants - * @{ - */ -#define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL - -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup TIM_Private_Functions - * @{ - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config); -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter); -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter); -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource); -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - const TIM_SlaveConfigTypeDef *sSlaveConfig); -/** - * @} - */ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup TIM_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions - * @brief Time Base functions - * -@verbatim - ============================================================================== - ##### Time Base functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM base. - (+) De-initialize the TIM base. - (+) Start the Time Base. - (+) Stop the Time Base. - (+) Start the Time Base and enable interrupt. - (+) Stop the Time Base and disable interrupt. - (+) Start the Time Base and enable DMA transfer. - (+) Stop the Time Base and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Time base Unit according to the specified - * parameters in the TIM_HandleTypeDef and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init() - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Base_MspInitCallback == NULL) - { - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Base_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the Time Base configuration */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Base peripheral - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Base_MspDeInitCallback == NULL) - { - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Base_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Base_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Base MSP. - * @param htim TIM Base handle - * @retval None - */ -__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Base_MspDeInit could be implemented in the user file - */ -} - - -/** - * @brief Starts the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Check the TIM state */ - if (htim->State != HAL_TIM_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Enable the TIM Update interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in interrupt mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - /* Disable the TIM Update interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, const uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Set the TIM state */ - if (htim->State == HAL_TIM_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->State == HAL_TIM_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - htim->State = HAL_TIM_STATE_BUSY; - } - } - else - { - return HAL_ERROR; - } - - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Update DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Base generation in DMA mode. - * @param htim TIM Base handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions - * @brief TIM Output Compare functions - * -@verbatim - ============================================================================== - ##### TIM Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Output Compare. - (+) De-initialize the TIM Output Compare. - (+) Start the TIM Output Compare. - (+) Stop the TIM Output Compare. - (+) Start the TIM Output Compare and enable interrupt. - (+) Stop the TIM Output Compare and disable interrupt. - (+) Start the TIM Output Compare and enable DMA transfer. - (+) Stop the TIM Output Compare and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Output Compare according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init() - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OC_MspInitCallback == NULL) - { - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the Output Compare */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Output Compare handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OC_MspDeInitCallback == NULL) - { - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Output Compare MSP. - * @param htim TIM Output Compare handle - * @retval None - */ -__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Output compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions - * @brief TIM PWM functions - * -@verbatim - ============================================================================== - ##### TIM PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM PWM. - (+) De-initialize the TIM PWM. - (+) Start the TIM PWM. - (+) Stop the TIM PWM. - (+) Start the TIM PWM and enable interrupt. - (+) Stop the TIM PWM and disable interrupt. - (+) Start the TIM PWM and enable DMA transfer. - (+) Stop the TIM PWM and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM PWM Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init() - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->PWM_MspInitCallback == NULL) - { - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->PWM_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the PWM */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM PWM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->PWM_MspDeInitCallback == NULL) - { - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - } - /* DeInit the low level hardware */ - htim->PWM_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_PWM_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM PWM MSP. - * @param htim TIM PWM handle - * @retval None - */ -__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the PWM signal generation. - * @param htim TIM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Set the TIM channel state */ - if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Capture/Compare 3 request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim TIM PWM handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions - * @brief TIM Input Capture functions - * -@verbatim - ============================================================================== - ##### TIM Input Capture functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Input Capture. - (+) De-initialize the TIM Input Capture. - (+) Start the TIM Input Capture. - (+) Stop the TIM Input Capture. - (+) Start the TIM Input Capture and enable interrupt. - (+) Stop the TIM Input Capture and disable interrupt. - (+) Start the TIM Input Capture and enable DMA transfer. - (+) Stop the TIM Input Capture and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Input Capture Time base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init() - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->IC_MspInitCallback == NULL) - { - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->IC_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Init the base time for the input capture */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM peripheral - * @param htim TIM Input Capture handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->IC_MspDeInitCallback == NULL) - { - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - } - /* DeInit the low level hardware */ - htim->IC_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_IC_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Input Capture MSP. - * @param htim TIM Input Capture handle - * @retval None - */ -__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Input Capture MSP. - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Input Capture measurement. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - /* Check the TIM channel state */ - if ((channel_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel); - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Input Capture measurement in DMA mode. - * @param htim TIM Input Capture handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel)); - assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel */ - TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions - * @brief TIM One Pulse functions - * -@verbatim - ============================================================================== - ##### TIM One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM One Pulse. - (+) De-initialize the TIM One Pulse. - (+) Start the TIM One Pulse. - (+) Stop the TIM One Pulse. - (+) Start the TIM One Pulse and enable interrupt. - (+) Stop the TIM One Pulse and disable interrupt. - (+) Start the TIM One Pulse and enable DMA transfer. - (+) Stop the TIM One Pulse and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM One Pulse Time Base according to the specified - * parameters in the TIM_HandleTypeDef and initializes the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init() - * @note When the timer instance is initialized in One Pulse mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM One Pulse handle - * @param OnePulseMode Select the One pulse mode. - * This parameter can be one of the following values: - * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. - * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode) -{ - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_OPM_MODE(OnePulseMode)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->OnePulse_MspInitCallback == NULL) - { - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->OnePulse_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_OnePulse_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the One Pulse Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Reset the OPM Bit */ - htim->Instance->CR1 &= ~TIM_CR1_OPM; - - /* Configure the OPM Mode */ - htim->Instance->CR1 |= OnePulseMode; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM One Pulse - * @param htim TIM One Pulse handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->OnePulse_MspDeInitCallback == NULL) - { - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - } - /* DeInit the low level hardware */ - htim->OnePulse_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_OnePulse_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM One Pulse MSP. - * @param htim TIM One Pulse handle - * @retval None - */ -__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together - - No need to enable the counter, it's enabled automatically by hardware - (the counter starts in response to a stimulus and generate a pulse */ - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Enable the main output */ - __HAL_TIM_MOE_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @note Though OutputChannel parameter is deprecated and ignored by the function - * it has been kept to avoid HAL_TIM API compatibility break. - * @note The pulse output channel is determined when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel See note above - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(OutputChannel); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the Capture compare and the Input Capture channels - (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) - if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and - if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output - whatever the combination, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET) - { - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions - * @brief TIM Encoder functions - * -@verbatim - ============================================================================== - ##### TIM Encoder functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure the TIM Encoder. - (+) De-initialize the TIM Encoder. - (+) Start the TIM Encoder. - (+) Stop the TIM Encoder. - (+) Start the TIM Encoder and enable interrupt. - (+) Stop the TIM Encoder and disable interrupt. - (+) Start the TIM Encoder and enable DMA transfer. - (+) Stop the TIM Encoder and disable DMA transfer. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Encoder Interface and initialize the associated handle. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init() - * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together - * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource - * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa - * @note When the timer instance is initialized in Encoder mode, timer - * channels 1 and channel 2 are reserved and cannot be used for other - * purpose. - * @param htim TIM Encoder Interface handle - * @param sConfig TIM Encoder Interface configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig) -{ - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); - assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy weak callbacks */ - TIM_ResetCallback(htim); - - if (htim->Encoder_MspInitCallback == NULL) - { - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->Encoder_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIM_Encoder_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Reset the SMS and ECE bits */ - htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE); - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = htim->Instance->CCMR1; - - /* Get the TIMx CCER register value */ - tmpccer = htim->Instance->CCER; - - /* Set the encoder Mode */ - tmpsmcr |= sConfig->EncoderMode; - - /* Select the Capture Compare 1 and the Capture Compare 2 as input */ - tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S); - tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U)); - - /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */ - tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC); - tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F); - tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U); - tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U); - - /* Set the TI1 and the TI2 Polarities */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P); - tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP); - tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U); - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Write to TIMx CCMR1 */ - htim->Instance->CCMR1 = tmpccmr1; - - /* Write to TIMx CCER */ - htim->Instance->CCER = tmpccer; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - - -/** - * @brief DeInitializes the TIM Encoder interface - * @param htim TIM Encoder Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->Encoder_MspDeInitCallback == NULL) - { - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - } - /* DeInit the low level hardware */ - htim->Encoder_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIM_Encoder_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim TIM Encoder Interface handle - * @retval None - */ -__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_Encoder_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - break; - } - } - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - break; - } - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - - /* Enable the encoder interface channels */ - /* Enable the capture compare Interrupts 1 and/or 2 */ - switch (Channel) - { - case TIM_CHANNEL_1: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - default : - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - } - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts 1 and 2 */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1 The destination Buffer address for IC1. - * @param pData2 The destination Buffer address for IC2. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, - uint32_t *pData2, uint16_t Length) -{ - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel(s) state */ - if (Channel == TIM_CHANNEL_1) - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData1 == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else if (Channel == TIM_CHANNEL_2) - { - if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData2 == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - else - { - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((((pData1 == NULL) || (pData2 == NULL))) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError; - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - - default: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - /* Enable the TIM Input Capture DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - - /* Enable the Capture compare channel */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE); - - /* Enable the Peripheral */ - __HAL_TIM_ENABLE(htim); - - break; - } - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim TIM Encoder Interface handle - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1 and 2 - (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */ - if (Channel == TIM_CHANNEL_1) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - } - else if (Channel == TIM_CHANNEL_2) - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - else - { - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE); - - /* Disable the capture compare DMA Request 1 and 2 */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - } - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel(s) state */ - if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2)) - { - TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ -/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management - * @brief TIM IRQ handler management - * -@verbatim - ============================================================================== - ##### IRQ handler management ##### - ============================================================================== - [..] - This section provides Timer IRQ handler function. - -@endverbatim - * @{ - */ -/** - * @brief This function handles TIM interrupts requests. - * @param htim TIM handle - * @retval None - */ -void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim) -{ - uint32_t itsource = htim->Instance->DIER; - uint32_t itflag = htim->Instance->SR; - - /* Capture compare 1 event */ - if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1)) - { - if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1)) - { - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - } - /* Capture compare 2 event */ - if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2)) - { - if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - /* Input capture event */ - if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 3 event */ - if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3)) - { - if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* Capture compare 4 event */ - if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4)) - { - if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4); - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - /* Input capture event */ - if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U) - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - /* Output compare event */ - else - { -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->OC_DelayElapsedCallback(htim); - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_OC_DelayElapsedCallback(htim); - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; - } - } - /* TIM Update event */ - if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE)) - { - if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break input event */ - if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \ - ((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK))) - { - if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->BreakCallback(htim); -#else - HAL_TIMEx_BreakCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Break2 input event */ - if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2)) - { - if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->Break2Callback(htim); -#else - HAL_TIMEx_Break2Callback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Trigger detection event */ - if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER)) - { - if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM commutation event */ - if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM)) - { - if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Encoder index event */ - if ((itflag & (TIM_FLAG_IDX)) == (TIM_FLAG_IDX)) - { - if ((itsource & (TIM_IT_IDX)) == (TIM_IT_IDX)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IDX); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->EncoderIndexCallback(htim); -#else - HAL_TIMEx_EncoderIndexCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Direction change event */ - if ((itflag & (TIM_FLAG_DIR)) == (TIM_FLAG_DIR)) - { - if ((itsource & (TIM_IT_DIR)) == (TIM_IT_DIR)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_DIR); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->DirectionChangeCallback(htim); -#else - HAL_TIMEx_DirectionChangeCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Index error event */ - if ((itflag & (TIM_FLAG_IERR)) == (TIM_FLAG_IERR)) - { - if ((itsource & (TIM_IT_IERR)) == (TIM_IT_IERR)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_IERR); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IndexErrorCallback(htim); -#else - HAL_TIMEx_IndexErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } - /* TIM Transition error event */ - if ((itflag & (TIM_FLAG_TERR)) == (TIM_FLAG_TERR)) - { - if ((itsource & (TIM_IT_TERR)) == (TIM_IT_TERR)) - { - __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TERR); -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TransitionErrorCallback(htim); -#else - HAL_TIMEx_TransitionErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - } -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions - * @brief TIM Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode. - (+) Configure External Clock source. - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master and the Slave synchronization. - (+) Configure the DMA Burst Mode. - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the TIM Output Compare Channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM Output Compare handle - * @param sConfig TIM Output Compare configuration structure - * @param Channel TIM Channels to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, - const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 1 in Output Compare */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 2 in Output Compare */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 3 in Output Compare */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 4 in Output Compare */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 5 in Output Compare */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - break; - } - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the TIM Channel 6 in Output Compare */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - break; - } - - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM Input Capture Channels according to the specified - * parameters in the TIM_IC_InitTypeDef. - * @param htim TIM IC handle - * @param sConfig TIM Input Capture configuration structure - * @param Channel TIM Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, const TIM_IC_InitTypeDef *sConfig, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity)); - assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter)); - - /* Process Locked */ - __HAL_LOCK(htim); - - if (Channel == TIM_CHANNEL_1) - { - /* TI1 Configuration */ - TIM_TI1_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_2) - { - /* TI2 Configuration */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Set the IC2PSC value */ - htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U); - } - else if (Channel == TIM_CHANNEL_3) - { - /* TI3 Configuration */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - TIM_TI3_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC3PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC; - - /* Set the IC3PSC value */ - htim->Instance->CCMR2 |= sConfig->ICPrescaler; - } - else if (Channel == TIM_CHANNEL_4) - { - /* TI4 Configuration */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - TIM_TI4_SetConfig(htim->Instance, - sConfig->ICPolarity, - sConfig->ICSelection, - sConfig->ICFilter); - - /* Reset the IC4PSC Bits */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC; - - /* Set the IC4PSC value */ - htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U); - } - else - { - status = HAL_ERROR; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM PWM channels according to the specified - * parameters in the TIM_OC_InitTypeDef. - * @param htim TIM PWM handle - * @param sConfig TIM PWM configuration structure - * @param Channel TIM Channels to be configured - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, - const TIM_OC_InitTypeDef *sConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CHANNELS(Channel)); - assert_param(IS_TIM_PWM_MODE(sConfig->OCMode)); - assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity)); - assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode)); - - /* Process Locked */ - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Configure the Channel 1 in PWM mode */ - TIM_OC1_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel1 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Configure the Channel 2 in PWM mode */ - TIM_OC2_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel2 */ - htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE; - htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Configure the Channel 3 in PWM mode */ - TIM_OC3_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel3 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Configure the Channel 4 in PWM mode */ - TIM_OC4_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel4 */ - htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE; - htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U; - break; - } - - case TIM_CHANNEL_5: - { - /* Check the parameters */ - assert_param(IS_TIM_CC5_INSTANCE(htim->Instance)); - - /* Configure the Channel 5 in PWM mode */ - TIM_OC5_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel5*/ - htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode; - break; - } - - case TIM_CHANNEL_6: - { - /* Check the parameters */ - assert_param(IS_TIM_CC6_INSTANCE(htim->Instance)); - - /* Configure the Channel 6 in PWM mode */ - TIM_OC6_SetConfig(htim->Instance, sConfig); - - /* Set the Preload enable bit for channel6 */ - htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE; - - /* Configure the Output Fast mode */ - htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE; - htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U; - break; - } - - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Initializes the TIM One Pulse Channels according to the specified - * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim TIM One Pulse handle - * @param sConfig TIM One Pulse configuration structure - * @param OutputChannel TIM output channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel TIM input Channel to configure - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @note To output a waveform with a minimum delay user can enable the fast - * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx - * output is forced in response to the edge detection on TIx input, - * without taking in account the comparison. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, - uint32_t OutputChannel, uint32_t InputChannel) -{ - HAL_StatusTypeDef status = HAL_OK; - TIM_OC_InitTypeDef temp1; - - /* Check the parameters */ - assert_param(IS_TIM_OPM_CHANNELS(OutputChannel)); - assert_param(IS_TIM_OPM_CHANNELS(InputChannel)); - - if (OutputChannel != InputChannel) - { - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Extract the Output compare configuration from sConfig structure */ - temp1.OCMode = sConfig->OCMode; - temp1.Pulse = sConfig->Pulse; - temp1.OCPolarity = sConfig->OCPolarity; - temp1.OCNPolarity = sConfig->OCNPolarity; - temp1.OCIdleState = sConfig->OCIdleState; - temp1.OCNIdleState = sConfig->OCNIdleState; - - switch (OutputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_OC1_SetConfig(htim->Instance, &temp1); - break; - } - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_OC2_SetConfig(htim->Instance, &temp1); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - switch (InputChannel) - { - case TIM_CHANNEL_1: - { - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1FP1; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - case TIM_CHANNEL_2: - { - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity, - sConfig->ICSelection, sConfig->ICFilter); - - /* Reset the IC2PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC; - - /* Select the Trigger source */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI2FP2; - - /* Select the Slave Mode */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER; - break; - } - - default: - status = HAL_ERROR; - break; - } - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_DTR2 - * @arg TIM_DMABASE_ECR - * @arg TIM_DMABASE_TISEL - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 - * @arg TIM_DMABASE_OR1 - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t BlockDataLength = 0; - uint32_t data_width; - const DMA_HandleTypeDef *hdma = NULL; - - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - hdma = htim->hdma[TIM_DMA_ID_UPDATE]; - break; - } - case TIM_DMA_CC1: - { - hdma = htim->hdma[TIM_DMA_ID_CC1]; - break; - } - case TIM_DMA_CC2: - { - hdma = htim->hdma[TIM_DMA_ID_CC2]; - break; - } - case TIM_DMA_CC3: - { - hdma = htim->hdma[TIM_DMA_ID_CC3]; - break; - } - case TIM_DMA_CC4: - { - hdma = htim->hdma[TIM_DMA_ID_CC4]; - break; - } - case TIM_DMA_COM: - { - hdma = htim->hdma[TIM_DMA_ID_COMMUTATION]; - break; - } - case TIM_DMA_TRIGGER: - { - hdma = htim->hdma[TIM_DMA_ID_TRIGGER]; - break; - } - default: - status = HAL_ERROR; - break; - } - - if (hdma != NULL) - { - - if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U) - && (hdma->LinkedListQueue->Head != 0U)) - { - data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; - } - else - { - data_width = hdma->Init.SrcDataWidth; - } - - switch (data_width) - { - case DMA_SRC_DATAWIDTH_BYTE: - { - BlockDataLength = (BurstLength >> TIM_DCR_DBL_Pos) + 1UL; - break; - } - case DMA_SRC_DATAWIDTH_HALFWORD: - { - BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL; - break; - } - case DMA_SRC_DATAWIDTH_WORD: - { - BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL; - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - status = HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - BlockDataLength); - } - } - - - return status; -} - -/** - * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_DTR2 - * @arg TIM_DMABASE_ECR - * @arg TIM_DMABASE_TISEL - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 - * @arg TIM_DMABASE_OR1 - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpDBSS = 0; - - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = TIM_DCR_DBSS_0; - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = TIM_DCR_DBSS_1; - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = TIM_DCR_DBSS_2; - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, - (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS); - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM DMA Burst mode - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_DTR2 - * @arg TIM_DMABASE_ECR - * @arg TIM_DMABASE_TISEL - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 - * @arg TIM_DMABASE_OR1 - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. - * @note This function should be used only when BurstLength is equal to DMA data transfer length. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t BlockDataLength = 0; - uint32_t data_width; - const DMA_HandleTypeDef *hdma = NULL; - - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - hdma = htim->hdma[TIM_DMA_ID_UPDATE]; - break; - } - case TIM_DMA_CC1: - { - hdma = htim->hdma[TIM_DMA_ID_CC1]; - break; - } - case TIM_DMA_CC2: - { - hdma = htim->hdma[TIM_DMA_ID_CC2]; - break; - } - case TIM_DMA_CC3: - { - hdma = htim->hdma[TIM_DMA_ID_CC3]; - break; - } - case TIM_DMA_CC4: - { - hdma = htim->hdma[TIM_DMA_ID_CC4]; - break; - } - case TIM_DMA_COM: - { - hdma = htim->hdma[TIM_DMA_ID_COMMUTATION]; - break; - } - case TIM_DMA_TRIGGER: - { - hdma = htim->hdma[TIM_DMA_ID_TRIGGER]; - break; - } - default: - status = HAL_ERROR; - break; - } - - if (hdma != NULL) - { - - if (((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) && (hdma->LinkedListQueue != 0U) - && (hdma->LinkedListQueue->Head != 0U)) - { - data_width = hdma->LinkedListQueue->Head->LinkRegisters[0] & DMA_CTR1_SDW_LOG2; - } - else - { - data_width = hdma->Init.SrcDataWidth; - } - - switch (data_width) - - { - case DMA_SRC_DATAWIDTH_BYTE: - { - BlockDataLength = ((BurstLength) >> TIM_DCR_DBL_Pos) + 1UL; - break; - } - case DMA_SRC_DATAWIDTH_HALFWORD: - { - BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 2UL; - break; - } - case DMA_SRC_DATAWIDTH_WORD: - { - BlockDataLength = ((BurstLength >> TIM_DCR_DBL_Pos) + 1UL) * 4UL; - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - status = HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength, - BlockDataLength); - } - } - - return status; -} - -/** - * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim TIM handle - * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read - * This parameter can be one of the following values: - * @arg TIM_DMABASE_CR1 - * @arg TIM_DMABASE_CR2 - * @arg TIM_DMABASE_SMCR - * @arg TIM_DMABASE_DIER - * @arg TIM_DMABASE_SR - * @arg TIM_DMABASE_EGR - * @arg TIM_DMABASE_CCMR1 - * @arg TIM_DMABASE_CCMR2 - * @arg TIM_DMABASE_CCER - * @arg TIM_DMABASE_CNT - * @arg TIM_DMABASE_PSC - * @arg TIM_DMABASE_ARR - * @arg TIM_DMABASE_RCR - * @arg TIM_DMABASE_CCR1 - * @arg TIM_DMABASE_CCR2 - * @arg TIM_DMABASE_CCR3 - * @arg TIM_DMABASE_CCR4 - * @arg TIM_DMABASE_BDTR - * @arg TIM_DMABASE_CCMR3 - * @arg TIM_DMABASE_CCR5 - * @arg TIM_DMABASE_CCR6 - * @arg TIM_DMABASE_DTR2 - * @arg TIM_DMABASE_ECR - * @arg TIM_DMABASE_TISEL - * @arg TIM_DMABASE_AF1 - * @arg TIM_DMABASE_AF2 - * @arg TIM_DMABASE_OR1 - * @param BurstRequestSrc TIM DMA Request sources - * This parameter can be one of the following values: - * @arg TIM_DMA_UPDATE: TIM update Interrupt source - * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source - * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source - * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source - * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source - * @arg TIM_DMA_COM: TIM Commutation DMA source - * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer The Buffer address. - * @param BurstLength DMA Burst length. This parameter can be one value - * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER. - * @param DataLength Data length. This parameter can be one value - * between 1 and 0xFFFF. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, uint32_t *BurstBuffer, - uint32_t BurstLength, uint32_t DataLength) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpDBSS = 0; - - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DMA_BASE(BurstBaseAddress)); - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength)); - - if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY) - { - return HAL_BUSY; - } - else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY) - { - if ((BurstBuffer == NULL) && (BurstLength > 0U)) - { - return HAL_ERROR; - } - else - { - htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY; - } - } - else - { - /* nothing to do */ - } - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - /* Set the DMA Period elapsed callbacks */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt; - htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = TIM_DCR_DBSS_0; - break; - } - case TIM_DMA_CC1: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = TIM_DCR_DBSS_1; - break; - } - case TIM_DMA_CC2: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); - break; - } - case TIM_DMA_CC3: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = TIM_DCR_DBSS_2; - break; - } - case TIM_DMA_CC4: - { - /* Set the DMA capture callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_0); - break; - } - case TIM_DMA_COM: - { - /* Set the DMA commutation callbacks */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1); - break; - } - case TIM_DMA_TRIGGER: - { - /* Set the DMA trigger callbacks */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt; - htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, - DataLength) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Configure the DMA Burst Source Selection */ - tmpDBSS = (TIM_DCR_DBSS_2 | TIM_DCR_DBSS_1 | TIM_DCR_DBSS_0); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Configure the DMA Burst Mode */ - htim->Instance->DCR = (BurstBaseAddress | BurstLength | tmpDBSS); - - /* Enable the TIM DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc); - } - - /* Return function status */ - return status; -} - -/** - * @brief Stop the DMA burst reading - * @param htim TIM handle - * @param BurstRequestSrc TIM DMA Request sources to disable. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); - - /* Abort the DMA transfer (at least disable the DMA channel) */ - switch (BurstRequestSrc) - { - case TIM_DMA_UPDATE: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]); - break; - } - case TIM_DMA_CC1: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - case TIM_DMA_CC2: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - case TIM_DMA_CC3: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - case TIM_DMA_CC4: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - case TIM_DMA_COM: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]); - break; - } - case TIM_DMA_TRIGGER: - { - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]); - break; - } - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the TIM Update DMA request */ - __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc); - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - } - - /* Return function status */ - return status; -} - -/** - * @brief Generate a software event - * @param htim TIM handle - * @param EventSource specifies the event source. - * This parameter can be one of the following values: - * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source - * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source - * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source - * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source - * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source - * @arg TIM_EVENTSOURCE_COM: Timer COM event source - * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source - * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source - * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source - * @note Basic timers can only generate an update event. - * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances. - * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant - * only for timer instances supporting break input(s). - * @retval HAL status - */ - -HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_EVENT_SOURCE(EventSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Set the event sources */ - htim->Instance->EGR = EventSource; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Configures the OCRef clear feature - * @param htim TIM handle - * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that - * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, - const TIM_ClearInputConfigTypeDef *sClearInputConfig, - uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - switch (sClearInputConfig->ClearInputSource) - { - case TIM_CLEARINPUTSOURCE_NONE: - { - /* Clear the OCREF clear selection bit and the the ETR Bits */ - CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP)); - break; - } - - case TIM_CLEARINPUTSOURCE_COMP1: -#if defined(COMP2) - case TIM_CLEARINPUTSOURCE_COMP2: -#endif /* COMP2 */ - { - /* Clear the OCREF clear selection bit */ - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - - /* Set the clear input source */ - MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource); - break; - } - - case TIM_CLEARINPUTSOURCE_ETR: - { - /* Check the parameters */ - assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity)); - assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler)); - assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter)); - - /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ - if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - TIM_ETR_SetConfig(htim->Instance, - sClearInputConfig->ClearInputPrescaler, - sClearInputConfig->ClearInputPolarity, - sClearInputConfig->ClearInputFilter); - - /* Set the OCREF clear selection bit */ - SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS); - - /* Clear TIMx_AF2_OCRSEL (reset value) */ - CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - switch (Channel) - { - case TIM_CHANNEL_1: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 1 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - else - { - /* Disable the OCREF clear feature for Channel 1 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE); - } - break; - } - case TIM_CHANNEL_2: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 2 */ - SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - else - { - /* Disable the OCREF clear feature for Channel 2 */ - CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE); - } - break; - } - case TIM_CHANNEL_3: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 3 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - else - { - /* Disable the OCREF clear feature for Channel 3 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE); - } - break; - } - case TIM_CHANNEL_4: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 4 */ - SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - else - { - /* Disable the OCREF clear feature for Channel 4 */ - CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE); - } - break; - } - case TIM_CHANNEL_5: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 5 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); - } - else - { - /* Disable the OCREF clear feature for Channel 5 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE); - } - break; - } - case TIM_CHANNEL_6: - { - if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE) - { - /* Enable the OCREF clear feature for Channel 6 */ - SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); - } - else - { - /* Disable the OCREF clear feature for Channel 6 */ - CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE); - } - break; - } - default: - break; - } - } - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Configures the clock source to be used - * @param htim TIM handle - * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that - * contains the clock source information for the TIM peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, const TIM_ClockConfigTypeDef *sClockSourceConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource)); - - /* Reset the SMS, TS, ECE, ETPS and ETRF bits */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS); - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - htim->Instance->SMCR = tmpsmcr; - - switch (sClockSourceConfig->ClockSource) - { - case TIM_CLOCKSOURCE_INTERNAL: - { - assert_param(IS_TIM_INSTANCE(htim->Instance)); - break; - } - - case TIM_CLOCKSOURCE_ETRMODE1: - { - /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - - /* Select the External clock mode1 and the ETRF trigger */ - tmpsmcr = htim->Instance->SMCR; - tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1); - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - break; - } - - case TIM_CLOCKSOURCE_ETRMODE2: - { - /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance)); - - /* Check ETR input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler)); - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - /* Configure the ETR Clock source */ - TIM_ETR_SetConfig(htim->Instance, - sClockSourceConfig->ClockPrescaler, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - /* Enable the External clock mode2 */ - htim->Instance->SMCR |= TIM_SMCR_ECE; - break; - } - - case TIM_CLOCKSOURCE_TI1: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1); - break; - } - - case TIM_CLOCKSOURCE_TI2: - { - /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI2 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI2_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2); - break; - } - - case TIM_CLOCKSOURCE_TI1ED: - { - /* Check whether or not the timer instance supports external clock mode 1 */ - assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance)); - - /* Check TI1 input conditioning related parameters */ - assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity)); - assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter)); - - TIM_TI1_ConfigInputStage(htim->Instance, - sClockSourceConfig->ClockPolarity, - sClockSourceConfig->ClockFilter); - TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED); - break; - } - - case TIM_CLOCKSOURCE_ITR0: - case TIM_CLOCKSOURCE_ITR1: - case TIM_CLOCKSOURCE_ITR2: - case TIM_CLOCKSOURCE_ITR3: - case TIM_CLOCKSOURCE_ITR4: - case TIM_CLOCKSOURCE_ITR5: - case TIM_CLOCKSOURCE_ITR6: - case TIM_CLOCKSOURCE_ITR7: - case TIM_CLOCKSOURCE_ITR8: - case TIM_CLOCKSOURCE_ITR11: - { - /* Check whether or not the timer instance supports internal trigger input */ - assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource)); - - TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource); - break; - } - - default: - status = HAL_ERROR; - break; - } - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Selects the signal connected to the TI1 input: direct from CH1_input - * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim TIM handle. - * @param TI1_Selection Indicate whether or not channel 1 is connected to the - * output of a XOR gate. - * This parameter can be one of the following values: - * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input - * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3 - * pins are connected to the TI1 input (XOR combination) - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection) -{ - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TI1SELECTION(TI1_Selection)); - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Reset the TI1 selection */ - tmpcr2 &= ~TIM_CR2_TI1S; - - /* Set the TI1 selection */ - tmpcr2 |= TI1_Selection; - - /* Write to TIMxCR2 */ - htim->Instance->CR2 = tmpcr2; - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Disable Trigger Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim TIM handle. - * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that - * contains the selected trigger (internal trigger input, filtered - * timer input or external trigger input) and the Slave mode - * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, - const TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode)); - assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger)); - - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) - { - htim->State = HAL_TIM_STATE_READY; - __HAL_UNLOCK(htim); - return HAL_ERROR; - } - - /* Enable Trigger Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER); - - /* Disable Trigger DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER); - - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Read the captured value from Capture Compare unit - * @param htim TIM handle. - * @param Channel TIM Channels to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval Captured value - */ -uint32_t HAL_TIM_ReadCapturedValue(const TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpreg = 0U; - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - - /* Return the capture 1 value */ - tmpreg = htim->Instance->CCR1; - - break; - } - case TIM_CHANNEL_2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - - /* Return the capture 2 value */ - tmpreg = htim->Instance->CCR2; - - break; - } - - case TIM_CHANNEL_3: - { - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(htim->Instance)); - - /* Return the capture 3 value */ - tmpreg = htim->Instance->CCR3; - - break; - } - - case TIM_CHANNEL_4: - { - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(htim->Instance)); - - /* Return the capture 4 value */ - tmpreg = htim->Instance->CCR4; - - break; - } - - default: - break; - } - - return tmpreg; -} - -/** - * @brief Start the DMA data transfer. - * @param hdma DMA handle - * @param src : The source memory Buffer address. - * @param dst : The destination memory Buffer address. - * @param length : The size of a source block transfer in byte. - * @retval HAL status - */ -HAL_StatusTypeDef TIM_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t src, uint32_t dst, - uint32_t length) -{ - HAL_StatusTypeDef status ; - - /* Enable the DMA channel */ - if ((hdma->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if ((hdma->LinkedListQueue != 0U) && (hdma->LinkedListQueue->Head != 0U)) - { - /* Enable the DMA channel */ - hdma->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = length; - hdma->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = src; - hdma->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = dst; - - status = HAL_DMAEx_List_Start_IT(hdma); - } - else - { - status = HAL_ERROR; - } - } - else - { - status = HAL_DMA_Start_IT(hdma, src, dst, length); - } - - return status; -} - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions - * @brief TIM Callbacks functions - * -@verbatim - ============================================================================== - ##### TIM Callbacks functions ##### - ============================================================================== - [..] - This section provides TIM callback functions: - (+) TIM Period elapsed callback - (+) TIM Output Compare callback - (+) TIM Input capture callback - (+) TIM Trigger callback - (+) TIM Error callback - (+) TIM Index callback - (+) TIM Direction change callback - (+) TIM Index error callback - (+) TIM Transition error callback - -@endverbatim - * @{ - */ - -/** - * @brief Period elapsed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Period elapsed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Output Compare callback in non-blocking mode - * @param htim TIM OC handle - * @retval None - */ -__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureCallback could be implemented in the user file - */ -} - -/** - * @brief Input Capture half complete callback in non-blocking mode - * @param htim TIM IC handle - * @retval None - */ -__weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file - */ -} - -/** - * @brief PWM Pulse finished half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Trigger detection half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Timer error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIM_ErrorCallback could be implemented in the user file - */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User TIM callback to be used instead of the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID - * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID - * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID - * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID - * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID - * @param pCallback pointer to the callback function - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, - pTIM_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - return HAL_ERROR; - } - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - htim->PeriodElapsedCallback = pCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - htim->PeriodElapsedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - htim->TriggerCallback = pCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - htim->TriggerHalfCpltCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - htim->IC_CaptureCallback = pCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - htim->IC_CaptureHalfCpltCallback = pCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - htim->OC_DelayElapsedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - htim->PWM_PulseFinishedCallback = pCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - htim->PWM_PulseFinishedHalfCpltCallback = pCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - htim->ErrorCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - htim->CommutationCallback = pCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - htim->CommutationHalfCpltCallback = pCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - htim->BreakCallback = pCallback; - break; - - case HAL_TIM_BREAK2_CB_ID : - htim->Break2Callback = pCallback; - break; - - case HAL_TIM_ENCODER_INDEX_CB_ID : - htim->EncoderIndexCallback = pCallback; - break; - - case HAL_TIM_DIRECTION_CHANGE_CB_ID : - htim->DirectionChangeCallback = pCallback; - break; - - case HAL_TIM_INDEX_ERROR_CB_ID : - htim->IndexErrorCallback = pCallback; - break; - - case HAL_TIM_TRANSITION_ERROR_CB_ID : - htim->TransitionErrorCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - htim->Base_MspInitCallback = pCallback; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - htim->Base_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - htim->IC_MspInitCallback = pCallback; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - htim->IC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - htim->OC_MspInitCallback = pCallback; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - htim->OC_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - htim->PWM_MspInitCallback = pCallback; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - htim->PWM_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - htim->OnePulse_MspInitCallback = pCallback; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - htim->OnePulse_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - htim->Encoder_MspInitCallback = pCallback; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - htim->Encoder_MspDeInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - htim->HallSensor_MspInitCallback = pCallback; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - htim->HallSensor_MspDeInitCallback = pCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a TIM callback - * TIM callback is redirected to the weak predefined callback - * @param htim tim handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID - * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID - * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID - * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID - * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID - * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID - * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID - * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID - * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID - * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID - * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID - * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID - * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID - * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID - * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID - * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID - * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID - * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID - * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID - * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID - * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID - * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID - * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID - * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID - * @retval status - */ -HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (htim->State == HAL_TIM_STATE_READY) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - case HAL_TIM_PERIOD_ELAPSED_CB_ID : - /* Legacy weak Period Elapsed Callback */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - break; - - case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID : - /* Legacy weak Period Elapsed half complete Callback */ - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - break; - - case HAL_TIM_TRIGGER_CB_ID : - /* Legacy weak Trigger Callback */ - htim->TriggerCallback = HAL_TIM_TriggerCallback; - break; - - case HAL_TIM_TRIGGER_HALF_CB_ID : - /* Legacy weak Trigger half complete Callback */ - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - break; - - case HAL_TIM_IC_CAPTURE_CB_ID : - /* Legacy weak IC Capture Callback */ - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - break; - - case HAL_TIM_IC_CAPTURE_HALF_CB_ID : - /* Legacy weak IC Capture half complete Callback */ - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - break; - - case HAL_TIM_OC_DELAY_ELAPSED_CB_ID : - /* Legacy weak OC Delay Elapsed Callback */ - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_CB_ID : - /* Legacy weak PWM Pulse Finished Callback */ - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - break; - - case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID : - /* Legacy weak PWM Pulse Finished half complete Callback */ - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - break; - - case HAL_TIM_ERROR_CB_ID : - /* Legacy weak Error Callback */ - htim->ErrorCallback = HAL_TIM_ErrorCallback; - break; - - case HAL_TIM_COMMUTATION_CB_ID : - /* Legacy weak Commutation Callback */ - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - break; - - case HAL_TIM_COMMUTATION_HALF_CB_ID : - /* Legacy weak Commutation half complete Callback */ - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - break; - - case HAL_TIM_BREAK_CB_ID : - /* Legacy weak Break Callback */ - htim->BreakCallback = HAL_TIMEx_BreakCallback; - break; - - case HAL_TIM_BREAK2_CB_ID : - /* Legacy weak Break2 Callback */ - htim->Break2Callback = HAL_TIMEx_Break2Callback; - break; - - case HAL_TIM_ENCODER_INDEX_CB_ID : - /* Legacy weak Encoder Index Callback */ - htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; - break; - - case HAL_TIM_DIRECTION_CHANGE_CB_ID : - /* Legacy weak Direction Change Callback */ - htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; - break; - - case HAL_TIM_INDEX_ERROR_CB_ID : - /* Legacy weak Index Error Callback */ - htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; - break; - - case HAL_TIM_TRANSITION_ERROR_CB_ID : - /* Legacy weak Transition Error Callback */ - htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (htim->State == HAL_TIM_STATE_RESET) - { - switch (CallbackID) - { - case HAL_TIM_BASE_MSPINIT_CB_ID : - /* Legacy weak Base MspInit Callback */ - htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; - break; - - case HAL_TIM_BASE_MSPDEINIT_CB_ID : - /* Legacy weak Base Msp DeInit Callback */ - htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; - break; - - case HAL_TIM_IC_MSPINIT_CB_ID : - /* Legacy weak IC Msp Init Callback */ - htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; - break; - - case HAL_TIM_IC_MSPDEINIT_CB_ID : - /* Legacy weak IC Msp DeInit Callback */ - htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; - break; - - case HAL_TIM_OC_MSPINIT_CB_ID : - /* Legacy weak OC Msp Init Callback */ - htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; - break; - - case HAL_TIM_OC_MSPDEINIT_CB_ID : - /* Legacy weak OC Msp DeInit Callback */ - htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; - break; - - case HAL_TIM_PWM_MSPINIT_CB_ID : - /* Legacy weak PWM Msp Init Callback */ - htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; - break; - - case HAL_TIM_PWM_MSPDEINIT_CB_ID : - /* Legacy weak PWM Msp DeInit Callback */ - htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; - break; - - case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID : - /* Legacy weak One Pulse Msp Init Callback */ - htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; - break; - - case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID : - /* Legacy weak One Pulse Msp DeInit Callback */ - htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; - break; - - case HAL_TIM_ENCODER_MSPINIT_CB_ID : - /* Legacy weak Encoder Msp Init Callback */ - htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; - break; - - case HAL_TIM_ENCODER_MSPDEINIT_CB_ID : - /* Legacy weak Encoder Msp DeInit Callback */ - htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID : - /* Legacy weak Hall Sensor Msp Init Callback */ - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - break; - - case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID : - /* Legacy weak Hall Sensor Msp DeInit Callback */ - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - break; - - default : - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions - * @brief TIM Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Base handle state. - * @param htim TIM Base handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM OC handle state. - * @param htim TIM Output Compare handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM PWM handle state. - * @param htim TIM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Input Capture handle state. - * @param htim TIM IC handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM One Pulse Mode handle state. - * @param htim TIM OPM handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM Encoder Interface handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return the TIM Encoder Mode handle state. - * @param htim TIM handle - * @retval Active channel - */ -HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(const TIM_HandleTypeDef *htim) -{ - return htim->Channel; -} - -/** - * @brief Return actual state of the TIM channel. - * @param htim TIM handle - * @param Channel TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 - * @arg TIM_CHANNEL_6: TIM Channel 6 - * @retval TIM Channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(const TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - - channel_state = TIM_CHANNEL_STATE_GET(htim, Channel); - - return channel_state; -} - -/** - * @brief Return actual state of a DMA burst operation. - * @param htim TIM handle - * @retval DMA burst state - */ -HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(const TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); - - return htim->DMABurstState; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_Private_Functions TIM Private Functions - * @{ - */ - -/** - * @brief TIM DMA error callback - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMAError(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - htim->State = HAL_TIM_STATE_READY; - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Delay Pulse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedHalfCpltCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureCallback(htim); -#else - HAL_TIM_IC_CaptureCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Capture half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->IC_CaptureHalfCpltCallback(htim); -#else - HAL_TIM_IC_CaptureHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA Period Elapse complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedCallback(htim); -#else - HAL_TIM_PeriodElapsedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Period Elapse half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PeriodElapsedHalfCpltCallback(htim); -#else - HAL_TIM_PeriodElapsedHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerCallback(htim); -#else - HAL_TIM_TriggerCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Trigger half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->TriggerHalfCpltCallback(htim); -#else - HAL_TIM_TriggerHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief Time Base configuration - * @param TIMx TIM peripheral - * @param Structure TIM Base configuration structure - * @retval None - */ -void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure) -{ - uint32_t tmpcr1; - tmpcr1 = TIMx->CR1; - - /* Set TIM Time Base Unit parameters ---------------------------------------*/ - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS); - tmpcr1 |= Structure->CounterMode; - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - tmpcr1 &= ~TIM_CR1_CKD; - tmpcr1 |= (uint32_t)Structure->ClockDivision; - } - - /* Set the auto-reload preload */ - MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - - TIMx->CR1 = tmpcr1; - - /* Set the Autoreload value */ - TIMx->ARR = (uint32_t)Structure->Period ; - - /* Set the Prescaler value */ - TIMx->PSC = Structure->Prescaler; - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - TIMx->RCR = Structure->RepetitionCounter; - } - - /* Generate an update event to reload the Prescaler - and the repetition counter (only for advanced timer) value immediately */ - TIMx->EGR = TIM_EGR_UG; - - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } -} - -/** - * @brief Timer Output Compare 1 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= ~TIM_CCER_CC1E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~TIM_CCMR1_OC1M; - tmpccmrx &= ~TIM_CCMR1_CC1S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC1P; - /* Set the Output Compare Polarity */ - tmpccer |= OC_Config->OCPolarity; - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) - { - /* Check parameters */ - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC1NP; - /* Set the Output N Polarity */ - tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS1; - tmpcr2 &= ~TIM_CR2_OIS1N; - /* Set the Output Idle state */ - tmpcr2 |= OC_Config->OCIdleState; - /* Set the Output N Idle state */ - tmpcr2 |= OC_Config->OCNIdleState; - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR1 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 2 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC2E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR1; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR1_OC2M; - tmpccmrx &= ~TIM_CCMR1_CC2S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC2P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 4U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC2NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; - - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS2; - tmpcr2 &= ~TIM_CR2_OIS2N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 2U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 2U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR1 */ - TIMx->CCMR1 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR2 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 3 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 3: Reset the CC2E Bit */ - TIMx->CCER &= ~TIM_CCER_CC3E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC3M; - tmpccmrx &= ~TIM_CCMR2_CC3S; - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC3P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 8U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC3NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare and Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS3; - tmpcr2 &= ~TIM_CR2_OIS3N; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 4U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 4U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR3 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 4 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= ~TIM_CCER_CC4E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - - /* Get the TIMx CCMR2 register value */ - tmpccmrx = TIMx->CCMR2; - - /* Reset the Output Compare mode and Capture/Compare selection Bits */ - tmpccmrx &= ~TIM_CCMR2_OC4M; - tmpccmrx &= ~TIM_CCMR2_CC4S; - - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC4P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 12U); - - if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4)) - { - assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); - - /* Reset the Output N Polarity level */ - tmpccer &= ~TIM_CCER_CC4NP; - /* Set the Output N Polarity */ - tmpccer |= (OC_Config->OCNPolarity << 12U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC4NE; - } - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Check parameters */ - assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState)); - assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState)); - - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4; - /* Reset the Output Compare N IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS4N; - - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 6U); - /* Set the Output N Idle state */ - tmpcr2 |= (OC_Config->OCNIdleState << 6U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR2 */ - TIMx->CCMR2 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR4 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 5 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, - const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC5E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC5M); - /* Select the Output Compare Mode */ - tmpccmrx |= OC_Config->OCMode; - - /* Reset the Output Polarity level */ - tmpccer &= ~TIM_CCER_CC5P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 16U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS5; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 8U); - } - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR5 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Timer Output Compare 6 configuration - * @param TIMx to select the TIM peripheral - * @param OC_Config The output configuration structure - * @retval None - */ -static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, - const TIM_OC_InitTypeDef *OC_Config) -{ - uint32_t tmpccmrx; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Get the TIMx CCER register value */ - tmpccer = TIMx->CCER; - - /* Disable the output: Reset the CCxE Bit */ - TIMx->CCER &= ~TIM_CCER_CC6E; - - /* Get the TIMx CR2 register value */ - tmpcr2 = TIMx->CR2; - /* Get the TIMx CCMR1 register value */ - tmpccmrx = TIMx->CCMR3; - - /* Reset the Output Compare Mode Bits */ - tmpccmrx &= ~(TIM_CCMR3_OC6M); - /* Select the Output Compare Mode */ - tmpccmrx |= (OC_Config->OCMode << 8U); - - /* Reset the Output Polarity level */ - tmpccer &= (uint32_t)~TIM_CCER_CC6P; - /* Set the Output Compare Polarity */ - tmpccer |= (OC_Config->OCPolarity << 20U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - /* Reset the Output Compare IDLE State */ - tmpcr2 &= ~TIM_CR2_OIS6; - /* Set the Output Idle state */ - tmpcr2 |= (OC_Config->OCIdleState << 10U); - } - - /* Write to TIMx CR2 */ - TIMx->CR2 = tmpcr2; - - /* Write to TIMx CCMR3 */ - TIMx->CCMR3 = tmpccmrx; - - /* Set the Capture Compare Register value */ - TIMx->CCR6 = OC_Config->Pulse; - - /* Write to TIMx CCER */ - TIMx->CCER = tmpccer; -} - -/** - * @brief Slave Timer configuration function - * @param htim TIM handle - * @param sSlaveConfig Slave timer configuration - * @retval None - */ -static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, - const TIM_SlaveConfigTypeDef *sSlaveConfig) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* Reset the Trigger Selection Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source */ - tmpsmcr |= sSlaveConfig->InputTrigger; - - /* Reset the slave mode Bits */ - tmpsmcr &= ~TIM_SMCR_SMS; - /* Set the slave mode */ - tmpsmcr |= sSlaveConfig->SlaveMode; - - /* Write to TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - - /* Configure the trigger prescaler, filter, and polarity */ - switch (sSlaveConfig->InputTrigger) - { - case TIM_TS_ETRF: - { - /* Check the parameters */ - assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - /* Configure the ETR Trigger source */ - TIM_ETR_SetConfig(htim->Instance, - sSlaveConfig->TriggerPrescaler, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI1F_ED: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || \ - (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET)) - { - return HAL_ERROR; - } - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = htim->Instance->CCER; - htim->Instance->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = htim->Instance->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - htim->Instance->CCMR1 = tmpccmr1; - htim->Instance->CCER = tmpccer; - break; - } - - case TIM_TS_TI1FP1: - { - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI1 Filter and Polarity */ - TIM_TI1_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_TI2FP2: - { - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity)); - assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter)); - - /* Configure TI2 Filter and Polarity */ - TIM_TI2_ConfigInputStage(htim->Instance, - sSlaveConfig->TriggerPolarity, - sSlaveConfig->TriggerFilter); - break; - } - - case TIM_TS_ITR0: - case TIM_TS_ITR1: - case TIM_TS_ITR2: - case TIM_TS_ITR3: - case TIM_TS_ITR4: - case TIM_TS_ITR5: - case TIM_TS_ITR6: - case TIM_TS_ITR7: - case TIM_TS_ITR8: - case TIM_TS_ITR11: - { - /* Check the parameter */ - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger)); - break; - } - - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Configure the TI1 as Input. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 - * (on channel2 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Select the Input */ - if (IS_TIM_CC2_INSTANCE(TIMx) != RESET) - { - tmpccmr1 &= ~TIM_CCMR1_CC1S; - tmpccmr1 |= TIM_ICSelection; - } - else - { - tmpccmr1 |= TIM_CCMR1_CC1S_0; - } - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI1. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 1: Reset the CC1E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC1E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC1F; - tmpccmr1 |= (TIM_ICFilter << 4U); - - /* Select the Polarity and set the CC1E Bit */ - tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP); - tmpccer |= TIM_ICPolarity; - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI2 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1. - * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 - * (on channel1 path) is used as the input signal. Therefore CCMR1 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - - /* Select the Input */ - tmpccmr1 &= ~TIM_CCMR1_CC2S; - tmpccmr1 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP)); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the Polarity and Filter for TI2. - * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - */ -static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Disable the Channel 2: Reset the CC2E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC2E; - tmpccmr1 = TIMx->CCMR1; - - /* Set the filter */ - tmpccmr1 &= ~TIM_CCMR1_IC2F; - tmpccmr1 |= (TIM_ICFilter << 12U); - - /* Select the Polarity and set the CC2E Bit */ - tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (TIM_ICPolarity << 4U); - - /* Write to TIMx CCMR1 and CCER registers */ - TIMx->CCMR1 = tmpccmr1 ; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI3 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @retval None - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - */ -static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 3: Reset the CC3E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC3E; - tmpccmr2 = TIMx->CCMR2; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC3S; - tmpccmr2 |= TIM_ICSelection; - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC3F; - tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F); - - /* Select the Polarity and set the CC3E Bit */ - tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP); - tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer; -} - -/** - * @brief Configure the TI4 as Input. - * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity The Input Polarity. - * This parameter can be one of the following values: - * @arg TIM_ICPOLARITY_RISING - * @arg TIM_ICPOLARITY_FALLING - * @arg TIM_ICPOLARITY_BOTHEDGE - * @param TIM_ICSelection specifies the input to be used. - * This parameter can be one of the following values: - * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4. - * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3. - * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter Specifies the Input Capture Filter. - * This parameter must be a value between 0x00 and 0x0F. - * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 - * (on channel1 path) is used as the input signal. Therefore CCMR2 must be - * protected against un-initialized filter and polarity values. - * @retval None - */ -static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, - uint32_t TIM_ICFilter) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - - /* Disable the Channel 4: Reset the CC4E Bit */ - tmpccer = TIMx->CCER; - TIMx->CCER &= ~TIM_CCER_CC4E; - tmpccmr2 = TIMx->CCMR2; - - /* Select the Input */ - tmpccmr2 &= ~TIM_CCMR2_CC4S; - tmpccmr2 |= (TIM_ICSelection << 8U); - - /* Set the filter */ - tmpccmr2 &= ~TIM_CCMR2_IC4F; - tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F); - - /* Select the Polarity and set the CC4E Bit */ - tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP); - tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP)); - - /* Write to TIMx CCMR2 and CCER registers */ - TIMx->CCMR2 = tmpccmr2; - TIMx->CCER = tmpccer ; -} - -/** - * @brief Selects the Input Trigger source - * @param TIMx to select the TIM peripheral - * @param InputTriggerSource The Input Trigger source. - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal Trigger 0 - * @arg TIM_TS_ITR1: Internal Trigger 1 - * @arg TIM_TS_ITR2: Internal Trigger 2 - * @arg TIM_TS_ITR3: Internal Trigger 3 - * @arg TIM_TS_ITR4: Internal Trigger 4 - * @arg TIM_TS_ITR5: Internal Trigger 5 - * @arg TIM_TS_ITR6: Internal Trigger 6 - * @arg TIM_TS_ITR7: Internal Trigger 7 - * @arg TIM_TS_ITR8: Internal Trigger 8 - * @arg TIM_TS_ITR11: Internal Trigger 11 - * @arg TIM_TS_TI1F_ED: TI1 Edge Detector - * @arg TIM_TS_TI1FP1: Filtered Timer Input 1 - * @arg TIM_TS_TI2FP2: Filtered Timer Input 2 - * @arg TIM_TS_ETRF: External Trigger input - * @retval None - */ -static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource) -{ - uint32_t tmpsmcr; - - /* Get the TIMx SMCR register value */ - tmpsmcr = TIMx->SMCR; - /* Reset the TS Bits */ - tmpsmcr &= ~TIM_SMCR_TS; - /* Set the Input Trigger source and the slave mode*/ - tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1); - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} -/** - * @brief Configures the TIMx External Trigger (ETR). - * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. - * This parameter can be one of the following values: - * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF. - * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2. - * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4. - * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity The external Trigger Polarity. - * This parameter can be one of the following values: - * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active. - * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active. - * @param ExtTRGFilter External Trigger Filter. - * This parameter must be a value between 0x00 and 0x0F - * @retval None - */ -void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, - uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter) -{ - uint32_t tmpsmcr; - - tmpsmcr = TIMx->SMCR; - - /* Reset the ETR Bits */ - tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP); - - /* Set the Prescaler, the Filter value and the Polarity */ - tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U))); - - /* Write to TIMx SMCR */ - TIMx->SMCR = tmpsmcr; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel x. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @arg TIM_CHANNEL_5: TIM Channel 5 selected - * @arg TIM_CHANNEL_6: TIM Channel 6 selected - * @param ChannelState specifies the TIM Channel CCxE bit new state. - * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE. - * @retval None - */ -void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState) -{ - uint32_t tmp; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_TIM_CHANNELS(Channel)); - - tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */ - - /* Reset the CCxE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxE Bit */ - TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */ -} - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) -/** - * @brief Reset interrupt callbacks to the legacy weak callbacks. - * @param htim pointer to a TIM_HandleTypeDef structure that contains - * the configuration information for TIM module. - * @retval None - */ -void TIM_ResetCallback(TIM_HandleTypeDef *htim) -{ - /* Reset the TIM callback to the legacy weak callbacks */ - htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; - htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; - htim->TriggerCallback = HAL_TIM_TriggerCallback; - htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; - htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; - htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; - htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; - htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; - htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; - htim->ErrorCallback = HAL_TIM_ErrorCallback; - htim->CommutationCallback = HAL_TIMEx_CommutCallback; - htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; - htim->BreakCallback = HAL_TIMEx_BreakCallback; - htim->Break2Callback = HAL_TIMEx_Break2Callback; - htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; - htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; - htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; - htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; -} -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c deleted file mode 100644 index afe917be1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_tim_ex.c +++ /dev/null @@ -1,3573 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_tim_ex.c - * @author MCD Application Team - * @brief TIM HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Timer Extended peripheral: - * + Time Hall Sensor Interface Initialization - * + Time Hall Sensor Interface Start - * + Time Complementary signal break and dead time configuration - * + Time Master and Slave synchronization configuration - * + Time Output Compare/PWM Channel Configuration (for channels 5 and 6) - * + Time OCRef clear configuration - * + Timer remapping capabilities configuration - * + Timer encoder index configuration - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### TIMER Extended features ##### - ============================================================================== - [..] - The Timer Extended features include: - (#) Complementary outputs with programmable dead-time for : - (++) Output Compare - (++) PWM generation (Edge and Center-aligned Mode) - (++) One-pulse mode output - (#) Synchronization circuit to control the timer with external signals and to - interconnect several timers together. - (#) Break input to put the timer output signals in reset state or in a known state. - (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for - positioning purposes - (#) In case of Pulse on compare, configure pulse length and delay - (#) Encoder index configuration - - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Initialize the TIM low level resources by implementing the following functions - depending on the selected feature: - (++) Hall Sensor output : HAL_TIMEx_HallSensor_MspInit() - - (#) Initialize the TIM low level resources : - (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE(); - (##) TIM pins configuration - (+++) Enable the clock for the TIM GPIOs using the following function: - __HAL_RCC_GPIOx_CLK_ENABLE(); - (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init(); - - (#) The external Clock can be configured, if needed (the default clock is the - internal clock from the APBx), using the following function: - HAL_TIM_ConfigClockSource, the clock configuration should be done before - any start function. - - (#) Configure the TIM in the desired functioning mode using one of the - initialization function of this driver: - (++) HAL_TIMEx_HallSensor_Init() and HAL_TIMEx_ConfigCommutEvent(): to use the - Timer Hall Sensor Interface and the commutation event with the corresponding - Interrupt and DMA request if needed (Note that One Timer is used to interface - with the Hall sensor Interface and another Timer should be used to use - the commutation event). - (#) In case of Pulse On Compare: - (++) HAL_TIMEx_OC_ConfigPulseOnCompare(): to configure pulse width and prescaler - - - (#) Activate the TIM peripheral using one of the start functions: - (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), - HAL_TIMEx_OCN_Start_IT() - (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), - HAL_TIMEx_PWMN_Start_IT() - (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT() - (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), - HAL_TIMEx_HallSensor_Start_IT(). - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup TIMEx TIMEx - * @brief TIM Extended HAL module driver - * @{ - */ - -#ifdef HAL_TIM_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Constants TIM Extended Private Constants - * @{ - */ -/* Timeout for break input rearm */ -#define TIM_BREAKINPUT_REARM_TIMEOUT 5UL /* 5 milliseconds */ -/** - * @} - */ -/* End of private constants --------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma); -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma); -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState); - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIMEx_Exported_Functions TIM Extended Exported Functions - * @{ - */ - -/** @defgroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions - * @brief Timer Hall Sensor functions - * -@verbatim - ============================================================================== - ##### Timer Hall Sensor functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Initialize and configure TIM HAL Sensor. - (+) De-initialize TIM HAL Sensor. - (+) Start the Hall Sensor Interface. - (+) Stop the Hall Sensor Interface. - (+) Start the Hall Sensor Interface and enable interrupts. - (+) Stop the Hall Sensor Interface and disable interrupts. - (+) Start the Hall Sensor Interface and enable DMA transfers. - (+) Stop the Hall Sensor Interface and disable DMA transfers. - -@endverbatim - * @{ - */ -/** - * @brief Initializes the TIM Hall Sensor Interface and initialize the associated handle. - * @note When the timer instance is initialized in Hall Sensor Interface mode, - * timer channels 1 and channel 2 are reserved and cannot be used for - * other purpose. - * @param htim TIM Hall Sensor Interface handle - * @param sConfig TIM Hall Sensor configuration structure - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, const TIM_HallSensor_InitTypeDef *sConfig) -{ - TIM_OC_InitTypeDef OC_Config; - - /* Check the TIM handle allocation */ - if (htim == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode)); - assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision)); - assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload)); - assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); - assert_param(IS_TIM_PERIOD(htim, htim->Init.Period)); - assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); - assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); - - if (htim->State == HAL_TIM_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - htim->Lock = HAL_UNLOCKED; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - /* Reset interrupt callbacks to legacy week callbacks */ - TIM_ResetCallback(htim); - - if (htim->HallSensor_MspInitCallback == NULL) - { - htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; - } - /* Init the low level hardware : GPIO, CLOCK, NVIC */ - htim->HallSensor_MspInitCallback(htim); -#else - /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */ - HAL_TIMEx_HallSensor_MspInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - } - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Configure the Time base in the Encoder Mode */ - TIM_Base_SetConfig(htim->Instance, &htim->Init); - - /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */ - TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter); - - /* Reset the IC1PSC Bits */ - htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC; - /* Set the IC1PSC value */ - htim->Instance->CCMR1 |= sConfig->IC1Prescaler; - - /* Enable the Hall sensor interface (XOR function of the three inputs) */ - htim->Instance->CR2 |= TIM_CR2_TI1S; - - /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= TIM_TS_TI1F_ED; - - /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */ - htim->Instance->SMCR &= ~TIM_SMCR_SMS; - htim->Instance->SMCR |= TIM_SLAVEMODE_RESET; - - /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/ - OC_Config.OCFastMode = TIM_OCFAST_DISABLE; - OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET; - OC_Config.OCMode = TIM_OCMODE_PWM2; - OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET; - OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH; - OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH; - OC_Config.Pulse = sConfig->Commutation_Delay; - - TIM_OC2_SetConfig(htim->Instance, &OC_Config); - - /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2 - register to 101 */ - htim->Instance->CR2 &= ~TIM_CR2_MMS; - htim->Instance->CR2 |= TIM_TRGO_OC2REF; - - /* Initialize the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_READY; - - /* Initialize the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Initialize the TIM state*/ - htim->State = HAL_TIM_STATE_READY; - - return HAL_OK; -} - -/** - * @brief DeInitializes the TIM Hall Sensor interface - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Disable the TIM Peripheral Clock */ - __HAL_TIM_DISABLE(htim); - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - if (htim->HallSensor_MspDeInitCallback == NULL) - { - htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; - } - /* DeInit the low level hardware */ - htim->HallSensor_MspDeInitCallback(htim); -#else - /* DeInit the low level hardware: GPIO, CLOCK, NVIC */ - HAL_TIMEx_HallSensor_MspDeInit(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - /* Change the DMA burst operation state */ - htim->DMABurstState = HAL_DMA_BURST_STATE_RESET; - - /* Change the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET); - - /* Change TIM state */ - htim->State = HAL_TIM_STATE_RESET; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Initializes the TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file - */ -} - -/** - * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim TIM Hall Sensor Interface handle - * @retval None - */ -__weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file - */ -} - -/** - * @brief Starts the TIM Hall Sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall sensor Interface. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channels 1, 2 and 3 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the capture compare Interrupts 1 event */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - /* Disable the capture compare Interrupts event */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @param pData The destination Buffer address. - * @param Length The length of data to be transferred from TIM peripheral to memory. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) -{ - uint32_t tmpsmcr; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Set the TIM channel state */ - if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY) - || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)) - { - return HAL_BUSY; - } - else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY) - && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - /* Enable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE); - - /* Set the DMA Input Capture 1 Callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; - - /* Enable the DMA channel for Capture 1*/ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the capture compare 1 Interrupt */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim TIM Hall Sensor Interface handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(htim->Instance)); - - /* Disable the Input Capture channel 1 - (in the Hall Sensor Interface the three possible channels that can be used are TIM_CHANNEL_1, - TIM_CHANNEL_2 and TIM_CHANNEL_3) */ - TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE); - - - /* Disable the capture compare Interrupts 1 event */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channel state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions - * @brief Timer Complementary Output Compare functions - * -@verbatim - ============================================================================== - ##### Timer Complementary Output Compare functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary Output Compare/PWM. - (+) Stop the Complementary Output Compare/PWM. - (+) Start the Complementary Output Compare/PWM and enable interrupts. - (+) Stop the Complementary Output Compare/PWM and disable interrupts. - (+) Start the Complementary Output Compare/PWM and enable DMA transfers. - (+) Stop the Complementary Output Compare/PWM and disable DMA transfers. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM Output Compare signal generation on the complementary - * output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM OC handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - - case TIM_CHANNEL_4: - { - /* Enable the TIM Output Compare interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in interrupt mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Output Compare DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM Output Compare signal generation in DMA mode - * on the complementary output. - * @param htim TIM Output Compare handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Output Compare DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Output Compare interrupt */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the Capture compare channel N */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions - * @brief Timer Complementary PWM functions - * -@verbatim - ============================================================================== - ##### Timer Complementary PWM functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary PWM. - (+) Stop the Complementary PWM. - (+) Start the Complementary PWM and enable interrupts. - (+) Stop the Complementary PWM and disable interrupts. - (+) Start the Complementary PWM and enable DMA transfers. - (+) Stop the Complementary PWM and disable DMA transfers. - (+) Start the Complementary Input Capture measurement. - (+) Stop the Complementary Input Capture. - (+) Start the Complementary Input Capture and enable interrupts. - (+) Stop the Complementary Input Capture and disable interrupts. - (+) Start the Complementary Input Capture and enable DMA transfers. - (+) Stop the Complementary Input Capture and disable DMA transfers. - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the PWM signal generation on the complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Check the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY) - { - return HAL_ERROR; - } - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Enable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Enable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the TIM Break interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK); - - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the PWM signal generation in interrupt mode on the - * complementary output. - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the TIM Break interrupt (only if no more channel is active) */ - tmpccer = htim->Instance->CCER; - if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE | TIM_CCER_CC4NE)) == (uint32_t)RESET) - { - __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK); - } - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @brief Starts the TIM PWM signal generation in DMA mode on the - * complementary output - * @param htim TIM handle - * @param Channel TIM Channel to be enabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData The source Buffer address. - * @param Length The length of data to be transferred from memory to TIM peripheral - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, const uint32_t *pData, - uint16_t Length) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - /* Set the TIM complementary channel state */ - if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY) - { - return HAL_BUSY; - } - else if (TIM_CHANNEL_N_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY) - { - if ((pData == NULL) || (Length == 0U)) - { - return HAL_ERROR; - } - else - { - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY); - } - } - else - { - return HAL_ERROR; - } - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1); - break; - } - - case TIM_CHANNEL_2: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2); - break; - } - - case TIM_CHANNEL_3: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3); - break; - } - - case TIM_CHANNEL_4: - { - /* Set the DMA compare callbacks */ - htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseNCplt; - htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt; - - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAErrorCCxN ; - - /* Enable the DMA channel */ - if (TIM_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, - Length) != HAL_OK) - { - /* Return error status */ - return HAL_ERROR; - } - /* Enable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Enable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */ - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS; - if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr)) - { - __HAL_TIM_ENABLE(htim); - } - } - else - { - __HAL_TIM_ENABLE(htim); - } - } - - /* Return function status */ - return status; -} - -/** - * @brief Stops the TIM PWM signal generation in DMA mode on the complementary - * output - * @param htim TIM handle - * @param Channel TIM Channel to be disabled - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); - - switch (Channel) - { - case TIM_CHANNEL_1: - { - /* Disable the TIM Capture/Compare 1 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]); - break; - } - - case TIM_CHANNEL_2: - { - /* Disable the TIM Capture/Compare 2 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]); - break; - } - - case TIM_CHANNEL_3: - { - /* Disable the TIM Capture/Compare 3 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]); - break; - } - - case TIM_CHANNEL_4: - { - /* Disable the TIM Capture/Compare 4 DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4); - (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]); - break; - } - - default: - status = HAL_ERROR; - break; - } - - if (status == HAL_OK) - { - /* Disable the complementary PWM output */ - TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM complementary channel state */ - TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY); - } - - /* Return function status */ - return status; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions - * @brief Timer Complementary One Pulse functions - * -@verbatim - ============================================================================== - ##### Timer Complementary One Pulse functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Start the Complementary One Pulse generation. - (+) Stop the Complementary One Pulse. - (+) Start the Complementary One Pulse and enable interrupts. - (+) Stop the Complementary One Pulse and disable interrupts. - -@endverbatim - * @{ - */ - -/** - * @brief Starts the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation on the complementary - * output. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Starts the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to enable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2); - HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1); - HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2); - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Check the TIM channels state */ - if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY) - || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY)) - { - return HAL_ERROR; - } - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY); - - /* Enable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1); - - /* Enable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2); - - /* Enable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_ENABLE); - - /* Enable the Main Output */ - __HAL_TIM_MOE_ENABLE(htim); - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Stops the TIM One Pulse signal generation in interrupt mode on the - * complementary channel. - * @note OutputChannel must match the pulse output channel chosen when calling - * @ref HAL_TIM_OnePulse_ConfigChannel(). - * @param htim TIM One Pulse handle - * @param OutputChannel pulse output channel to disable - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 selected - * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel) -{ - uint32_t input_channel = (OutputChannel == TIM_CHANNEL_1) ? TIM_CHANNEL_2 : TIM_CHANNEL_1; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel)); - - /* Disable the TIM Capture/Compare 1 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1); - - /* Disable the TIM Capture/Compare 2 interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2); - - /* Disable the complementary One Pulse output channel and the Input Capture channel */ - TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE); - TIM_CCxChannelCmd(htim->Instance, input_channel, TIM_CCx_DISABLE); - - /* Disable the Main Output */ - __HAL_TIM_MOE_DISABLE(htim); - - /* Disable the Peripheral */ - __HAL_TIM_DISABLE(htim); - - /* Set the TIM channels state */ - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - - /* Return function status */ - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - ============================================================================== - ##### Peripheral Control functions ##### - ============================================================================== - [..] - This section provides functions allowing to: - (+) Configure the commutation event in case of use of the Hall sensor interface. - (+) Configure Output channels for OC and PWM mode. - - (+) Configure Complementary channels, break features and dead time. - (+) Configure Master synchronization. - (+) Configure timer remapping capabilities. - (+) Select timer input source. - (+) Enable or disable channel grouping. - (+) Configure Pulse on compare. - (+) Configure Encoder index. - -@endverbatim - * @{ - */ - -/** - * @brief Configure the TIM commutation event sequence. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_ITR4: Internal trigger 4 selected - * @arg TIM_TS_ITR5: Internal trigger 5 selected - * @arg TIM_TS_ITR6: Internal trigger 6 selected - * @arg TIM_TS_ITR7: Internal trigger 7 selected - * @arg TIM_TS_ITR8: Internal trigger 8 selected - * @arg TIM_TS_ITR11: Internal trigger 11 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || - (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || - (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with interrupt. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_ITR4: Internal trigger 4 selected - * @arg TIM_TS_ITR5: Internal trigger 5 selected - * @arg TIM_TS_ITR6: Internal trigger 6 selected - * @arg TIM_TS_ITR7: Internal trigger 7 selected - * @arg TIM_TS_ITR8: Internal trigger 8 selected - * @arg TIM_TS_ITR11: Internal trigger 11 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || - (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || - (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Disable Commutation DMA request */ - __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_COM); - - /* Enable the Commutation Interrupt */ - __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure the TIM commutation event sequence with DMA. - * @note This function is mandatory to use the commutation event in order to - * update the configuration at each commutation detection on the TRGI input of the Timer, - * the typical use of this feature is with the use of another Timer(interface Timer) - * configured in Hall sensor interface, this interface Timer will generate the - * commutation at its TRGO output (connected to Timer used in this function) each time - * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @note The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim TIM handle - * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor - * This parameter can be one of the following values: - * @arg TIM_TS_ITR0: Internal trigger 0 selected - * @arg TIM_TS_ITR1: Internal trigger 1 selected - * @arg TIM_TS_ITR2: Internal trigger 2 selected - * @arg TIM_TS_ITR3: Internal trigger 3 selected - * @arg TIM_TS_ITR4: Internal trigger 4 selected - * @arg TIM_TS_ITR5: Internal trigger 5 selected - * @arg TIM_TS_ITR6: Internal trigger 6 selected - * @arg TIM_TS_ITR7: Internal trigger 7 selected - * @arg TIM_TS_ITR8: Internal trigger 8 selected - * @arg TIM_TS_ITR11: Internal trigger 11 selected - * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource the Commutation Event source - * This parameter can be one of the following values: - * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer - * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, - uint32_t CommutationSource) -{ - /* Check the parameters */ - assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); - assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE(htim->Instance, InputTrigger)); - - __HAL_LOCK(htim); - - if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) || - (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3) || - (InputTrigger == TIM_TS_ITR4) || (InputTrigger == TIM_TS_ITR5) || - (InputTrigger == TIM_TS_ITR6) || (InputTrigger == TIM_TS_ITR7) || - (InputTrigger == TIM_TS_ITR8) || (InputTrigger == TIM_TS_ITR11)) - { - /* Select the Input trigger */ - htim->Instance->SMCR &= ~TIM_SMCR_TS; - htim->Instance->SMCR |= InputTrigger; - } - - /* Select the Capture Compare preload feature */ - htim->Instance->CR2 |= TIM_CR2_CCPC; - /* Select the Commutation event source */ - htim->Instance->CR2 &= ~TIM_CR2_CCUS; - htim->Instance->CR2 |= CommutationSource; - - /* Enable the Commutation DMA Request */ - /* Set the DMA Commutation Callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt; - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt; - /* Set the DMA error callback */ - htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError; - - /* Disable Commutation Interrupt */ - __HAL_TIM_DISABLE_IT(htim, TIM_IT_COM); - - /* Enable the Commutation DMA Request */ - __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the TIM in master mode. - * @param htim TIM handle. - * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that - * contains the selected trigger output (TRGO) and the Master/Slave - * mode. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, - const TIM_MasterConfigTypeDef *sMasterConfig) -{ - uint32_t tmpcr2; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); - assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Change the handler state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx CR2 register value */ - tmpcr2 = htim->Instance->CR2; - - /* Get the TIMx SMCR register value */ - tmpsmcr = htim->Instance->SMCR; - - /* If the timer supports ADC synchronization through TRGO2, set the master mode selection 2 */ - if (IS_TIM_TRGO2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_TRGO2_SOURCE(sMasterConfig->MasterOutputTrigger2)); - - /* Clear the MMS2 bits */ - tmpcr2 &= ~TIM_CR2_MMS2; - /* Select the TRGO2 source*/ - tmpcr2 |= sMasterConfig->MasterOutputTrigger2; - } - - /* Reset the MMS Bits */ - tmpcr2 &= ~TIM_CR2_MMS; - /* Select the TRGO source */ - tmpcr2 |= sMasterConfig->MasterOutputTrigger; - - /* Update TIMx CR2 */ - htim->Instance->CR2 = tmpcr2; - - if (IS_TIM_SLAVE_INSTANCE(htim->Instance)) - { - /* Reset the MSM Bit */ - tmpsmcr &= ~TIM_SMCR_MSM; - /* Set master mode */ - tmpsmcr |= sMasterConfig->MasterSlaveMode; - - /* Update TIMx SMCR */ - htim->Instance->SMCR = tmpsmcr; - } - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State - * and the AOE(automatic output enable). - * @param htim TIM handle - * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that - * contains the BDTR Register configuration information for the TIM peripheral. - * @note Interrupts can be generated when an active level is detected on the - * break input, the break 2 input or the system break input. Break - * interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, - const TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig) -{ - /* Keep this variable initialized to 0 as it is used to configure BDTR register */ - uint32_t tmpbdtr = 0U; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode)); - assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode)); - assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel)); - assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime)); - assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState)); - assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter)); - assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput)); - - /* Check input state */ - __HAL_LOCK(htim); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, sBreakDeadTimeConfig->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, sBreakDeadTimeConfig->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, sBreakDeadTimeConfig->OffStateIDLEMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, sBreakDeadTimeConfig->OffStateRunMode); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, sBreakDeadTimeConfig->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos)); - - if (IS_TIM_BREAK_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode)); - - /* Set BREAK AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode); - } - - if (IS_TIM_BKIN2_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State)); - assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity)); - assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter)); - - /* Set the BREAK2 input related BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos)); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State); - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity); - - if (IS_TIM_ADVANCED_INSTANCE(htim->Instance)) - { - /* Check the parameters */ - assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode)); - - /* Set BREAK2 AF mode */ - MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode); - } - } - - /* Set TIMx_BDTR */ - htim->Instance->BDTR = tmpbdtr; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configures the break input source. - * @param htim TIM handle. - * @param BreakInput Break input to configure - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @param sBreakInputConfig Break input source configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, - uint32_t BreakInput, - const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig) - -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmporx; - uint32_t bkin_enable_mask; - uint32_t bkin_polarity_mask; - uint32_t bkin_enable_bitpos; - uint32_t bkin_polarity_bitpos; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source)); - assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable)); - if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_MDF1) - { - assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity)); - } - - /* Check input state */ - __HAL_LOCK(htim); - - switch (sBreakInputConfig->Source) - { - case TIM_BREAKINPUTSOURCE_BKIN: - { - bkin_enable_mask = TIM1_AF1_BKINE; - bkin_enable_bitpos = TIM1_AF1_BKINE_Pos; - bkin_polarity_mask = TIM1_AF1_BKINP; - bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; - break; - } - case TIM_BREAKINPUTSOURCE_COMP1: - { - bkin_enable_mask = TIM1_AF1_BKCMP1E; - bkin_enable_bitpos = TIM1_AF1_BKCMP1E_Pos; - bkin_polarity_mask = TIM1_AF1_BKCMP1P; - bkin_polarity_bitpos = TIM1_AF1_BKCMP1P_Pos; - break; - } -#if defined(COMP2) - case TIM_BREAKINPUTSOURCE_COMP2: - { - bkin_enable_mask = TIM1_AF1_BKCMP2E; - bkin_enable_bitpos = TIM1_AF1_BKCMP2E_Pos; - bkin_polarity_mask = TIM1_AF1_BKCMP2P; - bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; - break; - } -#endif /* COMP2 */ - case TIM_BREAKINPUTSOURCE_MDF1: - { - bkin_enable_mask = TIM1_AF1_BKDF1BK0E; - bkin_enable_bitpos = TIM1_AF1_BKDF1BK0E_Pos; - /* No polarity bit for MDF. Variable bkin_polarity_mask keeps its default value 0 */ - bkin_polarity_mask = 0U; - bkin_polarity_bitpos = 0U; - break; - } - - default: - { - bkin_enable_mask = 0U; - bkin_polarity_mask = 0U; - bkin_enable_bitpos = 0U; - bkin_polarity_bitpos = 0U; - break; - } - } - - switch (BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Get the TIMx_AF1 register value */ - tmporx = htim->Instance->AF1; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - - /* Set TIMx_AF1 */ - htim->Instance->AF1 = tmporx; - break; - } - case TIM_BREAKINPUT_BRK2: - { - /* Get the TIMx_AF2 register value */ - tmporx = htim->Instance->AF2; - - /* Enable the break input */ - tmporx &= ~bkin_enable_mask; - tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask; - - /* Set the break input polarity */ - tmporx &= ~bkin_polarity_mask; - tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask; - - /* Set TIMx_AF2 */ - htim->Instance->AF2 = tmporx; - break; - } - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Configures the TIMx Remapping input capabilities. - * @param htim TIM handle. - * @param Remap specifies the TIM remapping source. - * For TIM1, the parameter can take one of the following values: - * @arg TIM_TIM1_ETR_GPIO TIM1 ETR is connected to GPIO - * @arg TIM_TIM1_ETR_COMP1 TIM1 ETR is connected to COMP1 output - * @arg TIM_TIM1_ETR_COMP2 TIM1 ETR is connected to COMP2 output (*) - * @arg TIM_TIM1_ETR_HSI TIM1 ETR is connected to HSI - * @arg TIM_TIM1_ETR_MSIS TIM1_ETR is connected to MSIS - * @arg TIM_TIM1_ETR_ADC2_AWD2 TIM1_ETR is connected to ADC2 AWD2 (*) - * @arg TIM_TIM1_ETR_ADC2_AWD3 TIM1_ETR is connected to ADC2 AWD3 (*) - * @arg TIM_TIM1_ETR_ADC1_AWD1 TIM1 ETR is connected to ADC1 AWD1 - * @arg TIM_TIM1_ETR_ADC1_AWD2 TIM1 ETR is connected to ADC1 AWD2 - * @arg TIM_TIM1_ETR_ADC1_AWD3 TIM1 ETR is connected to ADC1 AWD3 - * @arg TIM_TIM1_ETR_ADC4_AWD1 TIM1 ETR is connected to ADC4 AWD1 - * @arg TIM_TIM1_ETR_ADC4_AWD2 TIM1 ETR is connected to ADC4 AWD2 - * @arg TIM_TIM1_ETR_ADC4_AWD3 TIM1 ETR is connected to ADC4 AWD3 - * @arg TIM_TIM1_ETR_ADC2_AWD1 TIM1_ETR is connected to ADC2 AWD1 (*) - * - * For TIM2, the parameter can take one of the following values: - * @arg TIM_TIM2_ETR_GPIO TIM2 ETR is connected to GPIO - * @arg TIM_TIM2_ETR_COMP1 TIM2 ETR is connected to COMP1 output - * @arg TIM_TIM2_ETR_COMP2 TIM2 ETR is connected to COMP2 output (*) - * @arg TIM_TIM2_ETR_MSIK TIM2 ETR is connected to MSIK - * @arg TIM_TIM2_ETR_HSI TIM2 ETR is connected to HSI - * @arg TIM_TIM2_ETR_MSIS TIM2_ETR is connected to MSIS - * @arg TIM_TIM2_ETR_DCMI_VSYNC TIM2_ETR is connected to DCMI VSYNC (*) - * @arg TIM_TIM2_ETR_LTDC_VSYNC TIM2_ETR is connected to LTDC_VSYNC (*) - * @arg TIM_TIM2_ETR_TIM3_ETR TIM2 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM2_ETR_TIM4_ETR TIM2 ETR is connected to TIM4 ETR pin - * @arg TIM_TIM2_ETR_TIM5_ETR TIM2 ETR is connected to TIM5 ETR pin - * @arg TIM_TIM2_ETR_LSE TIM2 ETR is connected to LSE - * @arg TIM_TIM2_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) - * @arg TIM_TIM2_ETR_DCMI_HSYNC TIM2_ETR is connected to DCMI HSYNC (*) - * @arg TIM_TIM2_ETR_LTDC_HSYNC TIM2_ETR is connected to LTDC HSYNC (*) - * - * For TIM3, the parameter can take one of the following values: - * @arg TIM_TIM3_ETR_GPIO TIM3 ETR is connected to GPIO - * @arg TIM_TIM3_ETR_COMP1 TIM3 ETR is connected to COMP1 output - * @arg TIM_TIM3_ETR_COMP2 TIM3 ETR is connected to COMP2 output (*) - * @arg TIM_TIM3_ETR_MSIK TIM3 ETR is connected to MSIK - * @arg TIM_TIM3_ETR_HSI TIM3 ETR is connected to HSI - * @arg TIM_TIM3_ETR_MSIS TIM3_ETR is connected to MSIS - * @arg TIM_TIM3_ETR_DCMI_VSYNC TIM3_ETR is connected to DCMI VSYNC (*) - * @arg TIM_TIM3_ETR_LTDC_VSYNC TIM3_ETR is connected to LTDC_VSYNC (*) - * @arg TIM_TIM3_ETR_TIM2_ETR TIM3 ETR is connected to TIM2 ETR pin - * @arg TIM_TIM3_ETR_TIM4_ETR TIM3 ETR is connected to TIM4 ETR pin - * @arg TIM_TIM3_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) - * @arg TIM_TIM3_ETR_ADC1_AWD1 TIM3 ETR is connected to ADC1 AWD1 - * @arg TIM_TIM3_ETR_ADC1_AWD2 TIM3 ETR is connected to ADC1 AWD2 - * @arg TIM_TIM3_ETR_ADC1_AWD3 TIM3 ETR is connected to ADC1 AWD3 - * @arg TIM_TIM3_ETR_DCMI_HSYNC TIM3_ETR is connected to DCMI HSYNC (*) - * @arg TIM_TIM3_ETR_LTDC_HSYNC TIM3_ETR is connected to LTDC HSYNC (*) - * - * For TIM4, the parameter can take one of the following values: - * @arg TIM_TIM4_ETR_GPIO TIM4 ETR is connected to GPIO - * @arg TIM_TIM4_ETR_COMP1 TIM4 ETR is connected to COMP1 output - * @arg TIM_TIM4_ETR_COMP2 TIM4 ETR is connected to COMP2 output (*) - * @arg TIM_TIM4_ETR_MSIK TIM4 ETR is connected to MSIK - * @arg TIM_TIM4_ETR_HSI TIM4 ETR is connected to HSI - * @arg TIM_TIM4_ETR_MSIS TIM4_ETR is connected to MSIS - * @arg TIM_TIM4_ETR_DCMI_VSYNC TIM4_ETR is connected to DCMI VSYNC (*) - * @arg TIM_TIM4_ETR_LTDC_VSYNC TIM4_ETR is connected to LTDC_VSYNC (*) - * @arg TIM_TIM4_ETR_TIM3_ETR TIM4 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM4_ETR_TIM5_ETR TIM4 ETR is connected to TIM5 ETR pin - * @arg TIM_TIM4_ETR_DSI_TE TIM2_ETR is connected to DSI_TE (*) - * @arg TIM_TIM4_ETR_ADC2_AWD1 TIM4_ETR is connected to ADC2 AWD1 (*) - * @arg TIM_TIM4_ETR_ADC2_AWD2 TIM4_ETR is connected to ADC2 AWD2 (*) - * @arg TIM_TIM4_ETR_ADC2_AWD3 TIM4_ETR is connected to ADC2 AWD3 (*) - * @arg TIM_TIM4_ETR_DCMI_HSYNC TIM4_ETR is connected to DCMI HSYNC (*) - * @arg TIM_TIM4_ETR_LTDC_HSYNC TIM4_ETR is connected to LTDC HSYNC (*) - * - * For TIM5, the parameter can take one of the following values: - * @arg TIM_TIM5_ETR_GPIO TIM5 ETR is connected to GPIO - * @arg TIM_TIM5_ETR_COMP1 TIM5 ETR is connected to COMP1 output - * @arg TIM_TIM5_ETR_COMP2 TIM5 ETR is connected to COMP2 output (*) - * @arg TIM_TIM5_ETR_MSIK TIM5 ETR is connected to MSIK - * @arg TIM_TIM5_ETR_HSI TIM5 ETR is connected to HSI - * @arg TIM_TIM5_ETR_MSIS TIM5_ETR is connected to MSIS - * @arg TIM_TIM5_ETR_DCMI_VSYNC TIM5_ETR is connected to DCMI VSYNC (*) - * @arg TIM_TIM5_ETR_LTDC_VSYNC TIM5_ETR is connected to LTDC_VSYNC (*) - * @arg TIM_TIM5_ETR_TIM2_ETR TIM5 ETR is connected to TIM2 ETR pin - * @arg TIM_TIM5_ETR_TIM3_ETR TIM5 ETR is connected to TIM3 ETR pin - * @arg TIM_TIM5_ETR_DSI_TE TIM5_ETR is connected to DSI_TE (*) - * @arg TIM_TIM5_ETR_DCMI_HSYNC TIM5_ETR is connected to DCMI HSYNC (*) - * @arg TIM_TIM5_ETR_LTDC_HSYNC TIM5_ETR is connected to LTDC HSYNC (*) - * - * For TIM8, the parameter can take one of the following values: - * @arg TIM_TIM8_ETR_GPIO TIM8 ETR is connected to GPIO - * @arg TIM_TIM8_ETR_COMP1 TIM8 ETR is connected to COMP1 output - * @arg TIM_TIM8_ETR_COMP2 TIM8 ETR is connected to COMP2 output (*) - * @arg TIM_TIM8_ETR_MSIK TIM8 ETR is connected to MSIK - * @arg TIM_TIM8_ETR_HSI TIM8 ETR is connected to HSI - * @arg TIM_TIM8_ETR_MSIS TIM8_ETR is connected to MSIS - * @arg TIM_TIM8_ETR_ADC2_AWD2 TIM8_ETR is connected to ADC2 AWD2 (*) - * @arg TIM_TIM8_ETR_ADC2_AWD3 TIM8_ETR is connected to ADC2 AWD3 (*) - * @arg TIM_TIM8_ETR_ADC1_AWD1 TIM8 ETR is connected to ADC1 AWD1 - * @arg TIM_TIM8_ETR_ADC1_AWD2 TIM8 ETR is connected to ADC1 AWD2 - * @arg TIM_TIM8_ETR_ADC1_AWD3 TIM8 ETR is connected to ADC1 AWD3 - * @arg TIM_TIM8_ETR_ADC4_AWD1 TIM8 ETR is connected to ADC4 AWD1 - * @arg TIM_TIM8_ETR_ADC4_AWD2 TIM8 ETR is connected to ADC4 AWD2 - * @arg TIM_TIM8_ETR_ADC4_AWD3 TIM8 ETR is connected to ADC4 AWD3 - * @arg TIM_TIM8_ETR_ADC2_AWD1 TIM8_ETR is connected to ADC2 AWD1 (*) - * - * (*) Value not defined in all devices. - * - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) -{ - /* Check parameters */ - assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance)); - assert_param(IS_TIM_REMAP(Remap)); - - __HAL_LOCK(htim); - - MODIFY_REG(htim->Instance->AF1, TIM1_AF1_ETRSEL_Msk, Remap); - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Select the timer input source - * @param htim TIM handle. - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TI1 input channel - * @arg TIM_CHANNEL_2: TI2 input channel - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param TISelection parameter of the TIM_TISelectionStruct structure is detailed as follows: - * For TIM1, the parameter is one of the following values: - * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to GPIO - * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output - * @arg TIM_TIM1_TI1_COMP2: TIM1 TI1 is connected to COMP2 output (*) - * - * For TIM2, the parameter is one of the following values: - * @arg TIM_TIM2_TI1_GPIO: TIM2 TI1 is connected to GPIO - * @arg TIM_TIM2_TI1_COMP1: TIM2 TI1 is connected to COMP1 output - * @arg TIM_TIM2_TI1_COMP2: TIM2 TI1 is connected to COMP2 output (*) - * @arg TIM_TIM2_TI2_GPIO: TIM2 TI2 is connected to GPIO - * @arg TIM_TIM2_TI2_COMP1: TIM2 TI2 is connected to COMP1 output - * @arg TIM_TIM2_TI2_COMP2: TIM2 TI2 is connected to COMP2 output (*) - * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to GPIO - * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output - * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*) - * - * For TIM3, the parameter is one of the following values: - * @arg TIM_TIM3_TI1_GPIO: TIM3 TI1 is connected to GPIO - * @arg TIM_TIM3_TI1_COMP1: TIM3 TI1 is connected to COMP1 output - * @arg TIM_TIM3_TI1_COMP2: TIM3 TI1 is connected to COMP2 output (*) - * @arg TIM_TIM3_TI2_GPIO: TIM3 TI2 is connected to GPIO - * @arg TIM_TIM3_TI2_COMP1: TIM3 TI2 is connected to COMP1 output - * @arg TIM_TIM3_TI2_COMP2: TIM3 TI2 is connected to COMP2 output (*) - * - * For TIM4, the parameter is one of the following values: - * @arg TIM_TIM4_TI1_GPIO: TIM4 TI1 is connected to GPIO - * @arg TIM_TIM4_TI1_COMP1: TIM4 TI1 is connected to COMP1 output - * @arg TIM_TIM4_TI1_COMP2: TIM4 TI1 is connected to COMP2 output (*) - * @arg TIM_TIM4_TI2_GPIO: TIM4 TI2 is connected to GPIO - * @arg TIM_TIM4_TI2_COMP1: TIM4 TI2 is connected to COMP1 output - * @arg TIM_TIM4_TI2_COMP2: TIM4 TI2 is connected to COMP2 output (*) - * - * For TIM5, the parameter is one of the following values: - * @arg TIM_TIM5_TI1_GPIO: TIM5 TI1 is connected to GPIO - * @arg TIM_TIM5_TI1_LSI: TIM5 TI1 is connected to LSI - * @arg TIM_TIM5_TI1_LSE: TIM5 TI1 is connected to LSE - * @arg TIM_TIM5_TI1_RTC_WKUP: TIM5 TI1 is connected to RTC wakeup interrupt - * @arg TIM_TIM5_TI1_COMP1: TIM5 TI1 is connected to COMP1 output - * @arg TIM_TIM5_TI1_COMP2: TIM5 TI1 is connected to COMP2 output (*) - * @arg TIM_TIM5_TI2_GPIO: TIM5 TI2 is connected to GPIO - * @arg TIM_TIM5_TI2_COMP1: TIM5 TI2 is connected to COMP1 output - * @arg TIM_TIM5_TI2_COMP2: TIM5 TI2 is connected to COMP2 output (*) - * - * For TIM8, the parameter is one of the following values: - * @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO - * @arg TIM_TIM8_TI1_COMP1: TIM8 TI1 is connected to COMP1 output - * @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output (*) - * - * For TIM15, the parameter is one of the following values: - * @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO - * @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE - * @arg TIM_TIM15_TI1_COMP1: TIM15 TI1 is connected to COMP1 output - * @arg TIM_TIM15_TI1_COMP2: TIM15 TI1 is connected to COMP2 output (*) - * @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO - * @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2 - * @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2 - * @arg TIM_TIM15_TI2_COMP2: TIM15 TI2 is connected to COMP2 output (*) - * - * For TIM16, the parameter can have the following values: - * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO - * @arg TIM_TIM16_TI1_MCO: TIM16 TI1 is connected to MCO - * @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI - * @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE - * @arg TIM_TIM16_TI1_RTC_WKUP: TIM16 TI1 is connected to RTC wakeup interrupt - * @arg TIM_TIM16_TI1_HSE_DIV32: TIM16 TI1 is connected to HSE/32 - * @arg TIM_TIM16_TI1_MSIS_1024: TIM16 TI1 is connected to MSIS/1024 - * @arg TIM_TIM16_TI1_MSIS_4: TIM16 TI1 is connected to MSIS/4 - * @arg TIM_TIM16_TI1_HSI_256: TIM16 TI1 is connected to HSI/256 - * - * For TIM17, the parameter can have the following values: - * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO - * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO - * @arg TIM_TIM17_TI1_LSI: TIM17 TI1 is connected to LSI - * @arg TIM_TIM17_TI1_LSE: TIM17 TI1 is connected to LSE - * @arg TIM_TIM17_TI1_RTC_WKUP: TIM17 TI1 is connected to RTC wakeup interrupt - * @arg TIM_TIM17_TI1_HSE_DIV32: TIM17 TI1 is connected to HSE/32 - * @arg TIM_TIM17_TI1_MSIS_1024: TIM17 TI1 is connected to MSIS/024 - * @arg TIM_TIM17_TI1_MSIS_4: TIM17 TI1 is connected to MSIS/4 - * @arg TIM_TIM17_TI1_HSI_256: TIM17 TI1 is connected to HSI/256 - * - * (*) Value not defined in all devices. \n - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISelection, uint32_t Channel) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check parameters */ - assert_param(IS_TIM_TISEL_INSTANCE(htim->Instance)); - assert_param(IS_TIM_TISEL(TISelection)); - - __HAL_LOCK(htim); - - switch (Channel) - { - case TIM_CHANNEL_1: - MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI1SEL, TISelection); - break; - case TIM_CHANNEL_2: - MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI2SEL, TISelection); - break; - case TIM_CHANNEL_4: - MODIFY_REG(htim->Instance->TISEL, TIM_TISEL_TI4SEL, TISelection); - break; - default: - status = HAL_ERROR; - break; - } - - __HAL_UNLOCK(htim); - - return status; -} - -/** - * @brief Group channel 5 and channel 1, 2 or 3 - * @param htim TIM handle. - * @param Channels specifies the reference signal(s) the OC5REF is combined with. - * This parameter can be any combination of the following values: - * TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC - * TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF - * TIM_GROUPCH5_OC2REFC: OC2REFC is the logical AND of OC2REFC and OC5REF - * TIM_GROUPCH5_OC3REFC: OC3REFC is the logical AND of OC3REFC and OC5REF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels) -{ - /* Check parameters */ - assert_param(IS_TIM_COMBINED3PHASEPWM_INSTANCE(htim->Instance)); - assert_param(IS_TIM_GROUPCH5(Channels)); - - /* Process Locked */ - __HAL_LOCK(htim); - - htim->State = HAL_TIM_STATE_BUSY; - - /* Clear GC5Cx bit fields */ - htim->Instance->CCR5 &= ~(TIM_CCR5_GC5C3 | TIM_CCR5_GC5C2 | TIM_CCR5_GC5C1); - - /* Set GC5Cx bit fields */ - htim->Instance->CCR5 |= Channels; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Disarm the designated break input (when it operates in bidirectional mode). - * @param htim TIM handle. - * @param BreakInput Break input to disarm - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @note The break input can be disarmed only when it is configured in - * bidirectional mode and when when MOE is reset. - * @note Purpose is to be able to have the input voltage back to high-state, - * whatever the time constant on the output . - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tmpbdtr; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - - switch (BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Check initial conditions */ - tmpbdtr = READ_REG(htim->Instance->BDTR); - if ((READ_BIT(tmpbdtr, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) && - (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) - { - /* Break input BRK is disarmed */ - SET_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM); - } - break; - } - - case TIM_BREAKINPUT_BRK2: - { - /* Check initial conditions */ - tmpbdtr = READ_REG(htim->Instance->BDTR); - if ((READ_BIT(tmpbdtr, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) && - (READ_BIT(tmpbdtr, TIM_BDTR_MOE) == 0U)) - { - /* Break input BRK is disarmed */ - SET_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM); - } - break; - } - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Arm the designated break input (when it operates in bidirectional mode). - * @param htim TIM handle. - * @param BreakInput Break input to arm - * This parameter can be one of the following values: - * @arg TIM_BREAKINPUT_BRK: Timer break input - * @arg TIM_BREAKINPUT_BRK2: Timer break 2 input - * @note Arming is possible at anytime, even if fault is present. - * @note Break input is automatically armed as soon as MOE bit is set. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_BREAKINPUT(BreakInput)); - - switch (BreakInput) - { - case TIM_BREAKINPUT_BRK: - { - /* Check initial conditions */ - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKBID) == TIM_BDTR_BKBID) - { - /* Break input BRK is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) - { - if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BKDSRM) != 0UL) - { - return HAL_TIMEOUT; - } - } - } - } - break; - } - - case TIM_BREAKINPUT_BRK2: - { - /* Check initial conditions */ - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2BID) == TIM_BDTR_BK2BID) - { - /* Break input BRK2 is re-armed automatically by hardware. Poll to check whether fault condition disappeared */ - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - while (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) - { - if ((HAL_GetTick() - tickstart) > TIM_BREAKINPUT_REARM_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if (READ_BIT(htim->Instance->BDTR, TIM_BDTR_BK2DSRM) != 0UL) - { - return HAL_TIMEOUT; - } - } - } - } - break; - } - default: - status = HAL_ERROR; - break; - } - - return status; -} - -/** - * @brief Enable dithering - * @param htim TIM handle - * @note Main usage is PWM mode - * @note This function must be called when timer is stopped or disabled (CEN =0) - * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: - * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) - * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers - * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers - * - ARR and CCRx values are limited to 0xFFEF in dithering mode for 16b timers - * (corresponds to 4094 for the integer part and 15 for the dithered part). - * @note Macros @ref __HAL_TIM_CALC_PERIOD_DITHER() __HAL_TIM_CALC_DELAY_DITHER() __HAL_TIM_CALC_PULSE_DITHER() - * can be used to calculate period (ARR) and delay (CCRx) value. - * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. - * @note Enabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. - * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() - * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DitheringEnable(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - SET_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); - return HAL_OK; -} - -/** - * @brief Disable dithering - * @param htim TIM handle - * @note This function must be called when timer is stopped or disabled (CEN =0) - * @note If dithering is activated, pay attention to ARR, CCRx, CNT interpretation: - * - CNT: only CNT[11:0] holds the non-dithered part for 16b timers (or CNT[26:0] for 32b timers) - * - ARR: ARR[15:4] holds the non-dithered part, and ARR[3:0] the dither part for 16b timers - * - CCRx: CCRx[15:4] holds the non-dithered part, and CCRx[3:0] the dither part for 16b timers - * - ARR and CCRx values are limited to 0xFFEF in dithering mode - * (corresponds to 4094 for the integer part and 15 for the dithered part). - * @note Disabling dithering, modifies automatically values of registers ARR/CCRx to keep the same integer part. - * So it may be necessary to read ARR value or CCRx value with macros @ref __HAL_TIM_GET_AUTORELOAD() - * __HAL_TIM_GET_COMPARE() and if necessary update Init structure field htim->Init.Period . - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DitheringDisable(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(htim->Instance)); - - CLEAR_BIT(htim->Instance->CR1, TIM_CR1_DITHEN); - return HAL_OK; -} - -/** - * @brief Initializes the pulse on compare pulse width and pulse prescaler - * @param htim TIM Output Compare handle - * @param PulseWidthPrescaler Pulse width prescaler - * This parameter can be a number between Min_Data = 0x0 and Max_Data = 0x7 - * @param PulseWidth Pulse width - * This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_OC_ConfigPulseOnCompare(TIM_HandleTypeDef *htim, - uint32_t PulseWidthPrescaler, - uint32_t PulseWidth) -{ - uint32_t tmpecr; - - /* Check the parameters */ - assert_param(IS_TIM_PULSEONCOMPARE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_PULSEONCOMPARE_WIDTH(PulseWidth)); - assert_param(IS_TIM_PULSEONCOMPARE_WIDTHPRESCALER(PulseWidthPrescaler)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Set the TIM state */ - htim->State = HAL_TIM_STATE_BUSY; - - /* Get the TIMx ECR register value */ - tmpecr = htim->Instance->ECR; - /* Reset the Pulse width prescaler and the Pulse width */ - tmpecr &= ~(TIM_ECR_PWPRSC | TIM_ECR_PW); - /* Set the Pulse width prescaler and Pulse width*/ - tmpecr |= PulseWidthPrescaler << TIM_ECR_PWPRSC_Pos; - tmpecr |= PulseWidth << TIM_ECR_PW_Pos; - /* Write to TIMx ECR */ - htim->Instance->ECR = tmpecr; - - /* Change the TIM state */ - htim->State = HAL_TIM_STATE_READY; - - /* Release Lock */ - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Configure preload source of Slave Mode Selection bitfield (SMS in SMCR register) - * @param htim TIM handle - * @param Source Source of slave mode selection preload - * This parameter can be one of the following values: - * @arg TIM_SMS_PRELOAD_SOURCE_UPDATE: Timer update event is used as source of Slave Mode Selection preload - * @arg TIM_SMS_PRELOAD_SOURCE_INDEX: Timer index event is used as source of Slave Mode Selection preload - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigSlaveModePreload(TIM_HandleTypeDef *htim, uint32_t Source) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_SLAVE_PRELOAD_SOURCE(Source)); - - MODIFY_REG(htim->Instance->SMCR, TIM_SMCR_SMSPS, Source); - return HAL_OK; -} - -/** - * @brief Enable preload of Slave Mode Selection bitfield (SMS in SMCR register) - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_EnableSlaveModePreload(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - - SET_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); - return HAL_OK; -} - -/** - * @brief Disable preload of Slave Mode Selection bitfield (SMS in SMCR register) - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DisableSlaveModePreload(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); - - CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_SMSPE); - return HAL_OK; -} - -/** - * @brief Enable deadtime preload - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_EnableDeadTimePreload(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - - SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); - return HAL_OK; -} - -/** - * @brief Disable deadtime preload - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DisableDeadTimePreload(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - - CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTPE); - return HAL_OK; -} - -/** - * @brief Configure deadtime - * @param htim TIM handle - * @param Deadtime Deadtime value - * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigDeadTime(TIM_HandleTypeDef *htim, uint32_t Deadtime) -{ - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DEADTIME(Deadtime)); - - MODIFY_REG(htim->Instance->BDTR, TIM_BDTR_DTG, Deadtime); - return HAL_OK; -} - -/** - * @brief Configure asymmetrical deadtime - * @param htim TIM handle - * @param FallingDeadtime Falling edge deadtime value - * @note This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigAsymmetricalDeadTime(TIM_HandleTypeDef *htim, uint32_t FallingDeadtime) -{ - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - assert_param(IS_TIM_DEADTIME(FallingDeadtime)); - - MODIFY_REG(htim->Instance->DTR2, TIM_DTR2_DTGF, FallingDeadtime); - return HAL_OK; -} - -/** - * @brief Enable asymmetrical deadtime - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_EnableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - - SET_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); - return HAL_OK; -} - -/** - * @brief Disable asymmetrical deadtime - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DisableAsymmetricalDeadTime(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); - - CLEAR_BIT(htim->Instance->DTR2, TIM_DTR2_DTAE); - return HAL_OK; -} - -/** - * @brief Configures the encoder index. - * @note warning in case of encoder mode clock plus direction - * @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X1 or @ref TIM_ENCODERMODE_CLOCKPLUSDIRECTION_X2 - * Direction must be set to @ref TIM_ENCODERINDEX_DIRECTION_UP_DOWN - * @param htim TIM handle. - * @param sEncoderIndexConfig Encoder index configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_ConfigEncoderIndex(TIM_HandleTypeDef *htim, - TIMEx_EncoderIndexConfigTypeDef *sEncoderIndexConfig) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - assert_param(IS_TIM_ENCODERINDEX_POLARITY(sEncoderIndexConfig->Polarity)); - assert_param(IS_TIM_ENCODERINDEX_PRESCALER(sEncoderIndexConfig->Prescaler)); - assert_param(IS_TIM_ENCODERINDEX_FILTER(sEncoderIndexConfig->Filter)); - assert_param(IS_TIM_ENCODERINDEX_BLANKING(sEncoderIndexConfig->Blanking)); - assert_param(IS_FUNCTIONAL_STATE(sEncoderIndexConfig->FirstIndexEnable)); - assert_param(IS_TIM_ENCODERINDEX_POSITION(sEncoderIndexConfig->Position)); - assert_param(IS_TIM_ENCODERINDEX_DIRECTION(sEncoderIndexConfig->Direction)); - - /* Process Locked */ - __HAL_LOCK(htim); - - /* Configures the TIMx External Trigger (ETR) which is used as Index input */ - TIM_ETR_SetConfig(htim->Instance, - sEncoderIndexConfig->Prescaler, - sEncoderIndexConfig->Polarity, - sEncoderIndexConfig->Filter); - - /* Configures the encoder index */ -#if defined (STM32U575xx) || defined (STM32U585xx) - if (HAL_GetREVID() >= REV_ID_B) /* supported in cut2 */ - { - MODIFY_REG(htim->Instance->ECR, - TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, - (sEncoderIndexConfig->Direction | - (sEncoderIndexConfig->Blanking) | - ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | - sEncoderIndexConfig->Position | - TIM_ECR_IE)); - } - else - { - MODIFY_REG(htim->Instance->ECR, - TIM_ECR_IDIR_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, - (sEncoderIndexConfig->Direction | - ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | - sEncoderIndexConfig->Position | - TIM_ECR_IE)); - } -#else - MODIFY_REG(htim->Instance->ECR, - TIM_ECR_IDIR_Msk | TIM_ECR_IBLK_Msk | TIM_ECR_FIDX_Msk | TIM_ECR_IPOS_Msk, - (sEncoderIndexConfig->Direction | - (sEncoderIndexConfig->Blanking) | - ((sEncoderIndexConfig->FirstIndexEnable == ENABLE) ? (0x1U << TIM_ECR_FIDX_Pos) : 0U) | - sEncoderIndexConfig->Position | - TIM_ECR_IE)); -#endif /* STM32U575xx || STM32U585xx */ - - __HAL_UNLOCK(htim); - - return HAL_OK; -} - -/** - * @brief Enable encoder index - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_EnableEncoderIndex(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - SET_BIT(htim->Instance->ECR, TIM_ECR_IE); - return HAL_OK; -} - -/** - * @brief Disable encoder index - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DisableEncoderIndex(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - CLEAR_BIT(htim->Instance->ECR, TIM_ECR_IE); - return HAL_OK; -} - -/** - * @brief Enable encoder first index - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_EnableEncoderFirstIndex(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - SET_BIT(htim->Instance->ECR, TIM_ECR_FIDX); - return HAL_OK; -} - -/** - * @brief Disable encoder first index - * @param htim TIM handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_TIMEx_DisableEncoderFirstIndex(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance)); - - CLEAR_BIT(htim->Instance->ECR, TIM_ECR_FIDX); - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group6 Extended Callbacks functions - * @brief Extended Callbacks functions - * -@verbatim - ============================================================================== - ##### Extended Callbacks functions ##### - ============================================================================== - [..] - This section provides Extended TIM callback functions: - (+) Timer Commutation callback - (+) Timer Break callback - -@endverbatim - * @{ - */ - -/** - * @brief Hall commutation changed callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutCallback could be implemented in the user file - */ -} -/** - * @brief Hall commutation changed half complete callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_CommutHalfCpltCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break detection callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_BreakCallback could be implemented in the user file - */ -} - -/** - * @brief Hall Break2 detection callback in non blocking mode - * @param htim: TIM handle - * @retval None - */ -__weak void HAL_TIMEx_Break2Callback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function Should not be modified, when the callback is needed, - the HAL_TIMEx_Break2Callback could be implemented in the user file - */ -} - -/** - * @brief Encoder index callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_EncoderIndexCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_EncoderIndexCallback could be implemented in the user file - */ -} - -/** - * @brief Direction change callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_DirectionChangeCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_DirectionChangeCallback could be implemented in the user file - */ -} - -/** - * @brief Index error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_IndexErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_IndexErrorCallback could be implemented in the user file - */ -} - -/** - * @brief Transition error callback in non-blocking mode - * @param htim TIM handle - * @retval None - */ -__weak void HAL_TIMEx_TransitionErrorCallback(TIM_HandleTypeDef *htim) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(htim); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_TIMEx_TransitionErrorCallback could be implemented in the user file - */ -} - -/** - * @} - */ - -/** @defgroup TIMEx_Exported_Functions_Group7 Extended Peripheral State functions - * @brief Extended Peripheral State functions - * -@verbatim - ============================================================================== - ##### Extended Peripheral State functions ##### - ============================================================================== - [..] - This subsection permits to get in run-time the status of the peripheral - and the data flow. - -@endverbatim - * @{ - */ - -/** - * @brief Return the TIM Hall Sensor interface handle state. - * @param htim TIM Hall Sensor handle - * @retval HAL state - */ -HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim) -{ - return htim->State; -} - -/** - * @brief Return actual state of the TIM complementary channel. - * @param htim TIM handle - * @param ChannelN TIM Complementary channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @retval TIM Complementary channel state - */ -HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) -{ - HAL_TIM_ChannelStateTypeDef channel_state; - - /* Check the parameters */ - assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, ChannelN)); - - channel_state = TIM_CHANNEL_N_STATE_GET(htim, ChannelN); - - return channel_state; -} -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -/** @defgroup TIMEx_Private_Functions TIM Extended Private Functions - * @{ - */ - -/** - * @brief TIM DMA Commutation callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationCallback(htim); -#else - HAL_TIMEx_CommutCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - -/** - * @brief TIM DMA Commutation half complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -void TIMEx_DMACommutationHalfCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Change the htim state */ - htim->State = HAL_TIM_STATE_READY; - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->CommutationHalfCpltCallback(htim); -#else - HAL_TIMEx_CommutHalfCpltCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ -} - - -/** - * @brief TIM DMA Delay Pulse complete callback (complementary channel). - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC4]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4; - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->PWM_PulseFinishedCallback(htim); -#else - HAL_TIM_PWM_PulseFinishedCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief TIM DMA error callback (complementary channel) - * @param hdma pointer to DMA handle. - * @retval None - */ -static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) -{ - TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - if (hdma == htim->hdma[TIM_DMA_ID_CC1]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC2]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY); - } - else if (hdma == htim->hdma[TIM_DMA_ID_CC3]) - { - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3; - TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY); - } - else - { - /* nothing to do */ - } - -#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) - htim->ErrorCallback(htim); -#else - HAL_TIM_ErrorCallback(htim); -#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ - - htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED; -} - -/** - * @brief Enables or disables the TIM Capture Compare Channel xN. - * @param TIMx to select the TIM peripheral - * @param Channel specifies the TIM Channel - * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 - * @param ChannelNState specifies the TIM Channel CCxNE bit new state. - * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. - * @retval None - */ -static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelNState) -{ - uint32_t tmp; - - tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */ - - /* Reset the CCxNE Bit */ - TIMx->CCER &= ~tmp; - - /* Set or reset the CCxNE Bit */ - TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */ -} - -/** - * @brief Enable HSE/32 . - * @note This function should be called to enable the HSE/32 when it is selected as TIM17_TI1 or TIM16_TI1 input - * source. - * @param htim TIM handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_TIMEx_EnableHSE32(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance)); - -#if defined (STM32U575xx) || defined (STM32U585xx) - /* The Cut1.x contains a limitation when using HSE/32 as input capture for TIM16 - Bug ID 56: On TIM16, the HSE/32 input capture requires the set of HSE32EN bit of TIM17 Option Register */ - if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */ - { - __HAL_RCC_TIM17_CLK_ENABLE(); - SET_BIT(TIM17->OR1, TIM_OR1_HSE32EN); - } - else - { - SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); - } -#else - SET_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); -#endif /* STM32U575xx || STM32U585xx */ - - return HAL_OK; -} - -/** - * @brief Disable HSE/32 . - * @note This function should be called to Disable the HSE/32 . - * @param htim TIM handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_TIMEx_DisableHSE32(TIM_HandleTypeDef *htim) -{ - /* Check the parameters */ - assert_param(IS_TIM_HSE32_INSTANCE(htim->Instance)); - -#if defined (STM32U575xx) || defined (STM32U585xx) - if (HAL_GetREVID() < REV_ID_B) /* Cut1.x */ - { - __HAL_RCC_TIM17_CLK_ENABLE(); - CLEAR_BIT(TIM17->OR1, TIM_OR1_HSE32EN); - } - else - { - CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); - } -#else - CLEAR_BIT(htim->Instance->OR1, TIM_OR1_HSE32EN); -#endif /* STM32U575xx || STM32U585xx */ - - return HAL_OK; -} -/** - * @} - */ - -#endif /* HAL_TIM_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c deleted file mode 100644 index a73760bec..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart.c +++ /dev/null @@ -1,4797 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_uart.c - * @author MCD Application Team - * @brief UART HAL module driver. - * This file provides firmware functions to manage the following - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + IO operation functions - * + Peripheral Control functions - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - =============================================================================== - ##### How to use this driver ##### - =============================================================================== - [..] - The UART HAL driver can be used as follows: - - (#) Declare a UART_HandleTypeDef handle structure (eg. UART_HandleTypeDef huart). - (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API: - (++) Enable the USARTx interface clock. - (++) UART pins configuration: - (+++) Enable the clock for the UART GPIOs. - (+++) Configure these UART pins as alternate function pull-up. - (++) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT() - and HAL_UART_Receive_IT() APIs): - (+++) Configure the USARTx interrupt priority. - (+++) Enable the NVIC USART IRQ handle. - (++) UART interrupts handling: - -@@- The specific UART interrupts (Transmission complete interrupt, - RXNE interrupt, RX/TX FIFOs related interrupts and Error Interrupts) - are managed using the macros __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() - inside the transmit and receive processes. - (++) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA() - and HAL_UART_Receive_DMA() APIs): - (+++) Declare a DMA handle structure for the Tx/Rx channel. - (+++) Enable the DMAx interface clock. - (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. - (+++) Configure the DMA Tx/Rx channel. - (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle. - (+++) Configure the priority and enable the NVIC for the transfer complete - interrupt on the DMA Tx/Rx channel. - - (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Prescaler value , Hardware - flow control and Mode (Receiver/Transmitter) in the huart handle Init structure. - - (#) If required, program UART advanced features (TX/RX pins swap, auto Baud rate detection,...) - in the huart handle AdvancedInit structure. - - (#) For the UART asynchronous mode, initialize the UART registers by calling - the HAL_UART_Init() API. - - (#) For the UART Half duplex mode, initialize the UART registers by calling - the HAL_HalfDuplex_Init() API. - - (#) For the UART LIN (Local Interconnection Network) mode, initialize the UART registers - by calling the HAL_LIN_Init() API. - - (#) For the UART Multiprocessor mode, initialize the UART registers - by calling the HAL_MultiProcessor_Init() API. - - (#) For the UART RS485 Driver Enabled mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - [..] - (@) These API's (HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init(), HAL_MultiProcessor_Init(), - also configure the low level Hardware GPIO, CLOCK, CORTEX...etc) by - calling the customized HAL_UART_MspInit() API. - - ##### Callback registration ##### - ================================== - - [..] - The compilation define USE_HAL_UART_REGISTER_CALLBACKS when set to 1 - allows the user to configure dynamically the driver callbacks. - - [..] - Use Function HAL_UART_RegisterCallback() to register a user callback. - Function HAL_UART_RegisterCallback() allows to register following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) WakeupCallback : Wakeup Callback. - (+) RxFifoFullCallback : Rx Fifo Full Callback. - (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - - [..] - Use function HAL_UART_UnRegisterCallback() to reset a callback to the default - weak function. - HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) TxHalfCpltCallback : Tx Half Complete Callback. - (+) TxCpltCallback : Tx Complete Callback. - (+) RxHalfCpltCallback : Rx Half Complete Callback. - (+) RxCpltCallback : Rx Complete Callback. - (+) ErrorCallback : Error Callback. - (+) AbortCpltCallback : Abort Complete Callback. - (+) AbortTransmitCpltCallback : Abort Transmit Complete Callback. - (+) AbortReceiveCpltCallback : Abort Receive Complete Callback. - (+) WakeupCallback : Wakeup Callback. - (+) RxFifoFullCallback : Rx Fifo Full Callback. - (+) TxFifoEmptyCallback : Tx Fifo Empty Callback. - (+) MspInitCallback : UART MspInit. - (+) MspDeInitCallback : UART MspDeInit. - - [..] - For specific callback RxEventCallback, use dedicated registration/reset functions: - respectively HAL_UART_RegisterRxEventCallback() , HAL_UART_UnRegisterRxEventCallback(). - - [..] - By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback(). - Exception done for MspInit and MspDeInit functions that are respectively - reset to the legacy weak functions in the HAL_UART_Init() - and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand). - If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand). - - [..] - Callbacks can be registered/unregistered in HAL_UART_STATE_READY state only. - Exception done MspInit/MspDeInit that can be registered/unregistered - in HAL_UART_STATE_READY or HAL_UART_STATE_RESET state, thus registered (user) - MspInit/DeInit callbacks can be used during the Init/DeInit. - In that case first register the MspInit/MspDeInit user callbacks - using HAL_UART_RegisterCallback() before calling HAL_UART_DeInit() - or HAL_UART_Init() function. - - [..] - When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available - and weak callbacks are used. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup UART UART - * @brief HAL UART module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UART_Private_Constants UART Private Constants - * @{ - */ -#define USART_CR1_FIELDS ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | \ - USART_CR1_OVER8 | USART_CR1_FIFOEN)) /*!< UART or USART CR1 fields of parameters set by UART_SetConfig API */ - -#define USART_CR3_FIELDS ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE | USART_CR3_ONEBIT | USART_CR3_TXFTCFG | \ - USART_CR3_RXFTCFG)) /*!< UART or USART CR3 fields of parameters set by UART_SetConfig API */ - -#define LPUART_BRR_MIN 0x00000300U /* LPUART BRR minimum authorized value */ -#define LPUART_BRR_MAX 0x000FFFFFU /* LPUART BRR maximum authorized value */ - -#define UART_BRR_MIN 0x10U /* UART BRR minimum authorized value */ -#define UART_BRR_MAX 0x0000FFFFU /* UART BRR maximum authorized value */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @addtogroup UART_Private_Functions - * @{ - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart); -#if defined(HAL_DMA_MODULE_ENABLED) -static void UART_EndTxTransfer(UART_HandleTypeDef *huart); -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma); -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma); -static void UART_DMAError(DMA_HandleTypeDef *hdma); -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma); -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma); -#endif /* HAL_DMA_MODULE_ENABLED */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart); -static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart); -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart); -static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart); -static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart); -/** - * @} - */ - -/* Private variables ---------------------------------------------------------*/ -/** @addtogroup UART_Private_variables - * @{ - */ -const uint16_t UARTPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; -/** - * @} - */ - -/* Exported Constants --------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UART_Exported_Functions UART Exported Functions - * @{ - */ - -/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init()and HAL_MultiProcessor_Init()API - follow respectively the UART asynchronous, UART Half duplex, UART LIN mode - and UART multiprocessor mode configuration procedures (details for the procedures - are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the UART mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - if (huart->Init.HwFlowCtl != UART_HWCONTROL_NONE) - { - /* Check the parameters */ - assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance)); - } - else - { - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - } - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In asynchronous mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Initialize the half-duplex mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check UART instance */ - assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In half-duplex mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_HDSEL); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the LIN mode according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param BreakDetectLength Specifies the LIN break detection length. - * This parameter can be one of the following values: - * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection - * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the LIN UART instance */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - /* Check the Break detection length parameter */ - assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength)); - - /* LIN mode limited to 16-bit oversampling only */ - if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - return HAL_ERROR; - } - /* LIN mode limited to 8-bit data length */ - if (huart->Init.WordLength != UART_WORDLENGTH_8B) - { - return HAL_ERROR; - } - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In LIN mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_CLKEN); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN)); - - /* Enable the LIN mode by setting the LINEN bit in the CR2 register */ - SET_BIT(huart->Instance->CR2, USART_CR2_LINEN); - - /* Set the USART LIN Break detection length. */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief Initialize the multiprocessor mode according to the specified - * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart UART handle. - * @param Address UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod Specifies the UART wakeup method. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection - * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark - * @note If the user resorts to idle line detection wake up, the Address parameter - * is useless and ignored by the initialization function. - * @note If the user resorts to address mark wake up, the address length detection - * is configured by default to 4 bits only. For the UART to be able to - * manage 6-, 7- or 8-bit long addresses detection, the API - * HAL_MultiProcessorEx_AddressLength_Set() must be called after - * HAL_MultiProcessor_Init(). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the wake up method parameter */ - assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* In multiprocessor mode, the following bits must be kept cleared: - - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN, HDSEL and IREN bits in the USART_CR3 register. */ - CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); - CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); - - if (WakeUpMethod == UART_WAKEUPMETHOD_ADDRESSMARK) - { - /* If address mark wake up method is chosen, set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)Address << UART_CR2_ADDRESS_LSB_POS)); - } - - /* Set the wake up method by setting the WAKE bit in the CR1 register */ - MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod); - - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - - -/** - * @brief DeInitialize the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); - - huart->gState = HAL_UART_STATE_BUSY; - - __HAL_UART_DISABLE(huart); - - huart->Instance->CR1 = 0x0U; - huart->Instance->CR2 = 0x0U; - huart->Instance->CR3 = 0x0U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - if (huart->MspDeInitCallback == NULL) - { - huart->MspDeInitCallback = HAL_UART_MspDeInit; - } - /* DeInit the low level hardware */ - huart->MspDeInitCallback(huart); -#else - /* DeInit the low level hardware */ - HAL_UART_MspDeInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_RESET; - huart->RxState = HAL_UART_STATE_RESET; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Initialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspInit can be implemented in the user file - */ -} - -/** - * @brief DeInitialize the UART MSP. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_MspDeInit can be implemented in the user file - */ -} - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User UART Callback - * To be used to override the weak predefined callback - * @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), - * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register - * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID - * @param huart uart handle - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID - * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID, - pUART_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (huart->gState == HAL_UART_STATE_READY) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = pCallback; - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = pCallback; - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = pCallback; - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = pCallback; - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = pCallback; - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = pCallback; - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = pCallback; - break; - - case HAL_UART_RX_FIFO_FULL_CB_ID : - huart->RxFifoFullCallback = pCallback; - break; - - case HAL_UART_TX_FIFO_EMPTY_CB_ID : - huart->TxFifoEmptyCallback = pCallback; - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else if (huart->gState == HAL_UART_STATE_RESET) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = pCallback; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = pCallback; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister an UART Callback - * UART callaback is redirected to the weak predefined callback - * @note The HAL_UART_UnRegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(), - * HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to un-register - * callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID - * @param huart uart handle - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_UART_TX_HALFCOMPLETE_CB_ID Tx Half Complete Callback ID - * @arg @ref HAL_UART_TX_COMPLETE_CB_ID Tx Complete Callback ID - * @arg @ref HAL_UART_RX_HALFCOMPLETE_CB_ID Rx Half Complete Callback ID - * @arg @ref HAL_UART_RX_COMPLETE_CB_ID Rx Complete Callback ID - * @arg @ref HAL_UART_ERROR_CB_ID Error Callback ID - * @arg @ref HAL_UART_ABORT_COMPLETE_CB_ID Abort Complete Callback ID - * @arg @ref HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID Abort Transmit Complete Callback ID - * @arg @ref HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID Abort Receive Complete Callback ID - * @arg @ref HAL_UART_WAKEUP_CB_ID Wakeup Callback ID - * @arg @ref HAL_UART_RX_FIFO_FULL_CB_ID Rx Fifo Full Callback ID - * @arg @ref HAL_UART_TX_FIFO_EMPTY_CB_ID Tx Fifo Empty Callback ID - * @arg @ref HAL_UART_MSPINIT_CB_ID MspInit Callback ID - * @arg @ref HAL_UART_MSPDEINIT_CB_ID MspDeInit Callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterCallback(UART_HandleTypeDef *huart, HAL_UART_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (HAL_UART_STATE_READY == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_TX_HALFCOMPLETE_CB_ID : - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - break; - - case HAL_UART_TX_COMPLETE_CB_ID : - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - break; - - case HAL_UART_RX_HALFCOMPLETE_CB_ID : - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - break; - - case HAL_UART_RX_COMPLETE_CB_ID : - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - break; - - case HAL_UART_ERROR_CB_ID : - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - break; - - case HAL_UART_ABORT_COMPLETE_CB_ID : - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - break; - - case HAL_UART_ABORT_TRANSMIT_COMPLETE_CB_ID : - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak - AbortTransmitCpltCallback */ - break; - - case HAL_UART_ABORT_RECEIVE_COMPLETE_CB_ID : - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak - AbortReceiveCpltCallback */ - break; - - case HAL_UART_RX_FIFO_FULL_CB_ID : - huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ - break; - - case HAL_UART_TX_FIFO_EMPTY_CB_ID : - huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ - break; - - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; /* Legacy weak MspInitCallback */ - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; /* Legacy weak MspDeInitCallback */ - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else if (HAL_UART_STATE_RESET == huart->gState) - { - switch (CallbackID) - { - case HAL_UART_MSPINIT_CB_ID : - huart->MspInitCallback = HAL_UART_MspInit; - break; - - case HAL_UART_MSPDEINIT_CB_ID : - huart->MspDeInitCallback = HAL_UART_MspDeInit; - break; - - default : - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - break; - } - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Register a User UART Rx Event Callback - * To be used instead of the weak predefined callback - * @param huart Uart handle - * @param pCallback Pointer to the Rx Event Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pUART_RxEventCallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if (huart->RxState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = pCallback; - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief UnRegister the UART Rx Event Callback - * UART Rx Event Callback is redirected to the weak HAL_UARTEx_RxEventCallback() predefined callback - * @param huart Uart handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (huart->RxState == HAL_UART_STATE_READY) - { - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */ - } - else - { - huart->ErrorCode |= HAL_UART_ERROR_INVALID_CALLBACK; - - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group2 IO operation functions - * @brief UART Transmit/Receive functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of functions allowing to manage the UART asynchronous - and Half duplex data transfers. - - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected - - (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() - - (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() - - (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() - - (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() - - (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() - - (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() - - (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced - reception services: - (+) HAL_UARTEx_RxEventCallback() - - (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. - Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. - - -@- In the Half duplex communication, it is forbidden to run the transmit - and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. - -@endverbatim - * @{ - */ - -/** - * @brief Send an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @note When FIFO mode is enabled, writing a data in the TDR register adds one - * data to the TXFIFO. Write operations to the TDR register are performed - * when TXFNF flag is set. From hardware perspective, TXFNF flag and - * TXE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - const uint8_t *pdata8bits; - const uint16_t *pdata16bits; - uint32_t tickstart; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - -#if defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - -#endif /* USART_DMAREQUESTS_SW_WA */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - /* In case of 9bits/No Parity transfer, pData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (const uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - while (huart->TxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, tickstart, Timeout) != HAL_OK) - { - - huart->gState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - huart->Instance->TDR = (uint16_t)(*pdata16bits & 0x01FFU); - pdata16bits++; - } - else - { - huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); - pdata8bits++; - } - huart->TxXferCount--; - } - - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) - { - huart->gState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in blocking mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and - * RXNE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @param Timeout Timeout duration. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - -#if defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - -#endif /* USART_DMAREQUESTS_SW_WA */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - huart->RxXferCount--; - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Send an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) -{ - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - -#if defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Tx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - } - -#endif /* USART_DMAREQUESTS_SW_WA */ - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - huart->TxISR = NULL; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - /* Configure Tx interrupt processing */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT_FIFOEN; - } - else - { - huart->TxISR = UART_TxISR_8BIT_FIFOEN; - } - - /* Enable the TX FIFO threshold interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - } - else - { - /* Set the Tx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->TxISR = UART_TxISR_16BIT; - } - else - { - huart->TxISR = UART_TxISR_8BIT; - } - - /* Enable the Transmit Data Register Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); - } - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - -#if defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - } - -#endif /* USART_DMAREQUESTS_SW_WA */ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - return (UART_Start_Receive_IT(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Send an amount of data in DMA mode. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the sent data is handled as a set of u16. In this case, Size must indicate the number - * of u16 provided through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be sent. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - uint16_t nbByte = Size; - - /* Check that a Tx process is not already ongoing */ - if (huart->gState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->pTxBuffPtr = pData; - huart->TxXferSize = Size; - huart->TxXferCount = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->gState = HAL_UART_STATE_BUSY_TX; - - if (huart->hdmatx != NULL) - { - /* Set the UART DMA transfer complete callback */ - huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmatx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmatx->XferAbortCallback = NULL; - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - nbByte = Size * 2U; - } - - /* Check linked list mode */ - if ((huart->hdmatx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if ((huart->hdmatx->LinkedListQueue != NULL) && (huart->hdmatx->LinkedListQueue->Head != NULL)) - { - /* Set DMA data size */ - huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; - - /* Set DMA source address */ - huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = (uint32_t)huart->pTxBuffPtr; - - /* Set DMA destination address */ - huart->hdmatx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = - (uint32_t)&huart->Instance->TDR; - - /* Enable the UART transmit DMA channel */ - status = HAL_DMAEx_List_Start_IT(huart->hdmatx); - } - else - { - /* Update status */ - status = HAL_ERROR; - } - } - else - { - /* Enable the UART transmit DMA channel */ - status = HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, nbByte); - } - - if (status != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - /* Restore huart->gState to ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } - } - /* Clear the TC flag in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); - - /* Enable the DMA transfer for transmit request by setting the DMAT bit - in the UART CR3 register */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in DMA mode. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of u16. In this case, Size must indicate the number - * of u16 available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to Standard reception */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - return (UART_Start_Receive_DMA(huart, pData, Size)); - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Pause the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) -{ - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - /* Suspend the UART DMA Tx channel : use blocking DMA Suspend API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Suspend callback to Null. - No call back execution at end of DMA Suspend procedure */ - huart->hdmatx->XferSuspendCallback = NULL; - - if (HAL_DMAEx_Suspend(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - /* Suspend the UART DMA Rx channel : use blocking DMA Suspend API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Set the UART DMA Suspend callback to Null. - No call back execution at end of DMA Suspend procedure */ - huart->hdmarx->XferSuspendCallback = NULL; - - if (HAL_DMAEx_Suspend(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - return HAL_OK; -} - -/** - * @brief Resume the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) -{ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - /* Resume the UART DMA Tx channel */ - if (huart->hdmatx != NULL) - { - if (HAL_DMAEx_Resume(huart->hdmatx) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_ERROR; - } - } - } - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - /* Clear the Overrun flag before resuming the Rx transfer */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Re-enable PE and ERR (Frame error, noise error, overrun error) interrupts */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - } - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Resume the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - if (HAL_DMAEx_Resume(huart->hdmarx) != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_ERROR; - } - } - } - - return HAL_OK; -} - -/** - * @brief Stop the DMA Transfer. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) -{ - /* The Lock is not implemented on this API to allow the user application - to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback() / - HAL_UART_TxHalfCpltCallback / HAL_UART_RxHalfCpltCallback: - indeed, when HAL_DMA_Abort() API is called, the DMA TX/RX Transfer or Half Transfer complete - interrupt is generated if the DMA transfer interruption occurs at the middle or at the end of - the stream and the corresponding call back is executed. */ - - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - /* Stop UART DMA Tx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - - /* Abort the UART DMA Tx channel */ - if (huart->hdmatx != NULL) - { - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - - UART_EndRxTransfer(huart); - } - - return HAL_OK; -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Abort ongoing transfers (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) -{ - /* Disable TXE, TC, RXNE, PE, RXFT, TXFT and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | - USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Tx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) -{ - /* Disable TCIE, TXEIE and TXFTIE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Tx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Tx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmatx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmatx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (blocking mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort (in case of transfer in DMA mode) - * - Set handle State to READY - * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) -{ - /* Disable PEIE, EIE, RXNEIE and RXFTIE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE | USART_CR3_RXFTIE); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Rx channel : use blocking DMA Abort API (no callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback to Null. - No call back execution at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = NULL; - - if (HAL_DMA_Abort(huart->hdmarx) != HAL_OK) - { - if (HAL_DMA_GetError(huart->hdmarx) == HAL_DMA_ERROR_TIMEOUT) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - return HAL_TIMEOUT; - } - } - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - return HAL_OK; -} - -/** - * @brief Abort ongoing transfers (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx and Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) -{ - uint32_t abortcplt = 1U; - - /* Disable interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_TCIE | USART_CR1_RXNEIE_RXFNEIE | - USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE | USART_CR3_TXFTIE)); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - -#if defined(HAL_DMA_MODULE_ENABLED) - /* If DMA Tx and/or DMA Rx Handles are associated to UART Handle, DMA Abort complete callbacks should be initialised - before any call to DMA Abort functions */ - /* DMA Tx Handle is valid */ - if (huart->hdmatx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Tx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { - huart->hdmatx->XferAbortCallback = UART_DMATxAbortCallback; - } - else - { - huart->hdmatx->XferAbortCallback = NULL; - } - } - /* DMA Rx Handle is valid */ - if (huart->hdmarx != NULL) - { - /* Set DMA Abort Complete callback if UART DMA Rx request if enabled. - Otherwise, set it to NULL */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - huart->hdmarx->XferAbortCallback = UART_DMARxAbortCallback; - } - else - { - huart->hdmarx->XferAbortCallback = NULL; - } - } - - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable DMA Tx at UART level */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* UART Tx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - huart->hdmatx->XferAbortCallback = NULL; - } - else - { - abortcplt = 0U; - } - } - } - - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* UART Rx DMA Abort callback has already been initialised : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - huart->hdmarx->XferAbortCallback = NULL; - abortcplt = 1U; - } - else - { - abortcplt = 0U; - } - } - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ - if (abortcplt == 1U) - { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Transmit transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Tx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Tx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TCIE | USART_CR1_TXEIE_TXFNFIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort the UART DMA Tx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Tx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Tx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmatx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmatx->XferAbortCallback = UART_DMATxOnlyAbortCallback; - - /* Abort DMA TX */ - if (HAL_DMA_Abort_IT(huart->hdmatx) != HAL_OK) - { - /* Call Directly huart->hdmatx->XferAbortCallback function in case of error */ - huart->hdmatx->XferAbortCallback(huart->hdmatx); - } - } - else - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else -#endif /* HAL_DMA_MODULE_ENABLED */ - { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - - /* Clear TxISR function pointers */ - huart->TxISR = NULL; - - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Abort ongoing Receive transfer (Interrupt mode). - * @param huart UART handle. - * @note This procedure could be used for aborting any ongoing Rx transfer started in Interrupt or DMA mode. - * This procedure performs following operations : - * - Disable UART Interrupts (Rx) - * - Disable the DMA transfer in the peripheral register (if enabled) - * - Abort DMA transfer by calling HAL_DMA_Abort_IT (in case of transfer in DMA mode) - * - Set handle State to READY - * - At abort completion, call user abort complete callback - * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be - * considered as completed only when user abort complete callback is executed (not when exiting function). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* If Reception till IDLE event was ongoing, disable IDLEIE interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_IDLEIE)); - } - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Rx channel : use non blocking DMA Abort API (callback) */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_AbortCpltCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMARxOnlyAbortCallback; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else -#endif /* HAL_DMA_MODULE_ENABLED */ - { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - - /* Clear RxISR function pointer */ - huart->pRxBuffPtr = NULL; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* As no DMA to be aborted, call directly user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - - return HAL_OK; -} - -/** - * @brief Handle UART interrupt request. - * @param huart UART handle. - * @retval None - */ -void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) -{ - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - - uint32_t errorflags; - uint32_t errorcode; - - /* If no error occurs */ - errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); - if (errorflags == 0U) - { - /* UART in mode Receiver ---------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) - || ((cr3its & USART_CR3_RXFTIE) != 0U))) - { - if (huart->RxISR != NULL) - { - huart->RxISR(huart); - } - return; - } - } - - /* If some errors occur */ - if ((errorflags != 0U) - && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) - || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) - { - /* UART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* UART Over-Run interrupt occurred -----------------------------------------*/ - if (((isrflags & USART_ISR_ORE) != 0U) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || - ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - huart->ErrorCode |= HAL_UART_ERROR_ORE; - } - - /* UART Receiver Timeout interrupt occurred ---------------------------------*/ - if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - huart->ErrorCode |= HAL_UART_ERROR_RTO; - } - - /* Call UART Error Call back function if need be ----------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* UART in mode Receiver --------------------------------------------------*/ - if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) - && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) - || ((cr3its & USART_CR3_RXFTIE) != 0U))) - { - if (huart->RxISR != NULL) - { - huart->RxISR(huart); - } - } - - /* If Error is to be considered as blocking : - - Receiver Timeout error in Reception - - Overrun error in Reception - - any error occurs in DMA mode reception - */ - errorcode = huart->ErrorCode; - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || - ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) - { - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ - UART_EndRxTransfer(huart); - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Abort the UART DMA Rx channel if enabled */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the UART DMA Rx request if enabled */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Abort the UART DMA Rx channel */ - if (huart->hdmarx != NULL) - { - /* Set the UART DMA Abort callback : - will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ - huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; - - /* Abort DMA RX */ - if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) - { - /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ - huart->hdmarx->XferAbortCallback(huart->hdmarx); - } - } - else - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - - } - } - else -#endif /* HAL_DMA_MODULE_ENABLED */ - { - /* Call user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - else - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - return; - - } /* End if some error occurs */ - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - && ((isrflags & USART_ISR_IDLE) != 0U) - && ((cr1its & USART_ISR_IDLE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - -#if defined(HAL_DMA_MODULE_ENABLED) - /* Check if DMA mode is enabled in UART */ - if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) - { - /* DMA mode enabled */ - /* Check received length : If all expected data are received, do nothing, - (DMA cplt callback will be called). - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); - if ((nb_remaining_rx_data > 0U) - && (nb_remaining_rx_data < huart->RxXferSize)) - { - /* Reception is not complete */ - huart->RxXferCount = nb_remaining_rx_data; - - /* In Normal mode, end DMA xfer and HAL UART Rx process*/ - if (huart->hdmarx->Mode != DMA_LINKEDLIST_CIRCULAR) - { - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Last bytes received, so no need as the abort is immediate */ - (void)HAL_DMA_Abort(huart->hdmarx); - } - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Idle Event */ - huart->RxEventType = HAL_UART_RXEVENT_IDLE; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - return; - } - else - { -#endif /* HAL_DMA_MODULE_ENABLED */ - /* DMA mode not enabled */ - /* Check received length : If all expected data are received, do nothing. - Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ - uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; - if ((huart->RxXferCount > 0U) - && (nb_rx_data > 0U)) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Idle Event */ - huart->RxEventType = HAL_UART_RXEVENT_IDLE; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxEventCallback(huart, nb_rx_data); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, nb_rx_data); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - return; -#if defined(HAL_DMA_MODULE_ENABLED) - } -#endif /* HAL_DMA_MODULE_ENABLED */ - } - - /* UART in mode Transmitter ------------------------------------------------*/ - if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) - && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) - || ((cr3its & USART_CR3_TXFTIE) != 0U))) - { - if (huart->TxISR != NULL) - { - huart->TxISR(huart); - } - return; - } - - /* UART in mode Transmitter (transmission end) -----------------------------*/ - if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) - { - UART_EndTransmit_IT(huart); - return; - } - - /* UART TX Fifo Empty occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Tx Fifo Empty Callback */ - huart->TxFifoEmptyCallback(huart); -#else - /* Call legacy weak Tx Fifo Empty Callback */ - HAL_UARTEx_TxFifoEmptyCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - return; - } - - /* UART RX Fifo Full occurred ----------------------------------------------*/ - if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Rx Fifo Full Callback */ - huart->RxFifoFullCallback(huart); -#else - /* Call legacy weak Rx Fifo Full Callback */ - HAL_UARTEx_RxFifoFullCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - return; - } -} - -/** - * @brief Tx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_TxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Tx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_TxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_RxCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Rx Half Transfer completed callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE: This function should not be modified, when the callback is needed, - the HAL_UART_RxHalfCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART error callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_ErrorCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortTransmitCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortTransmitCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief UART Abort Receive Complete callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UART_AbortReceiveCpltCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UART_AbortReceiveCpltCallback can be implemented in the user file. - */ -} - -/** - * @brief Reception Event Callback (Rx event notification called after use of advanced reception service). - * @param huart UART handle - * @param Size Number of data available in application reception buffer (indicates a position in - * reception buffer until which, data are available) - * @retval None - */ -__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - UNUSED(Size); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxEventCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions - * @brief UART control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to control the UART. - (+) HAL_UART_ReceiverTimeout_Config() API allows to configure the receiver timeout value on the fly - (+) HAL_UART_EnableReceiverTimeout() API enables the receiver timeout feature - (+) HAL_UART_DisableReceiverTimeout() API disables the receiver timeout feature - (+) HAL_MultiProcessor_EnableMuteMode() API enables mute mode - (+) HAL_MultiProcessor_DisableMuteMode() API disables mute mode - (+) HAL_MultiProcessor_EnterMuteMode() API enters mute mode - (+) UART_SetConfig() API configures the UART peripheral - (+) UART_AdvFeatureConfig() API optionally configures the UART advanced features - (+) UART_CheckIdleState() API ensures that TEACK and/or REACK are set after initialization - (+) HAL_HalfDuplex_EnableTransmitter() API disables receiver and enables transmitter - (+) HAL_HalfDuplex_EnableReceiver() API disables transmitter and enables receiver - (+) HAL_LIN_SendBreak() API transmits the break characters -@endverbatim - * @{ - */ - -/** - * @brief Update on the fly the receiver timeout value in RTOR register. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @param TimeoutValue receiver timeout value in number of baud blocks. The timeout - * value must be less or equal to 0x0FFFFFFFF. - * @retval None - */ -void HAL_UART_ReceiverTimeout_Config(UART_HandleTypeDef *huart, uint32_t TimeoutValue) -{ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - assert_param(IS_UART_RECEIVER_TIMEOUT_VALUE(TimeoutValue)); - MODIFY_REG(huart->Instance->RTOR, USART_RTOR_RTO, TimeoutValue); - } -} - -/** - * @brief Enable the UART receiver timeout feature. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_EnableReceiverTimeout(UART_HandleTypeDef *huart) -{ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Set the USART RTOEN bit */ - SET_BIT(huart->Instance->CR2, USART_CR2_RTOEN); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Disable the UART receiver timeout feature. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UART_DisableReceiverTimeout(UART_HandleTypeDef *huart) -{ - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear the USART RTOEN bit */ - CLEAR_BIT(huart->Instance->CR2, USART_CR2_RTOEN); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } - } - else - { - return HAL_ERROR; - } -} - -/** - * @brief Enable UART in mute mode (does not mean UART enters mute mode; - * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Enable USART mute mode by setting the MME bit in the CR1 register */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Disable UART mute mode (does not mean the UART actually exits mute mode - * as it may not have been in mute mode at this very moment). - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable USART mute mode by clearing the MME bit in the CR1 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_MME); - - huart->gState = HAL_UART_STATE_READY; - - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Enter UART mute mode (means UART actually enters mute mode). - * @note To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart UART handle. - * @retval None - */ -void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) -{ - __HAL_UART_SEND_REQ(huart, UART_MUTE_MODE_REQUEST); -} - -/** - * @brief Enable the UART transmitter and disable the UART receiver. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TE); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enable the UART receiver and disable the UART transmitter. - * @param huart UART handle. - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) -{ - __HAL_LOCK(huart); - huart->gState = HAL_UART_STATE_BUSY; - - /* Clear TE and RE bits */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TE | USART_CR1_RE)); - - /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RE); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - - -/** - * @brief Transmit break characters. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) -{ - /* Check the parameters */ - assert_param(IS_UART_LIN_INSTANCE(huart->Instance)); - - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Send break characters */ - __HAL_UART_SEND_REQ(huart, UART_SENDBREAK_REQUEST); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @} - */ - -/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Error functions - * @brief UART Peripheral State functions - * -@verbatim - ============================================================================== - ##### Peripheral State and Error functions ##### - ============================================================================== - [..] - This subsection provides functions allowing to : - (+) Return the UART handle state. - (+) Return the UART handle error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the UART handle state. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval HAL state - */ -HAL_UART_StateTypeDef HAL_UART_GetState(const UART_HandleTypeDef *huart) -{ - uint32_t temp1; - uint32_t temp2; - temp1 = huart->gState; - temp2 = huart->RxState; - - return (HAL_UART_StateTypeDef)(temp1 | temp2); -} - -/** - * @brief Return the UART handle error code. - * @param huart Pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART. - * @retval UART Error Code - */ -uint32_t HAL_UART_GetError(const UART_HandleTypeDef *huart) -{ - return huart->ErrorCode; -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup UART_Private_Functions UART Private Functions - * @{ - */ - -/** - * @brief Initialize the callbacks to their default values. - * @param huart UART handle. - * @retval none - */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -void UART_InitCallbacksToDefault(UART_HandleTypeDef *huart) -{ - /* Init the UART Callback settings */ - huart->TxHalfCpltCallback = HAL_UART_TxHalfCpltCallback; /* Legacy weak TxHalfCpltCallback */ - huart->TxCpltCallback = HAL_UART_TxCpltCallback; /* Legacy weak TxCpltCallback */ - huart->RxHalfCpltCallback = HAL_UART_RxHalfCpltCallback; /* Legacy weak RxHalfCpltCallback */ - huart->RxCpltCallback = HAL_UART_RxCpltCallback; /* Legacy weak RxCpltCallback */ - huart->ErrorCallback = HAL_UART_ErrorCallback; /* Legacy weak ErrorCallback */ - huart->AbortCpltCallback = HAL_UART_AbortCpltCallback; /* Legacy weak AbortCpltCallback */ - huart->AbortTransmitCpltCallback = HAL_UART_AbortTransmitCpltCallback; /* Legacy weak AbortTransmitCpltCallback */ - huart->AbortReceiveCpltCallback = HAL_UART_AbortReceiveCpltCallback; /* Legacy weak AbortReceiveCpltCallback */ - huart->RxFifoFullCallback = HAL_UARTEx_RxFifoFullCallback; /* Legacy weak RxFifoFullCallback */ - huart->TxFifoEmptyCallback = HAL_UARTEx_TxFifoEmptyCallback; /* Legacy weak TxFifoEmptyCallback */ - huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak RxEventCallback */ - -} -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - -/** - * @brief Configure the UART peripheral. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) -{ - uint32_t tmpreg; - uint16_t brrtemp; - uint32_t clocksource; - uint32_t usartdiv; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t lpuart_ker_ck_pres; - uint32_t pclk; - - /* Check the parameters */ - assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate)); - assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength)); - if (UART_INSTANCE_LOWPOWER(huart)) - { - assert_param(IS_LPUART_STOPBITS(huart->Init.StopBits)); - } - else - { - assert_param(IS_UART_STOPBITS(huart->Init.StopBits)); - assert_param(IS_UART_ONE_BIT_SAMPLE(huart->Init.OneBitSampling)); - } - - assert_param(IS_UART_PARITY(huart->Init.Parity)); - assert_param(IS_UART_MODE(huart->Init.Mode)); - assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl)); - assert_param(IS_UART_OVERSAMPLING(huart->Init.OverSampling)); - assert_param(IS_UART_PRESCALER(huart->Init.ClockPrescaler)); - - /*-------------------------- USART CR1 Configuration -----------------------*/ - /* Clear M, PCE, PS, TE, RE and OVER8 bits and configure - * the UART Word Length, Parity, Mode and oversampling: - * set the M bits according to huart->Init.WordLength value - * set PCE and PS bits according to huart->Init.Parity value - * set TE and RE bits according to huart->Init.Mode value - * set OVER8 bit according to huart->Init.OverSampling value */ - tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; - MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); - - /*-------------------------- USART CR2 Configuration -----------------------*/ - /* Configure the UART Stop Bits: Set STOP[13:12] bits according - * to huart->Init.StopBits value */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); - - /*-------------------------- USART CR3 Configuration -----------------------*/ - /* Configure - * - UART HardWare Flow Control: set CTSE and RTSE bits according - * to huart->Init.HwFlowCtl value - * - one-bit sampling method versus three samples' majority rule according - * to huart->Init.OneBitSampling (not applicable to LPUART) */ - tmpreg = (uint32_t)huart->Init.HwFlowCtl; - - if (!(UART_INSTANCE_LOWPOWER(huart))) - { - tmpreg |= huart->Init.OneBitSampling; - } - MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); - - /*-------------------------- USART PRESC Configuration -----------------------*/ - /* Configure - * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ - MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); - - /*-------------------------- USART BRR Configuration -----------------------*/ - UART_GETCLOCKSOURCE(huart, clocksource); - - /* Check LPUART instance */ - if (UART_INSTANCE_LOWPOWER(huart)) - { - /* Retrieve frequency clock */ - pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); - - /* If proper clock source reported */ - if (pclk != 0U) - { - /* Compute clock after Prescaler */ - lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); - - /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ - if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || - (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) - { - ret = HAL_ERROR; - } - else - { - /* Check computed UsartDiv value is in allocated range - (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ - usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) - { - huart->Instance->BRR = usartdiv; - } - else - { - ret = HAL_ERROR; - } - } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || - (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ - } /* if (pclk != 0) */ - } - /* Check UART Over Sampling to set Baud Rate Register */ - else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) - { - pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); - - /* USARTDIV must be greater than or equal to 0d16 */ - if (pclk != 0U) - { - usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - brrtemp = (uint16_t)(usartdiv & 0xFFF0U); - brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); - huart->Instance->BRR = brrtemp; - } - else - { - ret = HAL_ERROR; - } - } - } - else - { - pclk = HAL_RCCEx_GetPeriphCLKFreq(clocksource); - - if (pclk != 0U) - { - /* USARTDIV must be greater than or equal to 0d16 */ - usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); - if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) - { - huart->Instance->BRR = (uint16_t)usartdiv; - } - else - { - ret = HAL_ERROR; - } - } - } - - /* Initialize the number of data to process during RX/TX ISR execution */ - huart->NbTxDataToProcess = 1; - huart->NbRxDataToProcess = 1; - - /* Clear ISR function pointers */ - huart->RxISR = NULL; - huart->TxISR = NULL; - - return ret; -} - -/** - * @brief Configure the UART peripheral advanced features. - * @param huart UART handle. - * @retval None - */ -void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) -{ - /* Check whether the set of advanced features to configure is properly set */ - assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); - - /* if required, configure RX/TX pins swap */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) - { - assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); - } - - /* if required, configure TX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); - } - - /* if required, configure RX pin active level inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); - } - - /* if required, configure data inversion */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); - } - - /* if required, configure RX overrun detection disabling */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) - { - assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); - } - -#if defined(HAL_DMA_MODULE_ENABLED) - /* if required, configure DMA disabling on reception error */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) - { - assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); - MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); - } -#endif /* HAL_DMA_MODULE_ENABLED */ - - /* if required, configure auto Baud rate detection scheme */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) - { - assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); - /* set auto Baudrate detection parameters if detection is enabled */ - if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) - { - assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); - } - } - - /* if required, configure MSB first on communication line */ - if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) - { - assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); - MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); - } -} - -/** - * @brief Check the UART Idle State. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) -{ - uint32_t tickstart; - - /* Initialize the UART ErrorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Check if the Transmitter is enabled */ - if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) - { - /* Wait until TEACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Disable TXE interrupt for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE)); - - huart->gState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - - /* Check if the Receiver is enabled */ - if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) - { - /* Wait until REACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) - interrupts for the interrupt process */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - huart->RxState = HAL_UART_STATE_READY; - - __HAL_UNLOCK(huart); - - /* Timeout occurred */ - return HAL_TIMEOUT; - } - } - - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief This function handles UART Communication Timeout. It waits - * until a flag is no longer in the specified status. - * @param huart UART handle. - * @param Flag Specifies the UART flag to check - * @param Status The actual Flag status (SET or RESET) - * @param Tickstart Tick start value - * @param Timeout Timeout duration - * @retval HAL status - */ -HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, - uint32_t Tickstart, uint32_t Timeout) -{ - /* Wait until flag is set */ - while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) - { - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) - { - - return HAL_TIMEOUT; - } - - if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC)) - { - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET) - { - /* Clear Overrun Error flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); - - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts if ongoing */ - UART_EndRxTransfer(huart); - - huart->ErrorCode = HAL_UART_ERROR_ORE; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_ERROR; - } - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) - { - /* Clear Receiver Timeout flag*/ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); - - /* Blocking error : transfer is aborted - Set the UART state ready to be able to start again the process, - Disable Rx Interrupts if ongoing */ - UART_EndRxTransfer(huart); - - huart->ErrorCode = HAL_UART_ERROR_RTO; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_TIMEOUT; - } - } - } - } - return HAL_OK; -} - -/** - * @brief Start Receive operation in interrupt mode. - * @note This function could be called by all HAL UART API providing reception in Interrupt mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - huart->RxXferCount = Size; - huart->RxISR = NULL; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Configure Rx interrupt processing */ - if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT_FIFOEN; - } - else - { - huart->RxISR = UART_RxISR_8BIT_FIFOEN; - } - - /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - } - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - } - else - { - /* Set the Rx ISR function pointer according to the data word length */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - huart->RxISR = UART_RxISR_16BIT; - } - else - { - huart->RxISR = UART_RxISR_8BIT; - } - - /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); - } - else - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - return HAL_OK; -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Start Receive operation in DMA mode. - * @note This function could be called by all HAL UART API providing reception in DMA mode. - * @note When calling this function, parameters validity is considered as already checked, - * i.e. Rx State, buffer address, ... - * UART Handle is assumed as Locked. - * @param huart UART handle. - * @param pData Pointer to data buffer (u8 or u16 data elements). - * @param Size Amount of data elements (u8 or u16) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - uint16_t nbByte = Size; - - huart->pRxBuffPtr = pData; - huart->RxXferSize = Size; - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - - if (huart->hdmarx != NULL) - { - /* Set the UART DMA transfer complete callback */ - huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt; - - /* Set the UART DMA Half transfer complete callback */ - huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt; - - /* Set the DMA error callback */ - huart->hdmarx->XferErrorCallback = UART_DMAError; - - /* Set the DMA abort callback */ - huart->hdmarx->XferAbortCallback = NULL; - - /* In case of 9bits/No Parity transfer, pData buffer provided as input parameter - should be aligned on a u16 frontier, so nbByte should be equal to Size * 2 */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - nbByte = Size * 2U; - } - - /* Check linked list mode */ - if ((huart->hdmarx->Mode & DMA_LINKEDLIST) == DMA_LINKEDLIST) - { - if ((huart->hdmarx->LinkedListQueue != NULL) && (huart->hdmarx->LinkedListQueue->Head != NULL)) - { - /* Set DMA data size */ - huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CBR1_DEFAULT_OFFSET] = nbByte; - - /* Set DMA source address */ - huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CSAR_DEFAULT_OFFSET] = - (uint32_t)&huart->Instance->RDR; - - /* Set DMA destination address */ - huart->hdmarx->LinkedListQueue->Head->LinkRegisters[NODE_CDAR_DEFAULT_OFFSET] = (uint32_t)huart->pRxBuffPtr; - - /* Enable the UART receive DMA channel */ - status = HAL_DMAEx_List_Start_IT(huart->hdmarx); - } - else - { - /* Update status */ - status = HAL_ERROR; - } - } - else - { - /* Enable the UART receive DMA channel */ - status = HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->RDR, (uint32_t)huart->pRxBuffPtr, nbByte); - } - - if (status != HAL_OK) - { - /* Set error code to DMA */ - huart->ErrorCode = HAL_UART_ERROR_DMA; - - /* Restore huart->RxState to ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_ERROR; - } - } - - /* Enable the UART Parity Error Interrupt */ - if (huart->Init.Parity != UART_PARITY_NONE) - { - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); - } - - /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Enable the DMA transfer for the receiver request by setting the DMAR bit - in the UART CR3 register */ - ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAR); - - return HAL_OK; -} - - -/** - * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndTxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable TXEIE, TCIE, TXFT interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); - - /* At end of Tx process, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; -} -#endif /* HAL_DMA_MODULE_ENABLED */ - - -/** - * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart UART handle. - * @retval None - */ -static void UART_EndRxTransfer(UART_HandleTypeDef *huart) -{ - /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Reset RxIsr function pointer */ - huart->RxISR = NULL; -} - - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief DMA UART transmit process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* Check if DMA in circular mode */ - if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) - { - huart->TxXferCount = 0U; - -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the DMA transfer for transmit request by resetting the DMAT bit - in the UART CR3 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - /* DMA Circular mode */ - else - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART transmit process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx Half complete callback*/ - huart->TxHalfCpltCallback(huart); -#else - /*Call legacy weak Tx Half complete callback*/ - HAL_UART_TxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART receive process complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* Check if DMA in circular mode */ - if (hdma->Mode != DMA_LINKEDLIST_CIRCULAR) - { - huart->RxXferCount = 0U; - - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - -#if !defined(USART_DMAREQUESTS_SW_WA) - /* Disable the DMA transfer for the receiver request by resetting the DMAR bit - in the UART CR3 register */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); - -#endif /* !USART_DMAREQUESTS_SW_WA */ - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* If Reception till IDLE event has been selected, Disable IDLE Interrupt */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - } - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART receive process half complete callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - /* Initialize type of RxEvent that correspond to RxEvent callback execution; - In this case, Rx Event type is Half Transfer */ - huart->RxEventType = HAL_UART_RXEVENT_HT; - - /* Check current reception Mode : - If Reception till IDLE event has been selected : use Rx Event callback */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - else - { - /* In other cases : use Rx Half Complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Half complete callback*/ - huart->RxHalfCpltCallback(huart); -#else - /*Call legacy weak Rx Half complete callback*/ - HAL_UART_RxHalfCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } -} - -/** - * @brief DMA UART communication error callback. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - const HAL_UART_StateTypeDef gstate = huart->gState; - const HAL_UART_StateTypeDef rxstate = huart->RxState; - - /* Stop UART DMA Tx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && - (gstate == HAL_UART_STATE_BUSY_TX)) - { - huart->TxXferCount = 0U; - UART_EndTxTransfer(huart); - } - - /* Stop UART DMA Rx request if ongoing */ - if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && - (rxstate == HAL_UART_STATE_BUSY_RX)) - { - huart->RxXferCount = 0U; - UART_EndRxTransfer(huart); - } - - huart->ErrorCode |= HAL_UART_ERROR_DMA; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART communication abort callback, when initiated by HAL services on Error - * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user - * (To be called at end of DMA Tx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Rx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->hdmatx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmarx != NULL) - { - if (huart->hdmarx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user - * (To be called at end of DMA Rx Abort procedure following user abort request). - * @note When this callback is executed, User Abort complete call back is called only if no - * Abort still ongoing for Tx DMA Handle. - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->hdmarx->XferAbortCallback = NULL; - - /* Check if an Abort process is still ongoing */ - if (huart->hdmatx != NULL) - { - if (huart->hdmatx->XferAbortCallback != NULL) - { - return; - } - } - - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - - /* Reset errorCode */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->gState and huart->RxState to Ready */ - huart->gState = HAL_UART_STATE_READY; - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort complete callback */ - huart->AbortCpltCallback(huart); -#else - /* Call legacy weak Abort complete callback */ - HAL_UART_AbortCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - - -/** - * @brief DMA UART Tx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortTransmit_IT API (Abort only Tx transfer) - * (This callback is executed at end of DMA Tx Abort procedure following user abort request, - * and leads to user Tx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - - huart->TxXferCount = 0U; - - /* Flush the whole TX FIFO (if needed) */ - if (huart->FifoMode == UART_FIFOMODE_ENABLE) - { - __HAL_UART_SEND_REQ(huart, UART_TXDATA_FLUSH_REQUEST); - } - - /* Restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Transmit Complete Callback */ - huart->AbortTransmitCpltCallback(huart); -#else - /* Call legacy weak Abort Transmit Complete Callback */ - HAL_UART_AbortTransmitCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA UART Rx communication abort callback, when initiated by user by a call to - * HAL_UART_AbortReceive_IT API (Abort only Rx transfer) - * (This callback is executed at end of DMA Rx Abort procedure following user abort request, - * and leads to user Rx Abort Complete callback execution). - * @param hdma DMA handle. - * @retval None - */ -static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) -{ - UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - huart->RxXferCount = 0U; - - /* Clear the Error flags in the ICR register */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); - - /* Discard the received data */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - - /* Restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Call user Abort complete callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /* Call registered Abort Receive Complete Callback */ - huart->AbortReceiveCpltCallback(huart); -#else - /* Call legacy weak Abort Receive Complete Callback */ - HAL_UART_AbortReceiveCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief TX interrupt handler for 7 or 8 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT(UART_HandleTypeDef *huart) -{ - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); - huart->pTxBuffPtr++; - huart->TxXferCount--; - } - } -} - -/** - * @brief TX interrupt handler for 9 bits data word length. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT(UART_HandleTypeDef *huart) -{ - const uint16_t *tmp; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - if (huart->TxXferCount == 0U) - { - /* Disable the UART Transmit Data Register Empty Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TXEIE_TXFNFIE); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - } - else - { - tmp = (const uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - } -} - -/** - * @brief TX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t nb_tx_data; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) - { - if (huart->TxXferCount == 0U) - { - /* Disable the TX FIFO threshold interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - break; /* force exit loop */ - } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) - { - huart->Instance->TDR = (uint8_t)(*huart->pTxBuffPtr & (uint8_t)0xFF); - huart->pTxBuffPtr++; - huart->TxXferCount--; - } - else - { - /* Nothing to do */ - } - } - } -} - -/** - * @brief TX interrupt handler for 9 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Transmit_IT(). - * @param huart UART handle. - * @retval None - */ -static void UART_TxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - const uint16_t *tmp; - uint16_t nb_tx_data; - - /* Check that a Tx process is ongoing */ - if (huart->gState == HAL_UART_STATE_BUSY_TX) - { - for (nb_tx_data = huart->NbTxDataToProcess ; nb_tx_data > 0U ; nb_tx_data--) - { - if (huart->TxXferCount == 0U) - { - /* Disable the TX FIFO threshold interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_TXFTIE); - - /* Enable the UART Transmit Complete Interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - break; /* force exit loop */ - } - else if (READ_BIT(huart->Instance->ISR, USART_ISR_TXE_TXFNF) != 0U) - { - tmp = (const uint16_t *) huart->pTxBuffPtr; - huart->Instance->TDR = (((uint32_t)(*tmp)) & 0x01FFUL); - huart->pTxBuffPtr += 2U; - huart->TxXferCount--; - } - else - { - /* Nothing to do */ - } - } - } -} - -/** - * @brief Wrap up transmission in non-blocking mode. - * @param huart pointer to a UART_HandleTypeDef structure that contains - * the configuration information for the specified UART module. - * @retval None - */ -static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) -{ - /* Disable the UART Transmit Complete Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); - - /* Tx process is ended, restore huart->gState to Ready */ - huart->gState = HAL_UART_STATE_READY; - - /* Cleat TxISR function pointer */ - huart->TxISR = NULL; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Tx complete callback*/ - huart->TxCpltCallback(huart); -#else - /*Call legacy weak Tx complete callback*/ - HAL_UART_TxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ -} - -/** - * @brief RX interrupt handler for 7 or 8 bits data word length . - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - huart->pRxBuffPtr++; - huart->RxXferCount--; - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupts */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Initialize type of RxEvent to Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - { - /* Clear IDLE Flag */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrupt handler for 9 bits data word length . - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t *) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr += 2U; - huart->RxXferCount--; - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Initialize type of RxEvent to Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - { - /* Clear IDLE Flag */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrupt handler for 7 or 8 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - uint16_t nb_rx_data; - uint16_t rxdatacount; - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - nb_rx_data = huart->NbRxDataToProcess; - while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); - huart->pRxBuffPtr++; - huart->RxXferCount--; - isrflags = READ_REG(huart->Instance->ISR); - - /* If some non blocking errors occurred */ - if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) - { - /* UART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* Call UART Error Call back function if need be ----------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) - and RX FIFO Threshold interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Initialize type of RxEvent to Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - { - /* Clear IDLE Flag */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was - disabled (i.e. one interrupt per received frame). - */ - rxdatacount = huart->RxXferCount; - if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) - { - /* Disable the UART RXFT interrupt*/ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - - /* Update the RxISR function pointer */ - huart->RxISR = UART_RxISR_8BIT; - - /* Enable the UART Data Register Not Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @brief RX interrupt handler for 9 bits data word length and FIFO mode is enabled. - * @note Function is called under interruption only, once - * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart UART handle. - * @retval None - */ -static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) -{ - uint16_t *tmp; - uint16_t uhMask = huart->Mask; - uint16_t uhdata; - uint16_t nb_rx_data; - uint16_t rxdatacount; - uint32_t isrflags = READ_REG(huart->Instance->ISR); - uint32_t cr1its = READ_REG(huart->Instance->CR1); - uint32_t cr3its = READ_REG(huart->Instance->CR3); - - /* Check that a Rx process is ongoing */ - if (huart->RxState == HAL_UART_STATE_BUSY_RX) - { - nb_rx_data = huart->NbRxDataToProcess; - while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) - { - uhdata = (uint16_t) READ_REG(huart->Instance->RDR); - tmp = (uint16_t *) huart->pRxBuffPtr ; - *tmp = (uint16_t)(uhdata & uhMask); - huart->pRxBuffPtr += 2U; - huart->RxXferCount--; - isrflags = READ_REG(huart->Instance->ISR); - - /* If some non blocking errors occurred */ - if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) - { - /* UART parity error interrupt occurred -------------------------------------*/ - if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); - - huart->ErrorCode |= HAL_UART_ERROR_PE; - } - - /* UART frame error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); - - huart->ErrorCode |= HAL_UART_ERROR_FE; - } - - /* UART noise error interrupt occurred --------------------------------------*/ - if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); - - huart->ErrorCode |= HAL_UART_ERROR_NE; - } - - /* Call UART Error Call back function if need be ----------------------------*/ - if (huart->ErrorCode != HAL_UART_ERROR_NONE) - { - /* Non Blocking error : transfer could go on. - Error is notified to user through user error callback */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered error callback*/ - huart->ErrorCallback(huart); -#else - /*Call legacy weak error callback*/ - HAL_UART_ErrorCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - huart->ErrorCode = HAL_UART_ERROR_NONE; - } - } - - if (huart->RxXferCount == 0U) - { - /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); - - /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) - and RX FIFO Threshold interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); - - /* Rx process is completed, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - /* Clear RxISR function pointer */ - huart->RxISR = NULL; - - /* Initialize type of RxEvent to Transfer Complete */ - huart->RxEventType = HAL_UART_RXEVENT_TC; - - if (!(IS_LPUART_INSTANCE(huart->Instance))) - { - /* Check that USART RTOEN bit is set */ - if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) - { - /* Enable the UART Receiver Timeout Interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); - } - } - - /* Check current reception Mode : - If Reception till IDLE event has been selected : */ - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - /* Set reception type to Standard */ - huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; - - /* Disable IDLE interrupt */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) - { - /* Clear IDLE Flag */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - } - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); -#else - /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - else - { - /* Standard reception API called */ -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - /*Call registered Rx complete callback*/ - huart->RxCpltCallback(huart); -#else - /*Call legacy weak Rx complete callback*/ - HAL_UART_RxCpltCallback(huart); -#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ - } - } - } - - /* When remaining number of bytes to receive is less than the RX FIFO - threshold, next incoming frames are processed as if FIFO mode was - disabled (i.e. one interrupt per received frame). - */ - rxdatacount = huart->RxXferCount; - if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) - { - /* Disable the UART RXFT interrupt*/ - ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); - - /* Update the RxISR function pointer */ - huart->RxISR = UART_RxISR_16BIT; - - /* Enable the UART Data Register Not Empty interrupt */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); - } - } - else - { - /* Clear RXNE interrupt flag */ - __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); - } -} - -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c deleted file mode 100644 index 2d09a3ce3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_hal_uart_ex.c +++ /dev/null @@ -1,1145 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_uart_ex.c - * @author MCD Application Team - * @brief Extended UART HAL module driver. - * This file provides firmware functions to manage the following extended - * functionalities of the Universal Asynchronous Receiver Transmitter Peripheral (UART). - * + Initialization and de-initialization functions - * + Peripheral Control functions - * - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### UART peripheral extended features ##### - ============================================================================== - - (#) Declare a UART_HandleTypeDef handle structure. - - (#) For the UART RS485 Driver Enable mode, initialize the UART registers - by calling the HAL_RS485Ex_Init() API. - - (#) FIFO mode enabling/disabling and RX/TX FIFO threshold programming. - - -@- When UART operates in FIFO mode, FIFO mode must be enabled prior - starting RX/TX transfers. Also RX/TX FIFO thresholds must be - configured prior starting RX/TX transfers. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_HAL_Driver - * @{ - */ - -/** @defgroup UARTEx UARTEx - * @brief UART Extended HAL module driver - * @{ - */ - -#ifdef HAL_UART_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/** @defgroup UARTEX_Private_Constants UARTEx Private Constants - * @{ - */ -/* UART RX FIFO depth */ -#define RX_FIFO_DEPTH 8U - -/* UART TX FIFO depth */ -#define TX_FIFO_DEPTH 8U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UARTEx_Private_Functions UARTEx Private Functions - * @{ - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection); -static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup UARTEx_Exported_Functions UARTEx Exported Functions - * @{ - */ - -/** @defgroup UARTEx_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief Extended Initialization and Configuration Functions - * -@verbatim -=============================================================================== - ##### Initialization and Configuration functions ##### - =============================================================================== - [..] - This subsection provides a set of functions allowing to initialize the USARTx or the UARTy - in asynchronous mode. - (+) For the asynchronous mode the parameters below can be configured: - (++) Baud Rate - (++) Word Length - (++) Stop Bit - (++) Parity: If the parity is enabled, then the MSB bit of the data written - in the data register is transmitted but is changed by the parity bit. - (++) Hardware flow control - (++) Receiver/transmitter modes - (++) Over Sampling Method - (++) One-Bit Sampling Method - (+) For the asynchronous mode, the following advanced features can be configured as well: - (++) TX and/or RX pin level inversion - (++) data logical level inversion - (++) RX and TX pins swap - (++) RX overrun detection disabling - (++) DMA disabling on RX error - (++) MSB first on communication line - (++) auto Baud rate detection - [..] - The HAL_RS485Ex_Init() API follows the UART RS485 mode configuration - procedures (details for the procedures are available in reference manual). - -@endverbatim - - Depending on the frame length defined by the M1 and M0 bits (7-bit, - 8-bit or 9-bit), the possible UART formats are listed in the - following table. - - Table 1. UART frame format. - +-----------------------------------------------------------------------+ - | M1 bit | M0 bit | PCE bit | UART frame | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 0 | | SB | 8 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 0 | 1 | | SB | 7 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 0 | | SB | 9 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 0 | 1 | 1 | | SB | 8 bit data | PB | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 0 | | SB | 7 bit data | STB | | - |---------|---------|-----------|---------------------------------------| - | 1 | 0 | 1 | | SB | 6 bit data | PB | STB | | - +-----------------------------------------------------------------------+ - - * @{ - */ - -/** - * @brief Initialize the RS485 Driver enable feature according to the specified - * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart UART handle. - * @param Polarity Select the driver enable polarity. - * This parameter can be one of the following values: - * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high - * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime Driver Enable assertion time: - * 5-bit value defining the time between the activation of the DE (Driver Enable) - * signal and the beginning of the start bit. It is expressed in sample time - * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime Driver Enable deassertion time: - * 5-bit value defining the time between the end of the last stop bit, in a - * transmitted message, and the de-activation of the DE (Driver Enable) signal. - * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the - * oversampling rate). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, uint32_t AssertionTime, - uint32_t DeassertionTime) -{ - uint32_t temp; - - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - /* Check the Driver Enable UART instance */ - assert_param(IS_UART_DRIVER_ENABLE_INSTANCE(huart->Instance)); - - /* Check the Driver Enable polarity */ - assert_param(IS_UART_DE_POLARITY(Polarity)); - - /* Check the Driver Enable assertion time */ - assert_param(IS_UART_ASSERTIONTIME(AssertionTime)); - - /* Check the Driver Enable deassertion time */ - assert_param(IS_UART_DEASSERTIONTIME(DeassertionTime)); - - if (huart->gState == HAL_UART_STATE_RESET) - { - /* Allocate lock resource and initialize it */ - huart->Lock = HAL_UNLOCKED; - -#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) - UART_InitCallbacksToDefault(huart); - - if (huart->MspInitCallback == NULL) - { - huart->MspInitCallback = HAL_UART_MspInit; - } - - /* Init the low level hardware */ - huart->MspInitCallback(huart); -#else - /* Init the low level hardware : GPIO, CLOCK, CORTEX */ - HAL_UART_MspInit(huart); -#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ - } - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Perform advanced settings configuration */ - /* For some items, configuration requires to be done prior TE and RE bits are set */ - if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) - { - UART_AdvFeatureConfig(huart); - } - - /* Set the UART Communication parameters */ - if (UART_SetConfig(huart) == HAL_ERROR) - { - return HAL_ERROR; - } - - /* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */ - SET_BIT(huart->Instance->CR3, USART_CR3_DEM); - - /* Set the Driver Enable polarity */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_DEP, Polarity); - - /* Set the Driver Enable assertion and deassertion times */ - temp = (AssertionTime << UART_CR1_DEAT_ADDRESS_LSB_POS); - temp |= (DeassertionTime << UART_CR1_DEDT_ADDRESS_LSB_POS); - MODIFY_REG(huart->Instance->CR1, (USART_CR1_DEDT | USART_CR1_DEAT), temp); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group2 IO operation functions - * @brief Extended functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - This subsection provides a set of Wakeup and FIFO mode related callback functions. - - (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - -@endverbatim - * @{ - */ - -/** - * @brief UART RX Fifo full callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. - */ -} - -/** - * @brief UART TX Fifo empty callback. - * @param huart UART handle. - * @retval None - */ -__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(huart); - - /* NOTE : This function should not be modified, when the callback is needed, - the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup UARTEx_Exported_Functions_Group3 Peripheral Control functions - * @brief Extended Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides the following functions: - (+) HAL_MultiProcessorEx_AddressLength_Set() API optionally sets the UART node address - detection length to more than 4 bits for multiprocessor address mark wake up. - (+) HAL_UARTEx_StopModeWakeUpSourceConfig() API defines the wake-up from stop mode - trigger: address match, Start Bit detection or RXNE bit status. - (+) HAL_UARTEx_EnableStopMode() API enables the UART to wake up the MCU from stop mode - (+) HAL_UARTEx_DisableStopMode() API disables the above functionality - (+) HAL_UARTEx_EnableFifoMode() API enables the FIFO mode - (+) HAL_UARTEx_DisableFifoMode() API disables the FIFO mode - (+) HAL_UARTEx_SetTxFifoThreshold() API sets the TX FIFO threshold - (+) HAL_UARTEx_SetRxFifoThreshold() API sets the RX FIFO threshold - - [..] This subsection also provides a set of additional functions providing enhanced reception - services to user. (For example, these functions allow application to handle use cases - where number of data to be received is unknown). - - (#) Compared to standard reception services which only consider number of received - data elements as reception completion criteria, these functions also consider additional events - as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) - for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state - for a programmable time, after last received byte. - (+) Detection that a specific character has been received. - - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, - or till IDLE event occurs. Reception is handled only during function execution. - When function exits, no data reception could occur. HAL status and number of actually received data elements, - are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. - These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. - The HAL_UARTEx_RxEventCallback() user callback will be executed during Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. - - (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() - - (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() - - (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() - -@endverbatim - * @{ - */ - -/** - * @brief By default in multiprocessor mode, when the wake up method is set - * to address mark, the UART handles only 4-bit long addresses detection; - * this API allows to enable longer addresses detection (6-, 7- or 8-bit - * long). - * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, - * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart UART handle. - * @param AddressLength This parameter can be one of the following values: - * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address - * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address - * @retval HAL status - */ -HAL_StatusTypeDef HAL_MultiProcessorEx_AddressLength_Set(UART_HandleTypeDef *huart, uint32_t AddressLength) -{ - /* Check the UART handle allocation */ - if (huart == NULL) - { - return HAL_ERROR; - } - - /* Check the address length parameter */ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(AddressLength)); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - /* Set the address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, AddressLength); - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* TEACK and/or REACK to check before moving huart->gState to Ready */ - return (UART_CheckIdleState(huart)); -} - -/** - * @brief Set Wakeup from Stop mode interrupt flag selection. - * @note It is the application responsibility to enable the interrupt used as - * usart_wkup interrupt source before entering low-power mode. - * @param huart UART handle. - * @param WakeUpSelection Address match, Start Bit detection or RXNE/RXFNE bit status. - * This parameter can be one of the following values: - * @arg @ref UART_WAKEUP_ON_ADDRESS - * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - HAL_StatusTypeDef status = HAL_OK; - uint32_t tickstart; - - /* check the wake-up from stop mode UART instance */ - assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); - /* check the wake-up selection parameter */ - assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable the Peripheral */ - __HAL_UART_DISABLE(huart); - - - if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) - { - UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); - } - - /* Enable the Peripheral */ - __HAL_UART_ENABLE(huart); - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - /* Wait until REACK flag is set */ - if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) - { - status = HAL_TIMEOUT; - } - else - { - /* Initialize the UART State */ - huart->gState = HAL_UART_STATE_READY; - } - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return status; -} - -/** - * @brief Enable UART Stop Mode. - * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Set UESM bit */ - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable UART Stop Mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) -{ - /* Process Locked */ - __HAL_LOCK(huart); - - /* Clear UESM bit */ - ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Enable the FIFO mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Enable FIFO mode */ - SET_BIT(tmpcr1, USART_CR1_FIFOEN); - huart->FifoMode = UART_FIFOMODE_ENABLE; - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Disable the FIFO mode. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) -{ - uint32_t tmpcr1; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Enable FIFO mode */ - CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); - huart->FifoMode = UART_FIFOMODE_DISABLE; - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Set the TXFIFO threshold. - * @param huart UART handle. - * @param Threshold TX FIFO threshold value - * This parameter can be one of the following values: - * @arg @ref UART_TXFIFO_THRESHOLD_1_8 - * @arg @ref UART_TXFIFO_THRESHOLD_1_4 - * @arg @ref UART_TXFIFO_THRESHOLD_1_2 - * @arg @ref UART_TXFIFO_THRESHOLD_3_4 - * @arg @ref UART_TXFIFO_THRESHOLD_7_8 - * @arg @ref UART_TXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - uint32_t tmpcr1; - - /* Check parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Update TX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Set the RXFIFO threshold. - * @param huart UART handle. - * @param Threshold RX FIFO threshold value - * This parameter can be one of the following values: - * @arg @ref UART_RXFIFO_THRESHOLD_1_8 - * @arg @ref UART_RXFIFO_THRESHOLD_1_4 - * @arg @ref UART_RXFIFO_THRESHOLD_1_2 - * @arg @ref UART_RXFIFO_THRESHOLD_3_4 - * @arg @ref UART_RXFIFO_THRESHOLD_7_8 - * @arg @ref UART_RXFIFO_THRESHOLD_8_8 - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) -{ - uint32_t tmpcr1; - - /* Check the parameters */ - assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); - assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Save actual UART configuration */ - tmpcr1 = READ_REG(huart->Instance->CR1); - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Update RX threshold configuration */ - MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); - - /* Determine the number of data to process during RX/TX ISR execution */ - UARTEx_SetNbDataToProcess(huart); - - /* Restore UART configuration */ - WRITE_REG(huart->Instance->CR1, tmpcr1); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; -} - -/** - * @brief Receive an amount of data in blocking mode till either the expected number of data - * is received or an IDLE event occurs. - * @note HAL_OK is returned if reception is completed (expected number of data has been received) - * or if reception is stopped after IDLE event (less than the expected number of data has been received) - * In this case, RxLen output parameter indicates number of data available in reception buffer. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @note When FIFO mode is enabled, the RXFNE flag is set as long as the RXFIFO - * is not empty. Read operations from the RDR register are performed when - * RXFNE flag is set. From hardware perspective, RXFNE flag and - * RXNE are mapped on the same bit-field. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @param RxLen Number of data elements finally received - * (could be lower than Size, in case reception ends on IDLE event) - * @param Timeout Timeout duration expressed in ms (covers the whole reception sequence). - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, - uint32_t Timeout) -{ - uint8_t *pdata8bits; - uint16_t *pdata16bits; - uint16_t uhMask; - uint32_t tickstart; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - huart->ErrorCode = HAL_UART_ERROR_NONE; - huart->RxState = HAL_UART_STATE_BUSY_RX; - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - /* Init tickstart for timeout management */ - tickstart = HAL_GetTick(); - - huart->RxXferSize = Size; - huart->RxXferCount = Size; - - /* Computation of UART mask to apply to RDR register */ - UART_MASK_COMPUTATION(huart); - uhMask = huart->Mask; - - /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ - if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) - { - pdata8bits = NULL; - pdata16bits = (uint16_t *) pData; - } - else - { - pdata8bits = pData; - pdata16bits = NULL; - } - - /* Initialize output number of received elements */ - *RxLen = 0U; - - /* as long as data have to be received */ - while (huart->RxXferCount > 0U) - { - /* Check if IDLE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE)) - { - /* Clear IDLE flag in ISR */ - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - - /* If Set, but no data ever received, clear flag without exiting loop */ - /* If Set, and data has already been received, this means Idle Event is valid : End reception */ - if (*RxLen > 0U) - { - huart->RxEventType = HAL_UART_RXEVENT_IDLE; - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - } - - /* Check if RXNE flag is set */ - if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE)) - { - if (pdata8bits == NULL) - { - *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); - pdata16bits++; - } - else - { - *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); - pdata8bits++; - } - /* Increment number of received elements */ - *RxLen += 1U; - huart->RxXferCount--; - } - - /* Check for the Timeout */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) - { - huart->RxState = HAL_UART_STATE_READY; - - return HAL_TIMEOUT; - } - } - } - - /* Set number of received elements in output parameter : RxLen */ - *RxLen = huart->RxXferSize - huart->RxXferCount; - /* At end of Rx process, restore huart->RxState to Ready */ - huart->RxState = HAL_UART_STATE_READY; - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Receive an amount of data in interrupt mode till either the expected number of data - * is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to UART interrupts raised by RXNE and IDLE events. Callback is called at end of reception indicating - * number of received data elements. - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status = HAL_OK; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - (void)UART_Start_Receive_IT(huart, pData, Size); - - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - - return status; - } - else - { - return HAL_BUSY; - } -} - -#if defined(HAL_DMA_MODULE_ENABLED) -/** - * @brief Receive an amount of data in DMA mode till either the expected number - * of data is received or an IDLE event occurs. - * @note Reception is initiated by this function call. Further progress of reception is achieved thanks - * to DMA services, transferring automatically received data elements in user reception buffer and - * calling registered callbacks at half/end of reception. UART IDLE events are also used to consider - * reception phase as ended. In all cases, callback execution will indicate number of received data elements. - * @note When the UART parity is enabled (PCE = 1), the received data contain - * the parity bit (MSB position). - * @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01), - * the received data is handled as a set of uint16_t. In this case, Size must indicate the number - * of uint16_t available through pData. - * @param huart UART handle. - * @param pData Pointer to data buffer (uint8_t or uint16_t data elements). - * @param Size Amount of data elements (uint8_t or uint16_t) to be received. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) -{ - HAL_StatusTypeDef status; - - /* Check that a Rx process is not already ongoing */ - if (huart->RxState == HAL_UART_STATE_READY) - { - if ((pData == NULL) || (Size == 0U)) - { - return HAL_ERROR; - } - - /* Set Reception type to reception till IDLE Event*/ - huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE; - huart->RxEventType = HAL_UART_RXEVENT_TC; - - status = UART_Start_Receive_DMA(huart, pData, Size); - - /* Check Rx process has been successfully started */ - if (status == HAL_OK) - { - if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) - { - __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); - ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); - } - else - { - /* In case of errors already pending when reception is started, - Interrupts may have already been raised and lead to reception abortion. - (Overrun error for instance). - In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */ - status = HAL_ERROR; - } - } - - return status; - } - else - { - return HAL_BUSY; - } -} -#endif /* HAL_DMA_MODULE_ENABLED */ - -/** - * @brief Provide Rx Event type that has lead to RxEvent callback execution. - * @note When HAL_UARTEx_ReceiveToIdle_IT() or HAL_UARTEx_ReceiveToIdle_DMA() API are called, progress - * of reception process is provided to application through calls of Rx Event callback (either default one - * HAL_UARTEx_RxEventCallback() or user registered one). As several types of events could occur (IDLE event, - * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead - * to Rx Event callback execution. - * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; - * When DMA is configured in Normal Mode, HT event does not stop Reception process; - * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; - * @param huart UART handle. - * @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values) - */ -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart) -{ - /* Return Rx Event type value, as stored in UART handle */ - return (huart->RxEventType); -} - -/** - * @brief Set autonomous mode Configuration. - * @param huart UART handle. - * @param sConfig Autonomous mode structure parameters. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_SetConfigAutonomousMode(UART_HandleTypeDef *huart, - const UART_AutonomousModeConfTypeDef *sConfig) -{ - uint32_t tmpreg; - - if (huart->gState == HAL_UART_STATE_READY) - { - /* Check the parameters */ - assert_param(IS_UART_TRIGGER_POLARITY(sConfig->TriggerPolarity)); - assert_param(IS_UART_IDLE_FRAME_TRANSMIT(sConfig->IdleFrame)); - assert_param(IS_UART_TX_DATA_SIZE(sConfig->DataSize)); - if (IS_LPUART_INSTANCE(huart->Instance)) - { - assert_param(IS_LPUART_TRIGGER_SELECTION(sConfig->TriggerSelection)); - } - else - { - assert_param(IS_UART_TRIGGER_SELECTION(sConfig->TriggerSelection)); - } - - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Disable Transmitter */ - CLEAR_BIT(huart->Instance->CR1, USART_CR1_TE); - - /* Clear AUTOCR register */ - CLEAR_REG(huart->Instance->AUTOCR); - - /* UART AUTOCR Configuration */ - tmpreg = ((sConfig->DataSize << USART_AUTOCR_TDN_Pos) | (sConfig->TriggerPolarity) | \ - (sConfig->AutonomousModeState) | (sConfig->IdleFrame) | \ - (sConfig->TriggerSelection << USART_AUTOCR_TRIGSEL_Pos)); - - WRITE_REG(huart->Instance->AUTOCR, tmpreg); - - /* Enable UART */ - __HAL_UART_ENABLE(huart); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} - -/** - * @brief Get autonomous mode Configuration. - * @param huart UART handle. - * @param sConfig Autonomous mode structure parameters. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_GetConfigAutonomousMode(const UART_HandleTypeDef *huart, - UART_AutonomousModeConfTypeDef *sConfig) -{ - uint32_t tmpreg; - - /* Read AUTOCR register */ - tmpreg = READ_REG(huart->Instance->AUTOCR); - - /* Fill Autonomous structure parameter */ - sConfig->AutonomousModeState = (tmpreg & USART_AUTOCR_TRIGEN); - sConfig->TriggerSelection = ((tmpreg & USART_AUTOCR_TRIGSEL) >> USART_AUTOCR_TRIGSEL_Pos); - sConfig->TriggerPolarity = (tmpreg & USART_AUTOCR_TRIGPOL); - sConfig->IdleFrame = (tmpreg & USART_AUTOCR_IDLEDIS); - sConfig->DataSize = (tmpreg & USART_AUTOCR_TDN); - - return HAL_OK; -} - -/** - * @brief Clear autonomous mode Configuration. - * @param huart UART handle. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_UARTEx_ClearConfigAutonomousMode(UART_HandleTypeDef *huart) -{ - if (huart->gState == HAL_UART_STATE_READY) - { - /* Process Locked */ - __HAL_LOCK(huart); - - huart->gState = HAL_UART_STATE_BUSY; - - /* Disable UART */ - __HAL_UART_DISABLE(huart); - - /* Clear AUTOCR register */ - CLEAR_REG(huart->Instance->AUTOCR); - - /* Enable UART */ - __HAL_UART_ENABLE(huart); - - huart->gState = HAL_UART_STATE_READY; - - /* Process Unlocked */ - __HAL_UNLOCK(huart); - - return HAL_OK; - } - else - { - return HAL_BUSY; - } -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UARTEx_Private_Functions - * @{ - */ - -/** - * @brief Initialize the UART wake-up from stop mode parameters when triggered by address detection. - * @param huart UART handle. - * @param WakeUpSelection UART wake up from stop mode parameters. - * @retval None - */ -static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) -{ - assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); - - /* Set the USART address length */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); - - /* Set the USART address node */ - MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); -} - -/** - * @brief Calculate the number of data to process in RX/TX ISR. - * @note The RX FIFO depth and the TX FIFO depth is extracted from - * the UART configuration registers. - * @param huart UART handle. - * @retval None - */ -static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) -{ - uint8_t rx_fifo_depth; - uint8_t tx_fifo_depth; - uint8_t rx_fifo_threshold; - uint8_t tx_fifo_threshold; - static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; - static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; - - if (huart->FifoMode == UART_FIFOMODE_DISABLE) - { - huart->NbTxDataToProcess = 1U; - huart->NbRxDataToProcess = 1U; - } - else - { - rx_fifo_depth = RX_FIFO_DEPTH; - tx_fifo_depth = TX_FIFO_DEPTH; - rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); - tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); - huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / - (uint16_t)denominator[tx_fifo_threshold]; - huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / - (uint16_t)denominator[rx_fifo_threshold]; - } -} -/** - * @} - */ - -#endif /* HAL_UART_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c deleted file mode 100644 index 1459562d1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dlyb.c +++ /dev/null @@ -1,243 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_dlyb.c - * @author MCD Application Team - * @brief DelayBlock Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the DelayBlock peripheral: - * + input clock frequency - * + up to 12 oversampling phases - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### DelayBlock peripheral features ##### - ============================================================================== - [..] The DelayBlock is used to generate an Output clock which is de-phased from the Input - clock. The phase of the Output clock is programmed by FW. The Output clock is then used - to clock the receive data in i.e. a SDMMC, OSPI or QSPI interface. - The delay is Voltage and Temperature dependent, which may require FW to do re-tuning - and recenter the Output clock phase to the receive data. - - [..] The DelayBlock features include the following: - (+) Input clock frequency. - (+) Up to 12 oversampling phases. - - ##### How to use this driver ##### - ============================================================================== - [..] - This driver is a considered as a driver of service for external devices drivers - that interfaces with the DELAY peripheral. - The LL_DLYB_SetDelay() function, configure the Delay value configured on SEL and UNIT. - The LL_DLYB_GetDelay() function, return the Delay value configured on SEL and UNIT. - The LL_DLYB_GetClockPeriod()function, get the clock period. - - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -/** @defgroup DLYB_LL DLYB - * @brief DLYB LL module driver. - * @{ - */ - -#if defined(HAL_SD_MODULE_ENABLED) || defined(HAL_OSPI_MODULE_ENABLED) || defined(HAL_XSPI_MODULE_ENABLED) -#if defined (DLYB_SDMMC1) || defined (DLYB_SDMMC2) || defined (DLYB_OCTOSPI1) || defined (DLYB_OCTOSPI2) - -/** - @cond 0 - */ - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -#define DLYB_TIMEOUT 0xFFU -#define DLYB_LNG_10_0_MASK 0x07FF0000U -#define DLYB_LNG_11_10_MASK 0x0C000000U -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/** - @endcond - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DLYB_LL_Exported_Functions - * @brief Configuration and control functions - * -@verbatim - =============================================================================== - ##### Control functions ##### - =============================================================================== - [..] This section provides functions allowing to - (+) Control the DLYB. -@endverbatim - * @{ - */ - -/** @addtogroup DLYB_Control_Functions DLYB Control functions - * @{ - */ - -/** - * @brief Set the Delay value configured on SEL and UNIT. - * @param DLYBx: Pointer to DLYB instance. - * @param pdlyb_cfg: Pointer to DLYB configuration structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: the Delay value is set. - * - ERROR: the Delay value is not set. - */ -void LL_DLYB_SetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) -{ - /* Check the DelayBlock instance */ - assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); - - /* Enable the length sampling */ - SET_BIT(DLYBx->CR, DLYB_CR_SEN); - - /* Update the UNIT and SEL field */ - DLYBx->CFGR = (pdlyb_cfg->PhaseSel) | ((pdlyb_cfg->Units) << DLYB_CFGR_UNIT_Pos); - - /* Disable the length sampling */ - CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); -} - -/** - * @brief Get the Delay value configured on SEL and UNIT. - * @param DLYBx: Pointer to DLYB instance. - * @param pdlyb_cfg: Pointer to DLYB configuration structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: the Delay value is received. - * - ERROR: the Delay value is not received. - */ -void LL_DLYB_GetDelay(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) -{ - /* Check the DelayBlock instance */ - assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); - - /* Fill the DelayBlock configuration structure with SEL and UNIT value */ - pdlyb_cfg->Units = ((DLYBx->CFGR & DLYB_CFGR_UNIT) >> DLYB_CFGR_UNIT_Pos); - pdlyb_cfg->PhaseSel = (DLYBx->CFGR & DLYB_CFGR_SEL); -} - -/** - * @brief Get the clock period. - * @param DLYBx: Pointer to DLYB instance. - * @param pdlyb_cfg: Pointer to DLYB configuration structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: there is a valid period detected and stored in pdlyb_cfg. - * - ERROR: there is no valid period detected. - */ -uint32_t LL_DLYB_GetClockPeriod(DLYB_TypeDef *DLYBx, LL_DLYB_CfgTypeDef *pdlyb_cfg) -{ - uint32_t i = 0U; - uint32_t nb ; - uint32_t lng ; - uint32_t tickstart; - - /* Check the DelayBlock instance */ - assert_param(IS_DLYB_ALL_INSTANCE(DLYBx)); - - /* Enable the length sampling */ - SET_BIT(DLYBx->CR, DLYB_CR_SEN); - - /* Delay line length detection */ - while (i < DLYB_MAX_UNIT) - { - /* Set the Delay of the UNIT(s)*/ - DLYBx->CFGR = DLYB_MAX_SELECT | (i << DLYB_CFGR_UNIT_Pos); - - /* Waiting for a LNG valid value */ - tickstart = HAL_GetTick(); - while ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U) - { - if ((HAL_GetTick() - tickstart) >= DLYB_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if ((DLYBx->CFGR & DLYB_CFGR_LNGF) == 0U) - { - return (uint32_t) HAL_TIMEOUT; - } - } - } - - if ((DLYBx->CFGR & DLYB_LNG_10_0_MASK) != 0U) - { - if ((DLYBx->CFGR & (DLYB_CFGR_LNG_11 | DLYB_CFGR_LNG_10)) != DLYB_LNG_11_10_MASK) - { - /* Delay line length is configured to one input clock period*/ - break; - } - } - i++; - } - - if (DLYB_MAX_UNIT != i) - { - /* Determine how many unit delays (nb) span one input clock period */ - lng = (DLYBx->CFGR & DLYB_CFGR_LNG) >> 16U; - nb = 10U; - while ((nb > 0U) && ((lng >> nb) == 0U)) - { - nb--; - } - if (nb != 0U) - { - pdlyb_cfg->PhaseSel = nb ; - pdlyb_cfg->Units = i ; - - /* Disable the length sampling */ - CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); - - return (uint32_t)SUCCESS; - } - } - - /* Disable the length sampling */ - CLEAR_BIT(DLYBx->CR, DLYB_CR_SEN); - - return (uint32_t)ERROR; - -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* DLYB_SDMMC1 || DLYB_SDMMC2 || DLYB_OCTOSPI1 || DLYB_OCTOSPI2 */ -#endif /* HAL_SD_MODULE_ENABLED || HAL_OSPI_MODULE_ENABLED || HAL_XSPI_MODULE_ENABLED */ - -/** - * @} - */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c deleted file mode 100644 index 0c23c2cf1..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_dma.c +++ /dev/null @@ -1,1189 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_dma.c - * @author MCD Application Team - * @brief DMA LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### LL DMA driver acronyms ##### - ============================================================================== - [..] Acronyms table : - ========================================= - || Acronym || || - ========================================= - || SRC || Source || - || DEST || Destination || - || ADDR || Address || - || ADDRS || Addresses || - || INC || Increment / Incremented || - || DEC || Decrement / Decremented || - || BLK || Block || - || RPT || Repeat / Repeated || - || TRIG || Trigger || - ========================================= - @endverbatim - ****************************************************************************** - */ - -#if defined (USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_dma.h" -#include "stm32u5xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if (defined (GPDMA1) || defined (LPDMA1)) - -/** @addtogroup DMA_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup DMA_LL_Private_Macros - * @{ - */ -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, Channel) ((((INSTANCE) == GPDMA1) && \ - (((Channel) == LL_DMA_CHANNEL_0) || \ - ((Channel) == LL_DMA_CHANNEL_1) || \ - ((Channel) == LL_DMA_CHANNEL_2) || \ - ((Channel) == LL_DMA_CHANNEL_3) || \ - ((Channel) == LL_DMA_CHANNEL_4) || \ - ((Channel) == LL_DMA_CHANNEL_5) || \ - ((Channel) == LL_DMA_CHANNEL_6) || \ - ((Channel) == LL_DMA_CHANNEL_7) || \ - ((Channel) == LL_DMA_CHANNEL_8) || \ - ((Channel) == LL_DMA_CHANNEL_9) || \ - ((Channel) == LL_DMA_CHANNEL_10) || \ - ((Channel) == LL_DMA_CHANNEL_11) || \ - ((Channel) == LL_DMA_CHANNEL_12) || \ - ((Channel) == LL_DMA_CHANNEL_13) || \ - ((Channel) == LL_DMA_CHANNEL_14) || \ - ((Channel) == LL_DMA_CHANNEL_15) || \ - ((Channel) == LL_DMA_CHANNEL_ALL))) || \ - (((INSTANCE) == LPDMA1) && \ - (((Channel) == LL_DMA_CHANNEL_0) || \ - ((Channel) == LL_DMA_CHANNEL_1) || \ - ((Channel) == LL_DMA_CHANNEL_2) || \ - ((Channel) == LL_DMA_CHANNEL_3) || \ - ((Channel) == LL_DMA_CHANNEL_ALL)))) - -#define IS_LL_GPDMA_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \ - (((Channel) == LL_DMA_CHANNEL_0) || \ - ((Channel) == LL_DMA_CHANNEL_1) || \ - ((Channel) == LL_DMA_CHANNEL_2) || \ - ((Channel) == LL_DMA_CHANNEL_3) || \ - ((Channel) == LL_DMA_CHANNEL_4) || \ - ((Channel) == LL_DMA_CHANNEL_5) || \ - ((Channel) == LL_DMA_CHANNEL_6) || \ - ((Channel) == LL_DMA_CHANNEL_7) || \ - ((Channel) == LL_DMA_CHANNEL_8) || \ - ((Channel) == LL_DMA_CHANNEL_9) || \ - ((Channel) == LL_DMA_CHANNEL_10) || \ - ((Channel) == LL_DMA_CHANNEL_11) || \ - ((Channel) == LL_DMA_CHANNEL_12) || \ - ((Channel) == LL_DMA_CHANNEL_13) || \ - ((Channel) == LL_DMA_CHANNEL_14) || \ - ((Channel) == LL_DMA_CHANNEL_15))) - -#define IS_LL_DMA_2D_CHANNEL_INSTANCE(INSTANCE, Channel) (((INSTANCE) == GPDMA1) && \ - (((Channel) == LL_DMA_CHANNEL_12) || \ - ((Channel) == LL_DMA_CHANNEL_13) || \ - ((Channel) == LL_DMA_CHANNEL_14) || \ - ((Channel) == LL_DMA_CHANNEL_15))) - -#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY) || \ - ((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)) - -#define IS_LL_DMA_DATA_ALIGNMENT(__VALUE__) (((__VALUE__) == LL_DMA_DATA_ALIGN_ZEROPADD) || \ - ((__VALUE__) == LL_DMA_DATA_ALIGN_SIGNEXTPADD) || \ - ((__VALUE__) == LL_DMA_DATA_PACK_UNPACK)) - -#define IS_LL_DMA_BURST_LENGTH(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= 64U)) - -#define IS_LL_DMA_SRC_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_SRC_DATAWIDTH_BYTE) || \ - ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_HALFWORD) || \ - ((__VALUE__) == LL_DMA_SRC_DATAWIDTH_WORD)) - -#define IS_LL_DMA_DEST_DATA_WIDTH(__VALUE__) (((__VALUE__) == LL_DMA_DEST_DATAWIDTH_BYTE) || \ - ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_HALFWORD) || \ - ((__VALUE__) == LL_DMA_DEST_DATAWIDTH_WORD)) - -#define IS_LL_DMA_SRC_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_FIXED) || \ - ((__VALUE__) == LL_DMA_SRC_INCREMENT)) - -#define IS_LL_DMA_DEST_INCREMENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_FIXED) || \ - ((__VALUE__) == LL_DMA_DEST_INCREMENT)) - -#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_LOW_PRIORITY_LOW_WEIGHT) || \ - ((__VALUE__) == LL_DMA_LOW_PRIORITY_MID_WEIGHT) || \ - ((__VALUE__) == LL_DMA_LOW_PRIORITY_HIGH_WEIGHT) || \ - ((__VALUE__) == LL_DMA_HIGH_PRIORITY)) - -#define IS_LL_DMA_BLK_DATALENGTH(__VALUE__) ((__VALUE__) <= 0xFFFFU) - -#define IS_LL_DMA_BLK_REPEATCOUNT(__VALUE__) ((__VALUE__) <= 0x0EFFU) - -#define IS_LL_DMA_TRIGGER_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TRIGM_BLK_TRANSFER) || \ - ((__VALUE__) == LL_DMA_TRIGM_RPT_BLK_TRANSFER) || \ - ((__VALUE__) == LL_DMA_TRIGM_LLI_LINK_TRANSFER) || \ - ((__VALUE__) == LL_DMA_TRIGM_SINGLBURST_TRANSFER )) - -#define IS_LL_DMA_TRIGGER_POLARITY(__VALUE__) (((__VALUE__) == LL_DMA_TRIG_POLARITY_MASKED) || \ - ((__VALUE__) == LL_DMA_TRIG_POLARITY_RISING) || \ - ((__VALUE__) == LL_DMA_TRIG_POLARITY_FALLING)) - -#define IS_LL_DMA_BLKHW_REQUEST(__VALUE__) (((__VALUE__) == LL_DMA_HWREQUEST_SINGLEBURST) || \ - ((__VALUE__) == LL_DMA_HWREQUEST_BLK)) - -#if defined (LL_GPDMA1_TRIGGER_JPEG_OFT) -#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_JPEG_OFT) -#else -#define IS_LL_DMA_TRIGGER_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_TRIGGER_ADC1_AWD1) -#endif /* LL_GPDMA1_TRIGGER_JPEG_OFT */ - -#if defined (LL_GPDMA1_REQUEST_JPEG_TX) -#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_JPEG_TX) -#elif defined (LL_GPDMA1_REQUEST_ADC2) -#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_ADC2) -#else -#define IS_LL_DMA_REQUEST_SELECTION(__VALUE__) ((__VALUE__) <= LL_GPDMA1_REQUEST_LPTIM3_UE) -#endif /* LL_GPDMA1_REQUEST_JPEG_TX */ - -#define IS_LL_DMA_TRANSFER_EVENT_MODE(__VALUE__) (((__VALUE__) == LL_DMA_TCEM_BLK_TRANSFER) || \ - ((__VALUE__) == LL_DMA_TCEM_RPT_BLK_TRANSFER) || \ - ((__VALUE__) == LL_DMA_TCEM_EACH_LLITEM_TRANSFER) || \ - ((__VALUE__) == LL_DMA_TCEM_LAST_LLITEM_TRANSFER)) - -#define IS_LL_DMA_DEST_HALFWORD_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_HALFWORD_PRESERVE) || \ - ((__VALUE__) == LL_DMA_DEST_HALFWORD_EXCHANGE)) - -#define IS_LL_DMA_DEST_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_DEST_BYTE_PRESERVE) || \ - ((__VALUE__) == LL_DMA_DEST_BYTE_EXCHANGE)) - -#define IS_LL_DMA_SRC_BYTE_EXCHANGE(__VALUE__) (((__VALUE__) == LL_DMA_SRC_BYTE_PRESERVE) || \ - ((__VALUE__) == LL_DMA_SRC_BYTE_EXCHANGE)) - -#define IS_LL_DMA_LINK_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT0) || \ - ((__VALUE__) == LL_DMA_LINK_ALLOCATED_PORT1)) - -#define IS_LL_DMA_SRC_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT0) || \ - ((__VALUE__) == LL_DMA_SRC_ALLOCATED_PORT1)) - -#define IS_LL_DMA_DEST_ALLOCATED_PORT(__VALUE__) (((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT0) || \ - ((__VALUE__) == LL_DMA_DEST_ALLOCATED_PORT1)) - -#define IS_LL_DMA_LINK_STEP_MODE(__VALUE__) (((__VALUE__) == LL_DMA_LSM_FULL_EXECUTION) || \ - ((__VALUE__) == LL_DMA_LSM_1LINK_EXECUTION)) - -#define IS_LL_DMA_BURST_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_SRC_ADDR_INCREMENT) || \ - ((__VALUE__) == LL_DMA_BURST_SRC_ADDR_DECREMENT)) - -#define IS_LL_DMA_BURST_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BURST_DEST_ADDR_INCREMENT) || \ - ((__VALUE__) == LL_DMA_BURST_DEST_ADDR_DECREMENT)) - -#define IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0x1FFFU) - -#define IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_INCREMENT) || \ - ((__VALUE__) == LL_DMA_BLKRPT_SRC_ADDR_DECREMENT)) - -#define IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(__VALUE__) (((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_INCREMENT) || \ - ((__VALUE__) == LL_DMA_BLKRPT_DEST_ADDR_DECREMENT)) - -#define IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(__VALUE__) ((__VALUE__) <= 0xFFFFU) - -#define IS_LL_DMA_LINK_BASEADDR(__VALUE__) (((__VALUE__) & 0xFFFFU) == 0U) - -#define IS_LL_DMA_LINK_ADDR_OFFSET(__VALUE__) (((__VALUE__) & 0x03U) == 0U) - -#define IS_LL_DMA_LINK_UPDATE_REGISTERS(__VALUE__) ((((__VALUE__) & 0x01FE0000U) == 0U) && ((__VALUE__) != 0U)) - -#define IS_LL_DMA_LINK_NODETYPE(__VALUE__) (((__VALUE__) == LL_DMA_GPDMA_2D_NODE) || \ - ((__VALUE__) == LL_DMA_GPDMA_LINEAR_NODE) || \ - ((__VALUE__) == LL_DMA_LPDMA_LINEAR_NODE)) - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -#define IS_LL_DMA_CHANNEL_SRC_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_SRC_NSEC) || \ - ((__VALUE__) == LL_DMA_CHANNEL_SRC_SEC)) - -#define IS_LL_DMA_CHANNEL_DEST_SEC(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_DEST_NSEC) || \ - ((__VALUE__) == LL_DMA_CHANNEL_DEST_SEC)) - -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @addtogroup DMA_LL_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the DMA registers to their default reset values. - * @note This API is used for all available DMA channels. - * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use - * helper macros : - * @arg @ref LL_DMA_GET_INSTANCE - * @arg @ref LL_DMA_GET_CHANNEL - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval An ErrorStatus enumeration value: - * - SUCCESS : DMA registers are de-initialized. - * - ERROR : DMA registers are not de-initialized. - */ -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) -{ - DMA_Channel_TypeDef *tmp; - ErrorStatus status = SUCCESS; - - /* Check the DMA Instance DMAx and Channel parameters */ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - if (Channel == LL_DMA_CHANNEL_ALL) - { - if (DMAx == GPDMA1) - { - /* Force reset of DMA clock */ - LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_GPDMA1); - - /* Release reset of DMA clock */ - LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_GPDMA1); - } - else - { - /* Force reset of DMA clock */ - LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_LPDMA1); - - /* Release reset of DMA clock */ - LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_LPDMA1); - } - } - else - { - /* Get the DMA Channel Instance */ - tmp = (DMA_Channel_TypeDef *)(LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Suspend DMA channel */ - LL_DMA_SuspendChannel(DMAx, Channel); - - /* Disable the selected Channel */ - LL_DMA_ResetChannel(DMAx, Channel); - - /* Reset DMAx_Channely control register */ - LL_DMA_WriteReg(tmp, CLBAR, 0U); - - /* Reset DMAx_Channely control register */ - LL_DMA_WriteReg(tmp, CCR, 0U); - - /* Reset DMAx_Channely Configuration register */ - LL_DMA_WriteReg(tmp, CTR1, 0U); - - /* Reset DMAx_Channely transfer register 2 */ - LL_DMA_WriteReg(tmp, CTR2, 0U); - - /* Reset DMAx_Channely block number of data register */ - LL_DMA_WriteReg(tmp, CBR1, 0U); - - /* Reset DMAx_Channely source address register */ - LL_DMA_WriteReg(tmp, CSAR, 0U); - - /* Reset DMAx_Channely destination address register */ - LL_DMA_WriteReg(tmp, CDAR, 0U); - - /* Check DMA channel */ - if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - /* Reset DMAx_Channely transfer register 3 */ - LL_DMA_WriteReg(tmp, CTR3, 0U); - - /* Reset DMAx_Channely Block register 2 */ - LL_DMA_WriteReg(tmp, CBR2, 0U); - } - - /* Reset DMAx_Channely Linked list address register */ - LL_DMA_WriteReg(tmp, CLLR, 0U); - - /* Reset DMAx_Channely pending flags */ - LL_DMA_WriteReg(tmp, CFCR, 0x00003F00U); - - /* Reset DMAx_Channely attribute */ - LL_DMA_DisableChannelPrivilege(DMAx, Channel); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - LL_DMA_DisableChannelSecure(DMAx, Channel); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - } - - return (uint32_t)status; -} - -/** - * @brief Initialize the DMA registers according to the specified parameters - * in DMA_InitStruct. - * @note This API is used for all available DMA channels. - * @note A software request transfer can be done once programming the direction - * field in memory to memory value. - * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use - * helper macros : - * @arg @ref LL_DMA_GET_INSTANCE - * @arg @ref LL_DMA_GET_CHANNEL - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS : DMA registers are initialized. - * - ERROR : Not applicable. - */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Check the DMA Instance DMAx and Channel parameters*/ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Check the DMA parameters from DMA_InitStruct */ - assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); - - /* Check direction */ - if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) - { - assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitStruct->Request)); - } - - assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitStruct->DataAlignment)); - assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitStruct->SrcDataWidth)); - assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitStruct->DestDataWidth)); - assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitStruct->SrcIncMode)); - assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitStruct->DestIncMode)); - assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); - assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitStruct->BlkDataLength)); - assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitStruct->TriggerPolarity)); - assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitStruct->BlkHWRequest)); - assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitStruct->TransferEventMode)); - assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitStruct->LinkStepMode)); - assert_param(IS_LL_DMA_LINK_BASEADDR(DMA_InitStruct->LinkedListBaseAddr)); - assert_param(IS_LL_DMA_LINK_ADDR_OFFSET(DMA_InitStruct->LinkedListAddrOffset)); - - /* Check DMA instance */ - if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->SrcBurstLength)); - assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitStruct->DestBurstLength)); - assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitStruct->DestHWordExchange)); - assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitStruct->DestByteExchange)); - assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitStruct->SrcByteExchange)); - assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitStruct->LinkAllocatedPort)); - assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitStruct->SrcAllocatedPort)); - assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitStruct->DestAllocatedPort)); - } - - /* Check trigger polarity */ - if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) - { - assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitStruct->TriggerMode)); - assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitStruct->TriggerSelection)); - } - - /* Check DMA channel */ - if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitStruct->BlkRptCount)); - assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitStruct->SrcAddrUpdateMode)); - assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitStruct->DestAddrUpdateMode)); - assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->SrcAddrOffset)); - assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitStruct->DestAddrOffset)); - assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitStruct->BlkRptSrcAddrUpdateMode)); - assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitStruct->BlkRptDestAddrUpdateMode)); - assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptSrcAddrOffset)); - assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitStruct->BlkRptDestAddrOffset)); - } - - /*-------------------------- DMAx CLBAR Configuration ------------------------ - * Configure the Transfer linked list address with parameter : - * - LinkedListBaseAdd: DMA_CLBAR_LBA[31:16] bits - */ - LL_DMA_SetLinkedListBaseAddr(DMAx, Channel, DMA_InitStruct->LinkedListBaseAddr); - - /*-------------------------- DMAx CCR Configuration -------------------------- - * Configure the control parameter : - * - LinkAllocatedPort: DMA_CCR_LAP bit - * LinkAllocatedPort field is not supported by LPDMA channels. - * - LinkStepMode: DMA_CCR_LSM bit - * - Priority: DMA_CCR_PRIO [23:22] bits - */ - LL_DMA_ConfigControl(DMAx, Channel, DMA_InitStruct->Priority | \ - DMA_InitStruct->LinkAllocatedPort | \ - DMA_InitStruct->LinkStepMode); - - /*-------------------------- DMAx CTR1 Configuration ------------------------- - * Configure the Data transfer parameter : - * - DestAllocatedPort: DMA_CTR1_DAP bit - * DestAllocatedPort field is not supported by LPDMA channels. - * - DestHWordExchange: DMA_CTR1_DHX bit - * DestHWordExchange field is not supported by LPDMA channels. - * - DestByteExchange: DMA_CTR1_DBX bit - * DestByteExchange field is not supported by LPDMA channels. - * - DestIncMode: DMA_CTR1_DINC bit - * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits - * - SrcAllocatedPort: DMA_CTR1_SAP bit - * SrcAllocatedPort field is not supported by LPDMA channels. - * - SrcByteExchange: DMA_CTR1_SBX bit - * SrcByteExchange field is not supported by LPDMA channels. - * - DataAlignment: DMA_CTR1_PAM [12:11] bits - * DataAlignment field is reduced to one bit by LPDMA channels. - * - SrcIncMode: DMA_CTR1_SINC bit - * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits - * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits - * SrcBurstLength field is not supported by LPDMA channels. - * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits - * DestBurstLength field is not supported by LPDMA channels. - */ - LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->DestAllocatedPort | \ - DMA_InitStruct->DestHWordExchange | \ - DMA_InitStruct->DestByteExchange | \ - DMA_InitStruct->DestIncMode | \ - DMA_InitStruct->DestDataWidth | \ - DMA_InitStruct->SrcAllocatedPort | \ - DMA_InitStruct->SrcByteExchange | \ - DMA_InitStruct->DataAlignment | \ - DMA_InitStruct->SrcIncMode | \ - DMA_InitStruct->SrcDataWidth); - /* Check DMA instance */ - if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - LL_DMA_ConfigBurstLength(DMAx, Channel, DMA_InitStruct->SrcBurstLength, - DMA_InitStruct->DestBurstLength); - } - - /*-------------------------- DMAx CTR2 Configuration ------------------------- - * Configure the channel transfer parameter : - * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits - * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits - * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits - * - BlkHWRequest: DMA_CTR2_BREQ bit - * - Direction: DMA_CTR2_DREQ bit - * - Direction: DMA_CTR2_SWREQ bit - * Direction field is reduced to one bit for LPDMA channels (SWREQ). - * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits - * TriggerSelection field is reduced to 5 bits for LPDMA channels. - * - Request: DMA_CTR2_REQSEL [6:0] bits - * Request field is reduced to 5 bits for LPDMA channels. - */ - LL_DMA_ConfigChannelTransfer(DMAx, Channel, DMA_InitStruct->TransferEventMode | \ - DMA_InitStruct->TriggerPolarity | \ - DMA_InitStruct->BlkHWRequest | \ - DMA_InitStruct->Direction); - - /* Check direction */ - if (DMA_InitStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) - { - LL_DMA_SetPeriphRequest(DMAx, Channel, DMA_InitStruct->Request); - } - - /* Check trigger polarity */ - if (DMA_InitStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) - { - LL_DMA_SetHWTrigger(DMAx, Channel, DMA_InitStruct->TriggerSelection); - LL_DMA_SetTriggerMode(DMAx, Channel, DMA_InitStruct->TriggerMode); - } - - /*-------------------------- DMAx CBR1 Configuration ------------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits - * - BlkRptCount: DMA_CBR1_BRC[26:16] bits - * BlkRptCount field is supported only by 2D addressing channels. - * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit - * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels. - * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit - * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels. - * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit - * SrcAddrUpdateMode field is supported only by 2D addressing channels. - * - DestAddrUpdateMode: DMA_CBR1_DDEC bit - * DestAddrUpdateMode field is supported only by 2D addressing channels. - */ - LL_DMA_SetBlkDataLength(DMAx, Channel, DMA_InitStruct->BlkDataLength); - - /* Check DMA channel */ - if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - LL_DMA_SetBlkRptCount(DMAx, Channel, DMA_InitStruct->BlkRptCount); - LL_DMA_ConfigBlkRptAddrUpdate(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrUpdateMode | \ - DMA_InitStruct->BlkRptDestAddrUpdateMode | \ - DMA_InitStruct->SrcAddrUpdateMode | \ - DMA_InitStruct->DestAddrUpdateMode); - } - - /*-------------------------- DMAx CSAR and CDAR Configuration ---------------- - * Configure the Transfer source address with parameter : - * - SrcAddress: DMA_CSAR_SA[31:0] bits - * - DestAddress: DMA_CDAR_DA[31:0] bits - */ - LL_DMA_ConfigAddresses(DMAx, Channel, DMA_InitStruct->SrcAddress, DMA_InitStruct->DestAddress); - - /* Check DMA channel */ - if (IS_LL_DMA_2D_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - /*------------------------ DMAx CTR3 Configuration ------------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - SrcAddrOffset: DMA_CTR3_SAO[28:16] bits - * SrcAddrOffset field is supported only by 2D addressing channels. - * - DestAddrOffset: DMA_CTR3_DAO[12:0] bits - * DestAddrOffset field is supported only by 2D addressing channels. - */ - LL_DMA_ConfigAddrUpdateValue(DMAx, Channel, DMA_InitStruct->SrcAddrOffset, DMA_InitStruct->DestAddrOffset); - - /*------------------------ DMAx CBR2 Configuration ----------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits - * BlkRptSrcAddrOffset field is supported only by 2D addressing channels. - * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits - * BlkRptDestAddrOffset field is supported only by 2D addressing channels. - */ - LL_DMA_ConfigBlkRptAddrUpdateValue(DMAx, Channel, DMA_InitStruct->BlkRptSrcAddrOffset, - DMA_InitStruct->BlkRptDestAddrOffset); - } - - /*-------------------------- DMAx CLLR Configuration ------------------------- - * Configure the Transfer linked list address with parameter : - * - DestAddrOffset: DMA_CLLR_LA[15:2] bits - */ - LL_DMA_SetLinkedListAddrOffset(DMAx, Channel, DMA_InitStruct->LinkedListAddrOffset); - - return (uint32_t)SUCCESS; -} - -/** - * @brief Set each @ref LL_DMA_InitTypeDef field to default value. - * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval None. - */ -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->SrcAddress = 0x00000000U; - DMA_InitStruct->DestAddress = 0x00000000U; - DMA_InitStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; - DMA_InitStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; - DMA_InitStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; - DMA_InitStruct->SrcBurstLength = 1U; - DMA_InitStruct->DestBurstLength = 1U; - DMA_InitStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; - DMA_InitStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; - DMA_InitStruct->SrcIncMode = LL_DMA_SRC_FIXED; - DMA_InitStruct->DestIncMode = LL_DMA_DEST_FIXED; - DMA_InitStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; - DMA_InitStruct->BlkDataLength = 0x00000000U; - DMA_InitStruct->BlkRptCount = 0x00000000U; - DMA_InitStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; - DMA_InitStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; - DMA_InitStruct->TriggerSelection = 0x00000000U; - DMA_InitStruct->Request = 0x00000000U; - DMA_InitStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; - DMA_InitStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; - DMA_InitStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; - DMA_InitStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; - DMA_InitStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; - DMA_InitStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; - DMA_InitStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; - DMA_InitStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; - DMA_InitStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT; - DMA_InitStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT; - DMA_InitStruct->SrcAddrOffset = 0x00000000U; - DMA_InitStruct->DestAddrOffset = 0x00000000U; - DMA_InitStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT; - DMA_InitStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT; - DMA_InitStruct->BlkRptSrcAddrOffset = 0x00000000U; - DMA_InitStruct->BlkRptDestAddrOffset = 0x00000000U; - DMA_InitStruct->LinkedListBaseAddr = 0x00000000U; - DMA_InitStruct->LinkedListAddrOffset = 0x00000000U; -} - -/** - * @brief Set each @ref LL_DMA_InitLinkedListTypeDef field to default value. - * @param DMA_InitLinkedListStruct Pointer to - * a @ref LL_DMA_InitLinkedListTypeDef structure. - * @retval None. - */ -void LL_DMA_ListStructInit(LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct) -{ - /* Set LL_DMA_InitLinkedListTypeDef fields to default values */ - DMA_InitLinkedListStruct->Priority = LL_DMA_LOW_PRIORITY_LOW_WEIGHT; - DMA_InitLinkedListStruct->LinkStepMode = LL_DMA_LSM_FULL_EXECUTION; - DMA_InitLinkedListStruct->TransferEventMode = LL_DMA_TCEM_LAST_LLITEM_TRANSFER; - DMA_InitLinkedListStruct->LinkAllocatedPort = LL_DMA_LINK_ALLOCATED_PORT0; -} - -/** - * @brief De-initialize the DMA linked list. - * @note This API is used for all available DMA channels. - * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use - * helper macros : - * @arg @ref LL_DMA_GET_INSTANCE - * @arg @ref LL_DMA_GET_CHANNEL - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @retval An ErrorStatus enumeration value: - * - SUCCESS : DMA registers are de-initialized. - * - ERROR : DMA registers are not de-initialized. - */ -uint32_t LL_DMA_List_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return LL_DMA_DeInit(DMAx, Channel); -} - -/** - * @brief Initialize the DMA linked list according to the specified parameters - * in LL_DMA_InitLinkedListTypeDef. - * @note This API is used for all available DMA channels. - * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use - * helper macros : - * @arg @ref LL_DMA_GET_INSTANCE - * @arg @ref LL_DMA_GET_CHANNEL - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_0 - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @arg @ref LL_DMA_CHANNEL_4 - * @arg @ref LL_DMA_CHANNEL_5 - * @arg @ref LL_DMA_CHANNEL_6 - * @arg @ref LL_DMA_CHANNEL_7 - * @arg @ref LL_DMA_CHANNEL_8 - * @arg @ref LL_DMA_CHANNEL_9 - * @arg @ref LL_DMA_CHANNEL_10 - * @arg @ref LL_DMA_CHANNEL_11 - * @arg @ref LL_DMA_CHANNEL_12 - * @arg @ref LL_DMA_CHANNEL_13 - * @arg @ref LL_DMA_CHANNEL_14 - * @arg @ref LL_DMA_CHANNEL_15 - * @param DMA_InitLinkedListStruct pointer to - * a @ref LL_DMA_InitLinkedListTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS : DMA registers are initialized. - * - ERROR : Not applicable. - */ -uint32_t LL_DMA_List_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitLinkedListTypeDef *DMA_InitLinkedListStruct) -{ - /* Check the DMA Instance DMAx and Channel parameters*/ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Check the DMA parameters from DMA_InitLinkedListStruct */ - assert_param(IS_LL_DMA_PRIORITY(DMA_InitLinkedListStruct->Priority)); - assert_param(IS_LL_DMA_LINK_STEP_MODE(DMA_InitLinkedListStruct->LinkStepMode)); - assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitLinkedListStruct->TransferEventMode)); - /* Check DMA instance */ - if (IS_LL_GPDMA_CHANNEL_INSTANCE(DMAx, Channel) != 0U) - { - assert_param(IS_LL_DMA_LINK_ALLOCATED_PORT(DMA_InitLinkedListStruct->LinkAllocatedPort)); - } - - /*-------------------------- DMAx CCR Configuration -------------------------- - * Configure the control parameter : - * - LinkAllocatedPort: DMA_CCR_LAP bit - * LinkAllocatedPort field is supported only by GPDMA channels. - * - LinkStepMode: DMA_CCR_LSM bit - * - Priority: DMA_CCR_PRIO [23:22] bits - */ - LL_DMA_ConfigControl(DMAx, Channel, DMA_InitLinkedListStruct->Priority | \ - DMA_InitLinkedListStruct->LinkAllocatedPort | \ - DMA_InitLinkedListStruct->LinkStepMode); - - /*-------------------------- DMAx CTR2 Configuration ------------------------- - * Configure the channel transfer parameter : - * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits - */ - LL_DMA_SetTransferEventMode(DMAx, Channel, DMA_InitLinkedListStruct->TransferEventMode); - - return (uint32_t)SUCCESS; -} - -/** - * @brief Set each @ref LL_DMA_InitNodeTypeDef field to default value. - * @param DMA_InitNodeStruct Pointer to a @ref LL_DMA_InitNodeTypeDef - * structure. - * @retval None. - */ -void LL_DMA_NodeStructInit(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct) -{ - /* Set DMA_InitNodeStruct fields to default values */ -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - DMA_InitNodeStruct->DestSecure = LL_DMA_CHANNEL_DEST_NSEC; -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - DMA_InitNodeStruct->DestAllocatedPort = LL_DMA_DEST_ALLOCATED_PORT0; - DMA_InitNodeStruct->DestHWordExchange = LL_DMA_DEST_HALFWORD_PRESERVE; - DMA_InitNodeStruct->DestByteExchange = LL_DMA_DEST_BYTE_PRESERVE; - DMA_InitNodeStruct->DestBurstLength = 1U; - DMA_InitNodeStruct->DestIncMode = LL_DMA_DEST_FIXED; - DMA_InitNodeStruct->DestDataWidth = LL_DMA_DEST_DATAWIDTH_BYTE; -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - DMA_InitNodeStruct->SrcSecure = LL_DMA_CHANNEL_SRC_NSEC; -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - DMA_InitNodeStruct->SrcAllocatedPort = LL_DMA_SRC_ALLOCATED_PORT0; - DMA_InitNodeStruct->SrcByteExchange = LL_DMA_SRC_BYTE_PRESERVE; - DMA_InitNodeStruct->DataAlignment = LL_DMA_DATA_ALIGN_ZEROPADD; - DMA_InitNodeStruct->SrcBurstLength = 1U; - DMA_InitNodeStruct->SrcIncMode = LL_DMA_SRC_FIXED; - DMA_InitNodeStruct->SrcDataWidth = LL_DMA_SRC_DATAWIDTH_BYTE; - DMA_InitNodeStruct->TransferEventMode = LL_DMA_TCEM_BLK_TRANSFER; - DMA_InitNodeStruct->TriggerPolarity = LL_DMA_TRIG_POLARITY_MASKED; - DMA_InitNodeStruct->TriggerSelection = 0x00000000U; - DMA_InitNodeStruct->TriggerMode = LL_DMA_TRIGM_BLK_TRANSFER; - DMA_InitNodeStruct->BlkHWRequest = LL_DMA_HWREQUEST_SINGLEBURST; - DMA_InitNodeStruct->Direction = LL_DMA_DIRECTION_MEMORY_TO_MEMORY; - DMA_InitNodeStruct->Request = 0x00000000U; - DMA_InitNodeStruct->BlkRptDestAddrUpdateMode = LL_DMA_BLKRPT_DEST_ADDR_INCREMENT; - DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode = LL_DMA_BLKRPT_SRC_ADDR_INCREMENT; - DMA_InitNodeStruct->DestAddrUpdateMode = LL_DMA_BURST_DEST_ADDR_INCREMENT; - DMA_InitNodeStruct->SrcAddrUpdateMode = LL_DMA_BURST_SRC_ADDR_INCREMENT; - DMA_InitNodeStruct->BlkRptCount = 0x00000000U; - DMA_InitNodeStruct->BlkDataLength = 0x00000000U; - DMA_InitNodeStruct->SrcAddress = 0x00000000U; - DMA_InitNodeStruct->DestAddress = 0x00000000U; - DMA_InitNodeStruct->DestAddrOffset = 0x00000000U; - DMA_InitNodeStruct->SrcAddrOffset = 0x00000000U; - DMA_InitNodeStruct->BlkRptDestAddrOffset = 0x00000000U; - DMA_InitNodeStruct->BlkRptSrcAddrOffset = 0x00000000U; - DMA_InitNodeStruct->UpdateRegisters = (LL_DMA_UPDATE_CTR1 | LL_DMA_UPDATE_CTR2 | \ - LL_DMA_UPDATE_CBR1 | LL_DMA_UPDATE_CSAR | \ - LL_DMA_UPDATE_CDAR | LL_DMA_UPDATE_CTR3 | \ - LL_DMA_UPDATE_CBR2 | LL_DMA_UPDATE_CLLR); - DMA_InitNodeStruct->NodeType = LL_DMA_GPDMA_LINEAR_NODE; -} - -/** - * @brief Initializes DMA linked list node according to the specified - * parameters in the DMA_InitNodeStruct. - * @param DMA_InitNodeStruct Pointer to a LL_DMA_InitNodeTypeDef structure - * that contains linked list node - * registers configurations. - * @param pNode Pointer to linked list node to fill according to - * LL_DMA_LinkNodeTypeDef parameters. - * @retval None - */ -uint32_t LL_DMA_CreateLinkNode(LL_DMA_InitNodeTypeDef *DMA_InitNodeStruct, LL_DMA_LinkNodeTypeDef *pNode) -{ - uint32_t reg_counter = 0U; - - /* Check the DMA Node type */ - assert_param(IS_LL_DMA_LINK_NODETYPE(DMA_InitNodeStruct->NodeType)); - - /* Check the DMA parameters from DMA_InitNodeStruct */ - assert_param(IS_LL_DMA_DIRECTION(DMA_InitNodeStruct->Direction)); - - /* Check direction */ - if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) - { - assert_param(IS_LL_DMA_REQUEST_SELECTION(DMA_InitNodeStruct->Request)); - } - - assert_param(IS_LL_DMA_DATA_ALIGNMENT(DMA_InitNodeStruct->DataAlignment)); - assert_param(IS_LL_DMA_SRC_DATA_WIDTH(DMA_InitNodeStruct->SrcDataWidth)); - assert_param(IS_LL_DMA_DEST_DATA_WIDTH(DMA_InitNodeStruct->DestDataWidth)); - assert_param(IS_LL_DMA_SRC_INCREMENT_MODE(DMA_InitNodeStruct->SrcIncMode)); - assert_param(IS_LL_DMA_DEST_INCREMENT_MODE(DMA_InitNodeStruct->DestIncMode)); - assert_param(IS_LL_DMA_BLK_DATALENGTH(DMA_InitNodeStruct->BlkDataLength)); - assert_param(IS_LL_DMA_TRIGGER_POLARITY(DMA_InitNodeStruct->TriggerPolarity)); - assert_param(IS_LL_DMA_BLKHW_REQUEST(DMA_InitNodeStruct->BlkHWRequest)); - assert_param(IS_LL_DMA_TRANSFER_EVENT_MODE(DMA_InitNodeStruct->TransferEventMode)); - assert_param(IS_LL_DMA_LINK_UPDATE_REGISTERS(DMA_InitNodeStruct->UpdateRegisters)); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - assert_param(IS_LL_DMA_CHANNEL_SRC_SEC(DMA_InitNodeStruct->SrcSecure)); - assert_param(IS_LL_DMA_CHANNEL_DEST_SEC(DMA_InitNodeStruct->DestSecure)); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Check trigger polarity */ - if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) - { - assert_param(IS_LL_DMA_TRIGGER_MODE(DMA_InitNodeStruct->TriggerMode)); - assert_param(IS_LL_DMA_TRIGGER_SELECTION(DMA_InitNodeStruct->TriggerSelection)); - } - - /* Check node type */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_LINEAR_NODE) - { - assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->SrcBurstLength)); - assert_param(IS_LL_DMA_BURST_LENGTH(DMA_InitNodeStruct->DestBurstLength)); - assert_param(IS_LL_DMA_DEST_HALFWORD_EXCHANGE(DMA_InitNodeStruct->DestHWordExchange)); - assert_param(IS_LL_DMA_DEST_BYTE_EXCHANGE(DMA_InitNodeStruct->DestByteExchange)); - assert_param(IS_LL_DMA_SRC_BYTE_EXCHANGE(DMA_InitNodeStruct->SrcByteExchange)); - assert_param(IS_LL_DMA_SRC_ALLOCATED_PORT(DMA_InitNodeStruct->SrcAllocatedPort)); - assert_param(IS_LL_DMA_DEST_ALLOCATED_PORT(DMA_InitNodeStruct->DestAllocatedPort)); - } - - /* Check DMA channel */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE) - { - assert_param(IS_LL_DMA_BLK_REPEATCOUNT(DMA_InitNodeStruct->BlkRptCount)); - assert_param(IS_LL_DMA_BURST_SRC_ADDR_UPDATE(DMA_InitNodeStruct->SrcAddrUpdateMode)); - assert_param(IS_LL_DMA_BURST_DEST_ADDR_UPDATE(DMA_InitNodeStruct->DestAddrUpdateMode)); - assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->SrcAddrOffset)); - assert_param(IS_LL_DMA_BURST_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->DestAddrOffset)); - assert_param(IS_LL_DMA_BLKRPT_SRC_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode)); - assert_param(IS_LL_DMA_BLKRPT_DEST_ADDR_UPDATE(DMA_InitNodeStruct->BlkRptDestAddrUpdateMode)); - assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptSrcAddrOffset)); - assert_param(IS_LL_DMA_BLKRPT_ADDR_UPDATE_VALUE(DMA_InitNodeStruct->BlkRptDestAddrOffset)); - } - - /* Check if CTR1 register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR1) == LL_DMA_UPDATE_CTR1) - { - /*-------------------------- DMAx CTR1 Configuration ----------------------- - * Configure the Data transfer parameter : - * - DestAllocatedPort: DMA_CTR1_DAP bit - * DestAllocatedPort field is not supported by LPDMA channels. - * - DestHWordExchange: DMA_CTR1_DHX bit - * DestHWordExchange field is not supported by LPDMA channels. - * - DestByteExchange: DMA_CTR1_DBX bit - * DestByteExchange field is not supported by LPDMA channels. - * - DestIncMode: DMA_CTR1_DINC bit - * - DestDataWidth: DMA_CTR1_DDW_LOG2 [17:16] bits - * - SrcAllocatedPort: DMA_CTR1_SAP bit - * SrcAllocatedPort field is not supported by LPDMA channels. - * - SrcByteExchange: DMA_CTR1_SBX bit - * SrcByteExchange field is not supported by LPDMA channels. - * - DataAlignment: DMA_CTR1_PAM [12:11] bits - * DataAlignment field is reduced to one bit for LPDMA channels. - * - SrcIncMode: DMA_CTR1_SINC bit - * - SrcDataWidth: DMA_CTR1_SDW_LOG2 [1:0] bits - * - SrcBurstLength: DMA_CTR1_SBL_1 [9:4] bits - * SrcBurstLength field is not supported by LPDMA channels. - * - DestBurstLength: DMA_CTR1_DBL_1 [25:20] bits - * DestBurstLength field is not supported by LPDMA channels. - */ - - pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->DestIncMode | \ - DMA_InitNodeStruct->DestDataWidth | \ - DMA_InitNodeStruct->DataAlignment | \ - DMA_InitNodeStruct->SrcIncMode | \ - DMA_InitNodeStruct->SrcDataWidth); - -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestSecure | \ - DMA_InitNodeStruct->SrcSecure); -#endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ - - /* Update CTR1 register fields for not LPDMA channels */ - if (DMA_InitNodeStruct->NodeType != LL_DMA_LPDMA_LINEAR_NODE) - { - pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->DestAllocatedPort | \ - DMA_InitNodeStruct->DestHWordExchange | \ - DMA_InitNodeStruct->DestByteExchange | \ - ((DMA_InitNodeStruct->DestBurstLength - 1U) << DMA_CTR1_DBL_1_Pos) | \ - DMA_InitNodeStruct->SrcAllocatedPort | \ - DMA_InitNodeStruct->SrcByteExchange | \ - ((DMA_InitNodeStruct->SrcBurstLength - 1U) << DMA_CTR1_SBL_1_Pos)); - } - - /* Increment counter for the next register */ - reg_counter++; - } - - - /* Check if CTR2 register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR2) == LL_DMA_UPDATE_CTR2) - { - /*-------------------------- DMAx CTR2 Configuration ----------------------- - * Configure the channel transfer parameter : - * - TransferEventMode: DMA_CTR2_TCEM [31:30] bits - * - TriggerPolarity: DMA_CTR2_TRIGPOL [25:24] bits - * - TriggerMode: DMA_CTR2_TRIGM [15:14] bits - * - BlkHWRequest: DMA_CTR2_BREQ bit - * - Direction: DMA_CTR2_DREQ bit - * - Direction: DMA_CTR2_SWREQ bit - * Direction field is reduced to one bit for LPDMA channels (SWREQ). - * - TriggerSelection: DMA_CTR2_TRIGSEL [21:16] bits - * DataAlignment field is reduced to 5 bits for LPDMA channels. - * - Request: DMA_CTR2_REQSEL [6:0] bits - * DataAlignment field is reduced to 5 bits for LPDMA channels. - */ - pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->TransferEventMode | \ - DMA_InitNodeStruct->TriggerPolarity | \ - DMA_InitNodeStruct->BlkHWRequest | \ - DMA_InitNodeStruct->Direction); - - /* Check direction */ - if (DMA_InitNodeStruct->Direction != LL_DMA_DIRECTION_MEMORY_TO_MEMORY) - { - pNode->LinkRegisters[reg_counter] |= DMA_InitNodeStruct->Request & DMA_CTR2_REQSEL; - } - - /* Check trigger polarity */ - if (DMA_InitNodeStruct->TriggerPolarity != LL_DMA_TRIG_POLARITY_MASKED) - { - pNode->LinkRegisters[reg_counter] |= (((DMA_InitNodeStruct->TriggerSelection << DMA_CTR2_TRIGSEL_Pos) & \ - DMA_CTR2_TRIGSEL) | DMA_InitNodeStruct->TriggerMode); - } - - /* Update CTR2 register fields for LPDMA */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_LPDMA_LINEAR_NODE) - { - pNode->LinkRegisters[reg_counter] &= (~(1UL << 21U) & ~(3UL << 5U)); - } - - /* Increment counter for the next register */ - reg_counter++; - } - - /* Check if CBR1 register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR1) == LL_DMA_UPDATE_CBR1) - { - /*-------------------------- DMAx CBR1 Configuration ----------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - BlkDataLength: DMA_CBR1_BNDT[15:0] bits - * - BlkRptCount: DMA_CBR1_BRC[26:16] bits - * BlkRptCount field is supported only by 2D addressing channels. - * - BlkRptSrcAddrUpdateMode: DMA_CBR1_BRSDEC bit - * BlkRptSrcAddrUpdateMode field is supported only by 2D addressing channels. - * - BlkRptDestAddrUpdateMode: DMA_CBR1_BRDDEC bit - * BlkRptDestAddrUpdateMode field is supported only by 2D addressing channels. - * - SrcAddrUpdateMode: DMA_CBR1_SDEC bit - * SrcAddrUpdateMode field is supported only by 2D addressing channels. - * - DestAddrUpdateMode: DMA_CBR1_DDEC bit - * DestAddrUpdateMode field is supported only by 2D addressing channels. - */ - pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->BlkDataLength; - - /* Update CBR1 register fields for 2D addressing channels */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE) - { - pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->BlkRptDestAddrUpdateMode | \ - DMA_InitNodeStruct->BlkRptSrcAddrUpdateMode | \ - DMA_InitNodeStruct->DestAddrUpdateMode | \ - DMA_InitNodeStruct->SrcAddrUpdateMode | \ - ((DMA_InitNodeStruct->BlkRptCount << DMA_CBR1_BRC_Pos) & DMA_CBR1_BRC)); - } - - /* Increment counter for the next register */ - reg_counter++; - } - - /* Check if CSAR register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CSAR) == LL_DMA_UPDATE_CSAR) - { - /*-------------------------- DMAx CSAR Configuration ----------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - SrcAddress: DMA_CSAR_SA[31:0] bits - */ - pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->SrcAddress; - - /* Increment counter for the next register */ - reg_counter++; - } - - - /* Check if CDAR register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CDAR) == LL_DMA_UPDATE_CDAR) - { - /*-------------------------- DMAx CDAR Configuration ----------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - DestAddress: DMA_CDAR_DA[31:0] bits - */ - pNode->LinkRegisters[reg_counter] = DMA_InitNodeStruct->DestAddress; - - /* Increment counter for the next register */ - reg_counter++; - } - - - /* Update CTR3 register fields for 2D addressing channels */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE) - { - /* Check if CTR3 register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CTR3) == LL_DMA_UPDATE_CTR3) - { - /*-------------------------- DMAx CTR3 Configuration --------------------- - * Configure the Block counters and update mode with parameter : - * - DestAddressOffset: DMA_CTR3_DAO[12:0] bits - * DestAddressOffset field is supported only by 2D addressing channels. - * - SrcAddressOffset: DMA_CTR3_SAO[12:0] bits - * SrcAddressOffset field is supported only by 2D addressing channels. - */ - pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->SrcAddrOffset | \ - ((DMA_InitNodeStruct->DestAddrOffset << DMA_CTR3_DAO_Pos) & DMA_CTR3_DAO)); - - /* Increment counter for the next register */ - reg_counter++; - } - } - - - /* Update CBR2 register fields for 2D addressing channels */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE) - { - /* Check if CBR2 register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CBR2) == LL_DMA_UPDATE_CBR2) - { - /*-------------------------- DMAx CBR2 Configuration --------------------- - * Configure the Block counters and update mode with parameter : - * - BlkRptDestAddrOffset: DMA_CBR2_BRDAO[31:16] bits - * BlkRptDestAddrOffset field is supported only by 2D addressing channels. - * - BlkRptSrcAddrOffset: DMA_CBR2_BRSAO[15:0] bits - * BlkRptSrcAddrOffset field is supported only by 2D addressing channels. - */ - pNode->LinkRegisters[reg_counter] = (DMA_InitNodeStruct->BlkRptSrcAddrOffset | \ - ((DMA_InitNodeStruct->BlkRptDestAddrOffset << DMA_CBR2_BRDAO_Pos) & \ - DMA_CBR2_BRDAO)); - - /* Increment counter for the next register */ - reg_counter++; - } - } - - /* Check if CLLR register update is enabled */ - if ((DMA_InitNodeStruct->UpdateRegisters & LL_DMA_UPDATE_CLLR) == LL_DMA_UPDATE_CLLR) - { - /*-------------------------- DMAx CLLR Configuration ----------------------- - * Configure the Transfer Block counters and update mode with parameter : - * - UpdateRegisters DMA_CLLR_UT1 bit - * - UpdateRegisters DMA_CLLR_UT2 bit - * - UpdateRegisters DMA_CLLR_UB1 bit - * - UpdateRegisters DMA_CLLR_USA bit - * - UpdateRegisters DMA_CLLR_UDA bit - * - UpdateRegisters DMA_CLLR_UT3 bit - * DMA_CLLR_UT3 bit is discarded for linear addressing channels. - * - UpdateRegisters DMA_CLLR_UB2 bit - * DMA_CLLR_UB2 bit is discarded for linear addressing channels. - * - UpdateRegisters DMA_CLLR_ULL bit - */ - pNode->LinkRegisters[reg_counter] = ((DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT1 | DMA_CLLR_UT2 | \ - DMA_CLLR_UB1 | DMA_CLLR_USA | \ - DMA_CLLR_UDA | DMA_CLLR_ULL))); - - /* Update CLLR register fields for 2D addressing channels */ - if (DMA_InitNodeStruct->NodeType == LL_DMA_GPDMA_2D_NODE) - { - pNode->LinkRegisters[reg_counter] |= (DMA_InitNodeStruct->UpdateRegisters & (DMA_CLLR_UT3 | DMA_CLLR_UB2)); - } - } - - return (uint32_t)SUCCESS; -} - -/** - * @brief Connect Linked list Nodes. - * @param pPrevLinkNode Pointer to previous linked list node to be connected to new Linked list node. - * @param PrevNodeCLLRIdx Offset of Previous Node CLLR register. - * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET. - * @param pNewLinkNode Pointer to new Linked list. - * @param NewNodeCLLRIdx Offset of New Node CLLR register. - * This parameter can be a value of @ref DMA_LL_EC_CLLR_OFFSET. - * @retval None - */ -void LL_DMA_ConnectLinkNode(LL_DMA_LinkNodeTypeDef *pPrevLinkNode, uint32_t PrevNodeCLLRIdx, - LL_DMA_LinkNodeTypeDef *pNewLinkNode, uint32_t NewNodeCLLRIdx) -{ - pPrevLinkNode->LinkRegisters[PrevNodeCLLRIdx] = (((uint32_t)pNewLinkNode & DMA_CLLR_LA) | \ - (pNewLinkNode->LinkRegisters[NewNodeCLLRIdx] & (DMA_CLLR_UT1 | \ - DMA_CLLR_UT2 | DMA_CLLR_UB1 | DMA_CLLR_USA | DMA_CLLR_UDA | \ - DMA_CLLR_UT3 | DMA_CLLR_UB2 | DMA_CLLR_ULL))); -} - -/** - * @brief Disconnect the next linked list node. - * @param pLinkNode Pointer to linked list node to be disconnected from the next one. - * @param LinkNodeCLLRIdx Offset of Link Node CLLR register. - * @retval None. - */ -void LL_DMA_DisconnectNextLinkNode(LL_DMA_LinkNodeTypeDef *pLinkNode, uint32_t LinkNodeCLLRIdx) -{ - pLinkNode->LinkRegisters[LinkNodeCLLRIdx] = 0; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* GPDMA1 || LPDMA1 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c deleted file mode 100644 index 07067fe31..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_exti.c +++ /dev/null @@ -1,217 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_exti.c - * @author MCD Application Team - * @brief EXTI LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_exti.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Private_Macros - * @{ - */ - -#define IS_LL_EXTI_LINE_0_31(__VALUE__) (((__VALUE__) & ~LL_EXTI_LINE_ALL_0_31) == 0x00000000U) - -#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ - || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ - || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) - - -#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the EXTI registers to their default reset values. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_EXTI_DeInit(void) -{ - /* Interrupt mask register set to default reset values */ - LL_EXTI_WriteReg(IMR1, 0x00000000U); - /* Event mask register set to default reset values */ - LL_EXTI_WriteReg(EMR1, 0x00000000U); - /* Rising Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(RTSR1, 0x00000000U); - /* Falling Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(FTSR1, 0x00000000U); - /* Software interrupt event register set to default reset values */ - LL_EXTI_WriteReg(SWIER1, 0x00000000U); - /* Pending register set to default reset values */ - LL_EXTI_WriteReg(RPR1, 0xFFFFFFFFU); - LL_EXTI_WriteReg(FPR1, 0xFFFFFFFFU); - /* Privilege register set to default reset values */ - LL_EXTI_WriteReg(PRIVCFGR1, 0x00000000U); -#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) - /* Secure register set to default reset values */ - LL_EXTI_WriteReg(SECCFGR1, 0x00000000U); -#endif /* __ARM_FEATURE_CMSE */ - return SUCCESS; -} - -/** - * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. - * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: EXTI registers are initialized - * - ERROR: not applicable - */ -ErrorStatus LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - ErrorStatus status = SUCCESS; - /* Check the parameters */ - assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); - assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); - - /* ENABLE LineCommand */ - if (EXTI_InitStruct->LineCommand != DISABLE) - { - assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); - - /* Configure EXTI Lines in range from 0 to 31 */ - if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) - { - switch (EXTI_InitStruct->Mode) - { - case LL_EXTI_MODE_IT: - /* First Disable Event on provided Lines */ - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable IT on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_EVENT: - /* First Disable IT on provided Lines */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Event on provided Lines */ - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_MODE_IT_EVENT: - /* Directly Enable IT & Event on provided Lines */ - LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) - { - switch (EXTI_InitStruct->Trigger) - { - case LL_EXTI_TRIGGER_RISING: - /* First Disable Falling Trigger on provided Lines */ - LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Rising Trigger on provided Lines */ - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_FALLING: - /* First Disable Rising Trigger on provided Lines */ - LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - /* Then Enable Falling Trigger on provided Lines */ - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - case LL_EXTI_TRIGGER_RISING_FALLING: - LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); - break; - default: - status = ERROR; - break; - } - } - } - } - /* DISABLE LineCommand */ - else - { - /* De-configure EXTI Lines in range from 0 to 31 */ - LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); - LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); - } - return status; -} - -/** - * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. - * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval None - */ -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->Line_0_31 = LL_EXTI_LINE_NONE; - EXTI_InitStruct->LineCommand = DISABLE; - EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; - EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (EXTI) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_gpio.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_gpio.c deleted file mode 100644 index 11d9c1917..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_gpio.c +++ /dev/null @@ -1,295 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_gpio.c - * @author MCD Application Team - * @brief GPIO LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_gpio.h" -#include "stm32u5xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || defined (GPIOF) || \ - defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) - -/** @addtogroup GPIO_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Private_Macros - * @{ - */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) - -#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ - ((__VALUE__) == LL_GPIO_MODE_ANALOG)) - -#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ - ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) - -#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ - ((__VALUE__) == LL_GPIO_PULL_UP) ||\ - ((__VALUE__) == LL_GPIO_PULL_DOWN)) - -#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ - ((__VALUE__) == LL_GPIO_AF_1 ) ||\ - ((__VALUE__) == LL_GPIO_AF_2 ) ||\ - ((__VALUE__) == LL_GPIO_AF_3 ) ||\ - ((__VALUE__) == LL_GPIO_AF_4 ) ||\ - ((__VALUE__) == LL_GPIO_AF_5 ) ||\ - ((__VALUE__) == LL_GPIO_AF_6 ) ||\ - ((__VALUE__) == LL_GPIO_AF_7 ) ||\ - ((__VALUE__) == LL_GPIO_AF_8 ) ||\ - ((__VALUE__) == LL_GPIO_AF_9 ) ||\ - ((__VALUE__) == LL_GPIO_AF_10 ) ||\ - ((__VALUE__) == LL_GPIO_AF_11 ) ||\ - ((__VALUE__) == LL_GPIO_AF_12 ) ||\ - ((__VALUE__) == LL_GPIO_AF_13 ) ||\ - ((__VALUE__) == LL_GPIO_AF_14 ) ||\ - ((__VALUE__) == LL_GPIO_AF_15 )) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize GPIO registers (Registers restored to their default values). - * @param GPIOx GPIO Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: Wrong GPIO Port - */ -ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Force and Release reset on clock of GPIOx Port */ - if (GPIOx == GPIOA) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOA); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOA); - } - else if (GPIOx == GPIOB) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOB); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOB); - } - else if (GPIOx == GPIOC) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOC); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOC); - } -#if defined(GPIOD) - else if (GPIOx == GPIOD) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOD); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOD); - } -#endif /* GPIOD */ -#if defined(GPIOE) - else if (GPIOx == GPIOE) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOE); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOE); - } -#endif /* GPIOE */ -#if defined(GPIOF) - else if (GPIOx == GPIOF) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOF); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOF); - } -#endif /* GPIOF */ -#if defined(GPIOG) - else if (GPIOx == GPIOG) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOG); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOG); - } -#endif /* GPIOG */ -#if defined(GPIOH) - else if (GPIOx == GPIOH) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOH); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOH); - } -#endif /* GPIOH */ -#if defined(GPIOI) - else if (GPIOx == GPIOI) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOI); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOI); - } -#endif /* GPIOI */ -#if defined(GPIOJ) - else if (GPIOx == GPIOJ) - { - LL_AHB2_GRP1_ForceReset(LL_AHB2_GRP1_PERIPH_GPIOJ); - LL_AHB2_GRP1_ReleaseReset(LL_AHB2_GRP1_PERIPH_GPIOJ); - } -#endif /* GPIOJ */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. - * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure - * that contains the configuration information for the specified GPIO peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t pinpos; - uint32_t currentpin; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); - assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); - assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); - - /* ------------------------- Configure the port pins ---------------- */ - /* Initialize pinpos on first pin set */ - pinpos = POSITION_VAL(GPIO_InitStruct->Pin); - - /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0U) - { - /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (1UL << pinpos); - - if (currentpin != 0U) - { - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Speed mode parameters */ - assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); - - /* Speed mode configuration */ - LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); - - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - } - - /* Pull-up Pull down resistor configuration*/ - LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); - - if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) - { - /* Check Alternate parameter */ - assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); - - /* Speed mode configuration */ - if (POSITION_VAL(currentpin) < 8U) - { - LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - else - { - LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - } - - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - } - pinpos++; - } - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; - GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct->Alternate = LL_GPIO_AF_0; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOC) || defined (GPIOD) || defined (GPIOE) || \ - defined (GPIOF) || defined (GPIOG) || defined (GPIOH) || defined (GPIOI) || defined (GPIOJ) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpgpio.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpgpio.c deleted file mode 100644 index 5b72a71cb..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_lpgpio.c +++ /dev/null @@ -1,165 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_lpgpio.c - * @author MCD Application Team - * @brief LPGPIO LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_lpgpio.h" -#include "stm32u5xx_ll_bus.h" -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -#if defined (LPGPIO1) - -/** @addtogroup LPGPIO_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup LPGPIO_LL_Private_Macros - * @{ - */ -#define IS_LL_LPGPIO_PIN(__VALUE__) (((0x00000000U) < (__VALUE__)) && ((__VALUE__) <= (LL_LPGPIO_PIN_ALL))) - -#define IS_LL_LPGPIO_MODE(__VALUE__) (((__VALUE__) == LL_LPGPIO_MODE_INPUT) ||\ - ((__VALUE__) == LL_LPGPIO_MODE_OUTPUT)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup LPGPIO_LL_Exported_Functions - * @{ - */ - -/** @addtogroup LPGPIO_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize LPGPIO registers (Registers restored to their default values). - * @param LPGPIOx LPGPIO Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: LPGPIO registers are de-initialized - * - ERROR: Wrong LPGPIO Port - */ -ErrorStatus LL_LPGPIO_DeInit(const GPIO_TypeDef *LPGPIOx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_LPGPIO_ALL_INSTANCE(LPGPIOx)); - - /* Force and Release reset on clock of LPGPIOx Port */ - if (LPGPIOx == LPGPIO1) - { - LL_AHB3_GRP1_ForceReset(LL_AHB3_GRP1_PERIPH_LPGPIO1); - LL_AHB3_GRP1_ReleaseReset(LL_AHB3_GRP1_PERIPH_LPGPIO1); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize LPGPIO registers according to the specified parameters in LPGPIO_InitStruct. - * @param LPGPIOx LPGPIO Port - * @param LPGPIO_InitStruct: pointer to a @ref LL_LPGPIO_InitTypeDef structure - * that contains the configuration information for the specified LPGPIO peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: LPGPIO registers are initialized according to LPGPIO_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_LPGPIO_Init(GPIO_TypeDef *LPGPIOx, const LL_LPGPIO_InitTypeDef *const LPGPIO_InitStruct) -{ - uint32_t pinpos; - uint32_t currentpin; - - /* Check the parameters */ - assert_param(IS_LPGPIO_ALL_INSTANCE(LPGPIOx)); - assert_param(IS_LL_LPGPIO_PIN(LPGPIO_InitStruct->Pin)); - assert_param(IS_LL_LPGPIO_MODE(LPGPIO_InitStruct->Mode)); - - /* ------------------------- Configure the port pins ---------------- */ - /* Initialize pinpos on first pin set */ - pinpos = POSITION_VAL(LPGPIO_InitStruct->Pin); - - /* Configure the port pins */ - while (((LPGPIO_InitStruct->Pin) >> pinpos) != 0U) - { - /* Get current io position */ - currentpin = (LPGPIO_InitStruct->Pin) & (1UL << pinpos); - - if (currentpin != 0U) - { - /* Pin Mode configuration */ - LL_LPGPIO_SetPinMode(LPGPIOx, currentpin, LPGPIO_InitStruct->Mode); - } - pinpos++; - } - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_LPGPIO_InitTypeDef field to default value. - * @param LPGPIO_InitStruct: pointer to a @ref LL_LPGPIO_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_LPGPIO_StructInit(LL_LPGPIO_InitTypeDef *LPGPIO_InitStruct) -{ - /* Reset LPGPIO init structure parameters values */ - LPGPIO_InitStruct->Pin = LL_LPGPIO_PIN_ALL; - LPGPIO_InitStruct->Mode = LL_LPGPIO_MODE_INPUT; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (LPGPIO1) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c deleted file mode 100644 index 9c537026a..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_ucpd.c +++ /dev/null @@ -1,169 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_ucpd.c - * @author MCD Application Team - * @brief UCPD LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_ucpd.h" -#include "stm32u5xx_ll_bus.h" -#include "stm32u5xx_ll_rcc.h" - -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ -#if defined (UCPD1) -/** @addtogroup UCPD_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup UCPD_LL_Private_Constants UCPD Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup UCPD_LL_Private_Macros UCPD Private Macros - * @{ - */ - - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UCPD_LL_Exported_Functions - * @{ - */ - -/** @addtogroup UCPD_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the UCPD registers to their default reset values. - * @param UCPDx ucpd Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ucpd registers are de-initialized - * - ERROR: ucpd registers are not de-initialized - */ -ErrorStatus LL_UCPD_DeInit(UCPD_TypeDef *UCPDx) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); - - LL_UCPD_Disable(UCPDx); - - if (UCPD1 == UCPDx) - { - /* Force reset of ucpd clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_UCPD1); - - /* Release reset of ucpd clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_UCPD1); - - /* Disable ucpd clock */ - LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_UCPD1); - - status = SUCCESS; - } - - return status; -} - -/** - * @brief Initialize the ucpd registers according to the specified parameters in UCPD_InitStruct. - * @note As some bits in ucpd configuration registers can only be written when the ucpd is disabled - * (ucpd_CR1_SPE bit =0), UCPD peripheral should be in disabled state prior calling this function. - * Otherwise, ERROR result will be returned. - * @param UCPDx UCPD Instance - * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure that contains - * the configuration information for the UCPD peripheral. - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -ErrorStatus LL_UCPD_Init(UCPD_TypeDef *UCPDx, LL_UCPD_InitTypeDef *UCPD_InitStruct) -{ - /* Check the ucpd Instance UCPDx*/ - assert_param(IS_UCPD_ALL_INSTANCE(UCPDx)); - - if (UCPD1 == UCPDx) - { - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); - } - - - LL_UCPD_Disable(UCPDx); - - /*---------------------------- UCPDx CFG1 Configuration ------------------------*/ - MODIFY_REG(UCPDx->CFG1, - UCPD_CFG1_PSC_UCPDCLK | UCPD_CFG1_TRANSWIN | UCPD_CFG1_IFRGAP | UCPD_CFG1_HBITCLKDIV, - UCPD_InitStruct->psc_ucpdclk | (UCPD_InitStruct->transwin << UCPD_CFG1_TRANSWIN_Pos) | - (UCPD_InitStruct->IfrGap << UCPD_CFG1_IFRGAP_Pos) | UCPD_InitStruct->HbitClockDiv); - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_UCPD_InitTypeDef field to default value. - * @param UCPD_InitStruct pointer to a @ref LL_UCPD_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_UCPD_StructInit(LL_UCPD_InitTypeDef *UCPD_InitStruct) -{ - /* Set UCPD_InitStruct fields to default values */ - UCPD_InitStruct->psc_ucpdclk = LL_UCPD_PSC_DIV2; - UCPD_InitStruct->transwin = 0x7; /* Divide by 8 */ - UCPD_InitStruct->IfrGap = 0x10; /* Divide by 17 */ - UCPD_InitStruct->HbitClockDiv = 0x0D; /* Divide by 14 to produce HBITCLK */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (UCPD1) */ -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c deleted file mode 100644 index 4c841c934..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_usb.c +++ /dev/null @@ -1,3700 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_usb.c - * @author MCD Application Team - * @brief USB Low Layer HAL module driver. - * - * This file provides firmware functions to manage the following - * functionalities of the USB Peripheral Controller: - * + Initialization/de-initialization functions - * + I/O operation functions - * + Peripheral Control functions - * + Peripheral State functions - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### How to use this driver ##### - ============================================================================== - [..] - (#) Fill parameters of Init structure in USB_CfgTypeDef structure. - - (#) Call USB_CoreInit() API to initialize the USB Core peripheral. - - (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. - - @endverbatim - - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" - -/** @addtogroup STM32U5xx_LL_USB_DRIVER - * @{ - */ - -#if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ -#if defined (USB_OTG_FS) || defined (USB_OTG_HS) -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx); - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup USB_LL_Exported_Functions USB Low Layer Exported Functions - * @{ - */ - -/** @defgroup USB_LL_Exported_Functions_Group1 Initialization/de-initialization functions - * @brief Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization/de-initialization functions ##### - =============================================================================== - -@endverbatim - * @{ - */ - -/** - * @brief Initializes the USB Core - * @param USBx USB Instance - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret; -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) - { - /* Init The UTMI Interface */ - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS); - } - - /* Reset after a PHY select */ - ret = USB_CoreReset(USBx); - - if (cfg.dma_enable == 1U) - { - USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2; - USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN; - } - -#else - - /* Select FS Embedded PHY */ - USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL; - - /* Reset after a PHY select */ - ret = USB_CoreReset(USBx); - - if (cfg.battery_charging_enable == 0U) - { - /* Activate the USB Transceiver */ - USBx->GCCFG |= USB_OTG_GCCFG_PWRDWN; - } - else - { - /* Deactivate the USB Transceiver */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN); - } -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - - return ret; -} - - -/** - * @brief Set the USB turnaround time - * @param USBx USB Instance - * @param hclk: AHB clock frequency - * @retval USB turnaround time In PHY Clocks number - */ -HAL_StatusTypeDef USB_SetTurnaroundTime(USB_OTG_GlobalTypeDef *USBx, - uint32_t hclk, uint8_t speed) -{ - uint32_t UsbTrd; - - /* The USBTRD is configured according to the tables below, depending on AHB frequency - used by application. In the low AHB frequency range it is used to stretch enough the USB response - time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access - latency to the Data FIFO */ - if (speed == USBD_FS_SPEED) - { - if ((hclk >= 14200000U) && (hclk < 15000000U)) - { - /* hclk Clock Range between 14.2-15 MHz */ - UsbTrd = 0xFU; - } - else if ((hclk >= 15000000U) && (hclk < 16000000U)) - { - /* hclk Clock Range between 15-16 MHz */ - UsbTrd = 0xEU; - } - else if ((hclk >= 16000000U) && (hclk < 17200000U)) - { - /* hclk Clock Range between 16-17.2 MHz */ - UsbTrd = 0xDU; - } - else if ((hclk >= 17200000U) && (hclk < 18500000U)) - { - /* hclk Clock Range between 17.2-18.5 MHz */ - UsbTrd = 0xCU; - } - else if ((hclk >= 18500000U) && (hclk < 20000000U)) - { - /* hclk Clock Range between 18.5-20 MHz */ - UsbTrd = 0xBU; - } - else if ((hclk >= 20000000U) && (hclk < 21800000U)) - { - /* hclk Clock Range between 20-21.8 MHz */ - UsbTrd = 0xAU; - } - else if ((hclk >= 21800000U) && (hclk < 24000000U)) - { - /* hclk Clock Range between 21.8-24 MHz */ - UsbTrd = 0x9U; - } - else if ((hclk >= 24000000U) && (hclk < 27700000U)) - { - /* hclk Clock Range between 24-27.7 MHz */ - UsbTrd = 0x8U; - } - else if ((hclk >= 27700000U) && (hclk < 32000000U)) - { - /* hclk Clock Range between 27.7-32 MHz */ - UsbTrd = 0x7U; - } - else /* if(hclk >= 32000000) */ - { - /* hclk Clock Range between 32-200 MHz */ - UsbTrd = 0x6U; - } - } - else if (speed == USBD_HS_SPEED) - { - UsbTrd = USBD_HS_TRDT_VALUE; - } - else - { - UsbTrd = USBD_DEFAULT_TRDT_VALUE; - } - - USBx->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT; - USBx->GUSBCFG |= (uint32_t)((UsbTrd << 10) & USB_OTG_GUSBCFG_TRDT); - - return HAL_OK; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx) -{ - USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT; - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode Set functional mode - * @param USBx Selected device - * @param mode current core mode - * This parameter can be one of these values: - * @arg USB_DEVICE_MODE Peripheral mode - * @arg USB_HOST_MODE Host mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx, USB_OTG_ModeTypeDef mode) -{ - uint32_t ms = 0U; - - USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD); - - if (mode == USB_HOST_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD; - - do - { - HAL_Delay(10U); - ms += 10U; - } while ((USB_GetMode(USBx) != (uint32_t)USB_HOST_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); - } - else if (mode == USB_DEVICE_MODE) - { - USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD; - - do - { - HAL_Delay(10U); - ms += 10U; - } while ((USB_GetMode(USBx) != (uint32_t)USB_DEVICE_MODE) && (ms < HAL_USB_CURRENT_MODE_MAX_DELAY_MS)); - } - else - { - return HAL_ERROR; - } - - if (ms == HAL_USB_CURRENT_MODE_MAX_DELAY_MS) - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief USB_DevInit Initializes the USB_OTG controller registers - * for device mode - * @param USBx Selected device - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - - for (i = 0U; i < 15U; i++) - { - USBx->DIEPTXF[i] = 0U; - } - -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - /* Disable USB PHY pulldown resistors */ - USBx->GCCFG &= ~USB_OTG_GCCFG_PULLDOWNEN; -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - - /* VBUS Sensing setup */ - if (cfg.vbus_sensing_enable == 0U) - { - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - - /* Deactivate VBUS Sensing B */ - USBx->GCCFG &= ~USB_OTG_GCCFG_VBDEN; - - /* B-peripheral session valid override enable */ -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - USBx->GCCFG |= USB_OTG_GCCFG_VBVALEXTOEN; - USBx->GCCFG |= USB_OTG_GCCFG_VBVALOVAL; -#else - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN; - USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL; -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - } - else - { -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - /* B-peripheral session valid override disable */ - USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALEXTOEN; - USBx->GCCFG &= ~USB_OTG_GCCFG_VBVALOVAL; -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - - /* Enable HW VBUS sensing */ - USBx->GCCFG |= USB_OTG_GCCFG_VBDEN; - } - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0U; - -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY) - { - if (cfg.speed == USBD_HS_SPEED) - { - /* Set Core speed to High speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH); - } - else - { - /* Set Core speed to Full speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_HIGH_IN_FULL); - } - } - else -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - { - /* Set Core speed to Full speed mode */ - (void)USB_SetDevSpeed(USBx, USB_OTG_SPEED_FULL); - } - - /* Flush the FIFOs */ - if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ - { - ret = HAL_ERROR; - } - - if (USB_FlushRxFifo(USBx) != HAL_OK) - { - ret = HAL_ERROR; - } - - /* Clear all pending Device Interrupts */ - USBx_DEVICE->DIEPMSK = 0U; - USBx_DEVICE->DOEPMSK = 0U; - USBx_DEVICE->DAINTMSK = 0U; - - for (i = 0U; i < cfg.dev_endpoints; i++) - { - if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - if (i == 0U) - { - USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_SNAK; - } - else - { - USBx_INEP(i)->DIEPCTL = USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK; - } - } - else - { - USBx_INEP(i)->DIEPCTL = 0U; - } - - USBx_INEP(i)->DIEPTSIZ = 0U; - USBx_INEP(i)->DIEPINT = 0xFB7FU; - } - - for (i = 0U; i < cfg.dev_endpoints; i++) - { - if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - if (i == 0U) - { - USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_SNAK; - } - else - { - USBx_OUTEP(i)->DOEPCTL = USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK; - } - } - else - { - USBx_OUTEP(i)->DOEPCTL = 0U; - } - - USBx_OUTEP(i)->DOEPTSIZ = 0U; - USBx_OUTEP(i)->DOEPINT = 0xFB7FU; - } - - USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM); - - /* Disable all interrupts. */ - USBx->GINTMSK = 0U; - - /* Clear any pending interrupts */ - USBx->GINTSTS = 0xBFFFFFFFU; - - /* Enable the common interrupts */ - if (cfg.dma_enable == 0U) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Device mode ONLY */ - USBx->GINTMSK |= USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST | - USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT | - USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM | - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM; - - if (cfg.Sof_enable != 0U) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM; - } - - if (cfg.vbus_sensing_enable == 1U) - { - USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT); - } - - return ret; -} - -/** - * @brief USB_FlushTxFifo Flush a Tx FIFO - * @param USBx Selected device - * @param num FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_OTG_GlobalTypeDef *USBx, uint32_t num) -{ - __IO uint32_t count = 0U; - - /* Wait for AHB master IDLE state. */ - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - - /* Flush TX Fifo */ - count = 0U; - USBx->GRSTCTL = (USB_OTG_GRSTCTL_TXFFLSH | (num << 6)); - - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo Flush Rx FIFO - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t count = 0U; - - /* Wait for AHB master IDLE state. */ - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - - /* Flush RX Fifo */ - count = 0U; - USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH; - - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH); - - return HAL_OK; -} - -/** - * @brief USB_SetDevSpeed Initializes the DevSpd field of DCFG register - * depending the PHY type and the enumeration speed of the device. - * @param USBx Selected device - * @param speed device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @retval Hal status - */ -HAL_StatusTypeDef USB_SetDevSpeed(const USB_OTG_GlobalTypeDef *USBx, uint8_t speed) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - USBx_DEVICE->DCFG |= speed; - return HAL_OK; -} - -/** - * @brief USB_GetDevSpeed Return the Dev Speed - * @param USBx Selected device - * @retval speed device speed - * This parameter can be one of these values: - * @arg USBD_HS_SPEED: High speed mode - * @arg USBD_FS_SPEED: Full speed mode - */ -uint8_t USB_GetDevSpeed(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint8_t speed; - uint32_t DevEnumSpeed = USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD; - - if (DevEnumSpeed == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ) - { - speed = USBD_HS_SPEED; - } - else if ((DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ) || - (DevEnumSpeed == DSTS_ENUMSPD_FS_PHY_48MHZ)) - { - speed = USBD_FS_SPEED; - } - else - { - speed = 0xFU; - } - - return speed; -} - -/** - * @brief Activate and configure an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); - - if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_USBAEP) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | (epnum << 22) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_USBAEP; - } - } - else - { - USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); - - if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) - { - USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DOEPCTL_USBAEP; - } - } - return HAL_OK; -} - -/** - * @brief Activate and configure a dedicated endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* Read DEPCTLn register */ - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= (ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | (epnum << 22) | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_USBAEP; - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK)); - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0U) - { - USBx_OUTEP(epnum)->DOEPCTL |= (ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ) | - ((uint32_t)ep->type << 18) | (epnum << 22) | - USB_OTG_DOEPCTL_USBAEP; - } - - USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16); - } - - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* Read DEPCTLn register */ - if (ep->is_in == 1U) - { - if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; - } - - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_USBAEP | - USB_OTG_DIEPCTL_MPSIZ | - USB_OTG_DIEPCTL_TXFNUM | - USB_OTG_DIEPCTL_SD0PID_SEVNFRM | - USB_OTG_DIEPCTL_EPTYP); - } - else - { - if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; - } - - USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_USBAEP | - USB_OTG_DOEPCTL_MPSIZ | - USB_OTG_DOEPCTL_SD0PID_SEVNFRM | - USB_OTG_DOEPCTL_EPTYP); - } - - return HAL_OK; -} - -/** - * @brief De-activate and de-initialize a dedicated endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - /* Read DEPCTLn register */ - if (ep->is_in == 1U) - { - if ((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SNAK; - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_EPDIS; - } - - USBx_INEP(epnum)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & (uint32_t)(1UL << (ep->num & EP_ADDR_MSK))); - } - else - { - if ((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SNAK; - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_EPDIS; - } - - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP; - USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((uint32_t)(1UL << (ep->num & EP_ADDR_MSK)) << 16)); - } - - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer : setup and starts a transfer over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - uint16_t pktcnt; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* Zero Length Packet? */ - if (ep->xfer_len == 0U) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - } - else - { - /* Program the transfer size and packet count - * as follows: xfersize = N * maxpacket + - * short_packet pktcnt = N + (short_packet - * exist ? 1 : 0) - */ - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ); - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT); - - if (epnum == 0U) - { - if (ep->xfer_len > ep->maxpacket) - { - ep->xfer_len = ep->maxpacket; - } - - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1U << 19)); - } - else - { - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & - (((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket) << 19)); - } - - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len); - - if (ep->type == EP_TYPE_ISOC) - { - USBx_INEP(epnum)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT); - USBx_INEP(epnum)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1U << 29)); - } - } - - if (dma == 1U) - { - if ((uint32_t)ep->dma_addr != 0U) - { - USBx_INEP(epnum)->DIEPDMA = (uint32_t)(ep->dma_addr); - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - } - - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - } - else - { - /* EP enable, IN data in FIFO */ - USBx_INEP(epnum)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA); - - if (ep->type != EP_TYPE_ISOC) - { - /* Enable the Tx FIFO Empty Interrupt for this EP */ - if (ep->xfer_len > 0U) - { - USBx_DEVICE->DIEPEMPMSK |= 1UL << (ep->num & EP_ADDR_MSK); - } - } - else - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM; - } - else - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; - } - - (void)USB_WritePacket(USBx, ep->xfer_buff, ep->num, (uint16_t)ep->xfer_len, dma); - } - } - } - else /* OUT endpoint */ - { - /* Program the transfer size and packet count as follows: - * pktcnt = N - * xfersize = N * maxpacket - */ - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ); - USBx_OUTEP(epnum)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT); - - if (epnum == 0U) - { - if (ep->xfer_len > 0U) - { - ep->xfer_len = ep->maxpacket; - } - - /* Store transfer size, for EP0 this is equal to endpoint max packet size */ - ep->xfer_size = ep->maxpacket; - - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - } - else - { - if (ep->xfer_len == 0U) - { - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket); - USBx_OUTEP(epnum)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - } - else - { - pktcnt = (uint16_t)((ep->xfer_len + ep->maxpacket - 1U) / ep->maxpacket); - ep->xfer_size = ep->maxpacket * pktcnt; - - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_PKTCNT & ((uint32_t)pktcnt << 19); - USBx_OUTEP(epnum)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_XFRSIZ & ep->xfer_size; - } - } - - if (dma == 1U) - { - if ((uint32_t)ep->xfer_buff != 0U) - { - USBx_OUTEP(epnum)->DOEPDMA = (uint32_t)(ep->xfer_buff); - } - } - - if (ep->type == EP_TYPE_ISOC) - { - if ((USBx_DEVICE->DSTS & (1U << 8)) == 0U) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM; - } - else - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; - } - } - /* EP enable */ - USBx_OUTEP(epnum)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA); - } - - return HAL_OK; -} - - -/** - * @brief USB_EPStoptXfer Stop transfer on an EP - * @param USBx usb device instance - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStopXfer(const USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep) -{ - __IO uint32_t count = 0U; - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /* EP enable, IN data in FIFO */ - if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA) - { - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_SNAK); - USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_EPDIS); - - do - { - count++; - - if (count > 10000U) - { - ret = HAL_ERROR; - break; - } - } while (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA); - } - } - else /* OUT endpoint */ - { - if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_SNAK); - USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_EPDIS); - - do - { - count++; - - if (count > 10000U) - { - ret = HAL_ERROR; - break; - } - } while (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA); - } - } - - return ret; -} - - -/** - * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated - * with the EP/channel - * @param USBx Selected device - * @param src pointer to source buffer - * @param ch_ep_num endpoint or host channel number - * @param len Number of bytes to write - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL status - */ -HAL_StatusTypeDef USB_WritePacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *src, - uint8_t ch_ep_num, uint16_t len, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint8_t *pSrc = src; - uint32_t count32b; - uint32_t i; - - if (dma == 0U) - { - count32b = ((uint32_t)len + 3U) / 4U; - for (i = 0U; i < count32b; i++) - { - USBx_DFIFO((uint32_t)ch_ep_num) = __UNALIGNED_UINT32_READ(pSrc); - pSrc++; - pSrc++; - pSrc++; - pSrc++; - } - } - - return HAL_OK; -} - -/** - * @brief USB_ReadPacket : read a packet from the RX FIFO - * @param USBx Selected device - * @param dest source pointer - * @param len Number of bytes to read - * @retval pointer to destination buffer - */ -void *USB_ReadPacket(const USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint8_t *pDest = dest; - uint32_t pData; - uint32_t i; - uint32_t count32b = (uint32_t)len >> 2U; - uint16_t remaining_bytes = len % 4U; - - for (i = 0U; i < count32b; i++) - { - __UNALIGNED_UINT32_WRITE(pDest, USBx_DFIFO(0U)); - pDest++; - pDest++; - pDest++; - pDest++; - } - - /* When Number of data is not word aligned, read the remaining byte */ - if (remaining_bytes != 0U) - { - i = 0U; - __UNALIGNED_UINT32_WRITE(&pData, USBx_DFIFO(0U)); - - do - { - *(uint8_t *)pDest = (uint8_t)(pData >> (8U * (uint8_t)(i))); - i++; - pDest++; - remaining_bytes--; - } while (remaining_bytes != 0U); - } - - return ((void *)pDest); -} - -/** - * @brief USB_EPSetStall : set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - if (((USBx_INEP(epnum)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_INEP(epnum)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS); - } - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_STALL; - } - else - { - if (((USBx_OUTEP(epnum)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == 0U) && (epnum != 0U)) - { - USBx_OUTEP(epnum)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS); - } - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_STALL; - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall : Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(const USB_OTG_GlobalTypeDef *USBx, const USB_OTG_EPTypeDef *ep) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t epnum = (uint32_t)ep->num; - - if (ep->is_in == 1U) - { - USBx_INEP(epnum)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_INEP(epnum)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - else - { - USBx_OUTEP(epnum)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL; - if ((ep->type == EP_TYPE_INTR) || (ep->type == EP_TYPE_BULK)) - { - USBx_OUTEP(epnum)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */ - } - } - return HAL_OK; -} - -/** - * @brief USB_StopDevice : Stop the usb device mode - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx) -{ - HAL_StatusTypeDef ret; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - - /* Clear Pending interrupt */ - for (i = 0U; i < 15U; i++) - { - USBx_INEP(i)->DIEPINT = 0xFB7FU; - USBx_OUTEP(i)->DOEPINT = 0xFB7FU; - } - - /* Clear interrupt masks */ - USBx_DEVICE->DIEPMSK = 0U; - USBx_DEVICE->DOEPMSK = 0U; - USBx_DEVICE->DAINTMSK = 0U; - - /* Flush the FIFO */ - ret = USB_FlushRxFifo(USBx); - if (ret != HAL_OK) - { - return ret; - } - - ret = USB_FlushTxFifo(USBx, 0x10U); - if (ret != HAL_OK) - { - return ret; - } - - return ret; -} - -/** - * @brief USB_SetDevAddress : Stop the usb device mode - * @param USBx Selected device - * @param address new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress(const USB_OTG_GlobalTypeDef *USBx, uint8_t address) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - USBx_DEVICE->DCFG &= ~(USB_OTG_DCFG_DAD); - USBx_DEVICE->DCFG |= ((uint32_t)address << 4) & USB_OTG_DCFG_DAD; - - return HAL_OK; -} - -/** - * @brief USB_DevConnect : Connect the USB device by enabling Rpu - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* In case phy is stopped, ensure to ungate and restore the phy CLK */ - USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); - - USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS; - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect : Disconnect the USB device by disabling Rpu - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* In case phy is stopped, ensure to ungate and restore the phy CLK */ - USBx_PCGCCTL &= ~(USB_OTG_PCGCCTL_STOPCLK | USB_OTG_PCGCCTL_GATECLK); - - USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS; - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts: return the global USB interrupt status - * @param USBx Selected device - * @retval USB Global Interrupt status - */ -uint32_t USB_ReadInterrupts(USB_OTG_GlobalTypeDef const *USBx) -{ - uint32_t tmpreg; - - tmpreg = USBx->GINTSTS; - tmpreg &= USBx->GINTMSK; - - return tmpreg; -} - -/** - * @brief USB_ReadChInterrupts: return USB channel interrupt status - * @param USBx Selected device - * @param chnum Channel number - * @retval USB Channel Interrupt status - */ -uint32_t USB_ReadChInterrupts(const USB_OTG_GlobalTypeDef *USBx, uint8_t chnum) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_HC(chnum)->HCINT; - tmpreg &= USBx_HC(chnum)->HCINTMSK; - - return tmpreg; -} - -/** - * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status - * @param USBx Selected device - * @retval USB Device OUT EP interrupt status - */ -uint32_t USB_ReadDevAllOutEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - - return ((tmpreg & 0xffff0000U) >> 16); -} - -/** - * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status - * @param USBx Selected device - * @retval USB Device IN EP interrupt status - */ -uint32_t USB_ReadDevAllInEpInterrupt(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_DEVICE->DAINT; - tmpreg &= USBx_DEVICE->DAINTMSK; - - return ((tmpreg & 0xFFFFU)); -} - -/** - * @brief Returns Device OUT EP Interrupt register - * @param USBx Selected device - * @param epnum endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device OUT EP Interrupt register - */ -uint32_t USB_ReadDevOutEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - - tmpreg = USBx_OUTEP((uint32_t)epnum)->DOEPINT; - tmpreg &= USBx_DEVICE->DOEPMSK; - - return tmpreg; -} - -/** - * @brief Returns Device IN EP Interrupt register - * @param USBx Selected device - * @param epnum endpoint number - * This parameter can be a value from 0 to 15 - * @retval Device IN EP Interrupt register - */ -uint32_t USB_ReadDevInEPInterrupt(const USB_OTG_GlobalTypeDef *USBx, uint8_t epnum) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t tmpreg; - uint32_t msk; - uint32_t emp; - - msk = USBx_DEVICE->DIEPMSK; - emp = USBx_DEVICE->DIEPEMPMSK; - msk |= ((emp >> (epnum & EP_ADDR_MSK)) & 0x1U) << 7; - tmpreg = USBx_INEP((uint32_t)epnum)->DIEPINT & msk; - - return tmpreg; -} - -/** - * @brief USB_ClearInterrupts: clear a USB interrupt - * @param USBx Selected device - * @param interrupt flag - * @retval None - */ -void USB_ClearInterrupts(USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt) -{ - USBx->GINTSTS &= interrupt; -} - -/** - * @brief Returns USB core mode - * @param USBx Selected device - * @retval return core mode : Host or Device - * This parameter can be one of these values: - * 0 : Host - * 1 : Device - */ -uint32_t USB_GetMode(const USB_OTG_GlobalTypeDef *USBx) -{ - return ((USBx->GINTSTS) & 0x1U); -} - -/** - * @brief Activate EP0 for Setup transactions - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateSetup(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* Set the MPS of the IN EP0 to 64 bytes */ - USBx_INEP(0U)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ; - - USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK; - - return HAL_OK; -} - -/** - * @brief Prepare the EP0 to start the first control setup - * @param USBx Selected device - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @param psetup pointer to setup packet - * @retval HAL status - */ -HAL_StatusTypeDef USB_EP0_OutStart(const USB_OTG_GlobalTypeDef *USBx, uint8_t dma, const uint8_t *psetup) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t gSNPSiD = *(__IO const uint32_t *)(&USBx->CID + 0x1U); - - if (gSNPSiD > USB_OTG_CORE_ID_300A) - { - if ((USBx_OUTEP(0U)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA) - { - return HAL_OK; - } - } - - USBx_OUTEP(0U)->DOEPTSIZ = 0U; - USBx_OUTEP(0U)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1U << 19)); - USBx_OUTEP(0U)->DOEPTSIZ |= (3U * 8U); - USBx_OUTEP(0U)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT; - - if (dma == 1U) - { - USBx_OUTEP(0U)->DOEPDMA = (uint32_t)psetup; - /* EP enable */ - USBx_OUTEP(0U)->DOEPCTL |= USB_OTG_DOEPCTL_EPENA | USB_OTG_DOEPCTL_USBAEP; - } - - return HAL_OK; -} - -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx) -{ - __IO uint32_t count = 0U; - - /* Wait for AHB master IDLE state. */ - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0U); - - /* Core Soft Reset */ - count = 0U; - USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST; - - do - { - count++; - - if (count > HAL_USB_TIMEOUT) - { - return HAL_TIMEOUT; - } - } while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST); - - return HAL_OK; -} - -/** - * @brief USB_HostInit : Initializes the USB OTG controller registers - * for Host mode - * @param USBx Selected device - * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t i; - -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - /* Enable USB PHY pulldown resistors */ - USBx->GCCFG |= USB_OTG_GCCFG_PULLDOWNEN; -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - - /* Restart the Phy Clock */ - USBx_PCGCCTL = 0U; - -#if defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) \ - || defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) - /* Disable VBUS override */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_VBVALOVAL | USB_OTG_GCCFG_VBVALEXTOEN); -#endif /* defined (STM32U595xx) || defined (STM32U5A5xx) || defined (STM32U599xx) || defined (STM32U5A9xx) || - defined (STM32U5F7xx) || defined (STM32U5G7xx) || defined (STM32U5F9xx) || defined (STM32U5G9xx) */ - - /* Disable VBUS sensing */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_VBDEN); -#if defined (STM32U575xx) || defined (STM32U585xx) - /* Disable Battery chargin detector */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_BCDEN); -#else - /* Disable Battery chargin detector */ - USBx->GCCFG &= ~(USB_OTG_GCCFG_PDEN); - USBx->GCCFG &= ~(USB_OTG_GCCFG_SDEN); -#endif /* defined (STM32U575xx) || defined (STM32U585xx) */ - - if ((USBx->GUSBCFG & USB_OTG_GUSBCFG_PHYSEL) == 0U) - { - if (cfg.speed == USBH_FSLS_SPEED) - { - /* Force Device Enumeration to FS/LS mode only */ - USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS; - } - else - { - /* Set default Max speed support */ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - } - else - { - /* Set default Max speed support */ - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS); - } - - /* Make sure the FIFOs are flushed. */ - if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ - { - ret = HAL_ERROR; - } - - if (USB_FlushRxFifo(USBx) != HAL_OK) - { - ret = HAL_ERROR; - } - - /* Clear all pending HC Interrupts */ - for (i = 0U; i < cfg.Host_channels; i++) - { - USBx_HC(i)->HCINT = CLEAR_INTERRUPT_MASK; - USBx_HC(i)->HCINTMSK = 0U; - } - - /* Disable all interrupts. */ - USBx->GINTMSK = 0U; - - /* Clear any pending interrupts */ - USBx->GINTSTS = CLEAR_INTERRUPT_MASK; -#if defined (USB_OTG_HS) - if (USBx == USB_OTG_HS) - { - /* set Rx FIFO size */ - USBx->GRXFSIZ = 0x200U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x100U << 16) & USB_OTG_NPTXFD) | 0x200U); - USBx->HPTXFSIZ = (uint32_t)(((0xE0U << 16) & USB_OTG_HPTXFSIZ_PTXFD) | 0x300U); - } - else -#endif /* defined (USB_OTG_HS) */ - { - /* set Rx FIFO size */ - USBx->GRXFSIZ = 0x80U; - USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t)(((0x60U << 16) & USB_OTG_NPTXFD) | 0x80U); - USBx->HPTXFSIZ = (uint32_t)(((0x40U << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0U); - } - - /* Enable the common interrupts */ - if (cfg.dma_enable == 0U) - { - USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM; - } - - /* Enable interrupts matching to the Host mode ONLY */ - USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM | \ - USB_OTG_GINTMSK_SOFM | USB_OTG_GINTSTS_DISCINT | \ - USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM); - - return ret; -} - -/** - * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the - * HCFG register on the PHY type and set the right frame interval - * @param USBx Selected device - * @param freq clock frequency - * This parameter can be one of these values: - * HCFG_48_MHZ : Full Speed 48 MHz Clock - * HCFG_6_MHZ : Low Speed 6 MHz Clock - * @retval HAL status - */ -HAL_StatusTypeDef USB_InitFSLSPClkSel(const USB_OTG_GlobalTypeDef *USBx, uint8_t freq) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS); - USBx_HOST->HCFG |= (uint32_t)freq & USB_OTG_HCFG_FSLSPCS; - - if (freq == HCFG_48_MHZ) - { - USBx_HOST->HFIR = HFIR_48_MHZ; - } - else if (freq == HCFG_6_MHZ) - { - USBx_HOST->HFIR = HFIR_6_MHZ; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief USB_OTG_ResetPort : Reset Host Port - * @param USBx Selected device - * @retval HAL status - * @note (1)The application must wait at least 10 ms - * before clearing the reset bit. - */ -HAL_StatusTypeDef USB_ResetPort(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - __IO uint32_t hprt0 = 0U; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0); - HAL_Delay(100U); /* See Note #1 */ - USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0); - HAL_Delay(10U); - - return HAL_OK; -} - -/** - * @brief USB_DriveVbus : activate or de-activate vbus - * @param state VBUS state - * This parameter can be one of these values: - * 0 : Deactivate VBUS - * 1 : Activate VBUS - * @retval HAL status - */ -HAL_StatusTypeDef USB_DriveVbus(const USB_OTG_GlobalTypeDef *USBx, uint8_t state) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0 = 0U; - - hprt0 = USBx_HPRT0; - - hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET | - USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG); - - if (((hprt0 & USB_OTG_HPRT_PPWR) == 0U) && (state == 1U)) - { - USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0); - } - if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0U)) - { - USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0); - } - return HAL_OK; -} - -/** - * @brief Return Host Core speed - * @param USBx Selected device - * @retval speed : Host speed - * This parameter can be one of these values: - * @arg HCD_SPEED_HIGH: High speed mode - * @arg HCD_SPEED_FULL: Full speed mode - * @arg HCD_SPEED_LOW: Low speed mode - */ -uint32_t USB_GetHostSpeed(USB_OTG_GlobalTypeDef const *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t hprt0 = 0U; - - hprt0 = USBx_HPRT0; - return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17); -} - -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_OTG_GlobalTypeDef const *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM); -} - -/** - * @brief Initialize a host channel - * @param USBx Selected device - * @param ch_num Channel number - * This parameter can be a value from 1 to 15 - * @param epnum Endpoint number - * This parameter can be a value from 1 to 15 - * @param dev_address Current device address - * This parameter can be a value from 0 to 255 - * @param speed Current device speed - * This parameter can be one of these values: - * @arg USB_OTG_SPEED_HIGH: High speed mode - * @arg USB_OTG_SPEED_FULL: Full speed mode - * @arg USB_OTG_SPEED_LOW: Low speed mode - * @param ep_type Endpoint Type - * This parameter can be one of these values: - * @arg EP_TYPE_CTRL: Control type - * @arg EP_TYPE_ISOC: Isochronous type - * @arg EP_TYPE_BULK: Bulk type - * @arg EP_TYPE_INTR: Interrupt type - * @param mps Max Packet Size - * This parameter can be a value from 0 to 32K - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num, - uint8_t epnum, uint8_t dev_address, uint8_t speed, - uint8_t ep_type, uint16_t mps) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t HCcharEpDir; - uint32_t HCcharLowSpeed; - uint32_t HostCoreSpeed; - - /* Clear old interrupt conditions for this host channel. */ - USBx_HC((uint32_t)ch_num)->HCINT = CLEAR_INTERRUPT_MASK; - - /* Enable channel interrupts required for this transfer. */ - switch (ep_type) - { - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | - USB_OTG_HCINTMSK_STALLM | - USB_OTG_HCINTMSK_TXERRM | - USB_OTG_HCINTMSK_DTERRM | - USB_OTG_HCINTMSK_AHBERR | - USB_OTG_HCINTMSK_NAKM; - - if ((epnum & 0x80U) == 0x80U) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - else - { -#if defined (USB_OTG_HS) - if (USBx == USB_OTG_HS) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET | - USB_OTG_HCINTMSK_ACKM; - } -#endif /* defined (USB_OTG_HS) */ - } - break; - - case EP_TYPE_INTR: - USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | - USB_OTG_HCINTMSK_STALLM | - USB_OTG_HCINTMSK_TXERRM | - USB_OTG_HCINTMSK_DTERRM | - USB_OTG_HCINTMSK_NAKM | - USB_OTG_HCINTMSK_AHBERR | - USB_OTG_HCINTMSK_FRMORM; - - if ((epnum & 0x80U) == 0x80U) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM; - } - - break; - - case EP_TYPE_ISOC: - USBx_HC((uint32_t)ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM | - USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_AHBERR | - USB_OTG_HCINTMSK_FRMORM; - - if ((epnum & 0x80U) == 0x80U) - { - USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM); - } - break; - - default: - ret = HAL_ERROR; - break; - } - - /* Clear Hub Start Split transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; - - /* Enable host channel Halt interrupt */ - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM; - - /* Enable the top level host channel interrupt. */ - USBx_HOST->HAINTMSK |= 1UL << (ch_num & 0xFU); - - /* Make sure host channel interrupts are enabled. */ - USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM; - - /* Program the HCCHAR register */ - if ((epnum & 0x80U) == 0x80U) - { - HCcharEpDir = (0x1U << 15) & USB_OTG_HCCHAR_EPDIR; - } - else - { - HCcharEpDir = 0U; - } - - HostCoreSpeed = USB_GetHostSpeed(USBx); - - /* LS device plugged to HUB */ - if ((speed == HPRT0_PRTSPD_LOW_SPEED) && (HostCoreSpeed != HPRT0_PRTSPD_LOW_SPEED)) - { - HCcharLowSpeed = (0x1U << 17) & USB_OTG_HCCHAR_LSDEV; - } - else - { - HCcharLowSpeed = 0U; - } - - USBx_HC((uint32_t)ch_num)->HCCHAR = (((uint32_t)dev_address << 22) & USB_OTG_HCCHAR_DAD) | - ((((uint32_t)epnum & 0x7FU) << 11) & USB_OTG_HCCHAR_EPNUM) | - (((uint32_t)ep_type << 18) & USB_OTG_HCCHAR_EPTYP) | - ((uint32_t)mps & USB_OTG_HCCHAR_MPSIZ) | - USB_OTG_HCCHAR_MC_0 | HCcharEpDir | HCcharLowSpeed; - - if ((ep_type == EP_TYPE_INTR) || (ep_type == EP_TYPE_ISOC)) - { - USBx_HC((uint32_t)ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM; - } - - return ret; -} - -/** - * @brief Start a transfer over a host channel - * @param USBx Selected device - * @param hc pointer to host channel structure - * @param dma USB dma enabled or disabled - * This parameter can be one of these values: - * 0 : DMA feature not used - * 1 : DMA feature used - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t ch_num = (uint32_t)hc->ch_num; - __IO uint32_t tmpreg; - uint8_t is_oddframe; - uint16_t len_words; - uint16_t num_packets; - uint16_t max_hc_pkt_count = HC_MAX_PKT_CNT; - -#if defined (USB_OTG_HS) - if (USBx == USB_OTG_HS) - { - /* in DMA mode host Core automatically issues ping in case of NYET/NAK */ - if (dma == 1U) - { - if (((hc->ep_type == EP_TYPE_CTRL) || (hc->ep_type == EP_TYPE_BULK)) && (hc->do_ssplit == 0U)) - { - - USBx_HC((uint32_t)ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | - USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_NAKM); - } - } - else - { - if ((hc->speed == USBH_HS_SPEED) && (hc->do_ping == 1U)) - { - (void)USB_DoPing(USBx, hc->ch_num); - return HAL_OK; - } - } - } -#endif /* defined (USB_OTG_HS) */ - - if (hc->do_ssplit == 1U) - { - /* Set number of packet to 1 for Split transaction */ - num_packets = 1U; - - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - else - { - if (hc->ep_type == EP_TYPE_ISOC) - { - if (hc->xfer_len > ISO_SPLT_MPS) - { - /* Isochrone Max Packet Size for Split mode */ - hc->XferSize = hc->max_packet; - hc->xfer_len = hc->XferSize; - - if ((hc->iso_splt_xactPos == HCSPLT_BEGIN) || (hc->iso_splt_xactPos == HCSPLT_MIDDLE)) - { - hc->iso_splt_xactPos = HCSPLT_MIDDLE; - } - else - { - hc->iso_splt_xactPos = HCSPLT_BEGIN; - } - } - else - { - hc->XferSize = hc->xfer_len; - - if ((hc->iso_splt_xactPos != HCSPLT_BEGIN) && (hc->iso_splt_xactPos != HCSPLT_MIDDLE)) - { - hc->iso_splt_xactPos = HCSPLT_FULL; - } - else - { - hc->iso_splt_xactPos = HCSPLT_END; - } - } - } - else - { - if ((dma == 1U) && (hc->xfer_len > hc->max_packet)) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - else - { - hc->XferSize = hc->xfer_len; - } - } - } - } - else - { - /* Compute the expected number of packets associated to the transfer */ - if (hc->xfer_len > 0U) - { - num_packets = (uint16_t)((hc->xfer_len + hc->max_packet - 1U) / hc->max_packet); - - if (num_packets > max_hc_pkt_count) - { - num_packets = max_hc_pkt_count; - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - } - else - { - num_packets = 1U; - } - - /* - * For IN channel HCTSIZ.XferSize is expected to be an integer multiple of - * max_packet size. - */ - if (hc->ep_is_in != 0U) - { - hc->XferSize = (uint32_t)num_packets * hc->max_packet; - } - else - { - hc->XferSize = hc->xfer_len; - } - } - - /* Initialize the HCTSIZn register */ - USBx_HC(ch_num)->HCTSIZ = (hc->XferSize & USB_OTG_HCTSIZ_XFRSIZ) | - (((uint32_t)num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | - (((uint32_t)hc->data_pid << 29) & USB_OTG_HCTSIZ_DPID); - - if (dma != 0U) - { - /* xfer_buff MUST be 32-bits aligned */ - USBx_HC(ch_num)->HCDMA = (uint32_t)hc->xfer_buff; - } - - is_oddframe = (((uint32_t)USBx_HOST->HFNUM & 0x01U) != 0U) ? 0U : 1U; - USBx_HC(ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM; - USBx_HC(ch_num)->HCCHAR |= (uint32_t)is_oddframe << 29; - - if (hc->do_ssplit == 1U) - { - /* Set Hub start Split transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT = ((uint32_t)hc->hub_addr << USB_OTG_HCSPLT_HUBADDR_Pos) | - (uint32_t)hc->hub_port_nbr | USB_OTG_HCSPLT_SPLITEN; - - /* unmask ack & nyet for IN/OUT transactions */ - USBx_HC((uint32_t)ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_ACKM | - USB_OTG_HCINTMSK_NYET); - - if ((hc->do_csplit == 1U) && (hc->ep_is_in == 0U)) - { - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; - USBx_HC((uint32_t)ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_NYET; - } - - if (((hc->ep_type == EP_TYPE_ISOC) || (hc->ep_type == EP_TYPE_INTR)) && - (hc->do_csplit == 1U) && (hc->ep_is_in == 1U)) - { - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_COMPLSPLT; - } - - /* Position management for iso out transaction on split mode */ - if ((hc->ep_type == EP_TYPE_ISOC) && (hc->ep_is_in == 0U)) - { - /* Set data payload position */ - switch (hc->iso_splt_xactPos) - { - case HCSPLT_BEGIN: - /* First data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_1; - break; - - case HCSPLT_MIDDLE: - /* Middle data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_Pos; - break; - - case HCSPLT_END: - /* End data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS_0; - break; - - case HCSPLT_FULL: - /* Entire data payload for OUT Transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT |= USB_OTG_HCSPLT_XACTPOS; - break; - - default: - break; - } - } - } - else - { - /* Clear Hub Start Split transaction */ - USBx_HC((uint32_t)ch_num)->HCSPLT = 0U; - } - - /* Set host channel enable */ - tmpreg = USBx_HC(ch_num)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - - /* make sure to set the correct ep direction */ - if (hc->ep_is_in != 0U) - { - tmpreg |= USB_OTG_HCCHAR_EPDIR; - } - else - { - tmpreg &= ~USB_OTG_HCCHAR_EPDIR; - } - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(ch_num)->HCCHAR = tmpreg; - - if (dma != 0U) /* dma mode */ - { - return HAL_OK; - } - - if ((hc->ep_is_in == 0U) && (hc->xfer_len > 0U) && (hc->do_csplit == 0U)) - { - switch (hc->ep_type) - { - /* Non periodic transfer */ - case EP_TYPE_CTRL: - case EP_TYPE_BULK: - - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - - /* check if there is enough space in FIFO space */ - if (len_words > (USBx->HNPTXSTS & 0xFFFFU)) - { - /* need to process data in nptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM; - } - break; - - /* Periodic transfer */ - case EP_TYPE_INTR: - case EP_TYPE_ISOC: - len_words = (uint16_t)((hc->xfer_len + 3U) / 4U); - /* check if there is enough space in FIFO space */ - if (len_words > (USBx_HOST->HPTXSTS & 0xFFFFU)) /* split the transfer */ - { - /* need to process data in ptxfempty interrupt */ - USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM; - } - break; - - default: - break; - } - - /* Write packet into the Tx FIFO. */ - (void)USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, (uint16_t)hc->xfer_len, 0); - } - - return HAL_OK; -} - -/** - * @brief Read all host channel interrupts status - * @param USBx Selected device - * @retval HAL state - */ -uint32_t USB_HC_ReadInterrupt(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - return ((USBx_HOST->HAINT) & 0xFFFFU); -} - -/** - * @brief Halt a host channel - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Halt(const USB_OTG_GlobalTypeDef *USBx, uint8_t hc_num) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t hcnum = (uint32_t)hc_num; - __IO uint32_t count = 0U; - uint32_t HcEpType = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_EPTYP) >> 18; - uint32_t ChannelEna = (USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) >> 31; - uint32_t SplitEna = (USBx_HC(hcnum)->HCSPLT & USB_OTG_HCSPLT_SPLITEN) >> 31; - - /* In buffer DMA, Channel disable must not be programmed for non-split periodic channels. - At the end of the next uframe/frame (in the worst case), the core generates a channel halted - and disables the channel automatically. */ - - if ((((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == USB_OTG_GAHBCFG_DMAEN) && (SplitEna == 0U)) && - ((ChannelEna == 0U) || (((HcEpType == HCCHAR_ISOC) || (HcEpType == HCCHAR_INTR))))) - { - return HAL_OK; - } - - /* Check for space in the request queue to issue the halt. */ - if ((HcEpType == HCCHAR_CTRL) || (HcEpType == HCCHAR_BULK)) - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx->GAHBCFG & USB_OTG_GAHBCFG_DMAEN) == 0U) - { - if ((USBx->HNPTXSTS & (0xFFU << 16)) == 0U) - { - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - do - { - count++; - - if (count > 1000U) - { - break; - } - } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHDIS; - - if ((USBx_HOST->HPTXSTS & (0xFFU << 16)) == 0U) - { - USBx_HC(hcnum)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA; - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - do - { - count++; - - if (count > 1000U) - { - break; - } - } while ((USBx_HC(hcnum)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - else - { - USBx_HC(hcnum)->HCCHAR |= USB_OTG_HCCHAR_CHENA; - } - } - - return HAL_OK; -} - -/** - * @brief Initiate Do Ping protocol - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_DoPing(const USB_OTG_GlobalTypeDef *USBx, uint8_t ch_num) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - uint32_t chnum = (uint32_t)ch_num; - uint32_t num_packets = 1U; - uint32_t tmpreg; - - USBx_HC(chnum)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) | - USB_OTG_HCTSIZ_DOPING; - - /* Set host channel enable */ - tmpreg = USBx_HC(chnum)->HCCHAR; - tmpreg &= ~USB_OTG_HCCHAR_CHDIS; - tmpreg |= USB_OTG_HCCHAR_CHENA; - USBx_HC(chnum)->HCCHAR = tmpreg; - - return HAL_OK; -} - -/** - * @brief Stop Host Core - * @param USBx Selected device - * @retval HAL state - */ -HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t USBx_BASE = (uint32_t)USBx; - __IO uint32_t count = 0U; - uint32_t value; - uint32_t i; - - (void)USB_DisableGlobalInt(USBx); - - /* Flush USB FIFO */ - if (USB_FlushTxFifo(USBx, 0x10U) != HAL_OK) /* all Tx FIFOs */ - { - ret = HAL_ERROR; - } - - if (USB_FlushRxFifo(USBx) != HAL_OK) - { - ret = HAL_ERROR; - } - - /* Flush out any leftover queued requests. */ - for (i = 0U; i <= 15U; i++) - { - value = USBx_HC(i)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value &= ~USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; - } - - /* Halt all channels to put them into a known state. */ - for (i = 0U; i <= 15U; i++) - { - value = USBx_HC(i)->HCCHAR; - value |= USB_OTG_HCCHAR_CHDIS; - value |= USB_OTG_HCCHAR_CHENA; - value &= ~USB_OTG_HCCHAR_EPDIR; - USBx_HC(i)->HCCHAR = value; - - do - { - count++; - - if (count > 1000U) - { - break; - } - } while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA); - } - - /* Clear any pending Host interrupts */ - USBx_HOST->HAINT = CLEAR_INTERRUPT_MASK; - USBx->GINTSTS = CLEAR_INTERRUPT_MASK; - - (void)USB_EnableGlobalInt(USBx); - - return ret; -} - -/** - * @brief USB_ActivateRemoteWakeup active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - if ((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS) - { - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG; - } - - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(const USB_OTG_GlobalTypeDef *USBx) -{ - uint32_t USBx_BASE = (uint32_t)USBx; - - /* active Remote wakeup signalling */ - USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG); - - return HAL_OK; -} -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) */ - -#if defined (USB_DRD_FS) -static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx); -#if (USE_USB_DOUBLE_BUFFER == 1U) -static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, - USB_DRD_HCTypeDef *hc, - uint32_t ch_reg, - uint32_t *len); - -static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, - USB_DRD_HCTypeDef *hc, - uint32_t len); -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - -/** - * @brief Reset the USB Core (needed after USB clock settings change) - * @param USBx Selected device - * @retval HAL status - */ -static HAL_StatusTypeDef USB_CoreReset(USB_DRD_TypeDef *USBx) -{ - /* Disable Host Mode */ - USBx->CNTR &= ~USB_CNTR_HOST; - - /* Force Reset IP */ - USBx->CNTR |= USB_CNTR_USBRST; - - return HAL_OK; -} - -/** - * @brief Initializes the USB Core - * @param USBx USB Instance - * @param cfg pointer to a USB_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_CoreInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret; - UNUSED(cfg); - - if (USBx == NULL) - { - return HAL_ERROR; - } - - /* Reset after a PHY select */ - ret = USB_CoreReset(USBx); - - /* Clear pending interrupts */ - USBx->ISTR = 0U; - - return ret; -} - -/** - * @brief USB_EnableGlobalInt - * Enables the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_EnableGlobalInt(USB_DRD_TypeDef *USBx) -{ - uint32_t winterruptmask; - - /* Clear pending interrupts */ - USBx->ISTR = 0U; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | - USB_CNTR_SUSPM | USB_CNTR_ERRM | - USB_CNTR_SOFM | USB_CNTR_ESOFM | - USB_CNTR_RESETM | USB_CNTR_L1REQM; - - /* Set interrupt mask */ - USBx->CNTR = winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_DisableGlobalInt - * Disable the controller's Global Int in the AHB Config reg - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DisableGlobalInt(USB_DRD_TypeDef *USBx) -{ - uint32_t winterruptmask; - - /* Set winterruptmask variable */ - winterruptmask = USB_CNTR_CTRM | USB_CNTR_WKUPM | - USB_CNTR_SUSPM | USB_CNTR_ERRM | - USB_CNTR_SOFM | USB_CNTR_ESOFM | - USB_CNTR_RESETM | USB_CNTR_L1REQM; - - /* Clear interrupt mask */ - USBx->CNTR &= ~winterruptmask; - - return HAL_OK; -} - -/** - * @brief USB_SetCurrentMode Set functional mode - * @param USBx Selected device - * @param mode current core mode - * This parameter can be one of the these values: - * @arg USB_DEVICE_MODE Peripheral mode - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_DRD_TypeDef *USBx, USB_DRD_ModeTypeDef mode) -{ - if (mode == USB_DEVICE_MODE) - { - USBx->CNTR &= ~USB_CNTR_HOST; - } - else if (mode == USB_HOST_MODE) - { - USBx->CNTR |= USB_CNTR_HOST; - } - else - { - return HAL_ERROR; - } - - return HAL_OK; -} - -/** - * @brief USB_DevInit Initializes the USB controller registers - * for device mode - * @param USBx Selected device - * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) -{ - HAL_StatusTypeDef ret; - - /* Prevent unused argument(s) compilation warning */ - UNUSED(cfg); - - /* Force Reset */ - USBx->CNTR = USB_CNTR_USBRST; - - /* Release Reset */ - USBx->CNTR &= ~USB_CNTR_USBRST; - - /* Set the Device Mode */ - ret = USB_SetCurrentMode(USBx, USB_DEVICE_MODE); - - /* Clear pending interrupts */ - USBx->ISTR = 0U; - - return ret; -} - -/** - * @brief USB_FlushTxFifo : Flush a Tx FIFO - * @param USBx : Selected device - * @param num : FIFO number - * This parameter can be a value from 1 to 15 - 15 means Flush all Tx FIFOs - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushTxFifo(USB_DRD_TypeDef const *USBx, uint32_t num) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - UNUSED(num); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - -/** - * @brief USB_FlushRxFifo : Flush Rx FIFO - * @param USBx : Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_FlushRxFifo(USB_DRD_TypeDef const *USBx) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(USBx); - - /* NOTE : - This function is not required by USB Device FS peripheral, it is used - only by USB OTG FS peripheral. - - This function is added to ensure compatibility across platforms. - */ - - return HAL_OK; -} - - -#if defined (HAL_PCD_MODULE_ENABLED) -/** - * @brief Activate and configure an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t wEpRegVal; - - wEpRegVal = PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_T_MASK; - - /* initialize Endpoint */ - switch (ep->type) - { - case EP_TYPE_CTRL: - wEpRegVal |= USB_EP_CONTROL; - break; - - case EP_TYPE_BULK: - wEpRegVal |= USB_EP_BULK; - break; - - case EP_TYPE_INTR: - wEpRegVal |= USB_EP_INTERRUPT; - break; - - case EP_TYPE_ISOC: - wEpRegVal |= USB_EP_ISOCHRONOUS; - break; - - default: - ret = HAL_ERROR; - break; - } - - PCD_SET_ENDPOINT(USBx, ep->num, (wEpRegVal | USB_EP_VTRX | USB_EP_VTTX)); - - PCD_SET_EP_ADDRESS(USBx, ep->num, ep->num); - - if (ep->doublebuffer == 0U) - { - if (ep->is_in != 0U) - { - /*Set the endpoint Transmit buffer address */ - PCD_SET_EP_TX_ADDRESS(USBx, ep->num, ep->pmaadress); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /* Configure TX Endpoint to disabled state */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - } - else - { - /* Set the endpoint Receive buffer address */ - PCD_SET_EP_RX_ADDRESS(USBx, ep->num, ep->pmaadress); - - /* Set the endpoint Receive buffer counter */ - PCD_SET_EP_RX_CNT(USBx, ep->num, ep->maxpacket); - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - if (ep->num == 0U) - { - /* Configure VALID status for EP0 */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - else - { - /* Configure NAK status for OUT Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); - } - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - /* Double Buffer */ - else - { - if (ep->type == EP_TYPE_BULK) - { - /* Set bulk endpoint as double buffered */ - PCD_SET_BULK_EP_DBUF(USBx, ep->num); - } - else - { - /* Set the ISOC endpoint in double buffer mode */ - PCD_CLEAR_EP_KIND(USBx, ep->num); - } - - /* Set buffer address for double buffered mode */ - PCD_SET_EP_DBUF_ADDR(USBx, ep->num, ep->pmaaddr0, ep->pmaaddr1); - - if (ep->is_in == 0U) - { - /* Clear the data toggle bits for the endpoint IN/OUT */ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT */ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /* Configure TX Endpoint to disabled state */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - return ret; -} - -/** - * @brief De-activate and de-initialize an endpoint - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeactivateEndpoint(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) -{ - if (ep->doublebuffer == 0U) - { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Configure DISABLE status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure DISABLE status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - /* Double Buffer */ - else - { - if (ep->is_in == 0U) - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - /* Reset value of the data toggle bits for the endpoint out*/ - PCD_TX_DTOG(USBx, ep->num); - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - else - { - /* Clear the data toggle bits for the endpoint IN/OUT*/ - PCD_CLEAR_RX_DTOG(USBx, ep->num); - PCD_CLEAR_TX_DTOG(USBx, ep->num); - PCD_RX_DTOG(USBx, ep->num); - - /* Configure DISABLE status for the Endpoint*/ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - return HAL_OK; -} - -/** - * @brief USB_EPStartXfer setup and starts a transfer over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStartXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) -{ - uint32_t len; -#if (USE_USB_DOUBLE_BUFFER == 1U) - uint16_t pmabuffer; - uint16_t wEPVal; -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - /* IN endpoint */ - if (ep->is_in == 1U) - { - /*Multi packet transfer*/ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - } - else - { - len = ep->xfer_len; - } - - /* configure and validate Tx endpoint */ - if (ep->doublebuffer == 0U) - { - USB_WritePMA(USBx, ep->xfer_buff, ep->pmaadress, (uint16_t)len); - PCD_SET_EP_TX_CNT(USBx, ep->num, len); - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else - { - /* double buffer bulk management */ - if (ep->type == EP_TYPE_BULK) - { - if (ep->xfer_len_db > ep->maxpacket) - { - /* enable double buffer */ - PCD_SET_BULK_EP_DBUF(USBx, ep->num); - - /* each Time to write in PMA xfer_len_db will */ - ep->xfer_len_db -= len; - - /* Fill the two first buffer in the Buffer0 & Buffer1 */ - if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) - { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - ep->xfer_buff += len; - - if (ep->xfer_len_db > ep->maxpacket) - { - ep->xfer_len_db -= len; - } - else - { - len = ep->xfer_len_db; - ep->xfer_len_db = 0U; - } - - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - else - { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - ep->xfer_buff += len; - - if (ep->xfer_len_db > ep->maxpacket) - { - ep->xfer_len_db -= len; - } - else - { - len = ep->xfer_len_db; - ep->xfer_len_db = 0U; - } - - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - } - /* auto Switch to single buffer mode when transfer xfer_len_db; - - /* disable double buffer mode for Bulk endpoint */ - PCD_CLEAR_BULK_EP_DBUF(USBx, ep->num); - - /* Set Tx count with nbre of byte to be transmitted */ - PCD_SET_EP_TX_CNT(USBx, ep->num, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - } - else /* manage isochronous double buffer IN mode */ - { - /* each Time to write in PMA xfer_len_db will */ - ep->xfer_len_db -= len; - - /* Fill the data buffer */ - if ((PCD_GET_ENDPOINT(USBx, ep->num) & USB_EP_DTOG_TX) != 0U) - { - /* Set the Double buffer counter for pmabuffer1 */ - PCD_SET_EP_DBUF1_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr1; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - else - { - /* Set the Double buffer counter for pmabuffer0 */ - PCD_SET_EP_DBUF0_CNT(USBx, ep->num, ep->is_in, len); - pmabuffer = ep->pmaaddr0; - - /* Write the user buffer to USB PMA */ - USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); - } - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_VALID); - } - else /* OUT endpoint */ - { - if (ep->doublebuffer == 0U) - { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else - { - /* First Transfer Coming From HAL_PCD_EP_Receive & From ISR */ - /* Set the Double buffer counter */ - if (ep->type == EP_TYPE_BULK) - { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - - /* Coming from ISR */ - if (ep->xfer_count != 0U) - { - /* update last value to check if there is blocking state */ - wEPVal = (uint16_t)PCD_GET_ENDPOINT(USBx, ep->num); - - /*Blocking State */ - if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || - (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) - { - PCD_FREE_USER_BUFFER(USBx, ep->num, 0U); - } - } - } - /* iso out double */ - else if (ep->type == EP_TYPE_ISOC) - { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); - } - else - { - return HAL_ERROR; - } - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - - return HAL_OK; -} - - -/** - * @brief USB_EPSetStall set a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPSetStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) -{ - if (ep->is_in != 0U) - { - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_STALL); - } - else - { - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_STALL); - } - - return HAL_OK; -} - -/** - * @brief USB_EPClearStall Clear a stall condition over an EP - * @param USBx Selected device - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPClearStall(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) -{ - if (ep->doublebuffer == 0U) - { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); - - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else - { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); - } - } - - return HAL_OK; -} - -/** - * @brief USB_EPStoptXfer Stop transfer on an EP - * @param USBx usb device instance - * @param ep pointer to endpoint structure - * @retval HAL status - */ -HAL_StatusTypeDef USB_EPStopXfer(USB_DRD_TypeDef *USBx, USB_DRD_EPTypeDef *ep) -{ - /* IN endpoint */ - if (ep->is_in == 1U) - { - if (ep->doublebuffer == 0U) - { - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - else - { - /* Configure TX Endpoint to disabled state */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); - } - } - } - else /* OUT endpoint */ - { - if (ep->doublebuffer == 0U) - { - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_NAK); - } - else - { - /* Configure RX Endpoint to disabled state */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_DIS); - } - } - } - - return HAL_OK; -} -#endif /* defined (HAL_PCD_MODULE_ENABLED) */ - -/** - * @brief USB_StopDevice Stop the usb device mode - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_StopDevice(USB_DRD_TypeDef *USBx) -{ - /* disable all interrupts and force USB reset */ - USBx->CNTR = USB_CNTR_USBRST; - - /* clear interrupt status register */ - USBx->ISTR = 0U; - - /* switch-off device */ - USBx->CNTR = (USB_CNTR_USBRST | USB_CNTR_PDWN); - - return HAL_OK; -} - -/** - * @brief USB_SetDevAddress Stop the usb device mode - * @param USBx Selected device - * @param address new device address to be assigned - * This parameter can be a value from 0 to 255 - * @retval HAL status - */ -HAL_StatusTypeDef USB_SetDevAddress(USB_DRD_TypeDef *USBx, uint8_t address) -{ - if (address == 0U) - { - /* set device address and enable function */ - USBx->DADDR = USB_DADDR_EF; - } - - return HAL_OK; -} - -/** - * @brief USB_DevConnect Connect the USB device by enabling the pull-up/pull-down - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevConnect(USB_DRD_TypeDef *USBx) -{ - /* Enabling DP Pull-UP bit to Connect internal PU resistor on USB DP line */ - USBx->BCDR |= USB_BCDR_DPPU; - - return HAL_OK; -} - -/** - * @brief USB_DevDisconnect Disconnect the USB device by disabling the pull-up/pull-down - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DevDisconnect(USB_DRD_TypeDef *USBx) -{ - /* Disable DP Pull-Up bit to disconnect the Internal PU resistor on USB DP line */ - USBx->BCDR &= ~(USB_BCDR_DPPU); - - return HAL_OK; -} - -/** - * @brief USB_ReadInterrupts return the global USB interrupt status - * @param USBx Selected device - * @retval USB Global Interrupt status - */ -uint32_t USB_ReadInterrupts(USB_DRD_TypeDef const *USBx) -{ - uint32_t tmpreg; - - tmpreg = USBx->ISTR; - return tmpreg; -} - -/** - * @brief USB_ActivateRemoteWakeup : active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_ActivateRemoteWakeup(USB_DRD_TypeDef *USBx) -{ - USBx->CNTR |= USB_CNTR_L2RES; - - return HAL_OK; -} - -/** - * @brief USB_DeActivateRemoteWakeup de-active remote wakeup signalling - * @param USBx Selected device - * @retval HAL status - */ -HAL_StatusTypeDef USB_DeActivateRemoteWakeup(USB_DRD_TypeDef *USBx) -{ - USBx->CNTR &= ~USB_CNTR_L2RES; - - return HAL_OK; -} - -/** - * @brief Copy a buffer from user memory area to packet memory area (PMA) - * @param USBx USB peripheral instance register address. - * @param pbUsrBuf pointer to user memory area. - * @param wPMABufAddr address into PMA. - * @param wNBytes no. of bytes to be copied. - * @retval None - */ -void USB_WritePMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - UNUSED(USBx); - uint32_t WrVal; - uint32_t count; - __IO uint32_t *pdwVal; - uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U; - /* Due to the PMA access 32bit only so the last non word data should be processed alone */ - uint16_t remaining_bytes = wNBytes % 4U; - uint8_t *pBuf = pbUsrBuf; - - /* Check if there is a remaining byte */ - if (remaining_bytes != 0U) - { - NbWords--; - } - - /* Get the PMA Buffer pointer */ - pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr); - - /* Write the Calculated Word into the PMA related Buffer */ - for (count = NbWords; count != 0U; count--) - { - *pdwVal = __UNALIGNED_UINT32_READ(pBuf); - pdwVal++; - /* Increment pBuf 4 Time as Word Increment */ - pBuf++; - pBuf++; - pBuf++; - pBuf++; - } - - /* When Number of data is not word aligned, write the remaining Byte */ - if (remaining_bytes != 0U) - { - WrVal = 0U; - - do - { - WrVal |= (uint32_t)(*(uint8_t *)pBuf) << (8U * count); - count++; - pBuf++; - remaining_bytes--; - } while (remaining_bytes != 0U); - - *pdwVal = WrVal; - } -} - -/** - * @brief Copy data from packet memory area (PMA) to user memory buffer - * @param USBx USB peripheral instance register address. - * @param pbUsrBuf pointer to user memory area. - * @param wPMABufAddr address into PMA. - * @param wNBytes no. of bytes to be copied. - * @retval None - */ -void USB_ReadPMA(USB_DRD_TypeDef const *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes) -{ - UNUSED(USBx); - uint32_t count; - uint32_t RdVal; - __IO uint32_t *pdwVal; - uint32_t NbWords = ((uint32_t)wNBytes + 3U) >> 2U; - /*Due to the PMA access 32bit only so the last non word data should be processed alone */ - uint16_t remaining_bytes = wNBytes % 4U; - uint8_t *pBuf = pbUsrBuf; - - /* Get the PMA Buffer pointer */ - pdwVal = (__IO uint32_t *)(USB_DRD_PMAADDR + (uint32_t)wPMABufAddr); - - /* if nbre of byte is not word aligned decrement the nbre of word*/ - if (remaining_bytes != 0U) - { - NbWords--; - } - - /*Read the Calculated Word From the PMA related Buffer*/ - for (count = NbWords; count != 0U; count--) - { - __UNALIGNED_UINT32_WRITE(pBuf, *pdwVal); - - pdwVal++; - pBuf++; - pBuf++; - pBuf++; - pBuf++; - } - - /*When Number of data is not word aligned, read the remaining byte*/ - if (remaining_bytes != 0U) - { - RdVal = *(__IO uint32_t *)pdwVal; - - do - { - *(uint8_t *)pBuf = (uint8_t)(RdVal >> (8U * (uint8_t)(count))); - count++; - pBuf++; - remaining_bytes--; - } while (remaining_bytes != 0U); - } -} - - -/*------------------------------------------------------------------------*/ -/* HOST API */ -/*------------------------------------------------------------------------*/ - -/** - * @brief USB_HostInit Initializes the USB DRD controller registers - * for Host mode - * @param USBx Selected device - * @param cfg pointer to a USB_DRD_CfgTypeDef structure that contains - * the configuration information for the specified USBx peripheral. - * @retval HAL status - */ -HAL_StatusTypeDef USB_HostInit(USB_DRD_TypeDef *USBx, USB_DRD_CfgTypeDef cfg) -{ - UNUSED(cfg); - - /* Clear All Pending Interrupt */ - USBx->ISTR = 0U; - - /* Disable all interrupts */ - USBx->CNTR &= ~(USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | - USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | - USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); - - /* Clear All Pending Interrupt */ - USBx->ISTR = 0U; - - /* Set the PullDown on the PHY */ - USBx->BCDR |= USB_BCDR_DPPD; - - /* Enable Global interrupt */ - USBx->CNTR |= (USB_CNTR_CTRM | USB_CNTR_PMAOVRM | USB_CNTR_ERRM | - USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_DCON | - USB_CNTR_SOFM | USB_CNTR_ESOFM | USB_CNTR_L1REQM); - - return HAL_OK; -} - - -/** - * @brief USB_DRD_ResetPort : Reset Host Port - * @param USBx Selected device - * @retval HAL status - * @note (1)The application must wait at least 10 ms - * before clearing the reset bit. - */ -HAL_StatusTypeDef USB_ResetPort(USB_DRD_TypeDef *USBx) -{ - /* Force USB Reset */ - USBx->CNTR |= USB_CNTR_USBRST; - HAL_Delay(100); - /* Release USB Reset */ - USBx->CNTR &= ~USB_CNTR_USBRST; - HAL_Delay(30); - - return HAL_OK; -} - -/** - * @brief Return Host Core speed - * @param USBx Selected device - * @retval speed Host speed - * This parameter can be one of these values - * @arg USB_DRD_SPEED_FS Full speed mode - * @arg USB_DRD_SPEED_LS Low speed mode - */ -uint32_t USB_GetHostSpeed(USB_DRD_TypeDef const *USBx) -{ - if ((USBx->ISTR & USB_ISTR_LS_DCONN) != 0U) - { - return USB_DRD_SPEED_LS; - } - else - { - return USB_DRD_SPEED_FS; - } -} - -/** - * @brief Return Host Current Frame number - * @param USBx Selected device - * @retval current frame number - */ -uint32_t USB_GetCurrentFrame(USB_DRD_TypeDef const *USBx) -{ - return USBx->FNR & 0x7FFU; -} - -/** - * @brief Set the channel Kind (Single/double buffer mode) - * @param USBx Selected device - * @param phy_ch_num Selected device - * @param db_state double state can be USB_DRD_XXX_DBUFF_ENBALE/USB_DRD_XXX_DBUFF_DISABLE - * @retval HAL status - */ -HAL_StatusTypeDef USB_HC_DoubleBuffer(USB_DRD_TypeDef *USBx, - uint8_t phy_ch_num, uint8_t db_state) -{ - uint32_t tmp; - - if ((db_state == USB_DRD_BULK_DBUFF_ENBALE) || (db_state == USB_DRD_ISOC_DBUFF_DISABLE)) - { - tmp = (USB_DRD_GET_CHEP(USBx, phy_ch_num) | USB_CH_KIND) & USB_CHEP_DB_MSK; - } - else - { - tmp = USB_DRD_GET_CHEP(USBx, phy_ch_num) & (~USB_CH_KIND) & USB_CHEP_DB_MSK; - } - - /* Set the device speed in case using HUB FS with device LS */ - USB_DRD_SET_CHEP(USBx, phy_ch_num, tmp); - - return HAL_OK; -} - -/** - * @brief Initialize a host channel - * @param USBx Selected device - * @param phy_ch_num Channel number - * This parameter can be a value from 1 to 15 - * @param epnum Endpoint number - * This parameter can be a value from 1 to 15 - * @param dev_address Current device address - * This parameter can be a value from 0 to 255 - * @param speed Current device speed - * This parameter can be one of these values: - * @arg USB_DRD_SPEED_FULL Full speed mode - * @arg USB_DRD_SPEED_LOW Low speed mode - * @param ep_type Endpoint Type - * This parameter can be one of these values: - * @arg EP_TYPE_CTRL Control type - * @arg EP_TYPE_ISOC Isochronous type - * @arg EP_TYPE_BULK Bulk type - * @arg EP_TYPE_INTR Interrupt type - * @param mps Max Packet Size - * This parameter can be a value from 0 to 32K - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_Init(USB_DRD_TypeDef *USBx, uint8_t phy_ch_num, - uint8_t epnum, uint8_t dev_address, uint8_t speed, - uint8_t ep_type, uint16_t mps) -{ - HAL_StatusTypeDef ret = HAL_OK; - uint32_t wChRegVal; - uint32_t HostCoreSpeed; - - UNUSED(mps); - - wChRegVal = USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_T_MASK; - - /* Initialize host Channel */ - switch (ep_type) - { - case EP_TYPE_CTRL: - wChRegVal |= USB_EP_CONTROL; - break; - - case EP_TYPE_BULK: - wChRegVal |= USB_EP_BULK; - break; - - case EP_TYPE_INTR: - wChRegVal |= USB_EP_INTERRUPT; - break; - - case EP_TYPE_ISOC: - wChRegVal |= USB_EP_ISOCHRONOUS; - break; - - default: - ret = HAL_ERROR; - break; - } - - /* Clear device address, Endpoint number and Low Speed Endpoint fields */ - wChRegVal &= ~(USB_CHEP_DEVADDR | USB_CHEP_ADDR | USB_CHEP_LSEP); - - /* Set device address and Endpoint number associated to the channel */ - wChRegVal |= (((uint32_t)dev_address << USB_CHEP_DEVADDR_Pos) | - ((uint32_t)epnum & 0x0FU)); - - /* Get Host core Speed */ - HostCoreSpeed = USB_GetHostSpeed(USBx); - - /* Set the device speed in case using HUB FS with device LS */ - if ((speed == USB_DRD_SPEED_LS) && (HostCoreSpeed == USB_DRD_SPEED_FS)) - { - wChRegVal |= USB_CHEP_LSEP; - } - - /* Update the channel register value */ - USB_DRD_SET_CHEP(USBx, phy_ch_num, (wChRegVal | USB_CH_VTRX | USB_CH_VTTX)); - - return ret; -} - -/** - * @brief Start a transfer over a host channel - * @param USBx Selected device - * @param hc pointer to host channel structure - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_StartXfer(USB_DRD_TypeDef *USBx, USB_DRD_HCTypeDef *hc) -{ - uint32_t len; - uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; -#if (USE_USB_DOUBLE_BUFFER == 1U) - uint32_t ch_reg = USB_DRD_GET_CHEP(USBx, phy_ch_num); -#endif /* USE_USB_DOUBLE_BUFFER */ - - if (hc->ch_dir == CH_IN_DIR) /* In Channel */ - { - /* Multi packet transfer */ - if (hc->xfer_len > hc->max_packet) - { - len = hc->max_packet; - } - else - { - len = hc->xfer_len; - } - - if (hc->doublebuffer == 0U) - { - /* Set RX buffer count */ - USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else if (hc->ep_type == EP_TYPE_BULK) - { - /* Double buffer activated */ - if ((hc->xfer_len > hc->max_packet)) - { - (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); - - /* Set the Double buffer counter */ - USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); - USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); - } - else /* Switch to single buffer mode */ - { - (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); - - /* Set RX buffer count */ - USB_DRD_SET_CHEP_RX_CNT(USBx, phy_ch_num, len); - } - } - else /* Isochronous */ - { - /* Set the Double buffer counter */ - USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 0U, len); - USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 0U, len); - } -#endif /* USE_USB_DOUBLE_BUFFER */ - - /* Enable host channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch_num, USB_CH_RX_VALID); - } - else /* Out Channel */ - { - /* Multi packet transfer */ - if (hc->xfer_len > hc->max_packet) - { - len = hc->max_packet; - } - else - { - len = hc->xfer_len; - } - - /* Configure and validate Tx endpoint */ - if (hc->doublebuffer == 0U) - { - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaadress, (uint16_t)len); - USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)len); - - /* SET PID SETUP */ - if ((hc->data_pid) == HC_PID_SETUP) - { - USB_DRD_CHEP_TX_SETUP(USBx, phy_ch_num); - } - } -#if (USE_USB_DOUBLE_BUFFER == 1U) - else if (hc->ep_type == EP_TYPE_BULK) - { - (void)USB_HC_BULK_DB_StartXfer(USBx, hc, ch_reg, &len); - } - else - { - (void)USB_HC_ISO_DB_StartXfer(USBx, hc, len); - } -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - /* Enable host channel */ - USB_DRD_SET_CHEP_TX_STATUS(USBx, hc->phy_ch_num, USB_CH_TX_VALID); - } - - return HAL_OK; -} - -#if (USE_USB_DOUBLE_BUFFER == 1U) -/** - * @brief Start Transfer of Channel isochronous out double buffer - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @param len Transfer Length - * @retval HAL state - */ -static HAL_StatusTypeDef USB_HC_ISO_DB_StartXfer(USB_DRD_TypeDef *USBx, - USB_DRD_HCTypeDef *hc, - uint32_t len) -{ - uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; - - /* check the DTOG_TX to determine in which buffer we should write */ - if ((USB_DRD_GET_CHEP(USBx, phy_ch_num) & USB_CH_DTOG_TX) != 0U) - { - USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, len); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)len); - } - else - { - /* DTOGTX=0 */ - /* Set the Double buffer counter for pmabuffer0 */ - USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, len); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)len); - } - - return HAL_OK; -} - -/** - * @brief Start Transfer of Channel bulk out double buffer - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @param ch_reg snapshot of the CHEPR register - * @param len Transfer Length - * @retval HAL state - */ -static HAL_StatusTypeDef USB_HC_BULK_DB_StartXfer(USB_DRD_TypeDef *USBx, - USB_DRD_HCTypeDef *hc, - uint32_t ch_reg, - uint32_t *len) -{ - uint32_t phy_ch_num = (uint32_t)hc->phy_ch_num; - - /* -Double Buffer Mangement- */ - if (hc->xfer_len_db > hc->max_packet) - { - /* enable double buffer mode */ - (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_ENBALE); - *len = hc->max_packet; - hc->xfer_len_db -= *len; - - /* Prepare two buffer before enabling host */ - if ((ch_reg & USB_CH_DTOG_TX) == 0U) - { - /* Write Buffer0 */ - USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); - } - else - { - /* Write Buffer1 */ - USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len); - } - - hc->xfer_buff += *len; - - /* Multi packet transfer */ - if (hc->xfer_len_db > hc->max_packet) - { - hc->xfer_len_db -= *len; - } - else - { - *len = hc->xfer_len_db; - hc->xfer_len_db = 0U; - } - - if ((ch_reg & USB_CH_DTOG_TX) == 0U) - { - /* Write Buffer1 */ - USB_DRD_SET_CHEP_DBUF1_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr1, (uint16_t)*len); - } - else - { - /* Write Buffer0 */ - USB_DRD_SET_CHEP_DBUF0_CNT(USBx, phy_ch_num, 1U, (uint16_t)*len); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); - } - } - else - { - /* Disable bulk double buffer mode */ - (void)USB_HC_DoubleBuffer(USBx, (uint8_t)phy_ch_num, USB_DRD_BULK_DBUFF_DISABLE); - USB_WritePMA(USBx, hc->xfer_buff, hc->pmaaddr0, (uint16_t)*len); - USB_DRD_SET_CHEP_TX_CNT(USBx, phy_ch_num, (uint16_t)*len); - } - - return HAL_OK; -} -#endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - - -/** - * @brief Halt a host channel in - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_IN_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) -{ - /* Set disable to Channel */ - USB_DRD_SET_CHEP_RX_STATUS(USBx, phy_ch, USB_CH_RX_DIS); - - return HAL_OK; -} - - -/** - * @brief Halt a host channel out - * @param USBx Selected device - * @param hc_num Host Channel number - * This parameter can be a value from 1 to 15 - * @retval HAL state - */ -HAL_StatusTypeDef USB_HC_OUT_Halt(USB_DRD_TypeDef *USBx, uint8_t phy_ch) -{ - /* Set disable to Channel */ - USB_DRD_SET_CHEP_TX_STATUS(USBx, phy_ch, USB_CH_TX_DIS); - - return HAL_OK; -} - -/** - * @brief Stop Host Core - * @param USBx Selected device - * @retval HAL state - */ -HAL_StatusTypeDef USB_StopHost(USB_DRD_TypeDef *USBx) -{ - USBx->ISTR &= ~(USB_ISTR_DIR | USB_ISTR_L1REQ | - USB_ISTR_ESOF | USB_ISTR_SOF | - USB_ISTR_RESET | USB_ISTR_DCON | - USB_ISTR_SUSP | USB_ISTR_WKUP | - USB_ISTR_ERR | USB_ISTR_PMAOVR | - USB_ISTR_CTR); - - /* Set PowerDown */ - USBx->CNTR |= USB_CNTR_PDWN; - - /* Force a Reset */ - USBx->CNTR |= USB_CNTR_USBRST; - - return HAL_OK; -} -#endif /* defined (USB_DRD_FS) */ -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (USB_OTG_FS) || defined (USB_OTG_HS) || defined (USB_DRD_FS) */ -#endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */ - -/** - * @} - */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c deleted file mode 100644 index b1356c435..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Drivers/STM32U5xx_HAL_Driver/Src/stm32u5xx_ll_utils.c +++ /dev/null @@ -1,867 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_ll_utils.c - * @author MCD Application Team - * @brief UTILS LL module driver. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_ll_utils.h" -#include "stm32u5xx_ll_rcc.h" -#include "stm32u5xx_ll_system.h" -#include "stm32u5xx_ll_pwr.h" -#include -#ifdef USE_FULL_ASSERT -#include "stm32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup STM32U5xx_LL_Driver - * @{ - */ - -/** @addtogroup UTILS_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Constants - * @{ - */ -#define UTILS_MAX_FREQUENCY_SCALE0 160000000U /*!< Maximum frequency for system clock at power scale0, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE1 110000000U /*!< Maximum frequency for system clock at power scale1, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE2 55000000U /*!< Maximum frequency for system clock at power scale2, in Hz */ -#define UTILS_MAX_FREQUENCY_SCALE3 25000000U /*!< Maximum frequency for system clock at power scale3, in Hz */ - -/* Defines used for PLL range */ -#define UTILS_PLLVCO_INPUT_MIN 4000000U /*!< Frequency min for PLLVCO input, in Hz */ -#define UTILS_PLLVCO_INPUT_MAX 16000000U /*!< Frequency max for PLLVCO input, in Hz */ -#define UTILS_PLLVCO_OUTPUT_MIN 64000000U /*!< Frequency min for PLLVCO output, in Hz */ -#define UTILS_PLLVCO_OUTPUT_MAX 344000000U /*!< Frequency max for PLLVCO output, in Hz */ - -/* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX 50000000U /*!< Frequency max for HSE frequency, in Hz */ - -/* Defines used for FLASH latency according to HCLK Frequency */ -#define UTILS_SCALE1_LATENCY0_FREQ (32000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 1 */ -#define UTILS_SCALE1_LATENCY1_FREQ (64000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ -#define UTILS_SCALE1_LATENCY2_FREQ (96000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ -#define UTILS_SCALE1_LATENCY3_FREQ (128000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 1 */ -#define UTILS_SCALE1_LATENCY4_FREQ (160000000U) /*!< HCLK frequency to set FLASH latency 4 in power scale 1 */ -#define UTILS_SCALE2_LATENCY0_FREQ (25000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 2 */ -#define UTILS_SCALE2_LATENCY1_FREQ (50000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 2 */ -#define UTILS_SCALE2_LATENCY2_FREQ (75000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 2 */ -#define UTILS_SCALE2_LATENCY3_FREQ (100000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 2 */ -#define UTILS_SCALE3_LATENCY0_FREQ (12500000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 3 */ -#define UTILS_SCALE3_LATENCY1_FREQ (25000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 3 */ -#define UTILS_SCALE3_LATENCY2_FREQ (37500000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 3 */ -#define UTILS_SCALE3_LATENCY3_FREQ (50000000U) /*!< HCLK frequency to set FLASH latency 3 in power scale 3 */ -#define UTILS_SCALE4_LATENCY0_FREQ (8000000U) /*!< HCLK frequency to set FLASH latency 0 in power scale 4 */ -#define UTILS_SCALE4_LATENCY1_FREQ (16000000U) /*!< HCLK frequency to set FLASH latency 1 in power scale 4 */ -#define UTILS_SCALE4_LATENCY2_FREQ (24000000U) /*!< HCLK frequency to set FLASH latency 2 in power scale 4 */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Macros - * @{ - */ -#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) - -#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_16)) - -#define IS_LL_UTILS_APB2_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB2_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB2_DIV_16)) - -#define IS_LL_UTILS_APB3_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB3_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB3_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB3_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB3_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB3_DIV_16)) - -#define IS_LL_UTILS_PLLM_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 16U)) - -#define IS_LL_UTILS_PLLN_VALUE(__VALUE__) ((4U <= (__VALUE__)) && ((__VALUE__) <= 512U)) - -#define IS_LL_UTILS_PLLR_VALUE(__VALUE__) ((1U <= (__VALUE__)) && ((__VALUE__) <= 128U)) - -#define IS_LL_UTILS_PLLVCO_INPUT(__VALUE__) ((UTILS_PLLVCO_INPUT_MIN <= (__VALUE__))\ - && ((__VALUE__) <= UTILS_PLLVCO_INPUT_MAX)) - -#define IS_LL_UTILS_PLLVCO_OUTPUT(__VALUE__) ((UTILS_PLLVCO_OUTPUT_MIN <= (__VALUE__))\ - && ((__VALUE__) <= UTILS_PLLVCO_OUTPUT_MAX)) - -#define IS_LL_UTILS_PLL_FREQUENCY(__VALUE__) ((LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE4) ? \ - ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE0) : \ - (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) ? \ - ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE1) : \ - (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) ? \ - ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE2) : \ - ((__VALUE__) <= UTILS_MAX_FREQUENCY_SCALE3)) - -#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ - || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) - -#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN)\ - && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup UTILS_LL_Private_Functions UTILS Private functions - * @{ - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); -static ErrorStatus UTILS_PLL_IsBusy(void); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Exported_Functions - * @{ - */ - -/** @addtogroup UTILS_LL_EF_DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK - * as SysTick clock source. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param HCLKFrequency HCLK frequency in Hz - * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq - * @retval None - */ -void LL_Init1msTick(uint32_t HCLKFrequency) -{ - /* Use frequency provided in argument */ - LL_InitTick(HCLKFrequency, 1000U); -} - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base with HCLK/8 - * as SysTick clock source. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param HCLKFrequency HCLK frequency in Hz - * @retval None - */ -void LL_Init1msTick_HCLK_Div8(uint32_t HCLKFrequency) -{ - /* Configure the SysTick to have 1ms time base with HCLK/8 as SysTick clock source */ - SysTick->LOAD = (uint32_t)((HCLKFrequency / 8000U) - 1UL); - SysTick->VAL = 0UL; - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; -} - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSE as SysTick clock source. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * LSESYS needs to be enabled to get LSE working as SysTick clock source. - * @retval None - */ -void LL_Init1msTick_LSE(void) -{ - /* Configure the SysTick to have 1ms time base with LSE as SysTick clock source */ - SysTick->LOAD = (uint32_t)((LSE_VALUE / 1000U) - 1UL); - SysTick->VAL = 0UL; - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; -} - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base with LSI as SysTick clock source. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @retval None - */ -void LL_Init1msTick_LSI(void) -{ - /* Configure the SysTick to have 1ms time base with LSI as SysTick clock source */ - SysTick->LOAD = (uint32_t)((LSI_VALUE / 1000U) - 1UL); - SysTick->VAL = 0UL; - SysTick->CTRL = SysTick_CTRL_ENABLE_Msk; -} - -/** - * @brief This function provides minimum delay (in milliseconds) based - * on SysTick counter flag - * @note When a RTOS is used, it is recommended to avoid using blocking delay - * and use rather osDelay service. - * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which - * will configure Systick to 1ms - * @param Delay specifies the minimum delay time length, in milliseconds. - * @retval None - */ - -void LL_mDelay(uint32_t Delay) -{ - __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ - uint32_t tmpDelay = Delay; - - /* Add this code to indicate that local variable is not used */ - ((void)tmp); - - /* Add a period to guaranty minimum wait */ - if (tmpDelay < LL_MAX_DELAY) - { - tmpDelay++; - } - - while (tmpDelay != 0U) - { - if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) - { - tmpDelay--; - } - } -} - -/** - * @} - */ - -/** @addtogroup UTILS_EF_SYSTEM - * @brief System Configuration functions - * - @verbatim - =============================================================================== - ##### System Configuration functions ##### - =============================================================================== - [..] - System, AHB and APB buses clocks configuration - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 and PCLK2, PCLK3 is - 160000000 Hz. - @endverbatim - @internal - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - - (++) Table 1. HCLK clock frequency for STM32U5 devices - (++) +-----------------------------------------------------------------------------------------------+ - (++) | Latency | HCLK clock frequency (MHz) | - (++) | |-----------------------------------------------------------------------------| - (++) | | voltage range 1 | voltage range 2 | voltage range 3 | voltage range 4 | - (++) | | 1.2 V | 1.1 V | 1.0 V | 0.9 V | - (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |0WS(1 CPU cycles)| 0 < HCLK <= 32 | 0 < HCLK <= 25 | 0 < HCLK <= 12.5| 0 < HCLK <= 8 | - (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |1WS(2 CPU cycles)| 32 < HCLK <= 64 | 25 < HCLK <= 50 | 12.5 < HCLK <= 25| 0 < HCLK <= 16 | - (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |2WS(3 CPU cycles)| 64 < HCLK <= 96 | 50 < HCLK <= 75 | 25 < HCLK <= 37.5| 0 < HCLK <= 24 | - (++) |-----------------|-------------------|------------------|------------------|-------------------| - (++) |3WS(4 CPU cycles)| 96 < HCLK <= 128 | 75 < HCLK <= 100| 37.5 < HCLK <= 50| | - (++) |-----------------|-------------------|------------------|------------------| | - (++) |4WS(5 CPU cycles)| 128 < HCLK <= 160| | | | - (++) +-----------------+-------------------+------------------+------------------+-------------------+ - - @endinternal - * @{ - */ - -/** - * @brief This function sets directly SystemCoreClock CMSIS variable. - * @note Variable can be calculated also through SystemCoreClockUpdate function. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @retval None - */ -void LL_SetSystemCoreClock(uint32_t HCLKFrequency) -{ - /* HCLK clock frequency */ - SystemCoreClock = HCLKFrequency; -} - -/** - * @brief Update number of Flash wait states in line with new frequency and current - voltage range. - * @param HCLK_Frequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -ErrorStatus LL_SetFlashLatency(uint32_t HCLK_Frequency) -{ - ErrorStatus status = SUCCESS; - uint32_t timeout; - uint32_t getlatency; - uint32_t latency = LL_FLASH_LATENCY_0; /* default value 0WS */ - - /* Frequency cannot be equal to 0 */ - if (HCLK_Frequency == 0U) - { - status = ERROR; - } - else - { - if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE1) - { - if (HCLK_Frequency <= UTILS_SCALE1_LATENCY0_FREQ) - { - /* 0 < HCLK <= 32 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ - } - else if ((HCLK_Frequency <= UTILS_SCALE1_LATENCY1_FREQ)) - { - /* 32 < HCLK <=64 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY2_FREQ) - { - /* 64 < HCLK <= 96 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY3_FREQ) - { - /* 96 < HCLK <= 128 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else if (HCLK_Frequency <= UTILS_SCALE1_LATENCY4_FREQ) - { - /* 128 < HCLK <= 160 => 4WS (5 CPU cycles) */ - latency = LL_FLASH_LATENCY_4; - } - else - { - status = ERROR; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } - else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE2) - { - if (HCLK_Frequency <= UTILS_SCALE2_LATENCY0_FREQ) - { - /* 0 < HCLK <= 25 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ - } - else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY1_FREQ) - { - /* 25 < HCLK <= 50 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY2_FREQ) - { - /* 50 < HCLK <= 75 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else if (HCLK_Frequency <= UTILS_SCALE2_LATENCY3_FREQ) - { - /* 75 < HCLK <= 100 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else - { - status = ERROR; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } - else if (LL_PWR_GetRegulVoltageScaling() == LL_PWR_REGU_VOLTAGE_SCALE3) - { - if (HCLK_Frequency <= UTILS_SCALE3_LATENCY0_FREQ) - { - /* 0 < HCLK <= 12.5 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ - } - else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY1_FREQ) - { - /* 12.5 < HCLK <= 25 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY2_FREQ) - { - /* 25 < HCLK <= 37.5 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else if (HCLK_Frequency <= UTILS_SCALE3_LATENCY3_FREQ) - { - /* 37.5 < HCLK <= 50 => 3WS (4 CPU cycles) */ - latency = LL_FLASH_LATENCY_3; - } - else - { - status = ERROR; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } - else - { - if (HCLK_Frequency <= UTILS_SCALE4_LATENCY0_FREQ) - { - /* 0 < HCLK <= 8 => 0WS (1 CPU cycles) : Do nothing, keep latency to default LL_FLASH_LATENCY_0 */ - } - else if (HCLK_Frequency <= UTILS_SCALE4_LATENCY1_FREQ) - { - /* 8 < HCLK <= 16 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - else if (HCLK_Frequency <= UTILS_SCALE4_LATENCY2_FREQ) - { - /* 16 < HCLK <= 24 => 2WS (3 CPU cycles) */ - latency = LL_FLASH_LATENCY_2; - } - else - { - status = ERROR; - } - /* else HCLK_Frequency <= 10MHz default LL_FLASH_LATENCY_0 0WS */ - } - } - - if (status == SUCCESS) - { - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - timeout = 2; - do - { - /* Wait for Flash latency to be updated */ - getlatency = LL_FLASH_GetLatency(); - timeout--; - } while ((getlatency != latency) && (timeout > 0U)); - - if (getlatency != latency) - { - status = ERROR; - } - } - - return status; -} - -/** - * @brief This function configures system clock with MSI as clock source of the PLL - * @note The application needs to ensure that PLL1, PLL2 and/or PLL3 are disabled. - * @note Function is based on the following formula: - * - PLL1 output frequency = (((MSI frequency / PLL1M) * PLL1N) / PLL1R) - * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = MSI frequency / PLL1M) - * - PLL1N: ensure that the VCO output frequency is between 4 and 512 MHz - (PLL1VCO_output = PLL1VCO_input * PLL1N) - * - PLL1R: ensure that max frequency at 160 MHz is reached (PLL1VCO_output / PLL1R) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL1. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_MSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t pllfreq; - uint32_t msi_range; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Get the current MSI range */ - if (LL_RCC_MSI_IsEnabledRangeSelect() != 0U) - { - msi_range = LL_RCC_MSIS_GetRange(); - switch (msi_range) - { - case LL_RCC_MSISRANGE_15: /* MSI = 100 kHz */ - case LL_RCC_MSISRANGE_14: /* MSI = 150 kHz */ - case LL_RCC_MSISRANGE_13: /* MSI = 200 kHz */ - case LL_RCC_MSISRANGE_12: /* MSI = 400 kHz */ - case LL_RCC_MSISRANGE_11: /* MSI = 768 kHz */ - case LL_RCC_MSISRANGE_10: /* MSI = 1.024 MHz*/ - case LL_RCC_MSISRANGE_9: /* MSI = 1.536 MHz*/ - case LL_RCC_MSISRANGE_8: /* MSI = 3.072 MHz*/ - case LL_RCC_MSISRANGE_7: /* MSI = 1 MHz */ - case LL_RCC_MSISRANGE_6: /* MSI = 1.5 MHz */ - case LL_RCC_MSISRANGE_5: /* MSI = 2 MHz */ - /* PLLVCO input frequency is less then 4 MHz*/ - status = ERROR; - break; - - case LL_RCC_MSISRANGE_0: /* MSI = 48 MHz */ - case LL_RCC_MSISRANGE_1: /* MSI = 24 MHz */ - case LL_RCC_MSISRANGE_2: /* MSI = 16 MHz */ - case LL_RCC_MSISRANGE_3: /* MSI = 12 MHz */ - case LL_RCC_MSISRANGE_4: /* MSI = 4 MHz */ - default: - break; - } - } - else - { - msi_range = LL_RCC_MSIS_GetRangeAfterStandby(); - switch (msi_range) - { - case LL_RCC_MSISSRANGE_5: /* MSI = 2 MHz */ - case LL_RCC_MSISSRANGE_6: /* MSI = 1.5 MHz */ - case LL_RCC_MSISSRANGE_7: /* MSI = 1 MHz */ - case LL_RCC_MSISSRANGE_8: /* MSI = 3.072 MHz*/ - /* PLLVCO input frequency is less then 4 MHz */ - status = ERROR; - break; - - case LL_RCC_MSISSRANGE_4: /* MSI = 4 MHz */ - default: - break; - } - } - - /* Main PLL configuration and activation */ - if (status != ERROR) - { - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(__LL_RCC_CALC_MSIS_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), msi_range), - UTILS_PLLInitStruct); - - /* Enable MSI if not enabled */ - if (LL_RCC_MSIS_IsReady() != 1U) - { - LL_RCC_MSIS_Enable(); - while ((LL_RCC_MSIS_IsReady() != 1U)) - { - /* Wait for MSI ready */ - } - } - - /* Configure PLL1 */ - LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_MSIS, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, - UTILS_PLLInitStruct->PLLR); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - - } - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief This function configures system clock at maximum frequency with HSI as clock source of the PLL - * @note The application need to ensure that PLL1, PLL2 and/or PLL3 are disabled. - * @note Function is based on the following formula: - * - PLL output frequency = (((HSI frequency / PLLM) * PLLN) / PLLR) - * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = MSI frequency / PLL1M) - * - PLL1N: ensure that the VCO output frequency is between 4 and 512 MHz - (PLL1VCO_output = PLL1VCO_input * PLL1N) - * - PLL1R: ensure that max frequency at 160 MHz is reached (PLL1VCO_output / PLL1R) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status; - uint32_t pllfreq; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSI_VALUE, UTILS_PLLInitStruct); - - /* Enable HSI if not enabled */ - if (LL_RCC_HSI_IsReady() != 1U) - { - LL_RCC_HSI_Enable(); - while (LL_RCC_HSI_IsReady() != 1U) - { - /* Wait for HSI ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSI, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, - UTILS_PLLInitStruct->PLLR); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief This function configures system clock with HSE as clock source of the PLL - * @note The application need to ensure that PLL, PLLSAI1 and/or PLLSAI2 are disabled. - * @note Function is based on the following formula: - * - PLL output frequency = (((HSE frequency / PLLM) * PLLN) / PLLR) - * - PLL1M: ensure that the VCO input frequency ranges from 1 to 16 MHz (PLL1VCO_input = MSI frequency / PLL1M) - * - PLL1N: ensure that the VCO output frequency is between 4 and 512 MHz - (PLL1VCO_output = PLL1VCO_input * PLL1N) - * - PLL1R: ensure that max frequency at 160 MHz is reached (PLL1VCO_output / PLL1R) - * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 50000000 - * @param HSEBypass This parameter can be one of the following values: - * @arg @ref LL_UTILS_HSEBYPASS_ON - * @arg @ref LL_UTILS_HSEBYPASS_OFF - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status; - uint32_t pllfreq; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); - assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Calculate the new PLL output frequency */ - pllfreq = UTILS_GetPLLOutputFrequency(HSEFrequency, UTILS_PLLInitStruct); - - /* Enable HSE if not enabled */ - if (LL_RCC_HSE_IsReady() != 1U) - { - /* Check if need to enable HSE bypass feature or not */ - if (HSEBypass == LL_UTILS_HSEBYPASS_ON) - { - LL_RCC_HSE_EnableBypass(); - } - else - { - LL_RCC_HSE_DisableBypass(); - } - - /* Enable HSE */ - LL_RCC_HSE_Enable(); - while (LL_RCC_HSE_IsReady() != 1U) - { - /* Wait for HSE ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL1_ConfigDomain_SYS(LL_RCC_PLL1SOURCE_HSE, UTILS_PLLInitStruct->PLLM, UTILS_PLLInitStruct->PLLN, - UTILS_PLLInitStruct->PLLR); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup UTILS_LL_Private_Functions - * @{ - */ - -/** - * @brief Function to check that PLL can be modified - * @param PLL_InputFrequency PLL input frequency (in Hz) - * @param UTILS_PLLInitStruct pointer to a @ref LL_UTILS_PLLInitTypeDef structure that contains - * the configuration information for the PLL. - * @retval PLL output frequency (in Hz) - */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) -{ - uint32_t pllfreq; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_PLLM_VALUE(UTILS_PLLInitStruct->PLLM)); - assert_param(IS_LL_UTILS_PLLN_VALUE(UTILS_PLLInitStruct->PLLN)); - assert_param(IS_LL_UTILS_PLLR_VALUE(UTILS_PLLInitStruct->PLLR)); - - /* Check different PLL parameters according to RM */ - /* - PLLM: ensure that the VCO input frequency ranges from 1 to 16 MHz. */ - pllfreq = PLL_InputFrequency / (UTILS_PLLInitStruct->PLLM); - assert_param(IS_LL_UTILS_PLLVCO_INPUT(pllfreq)); - - /* - PLLN: ensure that the VCO output frequency is between 4 and 512 MHz.*/ - pllfreq = pllfreq * (UTILS_PLLInitStruct->PLLN); - assert_param(IS_LL_UTILS_PLLVCO_OUTPUT(pllfreq)); - - /* - PLLR: ensure that max frequency at 160 MHz is reached */ - pllfreq = pllfreq / (UTILS_PLLInitStruct->PLLR); - assert_param(IS_LL_UTILS_PLL_FREQUENCY(pllfreq)); - - return pllfreq; -} - -/** - * @brief Function to check that PLL can be modified - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLL modification can be done - * - ERROR: PLL is busy - */ -static ErrorStatus UTILS_PLL_IsBusy(void) -{ - ErrorStatus status = SUCCESS; - - /* Check if PLL1 is busy*/ - if (LL_RCC_PLL1_IsReady() != 0U) - { - /* PLL configuration cannot be modified */ - status = ERROR; - } - - /* Check if PLL2 is busy*/ - if (LL_RCC_PLL2_IsReady() != 0U) - { - /* PLL2 configuration cannot be modified */ - status = ERROR; - } - - /* Check if PLL3 is busy*/ - if (LL_RCC_PLL3_IsReady() != 0U) - { - /* PLL3 configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief Function to enable PLL and switch system clock to PLL - * @param SYSCLK_Frequency SYSCLK frequency - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: No problem to switch system to PLL - * - ERROR: Problem to switch system to PLL - */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, - LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t hclk_frequency; - - assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); - assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); - assert_param(IS_LL_UTILS_APB2_DIV(UTILS_ClkInitStruct->APB2CLKDivider)); - assert_param(IS_LL_UTILS_APB3_DIV(UTILS_ClkInitStruct->APB3CLKDivider)); - - /* Calculate HCLK frequency */ - hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); - - /* Increasing the number of wait states because of higher CPU frequency */ - if (SystemCoreClock < hclk_frequency) - { - /* Set FLASH latency to highest latency */ - status = LL_SetFlashLatency(hclk_frequency); - } - - /* Update system clock configuration */ - if (status == SUCCESS) - { - /* Enable PLL1 */ - LL_RCC_PLL1_Enable(); - LL_RCC_PLL1_EnableDomain_SYS(); - while (LL_RCC_PLL1_IsReady() != 1U) - { - /* Wait for PLL ready */ - } - - /* Sysclk activation on the main PLL */ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL1); - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL1) - { - /* Wait for system clock switch to PLL */ - } - - /* Set APB1, APB2 & APB3 prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - LL_RCC_SetAPB2Prescaler(UTILS_ClkInitStruct->APB2CLKDivider); - LL_RCC_SetAPB3Prescaler(UTILS_ClkInitStruct->APB3CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (SystemCoreClock > hclk_frequency) - { - /* Set FLASH latency to lowest latency */ - status = LL_SetFlashLatency(hclk_frequency); - } - - /* Update SystemCoreClock variable */ - if (status == SUCCESS) - { - LL_SetSystemCoreClock(hclk_frequency); - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/main.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/main.h deleted file mode 100644 index f4cf15418..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/main.h +++ /dev/null @@ -1,203 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.h - * @brief : Header for main.c file. - * This file contains the common defines of the application. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __MAIN_H -#define __MAIN_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" -#include "stm32u5xx_ll_ucpd.h" -#include "stm32u5xx_ll_bus.h" -#include "stm32u5xx_ll_cortex.h" -#include "stm32u5xx_ll_rcc.h" -#include "stm32u5xx_ll_system.h" -#include "stm32u5xx_ll_utils.h" -#include "stm32u5xx_ll_pwr.h" -#include "stm32u5xx_ll_gpio.h" -#include "stm32u5xx_ll_dma.h" - -#include "stm32u5xx_ll_exti.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void Error_Handler(void); - -/* USER CODE BEGIN EFP */ -extern int stdio_init (void); -extern int app_main (void); -/* USER CODE END EFP */ - -/* Private defines -----------------------------------------------------------*/ -#define WRLS_FLOW_Pin GPIO_PIN_15 -#define WRLS_FLOW_GPIO_Port GPIOG -#define WRLS_UART4_RX_Pin GPIO_PIN_11 -#define WRLS_UART4_RX_GPIO_Port GPIOC -#define USB_UCPD_CC1_Pin GPIO_PIN_15 -#define USB_UCPD_CC1_GPIO_Port GPIOA -#define OCTOSPI_F_NCS_Pin GPIO_PIN_5 -#define OCTOSPI_F_NCS_GPIO_Port GPIOI -#define OCTOSPI_R_IO5_Pin GPIO_PIN_0 -#define OCTOSPI_R_IO5_GPIO_Port GPIOI -#define OCTOSPI_F_IO7_Pin GPIO_PIN_12 -#define OCTOSPI_F_IO7_GPIO_Port GPIOH -#define PH3_BOOT0_Pin GPIO_PIN_3 -#define PH3_BOOT0_GPIO_Port GPIOH -#define UCPD_PWR_Pin GPIO_PIN_5 -#define UCPD_PWR_GPIO_Port GPIOB -#define WRLS_SPI2_MOSI_Pin GPIO_PIN_4 -#define WRLS_SPI2_MOSI_GPIO_Port GPIOD -#define WRLS_UART4_TX_Pin GPIO_PIN_10 -#define WRLS_UART4_TX_GPIO_Port GPIOC -#define T_SWCLK_Pin GPIO_PIN_14 -#define T_SWCLK_GPIO_Port GPIOA -#define OCTOSPI_F_IO5_Pin GPIO_PIN_10 -#define OCTOSPI_F_IO5_GPIO_Port GPIOH -#define PC14_OSC32_IN_Pin GPIO_PIN_14 -#define PC14_OSC32_IN_GPIO_Port GPIOC -#define OCTOSPI_R_DQS_Pin GPIO_PIN_3 -#define OCTOSPI_R_DQS_GPIO_Port GPIOE -#define T_SWO_Pin GPIO_PIN_3 -#define T_SWO_GPIO_Port GPIOB -#define OCTOSPI_R_IO7_Pin GPIO_PIN_7 -#define OCTOSPI_R_IO7_GPIO_Port GPIOD -#define WRLS_SPI2_MISO_Pin GPIO_PIN_3 -#define WRLS_SPI2_MISO_GPIO_Port GPIOD -#define OCTOSPI_F_IO6_Pin GPIO_PIN_11 -#define OCTOSPI_F_IO6_GPIO_Port GPIOH -#define PC15_OSC32_OUT_Pin GPIO_PIN_15 -#define PC15_OSC32_OUT_GPIO_Port GPIOC -#define OCTOSPI_F_IO0_Pin GPIO_PIN_0 -#define OCTOSPI_F_IO0_GPIO_Port GPIOF -#define USER_Button_Pin GPIO_PIN_13 -#define USER_Button_GPIO_Port GPIOC -#define OCTOSPI_F_IO4_Pin GPIO_PIN_9 -#define OCTOSPI_F_IO4_GPIO_Port GPIOH -#define LED_RED_Pin GPIO_PIN_6 -#define LED_RED_GPIO_Port GPIOH -#define OCTOSPI_R_IO0_Pin GPIO_PIN_8 -#define OCTOSPI_R_IO0_GPIO_Port GPIOF -#define OCTOSPI_F_IO1_Pin GPIO_PIN_1 -#define OCTOSPI_F_IO1_GPIO_Port GPIOF -#define OCTOSPI_F_IO2_Pin GPIO_PIN_2 -#define OCTOSPI_F_IO2_GPIO_Port GPIOF -#define WRLS_SPI2_SCK_Pin GPIO_PIN_1 -#define WRLS_SPI2_SCK_GPIO_Port GPIOD -#define LED_GREEN_Pin GPIO_PIN_7 -#define LED_GREEN_GPIO_Port GPIOH -#define OCTOSPI_R_IO4_Pin GPIO_PIN_2 -#define OCTOSPI_R_IO4_GPIO_Port GPIOH -#define T_VCP_RX_Pin GPIO_PIN_10 -#define T_VCP_RX_GPIO_Port GPIOA -#define T_SWDIO_Pin GPIO_PIN_13 -#define T_SWDIO_GPIO_Port GPIOA -#define USB_C_P_Pin GPIO_PIN_12 -#define USB_C_P_GPIO_Port GPIOA -#define OCTOSPI_R_IO2_Pin GPIO_PIN_7 -#define OCTOSPI_R_IO2_GPIO_Port GPIOF -#define OCTOSPI_R_IO1_Pin GPIO_PIN_9 -#define OCTOSPI_R_IO1_GPIO_Port GPIOF -#define OCTOSPI_F_IO3_Pin GPIO_PIN_3 -#define OCTOSPI_F_IO3_GPIO_Port GPIOF -#define OCTOSPI_F_CLK_P_Pin GPIO_PIN_4 -#define OCTOSPI_F_CLK_P_GPIO_Port GPIOF -#define T_VCP_TX_Pin GPIO_PIN_9 -#define T_VCP_TX_GPIO_Port GPIOA -#define USB_C_PA11_Pin GPIO_PIN_11 -#define USB_C_PA11_GPIO_Port GPIOA -#define MIC_CCK1_Pin GPIO_PIN_10 -#define MIC_CCK1_GPIO_Port GPIOF -#define OCTOSPI_R_IO3_Pin GPIO_PIN_6 -#define OCTOSPI_R_IO3_GPIO_Port GPIOF -#define MIC_SDINx_Pin GPIO_PIN_10 -#define MIC_SDINx_GPIO_Port GPIOE -#define WRLS_WKUP_B_Pin GPIO_PIN_6 -#define WRLS_WKUP_B_GPIO_Port GPIOG -#define Mems_VL53_xshut_Pin GPIO_PIN_1 -#define Mems_VL53_xshut_GPIO_Port GPIOH -#define MIC_CCK0_Pin GPIO_PIN_9 -#define MIC_CCK0_GPIO_Port GPIOE -#define Mems_VLX_GPIO_Pin GPIO_PIN_5 -#define Mems_VLX_GPIO_GPIO_Port GPIOG -#define WRLS_NOTIFY_Pin GPIO_PIN_14 -#define WRLS_NOTIFY_GPIO_Port GPIOD -#define OCTOSPI_R_IO6_Pin GPIO_PIN_3 -#define OCTOSPI_R_IO6_GPIO_Port GPIOC -#define OCTOSPI_F_DQS_Pin GPIO_PIN_12 -#define OCTOSPI_F_DQS_GPIO_Port GPIOF -#define USB_UCPD_FLT_Pin GPIO_PIN_8 -#define USB_UCPD_FLT_GPIO_Port GPIOE -#define OCTOSPI_R_CLK_P_Pin GPIO_PIN_10 -#define OCTOSPI_R_CLK_P_GPIO_Port GPIOB -#define Mems_INT_IIS2MDC_Pin GPIO_PIN_10 -#define Mems_INT_IIS2MDC_GPIO_Port GPIOD -#define USB_IANA_Pin GPIO_PIN_13 -#define USB_IANA_GPIO_Port GPIOD -#define Mems_INT_LPS22HH_Pin GPIO_PIN_2 -#define Mems_INT_LPS22HH_GPIO_Port GPIOG -#define USB_VBUS_SENSE_Pin GPIO_PIN_14 -#define USB_VBUS_SENSE_GPIO_Port GPIOF -#define OCTOSPI_R_NCS_Pin GPIO_PIN_11 -#define OCTOSPI_R_NCS_GPIO_Port GPIOB -#define WRLS_SPI2_NSS_Pin GPIO_PIN_12 -#define WRLS_SPI2_NSS_GPIO_Port GPIOB -#define USB_UCPD_CC2_Pin GPIO_PIN_15 -#define USB_UCPD_CC2_GPIO_Port GPIOB -#define Mems_STSAFE_RESET_Pin GPIO_PIN_11 -#define Mems_STSAFE_RESET_GPIO_Port GPIOF -#define Mems_ISM330DLC_INT1_Pin GPIO_PIN_11 -#define Mems_ISM330DLC_INT1_GPIO_Port GPIOE -#define MIC_SDIN0_Pin GPIO_PIN_1 -#define MIC_SDIN0_GPIO_Port GPIOB -#define WRLS_WKUP_W_Pin GPIO_PIN_15 -#define WRLS_WKUP_W_GPIO_Port GPIOF - -/* USER CODE BEGIN Private defines */ - -/* USER CODE END Private defines */ - -#ifdef __cplusplus -} -#endif - -#endif /* __MAIN_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32_assert.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32_assert.h deleted file mode 100644 index 3620d0511..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32_assert.h +++ /dev/null @@ -1,53 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32_assert.h - * @author MCD Application Team - * @brief STM32 assert file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32_ASSERT_H -#define __STM32_ASSERT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/* Includes ------------------------------------------------------------------*/ -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ -#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ -void assert_failed(uint8_t *file, uint32_t line); -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32_ASSERT_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32u5xx_hal_conf.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32u5xx_hal_conf.h deleted file mode 100644 index fa3b01074..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32u5xx_hal_conf.h +++ /dev/null @@ -1,507 +0,0 @@ -/** - ****************************************************************************** - * @file stm32u5xx_hal_conf.h - * @author MCD Application Team - * @brief HAL configuration file. - ****************************************************************************** - * @attention - * - * Copyright (c) 2021-2023 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32U5xx_HAL_CONF_H -#define STM32U5xx_HAL_CONF_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ - -/* ########################## Module Selection ############################## */ -/** - * @brief This is the list of modules to be used in the HAL driver - */ -#define HAL_MODULE_ENABLED - -/*#define HAL_ADC_MODULE_ENABLED */ -/*#define HAL_COMP_MODULE_ENABLED */ -/*#define HAL_CORDIC_MODULE_ENABLED */ -/*#define HAL_CRC_MODULE_ENABLED */ -/*#define HAL_CRYP_MODULE_ENABLED */ -/*#define HAL_DAC_MODULE_ENABLED */ -/*#define HAL_DCACHE_MODULE_ENABLED */ -/*#define HAL_DCMI_MODULE_ENABLED */ -/*#define HAL_DMA2D_MODULE_ENABLED */ -/*#define HAL_DSI_MODULE_ENABLED */ -/*#define HAL_FDCAN_MODULE_ENABLED */ -/*#define HAL_FMAC_MODULE_ENABLED */ -/*#define HAL_GFXMMU_MODULE_ENABLED */ -/*#define HAL_GFXTIM_MODULE_ENABLED */ -/*#define HAL_GPU2D_MODULE_ENABLED */ -/*#define HAL_GTZC_MODULE_ENABLED */ -/*#define HAL_HASH_MODULE_ENABLED */ -/*#define HAL_HCD_MODULE_ENABLED */ -#define HAL_I2C_MODULE_ENABLED -#define HAL_ICACHE_MODULE_ENABLED -/*#define HAL_IRDA_MODULE_ENABLED */ -/*#define HAL_IWDG_MODULE_ENABLED */ -/*#define HAL_JPEG_MODULE_ENABLED */ -/*#define HAL_LPTIM_MODULE_ENABLED */ -/*#define HAL_LTDC_MODULE_ENABLED */ -#define HAL_MDF_MODULE_ENABLED -/*#define HAL_MMC_MODULE_ENABLED */ -/*#define HAL_NAND_MODULE_ENABLED */ -/*#define HAL_NOR_MODULE_ENABLED */ -/*#define HAL_OPAMP_MODULE_ENABLED */ -#define HAL_OSPI_MODULE_ENABLED -/*#define HAL_OTFDEC_MODULE_ENABLED */ -#define HAL_PCD_MODULE_ENABLED -/*#define HAL_PKA_MODULE_ENABLED */ -/*#define HAL_PSSI_MODULE_ENABLED */ -/*#define HAL_RAMCFG_MODULE_ENABLED */ -/*#define HAL_RNG_MODULE_ENABLED */ -/*#define HAL_RTC_MODULE_ENABLED */ -/*#define HAL_SAI_MODULE_ENABLED */ -/*#define HAL_SD_MODULE_ENABLED */ -/*#define HAL_SMARTCARD_MODULE_ENABLED */ -/*#define HAL_SMBUS_MODULE_ENABLED */ -#define HAL_SPI_MODULE_ENABLED -/*#define HAL_SRAM_MODULE_ENABLED */ -#define HAL_TIM_MODULE_ENABLED -/*#define HAL_TSC_MODULE_ENABLED */ -#define HAL_UART_MODULE_ENABLED -/*#define HAL_USART_MODULE_ENABLED */ -/*#define HAL_WWDG_MODULE_ENABLED */ -/*#define HAL_XSPI_MODULE_ENABLED */ -#define HAL_GPIO_MODULE_ENABLED -#define HAL_EXTI_MODULE_ENABLED -#define HAL_DMA_MODULE_ENABLED -#define HAL_RCC_MODULE_ENABLED -#define HAL_FLASH_MODULE_ENABLED -#define HAL_PWR_MODULE_ENABLED -#define HAL_CORTEX_MODULE_ENABLED - -/* ########################## Oscillator Values adaptation ####################*/ -/** - * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSE is used as system clock source, directly or through the PLL). - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 16000000UL /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSE_STARTUP_TIMEOUT) -#define HSE_STARTUP_TIMEOUT 100UL /*!< Time out for HSE start up, in ms */ -#endif /* HSE_STARTUP_TIMEOUT */ - -/** - * @brief Internal Multiple Speed oscillator (MSI) default value. - * This value is the default MSI range value after Reset. - */ -#if !defined (MSI_VALUE) -#define MSI_VALUE 4000000UL /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI) value. - * This value is used by the RCC HAL module to compute the system frequency - * (when HSI is used as system clock source, directly or through the PLL). - */ -#if !defined (HSI_VALUE) -#define HSI_VALUE 16000000UL /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/** - * @brief Internal High Speed oscillator (HSI48) value for USB FS, SDMMC and RNG. - * This internal oscillator is mainly dedicated to provide a high precision clock to - * the USB peripheral by means of a special Clock Recovery System (CRS) circuitry. - * When the CRS is not used, the HSI48 RC oscillator runs on it default frequency - * which is subject to manufacturing process variations. - */ -#if !defined (HSI48_VALUE) -#define HSI48_VALUE 48000000UL /*!< Value of the Internal High Speed oscillator for USB FS/SDMMC/RNG in Hz. - The real value my vary depending on manufacturing process variations.*/ -#endif /* HSI48_VALUE */ - -/** - * @brief Internal Low Speed oscillator (LSI) value. - */ -#if !defined (LSI_VALUE) -#define LSI_VALUE 32000UL /*!< LSI Typical Value in Hz*/ -#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz. The real value may -vary depending on the variations in voltage and temperature.*/ - -/** - * @brief External Low Speed oscillator (LSE) value. - * This value is used by the UART, RTC HAL module to compute the system frequency - */ -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768UL /*!< Value of the External oscillator in Hz*/ -#endif /* LSE_VALUE */ - -#if !defined (LSE_STARTUP_TIMEOUT) -#define LSE_STARTUP_TIMEOUT 5000UL /*!< Time out for LSE start up, in ms */ -#endif /* LSE_STARTUP_TIMEOUT */ - -/** - * @brief External clock source for SAI1 peripheral - * This value is used by the RCC HAL module to compute the SAI1 & SAI2 clock source - * frequency. - */ -#if !defined (EXTERNAL_SAI1_CLOCK_VALUE) -#define EXTERNAL_SAI1_CLOCK_VALUE 48000UL /*!< Value of the SAI1 External clock source in Hz*/ -#endif /* EXTERNAL_SAI1_CLOCK_VALUE */ - -/* Tip: To avoid modifying this file each time you need to use different HSE, - === you can define the HSE value in your toolchain compiler preprocessor. */ - -/* ########################### System Configuration ######################### */ -/** - * @brief This is the HAL system configuration section - */ -#define VDD_VALUE 3300UL /*!< Value of VDD in mv */ -#define TICK_INT_PRIORITY (15UL) /*!< tick interrupt priority (lowest by default) */ -#define USE_RTOS 0U -#define PREFETCH_ENABLE 1U /*!< Enable prefetch */ - -/* ########################## Assert Selection ############################## */ -/** - * @brief Uncomment the line below to expanse the "assert_param" macro in the - * HAL drivers code - */ -/* #define USE_FULL_ASSERT 1U */ - -/* ################## Register callback feature configuration ############### */ -/** - * @brief Set below the peripheral configuration to "1U" to add the support - * of HAL callback registration/unregistration feature for the HAL - * driver(s). This allows user application to provide specific callback - * functions thanks to HAL_PPP_RegisterCallback() rather than overwriting - * the default weak callback functions (see each stm32u5xx_hal_ppp.h file - * for possible callback identifiers defined in HAL_PPP_CallbackIDTypeDef - * for each PPP peripheral). - */ -#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ -#define USE_HAL_COMP_REGISTER_CALLBACKS 0U /* COMP register callback disabled */ -#define USE_HAL_CORDIC_REGISTER_CALLBACKS 0U /* CORDIC register callback disabled */ -#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ -#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ -#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ -#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ -#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ -#define USE_HAL_FDCAN_REGISTER_CALLBACKS 0U /* FDCAN register callback disabled */ -#define USE_HAL_FMAC_REGISTER_CALLBACKS 0U /* FMAC register callback disabled */ -#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ -#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ -#define USE_HAL_GFXMMU_REGISTER_CALLBACKS 0U /* GFXMMU register callback disabled */ -#define USE_HAL_GFXTIM_REGISTER_CALLBACKS 0U /* GFXTIM register callback disabled */ -#define USE_HAL_GPU2D_REGISTER_CALLBACKS 0U /* GPU2D register callback disabled */ -#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ -#define USE_HAL_IWDG_REGISTER_CALLBACKS 0U /* IWDG register callback disabled */ -#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ -#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ -#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ -#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ -#define USE_HAL_MDF_REGISTER_CALLBACKS 0U /* MDF register callback disabled */ -#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ -#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ -#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ -#define USE_HAL_OPAMP_REGISTER_CALLBACKS 0U /* MDIO register callback disabled */ -#define USE_HAL_OTFDEC_REGISTER_CALLBACKS 0U /* OTFDEC register callback disabled */ -#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ -#define USE_HAL_PKA_REGISTER_CALLBACKS 0U /* PKA register callback disabled */ -#define USE_HAL_RAMCFG_REGISTER_CALLBACKS 0U /* RAMCFG register callback disabled */ -#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ -#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ -#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ -#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ -#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ -#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ -#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ -#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ -#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ -#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ -#define USE_HAL_TSC_REGISTER_CALLBACKS 0U /* TSC register callback disabled */ -#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ -#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ -#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ -#define USE_HAL_OSPI_REGISTER_CALLBACKS 0U /* OSPI register callback disabled */ -/* ################## SPI peripheral configuration ########################## */ - -/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver - * Activated: CRC code is present inside driver - * Deactivated: CRC code cleaned from driver - */ -#define USE_SPI_CRC 0U - -/* ################## SDMMC peripheral configuration ######################### */ - -#define USE_SD_TRANSCEIVER 0U - -/* Includes ------------------------------------------------------------------*/ -/** - * @brief Include module's header file - */ - -#ifdef HAL_RCC_MODULE_ENABLED -#include "stm32u5xx_hal_rcc.h" -#endif /* HAL_RCC_MODULE_ENABLED */ - -#ifdef HAL_GPIO_MODULE_ENABLED -#include "stm32u5xx_hal_gpio.h" -#endif /* HAL_GPIO_MODULE_ENABLED */ - -#ifdef HAL_ICACHE_MODULE_ENABLED -#include "stm32u5xx_hal_icache.h" -#endif /* HAL_ICACHE_MODULE_ENABLED */ - -#ifdef HAL_DCACHE_MODULE_ENABLED -#include "stm32u5xx_hal_dcache.h" -#endif /* HAL_DCACHE_MODULE_ENABLED */ - -#ifdef HAL_GTZC_MODULE_ENABLED -#include "stm32u5xx_hal_gtzc.h" -#endif /* HAL_GTZC_MODULE_ENABLED */ - -#ifdef HAL_DMA_MODULE_ENABLED -#include "stm32u5xx_hal_dma.h" -#endif /* HAL_DMA_MODULE_ENABLED */ - -#ifdef HAL_DMA2D_MODULE_ENABLED -#include "stm32u5xx_hal_dma2d.h" -#endif /* HAL_DMA2D_MODULE_ENABLED */ - -#ifdef HAL_DSI_MODULE_ENABLED -#include "stm32u5xx_hal_dsi.h" -#endif /* HAL_DSI_MODULE_ENABLED */ - -#ifdef HAL_CORTEX_MODULE_ENABLED -#include "stm32u5xx_hal_cortex.h" -#endif /* HAL_CORTEX_MODULE_ENABLED */ - -#ifdef HAL_PKA_MODULE_ENABLED -#include "stm32u5xx_hal_pka.h" -#endif /* HAL_PKA_MODULE_ENABLED */ - -#ifdef HAL_ADC_MODULE_ENABLED -#include "stm32u5xx_hal_adc.h" -#endif /* HAL_ADC_MODULE_ENABLED */ - -#ifdef HAL_COMP_MODULE_ENABLED -#include "stm32u5xx_hal_comp.h" -#endif /* HAL_COMP_MODULE_ENABLED */ - -#ifdef HAL_CRC_MODULE_ENABLED -#include "stm32u5xx_hal_crc.h" -#endif /* HAL_CRC_MODULE_ENABLED */ - -#ifdef HAL_CRYP_MODULE_ENABLED -#include "stm32u5xx_hal_cryp.h" -#endif /* HAL_CRYP_MODULE_ENABLED */ - -#ifdef HAL_DAC_MODULE_ENABLED -#include "stm32u5xx_hal_dac.h" -#endif /* HAL_DAC_MODULE_ENABLED */ - -#ifdef HAL_FLASH_MODULE_ENABLED -#include "stm32u5xx_hal_flash.h" -#endif /* HAL_FLASH_MODULE_ENABLED */ - -#ifdef HAL_HASH_MODULE_ENABLED -#include "stm32u5xx_hal_hash.h" -#endif /* HAL_HASH_MODULE_ENABLED */ - -#ifdef HAL_SRAM_MODULE_ENABLED -#include "stm32u5xx_hal_sram.h" -#endif /* HAL_SRAM_MODULE_ENABLED */ - -#ifdef HAL_MMC_MODULE_ENABLED -#include "stm32u5xx_hal_mmc.h" -#endif /* HAL_MMC_MODULE_ENABLED */ - -#ifdef HAL_NOR_MODULE_ENABLED -#include "stm32u5xx_hal_nor.h" -#endif /* HAL_NOR_MODULE_ENABLED */ - -#ifdef HAL_NAND_MODULE_ENABLED -#include "stm32u5xx_hal_nand.h" -#endif /* HAL_NAND_MODULE_ENABLED */ - -#ifdef HAL_I2C_MODULE_ENABLED -#include "stm32u5xx_hal_i2c.h" -#endif /* HAL_I2C_MODULE_ENABLED */ - -#ifdef HAL_IWDG_MODULE_ENABLED -#include "stm32u5xx_hal_iwdg.h" -#endif /* HAL_IWDG_MODULE_ENABLED */ - -#ifdef HAL_JPEG_MODULE_ENABLED -#include "stm32u5xx_hal_jpeg.h" -#endif /* HAL_JPEG_MODULE_ENABLED */ - -#ifdef HAL_LPTIM_MODULE_ENABLED -#include "stm32u5xx_hal_lptim.h" -#endif /* HAL_LPTIM_MODULE_ENABLED */ - -#ifdef HAL_LTDC_MODULE_ENABLED -#include "stm32u5xx_hal_ltdc.h" -#endif /* HAL_LTDC_MODULE_ENABLED */ - -#ifdef HAL_OPAMP_MODULE_ENABLED -#include "stm32u5xx_hal_opamp.h" -#endif /* HAL_OPAMP_MODULE_ENABLED */ - -#ifdef HAL_PWR_MODULE_ENABLED -#include "stm32u5xx_hal_pwr.h" -#endif /* HAL_PWR_MODULE_ENABLED */ - -#ifdef HAL_OSPI_MODULE_ENABLED -#include "stm32u5xx_hal_ospi.h" -#endif /* HAL_OSPI_MODULE_ENABLED */ - -#ifdef HAL_RNG_MODULE_ENABLED -#include "stm32u5xx_hal_rng.h" -#endif /* HAL_RNG_MODULE_ENABLED */ - -#ifdef HAL_RTC_MODULE_ENABLED -#include "stm32u5xx_hal_rtc.h" -#endif /* HAL_RTC_MODULE_ENABLED */ - -#ifdef HAL_SAI_MODULE_ENABLED -#include "stm32u5xx_hal_sai.h" -#endif /* HAL_SAI_MODULE_ENABLED */ - -#ifdef HAL_SD_MODULE_ENABLED -#include "stm32u5xx_hal_sd.h" -#endif /* HAL_SD_MODULE_ENABLED */ - -#ifdef HAL_SMBUS_MODULE_ENABLED -#include "stm32u5xx_hal_smbus.h" -#endif /* HAL_SMBUS_MODULE_ENABLED */ - -#ifdef HAL_SPI_MODULE_ENABLED -#include "stm32u5xx_hal_spi.h" -#endif /* HAL_SPI_MODULE_ENABLED */ - -#ifdef HAL_TIM_MODULE_ENABLED -#include "stm32u5xx_hal_tim.h" -#endif /* HAL_TIM_MODULE_ENABLED */ - -#ifdef HAL_TSC_MODULE_ENABLED -#include "stm32u5xx_hal_tsc.h" -#endif /* HAL_TSC_MODULE_ENABLED */ - -#ifdef HAL_UART_MODULE_ENABLED -#include "stm32u5xx_hal_uart.h" -#endif /* HAL_UART_MODULE_ENABLED */ - -#ifdef HAL_USART_MODULE_ENABLED -#include "stm32u5xx_hal_usart.h" -#endif /* HAL_USART_MODULE_ENABLED */ - -#ifdef HAL_IRDA_MODULE_ENABLED -#include "stm32u5xx_hal_irda.h" -#endif /* HAL_IRDA_MODULE_ENABLED */ - -#ifdef HAL_SMARTCARD_MODULE_ENABLED -#include "stm32u5xx_hal_smartcard.h" -#endif /* HAL_SMARTCARD_MODULE_ENABLED */ - -#ifdef HAL_WWDG_MODULE_ENABLED -#include "stm32u5xx_hal_wwdg.h" -#endif /* HAL_WWDG_MODULE_ENABLED */ - -#ifdef HAL_PCD_MODULE_ENABLED -#include "stm32u5xx_hal_pcd.h" -#endif /* HAL_PCD_MODULE_ENABLED */ - -#ifdef HAL_HCD_MODULE_ENABLED -#include "stm32u5xx_hal_hcd.h" -#endif /* HAL_HCD_MODULE_ENABLED */ - -#ifdef HAL_CORDIC_MODULE_ENABLED -#include "stm32u5xx_hal_cordic.h" -#endif /* HAL_CORDIC_MODULE_ENABLED */ - -#ifdef HAL_DCMI_MODULE_ENABLED -#include "stm32u5xx_hal_dcmi.h" -#endif /* HAL_DCMI_MODULE_ENABLED */ - -#ifdef HAL_EXTI_MODULE_ENABLED -#include "stm32u5xx_hal_exti.h" -#endif /* HAL_EXTI_MODULE_ENABLED */ - -#ifdef HAL_FDCAN_MODULE_ENABLED -#include "stm32u5xx_hal_fdcan.h" -#endif /* HAL_FDCAN_MODULE_ENABLED */ - -#ifdef HAL_FMAC_MODULE_ENABLED -#include "stm32u5xx_hal_fmac.h" -#endif /* HAL_FMAC_MODULE_ENABLED */ - -#ifdef HAL_GFXMMU_MODULE_ENABLED -#include "stm32u5xx_hal_gfxmmu.h" -#endif /* HAL_GFXMMU_MODULE_ENABLED */ - -#ifdef HAL_GFXTIM_MODULE_ENABLED -#include "stm32u5xx_hal_gfxtim.h" -#endif /* HAL_GFXTIM_MODULE_ENABLED */ - -#ifdef HAL_GPU2D_MODULE_ENABLED -#include "stm32u5xx_hal_gpu2d.h" -#endif /* HAL_GPU2D_MODULE_ENABLED */ - -#ifdef HAL_OTFDEC_MODULE_ENABLED -#include "stm32u5xx_hal_otfdec.h" -#endif /* HAL_OTFDEC_MODULE_ENABLED */ - -#ifdef HAL_PSSI_MODULE_ENABLED -#include "stm32u5xx_hal_pssi.h" -#endif /* HAL_PSSI_MODULE_ENABLED */ - -#ifdef HAL_RAMCFG_MODULE_ENABLED -#include "stm32u5xx_hal_ramcfg.h" -#endif /* HAL_RAMCFG_MODULE_ENABLED */ - -#ifdef HAL_MDF_MODULE_ENABLED -#include "stm32u5xx_hal_mdf.h" -#endif /* HAL_MDF_MODULE_ENABLED */ - -#ifdef HAL_XSPI_MODULE_ENABLED -#include "stm32u5xx_hal_xspi.h" -#endif /* HAL_XSPI_MODULE_ENABLED */ - -/* Exported macro ------------------------------------------------------------*/ -#ifdef USE_FULL_ASSERT -/** - * @brief The assert_param macro is used for function's parameters check. - * @param expr: If expr is false, it calls assert_failed function - * which reports the name of the source file and the source - * line number of the call that failed. - * If expr is true, it returns no value. - * @retval None - */ -#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) -/* Exported functions ------------------------------------------------------- */ -void assert_failed(uint8_t *file, uint32_t line); -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32U5xx_HAL_CONF_H */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32u5xx_it.h b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32u5xx_it.h deleted file mode 100644 index 8a3a823dd..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Inc/stm32u5xx_it.h +++ /dev/null @@ -1,65 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32u5xx_it.h - * @brief This file contains the headers of the interrupt handlers. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __STM32U5xx_IT_H -#define __STM32U5xx_IT_H - -#ifdef __cplusplus - extern "C" { -#endif - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Exported types ------------------------------------------------------------*/ -/* USER CODE BEGIN ET */ - -/* USER CODE END ET */ - -/* Exported constants --------------------------------------------------------*/ -/* USER CODE BEGIN EC */ - -/* USER CODE END EC */ - -/* Exported macro ------------------------------------------------------------*/ -/* USER CODE BEGIN EM */ - -/* USER CODE END EM */ - -/* Exported functions prototypes ---------------------------------------------*/ -void NMI_Handler(void); -void HardFault_Handler(void); -void MemManage_Handler(void); -void BusFault_Handler(void); -void UsageFault_Handler(void); -void DebugMon_Handler(void); -void USART1_IRQHandler(void); -void TIM17_IRQHandler(void); -/* USER CODE BEGIN EFP */ - -/* USER CODE END EFP */ - -#ifdef __cplusplus -} -#endif - -#endif /* __STM32U5xx_IT_H */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/MDK-ARM/startup_stm32u585xx.s b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/MDK-ARM/startup_stm32u585xx.s deleted file mode 100644 index cedd85f6e..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/MDK-ARM/startup_stm32u585xx.s +++ /dev/null @@ -1,566 +0,0 @@ -;******************************************************************************* -;* File Name : startup_stm32u585xx.s -;* Author : MCD Application Team -;* Description : STM32U585xx Ultra Low Power devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M33 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* @attention -;* -;* Copyright (c) 2021 STMicroelectronics. -;* All rights reserved. -;* -;* This software is licensed under terms that can be found in the LICENSE file -;* in the root directory of this software component. -;* If no LICENSE file comes with this software, it is provided AS-IS. -;* -;******************************************************************************* -;* <<< Use Configuration Wizard in Context Menu >>> -; -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; Stack Configuration -; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Stack_Size EQU 0x400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; Heap Configuration -; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; - -Heap_Size EQU 0x400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD SecureFault_Handler ; Secure Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_PVM_IRQHandler ; PVD/PVM through EXTI Line detection Interrupt - DCD RTC_IRQHandler ; RTC non-secure interrupt - DCD RTC_S_IRQHandler ; RTC secure interrupt - DCD TAMP_IRQHandler ; Tamper non-secure interrupt - DCD RAMCFG_IRQHandler ; RAMCFG global - DCD FLASH_IRQHandler ; FLASH non-secure global interrupt - DCD FLASH_S_IRQHandler ; FLASH secure global interrupt - DCD GTZC_IRQHandler ; Global TrustZone Controller interrupt - DCD RCC_IRQHandler ; RCC non-secure global interrupt - DCD RCC_S_IRQHandler ; RCC secure global interrupt - DCD EXTI0_IRQHandler ; EXTI Line0 interrupt - DCD EXTI1_IRQHandler ; EXTI Line1 interrupt - DCD EXTI2_IRQHandler ; EXTI Line2 interrupt - DCD EXTI3_IRQHandler ; EXTI Line3 interrupt - DCD EXTI4_IRQHandler ; EXTI Line4 interrupt - DCD EXTI5_IRQHandler ; EXTI Line5 interrupt - DCD EXTI6_IRQHandler ; EXTI Line6 interrupt - DCD EXTI7_IRQHandler ; EXTI Line7 interrupt - DCD EXTI8_IRQHandler ; EXTI Line8 interrupt - DCD EXTI9_IRQHandler ; EXTI Line9 interrupt - DCD EXTI10_IRQHandler ; EXTI Line10 interrupt - DCD EXTI11_IRQHandler ; EXTI Line11 interrupt - DCD EXTI12_IRQHandler ; EXTI Line12 interrupt - DCD EXTI13_IRQHandler ; EXTI Line13 interrupt - DCD EXTI14_IRQHandler ; EXTI Line14 interrupt - DCD EXTI15_IRQHandler ; EXTI Line15 interrupt - DCD IWDG_IRQHandler ; IWDG global interrupt - DCD SAES_IRQHandler ; Secure AES global interrupt - DCD GPDMA1_Channel0_IRQHandler ; GPDMA1 Channel 0 global interrupt - DCD GPDMA1_Channel1_IRQHandler ; GPDMA1 Channel 1 global interrupt - DCD GPDMA1_Channel2_IRQHandler ; GPDMA1 Channel 2 global interrupt - DCD GPDMA1_Channel3_IRQHandler ; GPDMA1 Channel 3 global interrupt - DCD GPDMA1_Channel4_IRQHandler ; GPDMA1 Channel 4 global interrupt - DCD GPDMA1_Channel5_IRQHandler ; GPDMA1 Channel 5 global interrupt - DCD GPDMA1_Channel6_IRQHandler ; GPDMA1 Channel 6 global interrupt - DCD GPDMA1_Channel7_IRQHandler ; GPDMA1 Channel 7 global interrupt - DCD ADC1_IRQHandler ; ADC1 global interrupt - DCD DAC1_IRQHandler ; DAC1 global interrupt - DCD FDCAN1_IT0_IRQHandler ; FDCAN1 interrupt 0 - DCD FDCAN1_IT1_IRQHandler ; FDCAN1 interrupt 1 - DCD TIM1_BRK_IRQHandler ; TIM1 Break interrupt - DCD TIM1_UP_IRQHandler ; TIM1 Update interrupt - DCD TIM1_TRG_COM_IRQHandler ; TIM1 Trigger and Commutation interrupt - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare interrupt - DCD TIM2_IRQHandler ; TIM2 global interrupt - DCD TIM3_IRQHandler ; TIM3 global interrupt - DCD TIM4_IRQHandler ; TIM4 global interrupt - DCD TIM5_IRQHandler ; TIM5 global interrupt - DCD TIM6_IRQHandler ; TIM6 global interrupt - DCD TIM7_IRQHandler ; TIM7 global interrupt - DCD TIM8_BRK_IRQHandler ; TIM8 Break interrupt - DCD TIM8_UP_IRQHandler ; TIM8 Update interrupt - DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation interrupt - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare interrupt - DCD I2C1_EV_IRQHandler ; I2C1 Event interrupt - DCD I2C1_ER_IRQHandler ; I2C1 Error interrupt - DCD I2C2_EV_IRQHandler ; I2C2 Event interrupt - DCD I2C2_ER_IRQHandler ; I2C2 Error interrupt - DCD SPI1_IRQHandler ; SPI1 global interrupt - DCD SPI2_IRQHandler ; SPI2 global interrupt - DCD USART1_IRQHandler ; USART1 global interrupt - DCD USART2_IRQHandler ; USART2 global interrupt - DCD USART3_IRQHandler ; USART3 global interrupt - DCD UART4_IRQHandler ; UART4 global interrupt - DCD UART5_IRQHandler ; UART5 global interrupt - DCD LPUART1_IRQHandler ; LPUART1 global interrupt - DCD LPTIM1_IRQHandler ; LPTIM1 global interrupt - DCD LPTIM2_IRQHandler ; LPTIM2 global interrupt - DCD TIM15_IRQHandler ; TIM15 global interrupt - DCD TIM16_IRQHandler ; TIM16 global interrupt - DCD TIM17_IRQHandler ; TIM17 global interrupt - DCD COMP_IRQHandler ; COMP1 and COMP2 through EXTI Lines interrupt - DCD OTG_FS_IRQHandler ; USB OTG FS global interrupt - DCD CRS_IRQHandler ; CRS global interrupt - DCD FMC_IRQHandler ; FMC global interrupt - DCD OCTOSPI1_IRQHandler ; OctoSPI1 global interrupt - DCD PWR_S3WU_IRQHandler ; PWR wake up from Stop3 interrupt - DCD SDMMC1_IRQHandler ; SDMMC1 global interrupt - DCD SDMMC2_IRQHandler ; SDMMC2 global interrupt - DCD GPDMA1_Channel8_IRQHandler ; GPDMA1 Channel 8 global interrupt - DCD GPDMA1_Channel9_IRQHandler ; GPDMA1 Channel 9 global interrupt - DCD GPDMA1_Channel10_IRQHandler ; GPDMA1 Channel 10 global interrupt - DCD GPDMA1_Channel11_IRQHandler ; GPDMA1 Channel 11 global interrupt - DCD GPDMA1_Channel12_IRQHandler ; GPDMA1 Channel 12 global interrupt - DCD GPDMA1_Channel13_IRQHandler ; GPDMA1 Channel 13 global interrupt - DCD GPDMA1_Channel14_IRQHandler ; GPDMA1 Channel 14 global interrupt - DCD GPDMA1_Channel15_IRQHandler ; GPDMA1 Channel 15 global interrupt - DCD I2C3_EV_IRQHandler ; I2C3 event interrupt - DCD I2C3_ER_IRQHandler ; I2C3 error interrupt - DCD SAI1_IRQHandler ; Serial Audio Interface 1 global interrupt - DCD SAI2_IRQHandler ; Serial Audio Interface 2 global interrupt - DCD TSC_IRQHandler ; Touch Sense Controller global interrupt - DCD AES_IRQHandler ; AES global interrupt - DCD RNG_IRQHandler ; RNG global interrupt - DCD FPU_IRQHandler ; FPU global interrupt - DCD HASH_IRQHandler ; HASH global interrupt - DCD PKA_IRQHandler ; PKA global interrupt - DCD LPTIM3_IRQHandler ; LPTIM3 global interrupt - DCD SPI3_IRQHandler ; SPI3 global interrupt - DCD I2C4_ER_IRQHandler ; I2C4 Error interrupt - DCD I2C4_EV_IRQHandler ; I2C4 Event interrupt - DCD MDF1_FLT0_IRQHandler ; MDF1 Filter 0 global interrupt - DCD MDF1_FLT1_IRQHandler ; MDF1 Filter 1 global interrupt - DCD MDF1_FLT2_IRQHandler ; MDF1 Filter 2 global interrupt - DCD MDF1_FLT3_IRQHandler ; MDF1 Filter 3 global interrupt - DCD UCPD1_IRQHandler ; UCPD1 global interrupt - DCD ICACHE_IRQHandler ; Instruction cache global interrupt - DCD OTFDEC1_IRQHandler ; OTFDEC1 global interrupt - DCD OTFDEC2_IRQHandler ; OTFDEC2 global interrupt - DCD LPTIM4_IRQHandler ; LPTIM4 global interrupt - DCD DCACHE1_IRQHandler ; Data cache global interrupt - DCD ADF1_IRQHandler ; ADF interrupt - DCD ADC4_IRQHandler ; ADC4 (12bits) global interrupt - DCD LPDMA1_Channel0_IRQHandler ; LPDMA1 SmartRun Channel 0 global interrupt - DCD LPDMA1_Channel1_IRQHandler ; LPDMA1 SmartRun Channel 1 global interrupt - DCD LPDMA1_Channel2_IRQHandler ; LPDMA1 SmartRun Channel 2 global interrupt - DCD LPDMA1_Channel3_IRQHandler ; LPDMA1 SmartRun Channel 3 global interrupt - DCD DMA2D_IRQHandler ; DMA2D global interrupt - DCD DCMI_PSSI_IRQHandler ; DCMI/PSSI global interrupt - DCD OCTOSPI2_IRQHandler ; OCTOSPI2 global interrupt - DCD MDF1_FLT4_IRQHandler ; MDF1 Filter 4 global interrupt - DCD MDF1_FLT5_IRQHandler ; MDF1 Filter 5 global interrupt - DCD CORDIC_IRQHandler ; CORDIC global interrupt - DCD FMAC_IRQHandler ; FMAC global interrupt - DCD LSECSSD_IRQHandler ; LSECSSD global interrupt - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SecureFault_Handler\ - PROC - EXPORT SecureFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_PVM_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_S_IRQHandler [WEAK] - EXPORT TAMP_IRQHandler [WEAK] - EXPORT RAMCFG_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT FLASH_S_IRQHandler [WEAK] - EXPORT GTZC_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT RCC_S_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT EXTI5_IRQHandler [WEAK] - EXPORT EXTI6_IRQHandler [WEAK] - EXPORT EXTI7_IRQHandler [WEAK] - EXPORT EXTI8_IRQHandler [WEAK] - EXPORT EXTI9_IRQHandler [WEAK] - EXPORT EXTI10_IRQHandler [WEAK] - EXPORT EXTI11_IRQHandler [WEAK] - EXPORT EXTI12_IRQHandler [WEAK] - EXPORT EXTI13_IRQHandler [WEAK] - EXPORT EXTI14_IRQHandler [WEAK] - EXPORT EXTI15_IRQHandler [WEAK] - EXPORT IWDG_IRQHandler [WEAK] - EXPORT SAES_IRQHandler [WEAK] - EXPORT GPDMA1_Channel0_IRQHandler [WEAK] - EXPORT GPDMA1_Channel1_IRQHandler [WEAK] - EXPORT GPDMA1_Channel2_IRQHandler [WEAK] - EXPORT GPDMA1_Channel3_IRQHandler [WEAK] - EXPORT GPDMA1_Channel4_IRQHandler [WEAK] - EXPORT GPDMA1_Channel5_IRQHandler [WEAK] - EXPORT GPDMA1_Channel6_IRQHandler [WEAK] - EXPORT GPDMA1_Channel7_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT DAC1_IRQHandler [WEAK] - EXPORT FDCAN1_IT0_IRQHandler [WEAK] - EXPORT FDCAN1_IT1_IRQHandler [WEAK] - EXPORT TIM1_BRK_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT TIM8_BRK_IRQHandler [WEAK] - EXPORT TIM8_UP_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT LPUART1_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - EXPORT LPTIM2_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT COMP_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT CRS_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT OCTOSPI1_IRQHandler [WEAK] - EXPORT PWR_S3WU_IRQHandler [WEAK] - EXPORT SDMMC1_IRQHandler [WEAK] - EXPORT SDMMC2_IRQHandler [WEAK] - EXPORT GPDMA1_Channel8_IRQHandler [WEAK] - EXPORT GPDMA1_Channel9_IRQHandler [WEAK] - EXPORT GPDMA1_Channel10_IRQHandler [WEAK] - EXPORT GPDMA1_Channel11_IRQHandler [WEAK] - EXPORT GPDMA1_Channel12_IRQHandler [WEAK] - EXPORT GPDMA1_Channel13_IRQHandler [WEAK] - EXPORT GPDMA1_Channel14_IRQHandler [WEAK] - EXPORT GPDMA1_Channel15_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT AES_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT HASH_IRQHandler [WEAK] - EXPORT PKA_IRQHandler [WEAK] - EXPORT LPTIM3_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT I2C4_ER_IRQHandler [WEAK] - EXPORT I2C4_EV_IRQHandler [WEAK] - EXPORT MDF1_FLT0_IRQHandler [WEAK] - EXPORT MDF1_FLT1_IRQHandler [WEAK] - EXPORT MDF1_FLT2_IRQHandler [WEAK] - EXPORT MDF1_FLT3_IRQHandler [WEAK] - EXPORT UCPD1_IRQHandler [WEAK] - EXPORT ICACHE_IRQHandler [WEAK] - EXPORT OTFDEC1_IRQHandler [WEAK] - EXPORT OTFDEC2_IRQHandler [WEAK] - EXPORT LPTIM4_IRQHandler [WEAK] - EXPORT DCACHE1_IRQHandler [WEAK] - EXPORT ADF1_IRQHandler [WEAK] - EXPORT ADC4_IRQHandler [WEAK] - EXPORT LPDMA1_Channel0_IRQHandler [WEAK] - EXPORT LPDMA1_Channel1_IRQHandler [WEAK] - EXPORT LPDMA1_Channel2_IRQHandler [WEAK] - EXPORT LPDMA1_Channel3_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT DCMI_PSSI_IRQHandler [WEAK] - EXPORT OCTOSPI2_IRQHandler [WEAK] - EXPORT MDF1_FLT4_IRQHandler [WEAK] - EXPORT MDF1_FLT5_IRQHandler [WEAK] - EXPORT CORDIC_IRQHandler [WEAK] - EXPORT FMAC_IRQHandler [WEAK] - EXPORT LSECSSD_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_PVM_IRQHandler -RTC_IRQHandler -RTC_S_IRQHandler -TAMP_IRQHandler -RAMCFG_IRQHandler -FLASH_IRQHandler -FLASH_S_IRQHandler -GTZC_IRQHandler -RCC_IRQHandler -RCC_S_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -EXTI5_IRQHandler -EXTI6_IRQHandler -EXTI7_IRQHandler -EXTI8_IRQHandler -EXTI9_IRQHandler -EXTI10_IRQHandler -EXTI11_IRQHandler -EXTI12_IRQHandler -EXTI13_IRQHandler -EXTI14_IRQHandler -EXTI15_IRQHandler -IWDG_IRQHandler -SAES_IRQHandler -GPDMA1_Channel0_IRQHandler -GPDMA1_Channel1_IRQHandler -GPDMA1_Channel2_IRQHandler -GPDMA1_Channel3_IRQHandler -GPDMA1_Channel4_IRQHandler -GPDMA1_Channel5_IRQHandler -GPDMA1_Channel6_IRQHandler -GPDMA1_Channel7_IRQHandler -ADC1_IRQHandler -DAC1_IRQHandler -FDCAN1_IT0_IRQHandler -FDCAN1_IT1_IRQHandler -TIM1_BRK_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -TIM5_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -TIM8_BRK_IRQHandler -TIM8_UP_IRQHandler -TIM8_TRG_COM_IRQHandler -TIM8_CC_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -LPUART1_IRQHandler -LPTIM1_IRQHandler -LPTIM2_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -COMP_IRQHandler -OTG_FS_IRQHandler -CRS_IRQHandler -FMC_IRQHandler -OCTOSPI1_IRQHandler -PWR_S3WU_IRQHandler -SDMMC1_IRQHandler -SDMMC2_IRQHandler -GPDMA1_Channel8_IRQHandler -GPDMA1_Channel9_IRQHandler -GPDMA1_Channel10_IRQHandler -GPDMA1_Channel11_IRQHandler -GPDMA1_Channel12_IRQHandler -GPDMA1_Channel13_IRQHandler -GPDMA1_Channel14_IRQHandler -GPDMA1_Channel15_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -SAI1_IRQHandler -SAI2_IRQHandler -TSC_IRQHandler -AES_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -HASH_IRQHandler -PKA_IRQHandler -LPTIM3_IRQHandler -SPI3_IRQHandler -I2C4_ER_IRQHandler -I2C4_EV_IRQHandler -MDF1_FLT0_IRQHandler -MDF1_FLT1_IRQHandler -MDF1_FLT2_IRQHandler -MDF1_FLT3_IRQHandler -UCPD1_IRQHandler -ICACHE_IRQHandler -OTFDEC1_IRQHandler -OTFDEC2_IRQHandler -LPTIM4_IRQHandler -DCACHE1_IRQHandler -ADF1_IRQHandler -ADC4_IRQHandler -LPDMA1_Channel0_IRQHandler -LPDMA1_Channel1_IRQHandler -LPDMA1_Channel2_IRQHandler -LPDMA1_Channel3_IRQHandler -DMA2D_IRQHandler -DCMI_PSSI_IRQHandler -OCTOSPI2_IRQHandler -MDF1_FLT4_IRQHandler -MDF1_FLT5_IRQHandler -CORDIC_IRQHandler -FMAC_IRQHandler -LSECSSD_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - END diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/STM32CubeMX.ioc b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/STM32CubeMX.ioc deleted file mode 100644 index a0b4bdbcc..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/STM32CubeMX.ioc +++ /dev/null @@ -1,588 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -CAD.formats= -CAD.pinconfig= -CAD.provider= -CORTEX_M33_NS.userName=CORTEX_M33 -File.Version=6 -GPIO.groupedBy= -I2C1.IPParameters=Timing -I2C1.Timing=0x30909DEC -I2C2.IPParameters=Timing -I2C2.Timing=0x30909DEC -KeepUserPlacement=false -MMTAppRegionsCount=0 -MMTConfigApplied=false -Mcu.CPN=STM32U585AII6Q -Mcu.ContextProject=TrustZoneDisabled -Mcu.Family=STM32U5 -Mcu.IP0=ADF1 -Mcu.IP1=CORTEX_M33_NS -Mcu.IP10=OCTOSPI1 -Mcu.IP11=OCTOSPI2 -Mcu.IP12=PWR -Mcu.IP13=RCC -Mcu.IP14=SPI2 -Mcu.IP15=SYS -Mcu.IP16=UART4 -Mcu.IP17=UCPD1 -Mcu.IP18=USART1 -Mcu.IP19=USB_OTG_FS -Mcu.IP2=DEBUG -Mcu.IP3=I2C1 -Mcu.IP4=I2C2 -Mcu.IP5=ICACHE -Mcu.IP6=LPBAM -Mcu.IP7=LPBAMQUEUE -Mcu.IP8=MEMORYMAP -Mcu.IP9=NVIC -Mcu.IPNb=20 -Mcu.Name=STM32U585AIIxQ -Mcu.Package=UFBGA169 -Mcu.Pin0=PG15 -Mcu.Pin1=PC11 -Mcu.Pin10=PA14 (JTCK/SWCLK) -Mcu.Pin11=PH10 -Mcu.Pin12=PC14-OSC32_IN (PC14) -Mcu.Pin13=PE3 -Mcu.Pin14=PB9 -Mcu.Pin15=PB3 (JTDO/TRACESWO) -Mcu.Pin16=PD7 -Mcu.Pin17=PD3 -Mcu.Pin18=PH11 -Mcu.Pin19=PC15-OSC32_OUT (PC15) -Mcu.Pin2=PA15 (JTDI) -Mcu.Pin20=PF0 -Mcu.Pin21=PC13 -Mcu.Pin22=PB8 -Mcu.Pin23=PH9 -Mcu.Pin24=PH4 -Mcu.Pin25=PH6 -Mcu.Pin26=PF8 -Mcu.Pin27=PF1 -Mcu.Pin28=PF2 -Mcu.Pin29=PD1 -Mcu.Pin3=PI5 -Mcu.Pin30=PH7 -Mcu.Pin31=PH5 -Mcu.Pin32=PH2 -Mcu.Pin33=PA10 -Mcu.Pin34=PA13 (JTMS/SWDIO) -Mcu.Pin35=PA12 -Mcu.Pin36=PF7 -Mcu.Pin37=PF9 -Mcu.Pin38=PF3 -Mcu.Pin39=PF4 -Mcu.Pin4=PI0 -Mcu.Pin40=PA9 -Mcu.Pin41=PA11 -Mcu.Pin42=PF10 -Mcu.Pin43=PF6 -Mcu.Pin44=PE10 -Mcu.Pin45=PG6 -Mcu.Pin46=PH1-OSC_OUT (PH1) -Mcu.Pin47=PE9 -Mcu.Pin48=PG5 -Mcu.Pin49=PD14 -Mcu.Pin5=PH12 -Mcu.Pin50=PC3 -Mcu.Pin51=PF12 -Mcu.Pin52=PE8 -Mcu.Pin53=PB10 -Mcu.Pin54=PD10 -Mcu.Pin55=PD13 -Mcu.Pin56=PG2 -Mcu.Pin57=PF14 -Mcu.Pin58=PB11 -Mcu.Pin59=PB12 -Mcu.Pin6=PH3-BOOT0 -Mcu.Pin60=PB15 -Mcu.Pin61=PF11 -Mcu.Pin62=PE11 -Mcu.Pin63=PB1 -Mcu.Pin64=PF15 -Mcu.Pin65=VP_ICACHE_VS_ICACHE -Mcu.Pin66=VP_LPBAMQUEUE_VS_QUEUE -Mcu.Pin67=VP_OCTOSPI1_VS_octo -Mcu.Pin68=VP_OCTOSPI2_VS_octo -Mcu.Pin69=VP_PWR_VS_DBSignals -Mcu.Pin7=PB5 -Mcu.Pin70=VP_PWR_VS_SECSignals -Mcu.Pin71=VP_PWR_VS_LPOM -Mcu.Pin72=VP_SYS_VS_tim17 -Mcu.Pin73=VP_LPBAM_VS_SIG1 -Mcu.Pin74=VP_LPBAM_VS_SIG4 -Mcu.Pin75=VP_MEMORYMAP_VS_MEMORYMAP -Mcu.Pin8=PD4 -Mcu.Pin9=PC10 -Mcu.PinsNb=76 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32U585AIIxQ -MxCube.Version=6.11.0 -MxDb.Version=DB.6.0.110 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false -NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:false\:false\:true\:false -NVIC.TIM17_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:true -NVIC.TimeBase=TIM17_IRQn -NVIC.TimeBaseIP=TIM17 -NVIC.USART1_IRQn=true\:0\:0\:false\:false\:true\:true\:true\:true -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -OCTOSPI1.ChipSelectBoundary=10 -OCTOSPI1.ClockPrescaler=2 -OCTOSPI1.DelayBlockBypass=HAL_OSPI_DELAY_BLOCK_USED -OCTOSPI1.DelayHoldQuarterCycle=HAL_OSPI_DHQC_ENABLE -OCTOSPI1.DeviceSize=23 -OCTOSPI1.IPParameters=MemoryType,DeviceSize,ClockPrescaler,DelayHoldQuarterCycle,ChipSelectBoundary,Refresh,DelayBlockBypass -OCTOSPI1.MemoryType=HAL_OSPI_MEMTYPE_APMEMORY -OCTOSPI1.Refresh=100 -OCTOSPI2.ChipSelectBoundary=0 -OCTOSPI2.ChipSelectHighTime=2 -OCTOSPI2.ClockPrescaler=4 -OCTOSPI2.DelayBlockBypass=HAL_OSPI_DELAY_BLOCK_USED -OCTOSPI2.DelayHoldQuarterCycle=HAL_OSPI_DHQC_ENABLE -OCTOSPI2.DeviceSize=26 -OCTOSPI2.FifoThreshold=4 -OCTOSPI2.IPParameters=FifoThreshold,MemoryType,DeviceSize,ChipSelectHighTime,ClockPrescaler,DelayHoldQuarterCycle,ChipSelectBoundary,DelayBlockBypass -OCTOSPI2.MemoryType=HAL_OSPI_MEMTYPE_MACRONIX -PA10.GPIOParameters=GPIO_Label -PA10.GPIO_Label=T.VCP_RX -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA11.GPIOParameters=GPIO_Label -PA11.GPIO_Label=USB.C_P -PA11.Locked=true -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.GPIOParameters=GPIO_Label -PA12.GPIO_Label=USB.C_P -PA12.Locked=true -PA12.Mode=Device_Only -PA12.Signal=USB_OTG_FS_DP -PA13\ (JTMS/SWDIO).GPIOParameters=GPIO_Label -PA13\ (JTMS/SWDIO).GPIO_Label=T.SWDIO -PA13\ (JTMS/SWDIO).Locked=true -PA13\ (JTMS/SWDIO).Mode=Trace_Asynchronous_SW -PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO -PA14\ (JTCK/SWCLK).GPIOParameters=GPIO_Label -PA14\ (JTCK/SWCLK).GPIO_Label=T.SWCLK -PA14\ (JTCK/SWCLK).Locked=true -PA14\ (JTCK/SWCLK).Mode=Trace_Asynchronous_SW -PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK -PA15\ (JTDI).GPIOParameters=GPIO_Label -PA15\ (JTDI).GPIO_Label=USB.UCPD_CC1 -PA15\ (JTDI).Locked=true -PA15\ (JTDI).Mode=Dual_Role_AllSignals -PA15\ (JTDI).Signal=UCPD1_CC1 -PA9.GPIOParameters=GPIO_Label -PA9.GPIO_Label=T.VCP_TX -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB1.GPIOParameters=GPIO_Label -PB1.GPIO_Label=MIC.SDIN0 -PB1.Locked=true -PB1.Signal=MDF1_SDI0 -PB10.GPIOParameters=GPIO_Label -PB10.GPIO_Label=OCTOSPI.R_CLK_P -PB10.Locked=true -PB10.Mode=O1_P1_CLK -PB10.Signal=OCTOSPIM_P1_CLK -PB11.GPIOParameters=GPIO_Label -PB11.GPIO_Label=OCTOSPI.R_NCS -PB11.Locked=true -PB11.Mode=OCTOSPI1_Port1_NCS -PB11.Signal=OCTOSPIM_P1_NCS -PB12.GPIOParameters=GPIO_Label -PB12.GPIO_Label=WRLS.SPI2_NSS -PB12.Locked=true -PB12.Mode=NSS_Signal_Hard_Output -PB12.Signal=SPI2_NSS -PB15.GPIOParameters=GPIO_Label -PB15.GPIO_Label=USB.UCPD_CC2 -PB15.Locked=true -PB15.Mode=Dual_Role_AllSignals -PB15.Signal=UCPD1_CC2 -PB3\ (JTDO/TRACESWO).GPIOParameters=GPIO_Label -PB3\ (JTDO/TRACESWO).GPIO_Label=T.SWO -PB3\ (JTDO/TRACESWO).Locked=true -PB3\ (JTDO/TRACESWO).Mode=Trace_Asynchronous_SW -PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO -PB5.GPIOParameters=GPIO_Label -PB5.GPIO_Label=UCPD_PWR -PB5.Locked=true -PB5.Signal=GPIO_Output -PB8.Locked=true -PB8.Mode=I2C -PB8.Signal=I2C1_SCL -PB9.Locked=true -PB9.Mode=I2C -PB9.Signal=I2C1_SDA -PC10.GPIOParameters=GPIO_Label -PC10.GPIO_Label=WRLS.UART4_TX -PC10.Locked=true -PC10.Mode=Asynchronous -PC10.Signal=UART4_TX -PC11.GPIOParameters=GPIO_Label -PC11.GPIO_Label=WRLS.UART4_RX -PC11.Locked=true -PC11.Mode=Asynchronous -PC11.Signal=UART4_RX -PC13.GPIOParameters=GPIO_Label -PC13.GPIO_Label=USER_Button -PC13.Locked=true -PC13.Signal=GPIO_Input -PC14-OSC32_IN\ (PC14).GPIOParameters=GPIO_Label -PC14-OSC32_IN\ (PC14).GPIO_Label=PC14-OSC32_IN -PC14-OSC32_IN\ (PC14).Locked=true -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (PC15).GPIOParameters=GPIO_Label -PC15-OSC32_OUT\ (PC15).GPIO_Label=PC15-OSC32_OUT -PC15-OSC32_OUT\ (PC15).Locked=true -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PC3.GPIOParameters=GPIO_Label -PC3.GPIO_Label=OCTOSPI.R_IO6 -PC3.Locked=true -PC3.Mode=OCTOSPI1_IOH_Port1H -PC3.Signal=OCTOSPIM_P1_IO6 -PD1.GPIOParameters=GPIO_Label -PD1.GPIO_Label=WRLS.SPI2_SCK -PD1.Locked=true -PD1.Mode=Full_Duplex_Master -PD1.Signal=SPI2_SCK -PD10.GPIOParameters=GPIO_Label -PD10.GPIO_Label=Mems.INT_IIS2MDC -PD10.Locked=true -PD10.Signal=GPIO_Input -PD13.GPIOParameters=GPIO_Label -PD13.GPIO_Label=USB.IANA -PD13.Locked=true -PD13.Signal=GPIO_Input -PD14.GPIOParameters=GPIO_Label -PD14.GPIO_Label=WRLS.NOTIFY -PD14.Locked=true -PD14.Signal=GPIO_Input -PD3.GPIOParameters=GPIO_Label -PD3.GPIO_Label=WRLS.SPI2_MISO -PD3.Locked=true -PD3.Mode=Full_Duplex_Master -PD3.Signal=SPI2_MISO -PD4.GPIOParameters=GPIO_Label -PD4.GPIO_Label=WRLS.SPI2_MOSI -PD4.Locked=true -PD4.Mode=Full_Duplex_Master -PD4.Signal=SPI2_MOSI -PD7.GPIOParameters=GPIO_Label -PD7.GPIO_Label=OCTOSPI.R_IO7 -PD7.Locked=true -PD7.Mode=OCTOSPI1_IOH_Port1H -PD7.Signal=OCTOSPIM_P1_IO7 -PE10.GPIOParameters=GPIO_Label -PE10.GPIO_Label=MIC.SDINx -PE10.Locked=true -PE10.Mode=MOD_ADF_CCK -PE10.Signal=ADF1_SDI0 -PE11.GPIOParameters=GPIO_Label -PE11.GPIO_Label=Mems.ISM330DLC_INT1 -PE11.Locked=true -PE11.Signal=GPIO_Input -PE3.GPIOParameters=GPIO_Label -PE3.GPIO_Label=OCTOSPI.R_DQS -PE3.Locked=true -PE3.Mode=OCTOSPI1_Port1_DQS -PE3.Signal=OCTOSPIM_P1_DQS -PE8.GPIOParameters=GPIO_Label -PE8.GPIO_Label=USB.UCPD_FLT -PE8.Locked=true -PE8.Signal=GPIO_Input -PE9.GPIOParameters=GPIO_Label -PE9.GPIO_Label=MIC.CCK0 -PE9.Locked=true -PE9.Mode=MOD_MDF_CCK0 -PE9.Signal=ADF1_CCK0 -PF0.GPIOParameters=GPIO_Label -PF0.GPIO_Label=OCTOSPI.F_IO0 -PF0.Locked=true -PF0.Mode=OCTOSPI2_IOL_Port2L -PF0.Signal=OCTOSPIM_P2_IO0 -PF1.GPIOParameters=GPIO_Label -PF1.GPIO_Label=OCTOSPI.F_IO1 -PF1.Locked=true -PF1.Mode=OCTOSPI2_IOL_Port2L -PF1.Signal=OCTOSPIM_P2_IO1 -PF10.GPIOParameters=GPIO_Label -PF10.GPIO_Label=MIC.CCK1 -PF10.Locked=true -PF10.Signal=MDF1_CCK1 -PF11.GPIOParameters=GPIO_Label -PF11.GPIO_Label=Mems.STSAFE_RESET -PF11.Locked=true -PF11.Signal=GPIO_Output -PF12.GPIOParameters=GPIO_Label -PF12.GPIO_Label=OCTOSPI.F_DQS -PF12.Locked=true -PF12.Mode=OCTOSPI2_Port2_DQS -PF12.Signal=OCTOSPIM_P2_DQS -PF14.GPIOParameters=GPIO_Label -PF14.GPIO_Label=USB.VBUS_SENSE -PF14.Locked=true -PF14.Signal=GPIO_Input -PF15.GPIOParameters=GPIO_Label -PF15.GPIO_Label=WRLS.WKUP_W -PF15.Locked=true -PF15.Signal=GPIO_Output -PF2.GPIOParameters=GPIO_Label -PF2.GPIO_Label=OCTOSPI.F_IO2 -PF2.Locked=true -PF2.Mode=OCTOSPI2_IOL_Port2L -PF2.Signal=OCTOSPIM_P2_IO2 -PF3.GPIOParameters=GPIO_Label -PF3.GPIO_Label=OCTOSPI.F_IO3 -PF3.Locked=true -PF3.Mode=OCTOSPI2_IOL_Port2L -PF3.Signal=OCTOSPIM_P2_IO3 -PF4.GPIOParameters=GPIO_Label -PF4.GPIO_Label=OCTOSPI.F_CLK_P -PF4.Locked=true -PF4.Mode=O2_P2_CLK -PF4.Signal=OCTOSPIM_P2_CLK -PF6.GPIOParameters=GPIO_Label -PF6.GPIO_Label=OCTOSPI.R_IO3 -PF6.Locked=true -PF6.Mode=OCTOSPI1_IOL_Port1L -PF6.Signal=OCTOSPIM_P1_IO3 -PF7.GPIOParameters=GPIO_Label -PF7.GPIO_Label=OCTOSPI.R_IO2 -PF7.Locked=true -PF7.Mode=OCTOSPI1_IOL_Port1L -PF7.Signal=OCTOSPIM_P1_IO2 -PF8.GPIOParameters=GPIO_Label -PF8.GPIO_Label=OCTOSPI.R_IO0 -PF8.Locked=true -PF8.Mode=OCTOSPI1_IOL_Port1L -PF8.Signal=OCTOSPIM_P1_IO0 -PF9.GPIOParameters=GPIO_Label -PF9.GPIO_Label=OCTOSPI.R_IO1 -PF9.Locked=true -PF9.Mode=OCTOSPI1_IOL_Port1L -PF9.Signal=OCTOSPIM_P1_IO1 -PG15.GPIOParameters=GPIO_Label -PG15.GPIO_Label=WRLS.FLOW -PG15.Locked=true -PG15.Signal=GPIO_Input -PG2.GPIOParameters=GPIO_Label -PG2.GPIO_Label=Mems.INT_LPS22HH -PG2.Locked=true -PG2.Signal=GPIO_Input -PG5.GPIOParameters=GPIO_Label -PG5.GPIO_Label=Mems.VLX_GPIO -PG5.Locked=true -PG5.Signal=GPIO_Input -PG6.GPIOParameters=GPIO_Label -PG6.GPIO_Label=WRLS.WKUP_B -PG6.Locked=true -PG6.Signal=GPIO_Output -PH1-OSC_OUT\ (PH1).GPIOParameters=GPIO_Label -PH1-OSC_OUT\ (PH1).GPIO_Label=Mems.VL53_xshut -PH1-OSC_OUT\ (PH1).Locked=true -PH1-OSC_OUT\ (PH1).Signal=GPIO_Output -PH10.GPIOParameters=GPIO_Label -PH10.GPIO_Label=OCTOSPI.F_IO5 -PH10.Locked=true -PH10.Mode=OCTOSPI2_IOH_Port2H -PH10.Signal=OCTOSPIM_P2_IO5 -PH11.GPIOParameters=GPIO_Label -PH11.GPIO_Label=OCTOSPI.F_IO6 -PH11.Locked=true -PH11.Mode=OCTOSPI2_IOH_Port2H -PH11.Signal=OCTOSPIM_P2_IO6 -PH12.GPIOParameters=GPIO_Label -PH12.GPIO_Label=OCTOSPI.F_IO7 -PH12.Locked=true -PH12.Mode=OCTOSPI2_IOH_Port2H -PH12.Signal=OCTOSPIM_P2_IO7 -PH2.GPIOParameters=GPIO_Label -PH2.GPIO_Label=OCTOSPI.R_IO4 -PH2.Locked=true -PH2.Mode=OCTOSPI1_IOH_Port1H -PH2.Signal=OCTOSPIM_P1_IO4 -PH3-BOOT0.GPIOParameters=GPIO_Label -PH3-BOOT0.GPIO_Label=PH3-BOOT0 -PH3-BOOT0.Locked=true -PH3-BOOT0.Signal=GPIO_Input -PH4.Locked=true -PH4.Mode=I2C -PH4.Signal=I2C2_SCL -PH5.Locked=true -PH5.Mode=I2C -PH5.Signal=I2C2_SDA -PH6.GPIOParameters=GPIO_Label -PH6.GPIO_Label=LED_RED -PH6.Locked=true -PH6.Signal=GPIO_Output -PH7.GPIOParameters=GPIO_Label -PH7.GPIO_Label=LED_GREEN -PH7.Locked=true -PH7.Signal=GPIO_Output -PH9.GPIOParameters=GPIO_Label -PH9.GPIO_Label=OCTOSPI.F_IO4 -PH9.Locked=true -PH9.Mode=OCTOSPI2_IOH_Port2H -PH9.Signal=OCTOSPIM_P2_IO4 -PI0.GPIOParameters=GPIO_Label -PI0.GPIO_Label=OCTOSPI.R_IO5 -PI0.Locked=true -PI0.Mode=OCTOSPI1_IOH_Port1H -PI0.Signal=OCTOSPIM_P1_IO5 -PI5.GPIOParameters=GPIO_Label -PI5.GPIO_Label=OCTOSPI.F_NCS -PI5.Locked=true -PI5.Mode=OCTOSPI2_Port2_NCS -PI5.Signal=OCTOSPIM_P2_NCS -PWR.IPParameters=PowerMode -PWR.PowerMode=PWR_SMPS_SUPPLY -PinOutPanel.CurrentBGAView=Top -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32U585AIIxQ -ProjectManager.FirmwarePackage=STM32Cube FW_U5 V1.5.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x400 -ProjectManager.KeepUserCode=true -ProjectManager.LPBAM.generateCode= -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=1 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=STM32CubeMX.ioc -ProjectManager.ProjectName=STM32CubeMX -ProjectManager.ProjectStructure= -ProjectManager.RegisterCallBack= -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5.32 -ProjectManager.ToolChainLocation= -ProjectManager.UAScriptAfterPath= -ProjectManager.UAScriptBeforePath= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADF1_Init-ADF1-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_ICACHE_Init-ICACHE-false-HAL-true,7-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,8-MX_OCTOSPI2_Init-OCTOSPI2-false-HAL-true,9-MX_SPI2_Init-SPI2-false-HAL-true,10-MX_UART4_Init-UART4-false-HAL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_UCPD1_Init-UCPD1-false-LL-true,13-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true -RCC.ADCFreq_Value=16000000 -RCC.ADF1Freq_Value=160000000 -RCC.AHBFreq_Value=160000000 -RCC.APB1Freq_Value=160000000 -RCC.APB1TimFreq_Value=160000000 -RCC.APB2Freq_Value=160000000 -RCC.APB2TimFreq_Value=160000000 -RCC.APB3Freq_Value=160000000 -RCC.CK48Freq_Value=48000000 -RCC.CRSFreq_Value=48000000 -RCC.CortexFreq_Value=160000000 -RCC.DACCLockSelectionVirtual=RCC_DAC1CLKSOURCE_LSI -RCC.DACFreq_Value=32000 -RCC.EPOD_VALUE=4000000 -RCC.FCLKCortexFreq_Value=160000000 -RCC.FDCANFreq_Value=160000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=160000000 -RCC.HSE_VALUE=16000000 -RCC.HSI48_VALUE=48000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=160000000 -RCC.I2C2Freq_Value=160000000 -RCC.I2C3Freq_Value=160000000 -RCC.I2C4Freq_Value=160000000 -RCC.IPParameters=ADCFreq_Value,ADF1Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CK48Freq_Value,CRSFreq_Value,CortexFreq_Value,DACCLockSelectionVirtual,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIDIV_VALUE,LSI_VALUE,MCO1PinFreq_Value,MDF1Freq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,RNGFreq_Value,SAESFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value -RCC.LPTIM2Freq_Value=160000000 -RCC.LPUART1Freq_Value=160000000 -RCC.LSCOPinFreq_Value=32000 -RCC.LSIDIV_VALUE=32000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=160000000 -RCC.MDF1Freq_Value=160000000 -RCC.MSI_VALUE=4000000 -RCC.OCTOSPIMFreq_Value=160000000 -RCC.PLL2PoutputFreq_Value=258000000 -RCC.PLL2QoutputFreq_Value=258000000 -RCC.PLL2RoutputFreq_Value=258000000 -RCC.PLL3PoutputFreq_Value=258000000 -RCC.PLL3QoutputFreq_Value=258000000 -RCC.PLL3RoutputFreq_Value=258000000 -RCC.PLLN=80 -RCC.PLLPoutputFreq_Value=160000000 -RCC.PLLQoutputFreq_Value=160000000 -RCC.PLLRCLKFreq_Value=160000000 -RCC.RNGFreq_Value=48000000 -RCC.SAESFreq_Value=48000000 -RCC.SAI1Freq_Value=258000000 -RCC.SAI2Freq_Value=258000000 -RCC.SDMMCFreq_Value=160000000 -RCC.SPI1Freq_Value=160000000 -RCC.SPI2Freq_Value=160000000 -RCC.SPI3Freq_Value=160000000 -RCC.SYSCLKFreq_VALUE=160000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=160000000 -RCC.UART5Freq_Value=160000000 -RCC.USART1Freq_Value=160000000 -RCC.USART2Freq_Value=160000000 -RCC.USART3Freq_Value=160000000 -RCC.USBFreq_Value=48000000 -RCC.VCOInput2Freq_Value=4000000 -RCC.VCOInput3Freq_Value=4000000 -RCC.VCOInputFreq_Value=4000000 -RCC.VCOOutputFreq_Value=320000000 -RCC.VCOPLL2OutputFreq_Value=516000000 -RCC.VCOPLL3OutputFreq_Value=516000000 -SPI2.CalculateBaudRate=80.0 MBits/s -SPI2.Direction=SPI_DIRECTION_2LINES -SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS -SPI2.Mode=SPI_MODE_MASTER -SPI2.VirtualNSS=VM_NSSHARD -SPI2.VirtualType=VM_MASTER -USART1.IPParameters=VirtualMode-Asynchronous -USART1.VirtualMode-Asynchronous=VM_ASYNC -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache -VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE -VP_LPBAMQUEUE_VS_QUEUE.Mode=QUEUEMODE -VP_LPBAMQUEUE_VS_QUEUE.Signal=LPBAMQUEUE_VS_QUEUE -VP_LPBAM_VS_SIG1.Mode=SmartRun -VP_LPBAM_VS_SIG1.Signal=LPBAM_VS_SIG1 -VP_LPBAM_VS_SIG4.Mode=LPDMA1 -VP_LPBAM_VS_SIG4.Signal=LPBAM_VS_SIG4 -VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg -VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP -VP_OCTOSPI1_VS_octo.Mode=octo_mode -VP_OCTOSPI1_VS_octo.Signal=OCTOSPI1_VS_octo -VP_OCTOSPI2_VS_octo.Mode=octo_mode -VP_OCTOSPI2_VS_octo.Signal=OCTOSPI2_VS_octo -VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals -VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals -VP_PWR_VS_LPOM.Mode=PowerOptimisation -VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM -VP_PWR_VS_SECSignals.Mode=Security/Privilege -VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals -VP_SYS_VS_tim17.Mode=TIM17 -VP_SYS_VS_tim17.Signal=SYS_VS_tim17 -board=B-U585I-IOT02A -boardIOC=true diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/main.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/main.c deleted file mode 100644 index 1418666c2..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/main.c +++ /dev/null @@ -1,934 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file : main.c - * @brief : Main program body - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ -/* Includes ------------------------------------------------------------------*/ -#include "main.h" - -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -#include "cmsis_vio.h" -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN PTD */ - -/* USER CODE END PTD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -MDF_HandleTypeDef AdfHandle0; -MDF_FilterConfigTypeDef AdfFilterConfig0; - -I2C_HandleTypeDef hi2c1; -I2C_HandleTypeDef hi2c2; - -OSPI_HandleTypeDef hospi1; -OSPI_HandleTypeDef hospi2; - -SPI_HandleTypeDef hspi2; - -UART_HandleTypeDef huart4; -UART_HandleTypeDef huart1; - -PCD_HandleTypeDef hpcd_USB_OTG_FS; - -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -void SystemClock_Config(void); -static void SystemPower_Config(void); -static void MX_GPIO_Init(void); -static void MX_ADF1_Init(void); -static void MX_I2C1_Init(void); -static void MX_I2C2_Init(void); -static void MX_ICACHE_Init(void); -static void MX_OCTOSPI1_Init(void); -static void MX_OCTOSPI2_Init(void); -static void MX_SPI2_Init(void); -static void MX_UART4_Init(void); -static void MX_USART1_UART_Init(void); -static void MX_UCPD1_Init(void); -static void MX_USB_OTG_FS_PCD_Init(void); -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/** - * @brief The application entry point. - * @retval int - */ -int main(void) -{ - - /* USER CODE BEGIN 1 */ - - /* USER CODE END 1 */ - - /* MCU Configuration--------------------------------------------------------*/ - - /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ - HAL_Init(); - - /* USER CODE BEGIN Init */ - - /* USER CODE END Init */ - - /* Configure the system clock */ - SystemClock_Config(); - - /* Configure the System Power */ - SystemPower_Config(); - - /* USER CODE BEGIN SysInit */ - SystemCoreClockUpdate(); - /* USER CODE END SysInit */ - - /* Initialize all configured peripherals */ - MX_GPIO_Init(); - MX_ADF1_Init(); - MX_I2C1_Init(); - MX_I2C2_Init(); - MX_ICACHE_Init(); - MX_OCTOSPI1_Init(); - MX_OCTOSPI2_Init(); - MX_SPI2_Init(); - MX_UART4_Init(); - MX_USART1_UART_Init(); - MX_UCPD1_Init(); - MX_USB_OTG_FS_PCD_Init(); - /* USER CODE BEGIN 2 */ - - stdio_init(); /* Initialize STDIO */ - - vioInit(); /* Initialize Virtual I/O */ - - app_main(); /* Application */ - - /* USER CODE END 2 */ - - /* Infinite loop */ - /* USER CODE BEGIN WHILE */ - while (1) - { - /* USER CODE END WHILE */ - - /* USER CODE BEGIN 3 */ - } - /* USER CODE END 3 */ -} - -/** - * @brief System Clock Configuration - * @retval None - */ -void SystemClock_Config(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - /** Configure the main internal regulator output voltage - */ - if (HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48|RCC_OSCILLATORTYPE_HSI - |RCC_OSCILLATORTYPE_MSI; - RCC_OscInitStruct.HSIState = RCC_HSI_ON; - RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; - RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIState = RCC_MSI_ON; - RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; - RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_4; - RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; - RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; - RCC_OscInitStruct.PLL.PLLMBOOST = RCC_PLLMBOOST_DIV1; - RCC_OscInitStruct.PLL.PLLM = 1; - RCC_OscInitStruct.PLL.PLLN = 80; - RCC_OscInitStruct.PLL.PLLP = 2; - RCC_OscInitStruct.PLL.PLLQ = 2; - RCC_OscInitStruct.PLL.PLLR = 2; - RCC_OscInitStruct.PLL.PLLRGE = RCC_PLLVCIRANGE_0; - RCC_OscInitStruct.PLL.PLLFRACN = 0; - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - Error_Handler(); - } - - /** Initializes the CPU, AHB and APB buses clocks - */ - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK|RCC_CLOCKTYPE_SYSCLK - |RCC_CLOCKTYPE_PCLK1|RCC_CLOCKTYPE_PCLK2 - |RCC_CLOCKTYPE_PCLK3; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1; - - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) - { - Error_Handler(); - } -} - -/** - * @brief Power Configuration - * @retval None - */ -static void SystemPower_Config(void) -{ - HAL_PWREx_EnableVddIO2(); - - /* - * Switch to SMPS regulator instead of LDO - */ - if (HAL_PWREx_ConfigSupply(PWR_SMPS_SUPPLY) != HAL_OK) - { - Error_Handler(); - } -/* USER CODE BEGIN PWR */ -/* USER CODE END PWR */ -} - -/** - * @brief ADF1 Initialization Function - * @param None - * @retval None - */ -static void MX_ADF1_Init(void) -{ - - /* USER CODE BEGIN ADF1_Init 0 */ - - /* USER CODE END ADF1_Init 0 */ - - /* USER CODE BEGIN ADF1_Init 1 */ - - /* USER CODE END ADF1_Init 1 */ - - /** - AdfHandle0 structure initialization and HAL_MDF_Init function call - */ - AdfHandle0.Instance = ADF1_Filter0; - AdfHandle0.Init.CommonParam.ProcClockDivider = 1; - AdfHandle0.Init.CommonParam.OutputClock.Activation = DISABLE; - AdfHandle0.Init.SerialInterface.Activation = ENABLE; - AdfHandle0.Init.SerialInterface.Mode = MDF_SITF_LF_MASTER_SPI_MODE; - AdfHandle0.Init.SerialInterface.ClockSource = MDF_SITF_CCK0_SOURCE; - AdfHandle0.Init.SerialInterface.Threshold = 4; - AdfHandle0.Init.FilterBistream = MDF_BITSTREAM0_FALLING; - if (HAL_MDF_Init(&AdfHandle0) != HAL_OK) - { - Error_Handler(); - } - - /** - AdfFilterConfig0 structure initialization - - WARNING : only structure is filled, no specific init function call for filter - */ - AdfFilterConfig0.DataSource = MDF_DATA_SOURCE_BSMX; - AdfFilterConfig0.Delay = 0; - AdfFilterConfig0.CicMode = MDF_ONE_FILTER_SINC4; - AdfFilterConfig0.DecimationRatio = 2; - AdfFilterConfig0.Gain = 0; - AdfFilterConfig0.ReshapeFilter.Activation = DISABLE; - AdfFilterConfig0.HighPassFilter.Activation = DISABLE; - AdfFilterConfig0.SoundActivity.Activation = DISABLE; - AdfFilterConfig0.AcquisitionMode = MDF_MODE_ASYNC_CONT; - AdfFilterConfig0.FifoThreshold = MDF_FIFO_THRESHOLD_NOT_EMPTY; - AdfFilterConfig0.DiscardSamples = 0; - /* USER CODE BEGIN ADF1_Init 2 */ - - /* USER CODE END ADF1_Init 2 */ - -} - -/** - * @brief I2C1 Initialization Function - * @param None - * @retval None - */ -static void MX_I2C1_Init(void) -{ - - /* USER CODE BEGIN I2C1_Init 0 */ - - /* USER CODE END I2C1_Init 0 */ - - /* USER CODE BEGIN I2C1_Init 1 */ - - /* USER CODE END I2C1_Init 1 */ - hi2c1.Instance = I2C1; - hi2c1.Init.Timing = 0x30909DEC; - hi2c1.Init.OwnAddress1 = 0; - hi2c1.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - hi2c1.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; - hi2c1.Init.OwnAddress2 = 0; - hi2c1.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - hi2c1.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; - hi2c1.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - if (HAL_I2C_Init(&hi2c1) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Analogue filter - */ - if (HAL_I2CEx_ConfigAnalogFilter(&hi2c1, I2C_ANALOGFILTER_ENABLE) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Digital filter - */ - if (HAL_I2CEx_ConfigDigitalFilter(&hi2c1, 0) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN I2C1_Init 2 */ - - /* USER CODE END I2C1_Init 2 */ - -} - -/** - * @brief I2C2 Initialization Function - * @param None - * @retval None - */ -static void MX_I2C2_Init(void) -{ - - /* USER CODE BEGIN I2C2_Init 0 */ - - /* USER CODE END I2C2_Init 0 */ - - /* USER CODE BEGIN I2C2_Init 1 */ - - /* USER CODE END I2C2_Init 1 */ - hi2c2.Instance = I2C2; - hi2c2.Init.Timing = 0x30909DEC; - hi2c2.Init.OwnAddress1 = 0; - hi2c2.Init.AddressingMode = I2C_ADDRESSINGMODE_7BIT; - hi2c2.Init.DualAddressMode = I2C_DUALADDRESS_DISABLE; - hi2c2.Init.OwnAddress2 = 0; - hi2c2.Init.OwnAddress2Masks = I2C_OA2_NOMASK; - hi2c2.Init.GeneralCallMode = I2C_GENERALCALL_DISABLE; - hi2c2.Init.NoStretchMode = I2C_NOSTRETCH_DISABLE; - if (HAL_I2C_Init(&hi2c2) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Analogue filter - */ - if (HAL_I2CEx_ConfigAnalogFilter(&hi2c2, I2C_ANALOGFILTER_ENABLE) != HAL_OK) - { - Error_Handler(); - } - - /** Configure Digital filter - */ - if (HAL_I2CEx_ConfigDigitalFilter(&hi2c2, 0) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN I2C2_Init 2 */ - - /* USER CODE END I2C2_Init 2 */ - -} - -/** - * @brief ICACHE Initialization Function - * @param None - * @retval None - */ -static void MX_ICACHE_Init(void) -{ - - /* USER CODE BEGIN ICACHE_Init 0 */ - - /* USER CODE END ICACHE_Init 0 */ - - /* USER CODE BEGIN ICACHE_Init 1 */ - - /* USER CODE END ICACHE_Init 1 */ - - /** Enable instruction cache in 1-way (direct mapped cache) - */ - if (HAL_ICACHE_ConfigAssociativityMode(ICACHE_1WAY) != HAL_OK) - { - Error_Handler(); - } - if (HAL_ICACHE_Enable() != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN ICACHE_Init 2 */ - - /* USER CODE END ICACHE_Init 2 */ - -} - -/** - * @brief OCTOSPI1 Initialization Function - * @param None - * @retval None - */ -static void MX_OCTOSPI1_Init(void) -{ - - /* USER CODE BEGIN OCTOSPI1_Init 0 */ - - /* USER CODE END OCTOSPI1_Init 0 */ - - OSPIM_CfgTypeDef sOspiManagerCfg = {0}; - HAL_OSPI_DLYB_CfgTypeDef HAL_OSPI_DLYB_Cfg_Struct = {0}; - - /* USER CODE BEGIN OCTOSPI1_Init 1 */ - - /* USER CODE END OCTOSPI1_Init 1 */ - /* OCTOSPI1 parameter configuration*/ - hospi1.Instance = OCTOSPI1; - hospi1.Init.FifoThreshold = 1; - hospi1.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; - hospi1.Init.MemoryType = HAL_OSPI_MEMTYPE_APMEMORY; - hospi1.Init.DeviceSize = 23; - hospi1.Init.ChipSelectHighTime = 1; - hospi1.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; - hospi1.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; - hospi1.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED; - hospi1.Init.ClockPrescaler = 2; - hospi1.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; - hospi1.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE; - hospi1.Init.ChipSelectBoundary = 10; - hospi1.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED; - hospi1.Init.MaxTran = 0; - hospi1.Init.Refresh = 100; - if (HAL_OSPI_Init(&hospi1) != HAL_OK) - { - Error_Handler(); - } - sOspiManagerCfg.ClkPort = 1; - sOspiManagerCfg.DQSPort = 1; - sOspiManagerCfg.NCSPort = 1; - sOspiManagerCfg.IOLowPort = HAL_OSPIM_IOPORT_1_LOW; - sOspiManagerCfg.IOHighPort = HAL_OSPIM_IOPORT_1_HIGH; - if (HAL_OSPIM_Config(&hospi1, &sOspiManagerCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - Error_Handler(); - } - HAL_OSPI_DLYB_Cfg_Struct.Units = 0; - HAL_OSPI_DLYB_Cfg_Struct.PhaseSel = 0; - if (HAL_OSPI_DLYB_SetConfig(&hospi1, &HAL_OSPI_DLYB_Cfg_Struct) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN OCTOSPI1_Init 2 */ - - /* USER CODE END OCTOSPI1_Init 2 */ - -} - -/** - * @brief OCTOSPI2 Initialization Function - * @param None - * @retval None - */ -static void MX_OCTOSPI2_Init(void) -{ - - /* USER CODE BEGIN OCTOSPI2_Init 0 */ - - /* USER CODE END OCTOSPI2_Init 0 */ - - OSPIM_CfgTypeDef sOspiManagerCfg = {0}; - HAL_OSPI_DLYB_CfgTypeDef HAL_OSPI_DLYB_Cfg_Struct = {0}; - - /* USER CODE BEGIN OCTOSPI2_Init 1 */ - - /* USER CODE END OCTOSPI2_Init 1 */ - /* OCTOSPI2 parameter configuration*/ - hospi2.Instance = OCTOSPI2; - hospi2.Init.FifoThreshold = 4; - hospi2.Init.DualQuad = HAL_OSPI_DUALQUAD_DISABLE; - hospi2.Init.MemoryType = HAL_OSPI_MEMTYPE_MACRONIX; - hospi2.Init.DeviceSize = 26; - hospi2.Init.ChipSelectHighTime = 2; - hospi2.Init.FreeRunningClock = HAL_OSPI_FREERUNCLK_DISABLE; - hospi2.Init.ClockMode = HAL_OSPI_CLOCK_MODE_0; - hospi2.Init.WrapSize = HAL_OSPI_WRAP_NOT_SUPPORTED; - hospi2.Init.ClockPrescaler = 4; - hospi2.Init.SampleShifting = HAL_OSPI_SAMPLE_SHIFTING_NONE; - hospi2.Init.DelayHoldQuarterCycle = HAL_OSPI_DHQC_ENABLE; - hospi2.Init.ChipSelectBoundary = 0; - hospi2.Init.DelayBlockBypass = HAL_OSPI_DELAY_BLOCK_USED; - hospi2.Init.MaxTran = 0; - hospi2.Init.Refresh = 0; - if (HAL_OSPI_Init(&hospi2) != HAL_OK) - { - Error_Handler(); - } - sOspiManagerCfg.ClkPort = 2; - sOspiManagerCfg.DQSPort = 2; - sOspiManagerCfg.NCSPort = 2; - sOspiManagerCfg.IOLowPort = HAL_OSPIM_IOPORT_2_LOW; - sOspiManagerCfg.IOHighPort = HAL_OSPIM_IOPORT_2_HIGH; - if (HAL_OSPIM_Config(&hospi2, &sOspiManagerCfg, HAL_OSPI_TIMEOUT_DEFAULT_VALUE) != HAL_OK) - { - Error_Handler(); - } - HAL_OSPI_DLYB_Cfg_Struct.Units = 0; - HAL_OSPI_DLYB_Cfg_Struct.PhaseSel = 0; - if (HAL_OSPI_DLYB_SetConfig(&hospi2, &HAL_OSPI_DLYB_Cfg_Struct) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN OCTOSPI2_Init 2 */ - - /* USER CODE END OCTOSPI2_Init 2 */ - -} - -/** - * @brief SPI2 Initialization Function - * @param None - * @retval None - */ -static void MX_SPI2_Init(void) -{ - - /* USER CODE BEGIN SPI2_Init 0 */ - - /* USER CODE END SPI2_Init 0 */ - - SPI_AutonomousModeConfTypeDef HAL_SPI_AutonomousMode_Cfg_Struct = {0}; - - /* USER CODE BEGIN SPI2_Init 1 */ - - /* USER CODE END SPI2_Init 1 */ - /* SPI2 parameter configuration*/ - hspi2.Instance = SPI2; - hspi2.Init.Mode = SPI_MODE_MASTER; - hspi2.Init.Direction = SPI_DIRECTION_2LINES; - hspi2.Init.DataSize = SPI_DATASIZE_4BIT; - hspi2.Init.CLKPolarity = SPI_POLARITY_LOW; - hspi2.Init.CLKPhase = SPI_PHASE_1EDGE; - hspi2.Init.NSS = SPI_NSS_HARD_OUTPUT; - hspi2.Init.BaudRatePrescaler = SPI_BAUDRATEPRESCALER_2; - hspi2.Init.FirstBit = SPI_FIRSTBIT_MSB; - hspi2.Init.TIMode = SPI_TIMODE_DISABLE; - hspi2.Init.CRCCalculation = SPI_CRCCALCULATION_DISABLE; - hspi2.Init.CRCPolynomial = 0x7; - hspi2.Init.NSSPMode = SPI_NSS_PULSE_ENABLE; - hspi2.Init.NSSPolarity = SPI_NSS_POLARITY_LOW; - hspi2.Init.FifoThreshold = SPI_FIFO_THRESHOLD_01DATA; - hspi2.Init.MasterSSIdleness = SPI_MASTER_SS_IDLENESS_00CYCLE; - hspi2.Init.MasterInterDataIdleness = SPI_MASTER_INTERDATA_IDLENESS_00CYCLE; - hspi2.Init.MasterReceiverAutoSusp = SPI_MASTER_RX_AUTOSUSP_DISABLE; - hspi2.Init.MasterKeepIOState = SPI_MASTER_KEEP_IO_STATE_DISABLE; - hspi2.Init.IOSwap = SPI_IO_SWAP_DISABLE; - hspi2.Init.ReadyMasterManagement = SPI_RDY_MASTER_MANAGEMENT_INTERNALLY; - hspi2.Init.ReadyPolarity = SPI_RDY_POLARITY_HIGH; - if (HAL_SPI_Init(&hspi2) != HAL_OK) - { - Error_Handler(); - } - HAL_SPI_AutonomousMode_Cfg_Struct.TriggerState = SPI_AUTO_MODE_DISABLE; - HAL_SPI_AutonomousMode_Cfg_Struct.TriggerSelection = SPI_GRP1_GPDMA_CH0_TCF_TRG; - HAL_SPI_AutonomousMode_Cfg_Struct.TriggerPolarity = SPI_TRIG_POLARITY_RISING; - if (HAL_SPIEx_SetConfigAutonomousMode(&hspi2, &HAL_SPI_AutonomousMode_Cfg_Struct) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN SPI2_Init 2 */ - - /* USER CODE END SPI2_Init 2 */ - -} - -/** - * @brief UART4 Initialization Function - * @param None - * @retval None - */ -static void MX_UART4_Init(void) -{ - - /* USER CODE BEGIN UART4_Init 0 */ - - /* USER CODE END UART4_Init 0 */ - - /* USER CODE BEGIN UART4_Init 1 */ - - /* USER CODE END UART4_Init 1 */ - huart4.Instance = UART4; - huart4.Init.BaudRate = 115200; - huart4.Init.WordLength = UART_WORDLENGTH_8B; - huart4.Init.StopBits = UART_STOPBITS_1; - huart4.Init.Parity = UART_PARITY_NONE; - huart4.Init.Mode = UART_MODE_TX_RX; - huart4.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart4.Init.OverSampling = UART_OVERSAMPLING_16; - huart4.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart4.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart4.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart4) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart4, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart4, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart4) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN UART4_Init 2 */ - - /* USER CODE END UART4_Init 2 */ - -} - -/** - * @brief USART1 Initialization Function - * @param None - * @retval None - */ -static void MX_USART1_UART_Init(void) -{ - - /* USER CODE BEGIN USART1_Init 0 */ - - /* USER CODE END USART1_Init 0 */ - - /* USER CODE BEGIN USART1_Init 1 */ - - /* USER CODE END USART1_Init 1 */ - huart1.Instance = USART1; - huart1.Init.BaudRate = 115200; - huart1.Init.WordLength = UART_WORDLENGTH_8B; - huart1.Init.StopBits = UART_STOPBITS_1; - huart1.Init.Parity = UART_PARITY_NONE; - huart1.Init.Mode = UART_MODE_TX_RX; - huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; - huart1.Init.OverSampling = UART_OVERSAMPLING_16; - huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; - huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; - huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; - if (HAL_UART_Init(&huart1) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) - { - Error_Handler(); - } - if (HAL_UARTEx_DisableFifoMode(&huart1) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USART1_Init 2 */ - - /* USER CODE END USART1_Init 2 */ - -} - -/** - * @brief UCPD1 Initialization Function - * @param None - * @retval None - */ -static void MX_UCPD1_Init(void) -{ - - /* USER CODE BEGIN UCPD1_Init 0 */ - - /* USER CODE END UCPD1_Init 0 */ - - LL_GPIO_InitTypeDef GPIO_InitStruct = {0}; - - /* Peripheral clock enable */ - LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_UCPD1); - - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOA); - LL_AHB2_GRP1_EnableClock(LL_AHB2_GRP1_PERIPH_GPIOB); - /**UCPD1 GPIO Configuration - PA15 (JTDI) ------> UCPD1_CC1 - PB15 ------> UCPD1_CC2 - */ - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = LL_GPIO_PIN_15; - GPIO_InitStruct.Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = LL_GPIO_PULL_NO; - LL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN UCPD1_Init 1 */ - - /* USER CODE END UCPD1_Init 1 */ - /* USER CODE BEGIN UCPD1_Init 2 */ - - /* USER CODE END UCPD1_Init 2 */ - -} - -/** - * @brief USB_OTG_FS Initialization Function - * @param None - * @retval None - */ -static void MX_USB_OTG_FS_PCD_Init(void) -{ - - /* USER CODE BEGIN USB_OTG_FS_Init 0 */ - - /* USER CODE END USB_OTG_FS_Init 0 */ - - /* USER CODE BEGIN USB_OTG_FS_Init 1 */ - - /* USER CODE END USB_OTG_FS_Init 1 */ - hpcd_USB_OTG_FS.Instance = USB_OTG_FS; - hpcd_USB_OTG_FS.Init.dev_endpoints = 6; - hpcd_USB_OTG_FS.Init.speed = PCD_SPEED_FULL; - hpcd_USB_OTG_FS.Init.phy_itface = PCD_PHY_EMBEDDED; - hpcd_USB_OTG_FS.Init.Sof_enable = DISABLE; - hpcd_USB_OTG_FS.Init.low_power_enable = DISABLE; - hpcd_USB_OTG_FS.Init.lpm_enable = DISABLE; - hpcd_USB_OTG_FS.Init.battery_charging_enable = DISABLE; - hpcd_USB_OTG_FS.Init.use_dedicated_ep1 = DISABLE; - hpcd_USB_OTG_FS.Init.vbus_sensing_enable = DISABLE; - hpcd_USB_OTG_FS.Init.dma_enable = DISABLE; - if (HAL_PCD_Init(&hpcd_USB_OTG_FS) != HAL_OK) - { - Error_Handler(); - } - /* USER CODE BEGIN USB_OTG_FS_Init 2 */ - - /* USER CODE END USB_OTG_FS_Init 2 */ - -} - -/** - * @brief GPIO Initialization Function - * @param None - * @retval None - */ -static void MX_GPIO_Init(void) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; -/* USER CODE BEGIN MX_GPIO_Init_1 */ -/* USER CODE END MX_GPIO_Init_1 */ - - /* GPIO Ports Clock Enable */ - __HAL_RCC_GPIOG_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOA_CLK_ENABLE(); - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(UCPD_PWR_GPIO_Port, UCPD_PWR_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOH, LED_RED_Pin|LED_GREEN_Pin|Mems_VL53_xshut_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(WRLS_WKUP_B_GPIO_Port, WRLS_WKUP_B_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pin Output Level */ - HAL_GPIO_WritePin(GPIOF, Mems_STSAFE_RESET_Pin|WRLS_WKUP_W_Pin, GPIO_PIN_RESET); - - /*Configure GPIO pins : WRLS_FLOW_Pin Mems_VLX_GPIO_Pin Mems_INT_LPS22HH_Pin */ - GPIO_InitStruct.Pin = WRLS_FLOW_Pin|Mems_VLX_GPIO_Pin|Mems_INT_LPS22HH_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOG, &GPIO_InitStruct); - - /*Configure GPIO pin : PH3_BOOT0_Pin */ - GPIO_InitStruct.Pin = PH3_BOOT0_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(PH3_BOOT0_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : UCPD_PWR_Pin */ - GPIO_InitStruct.Pin = UCPD_PWR_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(UCPD_PWR_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : USER_Button_Pin */ - GPIO_InitStruct.Pin = USER_Button_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(USER_Button_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : LED_RED_Pin LED_GREEN_Pin Mems_VL53_xshut_Pin */ - GPIO_InitStruct.Pin = LED_RED_Pin|LED_GREEN_Pin|Mems_VL53_xshut_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - /*Configure GPIO pin : MIC_CCK1_Pin */ - GPIO_InitStruct.Pin = MIC_CCK1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF6_MDF1; - HAL_GPIO_Init(MIC_CCK1_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pin : WRLS_WKUP_B_Pin */ - GPIO_InitStruct.Pin = WRLS_WKUP_B_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(WRLS_WKUP_B_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : WRLS_NOTIFY_Pin Mems_INT_IIS2MDC_Pin USB_IANA_Pin */ - GPIO_InitStruct.Pin = WRLS_NOTIFY_Pin|Mems_INT_IIS2MDC_Pin|USB_IANA_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - /*Configure GPIO pins : USB_UCPD_FLT_Pin Mems_ISM330DLC_INT1_Pin */ - GPIO_InitStruct.Pin = USB_UCPD_FLT_Pin|Mems_ISM330DLC_INT1_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - /*Configure GPIO pin : USB_VBUS_SENSE_Pin */ - GPIO_InitStruct.Pin = USB_VBUS_SENSE_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_INPUT; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(USB_VBUS_SENSE_GPIO_Port, &GPIO_InitStruct); - - /*Configure GPIO pins : Mems_STSAFE_RESET_Pin WRLS_WKUP_W_Pin */ - GPIO_InitStruct.Pin = Mems_STSAFE_RESET_Pin|WRLS_WKUP_W_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /*Configure GPIO pin : MIC_SDIN0_Pin */ - GPIO_InitStruct.Pin = MIC_SDIN0_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF6_MDF1; - HAL_GPIO_Init(MIC_SDIN0_GPIO_Port, &GPIO_InitStruct); - -/* USER CODE BEGIN MX_GPIO_Init_2 */ -/* USER CODE END MX_GPIO_Init_2 */ -} - -/* USER CODE BEGIN 4 */ - -/* USER CODE END 4 */ - -/** - * @brief Period elapsed callback in non blocking mode - * @note This function is called when TIM17 interrupt took place, inside - * HAL_TIM_IRQHandler(). It makes a direct call to HAL_IncTick() to increment - * a global variable "uwTick" used as application time base. - * @param htim : TIM handle - * @retval None - */ -void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim) -{ - /* USER CODE BEGIN Callback 0 */ - - /* USER CODE END Callback 0 */ - if (htim->Instance == TIM17) { - HAL_IncTick(); - } - /* USER CODE BEGIN Callback 1 */ - - /* USER CODE END Callback 1 */ -} - -/** - * @brief This function is executed in case of error occurrence. - * @retval None - */ -void Error_Handler(void) -{ - /* USER CODE BEGIN Error_Handler_Debug */ - /* User can add his own implementation to report the HAL error return state */ - __disable_irq(); - while (1) - { - } - /* USER CODE END Error_Handler_Debug */ -} - -#ifdef USE_FULL_ASSERT -/** - * @brief Reports the name of the source file and the source line number - * where the assert_param error has occurred. - * @param file: pointer to the source file name - * @param line: assert_param error line source number - * @retval None - */ -void assert_failed(uint8_t *file, uint32_t line) -{ - /* USER CODE BEGIN 6 */ - /* User can add his own implementation to report the file name and line number, - ex: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ - /* USER CODE END 6 */ -} -#endif /* USE_FULL_ASSERT */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_hal_msp.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_hal_msp.c deleted file mode 100644 index f20674319..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_hal_msp.c +++ /dev/null @@ -1,861 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32u5xx_hal_msp.c - * @brief This file provides code for the MSP Initialization - * and de-Initialization codes. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -/* USER CODE BEGIN Includes */ - -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN Define */ - -/* USER CODE END Define */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN Macro */ - -/* USER CODE END Macro */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* External functions --------------------------------------------------------*/ -/* USER CODE BEGIN ExternalFunctions */ - -/* USER CODE END ExternalFunctions */ - -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ -/** - * Initializes the Global MSP. - */ -void HAL_MspInit(void) -{ - - /* USER CODE BEGIN MspInit 0 */ - - /* USER CODE END MspInit 0 */ - - __HAL_RCC_PWR_CLK_ENABLE(); - - /* System interrupt init*/ - - /* USER CODE BEGIN MspInit 1 */ - - /* USER CODE END MspInit 1 */ -} - -/** -* @brief MDF MSP Initialization -* This function configures the hardware resources used in this example -* @param hmdf: MDF handle pointer -* @retval None -*/ -void HAL_MDF_MspInit(MDF_HandleTypeDef* hmdf) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(IS_ADF_INSTANCE(hmdf->Instance)) - { - /* USER CODE BEGIN ADF1_MspInit 0 */ - - /* USER CODE END ADF1_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADF1; - PeriphClkInit.Adf1ClockSelection = RCC_ADF1CLKSOURCE_HCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_ADF1_CLK_ENABLE(); - - __HAL_RCC_GPIOE_CLK_ENABLE(); - /**ADF1 GPIO Configuration - PE10 ------> ADF1_SDI0 - PE9 ------> ADF1_CCK0 - */ - GPIO_InitStruct.Pin = MIC_SDINx_Pin|MIC_CCK0_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF3_ADF1; - HAL_GPIO_Init(GPIOE, &GPIO_InitStruct); - - /* USER CODE BEGIN ADF1_MspInit 1 */ - - /* USER CODE END ADF1_MspInit 1 */ - } - -} - -/** -* @brief MDF MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hmdf: MDF handle pointer -* @retval None -*/ -void HAL_MDF_MspDeInit(MDF_HandleTypeDef* hmdf) -{ - if(IS_ADF_INSTANCE(hmdf->Instance)) - { - /* USER CODE BEGIN ADF1_MspDeInit 0 */ - - /* USER CODE END ADF1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADF1_CLK_DISABLE(); - - /**ADF1 GPIO Configuration - PE10 ------> ADF1_SDI0 - PE9 ------> ADF1_CCK0 - */ - HAL_GPIO_DeInit(GPIOE, MIC_SDINx_Pin|MIC_CCK0_Pin); - - /* USER CODE BEGIN ADF1_MspDeInit 1 */ - - /* USER CODE END ADF1_MspDeInit 1 */ - } - -} - -/** -* @brief I2C MSP Initialization -* This function configures the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspInit(I2C_HandleTypeDef* hi2c) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hi2c->Instance==I2C1) - { - /* USER CODE BEGIN I2C1_MspInit 0 */ - - /* USER CODE END I2C1_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C1; - PeriphClkInit.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**I2C1 GPIO Configuration - PB9 ------> I2C1_SDA - PB8 ------> I2C1_SCL - */ - GPIO_InitStruct.Pin = GPIO_PIN_9|GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_I2C1_CLK_ENABLE(); - /* USER CODE BEGIN I2C1_MspInit 1 */ - - /* USER CODE END I2C1_MspInit 1 */ - } - else if(hi2c->Instance==I2C2) - { - /* USER CODE BEGIN I2C2_MspInit 0 */ - - /* USER CODE END I2C2_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_I2C2; - PeriphClkInit.I2c2ClockSelection = RCC_I2C2CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - __HAL_RCC_GPIOH_CLK_ENABLE(); - /**I2C2 GPIO Configuration - PH4 ------> I2C2_SCL - PH5 ------> I2C2_SDA - */ - GPIO_InitStruct.Pin = GPIO_PIN_4|GPIO_PIN_5; - GPIO_InitStruct.Mode = GPIO_MODE_AF_OD; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF4_I2C2; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_I2C2_CLK_ENABLE(); - /* USER CODE BEGIN I2C2_MspInit 1 */ - - /* USER CODE END I2C2_MspInit 1 */ - } - -} - -/** -* @brief I2C MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hi2c: I2C handle pointer -* @retval None -*/ -void HAL_I2C_MspDeInit(I2C_HandleTypeDef* hi2c) -{ - if(hi2c->Instance==I2C1) - { - /* USER CODE BEGIN I2C1_MspDeInit 0 */ - - /* USER CODE END I2C1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_I2C1_CLK_DISABLE(); - - /**I2C1 GPIO Configuration - PB9 ------> I2C1_SDA - PB8 ------> I2C1_SCL - */ - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_9); - - HAL_GPIO_DeInit(GPIOB, GPIO_PIN_8); - - /* USER CODE BEGIN I2C1_MspDeInit 1 */ - - /* USER CODE END I2C1_MspDeInit 1 */ - } - else if(hi2c->Instance==I2C2) - { - /* USER CODE BEGIN I2C2_MspDeInit 0 */ - - /* USER CODE END I2C2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_I2C2_CLK_DISABLE(); - - /**I2C2 GPIO Configuration - PH4 ------> I2C2_SCL - PH5 ------> I2C2_SDA - */ - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_4); - - HAL_GPIO_DeInit(GPIOH, GPIO_PIN_5); - - /* USER CODE BEGIN I2C2_MspDeInit 1 */ - - /* USER CODE END I2C2_MspDeInit 1 */ - } - -} - -static uint32_t HAL_RCC_OSPIM_CLK_ENABLED=0; - -/** -* @brief OSPI MSP Initialization -* This function configures the hardware resources used in this example -* @param hospi: OSPI handle pointer -* @retval None -*/ -void HAL_OSPI_MspInit(OSPI_HandleTypeDef* hospi) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hospi->Instance==OCTOSPI1) - { - /* USER CODE BEGIN OCTOSPI1_MspInit 0 */ - - /* USER CODE END OCTOSPI1_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI; - PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - HAL_RCC_OSPIM_CLK_ENABLED++; - if(HAL_RCC_OSPIM_CLK_ENABLED==1){ - __HAL_RCC_OSPIM_CLK_ENABLE(); - } - __HAL_RCC_OSPI1_CLK_ENABLE(); - - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOE_CLK_ENABLE(); - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOC_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**OCTOSPI1 GPIO Configuration - PI0 ------> OCTOSPIM_P1_IO5 - PE3 ------> OCTOSPIM_P1_DQS - PD7 ------> OCTOSPIM_P1_IO7 - PF8 ------> OCTOSPIM_P1_IO0 - PH2 ------> OCTOSPIM_P1_IO4 - PF7 ------> OCTOSPIM_P1_IO2 - PF9 ------> OCTOSPIM_P1_IO1 - PF6 ------> OCTOSPIM_P1_IO3 - PC3 ------> OCTOSPIM_P1_IO6 - PB10 ------> OCTOSPIM_P1_CLK - PB11 ------> OCTOSPIM_P1_NCS - */ - GPIO_InitStruct.Pin = OCTOSPI_R_IO5_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1; - HAL_GPIO_Init(OCTOSPI_R_IO5_GPIO_Port, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_R_DQS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1; - HAL_GPIO_Init(OCTOSPI_R_DQS_GPIO_Port, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_R_IO7_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1; - HAL_GPIO_Init(OCTOSPI_R_IO7_GPIO_Port, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_R_IO0_Pin|OCTOSPI_R_IO2_Pin|OCTOSPI_R_IO1_Pin|OCTOSPI_R_IO3_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_R_IO4_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF3_OCTOSPI1; - HAL_GPIO_Init(OCTOSPI_R_IO4_GPIO_Port, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_R_IO6_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1; - HAL_GPIO_Init(OCTOSPI_R_IO6_GPIO_Port, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_R_CLK_P_Pin|OCTOSPI_R_NCS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF10_OCTOSPI1; - HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); - - /* USER CODE BEGIN OCTOSPI1_MspInit 1 */ - - /* USER CODE END OCTOSPI1_MspInit 1 */ - } - else if(hospi->Instance==OCTOSPI2) - { - /* USER CODE BEGIN OCTOSPI2_MspInit 0 */ - - /* USER CODE END OCTOSPI2_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_OSPI; - PeriphClkInit.OspiClockSelection = RCC_OSPICLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - HAL_RCC_OSPIM_CLK_ENABLED++; - if(HAL_RCC_OSPIM_CLK_ENABLED==1){ - __HAL_RCC_OSPIM_CLK_ENABLE(); - } - __HAL_RCC_OSPI2_CLK_ENABLE(); - - __HAL_RCC_GPIOI_CLK_ENABLE(); - __HAL_RCC_GPIOH_CLK_ENABLE(); - __HAL_RCC_GPIOF_CLK_ENABLE(); - /**OCTOSPI2 GPIO Configuration - PI5 ------> OCTOSPIM_P2_NCS - PH12 ------> OCTOSPIM_P2_IO7 - PH10 ------> OCTOSPIM_P2_IO5 - PH11 ------> OCTOSPIM_P2_IO6 - PF0 ------> OCTOSPIM_P2_IO0 - PH9 ------> OCTOSPIM_P2_IO4 - PF1 ------> OCTOSPIM_P2_IO1 - PF2 ------> OCTOSPIM_P2_IO2 - PF3 ------> OCTOSPIM_P2_IO3 - PF4 ------> OCTOSPIM_P2_CLK - PF12 ------> OCTOSPIM_P2_DQS - */ - GPIO_InitStruct.Pin = OCTOSPI_F_NCS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF5_OCTOSPI2; - HAL_GPIO_Init(OCTOSPI_F_NCS_GPIO_Port, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_F_IO7_Pin|OCTOSPI_F_IO5_Pin|OCTOSPI_F_IO6_Pin|OCTOSPI_F_IO4_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF5_OCTOSPI2; - HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = OCTOSPI_F_IO0_Pin|OCTOSPI_F_IO1_Pin|OCTOSPI_F_IO2_Pin|OCTOSPI_F_IO3_Pin - |OCTOSPI_F_CLK_P_Pin|OCTOSPI_F_DQS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; - GPIO_InitStruct.Alternate = GPIO_AF5_OCTOSPI2; - HAL_GPIO_Init(GPIOF, &GPIO_InitStruct); - - /* USER CODE BEGIN OCTOSPI2_MspInit 1 */ - - /* USER CODE END OCTOSPI2_MspInit 1 */ - } - -} - -/** -* @brief OSPI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hospi: OSPI handle pointer -* @retval None -*/ -void HAL_OSPI_MspDeInit(OSPI_HandleTypeDef* hospi) -{ - if(hospi->Instance==OCTOSPI1) - { - /* USER CODE BEGIN OCTOSPI1_MspDeInit 0 */ - - /* USER CODE END OCTOSPI1_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_OSPIM_CLK_ENABLED--; - if(HAL_RCC_OSPIM_CLK_ENABLED==0){ - __HAL_RCC_OSPIM_CLK_DISABLE(); - } - __HAL_RCC_OSPI1_CLK_DISABLE(); - - /**OCTOSPI1 GPIO Configuration - PI0 ------> OCTOSPIM_P1_IO5 - PE3 ------> OCTOSPIM_P1_DQS - PD7 ------> OCTOSPIM_P1_IO7 - PF8 ------> OCTOSPIM_P1_IO0 - PH2 ------> OCTOSPIM_P1_IO4 - PF7 ------> OCTOSPIM_P1_IO2 - PF9 ------> OCTOSPIM_P1_IO1 - PF6 ------> OCTOSPIM_P1_IO3 - PC3 ------> OCTOSPIM_P1_IO6 - PB10 ------> OCTOSPIM_P1_CLK - PB11 ------> OCTOSPIM_P1_NCS - */ - HAL_GPIO_DeInit(OCTOSPI_R_IO5_GPIO_Port, OCTOSPI_R_IO5_Pin); - - HAL_GPIO_DeInit(OCTOSPI_R_DQS_GPIO_Port, OCTOSPI_R_DQS_Pin); - - HAL_GPIO_DeInit(OCTOSPI_R_IO7_GPIO_Port, OCTOSPI_R_IO7_Pin); - - HAL_GPIO_DeInit(GPIOF, OCTOSPI_R_IO0_Pin|OCTOSPI_R_IO2_Pin|OCTOSPI_R_IO1_Pin|OCTOSPI_R_IO3_Pin); - - HAL_GPIO_DeInit(OCTOSPI_R_IO4_GPIO_Port, OCTOSPI_R_IO4_Pin); - - HAL_GPIO_DeInit(OCTOSPI_R_IO6_GPIO_Port, OCTOSPI_R_IO6_Pin); - - HAL_GPIO_DeInit(GPIOB, OCTOSPI_R_CLK_P_Pin|OCTOSPI_R_NCS_Pin); - - /* USER CODE BEGIN OCTOSPI1_MspDeInit 1 */ - - /* USER CODE END OCTOSPI1_MspDeInit 1 */ - } - else if(hospi->Instance==OCTOSPI2) - { - /* USER CODE BEGIN OCTOSPI2_MspDeInit 0 */ - - /* USER CODE END OCTOSPI2_MspDeInit 0 */ - /* Peripheral clock disable */ - HAL_RCC_OSPIM_CLK_ENABLED--; - if(HAL_RCC_OSPIM_CLK_ENABLED==0){ - __HAL_RCC_OSPIM_CLK_DISABLE(); - } - __HAL_RCC_OSPI2_CLK_DISABLE(); - - /**OCTOSPI2 GPIO Configuration - PI5 ------> OCTOSPIM_P2_NCS - PH12 ------> OCTOSPIM_P2_IO7 - PH10 ------> OCTOSPIM_P2_IO5 - PH11 ------> OCTOSPIM_P2_IO6 - PF0 ------> OCTOSPIM_P2_IO0 - PH9 ------> OCTOSPIM_P2_IO4 - PF1 ------> OCTOSPIM_P2_IO1 - PF2 ------> OCTOSPIM_P2_IO2 - PF3 ------> OCTOSPIM_P2_IO3 - PF4 ------> OCTOSPIM_P2_CLK - PF12 ------> OCTOSPIM_P2_DQS - */ - HAL_GPIO_DeInit(OCTOSPI_F_NCS_GPIO_Port, OCTOSPI_F_NCS_Pin); - - HAL_GPIO_DeInit(GPIOH, OCTOSPI_F_IO7_Pin|OCTOSPI_F_IO5_Pin|OCTOSPI_F_IO6_Pin|OCTOSPI_F_IO4_Pin); - - HAL_GPIO_DeInit(GPIOF, OCTOSPI_F_IO0_Pin|OCTOSPI_F_IO1_Pin|OCTOSPI_F_IO2_Pin|OCTOSPI_F_IO3_Pin - |OCTOSPI_F_CLK_P_Pin|OCTOSPI_F_DQS_Pin); - - /* USER CODE BEGIN OCTOSPI2_MspDeInit 1 */ - - /* USER CODE END OCTOSPI2_MspDeInit 1 */ - } - -} - -/** -* @brief SPI MSP Initialization -* This function configures the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspInit(SPI_HandleTypeDef* hspi) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hspi->Instance==SPI2) - { - /* USER CODE BEGIN SPI2_MspInit 0 */ - - /* USER CODE END SPI2_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_SPI2; - PeriphClkInit.Spi2ClockSelection = RCC_SPI2CLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_SPI2_CLK_ENABLE(); - - __HAL_RCC_GPIOD_CLK_ENABLE(); - __HAL_RCC_GPIOB_CLK_ENABLE(); - /**SPI2 GPIO Configuration - PD4 ------> SPI2_MOSI - PD3 ------> SPI2_MISO - PD1 ------> SPI2_SCK - PB12 ------> SPI2_NSS - */ - GPIO_InitStruct.Pin = WRLS_SPI2_MOSI_Pin|WRLS_SPI2_MISO_Pin|WRLS_SPI2_SCK_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; - HAL_GPIO_Init(GPIOD, &GPIO_InitStruct); - - GPIO_InitStruct.Pin = WRLS_SPI2_NSS_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF5_SPI2; - HAL_GPIO_Init(WRLS_SPI2_NSS_GPIO_Port, &GPIO_InitStruct); - - /* USER CODE BEGIN SPI2_MspInit 1 */ - - /* USER CODE END SPI2_MspInit 1 */ - } - -} - -/** -* @brief SPI MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hspi: SPI handle pointer -* @retval None -*/ -void HAL_SPI_MspDeInit(SPI_HandleTypeDef* hspi) -{ - if(hspi->Instance==SPI2) - { - /* USER CODE BEGIN SPI2_MspDeInit 0 */ - - /* USER CODE END SPI2_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_SPI2_CLK_DISABLE(); - - /**SPI2 GPIO Configuration - PD4 ------> SPI2_MOSI - PD3 ------> SPI2_MISO - PD1 ------> SPI2_SCK - PB12 ------> SPI2_NSS - */ - HAL_GPIO_DeInit(GPIOD, WRLS_SPI2_MOSI_Pin|WRLS_SPI2_MISO_Pin|WRLS_SPI2_SCK_Pin); - - HAL_GPIO_DeInit(WRLS_SPI2_NSS_GPIO_Port, WRLS_SPI2_NSS_Pin); - - /* USER CODE BEGIN SPI2_MspDeInit 1 */ - - /* USER CODE END SPI2_MspDeInit 1 */ - } - -} - -/** -* @brief UART MSP Initialization -* This function configures the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspInit(UART_HandleTypeDef* huart) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(huart->Instance==UART4) - { - /* USER CODE BEGIN UART4_MspInit 0 */ - - /* USER CODE END UART4_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_UART4; - PeriphClkInit.Uart4ClockSelection = RCC_UART4CLKSOURCE_PCLK1; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_UART4_CLK_ENABLE(); - - __HAL_RCC_GPIOC_CLK_ENABLE(); - /**UART4 GPIO Configuration - PC11 ------> UART4_RX - PC10 ------> UART4_TX - */ - GPIO_InitStruct.Pin = WRLS_UART4_RX_Pin|WRLS_UART4_TX_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF8_UART4; - HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); - - /* USER CODE BEGIN UART4_MspInit 1 */ - - /* USER CODE END UART4_MspInit 1 */ - } - else if(huart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspInit 0 */ - - /* USER CODE END USART1_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USART1; - PeriphClkInit.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_USART1_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USART1 GPIO Configuration - PA10 ------> USART1_RX - PA9 ------> USART1_TX - */ - GPIO_InitStruct.Pin = T_VCP_RX_Pin|T_VCP_TX_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF7_USART1; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USART1 interrupt Init */ - HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); - HAL_NVIC_EnableIRQ(USART1_IRQn); - /* USER CODE BEGIN USART1_MspInit 1 */ - - /* USER CODE END USART1_MspInit 1 */ - } - -} - -/** -* @brief UART MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param huart: UART handle pointer -* @retval None -*/ -void HAL_UART_MspDeInit(UART_HandleTypeDef* huart) -{ - if(huart->Instance==UART4) - { - /* USER CODE BEGIN UART4_MspDeInit 0 */ - - /* USER CODE END UART4_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_UART4_CLK_DISABLE(); - - /**UART4 GPIO Configuration - PC11 ------> UART4_RX - PC10 ------> UART4_TX - */ - HAL_GPIO_DeInit(GPIOC, WRLS_UART4_RX_Pin|WRLS_UART4_TX_Pin); - - /* USER CODE BEGIN UART4_MspDeInit 1 */ - - /* USER CODE END UART4_MspDeInit 1 */ - } - else if(huart->Instance==USART1) - { - /* USER CODE BEGIN USART1_MspDeInit 0 */ - - /* USER CODE END USART1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USART1_CLK_DISABLE(); - - /**USART1 GPIO Configuration - PA10 ------> USART1_RX - PA9 ------> USART1_TX - */ - HAL_GPIO_DeInit(GPIOA, T_VCP_RX_Pin|T_VCP_TX_Pin); - - /* USART1 interrupt DeInit */ - HAL_NVIC_DisableIRQ(USART1_IRQn); - /* USER CODE BEGIN USART1_MspDeInit 1 */ - - /* USER CODE END USART1_MspDeInit 1 */ - } - -} - -/** -* @brief PCD MSP Initialization -* This function configures the hardware resources used in this example -* @param hpcd: PCD handle pointer -* @retval None -*/ -void HAL_PCD_MspInit(PCD_HandleTypeDef* hpcd) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hpcd->Instance==USB_OTG_FS) - { - /* USER CODE BEGIN USB_OTG_FS_MspInit 0 */ - - /* USER CODE END USB_OTG_FS_MspInit 0 */ - - /** Initializes the peripherals clock - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_CLK48; - PeriphClkInit.IclkClockSelection = RCC_CLK48CLKSOURCE_HSI48; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**USB_OTG_FS GPIO Configuration - PA12 ------> USB_OTG_FS_DP - PA11 ------> USB_OTG_FS_DM - */ - GPIO_InitStruct.Pin = USB_C_P_Pin|USB_C_PA11_Pin; - GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; - GPIO_InitStruct.Pull = GPIO_NOPULL; - GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct.Alternate = GPIO_AF10_USB; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* Peripheral clock enable */ - __HAL_RCC_USB_CLK_ENABLE(); - - /* Enable VDDUSB */ - if(__HAL_RCC_PWR_IS_CLK_DISABLED()) - { - __HAL_RCC_PWR_CLK_ENABLE(); - HAL_PWREx_EnableVddUSB(); - __HAL_RCC_PWR_CLK_DISABLE(); - } - else - { - HAL_PWREx_EnableVddUSB(); - } - /* USER CODE BEGIN USB_OTG_FS_MspInit 1 */ - - /* USER CODE END USB_OTG_FS_MspInit 1 */ - } - -} - -/** -* @brief PCD MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hpcd: PCD handle pointer -* @retval None -*/ -void HAL_PCD_MspDeInit(PCD_HandleTypeDef* hpcd) -{ - if(hpcd->Instance==USB_OTG_FS) - { - /* USER CODE BEGIN USB_OTG_FS_MspDeInit 0 */ - - /* USER CODE END USB_OTG_FS_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_USB_CLK_DISABLE(); - - /**USB_OTG_FS GPIO Configuration - PA12 ------> USB_OTG_FS_DP - PA11 ------> USB_OTG_FS_DM - */ - HAL_GPIO_DeInit(GPIOA, USB_C_P_Pin|USB_C_PA11_Pin); - - /* USER CODE BEGIN USB_OTG_FS_MspDeInit 1 */ - - /* USER CODE END USB_OTG_FS_MspDeInit 1 */ - } - -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_hal_timebase_tim.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_hal_timebase_tim.c deleted file mode 100644 index cc08aa2e9..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_hal_timebase_tim.c +++ /dev/null @@ -1,126 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32u5xx_hal_timebase_tim.c - * @brief HAL time base based on the hardware TIM. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32u5xx_hal.h" -#include "stm32u5xx_hal_tim.h" - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -TIM_HandleTypeDef htim17; -/* Private function prototypes -----------------------------------------------*/ -/* Private functions ---------------------------------------------------------*/ - -/** - * @brief This function configures the TIM17 as a time base source. - * The time source is configured to have 1ms time base with a dedicated - * Tick interrupt priority. - * @note This function is called automatically at the beginning of program after - * reset by HAL_Init() or at any time when clock is configured, by HAL_RCC_ClockConfig(). - * @param TickPriority: Tick interrupt priority. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) -{ - RCC_ClkInitTypeDef clkconfig; - uint32_t uwTimclock = 0; - uint32_t uwPrescalerValue = 0; - uint32_t pFLatency; - HAL_StatusTypeDef status; - - /* Enable TIM17 clock */ - __HAL_RCC_TIM17_CLK_ENABLE(); - - /* Get clock configuration */ - HAL_RCC_GetClockConfig(&clkconfig, &pFLatency); - - /* Compute TIM17 clock */ - uwTimclock = HAL_RCC_GetPCLK2Freq(); - - /* Compute the prescaler value to have TIM17 counter clock equal to 1MHz */ - uwPrescalerValue = (uint32_t) ((uwTimclock / 1000000U) - 1U); - - /* Initialize TIM17 */ - htim17.Instance = TIM17; - - /* Initialize TIMx peripheral as follow: - - + Period = [(TIM17CLK/1000) - 1]. to have a (1/1000) s time base. - + Prescaler = (uwTimclock/1000000 - 1) to have a 1MHz counter clock. - + ClockDivision = 0 - + Counter direction = Up - */ - htim17.Init.Period = (1000000U / 1000U) - 1U; - htim17.Init.Prescaler = uwPrescalerValue; - htim17.Init.ClockDivision = 0; - htim17.Init.CounterMode = TIM_COUNTERMODE_UP; - - status = HAL_TIM_Base_Init(&htim17); - if (status == HAL_OK) - { - /* Start the TIM time Base generation in interrupt mode */ - status = HAL_TIM_Base_Start_IT(&htim17); - if (status == HAL_OK) - { - if (TickPriority < (1UL << __NVIC_PRIO_BITS)) - { - /* Enable the TIM17 global Interrupt */ - HAL_NVIC_SetPriority(TIM17_IRQn, TickPriority, 0U); - uwTickPrio = TickPriority; - } - else - { - status = HAL_ERROR; - } - } - } - - /* Enable the TIM17 global Interrupt */ - HAL_NVIC_EnableIRQ(TIM17_IRQn); - - /* Return function status */ - return status; -} - -/** - * @brief Suspend Tick increment. - * @note Disable the tick increment by disabling TIM17 update interrupt. - * @param None - * @retval None - */ -void HAL_SuspendTick(void) -{ - /* Disable TIM17 update Interrupt */ - __HAL_TIM_DISABLE_IT(&htim17, TIM_IT_UPDATE); -} - -/** - * @brief Resume Tick increment. - * @note Enable the tick increment by Enabling TIM17 update interrupt. - * @param None - * @retval None - */ -void HAL_ResumeTick(void) -{ - /* Enable TIM17 Update interrupt */ - __HAL_TIM_ENABLE_IT(&htim17, TIM_IT_UPDATE); -} - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_it.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_it.c deleted file mode 100644 index af28c6b00..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/stm32u5xx_it.c +++ /dev/null @@ -1,193 +0,0 @@ -/* USER CODE BEGIN Header */ -/** - ****************************************************************************** - * @file stm32u5xx_it.c - * @brief Interrupt Service Routines. - ****************************************************************************** - * @attention - * - * Copyright (c) 2024 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ -/* USER CODE END Header */ - -/* Includes ------------------------------------------------------------------*/ -#include "main.h" -#include "stm32u5xx_it.h" -/* Private includes ----------------------------------------------------------*/ -/* USER CODE BEGIN Includes */ -/* USER CODE END Includes */ - -/* Private typedef -----------------------------------------------------------*/ -/* USER CODE BEGIN TD */ - -/* USER CODE END TD */ - -/* Private define ------------------------------------------------------------*/ -/* USER CODE BEGIN PD */ - -/* USER CODE END PD */ - -/* Private macro -------------------------------------------------------------*/ -/* USER CODE BEGIN PM */ - -/* USER CODE END PM */ - -/* Private variables ---------------------------------------------------------*/ -/* USER CODE BEGIN PV */ - -/* USER CODE END PV */ - -/* Private function prototypes -----------------------------------------------*/ -/* USER CODE BEGIN PFP */ - -/* USER CODE END PFP */ - -/* Private user code ---------------------------------------------------------*/ -/* USER CODE BEGIN 0 */ - -/* USER CODE END 0 */ - -/* External variables --------------------------------------------------------*/ -extern UART_HandleTypeDef huart1; -extern TIM_HandleTypeDef htim17; - -/* USER CODE BEGIN EV */ - -/* USER CODE END EV */ - -/******************************************************************************/ -/* Cortex Processor Interruption and Exception Handlers */ -/******************************************************************************/ -/** - * @brief This function handles Non maskable interrupt. - */ -void NMI_Handler(void) -{ - /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ - - /* USER CODE END NonMaskableInt_IRQn 0 */ - /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ - while (1) - { - } - /* USER CODE END NonMaskableInt_IRQn 1 */ -} - -/** - * @brief This function handles Hard fault interrupt. - */ -void HardFault_Handler(void) -{ - /* USER CODE BEGIN HardFault_IRQn 0 */ - - /* USER CODE END HardFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_HardFault_IRQn 0 */ - /* USER CODE END W1_HardFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Memory management fault. - */ -void MemManage_Handler(void) -{ - /* USER CODE BEGIN MemoryManagement_IRQn 0 */ - - /* USER CODE END MemoryManagement_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_MemoryManagement_IRQn 0 */ - /* USER CODE END W1_MemoryManagement_IRQn 0 */ - } -} - -/** - * @brief This function handles Prefetch fault, memory access fault. - */ -void BusFault_Handler(void) -{ - /* USER CODE BEGIN BusFault_IRQn 0 */ - - /* USER CODE END BusFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_BusFault_IRQn 0 */ - /* USER CODE END W1_BusFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Undefined instruction or illegal state. - */ -void UsageFault_Handler(void) -{ - /* USER CODE BEGIN UsageFault_IRQn 0 */ - - /* USER CODE END UsageFault_IRQn 0 */ - while (1) - { - /* USER CODE BEGIN W1_UsageFault_IRQn 0 */ - /* USER CODE END W1_UsageFault_IRQn 0 */ - } -} - -/** - * @brief This function handles Debug monitor. - */ -void DebugMon_Handler(void) -{ - /* USER CODE BEGIN DebugMonitor_IRQn 0 */ - - /* USER CODE END DebugMonitor_IRQn 0 */ - /* USER CODE BEGIN DebugMonitor_IRQn 1 */ - - /* USER CODE END DebugMonitor_IRQn 1 */ -} - -/******************************************************************************/ -/* STM32U5xx Peripheral Interrupt Handlers */ -/* Add here the Interrupt Handlers for the used peripherals. */ -/* For the available peripheral interrupt handler names, */ -/* please refer to the startup file (startup_stm32u5xx.s). */ -/******************************************************************************/ - -/** - * @brief This function handles USART1 global interrupt. - */ -void USART1_IRQHandler(void) -{ - /* USER CODE BEGIN USART1_IRQn 0 */ - - /* USER CODE END USART1_IRQn 0 */ - HAL_UART_IRQHandler(&huart1); - /* USER CODE BEGIN USART1_IRQn 1 */ - - /* USER CODE END USART1_IRQn 1 */ -} - -/** - * @brief This function handles TIM17 global interrupt. - */ -void TIM17_IRQHandler(void) -{ - /* USER CODE BEGIN TIM17_IRQn 0 */ - - /* USER CODE END TIM17_IRQn 0 */ - HAL_TIM_IRQHandler(&htim17); - /* USER CODE BEGIN TIM17_IRQn 1 */ - - /* USER CODE END TIM17_IRQn 1 */ -} - -/* USER CODE BEGIN 1 */ - -/* USER CODE END 1 */ diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/system_stm32u5xx.c b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/system_stm32u5xx.c deleted file mode 100644 index c93ac0fa3..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/STM32CubeMX/Src/system_stm32u5xx.c +++ /dev/null @@ -1,362 +0,0 @@ -/** - ****************************************************************************** - * @file system_stm32u5xx.c - * @author MCD Application Team - * @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File - * - * This file provides two functions and one global variable to be called from - * user application: - * - SystemInit(): This function is called at startup just after reset and - * before branch to main program. This call is made inside - * the "startup_stm32u5xx.s" file. - * - * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used - * by the user application to setup the SysTick - * timer or configure other parameters. - * - * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must - * be called whenever the core clock is changed - * during program execution. - * - * After each device reset the MSI (4 MHz) is used as system clock source. - * Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to - * configure the system clock before to branch to main program. - * - * This file configures the system clock as follows: - *============================================================================= - *----------------------------------------------------------------------------- - * System Clock source | MSI - *----------------------------------------------------------------------------- - * SYSCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * HCLK(Hz) | 4000000 - *----------------------------------------------------------------------------- - * AHB Prescaler | 1 - *----------------------------------------------------------------------------- - * APB1 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB2 Prescaler | 1 - *----------------------------------------------------------------------------- - * APB3 Prescaler | 1 - *----------------------------------------------------------------------------- - * PLL1_SRC | No clock - *----------------------------------------------------------------------------- - * PLL1_M | 1 - *----------------------------------------------------------------------------- - * PLL1_N | 8 - *----------------------------------------------------------------------------- - * PLL1_P | 7 - *----------------------------------------------------------------------------- - * PLL1_Q | 2 - *----------------------------------------------------------------------------- - * PLL1_R | 2 - *----------------------------------------------------------------------------- - * PLL2_SRC | NA - *----------------------------------------------------------------------------- - * PLL2_M | NA - *----------------------------------------------------------------------------- - * PLL2_N | NA - *----------------------------------------------------------------------------- - * PLL2_P | NA - *----------------------------------------------------------------------------- - * PLL2_Q | NA - *----------------------------------------------------------------------------- - * PLL2_R | NA - *----------------------------------------------------------------------------- - * PLL3_SRC | NA - *----------------------------------------------------------------------------- - * PLL3_M | NA - *----------------------------------------------------------------------------- - * PLL3_N | NA - *----------------------------------------------------------------------------- - * PLL3_P | NA - *----------------------------------------------------------------------------- - * Require 48MHz for USB FS, | Disabled - * SDIO and RNG clock | - *----------------------------------------------------------------------------- - *============================================================================= - ****************************************************************************** - * @attention - * - * Copyright (c) 2021 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/** @addtogroup CMSIS - * @{ - */ - -/** @addtogroup STM32U5xx_system - * @{ - */ - -/** @addtogroup STM32U5xx_System_Private_Includes - * @{ - */ - -#include "stm32u5xx.h" -#include - -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Private_TypesDefinitions - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Private_Defines - * @{ - */ - -#if !defined (HSE_VALUE) - #define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (MSI_VALUE) - #define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* MSI_VALUE */ - -#if !defined (HSI_VALUE) - #define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/ -#endif /* HSI_VALUE */ - -/************************* Miscellaneous Configuration ************************/ -/*!< Uncomment the following line if you need to relocate your vector Table in - Internal SRAM. */ -/* #define VECT_TAB_SRAM */ -#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ -/******************************************************************************/ - -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Private_Macros - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Private_Variables - * @{ - */ - /* The SystemCoreClock variable is updated in three ways: - 1) by calling CMSIS function SystemCoreClockUpdate() - 2) by calling HAL API function HAL_RCC_GetHCLKFreq() - 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency - Note: If you use this function to configure the system clock; then there - is no need to call the 2 first functions listed above, since SystemCoreClock - variable is updated automatically. - */ - uint32_t SystemCoreClock = 4000000U; - - const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; - const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; - const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1330000U,\ - 1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 133000U, 100000U}; -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes - * @{ - */ - -/** - * @} - */ - -/** @addtogroup STM32U5xx_System_Private_Functions - * @{ - */ - -/** - * @brief Setup the microcontroller system. - * @param None - * @retval None - */ - -void SystemInit(void) -{ - /* FPU settings ------------------------------------------------------------*/ - #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) - SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */ - #endif - - /* Reset the RCC clock configuration to the default reset state ------------*/ - /* Set MSION bit */ - RCC->CR = RCC_CR_MSISON; - - /* Reset CFGR register */ - RCC->CFGR1 = 0U; - RCC->CFGR2 = 0U; - RCC->CFGR3 = 0U; - - /* Reset HSEON, CSSON , HSION, PLLxON bits */ - RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON); - - /* Reset PLLCFGR register */ - RCC->PLL1CFGR = 0U; - - /* Reset HSEBYP bit */ - RCC->CR &= ~(RCC_CR_HSEBYP); - - /* Disable all interrupts */ - RCC->CIER = 0U; - - /* Configure the Vector Table location add offset address ------------------*/ - #ifdef VECT_TAB_SRAM - SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ - #else - SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ - #endif -} - -/** - * @brief Update SystemCoreClock variable according to Clock Register Values. - * The SystemCoreClock variable contains the core clock (HCLK), it can - * be used by the user application to setup the SysTick timer or configure - * other parameters. - * - * @note Each time the core clock (HCLK) changes, this function must be called - * to update SystemCoreClock variable value. Otherwise, any configuration - * based on this variable will be incorrect. - * - * @note - The system frequency computed by this function is not the real - * frequency in the chip. It is calculated based on the predefined - * constant and the selected clock source: - * - * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*) - * - * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**) - * - * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***) - * - * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***) - * or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors. - * - * (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value - * 4 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value - * 16 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * - * (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * - * - The result of this function could be not correct when using fractional - * value for HSE crystal. - * - * @param None - * @retval None - */ -void SystemCoreClockUpdate(void) -{ - uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange; - float_t fracn1, pllvco; - - /* Get MSI Range frequency--------------------------------------------------*/ - if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U) - { - /* MSISRANGE from RCC_CSR applies */ - msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos; - } - else - { - /* MSIRANGE from RCC_CR applies */ - msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos; - } - - /*MSI frequency range in HZ*/ - msirange = MSIRangeTable[msirange]; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (RCC->CFGR1 & RCC_CFGR1_SWS) - { - case 0x00: /* MSI used as system clock source */ - SystemCoreClock = msirange; - break; - - case 0x04: /* HSI used as system clock source */ - SystemCoreClock = HSI_VALUE; - break; - - case 0x08: /* HSE used as system clock source */ - SystemCoreClock = HSE_VALUE; - break; - - case 0x0C: /* PLL used as system clock source */ - /* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN - SYSCLK = PLL_VCO / PLLR - */ - pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC); - pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U; - pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos); - fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos)); - - switch (pllsource) - { - case 0x00: /* No clock sent to PLL*/ - pllvco = (float_t)0U; - break; - - case 0x02: /* HSI used as PLL clock source */ - pllvco = ((float_t)HSI_VALUE / (float_t)pllm); - break; - - case 0x03: /* HSE used as PLL clock source */ - pllvco = ((float_t)HSE_VALUE / (float_t)pllm); - break; - - default: /* MSI used as PLL clock source */ - pllvco = ((float_t)msirange / (float_t)pllm); - break; - } - - pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U); - pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U ); - SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr); - break; - - default: - SystemCoreClock = msirange; - break; - } - /* Compute HCLK clock frequency --------------------------------------------*/ - /* Get HCLK prescaler */ - tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)]; - /* HCLK clock frequency */ - SystemCoreClock >>= tmp; -} - - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - diff --git a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/project.script b/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/project.script deleted file mode 100644 index e7753bd95..000000000 --- a/test-data/solutions/USBD/Board/B-U585I-IOT02A/CubeMX/project.script +++ /dev/null @@ -1,4 +0,0 @@ -loadboard B-U585I-IOT02A allmodes -project name STM32CubeMX -project toolchain "MDK-ARM V5" -SetCopyLibrary "copy only" diff --git a/test-data/solutions/USBD/HID/STM32CubeMX/Debug+B-U585I-IOT02A/STM32CubeMX/STM32CubeMX.ioc b/test-data/solutions/USBD/HID/STM32CubeMX/Debug+B-U585I-IOT02A/STM32CubeMX/STM32CubeMX.ioc deleted file mode 100644 index 091cb2133..000000000 --- a/test-data/solutions/USBD/HID/STM32CubeMX/Debug+B-U585I-IOT02A/STM32CubeMX/STM32CubeMX.ioc +++ /dev/null @@ -1,578 +0,0 @@ -#MicroXplorer Configuration settings - do not modify -CAD.formats= -CAD.pinconfig= -CAD.provider= -CORTEX_M33_NS.userName=CORTEX_M33 -File.Version=6 -GPIO.groupedBy= -I2C1.IPParameters=Timing -I2C1.Timing=0x30909DEC -I2C2.IPParameters=Timing -I2C2.Timing=0x30909DEC -KeepUserPlacement=false -Mcu.CPN=STM32U585AII6Q -Mcu.ContextProject=TrustZoneDisabled -Mcu.Family=STM32U5 -Mcu.IP0=ADF1 -Mcu.IP1=CORTEX_M33_NS -Mcu.IP10=OCTOSPI2 -Mcu.IP11=PWR -Mcu.IP12=RCC -Mcu.IP13=SPI2 -Mcu.IP14=SYS -Mcu.IP15=UART4 -Mcu.IP16=UCPD1 -Mcu.IP17=USART1 -Mcu.IP18=USB_OTG_FS -Mcu.IP2=DEBUG -Mcu.IP3=I2C1 -Mcu.IP4=I2C2 -Mcu.IP5=ICACHE -Mcu.IP6=LPBAM -Mcu.IP7=LPBAMQUEUE -Mcu.IP8=NVIC -Mcu.IP9=OCTOSPI1 -Mcu.IPNb=19 -Mcu.Name=STM32U585AIIxQ -Mcu.Package=UFBGA169 -Mcu.Pin0=PG15 -Mcu.Pin1=PC11 -Mcu.Pin10=PA14 (JTCK/SWCLK) -Mcu.Pin11=PH10 -Mcu.Pin12=PC14-OSC32_IN (PC14) -Mcu.Pin13=PE3 -Mcu.Pin14=PB9 -Mcu.Pin15=PB3 (JTDO/TRACESWO) -Mcu.Pin16=PD7 -Mcu.Pin17=PD3 -Mcu.Pin18=PH11 -Mcu.Pin19=PC15-OSC32_OUT (PC15) -Mcu.Pin2=PA15 (JTDI) -Mcu.Pin20=PF0 -Mcu.Pin21=PC13 -Mcu.Pin22=PB8 -Mcu.Pin23=PH9 -Mcu.Pin24=PH4 -Mcu.Pin25=PH6 -Mcu.Pin26=PF8 -Mcu.Pin27=PF1 -Mcu.Pin28=PF2 -Mcu.Pin29=PD1 -Mcu.Pin3=PI5 -Mcu.Pin30=PH7 -Mcu.Pin31=PH5 -Mcu.Pin32=PH2 -Mcu.Pin33=PA10 -Mcu.Pin34=PA13 (JTMS/SWDIO) -Mcu.Pin35=PA12 -Mcu.Pin36=PF7 -Mcu.Pin37=PF9 -Mcu.Pin38=PF3 -Mcu.Pin39=PF4 -Mcu.Pin4=PI0 -Mcu.Pin40=PA9 -Mcu.Pin41=PA11 -Mcu.Pin42=PF10 -Mcu.Pin43=PF6 -Mcu.Pin44=PE10 -Mcu.Pin45=PG6 -Mcu.Pin46=PH1-OSC_OUT (PH1) -Mcu.Pin47=PE9 -Mcu.Pin48=PG5 -Mcu.Pin49=PD14 -Mcu.Pin5=PH12 -Mcu.Pin50=PC3 -Mcu.Pin51=PF12 -Mcu.Pin52=PE8 -Mcu.Pin53=PB10 -Mcu.Pin54=PD10 -Mcu.Pin55=PD13 -Mcu.Pin56=PG2 -Mcu.Pin57=PF14 -Mcu.Pin58=PB11 -Mcu.Pin59=PB12 -Mcu.Pin6=PH3-BOOT0 -Mcu.Pin60=PB15 -Mcu.Pin61=PF11 -Mcu.Pin62=PE11 -Mcu.Pin63=PB1 -Mcu.Pin64=PF15 -Mcu.Pin65=VP_ICACHE_VS_ICACHE -Mcu.Pin66=VP_LPBAMQUEUE_VS_QUEUE -Mcu.Pin67=VP_OCTOSPI1_VS_octo -Mcu.Pin68=VP_OCTOSPI2_VS_octo -Mcu.Pin69=VP_PWR_VS_DBSignals -Mcu.Pin7=PB5 -Mcu.Pin70=VP_PWR_VS_SECSignals -Mcu.Pin71=VP_PWR_VS_LPOM -Mcu.Pin72=VP_SYS_VS_Systick -Mcu.Pin73=VP_LPBAM_VS_SIG1 -Mcu.Pin74=VP_LPBAM_VS_SIG4 -Mcu.Pin8=PD4 -Mcu.Pin9=PC10 -Mcu.PinsNb=75 -Mcu.ThirdPartyNb=0 -Mcu.UserConstants= -Mcu.UserName=STM32U585AIIxQ -MxCube.Version=6.11.0 -MxDb.Version=DB.6.0.110 -NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.ForceEnableDMAVector=true -NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4 -NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false -NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false -OCTOSPI1.ChipSelectBoundary=10 -OCTOSPI1.ClockPrescaler=2 -OCTOSPI1.DelayBlockBypass=HAL_OSPI_DELAY_BLOCK_USED -OCTOSPI1.DelayHoldQuarterCycle=HAL_OSPI_DHQC_ENABLE -OCTOSPI1.DeviceSize=23 -OCTOSPI1.IPParameters=MemoryType,DeviceSize,ClockPrescaler,DelayHoldQuarterCycle,ChipSelectBoundary,Refresh,DelayBlockBypass -OCTOSPI1.MemoryType=HAL_OSPI_MEMTYPE_APMEMORY -OCTOSPI1.Refresh=100 -OCTOSPI2.ChipSelectBoundary=0 -OCTOSPI2.ChipSelectHighTime=2 -OCTOSPI2.ClockPrescaler=4 -OCTOSPI2.DelayBlockBypass=HAL_OSPI_DELAY_BLOCK_USED -OCTOSPI2.DelayHoldQuarterCycle=HAL_OSPI_DHQC_ENABLE -OCTOSPI2.DeviceSize=26 -OCTOSPI2.FifoThreshold=4 -OCTOSPI2.IPParameters=FifoThreshold,MemoryType,DeviceSize,ChipSelectHighTime,ClockPrescaler,DelayHoldQuarterCycle,ChipSelectBoundary,DelayBlockBypass -OCTOSPI2.MemoryType=HAL_OSPI_MEMTYPE_MACRONIX -PA10.GPIOParameters=GPIO_Label -PA10.GPIO_Label=T.VCP_RX -PA10.Locked=true -PA10.Mode=Asynchronous -PA10.Signal=USART1_RX -PA11.GPIOParameters=GPIO_Label -PA11.GPIO_Label=USB.C_P -PA11.Locked=true -PA11.Mode=Device_Only -PA11.Signal=USB_OTG_FS_DM -PA12.GPIOParameters=GPIO_Label -PA12.GPIO_Label=USB.C_P -PA12.Locked=true -PA12.Mode=Device_Only -PA12.Signal=USB_OTG_FS_DP -PA13\ (JTMS/SWDIO).GPIOParameters=GPIO_Label -PA13\ (JTMS/SWDIO).GPIO_Label=T.SWDIO -PA13\ (JTMS/SWDIO).Locked=true -PA13\ (JTMS/SWDIO).Mode=Trace_Asynchronous_SW -PA13\ (JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO -PA14\ (JTCK/SWCLK).GPIOParameters=GPIO_Label -PA14\ (JTCK/SWCLK).GPIO_Label=T.SWCLK -PA14\ (JTCK/SWCLK).Locked=true -PA14\ (JTCK/SWCLK).Mode=Trace_Asynchronous_SW -PA14\ (JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK -PA15\ (JTDI).GPIOParameters=GPIO_Label -PA15\ (JTDI).GPIO_Label=USB.UCPD_CC1 -PA15\ (JTDI).Locked=true -PA15\ (JTDI).Mode=Dual_Role_AllSignals -PA15\ (JTDI).Signal=UCPD1_CC1 -PA9.GPIOParameters=GPIO_Label -PA9.GPIO_Label=T.VCP_TX -PA9.Locked=true -PA9.Mode=Asynchronous -PA9.Signal=USART1_TX -PB1.GPIOParameters=GPIO_Label -PB1.GPIO_Label=MIC.SDIN0 -PB1.Locked=true -PB1.Signal=MDF1_SDI0 -PB10.GPIOParameters=GPIO_Label -PB10.GPIO_Label=OCTOSPI.R_CLK_P -PB10.Locked=true -PB10.Mode=O1_P1_CLK -PB10.Signal=OCTOSPIM_P1_CLK -PB11.GPIOParameters=GPIO_Label -PB11.GPIO_Label=OCTOSPI.R_NCS -PB11.Locked=true -PB11.Mode=OCTOSPI1_Port1_NCS -PB11.Signal=OCTOSPIM_P1_NCS -PB12.GPIOParameters=GPIO_Label -PB12.GPIO_Label=WRLS.SPI2_NSS -PB12.Locked=true -PB12.Mode=NSS_Signal_Hard_Output -PB12.Signal=SPI2_NSS -PB15.GPIOParameters=GPIO_Label -PB15.GPIO_Label=USB.UCPD_CC2 -PB15.Locked=true -PB15.Mode=Dual_Role_AllSignals -PB15.Signal=UCPD1_CC2 -PB3\ (JTDO/TRACESWO).GPIOParameters=GPIO_Label -PB3\ (JTDO/TRACESWO).GPIO_Label=T.SWO -PB3\ (JTDO/TRACESWO).Locked=true -PB3\ (JTDO/TRACESWO).Mode=Trace_Asynchronous_SW -PB3\ (JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO -PB5.GPIOParameters=GPIO_Label -PB5.GPIO_Label=UCPD_PWR -PB5.Locked=true -PB5.Signal=GPIO_Output -PB8.Locked=true -PB8.Mode=I2C -PB8.Signal=I2C1_SCL -PB9.Locked=true -PB9.Mode=I2C -PB9.Signal=I2C1_SDA -PC10.GPIOParameters=GPIO_Label -PC10.GPIO_Label=WRLS.UART4_TX -PC10.Locked=true -PC10.Mode=Asynchronous -PC10.Signal=UART4_TX -PC11.GPIOParameters=GPIO_Label -PC11.GPIO_Label=WRLS.UART4_RX -PC11.Locked=true -PC11.Mode=Asynchronous -PC11.Signal=UART4_RX -PC13.GPIOParameters=GPIO_Label -PC13.GPIO_Label=USER_Button -PC13.Locked=true -PC13.Signal=GPIO_Input -PC14-OSC32_IN\ (PC14).GPIOParameters=GPIO_Label -PC14-OSC32_IN\ (PC14).GPIO_Label=PC14-OSC32_IN -PC14-OSC32_IN\ (PC14).Locked=true -PC14-OSC32_IN\ (PC14).Mode=LSE-External-Oscillator -PC14-OSC32_IN\ (PC14).Signal=RCC_OSC32_IN -PC15-OSC32_OUT\ (PC15).GPIOParameters=GPIO_Label -PC15-OSC32_OUT\ (PC15).GPIO_Label=PC15-OSC32_OUT -PC15-OSC32_OUT\ (PC15).Locked=true -PC15-OSC32_OUT\ (PC15).Mode=LSE-External-Oscillator -PC15-OSC32_OUT\ (PC15).Signal=RCC_OSC32_OUT -PC3.GPIOParameters=GPIO_Label -PC3.GPIO_Label=OCTOSPI.R_IO6 -PC3.Locked=true -PC3.Mode=OCTOSPI1_IOH_Port1H -PC3.Signal=OCTOSPIM_P1_IO6 -PD1.GPIOParameters=GPIO_Label -PD1.GPIO_Label=WRLS.SPI2_SCK -PD1.Locked=true -PD1.Mode=Full_Duplex_Master -PD1.Signal=SPI2_SCK -PD10.GPIOParameters=GPIO_Label -PD10.GPIO_Label=Mems.INT_IIS2MDC -PD10.Locked=true -PD10.Signal=GPIO_Input -PD13.GPIOParameters=GPIO_Label -PD13.GPIO_Label=USB.IANA -PD13.Locked=true -PD13.Signal=GPIO_Input -PD14.GPIOParameters=GPIO_Label -PD14.GPIO_Label=WRLS.NOTIFY -PD14.Locked=true -PD14.Signal=GPIO_Input -PD3.GPIOParameters=GPIO_Label -PD3.GPIO_Label=WRLS.SPI2_MISO -PD3.Locked=true -PD3.Mode=Full_Duplex_Master -PD3.Signal=SPI2_MISO -PD4.GPIOParameters=GPIO_Label -PD4.GPIO_Label=WRLS.SPI2_MOSI -PD4.Locked=true -PD4.Mode=Full_Duplex_Master -PD4.Signal=SPI2_MOSI -PD7.GPIOParameters=GPIO_Label -PD7.GPIO_Label=OCTOSPI.R_IO7 -PD7.Locked=true -PD7.Mode=OCTOSPI1_IOH_Port1H -PD7.Signal=OCTOSPIM_P1_IO7 -PE10.GPIOParameters=GPIO_Label -PE10.GPIO_Label=MIC.SDINx -PE10.Locked=true -PE10.Mode=MOD_ADF_CCK -PE10.Signal=ADF1_SDI0 -PE11.GPIOParameters=GPIO_Label -PE11.GPIO_Label=Mems.ISM330DLC_INT1 -PE11.Locked=true -PE11.Signal=GPIO_Input -PE3.GPIOParameters=GPIO_Label -PE3.GPIO_Label=OCTOSPI.R_DQS -PE3.Locked=true -PE3.Mode=OCTOSPI1_Port1_DQS -PE3.Signal=OCTOSPIM_P1_DQS -PE8.GPIOParameters=GPIO_Label -PE8.GPIO_Label=USB.UCPD_FLT -PE8.Locked=true -PE8.Signal=GPIO_Input -PE9.GPIOParameters=GPIO_Label -PE9.GPIO_Label=MIC.CCK0 -PE9.Locked=true -PE9.Mode=MOD_MDF_CCK0 -PE9.Signal=ADF1_CCK0 -PF0.GPIOParameters=GPIO_Label -PF0.GPIO_Label=OCTOSPI.F_IO0 -PF0.Locked=true -PF0.Mode=OCTOSPI2_IOL_Port2L -PF0.Signal=OCTOSPIM_P2_IO0 -PF1.GPIOParameters=GPIO_Label -PF1.GPIO_Label=OCTOSPI.F_IO1 -PF1.Locked=true -PF1.Mode=OCTOSPI2_IOL_Port2L -PF1.Signal=OCTOSPIM_P2_IO1 -PF10.GPIOParameters=GPIO_Label -PF10.GPIO_Label=MIC.CCK1 -PF10.Locked=true -PF10.Signal=MDF1_CCK1 -PF11.GPIOParameters=GPIO_Label -PF11.GPIO_Label=Mems.STSAFE_RESET -PF11.Locked=true -PF11.Signal=GPIO_Output -PF12.GPIOParameters=GPIO_Label -PF12.GPIO_Label=OCTOSPI.F_DQS -PF12.Locked=true -PF12.Mode=OCTOSPI2_Port2_DQS -PF12.Signal=OCTOSPIM_P2_DQS -PF14.GPIOParameters=GPIO_Label -PF14.GPIO_Label=USB.VBUS_SENSE -PF14.Locked=true -PF14.Signal=GPIO_Input -PF15.GPIOParameters=GPIO_Label -PF15.GPIO_Label=WRLS.WKUP_W -PF15.Locked=true -PF15.Signal=GPIO_Output -PF2.GPIOParameters=GPIO_Label -PF2.GPIO_Label=OCTOSPI.F_IO2 -PF2.Locked=true -PF2.Mode=OCTOSPI2_IOL_Port2L -PF2.Signal=OCTOSPIM_P2_IO2 -PF3.GPIOParameters=GPIO_Label -PF3.GPIO_Label=OCTOSPI.F_IO3 -PF3.Locked=true -PF3.Mode=OCTOSPI2_IOL_Port2L -PF3.Signal=OCTOSPIM_P2_IO3 -PF4.GPIOParameters=GPIO_Label -PF4.GPIO_Label=OCTOSPI.F_CLK_P -PF4.Locked=true -PF4.Mode=O2_P2_CLK -PF4.Signal=OCTOSPIM_P2_CLK -PF6.GPIOParameters=GPIO_Label -PF6.GPIO_Label=OCTOSPI.R_IO3 -PF6.Locked=true -PF6.Mode=OCTOSPI1_IOL_Port1L -PF6.Signal=OCTOSPIM_P1_IO3 -PF7.GPIOParameters=GPIO_Label -PF7.GPIO_Label=OCTOSPI.R_IO2 -PF7.Locked=true -PF7.Mode=OCTOSPI1_IOL_Port1L -PF7.Signal=OCTOSPIM_P1_IO2 -PF8.GPIOParameters=GPIO_Label -PF8.GPIO_Label=OCTOSPI.R_IO0 -PF8.Locked=true -PF8.Mode=OCTOSPI1_IOL_Port1L -PF8.Signal=OCTOSPIM_P1_IO0 -PF9.GPIOParameters=GPIO_Label -PF9.GPIO_Label=OCTOSPI.R_IO1 -PF9.Locked=true -PF9.Mode=OCTOSPI1_IOL_Port1L -PF9.Signal=OCTOSPIM_P1_IO1 -PG15.GPIOParameters=GPIO_Label -PG15.GPIO_Label=WRLS.FLOW -PG15.Locked=true -PG15.Signal=GPIO_Input -PG2.GPIOParameters=GPIO_Label -PG2.GPIO_Label=Mems.INT_LPS22HH -PG2.Locked=true -PG2.Signal=GPIO_Input -PG5.GPIOParameters=GPIO_Label -PG5.GPIO_Label=Mems.VLX_GPIO -PG5.Locked=true -PG5.Signal=GPIO_Input -PG6.GPIOParameters=GPIO_Label -PG6.GPIO_Label=WRLS.WKUP_B -PG6.Locked=true -PG6.Signal=GPIO_Output -PH1-OSC_OUT\ (PH1).GPIOParameters=GPIO_Label -PH1-OSC_OUT\ (PH1).GPIO_Label=Mems.VL53_xshut -PH1-OSC_OUT\ (PH1).Locked=true -PH1-OSC_OUT\ (PH1).Signal=GPIO_Output -PH10.GPIOParameters=GPIO_Label -PH10.GPIO_Label=OCTOSPI.F_IO5 -PH10.Locked=true -PH10.Mode=OCTOSPI2_IOH_Port2H -PH10.Signal=OCTOSPIM_P2_IO5 -PH11.GPIOParameters=GPIO_Label -PH11.GPIO_Label=OCTOSPI.F_IO6 -PH11.Locked=true -PH11.Mode=OCTOSPI2_IOH_Port2H -PH11.Signal=OCTOSPIM_P2_IO6 -PH12.GPIOParameters=GPIO_Label -PH12.GPIO_Label=OCTOSPI.F_IO7 -PH12.Locked=true -PH12.Mode=OCTOSPI2_IOH_Port2H -PH12.Signal=OCTOSPIM_P2_IO7 -PH2.GPIOParameters=GPIO_Label -PH2.GPIO_Label=OCTOSPI.R_IO4 -PH2.Locked=true -PH2.Mode=OCTOSPI1_IOH_Port1H -PH2.Signal=OCTOSPIM_P1_IO4 -PH3-BOOT0.GPIOParameters=GPIO_Label -PH3-BOOT0.GPIO_Label=PH3-BOOT0 -PH3-BOOT0.Locked=true -PH3-BOOT0.Signal=GPIO_Input -PH4.Locked=true -PH4.Mode=I2C -PH4.Signal=I2C2_SCL -PH5.Locked=true -PH5.Mode=I2C -PH5.Signal=I2C2_SDA -PH6.GPIOParameters=GPIO_Label -PH6.GPIO_Label=LED_RED -PH6.Locked=true -PH6.Signal=GPIO_Output -PH7.GPIOParameters=GPIO_Label -PH7.GPIO_Label=LED_GREEN -PH7.Locked=true -PH7.Signal=GPIO_Output -PH9.GPIOParameters=GPIO_Label -PH9.GPIO_Label=OCTOSPI.F_IO4 -PH9.Locked=true -PH9.Mode=OCTOSPI2_IOH_Port2H -PH9.Signal=OCTOSPIM_P2_IO4 -PI0.GPIOParameters=GPIO_Label -PI0.GPIO_Label=OCTOSPI.R_IO5 -PI0.Locked=true -PI0.Mode=OCTOSPI1_IOH_Port1H -PI0.Signal=OCTOSPIM_P1_IO5 -PI5.GPIOParameters=GPIO_Label -PI5.GPIO_Label=OCTOSPI.F_NCS -PI5.Locked=true -PI5.Mode=OCTOSPI2_Port2_NCS -PI5.Signal=OCTOSPIM_P2_NCS -PWR.IPParameters=PowerMode -PWR.PowerMode=PWR_SMPS_SUPPLY -PinOutPanel.CurrentBGAView=Top -PinOutPanel.RotationAngle=0 -ProjectManager.AskForMigrate=true -ProjectManager.BackupPrevious=false -ProjectManager.CompilerOptimize=6 -ProjectManager.ComputerToolchain=false -ProjectManager.CoupleFile=false -ProjectManager.CustomerFirmwarePackage= -ProjectManager.DefaultFWLocation=true -ProjectManager.DeletePrevious=true -ProjectManager.DeviceId=STM32U585AIIxQ -ProjectManager.FirmwarePackage=STM32Cube FW_U5 V1.5.0 -ProjectManager.FreePins=false -ProjectManager.HalAssertFull=false -ProjectManager.HeapSize=0x200 -ProjectManager.KeepUserCode=true -ProjectManager.LPBAM.generateCode= -ProjectManager.LastFirmware=true -ProjectManager.LibraryCopy=0 -ProjectManager.MainLocation=Src -ProjectManager.NoMain=false -ProjectManager.PreviousToolchain= -ProjectManager.ProjectBuild=false -ProjectManager.ProjectFileName=STM32CubeMX.ioc -ProjectManager.ProjectName=STM32CubeMX -ProjectManager.ProjectStructure= -ProjectManager.RegisterCallBack= -ProjectManager.StackSize=0x400 -ProjectManager.TargetToolchain=MDK-ARM V5.32 -ProjectManager.ToolChainLocation= -ProjectManager.UAScriptAfterPath= -ProjectManager.UAScriptBeforePath= -ProjectManager.UnderRoot=false -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADF1_Init-ADF1-false-HAL-true,4-MX_I2C1_Init-I2C1-false-HAL-true,5-MX_I2C2_Init-I2C2-false-HAL-true,6-MX_ICACHE_Init-ICACHE-false-HAL-true,7-MX_OCTOSPI1_Init-OCTOSPI1-false-HAL-true,8-MX_OCTOSPI2_Init-OCTOSPI2-false-HAL-true,9-MX_SPI2_Init-SPI2-false-HAL-true,10-MX_UART4_Init-UART4-false-HAL-true,11-MX_USART1_UART_Init-USART1-false-HAL-true,12-MX_UCPD1_Init-UCPD1-false-LL-true,13-MX_USB_OTG_FS_PCD_Init-USB_OTG_FS-false-HAL-true,0-MX_CORTEX_M33_NS_Init-CORTEX_M33_NS-false-HAL-true,0-MX_PWR_Init-PWR-false-HAL-true -RCC.ADCFreq_Value=16000000 -RCC.ADF1Freq_Value=160000000 -RCC.AHBFreq_Value=160000000 -RCC.APB1Freq_Value=160000000 -RCC.APB1TimFreq_Value=160000000 -RCC.APB2Freq_Value=160000000 -RCC.APB2TimFreq_Value=160000000 -RCC.APB3Freq_Value=160000000 -RCC.CK48Freq_Value=48000000 -RCC.CRSFreq_Value=48000000 -RCC.CortexFreq_Value=160000000 -RCC.DACCLockSelectionVirtual=RCC_DAC1CLKSOURCE_LSI -RCC.DACFreq_Value=32000 -RCC.EPOD_VALUE=4000000 -RCC.FCLKCortexFreq_Value=160000000 -RCC.FDCANFreq_Value=160000000 -RCC.FamilyName=M -RCC.HCLKFreq_Value=160000000 -RCC.HSE_VALUE=16000000 -RCC.HSI48_VALUE=48000000 -RCC.HSI_VALUE=16000000 -RCC.I2C1Freq_Value=160000000 -RCC.I2C2Freq_Value=160000000 -RCC.I2C3Freq_Value=160000000 -RCC.I2C4Freq_Value=160000000 -RCC.IPParameters=ADCFreq_Value,ADF1Freq_Value,AHBFreq_Value,APB1Freq_Value,APB1TimFreq_Value,APB2Freq_Value,APB2TimFreq_Value,APB3Freq_Value,CK48Freq_Value,CRSFreq_Value,CortexFreq_Value,DACCLockSelectionVirtual,DACFreq_Value,EPOD_VALUE,FCLKCortexFreq_Value,FDCANFreq_Value,FamilyName,HCLKFreq_Value,HSE_VALUE,HSI48_VALUE,HSI_VALUE,I2C1Freq_Value,I2C2Freq_Value,I2C3Freq_Value,I2C4Freq_Value,LPTIM2Freq_Value,LPUART1Freq_Value,LSCOPinFreq_Value,LSIDIV_VALUE,LSI_VALUE,MCO1PinFreq_Value,MDF1Freq_Value,MSI_VALUE,OCTOSPIMFreq_Value,PLL2PoutputFreq_Value,PLL2QoutputFreq_Value,PLL2RoutputFreq_Value,PLL3PoutputFreq_Value,PLL3QoutputFreq_Value,PLL3RoutputFreq_Value,PLLN,PLLPoutputFreq_Value,PLLQoutputFreq_Value,PLLRCLKFreq_Value,RNGFreq_Value,SAESFreq_Value,SAI1Freq_Value,SAI2Freq_Value,SDMMCFreq_Value,SPI1Freq_Value,SPI2Freq_Value,SPI3Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,UART4Freq_Value,UART5Freq_Value,USART1Freq_Value,USART2Freq_Value,USART3Freq_Value,USBFreq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value,VCOInputFreq_Value,VCOOutputFreq_Value,VCOPLL2OutputFreq_Value,VCOPLL3OutputFreq_Value -RCC.LPTIM2Freq_Value=160000000 -RCC.LPUART1Freq_Value=160000000 -RCC.LSCOPinFreq_Value=32000 -RCC.LSIDIV_VALUE=32000 -RCC.LSI_VALUE=32000 -RCC.MCO1PinFreq_Value=160000000 -RCC.MDF1Freq_Value=160000000 -RCC.MSI_VALUE=4000000 -RCC.OCTOSPIMFreq_Value=160000000 -RCC.PLL2PoutputFreq_Value=258000000 -RCC.PLL2QoutputFreq_Value=258000000 -RCC.PLL2RoutputFreq_Value=258000000 -RCC.PLL3PoutputFreq_Value=258000000 -RCC.PLL3QoutputFreq_Value=258000000 -RCC.PLL3RoutputFreq_Value=258000000 -RCC.PLLN=80 -RCC.PLLPoutputFreq_Value=160000000 -RCC.PLLQoutputFreq_Value=160000000 -RCC.PLLRCLKFreq_Value=160000000 -RCC.RNGFreq_Value=48000000 -RCC.SAESFreq_Value=48000000 -RCC.SAI1Freq_Value=258000000 -RCC.SAI2Freq_Value=258000000 -RCC.SDMMCFreq_Value=160000000 -RCC.SPI1Freq_Value=160000000 -RCC.SPI2Freq_Value=160000000 -RCC.SPI3Freq_Value=160000000 -RCC.SYSCLKFreq_VALUE=160000000 -RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK -RCC.UART4Freq_Value=160000000 -RCC.UART5Freq_Value=160000000 -RCC.USART1Freq_Value=160000000 -RCC.USART2Freq_Value=160000000 -RCC.USART3Freq_Value=160000000 -RCC.USBFreq_Value=48000000 -RCC.VCOInput2Freq_Value=4000000 -RCC.VCOInput3Freq_Value=4000000 -RCC.VCOInputFreq_Value=4000000 -RCC.VCOOutputFreq_Value=320000000 -RCC.VCOPLL2OutputFreq_Value=516000000 -RCC.VCOPLL3OutputFreq_Value=516000000 -SPI2.CalculateBaudRate=80.0 MBits/s -SPI2.Direction=SPI_DIRECTION_2LINES -SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS -SPI2.Mode=SPI_MODE_MASTER -SPI2.VirtualNSS=VM_NSSHARD -SPI2.VirtualType=VM_MASTER -USART1.IPParameters=VirtualMode-Asynchronous -USART1.VirtualMode-Asynchronous=VM_ASYNC -USB_OTG_FS.IPParameters=VirtualMode -USB_OTG_FS.VirtualMode=Device_Only -VP_ICACHE_VS_ICACHE.Mode=DirectMappedCache -VP_ICACHE_VS_ICACHE.Signal=ICACHE_VS_ICACHE -VP_LPBAMQUEUE_VS_QUEUE.Mode=QUEUEMODE -VP_LPBAMQUEUE_VS_QUEUE.Signal=LPBAMQUEUE_VS_QUEUE -VP_LPBAM_VS_SIG1.Mode=SmartRun -VP_LPBAM_VS_SIG1.Signal=LPBAM_VS_SIG1 -VP_LPBAM_VS_SIG4.Mode=LPDMA1 -VP_LPBAM_VS_SIG4.Signal=LPBAM_VS_SIG4 -VP_OCTOSPI1_VS_octo.Mode=octo_mode -VP_OCTOSPI1_VS_octo.Signal=OCTOSPI1_VS_octo -VP_OCTOSPI2_VS_octo.Mode=octo_mode -VP_OCTOSPI2_VS_octo.Signal=OCTOSPI2_VS_octo -VP_PWR_VS_DBSignals.Mode=DisableDeadBatterySignals -VP_PWR_VS_DBSignals.Signal=PWR_VS_DBSignals -VP_PWR_VS_LPOM.Mode=PowerOptimisation -VP_PWR_VS_LPOM.Signal=PWR_VS_LPOM -VP_PWR_VS_SECSignals.Mode=Security/Privilege -VP_PWR_VS_SECSignals.Signal=PWR_VS_SECSignals -VP_SYS_VS_Systick.Mode=SysTick -VP_SYS_VS_Systick.Signal=SYS_VS_Systick -board=B-U585I-IOT02A -boardIOC=true