Skip to content

Commit e8b7d45

Browse files
widgetiiclaude
widgetii
and
claude
committed
reginfo: add Hi3519DV500/Hi3516DV500 pinmux table + dispatch; audit cv6xx
DV500 (V5, aarch64) has three IOCFG controllers at IOCFG0 0x10260000, IOCFG2 0x179F0000, IOCFG3 0x0EFF0000 (IOCFG2/3 differ from cv6xx). It is already detected as HISI_OT but regs_by_chip() routed it to CV610regs, so reginfo decoded cv6xx pins at cv6xx addresses. Add a dedicated DV500regs[] and dispatch 3519/3516DV500 to it. Function lists are built from the vendor SDK pin_mux.c (every function the SDK selects across its modes, indexed by mux value) and cross-checked / extended with the vendor U-Boot register-init spreadsheets (the per-board .xlsm "pinout"/"normal" sheets). The xlsm filled the index-0 GPIO and index-1 names pin_mux.c never configures (GPIO2_6/2_7, MDCLK0/MDIO0, the GPIO13/14 alternates on the MIPI_RX1 pads) and added five U-Boot-only pins (PWM0/1/2, USB_PWREN, USB_OVRCUR). Mux values nothing selects are left "reserved". The AON pad-mux in the PMC (0x11120000) is out of scope, as on cv6xx. All addresses verified in-range, de-duplicated, and every pin_mux.c-configured register is covered. While here, audit CV610regs against the cv6xx SDK pin_mux.c and add 19 registers the SDK configures that were missing: the VI data bus (io2 0x30-0x78) and UART2 (io1 0x10/0x14). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
1 parent dc23b55 commit e8b7d45

1 file changed

Lines changed: 175 additions & 0 deletions

File tree

‎src/reginfo.c‎

Lines changed: 175 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2171,6 +2171,23 @@ MUXCTRL(CV610_io2_cfg_reg8, 0x17940020, "MIPI_RX_D0N", "GPIO5_2", "VI_BT1120_DAT
21712171
MUXCTRL(CV610_io2_cfg_reg9, 0x17940024, "MIPI_RX_D0P", "GPIO5_3", "VI_BT1120_DATA3", "VI_DATA3", "reserved", "reserved", "VI_DATA5", "PWM0_OUT1");
21722172
MUXCTRL(CV610_io2_cfg_reg10, 0x17940028, "MIPI_RX_D2N", "GPIO5_4", "VI_BT1120_DATA4", "VI_DATA2", "reserved", "reserved", "VI_DATA6", "PWM0_OUT2");
21732173
MUXCTRL(CV610_io2_cfg_reg11, 0x1794002C, "MIPI_RX_D2P", "GPIO5_5", "VI_BT1120_DATA5", "VI_DATA1", "reserved", "reserved", "VI_DATA3", "PWM0_OUT3");
2174+
MUXCTRL(CV610_io2_cfg_reg12, 0x17940030, "reserved", "VI_DATA9");
2175+
MUXCTRL(CV610_io2_cfg_reg13, 0x17940034, "reserved", "VI_DATA8");
2176+
MUXCTRL(CV610_io2_cfg_reg14, 0x17940038, "reserved", "VI_DATA6");
2177+
MUXCTRL(CV610_io2_cfg_reg15, 0x1794003C, "reserved", "VI_DATA7");
2178+
MUXCTRL(CV610_io2_cfg_reg16, 0x17940040, "reserved", "VI_DATA2", "SENSOR0_CLK");
2179+
MUXCTRL(CV610_io2_cfg_reg17, 0x17940044, "reserved", "VI_DATA4");
2180+
MUXCTRL(CV610_io2_cfg_reg18, 0x17940048, "reserved", "VI_DATA3");
2181+
MUXCTRL(CV610_io2_cfg_reg19, 0x1794004C, "reserved", "VI_DATA1", "SENSOR0_CLK");
2182+
MUXCTRL(CV610_io2_cfg_reg20, 0x17940050, "reserved", "VI_DATA5", "reserved", "reserved", "reserved", "reserved", "reserved", "SENSOR0_RSTN");
2183+
MUXCTRL(CV610_io2_cfg_reg21, 0x17940054, "reserved", "VI_DATA0", "reserved", "reserved", "reserved", "reserved", "reserved", "SENSOR0_RSTN");
2184+
MUXCTRL(CV610_io2_cfg_reg22, 0x17940058, "reserved", "VI_CLK");
2185+
MUXCTRL(CV610_io2_cfg_reg23, 0x1794005C, "reserved", "VI_DATA10");
2186+
MUXCTRL(CV610_io2_cfg_reg25, 0x17940064, "reserved", "VI_DATA11");
2187+
MUXCTRL(CV610_io2_cfg_reg26, 0x17940068, "reserved", "VI_DATA15");
2188+
MUXCTRL(CV610_io2_cfg_reg27, 0x1794006C, "reserved", "VI_DATA14");
2189+
MUXCTRL(CV610_io2_cfg_reg28, 0x17940070, "reserved", "VI_DATA12");
2190+
MUXCTRL(CV610_io2_cfg_reg30, 0x17940078, "reserved", "VI_DATA13");
21742191
MUXCTRL(CV610_io2_cfg_reg32, 0x17940080, "GPIO6_5", "SENSOR1_CLK", "reserved", "reserved", "reserved", "FAST_BOOT_MODE", "reserved", "SENSOR0_RSTN");
21752192
MUXCTRL(CV610_io2_cfg_reg33, 0x17940084, "TEST_CLK", "SENSOR0_CLK", "reserved", "GPIO6_4", "reserved", "SFC_EMMC_BOOT_MODE");
21762193
MUXCTRL(CV610_io2_cfg_reg34, 0x17940088, "GPIO7_3", "VI_BT1120_DATA6", "reserved", "reserved", "PWM0_OUT1", "SENSOR1_RSTN", "VI_DATA0");
@@ -2181,6 +2198,8 @@ MUXCTRL(CV610_io2_cfg_reg38, 0x17940098, "GPIO6_6", "VI_BT1120_DATA15", "ETH_LIN
21812198
MUXCTRL(CV610_io2_cfg_reg39, 0x1794009C, "GPIO6_7", "reserved", "ETH_LINK_ACT_LED", "SPI0_SCLK", "reserved", "I2C0_SCL", "VI_DATA2", "SENSOR1_VS");
21822199
MUXCTRL(CV610_io1_cfg_reg0, 0x11130000, "GPIO1_5", "I2C1_SDA", "PWM0_OUT2", "UART2_RXD", "LSADC_CH1");
21832200
MUXCTRL(CV610_io1_cfg_reg1, 0x11130004, "GPIO1_4", "I2C1_SCL", "PWM0_OUT3", "UART2_TXD", "LSADC_CH0");
2201+
MUXCTRL(CV610_io1_cfg_reg4, 0x11130010, "reserved", "reserved", "UART2_TXD");
2202+
MUXCTRL(CV610_io1_cfg_reg5, 0x11130014, "reserved", "reserved", "UART2_RXD");
21842203
MUXCTRL(CV610_io1_cfg_reg12, 0x11130030, "JTAG_TRSTN", "ETH_LINK_STA_LED", "GPIO0_6", "I2C0_SCL", "reserved", "UART1_RXD", "SPI0_CSN1", "PWM0_OUT1");
21852204
MUXCTRL(CV610_io1_cfg_reg13, 0x11130034, "JTAG_TDI", "ETH_LINK_ACT_LED", "ETH_STA_ACT_LED", "I2C0_SDA", "USB2_PWREN", "UART1_TXD", "GPIO0_7", "PWM0_OUT2");
21862205
MUXCTRL(CV610_io1_cfg_reg14, 0x11130038, "GPIO7_7", "SDIO1_CDATA2", "reserved", "I2S_MCLK", "reserved", "UART1_RTSN", "SPI1_SDO", "PWM1_OUT0");
@@ -2226,6 +2245,23 @@ static const muxctrl_reg_t *CV610regs[] = {
22262245
&CV610_io2_cfg_reg9,
22272246
&CV610_io2_cfg_reg10,
22282247
&CV610_io2_cfg_reg11,
2248+
&CV610_io2_cfg_reg12,
2249+
&CV610_io2_cfg_reg13,
2250+
&CV610_io2_cfg_reg14,
2251+
&CV610_io2_cfg_reg15,
2252+
&CV610_io2_cfg_reg16,
2253+
&CV610_io2_cfg_reg17,
2254+
&CV610_io2_cfg_reg18,
2255+
&CV610_io2_cfg_reg19,
2256+
&CV610_io2_cfg_reg20,
2257+
&CV610_io2_cfg_reg21,
2258+
&CV610_io2_cfg_reg22,
2259+
&CV610_io2_cfg_reg23,
2260+
&CV610_io2_cfg_reg25,
2261+
&CV610_io2_cfg_reg26,
2262+
&CV610_io2_cfg_reg27,
2263+
&CV610_io2_cfg_reg28,
2264+
&CV610_io2_cfg_reg30,
22292265
&CV610_io2_cfg_reg32,
22302266
&CV610_io2_cfg_reg33,
22312267
&CV610_io2_cfg_reg34,
@@ -2236,6 +2272,8 @@ static const muxctrl_reg_t *CV610regs[] = {
22362272
&CV610_io2_cfg_reg39,
22372273
&CV610_io1_cfg_reg0,
22382274
&CV610_io1_cfg_reg1,
2275+
&CV610_io1_cfg_reg4,
2276+
&CV610_io1_cfg_reg5,
22392277
&CV610_io1_cfg_reg12,
22402278
&CV610_io1_cfg_reg13,
22412279
&CV610_io1_cfg_reg14,
@@ -2252,6 +2290,141 @@ static const muxctrl_reg_t *CV610regs[] = {
22522290
0
22532291
};
22542292

2293+
/*
2294+
* Hi3519DV500 / Hi3516DV500 (V5, aarch64) pinmux. Three IOCFG controllers:
2295+
* IOCFG0 0x10260000, IOCFG2 0x179F0000, IOCFG3 0x0EFF0000.
2296+
* Function lists are derived from the vendor SDK pin_mux.c (every function the
2297+
* SDK configures across its modes, indexed by the mux value); mux values the
2298+
* SDK never selects are left "reserved".
2299+
*/
2300+
MUXCTRL(DV500_io0_cfg_reg0, 0x10260000, "GPIO2_0", "reserved", "reserved", "SPI2_CSN", "I2S0_WS", "I2C1_SDA");
2301+
MUXCTRL(DV500_io0_cfg_reg1, 0x10260004, "GPIO2_1", "reserved", "reserved", "SPI2_SCLK", "I2S0_MCLK", "I2C1_SCL");
2302+
MUXCTRL(DV500_io0_cfg_reg2, 0x10260008, "GPIO2_2", "reserved", "reserved", "SPI2_SDI", "I2S0_SD_TX", "I2C2_SDA");
2303+
MUXCTRL(DV500_io0_cfg_reg3, 0x1026000C, "GPIO2_3", "reserved", "reserved", "SPI2_SDO", "I2S0_BCLK", "I2C2_SCL");
2304+
MUXCTRL(DV500_io0_cfg_reg4, 0x10260010, "reserved", "reserved", "reserved", "reserved", "RGB_DATA15");
2305+
MUXCTRL(DV500_io0_cfg_reg5, 0x10260014, "reserved", "reserved", "reserved", "reserved", "RGB_DATA16");
2306+
MUXCTRL(DV500_io0_cfg_reg7, 0x1026001C, "GPIO2_6", "MDCLK0", "reserved", "reserved", "RGB_DATA17");
2307+
MUXCTRL(DV500_io0_cfg_reg8, 0x10260020, "GPIO2_7", "MDIO0", "reserved", "I2S0_SD_RX", "RGB_DATA18");
2308+
MUXCTRL(DV500_io0_cfg_reg10, 0x10260028, "reserved", "reserved", "SPI3_SDO", "reserved", "RGB_DATA4");
2309+
MUXCTRL(DV500_io0_cfg_reg11, 0x1026002C, "reserved", "reserved", "SPI3_SDI", "reserved", "RGB_DATA3");
2310+
MUXCTRL(DV500_io0_cfg_reg12, 0x10260030, "reserved", "reserved", "reserved", "reserved", "RGB_DATA12");
2311+
MUXCTRL(DV500_io0_cfg_reg13, 0x10260034, "reserved", "reserved", "reserved", "reserved", "RGB_DATA13");
2312+
MUXCTRL(DV500_io0_cfg_reg14, 0x10260038, "reserved", "reserved", "reserved", "reserved", "RGB_DATA14");
2313+
MUXCTRL(DV500_io0_cfg_reg15, 0x1026003C, "reserved", "reserved", "SPI3_SCLK", "reserved", "RGB_DATA6", "reserved", "SPI_TFT_CLK");
2314+
MUXCTRL(DV500_io0_cfg_reg16, 0x10260040, "reserved", "reserved", "SPI3_CSN0", "reserved", "RGB_DATA5", "reserved", "SPI_TFT_CSN");
2315+
MUXCTRL(DV500_io0_cfg_reg17, 0x10260044, "reserved", "reserved", "SPI3_CSN1", "reserved", "RGB_DATA7", "reserved", "SPI_TFT_DATA");
2316+
MUXCTRL(DV500_io0_cfg_reg18, 0x10260048, "reserved", "reserved", "reserved", "reserved", "RGB_DATA8");
2317+
MUXCTRL(DV500_io0_cfg_reg19, 0x1026004C, "reserved", "reserved", "reserved", "reserved", "RGB_DATA9");
2318+
MUXCTRL(DV500_io0_cfg_reg20, 0x10260050, "reserved", "reserved", "reserved", "reserved", "RGB_DATA11");
2319+
MUXCTRL(DV500_io0_cfg_reg21, 0x10260054, "reserved", "reserved", "reserved", "reserved", "RGB_DATA10");
2320+
MUXCTRL(DV500_io0_cfg_reg22, 0x10260058, "reserved", "reserved", "I2S0_SD_RX", "SPI3_CSN0", "RGB_HS", "reserved", "SPI_TFT_CSN", "DMIC_SD0");
2321+
MUXCTRL(DV500_io0_cfg_reg23, 0x1026005C, "reserved", "reserved", "I2S0_MCLK", "SPI3_SCLK", "RGB_CLK", "reserved", "SPI_TFT_CLK", "DMIC_MCLK");
2322+
MUXCTRL(DV500_io0_cfg_reg24, 0x10260060, "reserved", "reserved", "I2S0_WS", "SPI3_SDI", "RGB_DATA0", "reserved", "SPI_TFT_DATA", "DMIC_SD1");
2323+
MUXCTRL(DV500_io0_cfg_reg25, 0x10260064, "reserved", "reserved", "I2S0_SD_TX", "SPI3_SDO", "RGB_VS", "reserved", "reserved", "DMIC_SD2");
2324+
MUXCTRL(DV500_io0_cfg_reg26, 0x10260068, "reserved", "reserved", "I2S0_BCLK", "SPI3_CSN1", "RGB_DATA1", "reserved", "reserved", "DMIC_SD3");
2325+
MUXCTRL(DV500_io0_cfg_reg27, 0x1026006C, "GPIO5_1", "I2C0_SDA", "reserved", "reserved", "RGB_DE");
2326+
MUXCTRL(DV500_io0_cfg_reg28, 0x10260070, "reserved", "I2C0_SCL", "VO_BT1120_DATA15", "reserved", "RGB_DATA2");
2327+
MUXCTRL(DV500_io0_cfg_reg29, 0x10260074, "reserved", "PWM1");
2328+
MUXCTRL(DV500_io0_cfg_reg30, 0x10260078, "DSI_D3N", "reserved", "VO_BT656_CLK", "SPI3_CSN0", "VO_BT1120_DATA13", "reserved", "SPI_TFT_CSN");
2329+
MUXCTRL(DV500_io0_cfg_reg31, 0x1026007C, "DSI_D3P", "reserved", "VO_BT1120_DATA7", "SPI3_SDI", "reserved", "reserved", "SPI_TFT_DATA");
2330+
MUXCTRL(DV500_io0_cfg_reg32, 0x10260080, "DSI_D1N", "reserved", "VO_BT1120_DATA3", "reserved", "RGB_DATA20");
2331+
MUXCTRL(DV500_io0_cfg_reg33, 0x10260084, "DSI_D1P", "reserved", "VO_BT1120_DATA2", "reserved", "RGB_DATA21");
2332+
MUXCTRL(DV500_io0_cfg_reg34, 0x10260088, "DSI_CKN", "reserved", "VO_BT1120_DATA5", "SPI3_SCLK", "reserved", "reserved", "SPI_TFT_CLK");
2333+
MUXCTRL(DV500_io0_cfg_reg35, 0x1026008C, "DSI_CKP", "reserved", "VO_BT1120_DATA4", "reserved", "RGB_DATA19");
2334+
MUXCTRL(DV500_io0_cfg_reg36, 0x10260090, "DSI_D0N", "reserved", "VO_BT1120_DATA1", "reserved", "RGB_DATA22");
2335+
MUXCTRL(DV500_io0_cfg_reg37, 0x10260094, "DSI_D0P", "reserved", "VO_BT1120_DATA0", "reserved", "RGB_DATA23");
2336+
MUXCTRL(DV500_io0_cfg_reg38, 0x10260098, "DSI_D2N", "reserved", "VO_BT1120_DATA6", "SPI3_SDO");
2337+
MUXCTRL(DV500_io0_cfg_reg39, 0x1026009C, "DSI_D2P", "reserved", "VO_BT1120_DATA14", "SPI3_CSN1");
2338+
MUXCTRL(DV500_io0_cfg_reg40, 0x102600A0, "reserved", "reserved", "VO_BT1120_DATA11");
2339+
MUXCTRL(DV500_io0_cfg_reg41, 0x102600A4, "reserved", "reserved", "VO_BT1120_DATA10");
2340+
MUXCTRL(DV500_io0_cfg_reg42, 0x102600A8, "reserved", "reserved", "VO_BT1120_DATA12");
2341+
MUXCTRL(DV500_io0_cfg_reg43, 0x102600AC, "reserved", "reserved", "VO_BT1120_DATA9");
2342+
MUXCTRL(DV500_io0_cfg_reg44, 0x102600B0, "reserved", "reserved", "VO_BT1120_CLK");
2343+
MUXCTRL(DV500_io0_cfg_reg45, 0x102600B4, "reserved", "reserved", "VO_BT1120_DATA8");
2344+
2345+
MUXCTRL(DV500_io2_cfg_reg0, 0x179F0000, "reserved", "reserved", "I2C7_SDA");
2346+
MUXCTRL(DV500_io2_cfg_reg1, 0x179F0004, "reserved", "reserved", "I2C7_SCL");
2347+
MUXCTRL(DV500_io2_cfg_reg2, 0x179F0008, "reserved", "reserved", "reserved", "VSYNC_TE_MIPITX");
2348+
MUXCTRL(DV500_io2_cfg_reg4, 0x179F0010, "GPIO10_3", "USB_VBUS");
2349+
MUXCTRL(DV500_io2_cfg_reg5, 0x179F0014, "reserved", "USB_PWREN");
2350+
MUXCTRL(DV500_io2_cfg_reg7, 0x179F001C, "reserved", "reserved", "reserved", "reserved", "SENSOR2_CLK");
2351+
MUXCTRL(DV500_io2_cfg_reg9, 0x179F0024, "reserved", "SPI0_CSN1", "SENSOR3_CLK", "reserved", "reserved", "reserved", "VI_DATA3", "THERMO_PS");
2352+
MUXCTRL(DV500_io2_cfg_reg10, 0x179F0028, "reserved", "SPI0_CSN0", "I2C3_SDA", "reserved", "reserved", "reserved", "VI_DATA1", "THERMO_DO6");
2353+
MUXCTRL(DV500_io2_cfg_reg11, 0x179F002C, "reserved", "SPI0_SDI", "I2C3_SCL", "reserved", "reserved", "reserved", "VI_DATA0", "THERMO_DO7");
2354+
MUXCTRL(DV500_io2_cfg_reg12, 0x179F0030, "reserved", "SPI0_SDO", "I2C4_SDA", "reserved", "reserved", "reserved", "VI_DATA2", "THERMO_HS");
2355+
MUXCTRL(DV500_io2_cfg_reg13, 0x179F0034, "reserved", "SPI0_SCLK", "I2C4_SCL", "reserved", "reserved", "reserved", "VI_CLK", "THERMO_CLK");
2356+
MUXCTRL(DV500_io2_cfg_reg14, 0x179F0038, "reserved", "SENSOR0_HS", "reserved", "reserved", "reserved", "reserved", "VI_DATA7", "THERMO_VS");
2357+
MUXCTRL(DV500_io2_cfg_reg15, 0x179F003C, "reserved", "SENSOR0_VS", "reserved", "reserved", "reserved", "reserved", "VI_DATA6", "THERMO_SD1");
2358+
MUXCTRL(DV500_io2_cfg_reg16, 0x179F0040, "reserved", "SENSOR0_RSTN", "reserved", "reserved", "reserved", "VI_DATA8", "VI_DATA4", "THERMO_SD0");
2359+
MUXCTRL(DV500_io2_cfg_reg17, 0x179F0044, "reserved", "SENSOR0_CLK", "reserved", "reserved", "reserved", "VI_DATA9", "VI_DATA5", "THERMO_MCK");
2360+
MUXCTRL(DV500_io2_cfg_reg18, 0x179F0048, "MIPI_RX0_D0N", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA10");
2361+
MUXCTRL(DV500_io2_cfg_reg19, 0x179F004C, "MIPI_RX0_D0P", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA11");
2362+
MUXCTRL(DV500_io2_cfg_reg20, 0x179F0050, "MIPI_RX0_D2N", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA14");
2363+
MUXCTRL(DV500_io2_cfg_reg21, 0x179F0054, "MIPI_RX0_D2P", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA15");
2364+
MUXCTRL(DV500_io2_cfg_reg22, 0x179F0058, "MIPI_RX0_CK0N", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA12");
2365+
MUXCTRL(DV500_io2_cfg_reg23, 0x179F005C, "MIPI_RX0_CK0P", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA13");
2366+
MUXCTRL(DV500_io2_cfg_reg24, 0x179F0060, "MIPI_RX0_CK1N", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA4", "THERMO_DO3");
2367+
MUXCTRL(DV500_io2_cfg_reg25, 0x179F0064, "MIPI_RX0_CK1P", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA5", "THERMO_DO0");
2368+
MUXCTRL(DV500_io2_cfg_reg26, 0x179F0068, "MIPI_RX0_D1N", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA0", "THERMO_DO5");
2369+
MUXCTRL(DV500_io2_cfg_reg27, 0x179F006C, "MIPI_RX0_D1P", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA1", "THERMO_DO4");
2370+
MUXCTRL(DV500_io2_cfg_reg28, 0x179F0070, "MIPI_RX0_D3N", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA2", "THERMO_DO2");
2371+
MUXCTRL(DV500_io2_cfg_reg29, 0x179F0074, "MIPI_RX0_D3P", "reserved", "reserved", "reserved", "reserved", "reserved", "VI_DATA3", "THERMO_DO1");
2372+
MUXCTRL(DV500_io2_cfg_reg30, 0x179F0078, "MIPI_RX1_D0N", "GPIO13_5");
2373+
MUXCTRL(DV500_io2_cfg_reg31, 0x179F007C, "MIPI_RX1_D0P", "GPIO13_6");
2374+
MUXCTRL(DV500_io2_cfg_reg32, 0x179F0080, "MIPI_RX1_D2N", "GPIO13_7");
2375+
MUXCTRL(DV500_io2_cfg_reg33, 0x179F0084, "MIPI_RX1_D2P", "GPIO14_0");
2376+
MUXCTRL(DV500_io2_cfg_reg34, 0x179F0088, "MIPI_RX1_CK0N", "GPIO14_1");
2377+
MUXCTRL(DV500_io2_cfg_reg35, 0x179F008C, "MIPI_RX1_CK0P", "GPIO14_2");
2378+
MUXCTRL(DV500_io2_cfg_reg36, 0x179F0090, "MIPI_RX1_CK1N", "GPIO14_3");
2379+
MUXCTRL(DV500_io2_cfg_reg37, 0x179F0094, "MIPI_RX1_CK1P", "GPIO14_4");
2380+
MUXCTRL(DV500_io2_cfg_reg38, 0x179F0098, "MIPI_RX1_D1N", "GPIO14_5");
2381+
MUXCTRL(DV500_io2_cfg_reg39, 0x179F009C, "MIPI_RX1_D1P", "GPIO14_6");
2382+
MUXCTRL(DV500_io2_cfg_reg40, 0x179F00A0, "MIPI_RX1_D3N", "GPIO14_7");
2383+
MUXCTRL(DV500_io2_cfg_reg41, 0x179F00A4, "MIPI_RX1_D3P", "GPIO1_7");
2384+
2385+
MUXCTRL(DV500_io3_cfg_reg0, 0x0EFF0000, "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "reserved", "THERMO_RSTN");
2386+
MUXCTRL(DV500_io3_cfg_reg1, 0x0EFF0004, "reserved", "SENSOR1_CLK");
2387+
MUXCTRL(DV500_io3_cfg_reg2, 0x0EFF0008, "reserved", "SENSOR1_RSTN");
2388+
MUXCTRL(DV500_io3_cfg_reg3, 0x0EFF000C, "reserved", "SENSOR1_HS", "reserved", "reserved", "reserved", "reserved", "reserved", "THERMO_SD2");
2389+
MUXCTRL(DV500_io3_cfg_reg4, 0x0EFF0010, "reserved", "SENSOR1_VS", "reserved", "reserved", "reserved", "reserved", "reserved", "THERMO_SD3");
2390+
MUXCTRL(DV500_io3_cfg_reg5, 0x0EFF0014, "reserved", "PWM2");
2391+
MUXCTRL(DV500_io3_cfg_reg6, 0x0EFF0018, "reserved", "USB_OVRCUR");
2392+
MUXCTRL(DV500_io3_cfg_reg8, 0x0EFF0020, "reserved", "PWM0");
2393+
MUXCTRL(DV500_io3_cfg_reg9, 0x0EFF0024, "reserved", "SPI1_SCLK", "I2C5_SCL", "reserved", "reserved", "SPI_3WIRE_CLK");
2394+
MUXCTRL(DV500_io3_cfg_reg10, 0x0EFF0028, "reserved", "SPI1_SDO", "I2C5_SDA", "reserved", "reserved", "SPI_3WIRE_DATA");
2395+
MUXCTRL(DV500_io3_cfg_reg11, 0x0EFF002C, "reserved", "SPI1_SDI", "I2C6_SCL");
2396+
MUXCTRL(DV500_io3_cfg_reg12, 0x0EFF0030, "reserved", "SPI1_CSN", "I2C6_SDA", "reserved", "reserved", "SPI_3WIRE_CSN");
2397+
2398+
static const muxctrl_reg_t *DV500regs[] = {
2399+
&DV500_io0_cfg_reg0, &DV500_io0_cfg_reg1, &DV500_io0_cfg_reg2, &DV500_io0_cfg_reg3,
2400+
&DV500_io0_cfg_reg4, &DV500_io0_cfg_reg5, &DV500_io0_cfg_reg7, &DV500_io0_cfg_reg8,
2401+
&DV500_io0_cfg_reg10, &DV500_io0_cfg_reg11, &DV500_io0_cfg_reg12, &DV500_io0_cfg_reg13,
2402+
&DV500_io0_cfg_reg14, &DV500_io0_cfg_reg15, &DV500_io0_cfg_reg16, &DV500_io0_cfg_reg17,
2403+
&DV500_io0_cfg_reg18, &DV500_io0_cfg_reg19, &DV500_io0_cfg_reg20, &DV500_io0_cfg_reg21,
2404+
&DV500_io0_cfg_reg22, &DV500_io0_cfg_reg23, &DV500_io0_cfg_reg24, &DV500_io0_cfg_reg25,
2405+
&DV500_io0_cfg_reg26, &DV500_io0_cfg_reg27, &DV500_io0_cfg_reg28, &DV500_io0_cfg_reg29,
2406+
&DV500_io0_cfg_reg30,
2407+
&DV500_io0_cfg_reg31, &DV500_io0_cfg_reg32, &DV500_io0_cfg_reg33, &DV500_io0_cfg_reg34,
2408+
&DV500_io0_cfg_reg35, &DV500_io0_cfg_reg36, &DV500_io0_cfg_reg37, &DV500_io0_cfg_reg38,
2409+
&DV500_io0_cfg_reg39, &DV500_io0_cfg_reg40, &DV500_io0_cfg_reg41, &DV500_io0_cfg_reg42,
2410+
&DV500_io0_cfg_reg43, &DV500_io0_cfg_reg44, &DV500_io0_cfg_reg45, &DV500_io2_cfg_reg0,
2411+
&DV500_io2_cfg_reg1, &DV500_io2_cfg_reg2, &DV500_io2_cfg_reg4, &DV500_io2_cfg_reg5,
2412+
&DV500_io2_cfg_reg7,
2413+
&DV500_io2_cfg_reg9, &DV500_io2_cfg_reg10, &DV500_io2_cfg_reg11, &DV500_io2_cfg_reg12,
2414+
&DV500_io2_cfg_reg13, &DV500_io2_cfg_reg14, &DV500_io2_cfg_reg15, &DV500_io2_cfg_reg16,
2415+
&DV500_io2_cfg_reg17, &DV500_io2_cfg_reg18, &DV500_io2_cfg_reg19, &DV500_io2_cfg_reg20,
2416+
&DV500_io2_cfg_reg21, &DV500_io2_cfg_reg22, &DV500_io2_cfg_reg23, &DV500_io2_cfg_reg24,
2417+
&DV500_io2_cfg_reg25, &DV500_io2_cfg_reg26, &DV500_io2_cfg_reg27, &DV500_io2_cfg_reg28,
2418+
&DV500_io2_cfg_reg29, &DV500_io2_cfg_reg30, &DV500_io2_cfg_reg31, &DV500_io2_cfg_reg32,
2419+
&DV500_io2_cfg_reg33, &DV500_io2_cfg_reg34, &DV500_io2_cfg_reg35, &DV500_io2_cfg_reg36,
2420+
&DV500_io2_cfg_reg37, &DV500_io2_cfg_reg38, &DV500_io2_cfg_reg39, &DV500_io2_cfg_reg40,
2421+
&DV500_io2_cfg_reg41, &DV500_io3_cfg_reg0, &DV500_io3_cfg_reg1, &DV500_io3_cfg_reg2,
2422+
&DV500_io3_cfg_reg3, &DV500_io3_cfg_reg4, &DV500_io3_cfg_reg5, &DV500_io3_cfg_reg6,
2423+
&DV500_io3_cfg_reg8, &DV500_io3_cfg_reg9, &DV500_io3_cfg_reg10,
2424+
&DV500_io3_cfg_reg11, &DV500_io3_cfg_reg12,
2425+
0,
2426+
};
2427+
22552428
static int gpio_mux_by(const char *gpio_number, int func_num,
22562429
const char *set_func);
22572430

@@ -2307,6 +2480,8 @@ static const muxctrl_reg_t **regs_by_chip() {
23072480
return EV200regs;
23082481
break;
23092482
case HISI_OT:
2483+
if (IS_CHIP("3519DV500") || IS_CHIP("3516DV500"))
2484+
return DV500regs;
23102485
return CV610regs;
23112486
case HISI_3536C:
23122487
return RCV100regs;

0 commit comments

Comments
 (0)