ive_neo: Hi3516EV200/EV300 XNN/Conv HW appears non-functional at the silicon level

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Summary

After extensive work making ive_neo behaviorally equivalent to vendor open_ive.ko on hi3516ev300_lite, empirical evidence strongly suggests the XNN/Conv hardware block is non-functional on this SoC variant, regardless of driver. Both our driver and vendor's driver report success via ioctls but never actually execute the submitted XNN tasks.

Evidence

• HW task counter [0x11320018] stays at 0x00000000 throughout all XNN submissions — both with ive_neo and with vendor's /lib/modules/4.9.37/extra/open_ive.ko
• Output buffers (dst_phys) stay all-zero after fwd_slice ioctls
• tmp_phys + conv1_out_offset stays zero — Conv layer 1 never writes its activations
• Only the preproc output (691200 bytes at tmp_phys+0) is visible — that's our CPU-side preproc, not HW work
• Vendor test-fc-model returns forward ret=0x0 handle=0 instant completion in 0.7 ms — way too fast for any real compute
• Vendor test-ivp ivp_re_allday_f1y2f2m1_640x360_v1003.oms fails at SYS_Init: 0xa0028012 on this board
• This matches the earlier finding that HI_MPI_IVE_CNN_LoadModel returns HI_ERR_IVE_NOT_SUPPORT (see git 112c3fb "test-cnn-model: CNN API returns NOT_SUPPORT on Hi3516EV200")
• Task nodes are byte-for-byte identical to what vendor writes (verified via kprobe_ive.ko hooking drv_ive_write_regs)
• All init registers match vendor ([0x34]=0x00313307, [0x54]=0x00003f07, [0x60]=0xffffffff, [0x84]=1, [0x88]=1, [0x8c]=0, [0x90]=0x01ab5159)

What ive_neo does achieve (current state)

• Full libive.so compatibility — test-fc-model returns instant completion, test-ivp runs 50 frames at 50.9 fps (vendor hangs this test on the same board)
• All kernel memory bugs fixed (tile-node buffer, preproc pp_size, fwd_slice Unpack loop cap)
• Register init sequence matches vendor byte-for-byte (added drv_ive_set_mem_speed which was missing)
• IRQ handler registered with completion primitive
• Async submit semantics matching vendor's drv_ive_write_regs
• libive.so init path implemented: svp_alg_proc_init (cmd 0x8010463b), ivp_proc_init (cmd 0x801046c8), mmap fops callback using osal_io_remap_pfn_range
• Slot-based model ID allocation
• Preproc writes raw Y/U/V pixel values (matches vendor VGS behavior)

Action points (for future work)

1. Investigate CRG / AI subsystem enable bits. Vendor's ive_init path only touches registers in the IVE block itself (0x11320000..0x11330000). If there's a separate AI/NNIE power domain or clock gate outside this window, it may need to be toggled. Suggested: read a full CRG dump during vendor runtime on a board where XNN is known to work (if any exists), compare against this board.
2. Verify on a different SoC variant. Hi3516CV300, Hi3516CV500, Hi3519V101, Hi3516DV300 reportedly have functional CNN/XNN hardware. ive_neo should port with minimal changes since the kernel ABI is the OSAL layer and the task-node format is the same across variants. This would also establish a known-good baseline.
3. Confirm non-XNN IVE ops work on this board. Submit a simple DMA, Sobel, or ThreshU8 task (bytes [10]!=0x36) through ive_neo and check if HW actually runs it. If DMA works but XNN doesn't, the issue is XNN-specific (e.g., XNN subsystem disabled). If neither works, the whole IVE block is broken.
4. Compare Hi3516EV200 vs EV300 silicon. The "EV" suffix suggests a variant without the IVP/CNN block. Check the official datasheet feature matrix — it's possible that CNN/XNN is only in the D/C/V variants and EV stands for "entry video" with XNN fused off.
5. Check mpp_init flags. libive.so may require a specific MPP_SYS_CONFIG_S parameter to enable an XNN subsystem that's otherwise off. Try running the vendor SDK's sample_ive_xnn binary (if available) to see what it calls before submission.
6. RE vendor's ive_umap_module_init (ive.o.c:8185) fully. We verified the documented register writes but there may be undocumented side-effects in CMPI_GetModuleFuncById(2) callbacks or SysDrvIoCtrl calls with IDs other than 144/145.

Test recipe to reproduce

```bash

Build

cd ~/git/openhisilicon/kernel/ive
make -C /git/firmware/output/build/linux-custom M=$PWD ARCH=arm \
CROSS_COMPILE=/git/firmware/output/host/bin/arm-openipc-linux-musleabi- \
PREFIX=open_ \
EXTRA_CFLAGS="-Dhi3516ev200 \
-I/home/dima/git/openhisilicon/include \
-I/home/dima/git/openhisilicon/kernel/osal/include \
-I/home/dima/git/openhisilicon/kernel/osal \
-I/home/dima/git/openhisilicon/kernel/ext_inc" modules

Test with ive_neo (runs at 50 fps but 0 detections)

ssh root@ 'rmmod open_ive; insmod /root/open_ive.ko save_power=0
cd /utils && ./test-ivp ivp_re_allday_f1y2f2m1_640x360_v1003.oms test-ivp-people.y4m'

Test with vendor (reports success but [0x18] stays 0)

ssh root@ 'rmmod open_ive; insmod /lib/modules/4.9.37/extra/open_ive.ko save_power=0
cd /utils && ./test-fc-model test_fc_model.oms
busybox devmem 0x11320018' # → 0x00000000
```

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Update: non-XNN IVE ops are fully functional on this board

Ran test-qr-ive test-qr-full.y4m under vendor /lib/modules/4.9.37/extra/open_ive.ko on hi3516ev300_lite. Results:

• IVE gate: 388 ms / 50 frames = 7.8 ms/frame for Thresh + Erode + Dilate + CCL (4 ops per frame, ~2 ms/op — real HW timing)
• IVE CCL returned semantically correct blobs — 70×70 squares at positions (214,134), (354,134), (214,274) which are exactly where a QR code's finder patterns live
• IRQ 52 count grew from 1 to 5 on a shorter run — HW fires completion interrupts per op
• [0x11320018] does not increment — apparently it's not the task counter we thought; don't rely on that register to prove/disprove HW liveness

Scope correction for this issue: only XNN/Conv (byte[10]=0x36) is dead. The rest of the IVE block — Thresh, Erode, Dilate, CCL (verified), and presumably Filter/Sobel/Add/Sub/And/Or/Hist/Integ/etc. (same submit mechanism) — is fully alive.

This means:

1. Action point 3 ("Confirm non-XNN IVE ops work") is now done — YES, they work.
2. The problem is specifically the XNN/Conv subsystem, which is likely fused off or gated behind an un-documented enable bit on EV200/EV300 variants (see action points 1, 4, 5).
3. ive_neo can and should implement Tier 1 non-XNN ops (DMA, Thresh, Dilate, Erode, And, Or, Xor, Add, Sub, Filter, Sobel, Thresh_S16/U16) using vendor's ive_fill_<op>_task builders in ida/ive.o.c:8484..9064. Each is a single 208-byte task node with byte[10]=0, submitted via the existing drv_ive_write_regs path already working in ive_neo.

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PR #35 (feat/libive-neo) lands the clean-room ive_neo.c driver in the state this issue describes as "working around vendor behavior". No silicon-level progress — the underlying HW investigation remains open.

What the PR does that's consistent with this issue:

• kernel/ive/ive_neo.c matches vendor task-node format byte-for-byte and preserves the full init sequence described here (drv_ive_set_mem_speed, IRQ handler, slot-based model IDs, etc.). All the "What ive_neo does achieve" items carry over unchanged.
• libraries/ivp_neo/src/ivp.c — hi_ivp_process_ex returns 0 detections, which is the correct observable behavior on this silicon given that both vendor open_ive.ko and ive_neo see [0x11320018] stuck at 0 after XNN submits. The commit message calls this out explicitly.
• kernel/ive/test/qemu/test-ive-ops.c exercises the non-XNN IVE ops (DMA, SAD, CCL, Thresh, Dilate/Erode, Sobel, MagAndAng, Hist, Integ, etc.) under emulated Hi3516EV300 — Result: 19/19 passed. This partially addresses action point 3 ("confirm non-XNN IVE ops work on this board"): the non-XNN path is sound both on QEMU and on hi3516ev300_lite real hardware (test-ive-mpi-neo reports 25/34 passed — the 9 failures are exactly the ops vendor libive.so also can't run on this SoC).

What the PR does NOT do:

• Action points 1, 2, 4, 5, 6 (CRG/AI power domains, different SoC variants, EV vs D/C/V feature matrix, mpp_init flags, RE of ive_umap_module_init) — all still future work.

Leaving the issue open.