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Increase assumed L2 sizes for RISCV X280 / ZVL256B and for SVE-capabl…

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Increase L2 defaults for RISCV X280 / ZVL256B and ARM SVE targets in CMake cross-compilation #5425

Increase assumed L2 sizes for RISCV X280 / ZVL256B and for SVE-capabl…
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Cirun Application / Cirun succeeded Aug 21, 2025 in 0s

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Runner(s)

Runner Name Image Region Cloud Connected Preemptible Ephemeral
cirun-openmathlib--openblas-6928b07710 ami-0a0c8eebcdd6dcbd0 us-east-1 aws Yes No Yes
cirun-openmathlib--openblas-1916ca0081 ami-0a0c8eebcdd6dcbd0 us-east-1 aws Yes No Yes

Response

🚀 cirun-openmathlib--openblas-6928b07710

  • Creation Attempt #1 2025-08-21 10:03:31 UTC: No errors found, go to Cirun Dashboard for more information

🚀 cirun-openmathlib--openblas-1916ca0081

  • Creation Attempt #1 2025-08-21 10:03:31 UTC: No errors found, go to Cirun Dashboard for more information