Skip to content

Commit 178c2a7

Browse files
committed
VUnit: style
Signed-off-by: umarcor <unai.martinezcorral@ehu.eus>
1 parent 2031c6d commit 178c2a7

1 file changed

Lines changed: 14 additions & 19 deletions

File tree

run.py

Lines changed: 14 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -1,28 +1,23 @@
11
from pathlib import Path
22
from vunit import VUnit
33

4-
prj = VUnit.from_argv()
5-
prj.add_osvvm()
6-
root = Path(__file__).parent
4+
ROOT = Path(__file__).parent
75

8-
lib = prj.add_library("lib")
9-
lib.add_source_files(root / "litedram" / "extras" / "*.vhdl")
10-
lib.add_source_files(root / "litedram" / "generated" / "sim" / "*.vhdl")
6+
PRJ = VUnit.from_argv()
7+
PRJ.add_osvvm()
118

12-
# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
13-
vhdl_files = root.glob("*.vhdl")
14-
vhdl_files = [
9+
PRJ.add_library("lib").add_source_files([
10+
ROOT / "litedram" / "extras" / "*.vhdl",
11+
ROOT / "litedram" / "generated" / "sim" / "*.vhdl"
12+
] + [
1513
src_file
16-
for src_file in vhdl_files
17-
if ("xilinx-mult" not in src_file)
18-
and ("foreign_random" not in src_file)
19-
and ("nonrandom" not in src_file)
20-
]
21-
lib.add_source_files(vhdl_files)
14+
for src_file in ROOT.glob("*.vhdl")
15+
# Use multiply.vhd and not xilinx-mult.vhd. Use VHDL-based random.
16+
if not any(exclude in str(src_file) for exclude in ["xilinx-mult", "foreign_random", "nonrandom"])
17+
])
2218

23-
unisim = prj.add_library("unisim")
24-
unisim.add_source_files(root / "sim-unisim" / "*.vhdl")
19+
PRJ.add_library("unisim").add_source_files(ROOT / "sim-unisim" / "*.vhdl")
2520

26-
prj.set_sim_option("disable_ieee_warnings", True)
21+
PRJ.set_sim_option("disable_ieee_warnings", True)
2722

28-
prj.main()
23+
PRJ.main()

0 commit comments

Comments
 (0)