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mikeymikey
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Merge pull request #342 from mkj/orangecrab-merge
Orangecrab working with litedram Fixed up a few simple merge conflicts in the Makefile.
2 parents fda8879 + cdd661d commit 6ff3b24

31 files changed

Lines changed: 40591 additions & 43319 deletions

‎Makefile‎

Lines changed: 23 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -152,12 +152,17 @@ RAM_INIT_FILE ?=hello_world/hello_world.hex
152152
#MEMORY_SIZE=393216
153153
#RAM_INIT_FILE=micropython/firmware.hex
154154

155-
FPGA_TARGET ?= ORANGE-CRAB
155+
FPGA_TARGET ?= ORANGE-CRAB-0.21
156156

157157
# FIXME: icache RAMs aren't being inferrenced as block RAMs on ECP5
158158
# with yosys, so make it smaller for now as a workaround.
159159
ICACHE_NUM_LINES=4
160160

161+
clkgen=fpga/clk_gen_ecp5.vhd
162+
toplevel=fpga/top-generic.vhdl
163+
dmi_dtm=dmi_dtm_dummy.vhdl
164+
LITEDRAM_GHDL_ARG=
165+
161166
# OrangeCrab with ECP85 (original v0.0 with UM5G-85 chip)
162167
ifeq ($(FPGA_TARGET), ORANGE-CRAB)
163168
RESET_LOW=true
@@ -175,15 +180,18 @@ endif
175180
ifeq ($(FPGA_TARGET), ORANGE-CRAB-0.21)
176181
RESET_LOW=true
177182
CLK_INPUT=48000000
178-
CLK_FREQUENCY=40000000
179-
LPF=constraints/orange-crab.lpf
183+
CLK_FREQUENCY=48000000
184+
LPF=constraints/orange-crab-0.2.lpf
180185
PACKAGE=CSFBGA285
181-
NEXTPNR_FLAGS=--85k --speed 8 --freq 40
186+
NEXTPNR_FLAGS=--85k --speed 8 --freq 48 --timing-allow-fail --ignore-loops
182187
OPENOCD_JTAG_CONFIG=openocd/olimex-arm-usb-tiny-h.cfg
183188
OPENOCD_DEVICE_CONFIG=openocd/LFE5U-85F.cfg
184189
DFU_VENDOR=1209
185190
DFU_PRODUCT=5af0
186191
ECP_FLASH_OFFSET=0x80000
192+
toplevel=fpga/top-orangecrab0.2.vhdl
193+
litedram_target=orangecrab-85-0.2
194+
soc_extra_v += litesdcard/generated/lattice/litesdcard_core.v
187195
endif
188196

189197
# ECP5-EVN
@@ -198,12 +206,17 @@ OPENOCD_JTAG_CONFIG=openocd/ecp5-evn.cfg
198206
OPENOCD_DEVICE_CONFIG=openocd/LFE5UM5G-85F.cfg
199207
endif
200208

209+
ifneq ($(litedram_target),)
210+
soc_extra_synth += litedram/extras/litedram-wrapper-l2.vhdl \
211+
litedram/generated/$(litedram_target)/litedram-initmem.vhdl
212+
soc_extra_v += litedram/generated/$(litedram_target)/litedram_core.v
213+
LITEDRAM_GHDL_ARG=-gUSE_LITEDRAM=true
214+
endif
215+
201216
GHDL_IMAGE_GENERICS=-gMEMORY_SIZE=$(MEMORY_SIZE) -gRAM_INIT_FILE=$(RAM_INIT_FILE) \
202-
-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES)
217+
-gRESET_LOW=$(RESET_LOW) -gCLK_INPUT=$(CLK_INPUT) -gCLK_FREQUENCY=$(CLK_FREQUENCY) -gICACHE_NUM_LINES=$(ICACHE_NUM_LINES) \
218+
$(LITEDRAM_GHDL_ARG)
203219

204-
clkgen=fpga/clk_gen_ecp5.vhd
205-
toplevel=fpga/top-generic.vhdl
206-
dmi_dtm=dmi_dtm_dummy.vhdl
207220

208221
ifeq ($(FPGA_TARGET), verilator)
209222
RESET_LOW=true
@@ -216,10 +229,10 @@ fpga_files = fpga/soc_reset.vhdl \
216229
fpga/pp_fifo.vhd fpga/pp_soc_uart.vhd fpga/main_bram.vhdl \
217230
nonrandom.vhdl
218231

219-
synth_files = $(core_files) $(soc_files) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
232+
synth_files = $(core_files) $(soc_files) $(soc_extra_synth) $(fpga_files) $(clkgen) $(toplevel) $(dmi_dtm)
220233

221234
microwatt.json: $(synth_files) $(RAM_INIT_FILE)
222-
$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)"
235+
$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; read_verilog $(uart_files) $(soc_extra_v); synth_ecp5 -abc9 -nowidelut -json $@ $(SYNTH_ECP5_FLAGS)"
223236

224237
microwatt.v: $(synth_files) $(RAM_INIT_FILE)
225238
$(YOSYS) $(GHDLSYNTH) -p "ghdl --std=08 --no-formal $(GHDL_IMAGE_GENERICS) $(synth_files) -e toplevel; write_verilog $@"

‎constraints/orange-crab-0.2.lpf‎

Lines changed: 225 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,225 @@
1+
LOCATE COMP "ext_clk" SITE "A9";
2+
IOBUF PORT "ext_clk" IO_TYPE=LVCMOS33;
3+
4+
// LOCATE COMP "ext_rst_n" SITE "J2"; // io_13
5+
// IOBUF PORT "ext_rst_n" PULLMODE=UP IO_TYPE=LVCMOS33 DRIVE=4;
6+
7+
// user_button as reset
8+
LOCATE COMP "ext_rst_n" SITE "J17";
9+
IOBUF PORT "ext_rst_n" IO_TYPE=SSTL135_I;
10+
11+
LOCATE COMP "usb_d_p" SITE "N1";
12+
LOCATE COMP "usb_d_n" SITE "M2";
13+
LOCATE COMP "usb_pullup" SITE "N2";
14+
15+
IOBUF PORT "usb_d_p" IO_TYPE=LVCMOS33;
16+
IOBUF PORT "usb_d_n" IO_TYPE=LVCMOS33;
17+
IOBUF PORT "usb_pullup" IO_TYPE=LVCMOS33;
18+
19+
LOCATE COMP "led0_g" SITE "M3";
20+
LOCATE COMP "led0_r" SITE "K4";
21+
LOCATE COMP "led0_b" SITE "J3";
22+
23+
IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
24+
IOBUF PORT "led0_g" IO_TYPE=LVCMOS33;
25+
IOBUF PORT "led0_b" IO_TYPE=LVCMOS33;
26+
27+
// discontinuous gpio numbers, match orangecrab litex platform
28+
LOCATE COMP "pin_gpio_0" SITE "N17"; // tx
29+
LOCATE COMP "pin_gpio_1" SITE "M18"; // rx
30+
LOCATE COMP "pin_gpio_2" SITE "C10"; // sda
31+
LOCATE COMP "pin_gpio_3" SITE "C9"; // scl
32+
//
33+
LOCATE COMP "pin_gpio_5" SITE "B10"; // io_5
34+
LOCATE COMP "pin_gpio_6" SITE "B9"; // ...
35+
//
36+
LOCATE COMP "pin_gpio_9" SITE "C8"; //
37+
LOCATE COMP "pin_gpio_10" SITE "B8"; //
38+
LOCATE COMP "pin_gpio_11" SITE "A8"; //
39+
LOCATE COMP "pin_gpio_12" SITE "H2"; //
40+
LOCATE COMP "pin_gpio_13" SITE "J2"; // io_13
41+
LOCATE COMP "pin_gpio_14" SITE "N15"; // miso
42+
LOCATE COMP "pin_gpio_15" SITE "R17"; // sck
43+
LOCATE COMP "pin_gpio_16" SITE "N16"; // mosi
44+
45+
LOCATE COMP "pin_io_a0" SITE "L4";
46+
LOCATE COMP "pin_io_a1" SITE "N3";
47+
LOCATE COMP "pin_io_a2" SITE "N4";
48+
LOCATE COMP "pin_io_a3" SITE "H4";
49+
LOCATE COMP "pin_io_a4" SITE "G4";
50+
LOCATE COMP "pin_io_a5" SITE "T17";
51+
52+
IOBUF PORT "pin_gpio_0" IO_TYPE=LVCMOS33;
53+
IOBUF PORT "pin_gpio_1" IO_TYPE=LVCMOS33;
54+
IOBUF PORT "pin_gpio_2" IO_TYPE=LVCMOS33;
55+
IOBUF PORT "pin_gpio_3" IO_TYPE=LVCMOS33;
56+
IOBUF PORT "pin_gpio_5" IO_TYPE=LVCMOS33;
57+
IOBUF PORT "pin_gpio_6" IO_TYPE=LVCMOS33;
58+
IOBUF PORT "pin_gpio_9" IO_TYPE=LVCMOS33;
59+
IOBUF PORT "pin_gpio_10" IO_TYPE=LVCMOS33;
60+
IOBUF PORT "pin_gpio_11" IO_TYPE=LVCMOS33;
61+
IOBUF PORT "pin_gpio_12" IO_TYPE=LVCMOS33;
62+
IOBUF PORT "pin_gpio_13" IO_TYPE=LVCMOS33;
63+
IOBUF PORT "pin_gpio_14" IO_TYPE=LVCMOS33;
64+
IOBUF PORT "pin_gpio_15" IO_TYPE=LVCMOS33;
65+
IOBUF PORT "pin_gpio_16" IO_TYPE=LVCMOS33;
66+
IOBUF PORT "pin_io_a0" IO_TYPE=LVCMOS33;
67+
IOBUF PORT "pin_io_a1" IO_TYPE=LVCMOS33;
68+
IOBUF PORT "pin_io_a2" IO_TYPE=LVCMOS33;
69+
IOBUF PORT "pin_io_a3" IO_TYPE=LVCMOS33;
70+
IOBUF PORT "pin_io_a4" IO_TYPE=LVCMOS33;
71+
IOBUF PORT "pin_io_a5" IO_TYPE=LVCMOS33;
72+
73+
LOCATE COMP "ddram_a[0]" SITE "C4";
74+
LOCATE COMP "ddram_a[1]" SITE "D2";
75+
LOCATE COMP "ddram_a[2]" SITE "D3";
76+
LOCATE COMP "ddram_a[3]" SITE "A3";
77+
LOCATE COMP "ddram_a[4]" SITE "A4";
78+
LOCATE COMP "ddram_a[5]" SITE "D4";
79+
LOCATE COMP "ddram_a[6]" SITE "C3";
80+
LOCATE COMP "ddram_a[7]" SITE "B2";
81+
LOCATE COMP "ddram_a[8]" SITE "B1";
82+
LOCATE COMP "ddram_a[9]" SITE "D1";
83+
LOCATE COMP "ddram_a[10]" SITE "A7";
84+
LOCATE COMP "ddram_a[11]" SITE "C2";
85+
LOCATE COMP "ddram_a[12]" SITE "B6";
86+
LOCATE COMP "ddram_a[13]" SITE "C1";
87+
LOCATE COMP "ddram_a[14]" SITE "A2";
88+
LOCATE COMP "ddram_a[15]" SITE "C7";
89+
IOBUF PORT "ddram_a[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
90+
IOBUF PORT "ddram_a[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
91+
IOBUF PORT "ddram_a[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
92+
IOBUF PORT "ddram_a[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
93+
IOBUF PORT "ddram_a[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
94+
IOBUF PORT "ddram_a[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
95+
IOBUF PORT "ddram_a[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
96+
IOBUF PORT "ddram_a[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
97+
IOBUF PORT "ddram_a[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
98+
IOBUF PORT "ddram_a[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
99+
IOBUF PORT "ddram_a[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
100+
IOBUF PORT "ddram_a[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
101+
IOBUF PORT "ddram_a[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
102+
IOBUF PORT "ddram_a[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
103+
IOBUF PORT "ddram_a[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
104+
IOBUF PORT "ddram_a[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
105+
106+
LOCATE COMP "ddram_ba[0]" SITE "D6";
107+
LOCATE COMP "ddram_ba[1]" SITE "B7";
108+
LOCATE COMP "ddram_ba[2]" SITE "A6";
109+
LOCATE COMP "ddram_cas_n" SITE "D13";
110+
LOCATE COMP "ddram_cs_n" SITE "A12";
111+
LOCATE COMP "ddram_dm[0]" SITE "D16";
112+
LOCATE COMP "ddram_dm[1]" SITE "G16";
113+
LOCATE COMP "ddram_ras_n" SITE "C12";
114+
LOCATE COMP "ddram_we_n" SITE "B12";
115+
IOBUF PORT "ddram_ba[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
116+
IOBUF PORT "ddram_ba[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
117+
IOBUF PORT "ddram_ba[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
118+
IOBUF PORT "ddram_cas_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
119+
IOBUF PORT "ddram_cs_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
120+
IOBUF PORT "ddram_dm[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
121+
IOBUF PORT "ddram_dm[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST;
122+
IOBUF PORT "ddram_ras_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
123+
IOBUF PORT "ddram_we_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
124+
125+
// from litex platform, termination disabled to reduce heat
126+
LOCATE COMP "ddram_dq[0]" SITE "C17";
127+
LOCATE COMP "ddram_dq[1]" SITE "D15";
128+
LOCATE COMP "ddram_dq[2]" SITE "B17";
129+
LOCATE COMP "ddram_dq[3]" SITE "C16";
130+
LOCATE COMP "ddram_dq[4]" SITE "A15";
131+
LOCATE COMP "ddram_dq[5]" SITE "B13";
132+
LOCATE COMP "ddram_dq[6]" SITE "A17";
133+
LOCATE COMP "ddram_dq[7]" SITE "A13";
134+
LOCATE COMP "ddram_dq[8]" SITE "F17";
135+
LOCATE COMP "ddram_dq[9]" SITE "F16";
136+
LOCATE COMP "ddram_dq[10]" SITE "G15";
137+
LOCATE COMP "ddram_dq[11]" SITE "F15";
138+
LOCATE COMP "ddram_dq[12]" SITE "J16";
139+
LOCATE COMP "ddram_dq[13]" SITE "C18";
140+
LOCATE COMP "ddram_dq[14]" SITE "H16";
141+
LOCATE COMP "ddram_dq[15]" SITE "F18";
142+
IOBUF PORT "ddram_dq[0]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
143+
IOBUF PORT "ddram_dq[1]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
144+
IOBUF PORT "ddram_dq[2]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
145+
IOBUF PORT "ddram_dq[3]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
146+
IOBUF PORT "ddram_dq[4]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
147+
IOBUF PORT "ddram_dq[5]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
148+
IOBUF PORT "ddram_dq[6]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
149+
IOBUF PORT "ddram_dq[7]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
150+
IOBUF PORT "ddram_dq[8]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
151+
IOBUF PORT "ddram_dq[9]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
152+
IOBUF PORT "ddram_dq[10]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
153+
IOBUF PORT "ddram_dq[11]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
154+
IOBUF PORT "ddram_dq[12]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
155+
IOBUF PORT "ddram_dq[13]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
156+
IOBUF PORT "ddram_dq[14]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
157+
IOBUF PORT "ddram_dq[15]" IO_TYPE=SSTL135_I SLEWRATE=FAST TERMINATION=OFF;
158+
159+
LOCATE COMP "ddram_dqs_n[0]" SITE "A16";
160+
LOCATE COMP "ddram_dqs_n[1]" SITE "H17";
161+
LOCATE COMP "ddram_dqs_p[0]" SITE "B15";
162+
LOCATE COMP "ddram_dqs_p[1]" SITE "G18";
163+
IOBUF PORT "ddram_dqs_n[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
164+
IOBUF PORT "ddram_dqs_n[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
165+
IOBUF PORT "ddram_dqs_p[0]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
166+
IOBUF PORT "ddram_dqs_p[1]" IO_TYPE=SSTL135D_I SLEWRATE=FAST DIFFRESISTOR=100 TERMINATION=OFF;
167+
168+
LOCATE COMP "ddram_clk_p" SITE "J18";
169+
LOCATE COMP "ddram_clk_n" SITE "K18";
170+
IOBUF PORT "ddram_clk_p" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
171+
IOBUF PORT "ddram_clk_n" IO_TYPE=SSTL135D_I SLEWRATE=FAST;
172+
173+
LOCATE COMP "ddram_cke" SITE "D18";
174+
LOCATE COMP "ddram_odt" SITE "C13";
175+
LOCATE COMP "ddram_reset_n" SITE "L18";
176+
IOBUF PORT "ddram_cke" IO_TYPE=SSTL135_I SLEWRATE=FAST;
177+
IOBUF PORT "ddram_odt" IO_TYPE=SSTL135_I SLEWRATE=FAST;
178+
IOBUF PORT "ddram_reset_n" IO_TYPE=SSTL135_I SLEWRATE=FAST;
179+
180+
LOCATE COMP "ddram_vccio[0]" SITE "K16";
181+
LOCATE COMP "ddram_vccio[1]" SITE "D17";
182+
LOCATE COMP "ddram_vccio[2]" SITE "K15";
183+
LOCATE COMP "ddram_vccio[3]" SITE "K17";
184+
LOCATE COMP "ddram_vccio[4]" SITE "B18";
185+
LOCATE COMP "ddram_vccio[5]" SITE "C6";
186+
LOCATE COMP "ddram_gnd[0]" SITE "L15";
187+
LOCATE COMP "ddram_gnd[1]" SITE "L16";
188+
IOBUF PORT "ddram_vccio[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
189+
IOBUF PORT "ddram_vccio[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
190+
IOBUF PORT "ddram_vccio[2]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
191+
IOBUF PORT "ddram_vccio[3]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
192+
IOBUF PORT "ddram_vccio[4]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
193+
IOBUF PORT "ddram_vccio[5]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
194+
IOBUF PORT "ddram_gnd[0]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
195+
IOBUF PORT "ddram_gnd[1]" IO_TYPE=SSTL135_II SLEWRATE=FAST;
196+
197+
// We use USRMCLK instead for clk
198+
// LOCATE COMP "spi_flash_clk" SITE "U16";
199+
// IOBUF PORT "spi_flash_clk" IO_TYPE=LVCMOS33;
200+
LOCATE COMP "spi_flash_cs_n" SITE "U17";
201+
IOBUF PORT "spi_flash_cs_n" IO_TYPE=LVCMOS33;
202+
LOCATE COMP "spi_flash_mosi" SITE "U18";
203+
IOBUF PORT "spi_flash_mosi" IO_TYPE=LVCMOS33;
204+
LOCATE COMP "spi_flash_miso" SITE "T18";
205+
IOBUF PORT "spi_flash_miso" IO_TYPE=LVCMOS33;
206+
LOCATE COMP "spi_flash_wp_n" SITE "R18";
207+
IOBUF PORT "spi_flash_wp_n" IO_TYPE=LVCMOS33;
208+
LOCATE COMP "spi_flash_hold_n" SITE "N18";
209+
IOBUF PORT "spi_flash_hold_n" IO_TYPE=LVCMOS33;
210+
211+
LOCATE COMP "sdcard_data[0]" SITE "J1";
212+
LOCATE COMP "sdcard_data[1]" SITE "K3";
213+
LOCATE COMP "sdcard_data[2]" SITE "L3";
214+
LOCATE COMP "sdcard_data[3]" SITE "M1";
215+
LOCATE COMP "sdcard_cmd" SITE "K2";
216+
LOCATE COMP "sdcard_clk" SITE "K1";
217+
LOCATE COMP "sdcard_cd" SITE "L1";
218+
219+
IOBUF PORT "sdcard_data[0]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
220+
IOBUF PORT "sdcard_data[1]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
221+
IOBUF PORT "sdcard_data[2]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
222+
IOBUF PORT "sdcard_data[3]" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
223+
IOBUF PORT "sdcard_cmd" IO_TYPE=LVCMOS33 SLEWRATE=FAST PULLMODE=UP;
224+
IOBUF PORT "sdcard_clk" IO_TYPE=LVCMOS33 SLEWRATE=FAST;
225+
IOBUF PORT "sdcard_cd" IO_TYPE=LVCMOS33;

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