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mikeymikey
authored
Merge pull request #216 from paulusmack/cfar
Timing and speed improvements, implement CFAR register
2 parents 419c9a6 + 7406219 commit ce0205b

8 files changed

Lines changed: 152 additions & 93 deletions

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‎common.vhdl‎

Lines changed: 6 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -31,6 +31,7 @@ package common is
3131
constant SPR_DEC : spr_num_t := 22;
3232
constant SPR_SRR0 : spr_num_t := 26;
3333
constant SPR_SRR1 : spr_num_t := 27;
34+
constant SPR_CFAR : spr_num_t := 28;
3435
constant SPR_HSRR0 : spr_num_t := 314;
3536
constant SPR_HSRR1 : spr_num_t := 315;
3637
constant SPR_SPRG0 : spr_num_t := 272;
@@ -94,8 +95,8 @@ package common is
9495
tb: std_ulogic_vector(63 downto 0);
9596
dec: std_ulogic_vector(63 downto 0);
9697
msr: std_ulogic_vector(63 downto 0);
98+
cfar: std_ulogic_vector(63 downto 0);
9799
irq_state : irq_state_t;
98-
irq_nia: std_ulogic_vector(63 downto 0);
99100
srr1: std_ulogic_vector(63 downto 0);
100101
end record;
101102

@@ -150,6 +151,7 @@ package common is
150151
bypass_data2: std_ulogic;
151152
bypass_data3: std_ulogic;
152153
cr: std_ulogic_vector(31 downto 0);
154+
bypass_cr : std_ulogic;
153155
xerc: xer_common_t;
154156
lr: std_ulogic;
155157
rc: std_ulogic;
@@ -172,7 +174,7 @@ package common is
172174
end record;
173175
constant Decode2ToExecute1Init : Decode2ToExecute1Type :=
174176
(valid => '0', unit => NONE, insn_type => OP_ILLEGAL, bypass_data1 => '0', bypass_data2 => '0', bypass_data3 => '0',
175-
lr => '0', rc => '0', oe => '0', invert_a => '0',
177+
bypass_cr => '0', lr => '0', rc => '0', oe => '0', invert_a => '0',
176178
invert_out => '0', input_carry => ZERO, output_carry => '0', input_cr => '0', output_cr => '0',
177179
is_32bit => '0', is_signed => '0', xerc => xerc_init, reserve => '0', br_pred => '0',
178180
byte_reverse => '0', sign_extend => '0', update => '0', nia => (others => '0'), read_data1 => (others => '0'), read_data2 => (others => '0'), read_data3 => (others => '0'), cr => (others => '0'), insn => (others => '0'), data_len => (others => '0'), others => (others => '0'));
@@ -232,8 +234,8 @@ package common is
232234
priv_mode: std_ulogic;
233235
redirect_nia: std_ulogic_vector(63 downto 0);
234236
end record;
235-
constant Execute1ToFetch1TypeInit : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
236-
priv_mode => '0', others => (others => '0'));
237+
constant Execute1ToFetch1Init : Execute1ToFetch1Type := (redirect => '0', virt_mode => '0',
238+
priv_mode => '0', others => (others => '0'));
237239

238240
type Execute1ToLoadstore1Type is record
239241
valid : std_ulogic;

‎control.vhdl‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -38,14 +38,16 @@ entity control is
3838

3939
cr_read_in : in std_ulogic;
4040
cr_write_in : in std_ulogic;
41+
cr_bypassable : in std_ulogic;
4142

4243
valid_out : out std_ulogic;
4344
stall_out : out std_ulogic;
4445
stopped_out : out std_ulogic;
4546

4647
gpr_bypass_a : out std_ulogic;
4748
gpr_bypass_b : out std_ulogic;
48-
gpr_bypass_c : out std_ulogic
49+
gpr_bypass_c : out std_ulogic;
50+
cr_bypass : out std_ulogic
4951
);
5052
end entity control;
5153

@@ -161,8 +163,10 @@ begin
161163

162164
cr_read_in => cr_read_in,
163165
cr_write_in => cr_write_valid,
166+
bypassable => cr_bypassable,
164167

165-
stall_out => cr_stall_out
168+
stall_out => cr_stall_out,
169+
use_bypass => cr_bypass
166170
);
167171

168172
control0: process(clk)

‎cr_hazard.vhdl‎

Lines changed: 21 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -16,15 +16,18 @@ entity cr_hazard is
1616

1717
cr_read_in : in std_ulogic;
1818
cr_write_in : in std_ulogic;
19+
bypassable : in std_ulogic;
1920

20-
stall_out : out std_ulogic
21+
stall_out : out std_ulogic;
22+
use_bypass : out std_ulogic
2123
);
2224
end entity cr_hazard;
2325
architecture behaviour of cr_hazard is
2426
type pipeline_entry_type is record
25-
valid : std_ulogic;
27+
valid : std_ulogic;
28+
bypass : std_ulogic;
2629
end record;
27-
constant pipeline_entry_init : pipeline_entry_type := (valid => '0');
30+
constant pipeline_entry_init : pipeline_entry_type := (valid => '0', bypass => '0');
2831

2932
type pipeline_t is array(0 to PIPELINE_DEPTH) of pipeline_entry_type;
3033
constant pipeline_t_init : pipeline_t := (others => pipeline_entry_init);
@@ -47,7 +50,20 @@ begin
4750
if complete_in = '1' then
4851
v(1).valid := '0';
4952
end if;
50-
stall_out <= cr_read_in and (v(0).valid or v(1).valid);
53+
54+
use_bypass <= '0';
55+
stall_out <= '0';
56+
if cr_read_in = '1' then
57+
loop_0: for i in 0 to PIPELINE_DEPTH loop
58+
if v(i).valid = '1' then
59+
if r(i).bypass = '1' then
60+
use_bypass <= '1';
61+
else
62+
stall_out <= '1';
63+
end if;
64+
end if;
65+
end loop;
66+
end if;
5167

5268
-- XXX assumes PIPELINE_DEPTH = 1
5369
if busy_in = '0' then
@@ -56,6 +72,7 @@ begin
5672
end if;
5773
if deferred = '0' and issuing = '1' then
5874
v(0).valid := cr_write_in;
75+
v(0).bypass := bypassable;
5976
end if;
6077
if flush_in = '1' then
6178
v(0).valid := '0';

‎decode1.vhdl‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -60,7 +60,7 @@ architecture behaviour of decode1 is
6060
41 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is2B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- lhzu
6161
32 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- lwz
6262
33 => (LDST, OP_LOAD, RA_OR_ZERO, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', is4B, '0', '0', '1', '0', '0', '0', NONE, '0', '0'), -- lwzu
63-
7 => (ALU, OP_MUL_L64, RA, CONST_SI, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0'), -- mulli
63+
7 => (ALU, OP_MUL_L64, RA, CONST_SI, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', NONE, '0', '0'), -- mulli
6464
24 => (ALU, OP_OR, NONE, CONST_UI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- ori
6565
25 => (ALU, OP_OR, NONE, CONST_UI_HI, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- oris
6666
20 => (ALU, OP_RLC, RA, CONST_SH32, RS, RA, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- rlwimi
@@ -262,19 +262,19 @@ architecture behaviour of decode1 is
262262
2#0010010000# => (ALU, OP_MTCRF, NONE, NONE, RS, NONE, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- mtcrf/mtocrf
263263
2#0010110010# => (ALU, OP_MTMSRD, NONE, NONE, RS, NONE, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '1'), -- mtmsrd # ignore top bits and d
264264
2#0111010011# => (ALU, OP_MTSPR, NONE, NONE, RS, SPR, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', NONE, '0', '0'), -- mtspr
265-
2#0001001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulhd
266-
2#0000001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- mulhdu
267-
2#0001001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mulhw
268-
2#0000001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- mulhwu
265+
2#0001001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulhd
266+
2#0000001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- mulhdu
267+
2#0001001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mulhw
268+
2#0000001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- mulhwu
269269
-- next 4 have reserved bit set
270-
2#1001001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulhd
271-
2#1000001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- mulhdu
272-
2#1001001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mulhw
273-
2#1000001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- mulhwu
274-
2#0011101001# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulld
275-
2#1011101001# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulldo
276-
2#0011101011# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mullw
277-
2#1011101011# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '1', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mullwo
270+
2#1001001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulhd
271+
2#1000001001# => (ALU, OP_MUL_H64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- mulhdu
272+
2#1001001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mulhw
273+
2#1000001011# => (ALU, OP_MUL_H32, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '0', RC, '0', '0'), -- mulhwu
274+
2#0011101001# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulld
275+
2#1011101001# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '0', '1', RC, '0', '0'), -- mulldo
276+
2#0011101011# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mullw
277+
2#1011101011# => (ALU, OP_MUL_L64, RA, RB, NONE, RT, '0', '0', '0', '0', ZERO, '0', NONE, '0', '0', '0', '0', '1', '1', RC, '0', '0'), -- mullwo
278278
2#0111011100# => (ALU, OP_AND, NONE, RB, RS, RA, '0', '0', '0', '1', ZERO, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- nand
279279
2#0001101000# => (ALU, OP_ADD, RA, NONE, NONE, RT, '0', '0', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- neg
280280
2#1001101000# => (ALU, OP_ADD, RA, NONE, NONE, RT, '0', '0', '1', '0', ONE, '0', NONE, '0', '0', '0', '0', '0', '0', RC, '0', '0'), -- nego
@@ -473,8 +473,8 @@ begin
473473
end if;
474474
else
475475
-- Could be OP_RFID
476-
v.ispr1 := fast_spr_num(SPR_SRR0);
477-
v.ispr2 := fast_spr_num(SPR_SRR1);
476+
v.ispr1 := fast_spr_num(SPR_SRR1);
477+
v.ispr2 := fast_spr_num(SPR_SRR0);
478478
end if;
479479

480480
elsif majorop = "011110" then

‎decode2.vhdl‎

Lines changed: 12 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -213,7 +213,10 @@ architecture behaviour of decode2 is
213213
signal gpr_c_read : gpr_index_t;
214214
signal gpr_c_bypass : std_ulogic;
215215

216-
signal cr_write_valid : std_ulogic;
216+
signal cr_write_valid : std_ulogic;
217+
signal cr_bypass : std_ulogic;
218+
signal cr_bypass_avail : std_ulogic;
219+
217220
begin
218221
control_0: entity work.control
219222
generic map (
@@ -248,7 +251,9 @@ begin
248251
gpr_c_read_in => gpr_c_read,
249252

250253
cr_read_in => d_in.decode.input_cr,
251-
cr_write_in => cr_write_valid,
254+
cr_write_in => cr_write_valid,
255+
cr_bypass => cr_bypass,
256+
cr_bypassable => cr_bypass_avail,
252257

253258
valid_out => control_valid_out,
254259
stall_out => stall_out,
@@ -342,6 +347,7 @@ begin
342347
v.e.oe := decode_oe(d_in.decode.rc, d_in.insn);
343348
end if;
344349
v.e.cr := c_in.read_cr_data;
350+
v.e.bypass_cr := cr_bypass;
345351
v.e.xerc := c_in.read_xerc_data;
346352
v.e.invert_a := d_in.decode.invert_a;
347353
v.e.invert_out := d_in.decode.invert_out;
@@ -388,6 +394,10 @@ begin
388394
gpr_c_read <= gspr_to_gpr(decoded_reg_c.reg);
389395

390396
cr_write_valid <= d_in.decode.output_cr or decode_rc(d_in.decode.rc, d_in.insn);
397+
cr_bypass_avail <= '0';
398+
if EX1_BYPASS then
399+
cr_bypass_avail <= d_in.decode.output_cr;
400+
end if;
391401

392402
v.e.valid := control_valid_out;
393403
if d_in.decode.unit = NONE then

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