|
| 1 | +// SPDX-FileCopyrightText : © 2026 TU Wien <vadl@tuwien.ac.at> |
| 2 | +// SPDX-License-Identifier: GPL-3.0-or-later |
| 3 | +// |
| 4 | +// This program is free software: you can redistribute it and/or modify |
| 5 | +// it under the terms of the GNU General Public License as published by |
| 6 | +// the Free Software Foundation, either version 3 of the License, or |
| 7 | +// (at your option) any later version. |
| 8 | +// |
| 9 | +// This program is distributed in the hope that it will be useful, |
| 10 | +// but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 11 | +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 12 | +// GNU General Public License for more details. |
| 13 | +// |
| 14 | +// You should have received a copy of the GNU General Public License |
| 15 | +// along with this program. If not, see <https://www.gnu.org/licenses/>. |
| 16 | + |
| 17 | +package vadl.viam; |
| 18 | + |
| 19 | +import java.util.List; |
| 20 | +import java.util.Map; |
| 21 | + |
| 22 | +public class UserModeEmulation extends Definition { |
| 23 | + private final int sysReg; // e.g., 17 for RISC-V a7 (syscall number) |
| 24 | + private final int retReg; // e.g., 10 for RISC-V a0 (return value) |
| 25 | + private final int spReg; // Stack Pointer (e.g., 2 for RISC-V) |
| 26 | + private final int raReg; // Return Address (e.g., 1 for RISC-V) |
| 27 | + private final int tpReg; // Thread Pointer |
| 28 | + private final List<Integer> args; // Argument registers (e.g., [10, 11, 12, 13, 14, 15]) |
| 29 | + private final Map<String, Integer> excIds; // Exception IDs mapping |
| 30 | + |
| 31 | + /** |
| 32 | + * Constructs a UserModeEmulation configuration. |
| 33 | + */ |
| 34 | + public UserModeEmulation( |
| 35 | + Identifier identifier, |
| 36 | + int sysReg, |
| 37 | + int retReg, |
| 38 | + int spReg, |
| 39 | + int raReg, |
| 40 | + int tpReg, |
| 41 | + List<Integer> args, |
| 42 | + Map<String, Integer> excIds) { |
| 43 | + super(identifier); |
| 44 | + this.sysReg = sysReg; |
| 45 | + this.retReg = retReg; |
| 46 | + this.spReg = spReg; |
| 47 | + this.raReg = raReg; |
| 48 | + this.tpReg = tpReg; |
| 49 | + this.args = args; |
| 50 | + this.excIds = excIds; |
| 51 | + } |
| 52 | + |
| 53 | + public int sysReg() { |
| 54 | + return sysReg; |
| 55 | + } |
| 56 | + |
| 57 | + public int retReg() { |
| 58 | + return retReg; |
| 59 | + } |
| 60 | + |
| 61 | + public int spReg() { |
| 62 | + return spReg; |
| 63 | + } |
| 64 | + |
| 65 | + public int raReg() { |
| 66 | + return raReg; |
| 67 | + } |
| 68 | + |
| 69 | + public int tpReg() { |
| 70 | + return tpReg; |
| 71 | + } |
| 72 | + |
| 73 | + public List<Integer> args() { |
| 74 | + return args; |
| 75 | + } |
| 76 | + |
| 77 | + public Map<String, Integer> excIds() { |
| 78 | + return excIds; |
| 79 | + } |
| 80 | + |
| 81 | + @Override |
| 82 | + public void accept(DefinitionVisitor visitor) { |
| 83 | + visitor.visit(this); |
| 84 | + } |
| 85 | + |
| 86 | + @Override |
| 87 | + public String toString() { |
| 88 | + return simpleName() + " [sysReg=" + sysReg + ", retReg=" + retReg + ", spReg=" + spReg |
| 89 | + + ", raReg=" + raReg + ", tpReg=" + tpReg + ", args=" + args + ", excIds=" + excIds + "]"; |
| 90 | + } |
| 91 | +} |
0 commit comments