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viam: Remove the GeneratesRegisterFileName interface
1 parent 779593a commit 0ff2bb9

24 files changed

Lines changed: 189 additions & 222 deletions

‎vadl/main/vadl/gcb/passes/operands/model/GcbInstructionRegisterFileOperand.java‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -19,8 +19,7 @@
1919
import java.util.List;
2020
import vadl.gcb.passes.operands.ReferencesFormatField;
2121
import vadl.viam.Format;
22-
import vadl.viam.GeneratesRegisterFileName;
23-
import vadl.viam.RegisterTensor;
22+
import vadl.viam.RegisterResource;
2423
import vadl.viam.graph.dependency.FieldRefNode;
2524
import vadl.viam.graph.dependency.ReadArtificialResNode;
2625
import vadl.viam.graph.dependency.ReadRegTensorNode;
@@ -33,7 +32,7 @@
3332
public class GcbInstructionRegisterFileOperand
3433
extends GcbDefaultInstructionOperand
3534
implements ReferencesFormatField {
36-
private final GeneratesRegisterFileName registerFile;
35+
private final RegisterResource registerFile;
3736
private final Format.Field formatField;
3837

3938
/**
@@ -79,7 +78,7 @@ public GcbInstructionRegisterFileOperand(WriteArtificialResNode node, Format.Fie
7978
.ensure(registerFile.isRegisterFile(), "must be registerfile");
8079
}
8180

82-
public GeneratesRegisterFileName registerFile() {
81+
public RegisterResource registerFile() {
8382
return registerFile;
8483
}
8584

‎vadl/main/vadl/gcb/valuetypes/CompilerRegister.java‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -19,7 +19,7 @@
1919
import java.util.ArrayList;
2020
import java.util.List;
2121
import java.util.Objects;
22-
import vadl.viam.GeneratesRegisterFileName;
22+
import vadl.viam.RegisterResource;
2323

2424
/**
2525
* Extends the register with information which a compiler requires.
@@ -94,7 +94,7 @@ public int hashCode() {
9494
protected final List<String> altNames;
9595
protected final List<CompilerRegister> subRegs;
9696
protected final List<SubRegIndex> subRegIndices;
97-
protected final GeneratesRegisterFileName registerFile;
97+
protected final RegisterResource registerFile;
9898

9999
protected final int dwarfNumber;
100100
protected final int hwEncodingValue;
@@ -109,7 +109,7 @@ public CompilerRegister(String name,
109109
int dwarfNumber,
110110
int hwEncodingValue,
111111
boolean isArtificial,
112-
GeneratesRegisterFileName registerFile) {
112+
RegisterResource registerFile) {
113113
this.name = name;
114114
this.asmName = asmName;
115115
this.altNames = altNames;
@@ -153,7 +153,7 @@ public List<SubRegIndex> subRegIndices() {
153153
return subRegIndices;
154154
}
155155

156-
public GeneratesRegisterFileName registerFile() {
156+
public RegisterResource registerFile() {
157157
return registerFile;
158158
}
159159

‎vadl/main/vadl/gcb/valuetypes/CompilerRegisterClass.java‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -18,22 +18,22 @@
1818

1919
import java.util.List;
2020
import vadl.viam.Abi;
21-
import vadl.viam.GeneratesRegisterFileName;
21+
import vadl.viam.RegisterResource;
2222
import vadl.viam.ViamError;
2323

2424
/**
2525
* Extends the concept of the register class for the compiler.
2626
*/
2727
public class CompilerRegisterClass {
2828
private final String name;
29-
private final GeneratesRegisterFileName registerFile;
29+
private final RegisterResource registerFile;
3030
private final List<CompilerRegister> registers;
3131
private final Abi.Alignment alignment;
3232

3333
/**
3434
* Constructor.
3535
*/
36-
public CompilerRegisterClass(GeneratesRegisterFileName registerFile,
36+
public CompilerRegisterClass(RegisterResource registerFile,
3737
List<CompilerRegister> registers,
3838
Abi.Alignment alignment) {
3939
ViamError.ensure(registerFile.isRegisterFile(), "must be register file");
@@ -55,7 +55,7 @@ public Abi.Alignment alignment() {
5555
return alignment;
5656
}
5757

58-
public GeneratesRegisterFileName registerFile() {
58+
public RegisterResource registerFile() {
5959
return registerFile;
6060
}
6161
}

‎vadl/main/vadl/gcb/valuetypes/CompilerRegisterUtils.java‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
// SPDX-FileCopyrightText : © 2026 TU Wien <vadl@tuwien.ac.at>
2+
// SPDX-License-Identifier: GPL-3.0-or-later
3+
//
4+
// This program is free software: you can redistribute it and/or modify
5+
// it under the terms of the GNU General Public License as published by
6+
// the Free Software Foundation, either version 3 of the License, or
7+
// (at your option) any later version.
8+
//
9+
// This program is distributed in the hope that it will be useful,
10+
// but WITHOUT ANY WARRANTY; without even the implied warranty of
11+
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+
// GNU General Public License for more details.
13+
//
14+
// You should have received a copy of the GNU General Public License
15+
// along with this program. If not, see <https://www.gnu.org/licenses/>.
16+
17+
package vadl.gcb.valuetypes;
18+
19+
import java.util.List;
20+
import java.util.Optional;
21+
import vadl.viam.Constant;
22+
import vadl.viam.RegisterResource;
23+
import vadl.viam.ViamError;
24+
25+
/**
26+
* Utility methods for compiler-facing register names and register-file conventions.
27+
*/
28+
public final class CompilerRegisterUtils {
29+
30+
private CompilerRegisterUtils() {
31+
}
32+
33+
/**
34+
* Generates the compiler register name for an indexed register-file entry.
35+
*/
36+
public static String indexedRegisterName(RegisterResource registerFile, int index) {
37+
ViamError.ensure(registerFile.isRegisterFile(), "must be registerFile");
38+
return registerFile.identifier().simpleName() + index;
39+
}
40+
41+
/**
42+
* Returns the index tuple of a zero register if the register file defines one.
43+
*/
44+
public static Optional<List<Constant.Value>> zeroRegister(RegisterResource registerFile) {
45+
return registerFile.constraints()
46+
.stream()
47+
.filter(c -> c.value().intValue() == 0)
48+
.map(RegisterResource.Constraint::indices)
49+
.findFirst();
50+
}
51+
}

‎vadl/main/vadl/gcb/valuetypes/IndexedCompilerRegister.java‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -25,7 +25,7 @@
2525
import java.util.stream.IntStream;
2626
import vadl.utils.Pair;
2727
import vadl.viam.Abi;
28-
import vadl.viam.GeneratesRegisterFileName;
28+
import vadl.viam.RegisterResource;
2929

3030
/**
3131
* Like a {@link CompilerRegister} but contains the index in the register file.
@@ -44,7 +44,7 @@ private IndexedCompilerRegister(String regFileName,
4444
List<String> altNames,
4545
int dwarfNumber,
4646
boolean isArtificial,
47-
GeneratesRegisterFileName registerFile) {
47+
RegisterResource registerFile) {
4848
super(regFileName,
4949
asmName,
5050
altNames,
@@ -66,7 +66,7 @@ private IndexedCompilerRegister(String regFileName,
6666
* @param isArtificial registers in {@code registerFile} do not really exist.
6767
* @return a list of registers generated from the register file.
6868
*/
69-
public static List<CompilerRegister> fromRegisterFile(GeneratesRegisterFileName registerFile,
69+
public static List<CompilerRegister> fromRegisterFile(RegisterResource registerFile,
7070
Abi abi,
7171
int dwarfNumberOffset,
7272
boolean isArtificial) {
@@ -81,13 +81,13 @@ public static List<CompilerRegister> fromRegisterFile(GeneratesRegisterFileName
8181
.stream().map(Abi.RegisterAlias::value).toList();
8282
var alias = altNames
8383
.stream().findFirst()
84-
.orElse(registerFile.generateRegisterFileName(addr));
84+
.orElse(CompilerRegisterUtils.indexedRegisterName(registerFile, addr));
8585

8686
int dwarfNumber = dwarfNumberOffset + addr;
8787

8888
registers.add(
8989
new IndexedCompilerRegister(
90-
registerFile.generateRegisterFileName(addr),
90+
CompilerRegisterUtils.indexedRegisterName(registerFile, addr),
9191
addr,
9292
alias,
9393
altNames,

‎vadl/main/vadl/lcb/passes/llvmLowering/domain/selectionDag/LlvmReadResourceFactory.java‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -21,7 +21,7 @@
2121
import vadl.types.DataType;
2222
import vadl.viam.ArtificialResource;
2323
import vadl.viam.Counter;
24-
import vadl.viam.GeneratesRegisterFileName;
24+
import vadl.viam.RegisterResource;
2525
import vadl.viam.RegisterTensor;
2626
import vadl.viam.graph.dependency.ExpressionNode;
2727
import vadl.viam.graph.dependency.FieldRefNode;
@@ -33,7 +33,7 @@ public class LlvmReadResourceFactory {
3333
/**
3434
* Based on the {@code registerFile} creates a node.
3535
*/
36-
public ExpressionNode create(GeneratesRegisterFileName registerFile,
36+
public ExpressionNode create(RegisterResource registerFile,
3737
FieldRefNode address,
3838
DataType type,
3939
@Nullable Counter counter) {

‎vadl/main/vadl/lcb/passes/llvmLowering/strategies/instruction/LlvmInstructionLoweringIndirectJumpAndLinkStrategyImpl.java‎

Lines changed: 13 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -30,6 +30,7 @@
3030
import vadl.gcb.passes.RegisterRef;
3131
import vadl.gcb.passes.operands.model.GcbInstructionOperand;
3232
import vadl.gcb.passes.operands.model.GcbInstructionRegisterFileOperand;
33+
import vadl.gcb.valuetypes.CompilerRegisterUtils;
3334
import vadl.gcb.valuetypes.ValueType;
3435
import vadl.lcb.passes.isaMatching.IsaMachineInstructionMatchingPass;
3536
import vadl.lcb.passes.isaMatching.database.Database;
@@ -49,12 +50,11 @@
4950
import vadl.lcb.passes.llvmLowering.tablegen.model.TableGenPseudoInstExpansionPattern;
5051
import vadl.lcb.passes.llvmLowering.tablegen.model.TableGenSelectionWithOutputPattern;
5152
import vadl.lcb.passes.operands.TableGenInstructionImmediateOperand;
52-
import vadl.types.DataType;
5353
import vadl.types.Type;
5454
import vadl.viam.Abi;
5555
import vadl.viam.Constant;
56-
import vadl.viam.GeneratesRegisterFileName;
5756
import vadl.viam.Instruction;
57+
import vadl.viam.RegisterResource;
5858
import vadl.viam.graph.Graph;
5959
import vadl.viam.graph.NodeList;
6060
import vadl.viam.graph.dependency.ConstantNode;
@@ -194,7 +194,7 @@ protected List<TableGenPattern> generatePatternVariations(
194194
new LlvmReadRegFileNode(ref.regTensor(), address.copy(), ref.type(),
195195
ref.staticCounterAccess());
196196
machine.addWithInputs(new LcbMachineInstructionNode(
197-
new NodeList<>(new ConstantNode(new Constant.Str(abi.returnAddress().render())),
197+
new NodeList<>(new ConstantNode(new Constant.Str(renderAbiRegister(abi.returnAddress()))),
198198
llvmReadRegFile,
199199
new ConstantNode(constant)), jalr));
200200
return new TableGenPseudoInstExpansionPattern("PseudoCALLIndirect",
@@ -247,7 +247,7 @@ protected List<TableGenPattern> generatePatternVariations(
247247
var machine = new Graph("machine");
248248
machine.addWithInputs(new LcbMachineInstructionNode(
249249
new NodeList<>(
250-
new ConstantNode(new Constant.Str(zeroRegister(inputRegister.registerFile()))),
250+
new ConstantNode(new Constant.Str(zeroRegisterName(inputRegister.registerFile()))),
251251
new LlvmReadRegFileNode(ref.registerTensor(), address, ref.type(),
252252
ref.staticCounterAccess()),
253253
fieldRef), jalr));
@@ -332,15 +332,14 @@ private TableGenPattern generateBranchIndirectWithZero(
332332
return new TableGenSelectionWithOutputPattern(selector, machine);
333333
}
334334

335-
private static String zeroRegister(GeneratesRegisterFileName registerFile) {
336-
var constraint =
337-
ensurePresent(
338-
registerFile.constraints().stream().filter(x -> x.value().intValue() == 0)
339-
.findFirst(),
340-
() -> Diagnostic.error("There must a constraint for the zero register.",
341-
registerFile.location())
342-
);
335+
private static String zeroRegisterName(RegisterResource registerFile) {
336+
var indices = ensurePresent(CompilerRegisterUtils.zeroRegister(registerFile),
337+
() -> Diagnostic.error("There must a constraint for the zero register.",
338+
registerFile.location()));
339+
return CompilerRegisterUtils.indexedRegisterName(registerFile, indices.getFirst().intValue());
340+
}
343341

344-
return registerFile.identifier().simpleName() + constraint.indices().getFirst().intValue();
342+
private static String renderAbiRegister(Abi.AbiRegister register) {
343+
return CompilerRegisterUtils.indexedRegisterName(register.registerFile(), register.addr());
345344
}
346345
}

‎vadl/main/vadl/lcb/passes/llvmLowering/tablegen/model/register/TableGenRegisterClass.java‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -22,7 +22,7 @@
2222
import vadl.gcb.valuetypes.TargetName;
2323
import vadl.gcb.valuetypes.ValueType;
2424
import vadl.template.Renderable;
25-
import vadl.viam.GeneratesRegisterFileName;
25+
import vadl.viam.RegisterResource;
2626

2727
/**
2828
* Represents a single register file in TableGen. This is the lowered representation of a
@@ -35,7 +35,7 @@ public class TableGenRegisterClass implements
3535
private final int alignment;
3636
private final List<ValueType> regTypes;
3737
private final List<TableGenRegister> registers;
38-
private final GeneratesRegisterFileName registerFileRef;
38+
private final RegisterResource registerFileRef;
3939

4040
/**
4141
* Constructor.
@@ -45,7 +45,7 @@ public TableGenRegisterClass(TargetName namespace,
4545
int alignment,
4646
List<ValueType> regTypes,
4747
List<TableGenRegister> registers,
48-
GeneratesRegisterFileName registerFileRef) {
48+
RegisterResource registerFileRef) {
4949
this.namespace = namespace;
5050
this.name = name;
5151
this.alignment = alignment;
@@ -89,7 +89,7 @@ public List<TableGenRegister> registers() {
8989
return registers;
9090
}
9191

92-
public GeneratesRegisterFileName registerFileRef() {
92+
public RegisterResource registerFileRef() {
9393
return registerFileRef;
9494
}
9595
}

‎vadl/main/vadl/lcb/template/LcbTemplateRenderingPass.java‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -23,9 +23,10 @@
2323
import java.util.function.Predicate;
2424
import vadl.configuration.GeneralConfiguration;
2525
import vadl.configuration.LcbConfiguration;
26+
import vadl.gcb.valuetypes.CompilerRegisterUtils;
2627
import vadl.template.AbstractTemplateRenderingPass;
27-
import vadl.viam.GeneratesRegisterFileName;
28-
import vadl.viam.RegisterTensor;
28+
import vadl.viam.Abi;
29+
import vadl.viam.RegisterResource;
2930

3031
/**
3132
* Abstracts the subdir under the output.
@@ -39,8 +40,12 @@ public LcbConfiguration lcbConfiguration() {
3940
return (LcbConfiguration) configuration();
4041
}
4142

42-
protected String renderRegister(GeneratesRegisterFileName registerFile, int addr) {
43-
return registerFile.generateRegisterFileName(addr);
43+
protected String renderRegister(RegisterResource registerFile, int addr) {
44+
return CompilerRegisterUtils.indexedRegisterName(registerFile, addr);
45+
}
46+
47+
protected String renderRegister(Abi.AbiRegister register) {
48+
return renderRegister(register.registerFile(), register.addr());
4449
}
4550

4651
@Override

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