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viam: Extract Abi.RegisterRef and remove GeneratesRegisterFileName interface (#948)
This PR extracts most of the `Abi.RegisterRef` to `vadl.viam.RegisterRef`, so the datastructure can be reused in other definitions like the UME (#834). Additionally, it removes the `GeneratesRegisterFileName` which does not fit into the VIAM hierarchy and is already covered by the `RegisterResource` class.
1 parent a4493ff commit e34b28a

31 files changed

Lines changed: 339 additions & 280 deletions

‎vadl/main/vadl/ast/ViamLowering.java‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -2002,11 +2002,11 @@ public Optional<vadl.viam.Definition> visit(
20022002
}
20032003

20042004
/**
2005-
* Maps a {@link SpecialPurposeRegisterDefinition} to a {@link Abi.RegisterRef}.
2005+
* Maps a {@link SpecialPurposeRegisterDefinition} to a {@link Abi.AbiRegister}.
20062006
* It expects only one register in the {@link SpecialPurposeRegisterDefinition}. Otherwise,
20072007
* it will throw an error.
20082008
*/
2009-
private Abi.RegisterRef mapSingleSpecialPurposeRegisterDef(
2009+
private Abi.AbiRegister mapSingleSpecialPurposeRegisterDef(
20102010
Map<Identifier, Expr> aliasLookup,
20112011
SpecialPurposeRegisterDefinition specialPurposeRegisterDef) {
20122012
return specialPurposeRegisterDef.exprs.stream()
@@ -2015,9 +2015,9 @@ private Abi.RegisterRef mapSingleSpecialPurposeRegisterDef(
20152015
}
20162016

20172017
/**
2018-
* Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.RegisterRef}.
2018+
* Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.AbiRegister}.
20192019
*/
2020-
private List<Abi.RegisterRef> mapSpecialPurposeRegistersDef(
2020+
private List<Abi.AbiRegister> mapSpecialPurposeRegistersDef(
20212021
Map<Identifier, Expr> aliasLookup,
20222022
SpecialPurposeRegisterDefinition specialPurposeRegisterDef) {
20232023
return specialPurposeRegisterDef.exprs.stream()
@@ -2026,12 +2026,12 @@ private List<Abi.RegisterRef> mapSpecialPurposeRegistersDef(
20262026
}
20272027

20282028
/**
2029-
* Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.RegisterRef}.
2029+
* Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.AbiRegister}.
20302030
*/
2031-
private List<List<Abi.RegisterRef>> mapSpecialPurposeRegistersDefs(
2031+
private List<List<Abi.AbiRegister>> mapSpecialPurposeRegistersDefs(
20322032
Map<Identifier, Expr> aliasLookup,
20332033
List<SpecialPurposeRegisterDefinition> specialPurposeRegisterDefs) {
2034-
List<List<Abi.RegisterRef>> result = new ArrayList<>();
2034+
List<List<Abi.AbiRegister>> result = new ArrayList<>();
20352035

20362036
for (var def : specialPurposeRegisterDefs) {
20372037
var iter = def.exprs.stream()
@@ -2044,7 +2044,7 @@ private List<List<Abi.RegisterRef>> mapSpecialPurposeRegistersDefs(
20442044
return result;
20452045
}
20462046

2047-
private Abi.RegisterRef getRegisterRefByAliasOrRegister(
2047+
private Abi.AbiRegister getRegisterRefByAliasOrRegister(
20482048
Map<Identifier, Expr> aliasLookup,
20492049
ExpandedSequenceCallExpr aliasOrRegister) {
20502050
if (aliasOrRegister instanceof ExpandedAliasDefSequenceCallExpr registerCallExpr) {
@@ -2055,10 +2055,10 @@ private Abi.RegisterRef getRegisterRefByAliasOrRegister(
20552055
}
20562056

20572057
/**
2058-
* Maps the aliases {@code alias register zero = X(0)} to {@link Abi.RegisterRef} to be
2058+
* Maps the aliases {@code alias register zero = X(0)} to {@link Abi.AbiRegister} to be
20592059
* used in {@link Abi}.
20602060
*/
2061-
private Abi.RegisterRef mapAliasToRegisterRef(
2061+
private Abi.AbiRegister mapAliasToRegisterRef(
20622062
Map<Identifier, Expr> aliasLookup,
20632063
Identifier identifier) {
20642064
var expr = ensureNonNull(aliasLookup.get(identifier),
@@ -2067,12 +2067,12 @@ private Abi.RegisterRef mapAliasToRegisterRef(
20672067
return mapToRegisterRef(expr);
20682068
}
20692069

2070-
private Abi.RegisterRef mapToRegisterRef(Expr expr) {
2070+
private Abi.AbiRegister mapToRegisterRef(Expr expr) {
20712071
var pair = getRegisterFile(expr);
20722072
var registerFile = pair.left();
20732073
var index = pair.right();
20742074

2075-
return new Abi.RegisterRef(registerFile, index, new Abi.Alignment(-1), expr.location());
2075+
return new Abi.AbiRegister(registerFile, index, new Abi.Alignment(-1), expr.location());
20762076
}
20772077

20782078
/**

‎vadl/main/vadl/gcb/passes/operands/model/GcbInstructionRegisterFileOperand.java‎

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -19,8 +19,7 @@
1919
import java.util.List;
2020
import vadl.gcb.passes.operands.ReferencesFormatField;
2121
import vadl.viam.Format;
22-
import vadl.viam.GeneratesRegisterFileName;
23-
import vadl.viam.RegisterTensor;
22+
import vadl.viam.RegisterResource;
2423
import vadl.viam.graph.dependency.FieldRefNode;
2524
import vadl.viam.graph.dependency.ReadArtificialResNode;
2625
import vadl.viam.graph.dependency.ReadRegTensorNode;
@@ -33,7 +32,7 @@
3332
public class GcbInstructionRegisterFileOperand
3433
extends GcbDefaultInstructionOperand
3534
implements ReferencesFormatField {
36-
private final GeneratesRegisterFileName registerFile;
35+
private final RegisterResource registerFile;
3736
private final Format.Field formatField;
3837

3938
/**
@@ -79,7 +78,7 @@ public GcbInstructionRegisterFileOperand(WriteArtificialResNode node, Format.Fie
7978
.ensure(registerFile.isRegisterFile(), "must be registerfile");
8079
}
8180

82-
public GeneratesRegisterFileName registerFile() {
81+
public RegisterResource registerFile() {
8382
return registerFile;
8483
}
8584

‎vadl/main/vadl/gcb/valuetypes/CompilerRegister.java‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -19,7 +19,7 @@
1919
import java.util.ArrayList;
2020
import java.util.List;
2121
import java.util.Objects;
22-
import vadl.viam.GeneratesRegisterFileName;
22+
import vadl.viam.RegisterResource;
2323

2424
/**
2525
* Extends the register with information which a compiler requires.
@@ -94,7 +94,7 @@ public int hashCode() {
9494
protected final List<String> altNames;
9595
protected final List<CompilerRegister> subRegs;
9696
protected final List<SubRegIndex> subRegIndices;
97-
protected final GeneratesRegisterFileName registerFile;
97+
protected final RegisterResource registerFile;
9898

9999
protected final int dwarfNumber;
100100
protected final int hwEncodingValue;
@@ -109,7 +109,7 @@ public CompilerRegister(String name,
109109
int dwarfNumber,
110110
int hwEncodingValue,
111111
boolean isArtificial,
112-
GeneratesRegisterFileName registerFile) {
112+
RegisterResource registerFile) {
113113
this.name = name;
114114
this.asmName = asmName;
115115
this.altNames = altNames;
@@ -153,7 +153,7 @@ public List<SubRegIndex> subRegIndices() {
153153
return subRegIndices;
154154
}
155155

156-
public GeneratesRegisterFileName registerFile() {
156+
public RegisterResource registerFile() {
157157
return registerFile;
158158
}
159159

‎vadl/main/vadl/gcb/valuetypes/CompilerRegisterClass.java‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -18,22 +18,22 @@
1818

1919
import java.util.List;
2020
import vadl.viam.Abi;
21-
import vadl.viam.GeneratesRegisterFileName;
21+
import vadl.viam.RegisterResource;
2222
import vadl.viam.ViamError;
2323

2424
/**
2525
* Extends the concept of the register class for the compiler.
2626
*/
2727
public class CompilerRegisterClass {
2828
private final String name;
29-
private final GeneratesRegisterFileName registerFile;
29+
private final RegisterResource registerFile;
3030
private final List<CompilerRegister> registers;
3131
private final Abi.Alignment alignment;
3232

3333
/**
3434
* Constructor.
3535
*/
36-
public CompilerRegisterClass(GeneratesRegisterFileName registerFile,
36+
public CompilerRegisterClass(RegisterResource registerFile,
3737
List<CompilerRegister> registers,
3838
Abi.Alignment alignment) {
3939
ViamError.ensure(registerFile.isRegisterFile(), "must be register file");
@@ -55,7 +55,7 @@ public Abi.Alignment alignment() {
5555
return alignment;
5656
}
5757

58-
public GeneratesRegisterFileName registerFile() {
58+
public RegisterResource registerFile() {
5959
return registerFile;
6060
}
6161
}

‎vadl/main/vadl/gcb/valuetypes/CompilerRegisterUtils.java‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
// SPDX-FileCopyrightText : © 2026 TU Wien <vadl@tuwien.ac.at>
2+
// SPDX-License-Identifier: GPL-3.0-or-later
3+
//
4+
// This program is free software: you can redistribute it and/or modify
5+
// it under the terms of the GNU General Public License as published by
6+
// the Free Software Foundation, either version 3 of the License, or
7+
// (at your option) any later version.
8+
//
9+
// This program is distributed in the hope that it will be useful,
10+
// but WITHOUT ANY WARRANTY; without even the implied warranty of
11+
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12+
// GNU General Public License for more details.
13+
//
14+
// You should have received a copy of the GNU General Public License
15+
// along with this program. If not, see <https://www.gnu.org/licenses/>.
16+
17+
package vadl.gcb.valuetypes;
18+
19+
import java.util.List;
20+
import java.util.Optional;
21+
import vadl.viam.Constant;
22+
import vadl.viam.RegisterResource;
23+
import vadl.viam.ViamError;
24+
25+
/**
26+
* Utility methods for compiler-facing register names and register-file conventions.
27+
*/
28+
public final class CompilerRegisterUtils {
29+
30+
private CompilerRegisterUtils() {
31+
}
32+
33+
/**
34+
* Generates the compiler register name for an indexed register-file entry.
35+
*/
36+
public static String indexedRegisterName(RegisterResource registerFile, int index) {
37+
ViamError.ensure(registerFile.isRegisterFile(), "must be registerFile");
38+
return registerFile.identifier().simpleName() + index;
39+
}
40+
41+
/**
42+
* Returns the index tuple of a zero register if the register file defines one.
43+
*/
44+
public static Optional<List<Constant.Value>> zeroRegister(RegisterResource registerFile) {
45+
return registerFile.constraints()
46+
.stream()
47+
.filter(c -> c.value().intValue() == 0)
48+
.map(RegisterResource.Constraint::indices)
49+
.findFirst();
50+
}
51+
}

‎vadl/main/vadl/gcb/valuetypes/IndexedCompilerRegister.java‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
1+
// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
22
// SPDX-License-Identifier: GPL-3.0-or-later
33
//
44
// This program is free software: you can redistribute it and/or modify
@@ -25,7 +25,7 @@
2525
import java.util.stream.IntStream;
2626
import vadl.utils.Pair;
2727
import vadl.viam.Abi;
28-
import vadl.viam.GeneratesRegisterFileName;
28+
import vadl.viam.RegisterResource;
2929

3030
/**
3131
* Like a {@link CompilerRegister} but contains the index in the register file.
@@ -44,7 +44,7 @@ private IndexedCompilerRegister(String regFileName,
4444
List<String> altNames,
4545
int dwarfNumber,
4646
boolean isArtificial,
47-
GeneratesRegisterFileName registerFile) {
47+
RegisterResource registerFile) {
4848
super(regFileName,
4949
asmName,
5050
altNames,
@@ -66,7 +66,7 @@ private IndexedCompilerRegister(String regFileName,
6666
* @param isArtificial registers in {@code registerFile} do not really exist.
6767
* @return a list of registers generated from the register file.
6868
*/
69-
public static List<CompilerRegister> fromRegisterFile(GeneratesRegisterFileName registerFile,
69+
public static List<CompilerRegister> fromRegisterFile(RegisterResource registerFile,
7070
Abi abi,
7171
int dwarfNumberOffset,
7272
boolean isArtificial) {
@@ -81,13 +81,13 @@ public static List<CompilerRegister> fromRegisterFile(GeneratesRegisterFileName
8181
.stream().map(Abi.RegisterAlias::value).toList();
8282
var alias = altNames
8383
.stream().findFirst()
84-
.orElse(registerFile.generateRegisterFileName(addr));
84+
.orElse(CompilerRegisterUtils.indexedRegisterName(registerFile, addr));
8585

8686
int dwarfNumber = dwarfNumberOffset + addr;
8787

8888
registers.add(
8989
new IndexedCompilerRegister(
90-
registerFile.generateRegisterFileName(addr),
90+
CompilerRegisterUtils.indexedRegisterName(registerFile, addr),
9191
addr,
9292
alias,
9393
altNames,

‎vadl/main/vadl/iss/passes/common/IssLoopUnrollPass.java‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -17,13 +17,12 @@
1717
package vadl.iss.passes.common;
1818

1919
import java.io.IOException;
20-
import javax.annotation.CheckForNull;
20+
import javax.annotation.Nullable;
2121
import vadl.configuration.IssConfiguration;
2222
import vadl.iss.passes.AbstractIssPass;
2323
import vadl.iss.passes.common.safeResourceRead.IssSafeResourceReadAnalysis;
2424
import vadl.pass.PassName;
2525
import vadl.pass.PassResults;
26-
import vadl.viam.Counter;
2726
import vadl.viam.Instruction;
2827
import vadl.viam.Specification;
2928
import vadl.viam.graph.control.ForallNode;
@@ -45,7 +44,7 @@ public PassName getName() {
4544
return PassName.of("ISS Loop Unroll Pass");
4645
}
4746

48-
@CheckForNull
47+
@Nullable
4948
@Override
5049
public Object execute(PassResults passResults, Specification viam) throws IOException {
5150
tcgInstrs(viam).forEach(i -> new LoopUnroller(i.behavior()).run());

‎vadl/main/vadl/iss/passes/common/IssRegisterAccessInfoRetrievalPass.java‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121

2222
import java.io.IOException;
2323
import java.util.Set;
24-
import javax.annotation.CheckForNull;
24+
import javax.annotation.Nullable;
2525
import vadl.configuration.IssConfiguration;
2626
import vadl.iss.passes.AbstractIssPass;
2727
import vadl.iss.passes.extensions.IssAccessorRegistry;
@@ -64,7 +64,7 @@ public PassName getName() {
6464
return PassName.of("ISS Register Access Info Retrieval");
6565
}
6666

67-
@CheckForNull
67+
@Nullable
6868
@Override
6969
public Object execute(PassResults passResults, Specification viam) throws IOException {
7070
var registry = new IssAccessorRegistry();
@@ -96,7 +96,7 @@ public Object execute(PassResults passResults, Specification viam) throws IOExce
9696
}
9797

9898
private void collectAccessorDescriptors(Graph behavior,
99-
IssAccessorRegistry registry) {
99+
IssAccessorRegistry registry) {
100100
behavior.getNodes(Set.of(ReadRegTensorNode.class, WriteRegTensorNode.class))
101101
.forEach((n) -> {
102102
if (n instanceof ReadRegTensorNode readRegTensorNode) {
@@ -148,7 +148,7 @@ private void collectAliasAccessorDescriptor(WriteRegTensorNode node,
148148
collectAliasAccessorDescriptor(writeNode.aliasResource(), RegInfo.AccessType.WRITE, registry);
149149
}
150150

151-
private void collectAliasAccessorDescriptor(@CheckForNull ArtificialResource alias,
151+
private void collectAliasAccessorDescriptor(@Nullable ArtificialResource alias,
152152
RegInfo.AccessType type,
153153
IssAccessorRegistry registry) {
154154
if (alias == null) {

‎vadl/main/vadl/iss/passes/common/IssTensorAssignmentToForallPass.java‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -21,7 +21,7 @@
2121
import static vadl.utils.StreamUtils.only;
2222

2323
import java.io.IOException;
24-
import javax.annotation.CheckForNull;
24+
import javax.annotation.Nullable;
2525
import vadl.configuration.IssConfiguration;
2626
import vadl.iss.passes.AbstractIssPass;
2727
import vadl.iss.passes.nodes.IssWriteRegNode;
@@ -78,7 +78,7 @@ public PassName getName() {
7878
return PassName.of("ISS Tensor Assignment To Forall Pass");
7979
}
8080

81-
@CheckForNull
81+
@Nullable
8282
@Override
8383
public Object execute(PassResults passResults, Specification viam) throws IOException {
8484
allInstrs(viam).forEach(instruction ->

‎vadl/main/vadl/lcb/passes/asm/AsmGrammarRuleGenerationPass.java‎

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,6 @@
2727
import java.util.Set;
2828
import java.util.stream.Collectors;
2929
import java.util.stream.Stream;
30-
import javax.annotation.CheckForNull;
3130
import javax.annotation.Nullable;
3231
import vadl.configuration.GeneralConfiguration;
3332
import vadl.error.DeferredDiagnosticStore;
@@ -95,7 +94,7 @@ public PassName getName() {
9594

9695
private int namingSequence = 0;
9796

98-
@CheckForNull
97+
@Nullable
9998
@Override
10099
public Object execute(PassResults passResults, Specification viam) throws IOException {
101100

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