ume: Add interpolation to rv64ume and custom template tags by arcane-quill · Pull Request #834 · OpenVADL/openvadl

arcane-quill · 2026-03-22T16:50:22Z

PR for issue #757 (and #761, #759)
interpolated hardcoded rv64ume files from linux-user
created UmeHardcodedRiscvDefinitionPass and UmeTemplateRenderingPass to add custom template tags (e.g. registers, exceptions..) with hardcoded values that later get filled in by the vadl file
added VIAM definition UserModeEmulation

flofriday · 2026-03-22T17:14:36Z

I think the branch of this PR isn't cleanly based on a fresh master, because it contains some of my commits that are already on master.

So let's rebase on master with (on your branch):

git fetch
git rebase origin/master

There might be some conflicts but if you execute these commands in IntelliJ you'll get some help resolving the conflicts in a nice UI. 😉

arcane-quill · 2026-03-22T18:15:43Z

I think the branch of this PR isn't cleanly based on a fresh master, because it contains some of my commits that are already on master.

So let's rebase on master with (on your branch):
git fetch
git rebase origin/master
There might be some conflicts but if you execute these commands in IntelliJ you'll get some help resolving the conflicts in a nice UI. 😉

I tried to rebase twice now but it doesnt seem to be fixed @flofriday

flofriday · 2026-03-22T18:26:53Z

Yeah sometimes rebasing still contains some weired artifacts, but I just tried it on my machine and it (mostly) worked. I'll send you a DM (on matrix), let's figure it out there.

Jozott00

Unfortunately the current state is too RISC-V specific and needs an overhaul. Please take a closer look at other VIAM definitions and how they are handled in the code emission.

arcane-quill · 2026-04-14T09:02:12Z

Unfortunately the current state is too RISC-V specific and needs an overhaul. Please take a closer look at other VIAM definitions and how they are handled in the code emission.

Thanks for the extensive review, I'm working on it now

#757

arcane-quill · 2026-05-09T10:55:48Z

hi @Jozott00 I resolved the stuff that was missing, hopefully we can get this merged now

and do u know why passorders keeps telling me there is a merge conflict despite none of it showing up locally, even after rebasing?

flofriday · 2026-05-09T14:54:44Z

and do u know why passorders keeps telling me there is a merge conflict despite none of it showing up locally, even after rebasing?

Mostly guesses here but I assume you are not syncing your local branches with the remote (GitHub).

For example

git rebase master

Isn't good enough to rebase with the newest changes from GitHub.
This is mostly because master on your machine isn't updated and is stuck on an old commit.

The long way is to do:

git checkout master
git pull # (download from the remote, and also update the current master branch to the newest version from the remote)
git checkout <your-branch>
git rebase master

But you can even shorten this a bit with

git fetch # Downloads the branches from the remote but does not update the local branches only the branches prefixed with origin will be updated, so master is still stuck on an old commit but origin/master is synced with the remote
git rebase origin/master

Jozott00

I think there are still some important things to change. Mostly, what and how the VIAM definition stores specification details.

I also think, that we should reduce the scope for the PR a bit, as signals are just a bit too much to start with. Therefore, let's completely remove all logic that is related to signals.

The UME generation requires quite a bit of information from the ABI definition and could share some constructs (like alias registers and special register references). Therefore, I will do a little ABI refactoring, so you can use RegisterRef instead of defining you own RegisterLocation as mentioned in a comment below.

EDIT: Also note, that this PR won't fully close #761 as there is still RISC-V specific stuff in the template files.

Jozott00 · 2026-05-11T07:58:14Z

+
+  private final Identifier excCauseVar;
+  private final RegisterTensor mainRegisterFile;
+  private final RegisterUtils.Register sysReg;


major: Using vadl.lcb.templateUtils.RegisterUtils.Register is the wrong abstraction

First, it is part of the LCB and should not be referenced by the vadl.viam package, second, it is a rendering utility, not a VIAM construct. It does not contain the original RegisterTensor and has exactly one index.

Instead, add a new class in the vadl.viam package:

public record RegisterLocation( RegisterResource resource, List<Constant.Value> indices, SourceLocation location ) implements WithLocation { }

And use it instead. This will model those register references/locations much better and remains generic.

Jozott00 · 2026-05-11T08:37:03Z

+  private final ExceptionDef breakpointExcName;
+  private final ExceptionDef illegalInstrExcName;
+  private final Identifier initialPc;
+  private final Identifier initialSp;


question: What is the initialPC and initialSp? Can you give me an example, cause I am confused how its value can be represented as Identifier.

From what I understand, this can be removed, as it can be synthesized later by the generator.

Jozott00 · 2026-05-11T08:38:27Z

+    if (args == null || args.isEmpty()) {
+      throw new IllegalArgumentException("args must not be null/empty");
+    }
+
+    if (excIds == null || excIds.isEmpty()) {
+      throw new IllegalArgumentException("excIds must not be null/empty");
+    }


minor: We use nullaway, so null checking of arguments that are not annoated with @Nullable isn't necessary.

Jozott00 · 2026-05-11T08:40:12Z

+    if (args == null || args.isEmpty()) {
+      throw new IllegalArgumentException("args must not be null/empty");
+    }
+
+    if (excIds == null || excIds.isEmpty()) {
+      throw new IllegalArgumentException("excIds must not be null/empty");
+    }


question: Is there a reason why you require the args to be non-empty? From the generator side, it shouldn't matter if there is any argument.

Jozott00 · 2026-05-11T08:42:51Z

+  private final Map<String, Integer> excIds;
+  private final Instruction syscallInstr;
+  private final ExceptionDef syscallException;
+  private final ExceptionDef breakpointExcName;


minor: Should be breakpointExc instead of breakpointExcName

(same below)

Jozott00 · 2026-05-11T10:03:04Z

+                [# th:if="${config.hasIcacheFlush}"]
+                if (env->[(${config.mainRegisterFile})][ [(${config.sysReg})] ] == TARGET_NR_[(${gen_arch_lower})]_flush_icache) {
                    /* no-op in QEMU; TB invalidation is automatic */
                    ret = 0;
                } else {
+                [/]
                    ret = do_syscall(env,
-                                     env->x[RV64UME_REG_A7],
-                                     env->x[RV64UME_REG_A0],
-                                     env->x[RV64UME_REG_A1],
-                                     env->x[RV64UME_REG_A2],
-                                     env->x[RV64UME_REG_A3],
-                                     env->x[RV64UME_REG_A4],
-                                     env->x[RV64UME_REG_A5],
-                                     0, 0);
+                                      env->[(${config.mainRegisterFile})][ [(${config.sysReg})] ],
+                                      [# th:each="arg : ${config.args}"]
+                                      env->[(${config.mainRegisterFile})][ [(${arg})] ],
+                                      [/]
+                                      0, 0);
+                [# th:if="${config.hasIcacheFlush}"]
                }
+                [/]


major: Just assume there is no icache-flush

Jozott00 · 2026-05-11T10:08:55Z

            exit(EXIT_FAILURE);
        }
+        [/]
+        [# th:if="${#strings.isEmpty(config.excCauseVar)}"]


major: This check is unnecessary, as exceptions in the ISS are always rendered as cause variables in the state.

Jozott00 · 2026-05-11T10:09:57Z

-    env->pc = regs->sepc;
-    env->x[RV64UME_REG_SP] = regs->sp;
+    env->[(${pc_reg.name_lower})] = regs->[(${config.initialPc})];
+    env->[(${config.mainRegisterFile})][ [(${config.spReg})] ] = regs->[(${config.initalSp})];


major: As we just hardcode the target_pt_regs anyway, just use regs->pc and regs->sp instead.

Jozott00 · 2026-05-11T10:12:14Z

minor: This whole table is currently hardcoded. However, I think we should do the dynamic interpolation in a separate PR.

Jozott00 · 2026-05-11T10:14:03Z

    if (inputPath != null && inputPath.getFileName().endsWith("rv64ume.vadl")) {
      order
+          .add(new UmeHardcodedRiscvDefinitionPass(config))
+          .add(new UmeTemplateRenderingPass(config, "cpu_loop.c"))


major: The cpu_loop.c is now emitted twice

…` interface (#948) This PR extracts most of the `Abi.RegisterRef` to `vadl.viam.RegisterRef`, so the datastructure can be reused in other definitions like the UME (#834). Additionally, it removes the `GeneratesRegisterFileName` which does not fit into the VIAM hierarchy and is already covered by the `RegisterResource` class.

arcane-quill requested a review from Jozott00 March 22, 2026 16:50

arcane-quill self-assigned this Mar 22, 2026

github-actions Bot added lcb This is LCB related frontend This is frontend related iss This is ISS related labels Mar 22, 2026

This was linked to issues Mar 22, 2026

ume: Define VIAM definitions for the UME VADL specification #757

Open

ume: Add pass to add a hardcoded UserModeEmulation VIAM definition #759

Open

ume: Parameterize QEMU templates and render them using the VIAM #761

Open

arcane-quill force-pushed the wip/ume-viam-def branch 2 times, most recently from ce9eaf4 to 0d64625 Compare March 22, 2026 19:08

arcane-quill changed the title ~~Wip/ume viam def~~ ume: Add interpolation to rv64ume and custom template tags Mar 23, 2026

arcane-quill force-pushed the wip/ume-viam-def branch from 2c3616b to 4d6afb8 Compare March 23, 2026 00:41

arcane-quill force-pushed the wip/ume-viam-def branch from 7d8ab0a to 4d6afb8 Compare April 4, 2026 02:10

arcane-quill added 7 commits April 4, 2026 04:15

ume: Add interpolation and specific pass for ume template tags #757

95f83c9

ume: Add specific tags for regs and exceptions #757

fd922a7

ume: Fix subdir in meson

4815745

ume: Add interpolation and specific pass for ume template tags #757

143ecf7

ume: Remove everything related to frontend #757

b1784d9

ume: Add ume definition #757

0ae6c13

ume: Add more values for interpolation #757

f54e597

arcane-quill force-pushed the wip/ume-viam-def branch from 4d6afb8 to f54e597 Compare April 4, 2026 02:18

arcane-quill force-pushed the wip/ume-viam-def branch 2 times, most recently from 4d6afb8 to f54e597 Compare April 12, 2026 01:50

arcane-quill added 4 commits April 12, 2026 16:47

ume: Add missing interpolation #757

96d71b7

ume: Fix checkstyle violations #757

f89dc79

ume: Fix more checkstyle violations #757

d81708a

ume: Remove duplicate line #757

e98f083

flofriday reviewed Apr 13, 2026

View reviewed changes

Comment thread vadl/main/vadl/ast/AstVisitor.java

arcane-quill added 2 commits April 13, 2026 23:26

ume: Revert frontend changes #757

22b98c4

ume: Revert atg file changes #757

07cd92a

Jozott00 requested changes Apr 14, 2026

View reviewed changes

arcane-quill added 5 commits April 14, 2026 21:34

ume: Use proper viam objects and fix templates #757

7c65266

ume: Revert misc file

4037a28

#757

ume: Fix signal.c reigster handling #757

6a745f6

Merge branch 'master' into wip/ume-viam-def

f3e4ac7

ume: Add ifs for causevar and signal to template #757

d2e54fb

arcane-quill requested a review from Jozott00 May 9, 2026 10:55

Jozott00 requested changes May 11, 2026

View reviewed changes

Jozott00 mentioned this pull request May 11, 2026

viam: Extract Abi.RegisterRef and remove GeneratesRegisterFileName interface #948

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