aarch32: Prepare for ISS#944
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BadGraphixD
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@flofriday Would you like to take a look at this, as it has some changes on the frontend? |
I don't see any changes in the frontend, was this maybe an old commit, or just a weird diff because #932 wasn't merged yet? |
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@flofriday oups, I wanted to write the comment under #932 😭 |
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@BadGraphixD please use the cosim approach, as it was done for PowerPC. Eventually, we will migrate RISC-V and AArch64 to it as well. |
- Add virt.vadl, which behaves like upstream QEMU
- Some VADL builtins are not fully supported by all passes or not implemented - All related aarch32 instrs are disabled - The multiple memory instructions take extremely long to compile - All related aarch32 mem instrs are disabled
- Instructions were in wrong byte order - Rewrote with current limitations (no mov, pc not working)
- Uses arm-linux-gnueabihf-* - Host interaction (HTIF, semihosting) not yet done
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@Jozott00 I do not exactly know what you mean by the cosim approach, but I assume that you mean that tests are executed in parallel with an upstream QEMU aarch32 and the results are compared. I am not convinced that this is a good idea. I suggest to use selfcontained tests for most of the test cases and use the cosim approach only when a selfcontained test is difficult to specify. |
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aarch32/virt.vadlaarch32_compiler.pyaarch32/aarch32.vadlNote: currently the simulation with our a32 target does not have working HTIF. This is because pc-relative addresses do not work yet, which will be fixed by #932 and #938