viam: Extract Abi.RegisterRef and remove GeneratesRegisterFileName interface

vadl/main/vadl/ast/ViamLowering.java

@@ -2002,11 +2002,11 @@ public Optional<vadl.viam.Definition> visit(
   }
 
   /**
-   * Maps a {@link SpecialPurposeRegisterDefinition} to a {@link Abi.RegisterRef}.
+   * Maps a {@link SpecialPurposeRegisterDefinition} to a {@link Abi.AbiRegister}.
    * It expects only one register in the {@link SpecialPurposeRegisterDefinition}. Otherwise,
    * it will throw an error.
    */
-  private Abi.RegisterRef mapSingleSpecialPurposeRegisterDef(
+  private Abi.AbiRegister mapSingleSpecialPurposeRegisterDef(
       Map<Identifier, Expr> aliasLookup,
       SpecialPurposeRegisterDefinition specialPurposeRegisterDef) {
     return specialPurposeRegisterDef.exprs.stream()
@@ -2015,9 +2015,9 @@ private Abi.RegisterRef mapSingleSpecialPurposeRegisterDef(
   }
 
   /**
-   * Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.RegisterRef}.
+   * Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.AbiRegister}.
    */
-  private List<Abi.RegisterRef> mapSpecialPurposeRegistersDef(
+  private List<Abi.AbiRegister> mapSpecialPurposeRegistersDef(
       Map<Identifier, Expr> aliasLookup,
       SpecialPurposeRegisterDefinition specialPurposeRegisterDef) {
     return specialPurposeRegisterDef.exprs.stream()
@@ -2026,12 +2026,12 @@ private List<Abi.RegisterRef> mapSpecialPurposeRegistersDef(
   }
 
   /**
-   * Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.RegisterRef}.
+   * Maps a {@link SpecialPurposeRegisterDefinition} to a list of {@link Abi.AbiRegister}.
    */
-  private List<List<Abi.RegisterRef>> mapSpecialPurposeRegistersDefs(
+  private List<List<Abi.AbiRegister>> mapSpecialPurposeRegistersDefs(
       Map<Identifier, Expr> aliasLookup,
       List<SpecialPurposeRegisterDefinition> specialPurposeRegisterDefs) {
-    List<List<Abi.RegisterRef>> result = new ArrayList<>();
+    List<List<Abi.AbiRegister>> result = new ArrayList<>();
 
     for (var def : specialPurposeRegisterDefs) {
       var iter = def.exprs.stream()
@@ -2044,7 +2044,7 @@ private List<List<Abi.RegisterRef>> mapSpecialPurposeRegistersDefs(
     return result;
   }
 
-  private Abi.RegisterRef getRegisterRefByAliasOrRegister(
+  private Abi.AbiRegister getRegisterRefByAliasOrRegister(
       Map<Identifier, Expr> aliasLookup,
       ExpandedSequenceCallExpr aliasOrRegister) {
     if (aliasOrRegister instanceof ExpandedAliasDefSequenceCallExpr registerCallExpr) {
@@ -2055,10 +2055,10 @@ private Abi.RegisterRef getRegisterRefByAliasOrRegister(
   }
 
   /**
-   * Maps the aliases {@code alias register zero = X(0)} to {@link Abi.RegisterRef} to be
+   * Maps the aliases {@code alias register zero = X(0)} to {@link Abi.AbiRegister} to be
    * used in {@link Abi}.
    */
-  private Abi.RegisterRef mapAliasToRegisterRef(
+  private Abi.AbiRegister mapAliasToRegisterRef(
       Map<Identifier, Expr> aliasLookup,
       Identifier identifier) {
     var expr = ensureNonNull(aliasLookup.get(identifier),
@@ -2067,12 +2067,12 @@ private Abi.RegisterRef mapAliasToRegisterRef(
     return mapToRegisterRef(expr);
   }
 
-  private Abi.RegisterRef mapToRegisterRef(Expr expr) {
+  private Abi.AbiRegister mapToRegisterRef(Expr expr) {
     var pair = getRegisterFile(expr);
     var registerFile = pair.left();
     var index = pair.right();
 
-    return new Abi.RegisterRef(registerFile, index, new Abi.Alignment(-1), expr.location());
+    return new Abi.AbiRegister(registerFile, index, new Abi.Alignment(-1), expr.location());
   }
 
   /**

vadl/main/vadl/gcb/passes/operands/model/GcbInstructionRegisterFileOperand.java

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
+// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
 // SPDX-License-Identifier: GPL-3.0-or-later
 //
 // This program is free software: you can redistribute it and/or modify
@@ -19,8 +19,7 @@
 import java.util.List;
 import vadl.gcb.passes.operands.ReferencesFormatField;
 import vadl.viam.Format;
-import vadl.viam.GeneratesRegisterFileName;
-import vadl.viam.RegisterTensor;
+import vadl.viam.RegisterResource;
 import vadl.viam.graph.dependency.FieldRefNode;
 import vadl.viam.graph.dependency.ReadArtificialResNode;
 import vadl.viam.graph.dependency.ReadRegTensorNode;
@@ -33,7 +32,7 @@
 public class GcbInstructionRegisterFileOperand
     extends GcbDefaultInstructionOperand
     implements ReferencesFormatField {
-  private final GeneratesRegisterFileName registerFile;
+  private final RegisterResource registerFile;
   private final Format.Field formatField;
 
   /**
@@ -79,7 +78,7 @@ public GcbInstructionRegisterFileOperand(WriteArtificialResNode node, Format.Fie
         .ensure(registerFile.isRegisterFile(), "must be registerfile");
   }
 
-  public GeneratesRegisterFileName registerFile() {
+  public RegisterResource registerFile() {
     return registerFile;
   }
 

vadl/main/vadl/gcb/valuetypes/CompilerRegister.java

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
+// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
 // SPDX-License-Identifier: GPL-3.0-or-later
 //
 // This program is free software: you can redistribute it and/or modify
@@ -19,7 +19,7 @@
 import java.util.ArrayList;
 import java.util.List;
 import java.util.Objects;
-import vadl.viam.GeneratesRegisterFileName;
+import vadl.viam.RegisterResource;
 
 /**
  * Extends the register with information which a compiler requires.
@@ -94,7 +94,7 @@ public int hashCode() {
   protected final List<String> altNames;
   protected final List<CompilerRegister> subRegs;
   protected final List<SubRegIndex> subRegIndices;
-  protected final GeneratesRegisterFileName registerFile;
+  protected final RegisterResource registerFile;
 
   protected final int dwarfNumber;
   protected final int hwEncodingValue;
@@ -109,7 +109,7 @@ public CompilerRegister(String name,
                           int dwarfNumber,
                           int hwEncodingValue,
                           boolean isArtificial,
-                          GeneratesRegisterFileName registerFile) {
+                          RegisterResource registerFile) {
     this.name = name;
     this.asmName = asmName;
     this.altNames = altNames;
@@ -153,7 +153,7 @@ public List<SubRegIndex> subRegIndices() {
     return subRegIndices;
   }
 
-  public GeneratesRegisterFileName registerFile() {
+  public RegisterResource registerFile() {
     return registerFile;
   }
 

vadl/main/vadl/gcb/valuetypes/CompilerRegisterClass.java

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
+// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
 // SPDX-License-Identifier: GPL-3.0-or-later
 //
 // This program is free software: you can redistribute it and/or modify
@@ -18,22 +18,22 @@
 
 import java.util.List;
 import vadl.viam.Abi;
-import vadl.viam.GeneratesRegisterFileName;
+import vadl.viam.RegisterResource;
 import vadl.viam.ViamError;
 
 /**
  * Extends the concept of the register class for the compiler.
  */
 public class CompilerRegisterClass {
   private final String name;
-  private final GeneratesRegisterFileName registerFile;
+  private final RegisterResource registerFile;
   private final List<CompilerRegister> registers;
   private final Abi.Alignment alignment;
 
   /**
    * Constructor.
    */
-  public CompilerRegisterClass(GeneratesRegisterFileName registerFile,
+  public CompilerRegisterClass(RegisterResource registerFile,
                                List<CompilerRegister> registers,
                                Abi.Alignment alignment) {
     ViamError.ensure(registerFile.isRegisterFile(), "must be register file");
@@ -55,7 +55,7 @@ public Abi.Alignment alignment() {
     return alignment;
   }
 
-  public GeneratesRegisterFileName registerFile() {
+  public RegisterResource registerFile() {
     return registerFile;
   }
 }

vadl/main/vadl/gcb/valuetypes/CompilerRegisterUtils.java

@@ -0,0 +1,51 @@
+// SPDX-FileCopyrightText : © 2026 TU Wien <vadl@tuwien.ac.at>
+// SPDX-License-Identifier: GPL-3.0-or-later
+//
+// This program is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <https://www.gnu.org/licenses/>.
+
+package vadl.gcb.valuetypes;
+
+import java.util.List;
+import java.util.Optional;
+import vadl.viam.Constant;
+import vadl.viam.RegisterResource;
+import vadl.viam.ViamError;
+
+/**
+ * Utility methods for compiler-facing register names and register-file conventions.
+ */
+public final class CompilerRegisterUtils {
+
+  private CompilerRegisterUtils() {
+  }
+
+  /**
+   * Generates the compiler register name for an indexed register-file entry.
+   */
+  public static String indexedRegisterName(RegisterResource registerFile, int index) {
+    ViamError.ensure(registerFile.isRegisterFile(), "must be registerFile");
+    return registerFile.identifier().simpleName() + index;
+  }
+
+  /**
+   * Returns the index tuple of a zero register if the register file defines one.
+   */
+  public static Optional<List<Constant.Value>> zeroRegister(RegisterResource registerFile) {
+    return registerFile.constraints()
+        .stream()
+        .filter(c -> c.value().intValue() == 0)
+        .map(RegisterResource.Constraint::indices)
+        .findFirst();
+  }
+}

vadl/main/vadl/gcb/valuetypes/IndexedCompilerRegister.java

@@ -1,4 +1,4 @@
-// SPDX-FileCopyrightText : © 2025 TU Wien <vadl@tuwien.ac.at>
+// SPDX-FileCopyrightText : © 2025-2026 TU Wien <vadl@tuwien.ac.at>
 // SPDX-License-Identifier: GPL-3.0-or-later
 //
 // This program is free software: you can redistribute it and/or modify
@@ -25,7 +25,7 @@
 import java.util.stream.IntStream;
 import vadl.utils.Pair;
 import vadl.viam.Abi;
-import vadl.viam.GeneratesRegisterFileName;
+import vadl.viam.RegisterResource;
 
 /**
  * Like a {@link CompilerRegister} but contains the index in the register file.
@@ -44,7 +44,7 @@ private IndexedCompilerRegister(String regFileName,
                                   List<String> altNames,
                                   int dwarfNumber,
                                   boolean isArtificial,
-                                  GeneratesRegisterFileName registerFile) {
+                                  RegisterResource registerFile) {
     super(regFileName,
         asmName,
         altNames,
@@ -66,7 +66,7 @@ private IndexedCompilerRegister(String regFileName,
    * @param isArtificial      registers in {@code registerFile} do not really exist.
    * @return a list of registers generated from the register file.
    */
-  public static List<CompilerRegister> fromRegisterFile(GeneratesRegisterFileName registerFile,
+  public static List<CompilerRegister> fromRegisterFile(RegisterResource registerFile,
                                                         Abi abi,
                                                         int dwarfNumberOffset,
                                                         boolean isArtificial) {
@@ -81,13 +81,13 @@ public static List<CompilerRegister> fromRegisterFile(GeneratesRegisterFileName
               .stream().map(Abi.RegisterAlias::value).toList();
       var alias = altNames
           .stream().findFirst()
-          .orElse(registerFile.generateRegisterFileName(addr));
+          .orElse(CompilerRegisterUtils.indexedRegisterName(registerFile, addr));
 
       int dwarfNumber = dwarfNumberOffset + addr;
 
       registers.add(
           new IndexedCompilerRegister(
-              registerFile.generateRegisterFileName(addr),
+              CompilerRegisterUtils.indexedRegisterName(registerFile, addr),
               addr,
               alias,
               altNames,

vadl/main/vadl/iss/passes/common/IssLoopUnrollPass.java

@@ -17,13 +17,12 @@
 package vadl.iss.passes.common;
 
 import java.io.IOException;
-import javax.annotation.CheckForNull;
+import javax.annotation.Nullable;
 import vadl.configuration.IssConfiguration;
 import vadl.iss.passes.AbstractIssPass;
 import vadl.iss.passes.common.safeResourceRead.IssSafeResourceReadAnalysis;
 import vadl.pass.PassName;
 import vadl.pass.PassResults;
-import vadl.viam.Counter;
 import vadl.viam.Instruction;
 import vadl.viam.Specification;
 import vadl.viam.graph.control.ForallNode;
@@ -45,7 +44,7 @@ public PassName getName() {
     return PassName.of("ISS Loop Unroll Pass");
   }
 
-  @CheckForNull
+  @Nullable
   @Override
   public Object execute(PassResults passResults, Specification viam) throws IOException {
     tcgInstrs(viam).forEach(i -> new LoopUnroller(i.behavior()).run());

vadl/main/vadl/iss/passes/common/IssRegisterAccessInfoRetrievalPass.java

@@ -21,7 +21,7 @@
 
 import java.io.IOException;
 import java.util.Set;
-import javax.annotation.CheckForNull;
+import javax.annotation.Nullable;
 import vadl.configuration.IssConfiguration;
 import vadl.iss.passes.AbstractIssPass;
 import vadl.iss.passes.extensions.IssAccessorRegistry;
@@ -64,7 +64,7 @@ public PassName getName() {
     return PassName.of("ISS Register Access Info Retrieval");
   }
 
-  @CheckForNull
+  @Nullable
   @Override
   public Object execute(PassResults passResults, Specification viam) throws IOException {
     var registry = new IssAccessorRegistry();
@@ -96,7 +96,7 @@ public Object execute(PassResults passResults, Specification viam) throws IOExce
   }
 
   private void collectAccessorDescriptors(Graph behavior,
-                                         IssAccessorRegistry registry) {
+                                          IssAccessorRegistry registry) {
     behavior.getNodes(Set.of(ReadRegTensorNode.class, WriteRegTensorNode.class))
         .forEach((n) -> {
           if (n instanceof ReadRegTensorNode readRegTensorNode) {
@@ -148,7 +148,7 @@ private void collectAliasAccessorDescriptor(WriteRegTensorNode node,
     collectAliasAccessorDescriptor(writeNode.aliasResource(), RegInfo.AccessType.WRITE, registry);
   }
 
-  private void collectAliasAccessorDescriptor(@CheckForNull ArtificialResource alias,
+  private void collectAliasAccessorDescriptor(@Nullable ArtificialResource alias,
                                               RegInfo.AccessType type,
                                               IssAccessorRegistry registry) {
     if (alias == null) {

vadl/main/vadl/iss/passes/common/IssTensorAssignmentToForallPass.java

@@ -21,7 +21,7 @@
 import static vadl.utils.StreamUtils.only;
 
 import java.io.IOException;
-import javax.annotation.CheckForNull;
+import javax.annotation.Nullable;
 import vadl.configuration.IssConfiguration;
 import vadl.iss.passes.AbstractIssPass;
 import vadl.iss.passes.nodes.IssWriteRegNode;
@@ -78,7 +78,7 @@ public PassName getName() {
     return PassName.of("ISS Tensor Assignment To Forall Pass");
   }
 
-  @CheckForNull
+  @Nullable
   @Override
   public Object execute(PassResults passResults, Specification viam) throws IOException {
     allInstrs(viam).forEach(instruction ->

vadl/main/vadl/lcb/passes/asm/AsmGrammarRuleGenerationPass.java

@@ -27,7 +27,6 @@
 import java.util.Set;
 import java.util.stream.Collectors;
 import java.util.stream.Stream;
-import javax.annotation.CheckForNull;
 import javax.annotation.Nullable;
 import vadl.configuration.GeneralConfiguration;
 import vadl.error.DeferredDiagnosticStore;
@@ -95,7 +94,7 @@ public PassName getName() {
 
   private int namingSequence = 0;
 
-  @CheckForNull
+  @Nullable
   @Override
   public Object execute(PassResults passResults, Specification viam) throws IOException {