Add multi-port SRAM generation support

[Copilot]

Exposes OpenRAM's existing multi-port capability through configuration parameters, enabling generation of single-port and dual-port SRAMs.

Changes

Configuration Interface

• Added num_rw_ports, num_r_ports, num_w_ports parameters to config files
• Validates total port count (1-2 ports supported by OpenRAM)
• Updated SRAM naming: sram_1rw0r0w_16x32_1v (single-port) vs sram_1rw1r0w_16x32_1v (dual-port)

Generator Integration

• Passes port configuration to globals.OPTS before SRAM initialization
• Enhanced output display with port configuration details
• Error handling for invalid port combinations

Documentation

• Port type descriptions (RW, R, W) and common configurations
• Usage examples for FIFO buffers (1 RW + 1 R) and video buffers (1 W + 1 R)

Example Usage

# config.py - Dual-port SRAM for FIFO
word_size = 32
num_words = 256
num_banks = 1
num_rw_ports = 1  # Read-write port
num_r_ports = 1   # Read-only port
num_w_ports = 0

Generates Verilog with dual interfaces:

module sram_1rw1r0w_32x256_1v(
  // Port 0: RW
  input clk0, csb0, web0, addr0[4:0], din0[31:0],
  output dout0[31:0],
  // Port 1: R
  input clk1, csb1, addr1[4:0],
  output dout1[31:0]
);

Default configuration remains single-port (backward compatible).

Original prompt

---

This section details on the original issue you should resolve

<issue_title>Adding multi port srams</issue_title>
<issue_description>Need to implement multi port sram generation</issue_description>

Comments on the Issue (you are @copilot in this section)

• Fixes Adding multi port srams #2

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