Merge pull request The-OpenROAD-Project#1980 from Pinata-Consulting/mock-sram-example

sram: add example of mocking SRAMs to asap7/riscv32i

Author: maliberty

flow/designs/asap7/mock-array/README.md

@@ -44,55 +44,3 @@ to be fitted into a higher level module where CTS creates a balanced clock tree
 that takes the mock-array and mock-array Element clock insertion
 latency into account. This means that the optimization target
 for mock-array and mock-array Element have zero skew.
-
-constraint.sdc shared between mock-array and mock-array/Element
----------------------------------------------------------------
-
-From the following observations, all else follows: the only thing
-that can fail timing closure, is a register to register path. All
-other constraints give the flow an optimization target. Failure
-to meet the timing constraint of an optimization target constraint
-is not a timing closure failure.
-
-Note that ORFS regression checks does not have the ability to distinguish
-between timing closure failures(register to register paths) and
-optimization constraints violations. Timing violations for optimization constraints
-in mock-array Element, such as maximum transit time for a combinational path
-through mock-array Element, may or may not cause timing
-violations later on higher up in mock-array on register to register paths.
-
-For the Element constraint.sdc, the only register to register path
-are within the Element and no lower level macros are
-involved. Register to register paths within Element have to be checked
-at the Element level as they are invisible higher up in mock-array.
-
-As for the remaining optimization constraints for Element, they
-should be for combinational through paths and from input pins to register and
-from register to output pins.
-
-The constraints.sdc file is designed such that the clock latency & tree
-can be ignored as far constraints go;
-it is not part of the optimization constraints. The clock tree latency
-is accounted for in register to register paths within.
-
-The timing closure for the register to register paths between
-Element macros is checked at the mock-array level.
-
-With this in mind, the constraints.sdc file for the Element becomes
-quite general and simple. set_max_delay is used exclusively for
-optimization constraints and the clock period is used to check timing
-closure for register to register paths.
-
-set_input/output_delay are not used and can't really be used
-with the requirement that the constraint.sdc file should be articulated
-without making assumptions on the clock tree insertion latency. The time specified
-for set_input/output_delay is relative to the clock insertion point, i.e.
-the time at the clock pin for the macro, which makes it impossible to articulate
-the number that is passed in to set_input/output_delay without taking
-clock network insertion latency into account.
-
-Since set_input_delay is not used and set_max_delay is used instead, then
-no hold cells are inserted, which is what is desired here.
-
-Beware of [path segmentation](https://docs.xilinx.com/r/2020.2-English/ug906-vivado-design-analysis/TIMING-13-Timing-Paths-Ignored-Due-to-Path-Segmentation), which
-can occur with OpenSTA.

flow/designs/asap7/mock-array/constraints.sdc

@@ -1,32 +1,5 @@
-# see README.md
-set sdc_version 2.0
-
 set clk_name clock
 set clk_port_name clock
 set clk_period 250
 
-set clk_port [get_ports $clk_port_name]
-create_clock -period $clk_period -waveform [list 0 [expr $clk_period / 2]] -name $clk_name $clk_port
-set_clock_uncertainty -setup 20.0 [get_clocks $clk_name]
-set_clock_uncertainty -hold  20.0 [get_clocks $clk_name]
-
-set_max_transition 250 [current_design]
-set_max_transition 100 -clock_path [all_clocks]
-
-set non_clk_inputs  [lsearch -inline -all -not -exact [all_inputs] $clk_port]
-set all_register_outputs [get_pins -of_objects [all_registers] -filter {direction == output}]
-
-# Optimization targets
-set max_delay 80
-set_max_delay $max_delay -from $non_clk_inputs -to [all_registers]
-set_max_delay $max_delay -from $all_register_outputs -to [all_outputs]
-set_max_delay $max_delay -from $non_clk_inputs -to [all_outputs]
-
-# Set driving cell and load capacitance explicitly to ensure timing results are sufficiently pessimistic
-set_driving_cell [all_inputs] -lib_cell BUFx4_ASAP7_75t_R
-
-# Assuming the load on each output is a BUFx2_ASAP7_75t_R, we pessimistically use 3 times the highest input
-#  pin capacitance for this cell, which is 0.577042.
-#  See platforms/asap7/lib/asap7sc7p5t_INVBUF_RVT_FF_nldm_220122.lib.gz, line 1223.
-#set_load -pin_load 2.731126 [all_outputs]
-set_load -pin_load 10 [all_outputs]
+source $env(PLATFORM_DIR)/constraints.sdc

flow/designs/asap7/riscv32i-mock-sram/README.md

@@ -0,0 +1,29 @@
+mock sram example
+-----------------
+
+To mock an SRAM means to take the behavioral Verilog and create a
+scaled down version while still using all the input/outputs. This can
+be useful when no fake sram is available from the PDK or the existing
+fake srams are not a great match for the SRAMs used in the design.
+
+Typically this is done by reducing the number of rows, such as from 128
+to 4 in this case. The unused address bits are xor'ed together the
+unused address bits so that all input/outputs of the module are still in
+use.
+
+This gives us a mock .lef and .lib file.
+
+Mocking for non-SRAM purposes
+-----------------------------
+
+The mocking technique illustrated here can also be used for other cases
+where hard macros are not immediately available or suitable, indeed it
+can be used for entire modules that are not currently fleshed out
+during early architectural exploration stages:
+
+- register file, of pivotal importance for CPU performance and the design
+  thereof is critical for performance. A register file's defining feature
+  is that it has a very large number of ports and relatively few rows, so
+  fake SRAMs are generally not suitable to model a register file.
+- multipliers, barrel shifters and other highly PDK specific and optimized
+  macros.

flow/designs/asap7/riscv32i-mock-sram/config.mk

@@ -0,0 +1,4 @@
+export DESIGN_NICKNAME = riscv32i-mock-sram
+export BLOCKS=fakeram7_256x32
+
+include designs/asap7/riscv32i/config.mk

flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/config.mk

@@ -0,0 +1,13 @@
+export DESIGN_NICKNAME = riscv32i-mock-sram_fakeram7_256x32
+export DESIGN_NAME = fakeram7_256x32
+export PLATFORM    = asap7
+
+export VERILOG_FILES = ./designs/asap7/riscv32i-mock-sram/fakeram7_256x32/*.v
+export SDC_FILE      = ./designs/$(PLATFORM)/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc
+
+export CORE_UTILIZATION = 50
+export CORE_ASPECT_RATIO = 8
+export PLACE_DENSITY = 0.80
+export MAX_ROUTING_LAYER = M4
+
+export PLACE_PINS_ARGS = -exclude left:* -exclude bottom:* -exclude top:* -min_distance 6 -min_distance_in_tracks

flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/constraints.sdc

@@ -0,0 +1,5 @@
+set clk_name clk
+set clk_port_name clk
+set clk_period 1660
+
+source $env(PLATFORM_DIR)/constraints.sdc