Add Local APIC and Per-CPU data structures for SMP support

- Implemented LAPIC driver in `apic.rs` for initialization, EOI, IPI, and timer setup.
- Added functions for LAPIC base probing, BSP/AP initialization, and timer calibration.
- Introduced per-CPU data structure in `per_cpu.rs` to manage CPU-specific information.
- Established ABI for per-CPU fields to ensure compatibility with assembly code.
- Included functions for accessing and managing per-CPU data, including CPU count detection.

Author: T. Andrew Davis

bootloader/src/uefi_allocator.rs

@@ -220,7 +220,7 @@ unsafe fn try_init_overflow() -> Option<OverflowState> {
         return None;
     }
 
-    let registry = morpheus_hwinit::global_registry_mut();
+    let mut registry = morpheus_hwinit::global_registry_mut();
     let pages = (OVERFLOW_GROW_CHUNK as u64).div_ceil(morpheus_hwinit::PAGE_SIZE);
 
     match registry.allocate_pages(
@@ -269,7 +269,7 @@ unsafe fn try_grow_overflow(state: &mut OverflowState, _needed: usize) -> bool {
     // linked_list_allocator::Heap::extend() can merge them into the free list.
     let extend_addr = state.base + state.size as u64;
 
-    let registry = morpheus_hwinit::global_registry_mut();
+    let mut registry = morpheus_hwinit::global_registry_mut();
     match registry.allocate_pages(
         morpheus_hwinit::AllocateType::Address(extend_addr),
         morpheus_hwinit::MemoryType::AllocatedHeap,

hwinit/Cargo.toml

@@ -5,7 +5,8 @@ edition.workspace = true
 description = "Hardware initialization layer for MorpheusX"
 
 [features]
-default = []
+default = ["smp"]
+smp = []
 
 [dependencies]
 # Heap allocator backing

hwinit/asm/cpu/ap_trampoline.s

@@ -0,0 +1,143 @@
+; ═══════════════════════════════════════════════════════════════════════════
+; ap_trampoline.s — AP bootstrap: real mode → protected → long mode
+;
+; Assembled as flat binary (nasm -f bin).  The BSP copies this blob to
+; physical address 0x8000 and sends SIPI with vector = 0x08.
+;
+; At SIPI delivery the AP starts executing at CS:IP = 0x0800:0x0000
+; in 16-bit real mode.  We need to get to 64-bit long mode and jump
+; into ap_rust_entry(core_idx, lapic_id).
+;
+; DATA AREA at offset 0xF00 within this page is filled by ap_boot.rs
+; before each AP is woken.  Layout must match the TD_* constants there.
+;
+; ═══════════════════════════════════════════════════════════════════════════
+
+bits 16
+org 0x8000          ; physical load address
+
+; ───────────────────────────────────────────────────────────────────────────
+; 16-bit real mode entry
+; ───────────────────────────────────────────────────────────────────────────
+ap_start:
+    cli
+    cld
+
+    ; cs = 0x0800 from SIPI, set ds/es/ss to match
+    mov     ax, cs
+    mov     ds, ax
+    mov     es, ax
+    mov     ss, ax
+    xor     sp, sp          ; stack at top of segment (wraps to 0xFFFF)
+
+    ; ── load the GDT pointer from the data area ──────────────────────────
+    ; data area is at this_page + 0xF00.  Our segment base = 0x8000.
+    ; so offset within segment = 0xF00 + 0x20 (TD_GDT_PTR within data area)
+    lgdt    [0xF20]         ; 0x8000 + 0xF20 in linear addressing = offset 0xF20 from segment base
+
+    ; ── enter protected mode ──────────────────────────────────────────────
+    mov     eax, cr0
+    or      eax, 1          ; PE bit
+    mov     cr0, eax
+
+    ; far jump to 32-bit protected mode code
+    ; selector 0x08 = index 1 = kernel code descriptor in BSP's GDT
+    jmp     dword 0x08:ap_pm32
+
+; ───────────────────────────────────────────────────────────────────────────
+; 32-bit protected mode
+; ───────────────────────────────────────────────────────────────────────────
+bits 32
+ap_pm32:
+    ; load data segments with kernel data selector (0x10)
+    mov     ax, 0x10
+    mov     ds, ax
+    mov     es, ax
+    mov     fs, ax
+    mov     gs, ax
+    mov     ss, ax
+
+    ; ── enable PAE (required for long mode) ───────────────────────────────
+    mov     eax, cr4
+    or      eax, (1 << 5)   ; CR4.PAE
+    mov     cr4, eax
+
+    ; ── load kernel CR3 from data area ────────────────────────────────────
+    mov     eax, dword [0x8F00]     ; TD_CR3 low 32 bits (phys address < 4GB)
+    mov     cr3, eax
+
+    ; ── enable long mode via IA32_EFER.LME ────────────────────────────────
+    mov     ecx, 0xC0000080         ; IA32_EFER
+    rdmsr
+    or      eax, (1 << 8)           ; LME = bit 8
+    wrmsr
+
+    ; ── enable paging → activates long mode ───────────────────────────────
+    mov     eax, cr0
+    or      eax, (1 << 31)          ; CR0.PG
+    mov     cr0, eax
+
+    ; far jump to 64-bit long mode code
+    jmp     dword 0x08:ap_lm64
+
+; ───────────────────────────────────────────────────────────────────────────
+; 64-bit long mode
+; ───────────────────────────────────────────────────────────────────────────
+bits 64
+ap_lm64:
+    ; reload data segments for 64-bit mode
+    mov     ax, 0x10
+    mov     ds, ax
+    mov     es, ax
+    mov     fs, ax
+    mov     ss, ax
+    ; intentionally skip gs — Rust will set GS base via MSR
+
+    ; ── load the per-AP stack from data area ──────────────────────────────
+    mov     rsp, qword [0x8F10]     ; TD_STACK
+
+    ; ── read core_idx and lapic_id from data area ─────────────────────────
+    mov     ecx, dword [0x8F18]     ; TD_CORE_IDX → RCX (arg1, MS x64)
+    mov     edx, dword [0x8F1C]     ; TD_LAPIC_ID → RDX (arg2, MS x64)
+
+    ; ── jump to Rust entry point ──────────────────────────────────────────
+    mov     rax, qword [0x8F08]     ; TD_ENTRY64
+    jmp     rax                     ; ap_rust_entry(core_idx, lapic_id) — never returns
+
+; ───────────────────────────────────────────────────────────────────────────
+; Pad to keep total code well under 0xF00 (data area starts there)
+; ───────────────────────────────────────────────────────────────────────────
+times (0xF00 - ($ - $$)) db 0
+
+; ───────────────────────────────────────────────────────────────────────────
+; DATA AREA (offset 0xF00 within the 4K page)
+;
+; Filled by ap_boot.rs before each SIPI.  Layout must match TD_* constants.
+; ───────────────────────────────────────────────────────────────────────────
+; 0xF00: CR3 (8 bytes)
+dd 0, 0
+
+; 0xF08: ENTRY64 — 64-bit Rust entry point address (8 bytes)
+dd 0, 0
+
+; 0xF10: STACK — per-AP kernel stack top (8 bytes)
+dd 0, 0
+
+; 0xF18: CORE_IDX (4 bytes)
+dd 0
+
+; 0xF1C: LAPIC_ID (4 bytes)
+dd 0
+
+; 0xF20: GDT_PTR — 10 bytes (limit:2 + base:8), copied from BSP's SGDT
+dw 0            ; limit
+dd 0, 0         ; base (8 bytes, split as dd to avoid `dq` in 16-bit section)
+
+; 0xF2A: padding to 0xF30
+times (0xF30 - (0xF20 + 10)) db 0
+
+; 0xF30: READY flag (4 bytes) — AP sets to 1 when Rust entry is reached
+dd 0
+
+; pad rest of page
+times (0x1000 - ($ - $$)) db 0

hwinit/asm/cpu/context_switch.s

@@ -1,15 +1,31 @@
 ; ═══════════════════════════════════════════════════════════════════════════
-; context_switch.s — Timer ISR + preemptive context switch
+; context_switch.s — Timer ISR + preemptive context switch (SMP-safe)
 ;
 ; ABI:  Microsoft x64 (RCX, RDX, R8, R9, xmm0-3, shadow space)
 ; Format: PE/COFF (win64)
 ;
 ; Exports:
-;   irq_timer_isr   — installed in IDT vector 0x20 (PIT IRQ 0).
+;   irq_timer_isr   — installed in IDT vector 0x20 (LAPIC timer).
 ;                     Saves the current CpuContext + FPU/SSE state,
 ;                     calls scheduler_tick() (Rust, MS x64), restores
 ;                     the next process's state, and resumes via iretq.
 ;
+; Per-CPU data is accessed via GS segment register.  The kernel sets
+; IA32_GS_BASE to point at the PerCpu struct for each core.  SWAPGS
+; is used on transitions between ring 3 and ring 0.
+;
+; PerCpu field offsets (must match per_cpu.rs):
+;   gs:[0x00]  self_ptr
+;   gs:[0x08]  cpu_id (u32)
+;   gs:[0x0C]  current_pid (u32)
+;   gs:[0x10]  next_cr3 (u64)
+;   gs:[0x18]  current_fpu_ptr (u64)
+;   gs:[0x20]  kernel_syscall_rsp (u64)
+;   gs:[0x28]  user_rsp_scratch (u64)
+;   gs:[0x30]  tss_ptr (u64)
+;   gs:[0x38]  lapic_base (u64)
+;   gs:[0x40]  tick_count (u64)
+;
 ; CpuContext field layout (must match hwinit/src/process/context.rs):
 ;   0x00  rax
 ;   0x08  rbx
@@ -33,58 +49,37 @@
 ;   0x98  ss
 ;   Total: 0xA0 (160) bytes
 ;
-; FPU/SSE state (FpuState):
-;   Saved/restored via FXSAVE/FXRSTOR through `current_fpu_ptr`.
-;   512 bytes, 16-byte aligned, stored per-process in PROCESS_TABLE.
-;   The pointer is updated by scheduler_tick() when it picks the next process.
-;
 ; iretq frame layout pushed by CPU at ISR entry (all 8-byte slots):
-;   [rsp+0x00]  RIP      (return address in interrupted code)
-;   [rsp+0x08]  CS       (code segment selector, zero-extended)
+;   [rsp+0x00]  RIP
+;   [rsp+0x08]  CS
 ;   [rsp+0x10]  RFLAGS
-;   [rsp+0x18]  RSP      (stack pointer before interrupt)
-;   [rsp+0x20]  SS       (stack segment selector, zero-extended)
+;   [rsp+0x18]  RSP
+;   [rsp+0x20]  SS
 ;   Size: 0x28 (40) bytes
 ; ═══════════════════════════════════════════════════════════════════════════
 
 bits 64
 default rel
 
-; ── Data ──────────────────────────────────────────────────────────────────
-section .data
-
-align 8
-global next_cr3
-next_cr3: dq 0
-
-; Pointer to the FpuState of the currently-running process.
-; Written by scheduler_tick() on every switch; read by this ISR for
-; FXSAVE (outgoing) and FXRSTOR (incoming).  NULL during early boot
-; before the scheduler is initialized — guarded by a null check.
-align 16
-global current_fpu_ptr
-current_fpu_ptr: dq 0
+; LAPIC EOI register (identity-mapped)
+%define LAPIC_EOI_ADDR  0xFEE000B0
 
 section .text
 
 global irq_timer_isr
 extern scheduler_tick           ; Rust fn: unsafe extern "C" (MS x64 ABI)
 
 ; ───────────────────────────────────────────────────────────────────────────
-; irq_timer_isr — PIT timer interrupt handler (vector 0x20)
-; ───────────────────────────────────────────────────────────────────────────
-; Stack layout at ISR entry (before any pushes):
-;   [rsp+0x28]  SS
-;   [rsp+0x20]  RSP (before IRQ)
-;   [rsp+0x18]  RFLAGS
-;   [rsp+0x10]  CS
-;   [rsp+0x00]  RIP
-;
-; After `sub rsp, 0xA0` our CpuContext struct lives at [rsp]:
-;   [rsp+0x00 .. 0x9F]  CpuContext
-;   [rsp+0xA0 .. 0xC7]  CPU iretq frame (5 × 8 bytes)
+; irq_timer_isr — LAPIC timer interrupt handler (vector 0x20)
 ; ───────────────────────────────────────────────────────────────────────────
 irq_timer_isr:
+    ; ── SWAPGS if coming from user mode (ring 3) ─────────────────────────
+    ; check CS RPL in the iretq frame pushed by CPU
+    test    qword [rsp + 0x08], 3   ; CS is at rsp+8 (second qword)
+    jz      .no_swapgs_entry
+    swapgs
+.no_swapgs_entry:
+
     ; ── Allocate CpuContext on stack ──────────────────────────────────────
     sub     rsp, 0xA0
 
@@ -118,49 +113,42 @@ irq_timer_isr:
     mov     [rsp + 0x98], rax
 
     ; ── Save outgoing process FPU/SSE state (FXSAVE) ─────────────────────
-    ; current_fpu_ptr → &proc.fpu_state of the process being preempted.
-    ; Must happen BEFORE calling Rust (scheduler_tick may use XMM regs).
-    mov     rbx, [rel current_fpu_ptr]
+    ; per-CPU FPU pointer: gs:[0x18]
+    mov     rbx, [gs:0x18]              ; current_fpu_ptr
     test    rbx, rbx
     jz      .skip_fxsave
     fxsave  [rbx]
 .skip_fxsave:
 
-    ; ── ACK PIT (send EOI to master PIC before calling Rust) ─────────────
-    mov     al, 0x20
-    out     0x20, al
+    ; ── ACK LAPIC (write 0 to EOI register) ──────────────────────────────
+    xor     eax, eax
+    mov     dword [LAPIC_EOI_ADDR], eax
 
     ; ── Call scheduler_tick(current_ctx: *const CpuContext) ──────────────
     ; MS x64 ABI: first arg in RCX.  Need 32-byte shadow space on stack.
-    ; Current RSP = 8 mod 16 (verified in file header comment).
-    ; After sub 32 still 8 mod 16; CALL pushes 8 → callee sees 0 mod 16. ✓
     sub     rsp, 32                     ; shadow space
     lea     rcx, [rsp + 32]             ; &current_ctx
     call    scheduler_tick              ; RAX = *const CpuContext (next proc)
     add     rsp, 32                     ; remove shadow space
 
-    ; RAX = *const CpuContext of next process (points into PROCESS_TABLE).
-    ; scheduler_tick has updated current_fpu_ptr to point to the incoming
-    ; process's FpuState.
+    ; RAX = *const CpuContext of next process.
+    ; scheduler_tick has updated gs:[0x18] (current_fpu_ptr) and
+    ; gs:[0x10] (next_cr3) for the incoming process.
 
     ; ── Restore incoming process FPU/SSE state (FXRSTOR) ──────────────────
-    ; Must happen AFTER scheduler_tick (which updated the pointer) and
-    ; BEFORE restoring GPRs (FXRSTOR clobbers no GPRs, but we use RBX as
-    ; scratch — RBX will be properly restored from the next context below).
-    mov     rbx, [rel current_fpu_ptr]
+    mov     rbx, [gs:0x18]              ; updated current_fpu_ptr
     test    rbx, rbx
     jz      .skip_fxrstor
     fxrstor [rbx]
 .skip_fxrstor:
 
     ; ── Switch CR3 if process address spaces differ ───────────────────────
-    ; next_cr3 is written by scheduler_tick() before returning.
-    mov     rbx, [rel next_cr3]
+    mov     rbx, [gs:0x10]              ; next_cr3 from PerCpu
     test    rbx, rbx
-    jz      .skip_cr3                   ; zero = unset, don't switch
+    jz      .skip_cr3
     mov     rcx, cr3
     cmp     rbx, rcx
-    je      .skip_cr3                   ; same address space — avoid TLB flush
+    je      .skip_cr3
     mov     cr3, rbx
 .skip_cr3:
 
@@ -177,7 +165,6 @@ irq_timer_isr:
     mov     [rsp + 0xA0 + 0x20], rbx
 
     ; ── Restore GPRs from next-process context ────────────────────────────
-    ; rbx is restored last (used as scratch above) except rax (used as ptr).
     mov     r15, [rax + 0x70]
     mov     r14, [rax + 0x68]
     mov     r13, [rax + 0x60]
@@ -191,9 +178,18 @@ irq_timer_isr:
     mov     rsi, [rax + 0x20]
     mov     rdx, [rax + 0x18]
     mov     rcx, [rax + 0x10]
-    mov     rbx, [rax + 0x08]           ; restore rbx (was used as scratch)
-    mov     rax, [rax + 0x00]           ; restore rax last
+    mov     rbx, [rax + 0x08]
+    mov     rax, [rax + 0x00]
+
+    ; ── Remove CpuContext frame ───────────────────────────────────────────
+    add     rsp, 0xA0
+
+    ; ── SWAPGS if returning to user mode (ring 3) ────────────────────────
+    ; check next CS in the patched iretq frame
+    test    qword [rsp + 0x08], 3
+    jz      .no_swapgs_exit
+    swapgs
+.no_swapgs_exit:
 
     ; ── Return to next process ────────────────────────────────────────────
-    add     rsp, 0xA0                   ; remove CpuContext frame
     iretq