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| 1 | +#include <Library/DebugLib.h> |
| 2 | +#include <Library/UefiBootServicesTableLib.h> |
| 3 | +#include <Library/IoLib.h> |
| 4 | +#include <Library/UfsHostBridge.h> |
| 5 | + |
| 6 | +#include <Protocol/EfiGpio.h> |
| 7 | + |
| 8 | +#define WARM_RESET (1U << 28) |
| 9 | +#define LITTLE_WDT_RESET (1U << 24) |
| 10 | +#define EXYNOS9830_EDPCSR_DUMP_EN (1U << 0) |
| 11 | + |
| 12 | +#define UFS_SCLK 166000000UL |
| 13 | +#define CNT_VAL_1US_MASK 0x3FFU |
| 14 | +#define UFSHCI_VS_1US_TO_CNT_VAL 0x110CU |
| 15 | +#define UFSHCI_VS_UFSHCI_V2P1_CTRL 0x118CU |
| 16 | +#define IA_TICK_SEL (1U << 16) |
| 17 | + |
| 18 | +#define MUX_CLKCMU_UFS_EMBD_CON 0x1A331098UL |
| 19 | +#define DIV_CLKCMU_UFS_EMBD_MUX 0x1A331890UL |
| 20 | +#define UFS_CLKCMU_TIMEOUT 100 |
| 21 | + |
| 22 | +#define EXYNOS9830_UFS_BASE 0x13100000 |
| 23 | +#define EXYNOS9830_UFS_VS_BASE (EXYNOS9830_UFS_BASE + 0x1100) |
| 24 | +#define EXYNOS9830_UNIPRO_BASE (EXYNOS9830_UFS_BASE + 0x8000) |
| 25 | +#define EXYNOS9830_PHY_PMA_BASE (EXYNOS9830_UFS_BASE + 0x4000) |
| 26 | + |
| 27 | +#define EXYNOS9830_PMU_BASE 0x15860000 |
| 28 | +#define EXYNOS9830_PMU_RST_STAT (EXYNOS9830_PMU_BASE + 0x404) |
| 29 | +#define EXYNOS9830_PMU_SEQUENCER (EXYNOS9830_PMU_BASE + 0x500) |
| 30 | +#define EXYNOS9830_PMU_UFS_PHY_CONTROL (EXYNOS9830_PMU_BASE + 0x724) |
| 31 | + |
| 32 | +#define EXYNOS9830_PERIC1_BASE 0x10730000 |
| 33 | +#define EXYNOS9830_GPG1_BASE (EXYNOS9830_PERIC1_BASE + 0x00C0) |
| 34 | +#define EXYNOS9830_GPG1_DAT (EXYNOS9830_GPG1_BASE + 0x0004) |
| 35 | + |
| 36 | +#define EXYNOS9830_SYSREG_HSI1_BASE 0x13020000 |
| 37 | +#define EXYNOS9830_SYSREG_HSI1_IOCOHERENCY (EXYNOS9830_SYSREG_HSI1_BASE + 0x700) |
| 38 | + |
| 39 | +STATIC EFI_EXYNOS_GPIO_PROTOCOL *mGpioProtocol; |
| 40 | + |
| 41 | +STATIC |
| 42 | +VOID |
| 43 | +UfsVsSet1usToCnt (struct UfsHost *Ufs) |
| 44 | +{ |
| 45 | + UINT32 nVal = MmioRead32((UINTN)(Ufs->IoAddr + UFSHCI_VS_UFSHCI_V2P1_CTRL)); |
| 46 | + nVal |= IA_TICK_SEL; |
| 47 | + MmioWrite32((UINTN)(Ufs->IoAddr + UFSHCI_VS_UFSHCI_V2P1_CTRL), nVal); |
| 48 | + MmioWrite32((UINTN)(Ufs->IoAddr + UFSHCI_VS_1US_TO_CNT_VAL), (UFS_SCLK / 1000000) & CNT_VAL_1US_MASK); |
| 49 | +} |
| 50 | + |
| 51 | +STATIC |
| 52 | +VOID |
| 53 | +UfsSetUniProClk (struct UfsHost *Ufs) |
| 54 | +{ |
| 55 | + int timeout = 0; |
| 56 | + MmioWrite32(DIV_CLKCMU_UFS_EMBD_MUX, 3); |
| 57 | + do { timeout++; } while ((MmioRead32(DIV_CLKCMU_UFS_EMBD_MUX) & 0x10000) && timeout < UFS_CLKCMU_TIMEOUT); |
| 58 | + timeout = 0; |
| 59 | + MmioWrite32(MUX_CLKCMU_UFS_EMBD_CON, 1); |
| 60 | + do { timeout++; } while ((MmioRead32(MUX_CLKCMU_UFS_EMBD_CON) & 0x10000) && timeout < UFS_CLKCMU_TIMEOUT); |
| 61 | + UfsVsSet1usToCnt (Ufs); |
| 62 | +} |
| 63 | + |
| 64 | +EFI_STATUS |
| 65 | +UfsBoardInit (struct UfsHost *Ufs) |
| 66 | +{ |
| 67 | + UINT32 Register; |
| 68 | + UINT32 rst_stat = MmioRead32(EXYNOS9830_PMU_RST_STAT); |
| 69 | + UINT32 dfd_en = MmioRead32(EXYNOS9830_PMU_SEQUENCER); |
| 70 | + EFI_STATUS Status; |
| 71 | + |
| 72 | + Status = gBS->LocateProtocol (&gEfiExynosGpioProtocolGuid, NULL, (VOID *)&mGpioProtocol); |
| 73 | + if (EFI_ERROR (Status)) { |
| 74 | + DEBUG ((EFI_D_ERROR, "Failed to Locate GPIO Protocol! Status = %r\n", Status)); |
| 75 | + return Status; |
| 76 | + } |
| 77 | + |
| 78 | + DEBUG ((EFI_D_INFO, "UFS: Board init\n")); |
| 79 | + |
| 80 | + /* UFS Addrs */ |
| 81 | + Ufs->IoAddr = (VOID *)(UINTN)EXYNOS9830_UFS_BASE; |
| 82 | + Ufs->VsAddr = (VOID *)(UINTN)EXYNOS9830_UFS_VS_BASE; |
| 83 | + Ufs->UniProAddr = (VOID *)(UINTN)EXYNOS9830_UNIPRO_BASE; |
| 84 | + Ufs->PhyPma = (VOID *)(UINTN)EXYNOS9830_PHY_PMA_BASE; |
| 85 | + |
| 86 | + /* Power / PHY isolation addresses */ |
| 87 | + Ufs->DevPwrAddr = (VOID *)(UINTN)EXYNOS9830_GPG1_DAT; |
| 88 | + Ufs->DevPwrShift = 0; |
| 89 | + Ufs->PhyIsoAddr = (VOID *)(UINTN)EXYNOS9830_PMU_UFS_PHY_CONTROL; |
| 90 | + |
| 91 | + Ufs->MclkRate = 166 * 1000 * 1000; |
| 92 | + Ufs->GearMode = 4; |
| 93 | + |
| 94 | + UfsSetUniProClk (Ufs); |
| 95 | + |
| 96 | + // TODO : Hook this in with the actual GPIO driver, instead of direct memory writes. |
| 97 | + |
| 98 | + /* GPIO: RST_N and REFCLK */ |
| 99 | + Status = mGpioProtocol->SetPull(2, GPIO_BANK_ID_F, 0, GPIO_PULL_NONE); |
| 100 | + if (EFI_ERROR (Status)) { |
| 101 | + DEBUG ((EFI_D_ERROR, "Failed to set GPIO pull for RST_N! Status = %r\n", Status)); |
| 102 | + return Status; |
| 103 | + } |
| 104 | + |
| 105 | + Status = mGpioProtocol->SetPull(2, GPIO_BANK_ID_F, 1, GPIO_PULL_NONE); |
| 106 | + if (EFI_ERROR (Status)) { |
| 107 | + DEBUG ((EFI_D_ERROR, "Failed to set GPIO pull for REFCLK! Status = %r\n", Status)); |
| 108 | + return Status; |
| 109 | + } |
| 110 | + |
| 111 | + Status = mGpioProtocol->ConfigurePin(2, GPIO_BANK_ID_F, 0, 2); |
| 112 | + if (EFI_ERROR (Status)) { |
| 113 | + DEBUG ((EFI_D_ERROR, "Failed to configure GPIO pin for RST_N! Status = %r\n", Status)); |
| 114 | + return Status; |
| 115 | + } |
| 116 | + |
| 117 | + Status = mGpioProtocol->ConfigurePin(2, GPIO_BANK_ID_F, 1, 2); |
| 118 | + if (EFI_ERROR (Status)) { |
| 119 | + DEBUG ((EFI_D_ERROR, "Failed to configure GPIO pin for REFCLK! Status = %r\n", Status)); |
| 120 | + return Status; |
| 121 | + } |
| 122 | + |
| 123 | + /* XBOOTLDO GPG1[0] */ |
| 124 | + Status = mGpioProtocol->ConfigurePin(1, GPIO_BANK_ID_G, 0, GPIO_OUTPUT); |
| 125 | + if (EFI_ERROR (Status)) { |
| 126 | + DEBUG ((EFI_D_ERROR, "Failed to configure GPG1-0! Status = %r\n", Status)); |
| 127 | + return Status; |
| 128 | + } |
| 129 | + |
| 130 | + /* IO coherency in SYSREG (skip if warm/wdt reset with DFD) */ |
| 131 | + if (!((rst_stat & (WARM_RESET | LITTLE_WDT_RESET)) && (dfd_en & EXYNOS9830_EDPCSR_DUMP_EN))) |
| 132 | + { |
| 133 | + Register = MmioRead32(EXYNOS9830_SYSREG_HSI1_IOCOHERENCY); |
| 134 | + Register |= (BIT22 | BIT23); |
| 135 | + MmioWrite32(EXYNOS9830_SYSREG_HSI1_IOCOHERENCY, Register); |
| 136 | + } |
| 137 | + |
| 138 | + return EFI_SUCCESS; |
| 139 | +} |
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