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1 parent 1e9f2e6 commit c1dcc10Copy full SHA for c1dcc10
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src/implementations/eig.jl
@@ -129,7 +129,7 @@ end
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# Diagonal logic
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# --------------
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-eig_sortby(x::T) where {T <: Number} = T <: Complex ? (real(x), imag(X)) : x
+eig_sortby(x::T) where {T <: Number} = T <: Complex ? (real(x), imag(x)) : x
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function eig_full!(A::Diagonal, DV, alg::DiagonalAlgorithm)
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check_input(eig_full!, A, DV, alg)
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D, V = DV
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