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author
Adarsh Nair Mullachery
committed
cpu/stm32: address review comments
1 parent c7cd050 commit 4072c14

24 files changed

Lines changed: 101 additions & 104 deletions

‎boards/nucleo-u385rg-q/Makefile.features‎

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Original file line numberDiff line numberDiff line change
@@ -2,8 +2,6 @@ CPU = stm32
22
CPU_MODEL = stm32u385rg
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44
# Put defined MCU peripherals here (in alphabetical order)
5-
#FEATURES_PROVIDED += periph_i2c
6-
#FEATURES_PROVIDED += periph_pwm
75
FEATURES_PROVIDED += periph_timer
86
FEATURES_PROVIDED += periph_uart periph_lpuart
97
FEATURES_PROVIDED += periph_usbdev

‎boards/nucleo-u385rg-q/doc.md‎

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@@ -19,15 +19,15 @@ still be incomplete or untested.
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2020
### MCU
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22-
| MCU | STM32U385RG |
23-
|:------------------|:------------|
24-
| Family | ARM Cortex-M33 |
25-
| Vendor | STMicroelectronics |
26-
| RAM | 640KiB |
27-
| Flash | 1MiB |
28-
| Frequency | up to 96MHz |
29-
| FPU | yes |
30-
| TrustZone | yes |
22+
| MCU | STM32U385RG |
23+
|:------------------|:---------------------|
24+
| Family | ARM Cortex-M33 |
25+
| Vendor | STMicroelectronics |
26+
| RAM | 640KiB |
27+
| Flash | 1MiB |
28+
| Frequency | up to 96MHz |
29+
| FPU | yes |
30+
| TrustZone | yes |
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| Datasheet | [Datasheet](https://www.st.com/resource/en/datasheet/stm32u375ce.pdf) |
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| Reference Manual | [Reference Manual](https://www.st.com/resource/en/reference_manual/rm0487-stm32u3-series-armbased-32bit-mcus-stmicroelectronics.pdf) |
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| Programming Manual| [Programming Manual](https://www.st.com/resource/en/programming_manual/pm0264-stm32-cortexm33-mcus-and-mpus-programming-manual-stmicroelectronics.pdf) |

‎boards/nucleo-u385rg-q/include/periph_conf.h‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,6 @@
1+
# SPDX-FileCopyrightText: 2026 Technische Universität Hamburg
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# SPDX-License-Identifier: LGPL-2.1-only
3+
14
#pragma once
25

36
/**
@@ -8,8 +11,6 @@
811
* @brief Minimal peripheral configuration for STM32U385 (bring-up)
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*
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* @author Adarsh Nair Mullachery
11-
* This file is intentionally minimal to allow first successful boot
12-
* and GPIO operation (blinky).
1314
*/
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1516
#include "periph_cpu.h"
@@ -21,8 +22,6 @@ extern "C" {
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2223
/* No UART, SPI, I2C, PWM, USB yet */
2324

24-
25-
2625
/** @} */
2726
/**
2827
* @name Timer configuration
@@ -58,10 +57,13 @@ static const uart_conf_t uart_config[] = {
5857
}
5958
};
6059

61-
6260
#define UART_0_ISR isr_usart1
6361
#define UART_NUMOF (1)
6462

63+
/** @} */
64+
6565
#ifdef __cplusplus
6666
}
6767
#endif
68+
69+
/** @} */

‎cpu/stm32/Makefile.cmsis‎

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Original file line numberDiff line numberDiff line change
@@ -29,7 +29,7 @@ PKG_VERSION_l1=dafdef897e29b4f5934f1e2b9de9957410435476
2929
PKG_VERSION_l4=013bf0e41256ffbc2b539676f2007d08b297a86a
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# v1.0.5
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PKG_VERSION_l5=a43f959bdb1e7449cbabe14356ca9309dbd48ad3
32-
# v1.2.0 (STM32U3 CMSIS)
32+
# v1.2.0
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PKG_VERSION_u3=8b05f32016213eaf818fbceb01fab4c8347b15c3
3434
# v1.3.0
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PKG_VERSION_u5=06d7edade7167b0eafdd550bf77cfc4fa98eae2e

‎cpu/stm32/Makefile.features‎

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Original file line numberDiff line numberDiff line change
@@ -63,8 +63,8 @@ STM32_WITH_VBAT = stm32f031% stm32f038% stm32f042% stm32f048% \
6363
stm32g4% stm32gbk1cb \
6464
stm32l412% stm32l433% stm32l45% stm32l47% stm32l49% stm32l4r% \
6565
stm32l5% \
66+
stm32u3% \
6667
stm32u5% \
67-
stm32u3% \
6868
stm32wb% \
6969
stm32wl%
7070

‎cpu/stm32/cpu_common.c‎

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Original file line numberDiff line numberDiff line change
@@ -62,18 +62,18 @@ static const uint8_t apbmul[] = {
6262
[APB1] = 2,
6363
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
6464
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
65-
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
66-
defined(CPU_FAM_STM32U3) || \
67-
defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
65+
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U3) || \
66+
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32C0) || \
67+
defined(CPU_FAM_STM32WL)
6868
[APB12] = 2,
6969
#endif
7070
#else
7171
[APB1] = 1,
7272
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
7373
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32G4) || \
74-
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
75-
defined(CPU_FAM_STM32U3) || \
76-
defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0)
74+
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U3) || \
75+
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32C0) || \
76+
defined(CPU_FAM_STM32WL)
7777
[APB12] = 1,
7878
#endif
7979
#endif

‎cpu/stm32/dist/irqs/gen_irqs.py‎

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Original file line numberDiff line numberDiff line change
@@ -136,8 +136,6 @@ def generate_irqs(context):
136136
def main(args):
137137
"""Main function."""
138138
cpu_lines = list_cpu_lines(args.cmsis_dir, args.cpu_fam)
139-
140-
141139
context = {
142140
"cpu_fam": args.cpu_fam,
143141
"cpu_lines": [

‎cpu/stm32/include/clk/u3/cfg_clock_default.h‎

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Original file line numberDiff line numberDiff line change
@@ -1,3 +1,5 @@
1+
# SPDX-FileCopyrightText: 2026 Technische Universität Hamburg
2+
# SPDX-License-Identifier: LGPL-2.1-only
13

24
#pragma once
35

@@ -11,10 +13,10 @@
1113
* This configuration is intentionally conservative for early bring-up.
1214
* By default it uses HSI (16 MHz) as SYSCLK and disables PLL usage.
1315
*
14-
* @author <Adarsh Nair Mullachery>
16+
* @author Adarsh Nair Mullachery
1517
* @}
1618
*/
17-
/* cpu/stm32/include/clk/u3/cfg_clock_default.h */
19+
1820
#pragma once
1921

2022
#include "cfg_clock_common_lx_u5_wx.h"
@@ -31,45 +33,45 @@ extern "C" {
3133

3234
/* STM32U3: no main PLL */
3335
#ifndef CONFIG_USE_CLOCK_PLL
34-
#define CONFIG_USE_CLOCK_PLL 0
36+
# define CONFIG_USE_CLOCK_PLL 0
3537
#endif
3638

3739
/* Default to HSI for bring-up */
3840
#ifndef CONFIG_USE_CLOCK_HSI
39-
#define CONFIG_USE_CLOCK_HSI 1
41+
# define CONFIG_USE_CLOCK_HSI 1
4042
#endif
4143

4244
#ifndef CONFIG_CLOCK_HSI
43-
#define CONFIG_CLOCK_HSI MHZ(16)
45+
# define CONFIG_CLOCK_HSI MHZ(16)
4446
#endif
4547
#ifndef CONFIG_CLOCK_HSE
46-
#define CONFIG_CLOCK_HSE MHZ(8)
48+
# define CONFIG_CLOCK_HSE MHZ(8)
4749
#endif
4850
/* Pick a safe MSIS default if you later enable MSI mode */
4951
#ifndef CONFIG_CLOCK_MSI
50-
#define CONFIG_CLOCK_MSI MHZ(12)
52+
# define CONFIG_CLOCK_MSI MHZ(12)
5153
#endif
5254

5355
#if IS_ACTIVE(CONFIG_USE_CLOCK_HSE)
54-
#define CLOCK_CORECLOCK CONFIG_CLOCK_HSE
56+
# define CLOCK_CORECLOCK CONFIG_CLOCK_HSE
5557
#elif IS_ACTIVE(CONFIG_USE_CLOCK_MSI)
56-
#define CLOCK_CORECLOCK CONFIG_CLOCK_MSI
58+
# define CLOCK_CORECLOCK CONFIG_CLOCK_MSI
5759
#else
58-
#define CLOCK_CORECLOCK CONFIG_CLOCK_HSI
60+
# define CLOCK_CORECLOCK CONFIG_CLOCK_HSI
5961
#endif
6062

6163
#define CLOCK_CORECLOCK_MAX MHZ(96)
6264
#if CLOCK_CORECLOCK > CLOCK_CORECLOCK_MAX
63-
#error "SYSCLK cannot exceed 96MHz on STM32U3"
65+
# error "SYSCLK cannot exceed 96MHz on STM32U3"
6466
#endif
6567

6668
#define CLOCK_AHB CLOCK_CORECLOCK
6769

6870
#ifndef CONFIG_CLOCK_APB1_DIV
69-
#define CONFIG_CLOCK_APB1_DIV (1)
71+
# define CONFIG_CLOCK_APB1_DIV (1)
7072
#endif
7173
#ifndef CONFIG_CLOCK_APB2_DIV
72-
#define CONFIG_CLOCK_APB2_DIV (1)
74+
# define CONFIG_CLOCK_APB2_DIV (1)
7375
#endif
7476

7577
#define CLOCK_APB1 (CLOCK_AHB / CONFIG_CLOCK_APB1_DIV)

‎cpu/stm32/include/cpu_conf.h‎

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Original file line numberDiff line numberDiff line change
@@ -63,14 +63,14 @@
6363
#elif CPU_FAM_STM32L5
6464
#include "stm32l5xx.h"
6565
#include "irqs/l5/irqs.h"
66-
#elif CPU_FAM_STM32U5
67-
#include "stm32u5xx.h"
68-
#include "irqs/u5/irqs.h"
69-
#define NUM_HEAPS 3
7066
#elif CPU_FAM_STM32U3
7167
#include "stm32u3xx.h"
7268
#include "irqs/u3/irqs.h"
7369
#define NUM_HEAPS 3
70+
#elif CPU_FAM_STM32U5
71+
#include "stm32u5xx.h"
72+
#include "irqs/u5/irqs.h"
73+
#define NUM_HEAPS 3
7474
#elif CPU_FAM_STM32WB
7575
#include "stm32wbxx.h"
7676
#include "irqs/wb/irqs.h"
@@ -221,9 +221,9 @@ extern "C" {
221221
*/
222222
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
223223
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
224-
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
225-
defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0) || \
226-
defined(CPU_FAM_STM32U3)
224+
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U3) || \
225+
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32C0) || \
226+
defined(CPU_FAM_STM32WL)
227227
#define FLASHPAGE_WRITE_BLOCK_SIZE (8U)
228228
typedef uint64_t stm32_flashpage_block_t;
229229
#elif defined(CPU_FAM_STM32L0) || defined(CPU_FAM_STM32L1) || \
@@ -238,9 +238,9 @@ typedef uint16_t stm32_flashpage_block_t;
238238

239239
#if defined(CPU_FAM_STM32L4) || defined(CPU_FAM_STM32WB) || \
240240
defined(CPU_FAM_STM32G4) || defined(CPU_FAM_STM32G0) || \
241-
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U5) || \
242-
defined(CPU_FAM_STM32WL) || defined(CPU_FAM_STM32C0) || \
243-
defined(CPU_FAM_STM32U3)
241+
defined(CPU_FAM_STM32L5) || defined(CPU_FAM_STM32U3) || \
242+
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32C0) || \
243+
defined(CPU_FAM_STM32WL)
244244
#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (8U)
245245
#else
246246
/* Writing should be always 4 bytes aligned */

‎cpu/stm32/include/periph/cpu_common.h‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -59,7 +59,7 @@ extern "C" {
5959
defined(CPU_FAM_STM32F7) || defined(CPU_FAM_STM32L4) || \
6060
defined(CPU_FAM_STM32WB) || defined(CPU_FAM_STM32G4) || \
6161
defined(CPU_FAM_STM32G0) || defined(CPU_FAM_STM32L5) || \
62-
defined(CPU_FAM_STM32U5) || defined(CPU_FAM_STM32U3) || \
62+
defined(CPU_FAM_STM32U3) || defined(CPU_FAM_STM32U5) || \
6363
defined(CPU_FAM_STM32MP1) || defined(CPU_FAM_STM32WL) || \
6464
defined(CPU_FAM_STM32C0)
6565
#define CLOCK_LSI (32000U)
@@ -71,8 +71,8 @@ extern "C" {
7171
#if defined(CPU_FAM_STM32G4) || \
7272
defined(CPU_FAM_STM32L4) || \
7373
defined(CPU_FAM_STM32L5) || \
74+
defined(CPU_FAM_STM32U3) || \
7475
defined(CPU_FAM_STM32U5) || \
75-
defined(CPU_FAM_STM32U3) || \
7676
defined(CPU_FAM_STM32WB) || \
7777
defined(CPU_FAM_STM32WL)
7878
#define APB1_PERIPH_EN RCC->APB1ENR1
@@ -116,7 +116,7 @@ extern "C" {
116116
#define AHB_PERIPH_EN RCC->AHBENR
117117
#elif defined(CPU_FAM_STM32U3)
118118
#define AHB1_PERIPH_EN RCC->AHB1ENR1
119-
#define AHB12_PERIPH_EN RCC->AHB1ENR2
119+
#define AHB12_PERIPH_EN RCC->AHB1ENR2
120120
#elif defined(CPU_FAM_STM32MP1)
121121
/* CPU has AHB1, but no periph enable registers for the bus. */
122122
#undef AHB1_PERIPH_EN /* not defined */
@@ -130,8 +130,8 @@ extern "C" {
130130
defined(CPU_FAM_STM32F3)
131131
/* CPU has AHB2, but no periph enable registers for the bus. */
132132
#undef AHB2_PERIPH_EN /* not defined */
133-
#elif defined(CPU_FAM_STM32U5) || \
134-
defined(CPU_FAM_STM32U3)
133+
#elif defined(CPU_FAM_STM32U3) || \
134+
defined(CPU_FAM_STM32U5)
135135
#define AHB2_PERIPH_EN RCC->AHB2ENR1
136136
#define AHB22_PERIPH_EN RCC->AHB2ENR2
137137
#elif defined(CPU_FAM_STM32F4) && defined(RCC_AHB2_SUPPORT)

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