Merge pull request #239 from RISC-KC/develop

[Feat] Revised Data Memory, Instruction Memory, Byte Enable logic, Top module to solve z-x signals in waveform

Author: ChoiCube84

modules/Byte_Enable_Logic.v

@@ -117,6 +117,8 @@ module ByteEnableLogic (
 			register_file_write_data = 32'b0;
 			data_memory_write_data = 32'b0;
 			write_mask = 4'b0;
+			byte_sel = 8'b0;
+			half_sel = 16'b0;
 		end
     end
 

modules/Data_Memory.v

@@ -26,6 +26,7 @@ module DataMemory (
         for (i=0; i<1024; i=i+1) begin
             memory[i] = 32'b0;
         end // $readmemh("./data_init.mem", memory, 13'h1424);
+        new_word = 32'b0;
     end
 
     always @(*) begin

modules/Instruction_Memory.v

@@ -58,6 +58,10 @@ module RV32I46F5SPMMIO #(
     wire [XLEN-1:0] IF_imm;
     wire [6:0] IF_opcode;
 
+    // ROM bypass signals (MEM stage instruction memory access)
+    wire [31:0] rom_address;
+    wire [31:0] rom_read_data;
+
     assign IF_imm = {{20{instruction[31]}}, instruction[7], instruction[30:25], instruction[11:8], 1'b0};
     assign IF_opcode = (instruction[6:0]);
 
@@ -348,6 +352,8 @@ module RV32I46F5SPMMIO #(
         .address(MEM_alu_result),
         .write_data(data_memory_write_data),
         .write_mask(write_mask),
+        .rom_read_data(rom_read_data),
+        .rom_address(rom_address),
 
         .read_data(data_memory_read_data)
     );
@@ -474,7 +480,9 @@ module RV32I46F5SPMMIO #(
 
     InstructionMemory instruction_memory (
         .pc(pc),
-        .instruction(im_instruction)
+        .instruction(im_instruction),
+        .rom_address(rom_address),
+        .rom_read_data(rom_read_data)
     );
 
     MMIO_Interface mmio_interface (

modules/RV32I46F_5SP_MMIO.v

@@ -1,5 +1,5 @@
 $date
-	Sat Dec 13 20:29:33 2025
+	Wed Dec 24 12:20:00 2025
 $end
 $version
 	Icarus Verilog
@@ -33,7 +33,7 @@ $end
 $dumpvars
 b10000000000 .
 b10010001101000101011001111000 -
-bx ,
+b0 ,
 b0 +
 0*
 b1 )