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Commit 393a27f

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author
Ben Davis
committed
Added clocking blocks to the interface
1 parent 84fe1dc commit 393a27f

4 files changed

Lines changed: 108 additions & 59 deletions

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‎proj.toml‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,5 +3,5 @@
33
[package]
44

55
name="ahb_agent"
6-
version="0.1.0"
6+
version="0.1.1b1"
77
description="An AHB UVM Agent"

‎src/agent/ahb_driver.svh‎

Lines changed: 47 additions & 47 deletions
Original file line numberDiff line numberDiff line change
@@ -117,49 +117,49 @@ class ahb_driver#(`_AHB_AGENT_PARAM_DEFS) extends uvm_driver#(ahb_transaction#(`
117117
end
118118
join_none
119119

120-
m_vif.haddr = '0;
121-
m_vif.hburst = SINGLE;
122-
m_vif.hmastlock = 1'b0;
123-
m_vif.hprot = (HPROT_WIDTH == 7) ? 7'b000_0011 : 4'b0011;
124-
m_vif.hsize = (DATA_WIDTH <= 8 ) ? BYTE_SIZE :
125-
(DATA_WIDTH <= 16) ? HALFWORD_SIZE :
126-
(DATA_WIDTH <= 32) ? WORD_SIZE :
127-
(DATA_WIDTH <= 64) ? DOUBLEWORD_SIZE :
128-
(DATA_WIDTH <= 128) ? FOUR_WORD_SIZE :
129-
(DATA_WIDTH <= 256) ? EIGHT_WORD_SIZE :
130-
(DATA_WIDTH <= 512) ? SIXTEEN_WORD_SIZE :
131-
THIRTY_TWO_WORD_SIZE;
132-
m_vif.hnonsec = 1'b1;
133-
m_vif.hexcl = 1'b0;
134-
m_vif.hmaster = '0;
135-
m_vif.htrans = IDLE;
136-
m_vif.hwdata = '0;
137-
m_vif.hwstrb = '1;
138-
m_vif.hwrite = 1'b0;
139-
140-
m_vif.hsel = 1'b0;
120+
m_vif.drv_mgr_cb.haddr <= '0;
121+
m_vif.drv_mgr_cb.hburst <= SINGLE;
122+
m_vif.drv_mgr_cb.hmastlock <= 1'b0;
123+
m_vif.drv_mgr_cb.hprot <= (HPROT_WIDTH == 7) ? 7'b000_0011 : 4'b0011;
124+
m_vif.drv_mgr_cb.hsize <= (DATA_WIDTH <= 8 ) ? BYTE_SIZE :
125+
(DATA_WIDTH <= 16) ? HALFWORD_SIZE :
126+
(DATA_WIDTH <= 32) ? WORD_SIZE :
127+
(DATA_WIDTH <= 64) ? DOUBLEWORD_SIZE :
128+
(DATA_WIDTH <= 128) ? FOUR_WORD_SIZE :
129+
(DATA_WIDTH <= 256) ? EIGHT_WORD_SIZE :
130+
(DATA_WIDTH <= 512) ? SIXTEEN_WORD_SIZE :
131+
THIRTY_TWO_WORD_SIZE;
132+
m_vif.drv_mgr_cb.hnonsec <= 1'b1;
133+
m_vif.drv_mgr_cb.hexcl <= 1'b0;
134+
m_vif.drv_mgr_cb.hmaster <= '0;
135+
m_vif.drv_mgr_cb.htrans <= IDLE;
136+
m_vif.drv_mgr_cb.hwdata <= '0;
137+
m_vif.drv_mgr_cb.hwstrb <= '1;
138+
m_vif.drv_mgr_cb.hwrite <= 1'b0;
139+
140+
m_vif.drv_mgr_cb.hsel <= 1'b0;
141141

142142
forever begin
143-
@(posedge m_vif.hclk);
143+
@(m_vif.drv_mgr_cb);
144144

145145
if (!m_vif.hreset_n)
146146
continue;
147147

148148
// First Check if the data_transaction is done
149-
if (m_vif.hready && data_trans != null) begin
149+
if (m_vif.drv_mgr_cb.hready && data_trans != null) begin
150150
if (data_trans.write == AHB_WRITE) begin
151-
data_trans.data = m_vif.hwdata;
151+
data_trans.data = m_vif.drv_mgr_cb.hwdata;
152152
end
153153
else begin
154-
data_trans.data = m_vif.hrdata;
154+
data_trans.data = m_vif.drv_mgr_cb.hrdata;
155155
end
156156

157157
`uvm_info(get_type_name(), "Finished Transaction", UVM_HIGH)
158158
seq_item_port.put(data_trans);
159159
data_trans = addr_trans;
160160
addr_trans = null;
161161
end
162-
else if (m_vif.hready) begin
162+
else if (m_vif.drv_mgr_cb.hready) begin
163163
data_trans = addr_trans;
164164
addr_trans = null;
165165
end
@@ -174,7 +174,7 @@ class ahb_driver#(`_AHB_AGENT_PARAM_DEFS) extends uvm_driver#(ahb_transaction#(`
174174

175175
// Check if there is a data_trans to update the transaction with
176176
if (data_trans != null) begin
177-
m_vif.hwdata = data_trans.data;
177+
m_vif.drv_mgr_cb.hwdata <= data_trans.data;
178178
end
179179

180180
// Check if we should fetch the next transaction
@@ -185,17 +185,17 @@ class ahb_driver#(`_AHB_AGENT_PARAM_DEFS) extends uvm_driver#(ahb_transaction#(`
185185

186186
// Check if there is a transaction in the address phase
187187
if (addr_trans != null) begin
188-
m_vif.hsel = 1'b1;
189-
m_vif.htrans = NONSEQ;
190-
m_vif.hsize = addr_trans.size;
191-
m_vif.haddr = addr_trans.addr;
192-
m_vif.hwrite = addr_trans.write;
193-
m_vif.hwstrb = addr_trans.wstrb;
194-
m_vif.hprot = addr_trans.hprot;
188+
m_vif.drv_mgr_cb.hsel <= 1'b1;
189+
m_vif.drv_mgr_cb.htrans <= NONSEQ;
190+
m_vif.drv_mgr_cb.hsize <= addr_trans.size;
191+
m_vif.drv_mgr_cb.haddr <= addr_trans.addr;
192+
m_vif.drv_mgr_cb.hwrite <= addr_trans.write;
193+
m_vif.drv_mgr_cb.hwstrb <= addr_trans.wstrb;
194+
m_vif.drv_mgr_cb.hprot <= addr_trans.hprot;
195195
end
196196
else begin
197-
m_vif.hsel = 1'b0;
198-
m_vif.htrans = IDLE;
197+
m_vif.drv_mgr_cb.hsel <= 1'b0;
198+
m_vif.drv_mgr_cb.htrans <= IDLE;
199199
end
200200

201201
end
@@ -215,29 +215,29 @@ class ahb_driver#(`_AHB_AGENT_PARAM_DEFS) extends uvm_driver#(ahb_transaction#(`
215215
end
216216
join_none
217217

218-
m_vif.hrdata = '0;
219-
m_vif.hreadyout = 1'b1;
220-
m_vif.hresp = 1'b0;
221-
m_vif.hexokay = 1'b1;
218+
m_vif.drv_sub_cb.hrdata <= '0;
219+
m_vif.drv_sub_cb.hreadyout <= 1'b1;
220+
m_vif.drv_sub_cb.hresp <= 1'b0;
221+
m_vif.drv_sub_cb.hexokay <= 1'b1;
222222

223223
forever begin
224-
m_vif.hreadyout = 1'b1;
224+
m_vif.drv_sub_cb.hreadyout <= 1'b1;
225225

226226
seq_item_port.get_next_item(trans);
227-
m_vif.hreadyout = 1'b0;
227+
m_vif.drv_sub_cb.hreadyout <= 1'b0;
228228

229229
repeat(trans.wait_states) begin
230-
@(posedge m_vif.hclk);
230+
@(m_vif.drv_sub_cb);
231231
end
232232

233233
if (trans.write == AHB_READ) begin
234-
m_vif.hrdata = trans.data;
234+
m_vif.drv_sub_cb.hrdata <= trans.data;
235235
end
236236

237-
m_vif.hreadyout = 1'b1;
238-
m_vif.hresp = trans.error;
237+
m_vif.drv_sub_cb.hreadyout <= 1'b1;
238+
m_vif.drv_sub_cb.hresp <= trans.error;
239239

240-
@(posedge m_vif.hclk);
240+
@(m_vif.drv_sub_cb);
241241
seq_item_port.item_done();
242242
end
243243
endtask : manager_run_phase

‎src/agent/ahb_monitor.svh‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -98,33 +98,33 @@ class ahb_monitor#(`_AHB_AGENT_PARAM_DEFS) extends uvm_monitor;
9898
ahb_transaction #(`_AHB_AGENT_PARAM_MAP) trans;
9999

100100
forever begin
101-
@(posedge m_vif.hclk);
101+
@(m_vif.mon_cb);
102102

103103
if (!m_vif.hreset_n) begin
104104
trans = null;
105105
continue;
106106
end
107107

108-
if (m_vif.hready) begin
108+
if (m_vif.mon_cb.hready) begin
109109
if (trans != null) begin
110110
if (trans.write == AHB_READ) begin
111-
trans.data = m_vif.hrdata;
111+
trans.data = m_vif.mon_cb.hrdata;
112112
end
113113
else begin
114-
trans.data = m_vif.hwdata;
114+
trans.data = m_vif.mon_cb.hwdata;
115115
end
116116

117117
ap.write(trans);
118118
trans = null;
119119
end
120120

121-
if (trans == null && m_vif.hsel && m_vif.htrans == NONSEQ) begin
121+
if (trans == null && m_vif.mon_cb.hsel && m_vif.mon_cb.htrans == NONSEQ) begin
122122
trans = ahb_transaction#(`_AHB_AGENT_PARAM_MAP)::type_id::create("monitor_trans");
123-
trans.addr = m_vif.haddr;
124-
trans.write = ahb_write_e'(m_vif.hwrite);
125-
trans.size = ahb_size_e'(m_vif.hsize);
126-
trans.hprot = m_vif.hprot;
127-
trans.wstrb = m_vif.hwstrb;
123+
trans.addr = m_vif.mon_cb.haddr;
124+
trans.write = ahb_write_e'(m_vif.mon_cb.hwrite);
125+
trans.size = ahb_size_e'(m_vif.mon_cb.hsize);
126+
trans.hprot = m_vif.mon_cb.hprot;
127+
trans.wstrb = m_vif.mon_cb.hwstrb;
128128

129129
for (int i = 0; i < int'(trans.size); i++) begin
130130
if (trans.addr[i] !== 1'b0) begin
@@ -152,7 +152,7 @@ class ahb_monitor#(`_AHB_AGENT_PARAM_DEFS) extends uvm_monitor;
152152
)
153153
)
154154
end
155-
req.data = m_vif.hwdata;
155+
req.data = m_vif.mon_cb.hwdata;
156156
req_ap.write(req);
157157
end
158158
end

‎src/interfaces/ahb_vip_if.sv‎

Lines changed: 49 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -65,4 +65,53 @@ interface ahb_vip_if #(
6565

6666
logic hready;
6767

68+
// Group: Clocking Blocks
69+
////////////////////////////////////////////////////////////////////////////////////////////////
70+
//
71+
// Note: 'hready' models the bus multiplexor output (a combinational passthrough of
72+
// 'hreadyout' driven by the agent), so it is only ever sampled - never an output - of the
73+
// clocking blocks below to avoid a multi-driver conflict with that passthrough.
74+
75+
// Clocking Block: drv_mgr_cb
76+
// Drives the manager-side stimulus (used by the driver in AHB_SUBORDINATE_AGENT mode)
77+
clocking drv_mgr_cb @(posedge hclk);
78+
default input #1step output #1;
79+
output haddr, hburst, hmastlock, hprot, hsize, hnonsec, hexcl, hmaster,
80+
htrans, hwdata, hwstrb, hwrite, hsel;
81+
input hrdata, hreadyout, hresp, hexokay, hready;
82+
endclocking : drv_mgr_cb
83+
84+
// Clocking Block: drv_sub_cb
85+
// Drives the subordinate-side response (used by the driver in AHB_MANAGER_AGENT mode)
86+
clocking drv_sub_cb @(posedge hclk);
87+
default input #1step output #1;
88+
output hrdata, hreadyout, hresp, hexokay;
89+
input haddr, hburst, hmastlock, hprot, hsize, hnonsec, hexcl, hmaster,
90+
htrans, hwdata, hwstrb, hwrite, hsel, hready;
91+
endclocking : drv_sub_cb
92+
93+
// Clocking Block: mon_cb
94+
// Samples every functional signal (used by the monitor)
95+
clocking mon_cb @(posedge hclk);
96+
default input #1step;
97+
input haddr, hburst, hmastlock, hprot, hsize, hnonsec, hexcl, hmaster,
98+
htrans, hwdata, hwstrb, hwrite, hsel,
99+
hrdata, hreadyout, hresp, hexokay, hready;
100+
endclocking : mon_cb
101+
102+
// Group: Modports
103+
////////////////////////////////////////////////////////////////////////////////////////////////
104+
105+
// Modport: drv_mgr
106+
// Manager-stimulus driver view
107+
modport drv_mgr (clocking drv_mgr_cb, input hclk, input hreset_n);
108+
109+
// Modport: drv_sub
110+
// Subordinate-response driver view
111+
modport drv_sub (clocking drv_sub_cb, input hclk, input hreset_n);
112+
113+
// Modport: mon
114+
// Passive monitor view
115+
modport mon (clocking mon_cb, input hclk, input hreset_n);
116+
68117
endinterface : ahb_vip_if

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