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IFU-dev-20260706-v2.17
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Ifu dev 20260706 v2.17#660
AllenFarcas wants to merge 178 commits into
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IFU-dev-20260706-v2.17

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Description

Please include a brief summary of the changes, relevant motivation and context.

Fixes # (issue)

Type of change

  • Documentation change (change only to the documentation, either a fix or a new content)
  • Bug fix (non-breaking change which fixes an issue)
  • New feature (non-breaking change which adds functionality)
  • Breaking change (fix or feature that would cause existing functionality to not work as expected)
  • Infra/Build change
  • Code refactoring

Changes

Please list the changes introduced in this PR:

  • Change A
  • Change B

Checklist:

  • I have read and followed the contributing guidelines
  • The functionality is complete
  • I have commented my code, particularly in hard-to-understand areas
  • I have made corresponding changes to the documentation
  • My changes generate no new warnings
  • I have added tests that prove my fix is effective or that my feature works
  • New and existing unit tests pass locally with my changes

ptrendx and others added 30 commits April 20, 2026 11:45
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
* Reduced padding kernel compilation time

Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>

* Completely removed unroll for better performance

Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>

---------

Signed-off-by: Oleg Goncharov <ogoncharov@nvidia.com>
…(#2905)

Zero out padded region when swizzling via group quantize

Signed-off-by: Kirthi Shankar Sivamani <ksivamani@nvidia.com>
…2879)

* fix broken links in README

Signed-off-by: Santosh Bhavani <santosh.bhavani@live.com>

* update README to modernize description and standardize terminology

Signed-off-by: Santosh Bhavani <santosh.bhavani@live.com>

* Update README.rst

Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
Signed-off-by: Santosh Bhavani <santosh.bhavani@live.com>

* Removed the duplicate line

Signed-off-by: Przemek Tredak <ptredak@nvidia.com>

---------

Signed-off-by: Santosh Bhavani <santosh.bhavani@live.com>
Signed-off-by: Przemek Tredak <ptredak@nvidia.com>
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
Co-authored-by: Przemek Tredak <ptredak@nvidia.com>
* initial implementation for mxfp8

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* semi-working FP8; broken F16

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IFU of upstream release_v2.17 (156 commits, v2.15 -> v2.17) into ROCm dev.
Resolved 78 conflicts and audited non-conflicting upstream changes for ROCm.

Highlights:
- NVFP4/MXFP4 enum chain: upstream enums keep values 8/9; ROCm-guarded MXFP4
  enums renumbered to 10/11 across transformer_engine.h, common.h attr_sizes[],
  and transformer_engine.cpp switch cases.
- _Linear refactored to upstream's LinearFwdArgs/LinearBwdArgs dataclass API;
  ROCm fields (keep_fp8_weight_transpose_cache, use_fsdp2, FSDP2 autocast) folded in.
- Test Tensor helper adopted upstream Buffer/CudaPtr model; ROCm MXFP4 + gfx950
  stochastic-rounding + NVTE_ROCM_BENCHMARK paths re-grafted.
- Attention backend gating: re-fenced new NV-only cuDNN/SM disables behind
  not IS_HIP_EXTENSION; CP fused-attn API rename adopted with CK backend selection.
- NCCL EP (new CUDA/NCCL-only subsystem) force-disabled on ROCm; topk moved to
  cuda_only (cub/cooperative_groups have no HIP equivalent) with jax guards;
  async_loader.h cuda_pipeline.h include guarded.

Note: full ROCm HIP build + GPU runtime tests not yet run (no GPU/torch in the
resolution environment). Static validation only: zero conflict markers, all
Python py_compile clean, C++ preprocessor/brace balance verified, cross-file
coherence audited.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
@AllenFarcas AllenFarcas self-assigned this Jul 7, 2026
@wenchenvincent wenchenvincent marked this pull request as draft July 7, 2026 19:26
AllenFarcas and others added 21 commits July 7, 2026 21:50
Post-merge fixes so the release_v2.17 IFU compiles and installs on ROCm
(gfx950): common library + PyTorch and JAX extensions.

Common library:
- quantize.cuh: guard CUDA-only nvfp4::compute_rowwise_amax (row-scaled NVFP4
  unsupported on ROCm).
- fused_router/utils.h: restore sum()/max() helpers dropped by upstream's
  warp_reduce_on_shmem rewrite; guard naive_topk_and_mask_smallk warp shuffles
  for wave64 (non-sync width-32 variants).
- swizzle.cu: guard the new variable-shape grouped-swizzle kernel (wave32
  reduction) on ROCm; keep the uniform-shape path.
- flash_attn.cu: guard the new TMA (CUtensorMap) multi_tensor_transpose_to_bhsd
  path; ROCm stub for the entry point.
- rtc.cpp: guard the new CUDA-version diagnostic block.
- fused_router/async_loader.h: guard <cuda_pipeline.h>.
- fused_attn_rocm/fused_attn.cpp: reconcile nvte_fused_attn_fwd/bwd with the new
  upstream format-descriptor params (strict on layout formats, ignore FP8
  scale-inv formats).
- fused_attn.h: keep NVTE_F16_max512_seqlen on the CUDA path.

PyTorch extension:
- MXFP4Quantizer::create_tensor/create_grouped_tensor: match the new base
  Quantizer virtuals (device/pin_memory; precomputed tensor_offsets).

JAX extension:
- Guard the new cuDNN score_mod (flex-attention) feature on ROCm; add a ROCm
  stub for GetCudnnFrontendVersion.
- topk / EP handled elsewhere; NCCL EP forced off on ROCm.

Also: normalize ROCm guard comments ("Disabled on ROCm") and fix pre-existing
comment typos.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Upstream v2.17's Tensor test helper made scalar accessors (scale, amax,
rowwise_scale_inv) strict: they assert the underlying buffer exists.
Fork test call sites read them unconditionally, aborting on non-scaled
tensors. Gate each call on the condition that governs buffer existence
(is_fp8_output / isFp8Type input / MXFP4 has no global scale) so the
accessors stay strict and still catch genuine misuse.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The v2.17 merge replaced the arch-aware fp8 e4m3 max with a hardcoded
E4M3_MAX=448 in the dequant factor. On fnuz archs (e.g. gfx942/gfx950,
maxNorm=240) this scales the dequantized output by 448/240 (~1.87x),
producing wrong results. Restore the arch-aware factor on HIP device
compilation using detail::TypeExtrema<fp8e4m3>::max; the CUDA path is
unchanged.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Align the upstream v2.17 operator tests with ROCm's actual support surface:

- test_cast_nvfp4_transpose.cu: skip NVFP4 4over6 and row-scaled NVFP4 on
  ROCm (both are rejected by the production quantize guards) so they report
  SKIPPED instead of aborting on the assert.
- test_multi_swizzle.cu: mirror the sibling swizzle suites. MultiTensorSwizzle
  runs on ROCm (skip gfx1250 pre-swizzle layout + shapes whose compact MXFP8
  scales are not 128-aligned); Unswizzle and Roundtrip are compiled out, like
  UnswizzleTestSuite.
- test_dequantize_nvfp4.cu: null the tensor amax so the dequant kernel takes
  the intended nullptr->1.0 fallback (the merged Tensor helper now allocates a
  zero-initialized amax buffer), matching the reference.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
inplace_swizzle_scale_for_gemm lacked the ROCm early-return that its sibling
swizzle_scales_for_gemm has, so it wrote the nullopt swizzle result back and
nulled valid NVFP4 scale_inv for optimize_for_gemm activations, crashing at
generic_gemm. Mirror the sibling's guard (MXFP8/gfx1250 only).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The row-wise amax kernel was trapped in the Blackwell-only
quantize_transpose_nvfp4 header (excluded from the ROCm build). Extract a
portable nvfp4::compute_rowwise_amax into rowwise_amax_nvfp4.cuh and call it on
both platforms; the quantize (vector_blockwise) and dequantize kernels already
handle row-scaled inputs.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The grouped-tensor GEMM entry points and fused grouped-linear path are CUDA-only;
guard them with USE_ROCM / IS_HIP_EXTENSION so ROCm uses te_general_grouped_gemm.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Move _QuantizeFunc / _IdentityFunc / _stride_from_shape imports to function
scope to break the import cycle that prevented the module from loading.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Current scaling computes amax/scale inside the kernel, so supply workspace
buffers instead of reading quantizer.scale/amax, use storage-safe size() and
transpose-cache clears, and compare on _scale_inv in the test.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
RecipeState.create() passes roles= to every recipe-state class; MXFP4 was the
only one missing it (parity with the other six). Update the MXFP4 test factory
to dispatch on QuantizerRole fields instead of the obsolete string roles, and
return a quantizer for every slot to satisfy make_quantizers.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
Skip un-ported upstream features on ROCm: 4over6 and grouped NVFP4, and the
Blackwell-only RHT cast-fusion swizzled-SF tests. Also fix tex->te.DType in
test_permutation and add the bshd KV-cache FusedAttention ROCm skip.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
v2.17 gave recipes named ids (ids=recipe_id), so the positional 'recipe0' no
longer matches and the mxfp8 test_numerics run selected 0 tests (pytest exit 5,
counted as a harness error). Target the MXFP8 recipe by its name.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The fused quantized Triton-norm path on ROCm allocates the destination via
make_empty with an internal quantizer, yielding an NVFP4TensorStorage; but
update_quantized asserted the full NVFP4Tensor and aborted. Storage is the
legitimate quantize target — the C++ fused-norm path writes into create_tensor
output the same way, and tex.quantize operates on the storage buffers — so
accept the NVFP4TensorStorage base type (NVFP4Tensor subclasses it, CUDA
unaffected). Fixes NVFP4 activation-recompute under NVTE_USE_LAYERNORM_TRITON.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
_FromNVFP4Func.forward moved a CPU-resident NVFP4 tensor to CUDA via the
subclass .to(), which re-enters __torch_dispatch__ -> dequantize -> .to() and
recurses infinitely (hit by FSDP2 DCP CPU staging). Move the raw buffers via
the metadata dict instead (matching the _to_copy handler), avoiding the
re-dispatch. Verified on mGPU: NVFP4 sync-DCP parity and the other NVFP4
fused-adam tests pass; recursion eliminated.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
fsdp_post_all_gather reconstructed the scale_inv via 1 / quantizer.scale,
but Float8CurrentScalingQuantizer computes its scale in-kernel and has no
.scale attribute, so current-scaling weights crashed with AttributeError
during the FSDP2 all-gather (test_distributed[current-False]).

fsdp_pre_all_gather already quantizes with amax reduction, so every rank's
per-tensor scale_inv is identical; thread it through the all-gather metadata
and use it for current scaling in post_all_gather. The delayed-scaling path
(1 / quantizer.scale) is unchanged.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
test_dcp_output_parity[NVFP4BlockScaling-async] is not bitwise-identical on
torch 2.8: the default BlockingAsyncStager stages each parameter into a plain
torch.empty(logical_shape, dtype) buffer, dequantizing the NVFP4Tensor. The
checkpoint stores bf16 instead of the fp4 data + scales, and reload re-quantizes
-- NVFP4's E4M3 block scales/amax do not survive the bf16 round-trip (MXFP8
survives via E8M0). Upstream #2721 fixes only Float8Tensor, via an aten.new_empty
hook that torch 2.8's torch.empty-based stager never calls.

Sync DCP is bitwise-correct, so checkpointing works. xfail is a temporary
placeholder pending a proper fix (custom AsyncStager or torch upgrade).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
test_fp8_temp_accumulation_across_layers with quantized_model_init leaks
~0.68 MiB/layer for DelayedScaling/Float8CurrentScaling on ROCm: FSDP2's
FSDPParam retains the all-gathered Float8Tensor reconstructed in the native
fsdp_post_all_gather instead of freeing it on reshard (verified: the count
of live reconstructed tensors grows unboundedly).

This is FSDP2's unsharded-param free path for custom tensor subclasses, not
the TE weight workspace -- skipping the workspace save was implemented and
confirmed to have no effect. no_quant_init, sync/async DCP, and CUDA are
unaffected. xfail is a temporary placeholder pending a proper fix.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
test_cpu_offloading_v1.py (multihead_attention, transformer_layer) failed with
"ROCm fused attention: unsupported output/grad format" at NVTE_CPU_OFFLOAD_V1=1.

When an interleaved QKV tensor is CPU-offloaded and reloaded, it comes back
de-interleaved, so the backward sets ctx.qkv_layout to the de-interleaved
reload layout (e.g. sbhd_sbhd_sbhd) while ctx.dqkv_layout stayed at the original
interleaved layout (e.g. sb3hd). The ROCm fused-attn kernel uses a single
qkv_layout for both inputs and gradients (it does not honor a separate
dqkv_layout), so the nvte_fused_attn_bwd guard rejected the mismatch.

On ROCm, make the grad layout follow the (possibly de-interleaved) input layout
for the offload-reload case, matching pre-v2.17 behavior. Scoped to
IS_HIP_EXTENSION and the reload path, so CUDA, non-offload, and MXFP8 layout
handling are unchanged.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
test_dpa_qkv_layout_thd[pad_between_seqs=True] failed with "No dot product
attention backend is available" on ROCm. The test force-sets
flash_attn_supported=True for the pad_between_seqs case (relying on
_run_dot_product_attention to manually pad/unpad for the FlashAttention leg),
but on ROCm the FlashAttention backend is disabled for THD with padding between
sequences: flash-attn 2 cannot handle it and flash-attn 3 is not available.
Forcing that leg left no usable backend and raised instead of comparing.

Gate the override with `not IS_HIP_EXTENSION`. FusedAttention (CK) supports this
case on ROCm, so the test now compares the backends that actually run. CUDA
behavior is unchanged.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
The NVFP4 global encode scale hardcoded E4M3_MAX=448, but on fnuz archs
(gfx942, maxNorm=240) the fp8 e4m3 scale storage and the dequant factor
(fixed in 4e94fd7) use 240, so the encode scale was off by ~448/240,
shifting quantized fp4 codes and failing the nvfp4 exact tests on gfx942.
Use the arch-native fp8e4m3 max on HIP device compilation, mirroring the
dequant fix. gfx950 (OCP, 448) is unchanged; CUDA path unchanged.

NOTE: pending validation on gfx942 (rebuild + nvfp4 exact tests).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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