fix(tensilelite): Fix sia bug (#8937)

## Motivation
[AIHPBLAS-830]
JIRA ID: https://amd-hub.atlassian.net/browse/AIHPBLAS-830
Fix a bug from
4068136#diff-be3579e876404146e15d81d6dd89c962c5632c8ebfff2c58c088ec6f11bf20a2

## Technical Details

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## Test Plan

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## Test Result

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## Submission Checklist

- [x] Look over the contributing guidelines at
https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.


[AIHPBLAS-830]:
https://amd-hub.atlassian.net/browse/AIHPBLAS-830?atlOrigin=eyJpIjoiNWRkNTljNzYxNjVmNDY3MDlhMDU5Y2ZhYzA5YTRkZjUiLCJwIjoiZ2l0aHViLWNvbS1KU1cifQ

Author: hcman2

projects/hipblaslt/tensilelite/Tensile/KernelWriter.py

@@ -6896,7 +6896,7 @@ def initSubTileInfo(tc):
           and kernel["PrefetchGlobalRead"]
       self.states.scheduleLocalWrite = kernel["ScheduleLocalWrite"] \
           and kernel["PrefetchGlobalRead"]
-      self.states.scheduleIterAlg = kernel["ScheduleIterAlg"]
+      self.states.scheduleIterAlg = kernel["_ScheduleIterAlg"]
     else:
       self.states.scheduleGlobalRead = 0
       self.states.scheduleLocalWrite = 0