[hipDNN][SDPA] CSV-driven multi-kernel dispatch for SDPA backward (ALMIOPEN-1824)

[DarylHawkinsAMD]

Summary

Replaces the hard-coded SDPA backward POC kernel selection in asm_sdpa_engine with
a runtime, CSV-driven dispatch that mirrors the forward path. The plan builder now
resolves a kernel for each backward stage (odo, dqdkdv, dq_convert) from
AITER-derived registries, and the plan consumes per-stage tile sizes instead of three
hard-coded constants. Day-one gate is pinned to the verified gfx942 / bf16 / hd128 /
A32 / NO_MASK matrix; every other axis is explicitly rejected for follow-up tasks
to lift one at a time.

Reviewer note: filter out .csv and .co files in the GitHub "Files changed" view
to see only relevant code, build, and documentation changes.

Risk Assessment

Medium (3). Core SDPA bwd dispatch is rewritten and a CSV-to-header generator path
is added to the build, but isApplicable rejects every configuration outside the
verified hd128/bf16 baseline, so observable bwd behavior is unchanged on shipping
configs. Largest residual risks are the forward-path drive-by fix (silent
registry-lookup fall-through, now propagated) and the local bwd_hd128_odo_bf16.co
override vs. the AITER snapshot, both documented inline.

Testing Summary

• Unit coverage for the new dispatch: registry lookup, isApplicable rejection
  matrix, and tile / grid math.
• End-to-end correctness on the verified hd128/bf16 backward path against the
  in-tree CPU reference.
• Lint/format gates clean (clang-tidy, pre-commit, ninja format).

Testing Checklist

• TestSdpaBwdPlanBuilder — registry lookup + isApplicable rejection (gfx950,
  FP8, asymmetric hdim, hd64, FP16, hd192, fractional GQA, non-NO_MASK) +
  parameterised pssk/pddv — Status: Passed
• TestSdpaBwdPlanGridMath — pins POC hd128/bf16/seqlen=2048 grid dims to the
  values the deleted K_TS_* constants produced; KernelTiles ceil-div edges —
  Status: Passed
• hd128/bf16 SDPA backward correctness test — ASICs: gfx942 — Status: Passed
• hd128/bf16 backward integration smoke (regression baseline) —
  ASICs: gfx942 — Status: Passed
• pre-commit run --all-files — Status: Passed
• ninja format + clang-tidy (braces, switch-default, identifier-naming) —
  Status: Passed
• PR CI — GitHub PR checks — Status: Pending

Technical Changes

• Kernel snapshot & build wiring — Snapshot fmha_v3_bwd CSVs and .co from
  AITER (9522048dc10de20ba9dcda1c0a3f640867e7a586) into
  asm_kernels/{gfx942,gfx950}/fmha_v3_bwd/ using AITER's flat layout (no MI300
  split for bwd). Three CSVs per arch (odo, dqdkdv, dq_convert); empty
  dq_shuffle.csv omitted. Per-arch SOURCE.md records source URL, commit, and
  SHA256 manifest. CMake invokes the existing CSV-to-header generator a second time
  to produce asm_fmha_v3_bwd_configs.hpp.
• Tile-size plumbing — SdpaBwdParams gains a KernelTiles struct with a
  constexpr gridDim(extent) ceil-div helper that returns 0 when ts == 0 (so unit
  tests can exercise the unpopulated case), plus odoTiles / dqdkdvTiles /
  dqConvertTiles fields. SdpaBwdPlan.cpp deletes K_TS_ODO / K_TS_KV /
  K_TS_DQ, routes grid-x at each stage through _params.<stage>Tiles.gridDim(...),
  and passes the dqdkdv KV-tile to buildDqdkdvArgs /
  validateMhaBwdByteStrides explicitly. MhaBwdArgs stays a line-for-line mirror
  of AITER's mha_bwd_args (no added fields).
• Dispatch (SdpaBwdPlanBuilder) — Backward-local enums and helpers ported from
  forward (getMaskType, getRoundingMode, getBatchMode, getDataTypeIdentifier,
  lookupKernelNameKey). getKernelCoPath uses the flat layout and does not
  consult isMi308Device(). A single BwdDispatchTuple is computed once and
  consumed by both isApplicable and buildPlan so per-stage tuples cannot drift;
  resolveStage returns std::optional<ResolvedKernel>. Includes the gfx950 BF16
  bf16_cvt special case to match forward.
• Day-one accepted matrix — isApplicable accepts gfx942 / batch / atomic32 /
  pssk=1 / pddv=1 / square hdim / NO_MASK only. hd128/bf16 is the verified path;
  hd192 and FP16 are reachable through registry walk and tile plumbing but gated off
  until the in-tree CPU reference is calibrated (ALMIOPEN-1832). gfx950, group mode,
  FP8, fractional GQA, non-square hdim, and other masks are explicitly rejected with
  a clear log line keyed to the relevant follow-up task (ALMIOPEN-1825 /
  ALMIOPEN-1826 / ALMIOPEN-1827 / ALMIOPEN-1833).
• Correctness hardening (PR-review pass) — Zero-init dq_acc before A32 dqdkdv
  (matches AITER's torch::zeros; without this, dQ silently corrupts when
  seq_kv > ts*2). Reject uint32 byte-stride overflow on every Q/K/V/O/dO/dQ/dK/dV/
  lse/dq_acc field (was log-and-continue). hipPeekAtLastError + gridX > 0
  precheck on every launch. tensorMap.at lookups in isApplicable wrapped in
  find() + return-false. static_assert(offsetof) on load-bearing kernarg fields.
  A16 path modeled as dormant-but-correct (skip dq_convert and dq_acc when
  resolved atomic32 == 0); day-one gate stays pinned to A32.
  initializeExecutionSettings throws std::logic_error instead of emitting a
  spurious LOG_ERROR on every engine instantiation.
• Local override — bwd_hd128_odo_bf16.co is the develop POC binary (10280 B),
  not the AITER snapshot (9344 B). AITER's version produced D-aux values that
  diverged from the in-tree CPU reference enough to fail the existing hd128/bf16
  correctness test. Documented in SOURCE.md so future AITER refreshes know to keep
  the override or coordinate a tolerance / reference update.

Out of scope (handed off to sibling tasks)

Workspace sizing for A16 vs A32 (ALMIOPEN-1825),
causal-mask end-to-end correctness (ALMIOPEN-1826),
CPU-reference calibration for hd192/FP16 (ALMIOPEN-1832),
grid-formula full coverage including split-K (ALMIOPEN-1827),
gfx950 enablement (ALMIOPEN-1833),
automated AITER sync / binary versioning (ALMIOPEN-1828).