feat(ck-tile): batched-contraction GEMM TE to dispatcher bridge#9328
feat(ck-tile): batched-contraction GEMM TE to dispatcher bridge#9328ozturkosu wants to merge 8 commits into
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Add a Python/ctypes TileEngine -> Dispatcher bridge for the batched_contraction op
so the dispatcher can codegen, build, and launch batched tensor contraction
(E[G..,M..,N..] = sum_K A[G..,M..,K..] * B[G..,N..,K..]) at parity with Old-TE,
following the direct-launch (registry-bypass) pattern of the batched/multi-D bridges.
New:
- dispatcher/codegen/unified_batched_contraction_codegen.py (self-contained kernel
header generator; make_batched_contraction_kernel_name is the single name source)
- dispatcher/bindings/ctypes/batched_contraction_ctypes_lib.cpp (flat C ABI; builds
ck_tile::BatchedContractionHostArgs from C arrays; packed row-major strides; direct
SelectedKernel::launch; warmup/repeat timing)
- dispatcher/python/batched_contraction_utils.py (KernelConfig with byte-exact .name,
Problem, DispatcherLib, GpuRunner, setup_multiple_*, expand_sweep)
- dispatcher/tests/test_batched_contraction_bridge.py (CPU-only unit tests)
- tile_engine/ops/gemm/batched_contraction_full_benchmark.py + run_one_batched_contraction_kernel.py
- tile_engine/ops/gemm/batched_contraction/configs/bridge_default*.json
- dispatcher/bindings/ctypes/BATCHED_CONTRACTION_BRIDGE.md
Modified:
- dispatcher/bindings/ctypes/CMakeLists.txt (dispatcher_batched_contraction_lib target)
v1 scope: dtype {fp16,bf16,fp32}, layout rcr, num_dim_g/m/n/k, num_d_tensors=0,
k_batch=1. GPU-verified on gfx950 (fp16/bf16/fp32, multi-dim g/m/n/k, compv3/compv4/mem)
at max_rel <= ~4e-3 vs fp32 reference.
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A/B performance-parity vs Old Tile-Engine — at parityArch: gfx950 / MI350X. Both sides built + run on the same node/container/toolchain ( fp16,
Distribution (n=10): median -0.95%, mean -0.13%, range [-4.41%, +6.29%], 100% within ±15%, 90% within ±5%. Zero rows exceeded ±15% (no re-measure triggered). Correctness verified vs fp32 einsum every row (rel_err 2.6e-4–4.0e-4). Verdict: at parity — the bridge matches Old-TE |
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Pull request overview
This PR adds a TileEngine → Dispatcher “bridge” for batched_contraction GEMM, enabling codegen → per-kernel shared library build → C ABI launch → Python utilities/benchmarking, matching the existing direct-launch / registry-bypass bridge pattern used by other CK Tile GEMM variants.
Changes:
- Introduces a new batched-contraction kernel header codegen path and a dedicated ctypes C ABI for direct kernel launch.
- Adds Python utilities (config/problem/runner/build pipeline) plus a TE-side 3-phase benchmark driver + per-GPU worker.
- Adds CPU-only unit tests and default/CI sweep configs, plus bridge documentation.
Reviewed changes
Copilot reviewed 10 out of 10 changed files in this pull request and generated 4 comments.
Show a summary per file
| File | Description |
|---|---|
| projects/composablekernel/tile_engine/ops/gemm/run_one_batched_contraction_kernel.py | Per-GPU worker that loads a single kernel .so, runs it, and optionally verifies vs NumPy fp32 reference. |
| projects/composablekernel/tile_engine/ops/gemm/batched_contraction/configs/bridge_default_config.json | Default sweep config for bridge-side kernel expansion (fp16 warp-tile set). |
| projects/composablekernel/tile_engine/ops/gemm/batched_contraction/configs/bridge_default_ci_config.json | Minimal CI sweep config intended to build at least one validated kernel. |
| projects/composablekernel/tile_engine/ops/gemm/batched_contraction_full_benchmark.py | 3-phase driver (expand → build → per-kernel per-GPU worker) for benchmarking and optional verification. |
| projects/composablekernel/dispatcher/tests/test_batched_contraction_bridge.py | CPU-only tests for name contract, codegen JSON projection, problem flops, and sweep behavior. |
| projects/composablekernel/dispatcher/python/batched_contraction_utils.py | Python config + runner + ctypes wrapper + codegen/hipcc build pipeline + sweep expansion. |
| projects/composablekernel/dispatcher/codegen/unified_batched_contraction_codegen.py | Generates one .hpp per config with SelectedKernel::launch(...) for batched contraction. |
| projects/composablekernel/dispatcher/bindings/ctypes/CMakeLists.txt | Adds a dispatcher_batched_contraction_lib target that force-includes a generated kernel header. |
| projects/composablekernel/dispatcher/bindings/ctypes/batched_contraction_ctypes_lib.cpp | Flat C ABI that marshals dim arrays → BatchedContractionHostArgs and direct-launches SelectedKernel. |
| projects/composablekernel/dispatcher/bindings/ctypes/BATCHED_CONTRACTION_BRIDGE.md | Design/usage documentation for the bridge and its ABI. |
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🔎 Automated parity review — Round 1 (batched_contraction bridge vs Old-TE)Reviewed working tree at HEAD VerdictAt parity for the committed v1 scope (fp16/bf16/fp32 × rcr × num_dim g/m/n/k × num_d=0 × k_batch=1). Row-major stride packing, ColumnMajor-B tag handling, and the shared Parity gaps vs Old-TE's real (compilable) set
Code correctness findings
Test coverage gaps
Requested changes for Round 2
|
… split-K determination Round-2 review fixes for the batched_contraction TE->Dispatcher bridge: num_d_tensors > 0 (MultiDAdd / MultiDMultiply), end-to-end: - is_valid() accepts num_d 0..8 and enforces num_d<->elementwise consistency (num_d==0 => PassThrough; num_d>0 => MultiDAdd/MultiDMultiply). - GpuBatchedContractionRunner.run() now constructs the Ds device buffers (shape==E [G,M,N], dtype==A/B, values in [-1,1] mirroring Old-TE's profiler) and marshals them through the ctypes run(); returns the Ds it used. - reference() applies the D epilogue in fp32 (C+D0+D1... for MultiDAdd, C*D0*D1... for MultiDMultiply) matching ck_tile::element_wise::MultiD* and reference_batched_contraction.hpp; plain contraction only when num_d==0. - run_one worker threads num_d/elementwise through and verifies with the same Ds. - ctypes lib: fix latent D byte-sizing (was sizeof(ADataType)) to key off the codegen DBaseDataType typedef; codegen now re-exports DBaseDataType under CK_TILE_SINGLE_KERNEL_INCLUDE. split-K (k_batch>1): determined to be a SHARED Old-TE kernel defect, not a bridge gap. The batched-contraction CShuffle epilogue is hard-wired to memory_operation_enum::set (no atomic accumulation) while GridSize launches k_batch blockIdx.z K-split blocks writing the same E tile; driving the exact Old-TE kernel at k_batch=2 faults with an illegal memory access on gfx950 (k_batch=1 correct, max_rel ~4e-4). Kept the hard-reject and documented it. Tests: add num_d>0 name/codegen-projection round-trip and validity-rejection tests (non-rcr layout, bad dtype, bad warp-tile, num_d range, num_d/elementwise consistency). 23/23 pass. GPU-verified on gfx950 vs fp32 reference: num_d=1 MultiDAdd max_rel 7.14e-4, num_d=2 MultiDAdd 7.07e-4, num_d=1 MultiDMultiply 8.18e-4, num_d=0 3.06e-4.
…er job Phase-3 worker job dict in batched_contraction_full_benchmark.py omitted num_d_tensors and elementwise, so configs with num_d_tensors>0 were swept with the default PassThrough reference op. Thread both keys from the kernel config (defaulting to 0 / PassThrough) to mirror the direct worker path.
✅ Automated parity review — Round 2 verdict: AT PARITYRound-1 requested changes implemented and independently verified (local commits Verified fixes
Out-of-scope exclusions (verified genuine, under "match Old-TE's real compilable set")
Remaining parity gaps vs Old-TE's compilable set: none.Verdict: full functional parity reached. Proceeding to the apples-to-apples A/B interleaved timing parity check on gfx950 (warmup50/repeat100 both sides, stale-.so guard, fresh rebuild) — results to follow. |
📊 A/B interleaved timing parity — gfx950/MI350 — VERDICT: AT PARITYApples-to-apples bridge-vs-Old-TE sweep on local gfx950, fresh build from HEAD Result: bridge is equal-or-faster on every measured row.
Fairness (all enforced): warmup=50/repeat=100 both sides; identical measurement mode (CPU timer, hot cache, no rotation) on both; Old-TE built via CK's own CMake with real TE codegen flags; stale-.so guard; interleaved A/B per (stem,shape) median-of-5, outlier remeasured standalone; matched tile configs (no coverage asymmetry). Scope: fp16/bf16/fp32 × rcr × num_d=0 × k_batch=1 (Old-TE's compilable surface), 6 stems × 6 shapes = 36 rows. Combined with the Round-2 functional verdict (num_d>0 D-tensor epilogue GPU-verified, non-rcr & split-K genuinely out-of-scope), PR #9328 is at full functional + timing parity with Old-TE. |
…um_d>0 + split-K reject The bridge MD still described num_d_tensors>0 as a follow-up and split-K as merely 'not yet numerically correct'. The shipped code supports the D-tensor epilogue (num_d 0..8, MultiDAdd/MultiDMultiply) end-to-end and hard-rejects split-K as a shared Old-TE kernel defect. Update Coverage, the C-ABI note, and add a num_d>0 codegen example so the docs match is_valid()/reference()/the ABI.
Round-1 fixes pushed — D-tensor epilogue now on the remote (
|
| case | max_rel | neg-control (with-D ref vs plain-C) |
|---|---|---|
| num_d=0 PassThrough | 3.36e-4 | — |
| num_d=1 MultiDAdd | 6.46e-4 | 4.30e-2 (differs) |
| num_d=2 MultiDAdd | 6.31e-4 | 8.58e-2 (differs) |
| num_d=1 MultiDMultiply | 5.41e-4 | 1.82 (differs) |
Negative controls confirm the D epilogue is applied on-device. clang-format-18 clean; CI
re-triggered and green.
… validate dims, fix CMake stub, copy-back E, encode k_block_per_cu in name
|
Addressed all 5 unresolved review threads in commit 5789b65.
Verified: |
Note on compilation after 5789b65 (arch is now required, no gfx942 default)Following the "don't default to gfx942; use get_arch and throw for unsupported arch" fix, the GPU architecture must now be provided explicitly at compile time — the bridge no longer silently assumes What changed
How to build now
CI note: on no-GPU nodes there is no Verified on MI355 (gfx950, ROCm 7.2): building with the arch passed produces a working |
Co-authored-by: Copilot Autofix powered by AI <175728472+Copilot@users.noreply.github.com>
…elementwise, fix doc ABI signature Addresses two open Copilot review findings: - codegen: BCHeaderGenerator.generate() now explicitly rejects unsupported `epilogue` (must be cshuffle|default) and `elementwise` (must be a key of ELEMENTWISE_TO_CK) values with a clear ValueError, matching the existing dtype/layout/pipeline validation. Previously a typo silently fell through to PassThrough / DefaultGemm2DEpilogue, producing a kernel whose behavior did not match its config/name. Also drops the now-dead .get(...) fallback. - BATCHED_CONTRACTION_BRIDGE.md: the documented C ABI block omitted the `const void** d_ptrs, int num_d` parameters that the real exported function takes right after E, so a reader could not call the ABI for num_d>0. Signature now matches batched_contraction_ctypes_lib.cpp.
July21 review feedback — all 5 threads satisfiedThe July21 review batch (archived as
Separately, the 3 remaining open threads from the latest session — all-zeros verify guard, codegen All 8 review threads on PR #9328 are now addressed. |
Whole-config perf parity — batched_contraction bridge vs Old Tile-Engine (MI300X / gfx942)Ran the comprehensive v1 config-space (not just a shape sweep): Verdict: AT PARITY (bridge equal-or-faster).
gap = (bridge − old)/old × 100 (+ = bridge faster). Shapes: g1·1024³, g1·2048³, g4·512³. Per-op: PassThrough −1.89 %, MultiDAdd −0.11 %, MultiDMultiply −0.75 %. Per-num_d: 0/1/2 = compv4 note: the compv4 bucket is consistently bridge-faster (+11 … +17 %) — a bridge Coverage: bridge=130 .so and Old-TE=130 binaries (5 op/num_d builds × 26), 130 fair Correctness: bf16 fp32-verified (global metric max|Δ|/max|ref|) before timing. Out of scope (correctly): non-rcr layouts (col-major static_asserts, don't compile), Fairness: 50/100 warmup/repeat + flush + identical rotating both sides; Old-TE from its own |
## Summary Adds a microscaling-GEMM (`mx_gemm`) bridge from the Old Tile-Engine into the dispatcher's ctypes path for gfx950/MI350. Supports **fp4** (`pk_fp4_t`, e2m1) and **fp8** (e4m3), **rcr** layout, `comp_async` + `cshuffle` + `intrawave`, fixed `16x16x128` warp tile, `k_batch == 1`. Per-32-K `e8m0` block scales are pre-shuffled on-host exactly as the Old-TE profiler does. ## Motivation Extend the TE→Dispatcher bridge family to the microscaling GEMM op so the dispatcher can launch byte-identical `mx_gemm` kernels with block scaling. Sibling to the other bridge PRs (see below). ## Design note - **Byte-exact kernels:** the codegen reuses Old-TE `MxGemmKernelBuilder._generate_kernel_instance` directly rather than re-implementing header assembly, guaranteeing the emitted kernel matches Old-TE. It only strips the stale `ck_tile/ops/gemm_mx.hpp` umbrella include (absent on develop; the mx pipeline is pulled in via `ck_tile/ops/gemm.hpp`). - **Registry bypass:** `mx_gemm`'s `launch` takes `ck_tile::MxGemmHostArgs` with per-32-K `e8m0` scales that the generic dispatcher backend cannot express, so the ctypes lib builds `MxGemmHostArgs` from plain C arrays and calls `SelectedKernel::launch()` directly — the same direct-launch pattern as the batched/multi-D bridges. - **Scale pre-shuffle** mirrors `mx_gemm_profiler.hpp`; pack params are derived from `SelectedKernel` tile dims at compile time (not hardcoded). - **Packing-correct byte accounting:** device buffers are sized via `HostTensor::get_element_space_size_in_bytes()`, which divides by `numeric_traits<T>::PackedSize`, so fp4 (`PackedSize==2`, two e2m1 per byte) and fp8 (`PackedSize==1`) are both correct. ## Verification - fp8 derisk: PASS (`max_rel = 0.0`, kernel-name match, output fully non-zero) on gfx950 - fp4: GPU-verified on gfx950 - `clang-format-18 -style=file` clean; Python `py_compile` clean ## Sibling PRs - #8997 — TE→dispatcher GEMM bridge (fp16/bf16, all layouts) — foundational (merged) - #8998 — fp8/bf8/int8 bridge (merged) - #9000 — grouped GEMM - #9028 — stream-K GEMM - #9305 — multi-ABD GEMM - #9306 — batched GEMM - #9307 — preshuffle GEMM - #9308 — multi-D GEMM - #9328 — batched-contraction GEMM --------- Co-authored-by: Muhammed Emin Ozturk <3836908+ozturkosu@users.noreply.github.com>
gfx942 (MI300X) verification — AT PARITY + full functional equivalenceVerified on ctr-cx64-mi300x-4, gfx942, ROCm 7.2 native, PR HEAD A/B performance parity (fair, interleaved)Matched set: fp16 / bf16 / fp32 × rcr × num_d=0 × k_batch=1, 6 shapes each = 18 rows.
Correctness (fp32 einsum ref, global max|Δ|/max|ref|): fp16 ~3e-4, bf16 ~6e-3, fp32 ~1e-6 — all PASS. Fairness (all enforced): warmup=50 / repeat=100, GPU timer + flush_cache=true + rotating_count=1000 on both sides (bridge ctypes Functional equivalence vs Old-TE gfx942 support surfaceOld-TE surface (instance-builder argparse): datatype {fp16,bf16,fp32}, 3-char a/b/e layout, num_dim_g/m/n/k, num_d_tensors, elementwise {PassThrough,Add,Mul}. Bridge build+run+correct on gfx942 for:
The bridge covers Old-TE's entire gfx942-compilable support surface; no Old-TE-buildable config is missing from the bridge. (Note: the fair-timing |
…bridge_batched_contraction # Conflicts: # projects/composablekernel/dispatcher/bindings/ctypes/CMakeLists.txt
Conflict-proofing update (merged develop, resolved CMakeLists conflict)Merged What changed here (append-only identical-superset strategy):
Why: so that after ANY sibling bridge PR merges to develop, the others do not re-conflict on the shared CMakeLists. Validated: the branch's tests pass (40 tests incl. |
ISSUE ID: #8997
Motivation
The TileEngine → Dispatcher bridge could generate and launch regular/batched/grouped
GEMM, but had no path for the batched_contraction op — a generalized batched tensor
contraction
E[G.., M.., N..] = sum_K A[G.., M.., K..] * B[G.., N.., K..]withindependent multi-dimensional G/M/N/K index groups. This is a real Old-TE capability
with no dispatcher equivalent, so this PR adds a complete bridge (codegen → C ABI →
Python) so callers can generate, build, and launch batched contraction at parity with
the legacy Tile Engine version, without writing any C++.
It follows the direct-launch, registry-bypass pattern used by the batched (#9306)
and multi-D (#9308) bridges, because batched contraction's launch takes
ck_tile::BatchedContractionHostArgs<NumDTensor>with variable-length dim/stridevectors that the single-pointer registry backend cannot express.
Test Plan
python3 -m pytest dispatcher/tests/test_batched_contraction_bridge.py -vTest Result
sweep dedup, num_d>0 round-trip, and validity-rejection tests for non-rcr layout, bad
dtype, bad warp-tile, num_d range, and num_d<->elementwise consistency).
max_rel 4.8e-4, bf163.9e-3, fp329e-5— all PASS.num_dim_g=2 [2,3],num_dim_m=2/num_dim_k=2 [4,16],num_dim_n=2 [8,16]— all PASS.max_rel 7.14e-4, num_d=2 MultiDAdd7.07e-4, num_d=1 MultiDMultiply8.18e-4vs a with-D fp32 reference (negative control:with-D ref vs plain-C differs ~4e-2, confirming the epilogue is on-device) — all PASS.
KERNEL_NAME(byte-exact).batched_contraction_ctypes_lib.cpp.Scope / known limitations (documented in the bridge MD)
rcronly. Column-major A/B (rrr/ccr/crr) trip kernelstatic_assertsand do not compile in Old-TE either; gated off in
is_valid().fp16/bf16/fp32— exact match to Old-TE argparse; gated inis_valid()against the dtype→MFMA-warp-tile allow-list.
num_d_tensors0..8.num_d==0= plain contraction (PassThrough);num_d>0runs the D-tensor epilogue (
MultiDAdd/MultiDMultiply), matching Old-TE'sreference_batched_contraction.hpp. Gated + verified (see above).k_batch == 1only. Split-K (k_batch>1) is a shared Old-TE kernel defect (theCShuffle epilogue is hard-wired to
memory_operation_enum::setwhilek_batchz-splitblocks race the same E tile with no atomic → illegal memory access at
k_batch=2even inOld-TE). Hard-rejected by the ABI (returns -1, never silently-wrong) — out of scope.
IsSupportedArguments(rc=-2).Performance parity
Serialized A/B perf-parity vs Old-TE
batched_contraction(gfx950 / MI350X, fp16 rcr,2 tile configs × 5 shapes = 10 rows, interleaved, fair 50/100/flush/rotating both sides):
at parity — median gap -0.95%, mean -0.13%, 100% within ±15%, 90% within ±5%
(range [-4.41%, +6.29%]; + = bridge faster). See the parity comment for the per-row table.
Related PRs / references (TileEngine → Dispatcher GEMM bridge series): #8997 (regular GEMM), #9000 (grouped), #9028 (stream-K), #8887 (fp8/bf8/int8), #9305 (multi-ABD), #9306 (batched), #9307 (preshuffle), #9308 (multi-D). This PR is a sibling in the same bridge effort.