diff --git a/libraries/HAL_Drivers/SConscript b/libraries/HAL_Drivers/SConscript
index f3c8da1c..08701ff9 100644
--- a/libraries/HAL_Drivers/SConscript
+++ b/libraries/HAL_Drivers/SConscript
@@ -27,7 +27,7 @@ if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']):
         src += ['drv_soft_i2c.c']
 
 if GetDepend(['RT_USING_I2C']):
-    if GetDepend('BSP_USING_HW_I2C0') or GetDepend('BSP_USING_HW_I2C4') or GetDepend('BSP_USING_HW_I2C6'):
+    if GetDepend('BSP_USING_HW_I2C0') or GetDepend('BSP_USING_HW_I2C3') or GetDepend('BSP_USING_HW_I2C4') or GetDepend('BSP_USING_HW_I2C5') or GetDepend('BSP_USING_HW_I2C6') or GetDepend('BSP_USING_HW_I2C8'):
         src += ['drv_i2c.c']
 
 if GetDepend(['BSP_USING_SDIO1']):
diff --git a/libraries/HAL_Drivers/drv_i2c.c b/libraries/HAL_Drivers/drv_i2c.c
index 62cb4b7e..94d972a4 100644
--- a/libraries/HAL_Drivers/drv_i2c.c
+++ b/libraries/HAL_Drivers/drv_i2c.c
@@ -11,9 +11,24 @@
 #include "board.h"
 
 #if defined(RT_USING_I2C)
-#if defined(BSP_USING_HW_I2C0) || defined(BSP_USING_HW_I2C3) || defined(BSP_USING_HW_I2C4) || defined(BSP_USING_HW_I2C6)
 #include <rtdevice.h>
 
+#include "cy_scb_i2c.h"
+#include "mtb_hal_i2c.h"
+
+#ifdef BSP_USING_HW_I2C0
+extern const cy_stc_scb_i2c_config_t CYBSP_I2C_CONTROLLER_config;
+extern const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config;
+#endif
+#ifdef BSP_USING_HW_I2C5
+extern const cy_stc_scb_i2c_config_t CYBSP_I2C5_CONTROLLER_config;
+extern const mtb_hal_i2c_configurator_t CYBSP_I2C5_CONTROLLER_hal_config;
+#endif
+#ifdef BSP_USING_HW_I2C8
+extern const cy_stc_scb_i2c_config_t scb_8_config;
+extern const mtb_hal_i2c_configurator_t scb_8_hal_config;
+#endif
+
 #ifndef I2C0_CONFIG
 #define I2C0_CONFIG                                                     \
     {                                                                   \
@@ -24,20 +39,68 @@
     }
 #endif /* I2C0_CONFIG */
 
-#endif
+#ifndef I2C3_CONFIG
+#define I2C3_CONFIG                              \
+    {                                            \
+        .name = "i2c3",                        \
+        .base = SCB3,                           \
+        .cy_stc_scb_i2c_config = RT_NULL,       \
+        .mtb_hal_i2c_configurator = RT_NULL,    \
+    }
+#endif /* I2C3_CONFIG */
+
+#ifndef I2C4_CONFIG
+#define I2C4_CONFIG                              \
+    {                                            \
+        .name = "i2c4",                        \
+        .base = SCB4,                           \
+        .cy_stc_scb_i2c_config = RT_NULL,       \
+        .mtb_hal_i2c_configurator = RT_NULL,    \
+    }
+#endif /* I2C4_CONFIG */
+
+#ifndef I2C5_CONFIG
+#define I2C5_CONFIG                                                     \
+    {                                                                   \
+        .name = "i2c5",                                               \
+        .base = SCB5,                                                   \
+        .cy_stc_scb_i2c_config = &CYBSP_I2C5_CONTROLLER_config,         \
+        .mtb_hal_i2c_configurator = &CYBSP_I2C5_CONTROLLER_hal_config,  \
+    }
+#endif /* I2C5_CONFIG */
+
+#ifndef I2C6_CONFIG
+#define I2C6_CONFIG                              \
+    {                                            \
+        .name = "i2c6",                        \
+        .base = SCB6,                           \
+        .cy_stc_scb_i2c_config = RT_NULL,       \
+        .mtb_hal_i2c_configurator = RT_NULL,    \
+    }
+#endif /* I2C6_CONFIG */
+
+#ifndef I2C8_CONFIG
+#define I2C8_CONFIG                                  \
+    {                                                \
+        .name = "i2c8",                            \
+        .base = SCB8,                                \
+        .cy_stc_scb_i2c_config = &scb_8_config,      \
+        .mtb_hal_i2c_configurator = &scb_8_hal_config, \
+    }
+#endif /* I2C8_CONFIG */
 
 struct ifx_i2c
 {
-    mtb_hal_i2c_t *mtb_hal_i2c;
-    char *name;
+    const char *name;
     CySCB_Type *base;
     const cy_stc_scb_i2c_config_t *cy_stc_scb_i2c_config;
     const mtb_hal_i2c_configurator_t *mtb_hal_i2c_configurator;
-    cy_stc_scb_i2c_context_t *context;
+    mtb_hal_i2c_t hal_obj;
+    cy_stc_scb_i2c_context_t context;
     struct rt_i2c_bus_device i2c_bus;
 };
 
-static struct ifx_i2c ifx_i2c[] =
+static struct ifx_i2c i2c_objs[] =
 {
 #ifdef BSP_USING_HW_I2C0
     I2C0_CONFIG,
@@ -51,16 +114,24 @@ static struct ifx_i2c ifx_i2c[] =
     I2C4_CONFIG,
 #endif
 
+#ifdef BSP_USING_HW_I2C5
+    I2C5_CONFIG,
+#endif
+
 #ifdef BSP_USING_HW_I2C6
     I2C6_CONFIG,
 #endif
+
+#ifdef BSP_USING_HW_I2C8
+    I2C8_CONFIG,
+#endif
 };
 
-static struct ifx_i2c i2c_objs[sizeof(ifx_i2c) / sizeof(struct ifx_i2c)] = {0};
+#define I2C_BUS_NUM (sizeof(i2c_objs) / sizeof(i2c_objs[0]))
 
 static int ifx_i2c_read(struct ifx_i2c *hi2c, rt_uint16_t slave_address, rt_uint8_t *p_buffer, rt_uint16_t data_byte)
 {
-    if (mtb_hal_i2c_controller_read(hi2c->mtb_hal_i2c, slave_address, p_buffer, data_byte, 10, true) != RT_EOK)
+    if (mtb_hal_i2c_controller_read(&hi2c->hal_obj, slave_address, p_buffer, data_byte, 10, true) != CY_RSLT_SUCCESS)
     {
         return -RT_ERROR;
     }
@@ -70,7 +141,7 @@ static int ifx_i2c_read(struct ifx_i2c *hi2c, rt_uint16_t slave_address, rt_uint
 
 static int ifx_i2c_write(struct ifx_i2c *hi2c, uint16_t slave_address, uint8_t *p_buffer, uint16_t data_byte)
 {
-    if (mtb_hal_i2c_controller_write(hi2c->mtb_hal_i2c, slave_address, p_buffer, data_byte, 10, true) != RT_EOK)
+    if (mtb_hal_i2c_controller_write(&hi2c->hal_obj, slave_address, p_buffer, data_byte, 10, true) != CY_RSLT_SUCCESS)
     {
         return -RT_ERROR;
     }
@@ -121,33 +192,35 @@ static const struct rt_i2c_bus_device_ops i2c_ops =
     RT_NULL
 };
 
-void HAL_I2C_Init(struct ifx_i2c *obj)
+static rt_err_t ifx_i2c_hw_init(struct ifx_i2c *obj)
 {
     RT_ASSERT(obj != RT_NULL);
-    RT_ASSERT(obj->mtb_hal_i2c != RT_NULL);
-    RT_ASSERT(obj->mtb_hal_i2c_configurator != RT_NULL);
-    RT_ASSERT(obj->context != RT_NULL);
+
+    if ((obj->mtb_hal_i2c_configurator == RT_NULL) || (obj->cy_stc_scb_i2c_config == RT_NULL))
+    {
+        rt_kprintf("I2C %s config is missing, skip register\n", obj->name);
+        return -RT_ERROR;
+    }
 
     cy_rslt_t rslt;
     cy_en_scb_i2c_status_t result;
 
-    result = Cy_SCB_I2C_Init(obj->base, obj->cy_stc_scb_i2c_config, obj->context);
+    result = Cy_SCB_I2C_Init(obj->base, obj->cy_stc_scb_i2c_config, &obj->context);
     if (result != CY_SCB_I2C_SUCCESS)
     {
         rt_kprintf("Cy_SCB_I2C_Init failed for %s, code: 0x%08x\n", obj->name, result);
-        return;
+        return -RT_ERROR;
     }
 
     Cy_SCB_I2C_Enable(obj->base);
 
-    rslt = mtb_hal_i2c_setup(obj->mtb_hal_i2c, obj->mtb_hal_i2c_configurator, obj->context, NULL);
+    rslt = mtb_hal_i2c_setup(&obj->hal_obj, obj->mtb_hal_i2c_configurator, &obj->context, NULL);
     if (rslt != CY_RSLT_SUCCESS)
     {
         rt_kprintf("I2C setup failed for %s, code: 0x%08x\n", obj->name, rslt);
-        return;
+        return -RT_ERROR;
     }
 
-    // Define the I2C controller dev_config_struct structure
     mtb_hal_i2c_cfg_t i2c_controller_config =
     {
         MTB_HAL_I2C_MODE_CONTROLLER,
@@ -157,28 +230,30 @@ void HAL_I2C_Init(struct ifx_i2c *obj)
         false,
     };
 
-    rslt = mtb_hal_i2c_configure(obj->mtb_hal_i2c, &i2c_controller_config);
+    rslt = mtb_hal_i2c_configure(&obj->hal_obj, &i2c_controller_config);
     if (rslt != CY_RSLT_SUCCESS)
     {
         rt_kprintf("I2C configure failed for %s, code: 0x%08x\n", obj->name, rslt);
-        return;
+        return -RT_ERROR;
     }
+
+    return RT_EOK;
 }
 
 int rt_hw_i2c_init(void)
 {
     rt_err_t result = RT_EOK;
-    size_t i2c_num = sizeof(ifx_i2c) / sizeof(struct ifx_i2c);
+    size_t i2c_num = I2C_BUS_NUM;
 
     for (size_t i = 0; i < i2c_num; i++)
     {
-        i2c_objs[i] = ifx_i2c[i];
         i2c_objs[i].i2c_bus.ops = &i2c_ops;
-        i2c_objs[i].context = rt_malloc(sizeof(cy_stc_scb_i2c_context_t));
-        RT_ASSERT(i2c_objs[i].context != RT_NULL);
-        i2c_objs[i].mtb_hal_i2c = rt_malloc(sizeof(mtb_hal_i2c_t));
-        RT_ASSERT(i2c_objs[i].mtb_hal_i2c != RT_NULL);
-        HAL_I2C_Init(&i2c_objs[i]);
+
+        if (ifx_i2c_hw_init(&i2c_objs[i]) != RT_EOK)
+        {
+            continue;
+        }
+
         result = rt_i2c_bus_device_register(&i2c_objs[i].i2c_bus, i2c_objs[i].name);
         RT_ASSERT(result == RT_EOK);
     }
diff --git a/libraries/HAL_Drivers/drv_uart.c b/libraries/HAL_Drivers/drv_uart.c
index b0de62cb..0610d416 100644
--- a/libraries/HAL_Drivers/drv_uart.c
+++ b/libraries/HAL_Drivers/drv_uart.c
@@ -64,7 +64,11 @@ static struct ifx_uart_config uart_config[] =
 #endif
 };
 
-static struct ifx_uart uart_obj[sizeof(uart_config) / sizeof(uart_config[0])] = {0};
+#define UART_OBJ_NUM (sizeof(uart_config) / sizeof(uart_config[0]))
+
+static struct ifx_uart uart_obj[UART_OBJ_NUM] = {0};
+static mtb_hal_uart_t uart_hal_obj[UART_OBJ_NUM];
+static cy_stc_scb_uart_context_t uart_hal_context[UART_OBJ_NUM];
 
 static void uart_isr(struct rt_serial_device *serial)
 {
@@ -176,6 +180,8 @@ void uart6_isr_callback(void)
 /*
  * UARTHS interface
  */
+static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg);
+
 static rt_err_t ifx_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
 {
     RT_ASSERT(serial != RT_NULL);
@@ -198,6 +204,11 @@ static rt_err_t ifx_configure(struct rt_serial_device *serial, struct serial_con
 
     RT_ASSERT(result == RT_EOK);
 
+    if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX)
+    {
+        ifx_control(serial, RT_DEVICE_CTRL_SET_INT, (void *)RT_DEVICE_FLAG_INT_RX);
+    }
+
     return RT_EOK;
 }
 
@@ -207,10 +218,13 @@ static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg)
     struct ifx_uart *uart = (struct ifx_uart *)serial->parent.user_data;
     RT_ASSERT(uart != RT_NULL);
 
+    (void)arg;
+
     switch (cmd)
     {
     case RT_DEVICE_CTRL_CLR_INT:
-
+        uart->config->usart_x->INTR_RX_MASK &= ~SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
+        NVIC_DisableIRQ(uart->config->intrSrc);
         break;
 
     case RT_DEVICE_CTRL_SET_INT:
@@ -223,6 +237,25 @@ static rt_err_t ifx_control(struct rt_serial_device *serial, int cmd, void *arg)
         /* Enable the interrupt */
         NVIC_EnableIRQ(uart->config->intrSrc);
         break;
+
+    case RT_DEVICE_CTRL_SUSPEND:
+        if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            uart->config->usart_x->INTR_RX_MASK &= ~SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
+            NVIC_DisableIRQ(uart->config->intrSrc);
+        }
+        break;
+
+    case RT_DEVICE_CTRL_RESUME:
+        if (serial->parent.open_flag & RT_DEVICE_FLAG_INT_RX)
+        {
+            uart->config->usart_x->INTR_RX_MASK = SCB_INTR_RX_MASK_NOT_EMPTY_Msk;
+            NVIC_EnableIRQ(uart->config->intrSrc);
+        }
+        break;
+
+    default:
+        break;
     }
 
     return (RT_EOK);
@@ -280,22 +313,19 @@ const struct rt_uart_ops _uart_ops =
 
 void rt_hw_uart_init(void)
 {
-    int index;
-
-    rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct ifx_uart);
+    rt_size_t index;
     struct serial_configure serial_config = RT_SERIAL_CONFIG_DEFAULT;
     rt_err_t result = 0;
 
-    for (index = 0; index < obj_num; index++)
+    for (index = 0; index < UART_OBJ_NUM; index++)
     {
         uart_obj[index].config = &uart_config[index];
         uart_obj[index].serial.ops = &_uart_ops;
         uart_obj[index].serial.config = serial_config;
 
-        uart_obj[index].config->uart_obj = rt_malloc(sizeof(mtb_hal_uart_t));
-        uart_obj[index].config->uart_context = rt_malloc(sizeof(cy_stc_scb_uart_context_t));
+        uart_obj[index].config->uart_obj = &uart_hal_obj[index];
+        uart_obj[index].config->uart_context = &uart_hal_context[index];
 
-        RT_ASSERT(uart_obj[index].config->uart_obj != RT_NULL);
         /* register uart device */
         result = rt_hw_serial_register(&uart_obj[index].serial,
                                        uart_obj[index].config->name,
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c
index 405989d8..f8acd59d 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.c
@@ -33,9 +33,9 @@ void init_cycfg_peripheral_clocks(void)
     Cy_SysClk_PeriGroupSetDivider((0 << 8) | 2, 1U);
     Cy_SysClk_PeriGroupSetDivider((1 << 8) | 1, 1U);
     Cy_SysClk_PeriGroupSetDivider((1 << 8) | 3, 3U);
-    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
-    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 86U);
-    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_UART5_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
+    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_UART5_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 86U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_UART5_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
     Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U);
     Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U, 9U);
     Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_SPI_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 1U);
@@ -72,6 +72,9 @@ void init_cycfg_peripheral_clocks(void)
     Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U);
     Cy_SysClk_PeriPclkSetFracDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U, 0U, 0U);
     Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_TRACE_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_16_5_BIT, 0U);
+    Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)PERI_0_GROUP_8_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
+    Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)PERI_0_GROUP_8_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U, 173U);
+    Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)PERI_0_GROUP_8_DIV_16_0_GRP_NUM, CY_SYSCLK_DIV_16_BIT, 0U);
     Cy_SysClk_PeriPclkDisableDivider((en_clk_dst_t)CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
     Cy_SysClk_PeriPclkSetDivider((en_clk_dst_t)CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U, 7U);
     Cy_SysClk_PeriPclkEnableDivider((en_clk_dst_t)CYBSP_I3C_CONTROLLER_CLK_DIV_GRP_NUM, CY_SYSCLK_DIV_8_BIT, 0U);
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h
index 1d543d45..d4431975 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripheral_clocks.h
@@ -38,18 +38,18 @@ extern "C" {
 
 #define peri_0_mmio_0_ENABLED 1U
 #define peri_1_mmio_0_ENABLED 1U
-#define CYBSP_EZ_I2C_TARGET_CLK_DIV_ENABLED 1U
+#define CYBSP_UART5_CLK_DIV_ENABLED 1U
 
 #if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
-#define CYBSP_EZ_I2C_TARGET_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
+#define CYBSP_UART5_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT
 #endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
 
-#define CYBSP_EZ_I2C_TARGET_CLK_DIV_NUM 0U
-#define CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
+#define CYBSP_UART5_CLK_DIV_NUM 0U
+#define CYBSP_UART5_CLK_DIV_GRP_NUM ((1U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
 
-#if !defined (CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM)
-#define CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM
-#endif /* !defined (CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM) */
+#if !defined (CYBSP_UART5_CLK_DIV_GRP_NUM)
+#define CYBSP_UART5_CLK_DIV_GRP_NUM CYBSP_UART5_CLK_DIV_GRP_NUM
+#endif /* !defined (CYBSP_UART5_CLK_DIV_GRP_NUM) */
 
 #define CYBSP_SPI_CONTROLLER_CLK_DIV_ENABLED 1U
 
@@ -207,6 +207,19 @@ extern "C" {
 #define CYBSP_TRACE_CLK_DIV_GRP_NUM CYBSP_TRACE_CLK_DIV_GRP_NUM
 #endif /* !defined (CYBSP_TRACE_CLK_DIV_GRP_NUM) */
 
+#define peri_0_group_8_div_16_0_ENABLED 1U
+
+#if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
+#define peri_0_group_8_div_16_0_HW CY_SYSCLK_DIV_16_BIT
+#endif /* !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE) */
+
+#define peri_0_group_8_div_16_0_NUM 0U
+#define PERI_0_GROUP_8_DIV_16_0_GRP_NUM ((8U << PERI_PCLK_GR_NUM_Pos) | (0U << PERI_PCLK_INST_NUM_Pos))
+
+#if !defined (peri_0_group_8_div_16_0_GRP_NUM)
+#define peri_0_group_8_div_16_0_GRP_NUM PERI_0_GROUP_8_DIV_16_0_GRP_NUM
+#endif /* !defined (peri_0_group_8_div_16_0_GRP_NUM) */
+
 #define CYBSP_I3C_CONTROLLER_CLK_DIV_ENABLED 1U
 
 #if !defined (CY_USING_HAL) && !defined (CY_USING_HAL_LITE)
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c
index 5df1bb94..a45d9627 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.c
@@ -44,7 +44,6 @@
 #define emUSB_OS_Timer_INPUT_DISABLED 0x7U
 #define tcpwm_0_group_0_cnt_5_INPUT_DISABLED 0x7U
 #define tcpwm_0_group_0_cnt_6_INPUT_DISABLED 0x7U
-#define CYBSP_DEAD_TIME_PWM_INPUT_DISABLED 0x7U
 #define tcpwm_0_group_1_cnt_6_INPUT_DISABLED 0x7U
 #define tcpwm_0_group_1_cnt_9_INPUT_DISABLED 0x7U
 #define tcpwm_0_group_1_cnt_13_INPUT_DISABLED 0x7U
@@ -564,6 +563,67 @@ const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config =
 };
 #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */
 
+const cy_stc_scb_uart_config_t CYBSP_UART1_config =
+{
+    .uartMode = CY_SCB_UART_STANDARD,
+    .enableMultiProcessorMode = false,
+    .smartCardRetryOnNack = false,
+    .irdaInvertRx = false,
+    .irdaEnableLowPowerReceiver = false,
+    .oversample = 10,
+    .enableMsbFirst = false,
+    .dataWidth = 8UL,
+    .parity = CY_SCB_UART_PARITY_NONE,
+    .stopBits = CY_SCB_UART_STOP_BITS_1,
+    .enableInputFilter = false,
+    .breakWidth = 11UL,
+    .dropOnFrameError = false,
+    .dropOnParityError = false,
+    .breaklevel = false,
+    .receiverAddress = 0x0UL,
+    .receiverAddressMask = 0x0UL,
+    .acceptAddrInFifo = false,
+    .enableCts = false,
+    .ctsPolarity = CY_SCB_UART_ACTIVE_LOW,
+    .rtsRxFifoLevel = 0UL,
+    .rtsPolarity = CY_SCB_UART_ACTIVE_LOW,
+    .rxFifoTriggerLevel = 63UL,
+    .rxFifoIntEnableMask = 0UL,
+    .txFifoTriggerLevel = 63UL,
+    .txFifoIntEnableMask = 0UL,
+};
+
+#if defined (COMPONENT_MTB_HAL)
+const mtb_hal_peri_div_t CYBSP_UART1_clock_ref =
+{
+    .clk_dst = (en_clk_dst_t)peri_0_group_8_div_16_0_GRP_NUM,
+    .div_type = peri_0_group_8_div_16_0_HW,
+    .div_num = peri_0_group_8_div_16_0_NUM,
+};
+const mtb_hal_clock_t CYBSP_UART1_hal_clock =
+{
+    .clock_ref = &CYBSP_UART1_clock_ref,
+    .interface = &mtb_hal_clock_peri_interface,
+};
+#endif /* defined (COMPONENT_MTB_HAL) */
+
+#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART)
+const mtb_hal_uart_configurator_t CYBSP_UART1_hal_config =
+{
+    .base = CYBSP_UART1_HW,
+    .clock = &CYBSP_UART1_hal_clock,
+    .tx_pin = 2,
+#if defined (COMPONENT_MW_ASYNC_TRANSFER)
+    .rts_pin = 0xFF,
+#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */
+    .tx_port = 9,
+#if defined (COMPONENT_MW_ASYNC_TRANSFER)
+    .rts_port = 0xFF,
+    .rts_enable = 0UL,
+#endif /* defined (COMPONENT_MW_ASYNC_TRANSFER) */
+};
+#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */
+
 const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config =
 {
     .uartMode = CY_SCB_UART_STANDARD,
@@ -719,9 +779,9 @@ const cy_stc_scb_uart_config_t CYBSP_UART5_config =
 #if defined (COMPONENT_MTB_HAL)
 const mtb_hal_peri_div_t CYBSP_UART5_clock_ref =
 {
-    .clk_dst = (en_clk_dst_t)CYBSP_EZ_I2C_TARGET_CLK_DIV_GRP_NUM,
-    .div_type = CYBSP_EZ_I2C_TARGET_CLK_DIV_HW,
-    .div_num = CYBSP_EZ_I2C_TARGET_CLK_DIV_NUM,
+    .clk_dst = (en_clk_dst_t)CYBSP_UART5_CLK_DIV_GRP_NUM,
+    .div_type = CYBSP_UART5_CLK_DIV_HW,
+    .div_num = CYBSP_UART5_CLK_DIV_NUM,
 };
 const mtb_hal_clock_t CYBSP_UART5_hal_clock =
 {
@@ -1529,97 +1589,6 @@ const mtb_hal_pwm_configurator_t tcpwm_0_group_0_cnt_6_hal_config =
 };
 #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */
 
-const cy_stc_tcpwm_pwm_config_t CYBSP_DEAD_TIME_PWM_config =
-{
-    .pwmMode = CY_TCPWM_PWM_MODE_DEADTIME,
-    .clockPrescaler = CY_TCPWM_PWM_PRESCALER_DIVBY_1,
-    .pwmAlignment = CY_TCPWM_PWM_LEFT_ALIGN,
-    .deadTimeClocks = 100,
-    .runMode = CY_TCPWM_PWM_CONTINUOUS,
-    .period0 = 400,
-    .period1 = 32768,
-    .enablePeriodSwap = false,
-    .compare0 = 200,
-    .compare1 = 16384,
-    .enableCompareSwap = false,
-    .interruptSources = (CY_TCPWM_INT_ON_TC & 0U) | (CY_TCPWM_INT_ON_CC0 & 0U) | (CY_TCPWM_INT_ON_CC1 & 0U),
-    .invertPWMOut = CY_TCPWM_PWM_INVERT_DISABLE,
-    .invertPWMOutN = CY_TCPWM_PWM_INVERT_DISABLE,
-    .killMode = CY_TCPWM_PWM_STOP_ON_KILL,
-    .swapInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U,
-    .swapInput = CY_TCPWM_INPUT_0,
-    .reloadInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U,
-    .reloadInput = CY_TCPWM_INPUT_0,
-    .startInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U,
-    .startInput = CY_TCPWM_INPUT_0,
-    .killInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U,
-    .killInput = CY_TCPWM_INPUT_0,
-    .countInputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U,
-    .countInput = CY_TCPWM_INPUT_1,
-    .swapOverflowUnderflow = false,
-    .immediateKill = false,
-    .tapsEnabled = 45,
-    .compare2 = CY_TCPWM_GRP_CNT_CC0_DEFAULT,
-    .compare3 = CY_TCPWM_GRP_CNT_CC0_BUFF_DEFAULT,
-    .enableCompare1Swap = false,
-    .compare0MatchUp = true,
-    .compare0MatchDown = false,
-    .compare1MatchUp = true,
-    .compare1MatchDown = false,
-    .kill1InputMode = CYBSP_DEAD_TIME_PWM_INPUT_DISABLED & 0x3U,
-    .kill1Input = CY_TCPWM_INPUT_0,
-    .pwmOnDisable = CY_TCPWM_PWM_OUTPUT_HIGHZ,
-    .trigger0Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED,
-    .trigger1Event = CY_TCPWM_CNT_TRIGGER_ON_DISABLED,
-    .reloadLineSelect = false,
-    .line_out_sel = CY_TCPWM_OUTPUT_PWM_SIGNAL,
-    .linecompl_out_sel = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL,
-    .line_out_sel_buff = CY_TCPWM_OUTPUT_PWM_SIGNAL,
-    .linecompl_out_sel_buff = CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL,
-    .deadTimeClocks_linecompl_out = 100,
-#if defined (CY_IP_MXS40TCPWM)
-    .hrpwm_enable = false,
-    .hrpwm_input_freq = CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ,
-    .kill_line_polarity = CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW,
-    .deadTimeClocksBuff = 0,
-    .deadTimeClocksBuff_linecompl_out = 0,
-    .buffer_swap_enable = false,
-    .glitch_filter_enable = false,
-    .gf_depth = CY_GLITCH_FILTER_DEPTH_SUPPORT_VALUE_0,
-    .dithering_mode = CY_TCPWM_DITHERING_DISABLE,
-    .period_dithering_value = 128,
-    .duty_dithering_value = 128,
-    .limiter = CY_TCPWM_DITHERING_LIMITER_7,
-    .pwm_tc_sync_kill_dt = false,
-    .pwm_sync_kill_dt = false,
-#endif /* defined (CY_IP_MXS40TCPWM) */
-};
-
-#if defined (COMPONENT_MTB_HAL)
-const mtb_hal_peri_div_t CYBSP_DEAD_TIME_PWM_clock_ref =
-{
-    .clk_dst = (en_clk_dst_t)PCLK_TCPWM0_CLOCK_COUNTER_EN7,
-    .div_type = CY_SYSCLK_DIV_8_BIT,
-    .div_num = 3,
-};
-const mtb_hal_clock_t CYBSP_DEAD_TIME_PWM_hal_clock =
-{
-    .clock_ref = &CYBSP_DEAD_TIME_PWM_clock_ref,
-    .interface = &mtb_hal_clock_peri_interface,
-};
-#endif /* defined (COMPONENT_MTB_HAL) */
-
-#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM)
-const mtb_hal_pwm_configurator_t CYBSP_DEAD_TIME_PWM_hal_config =
-{
-    .base = CYBSP_DEAD_TIME_PWM_HW,
-    .clock = &CYBSP_DEAD_TIME_PWM_hal_clock,
-    .group = 0UL,
-    .cntnum = 7UL,
-    .max_count = 400,
-};
-#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */
-
 const cy_stc_tcpwm_pwm_config_t tcpwm_0_group_1_cnt_6_config =
 {
     .pwmMode = CY_TCPWM_PWM_MODE_PWM,
@@ -1915,6 +1884,8 @@ void init_cycfg_peripherals(void)
     Cy_SysClk_PeriPclkAssignDivider(PCLK_PDM0_CLK_IF_SRSS, CY_SYSCLK_DIV_16_5_BIT, 1U);
     Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB0_PERI_NR, CY_MMIO_SCB0_GROUP_NR, CY_MMIO_SCB0_SLAVE_NR, CY_MMIO_SCB0_CLK_HF_NR);
     Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB0_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 0U);
+    Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB1_PERI_NR, CY_MMIO_SCB1_GROUP_NR, CY_MMIO_SCB1_SLAVE_NR, CY_MMIO_SCB1_CLK_HF_NR);
+    Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB1_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 0U);
     Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB2_PERI_NR, CY_MMIO_SCB2_GROUP_NR, CY_MMIO_SCB2_SLAVE_NR, CY_MMIO_SCB2_CLK_HF_NR);
     Cy_SysClk_PeriPclkAssignDivider(PCLK_SCB2_CLOCK_SCB_EN, CY_SYSCLK_DIV_16_BIT, 1U);
     Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_SCB4_PERI_NR, CY_MMIO_SCB4_GROUP_NR, CY_MMIO_SCB4_SLAVE_NR, CY_MMIO_SCB4_CLK_HF_NR);
@@ -1960,10 +1931,6 @@ void init_cycfg_peripherals(void)
     Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN6, CY_SYSCLK_DIV_16_BIT, 3U);
 #if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)
     Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR);
-#endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */
-    Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN7, CY_SYSCLK_DIV_8_BIT, 3U);
-#if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)
-    Cy_SysClk_PeriGroupSlaveInit(CY_MMIO_TCPWM0_PERI_NR, CY_MMIO_TCPWM0_GROUP_NR, CY_MMIO_TCPWM0_SLAVE_NR, CY_MMIO_TCPWM0_CLK_HF_NR);
 #endif /* defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE) */
     Cy_SysClk_PeriphAssignDivider(PCLK_TCPWM0_CLOCK_COUNTER_EN262, CY_SYSCLK_DIV_16_5_BIT, 1U);
 #if defined (CY_DEVICE_CONFIGURATOR_IP_ENABLE_FEATURE)
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h
index 2555cd0c..0cb459ad 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_peripherals.h
@@ -90,6 +90,9 @@ extern "C" {
 #define CYBSP_I2C_CONTROLLER_ENABLED 1U
 #define CYBSP_I2C_CONTROLLER_HW SCB0
 #define CYBSP_I2C_CONTROLLER_IRQ scb_0_interrupt_IRQn
+#define CYBSP_UART1_ENABLED 1U
+#define CYBSP_UART1_HW SCB1
+#define CYBSP_UART1_IRQ scb_1_interrupt_IRQn
 #define CYBSP_DEBUG_UART_ENABLED 1U
 #define CYBSP_DEBUG_UART_HW SCB2
 #define CYBSP_DEBUG_UART_IRQ scb_2_interrupt_IRQn
@@ -199,9 +202,6 @@ extern "C" {
 #define tcpwm_0_group_0_cnt_6_ENABLED 1U
 #define tcpwm_0_group_0_cnt_6_HW TCPWM0
 #define tcpwm_0_group_0_cnt_6_NUM 6UL
-#define CYBSP_DEAD_TIME_PWM_ENABLED 1U
-#define CYBSP_DEAD_TIME_PWM_HW TCPWM0
-#define CYBSP_DEAD_TIME_PWM_NUM 7UL
 #define tcpwm_0_group_1_cnt_6_ENABLED 1U
 #define tcpwm_0_group_1_cnt_6_HW TCPWM0
 #define tcpwm_0_group_1_cnt_6_NUM 262UL
@@ -252,6 +252,17 @@ extern const mtb_hal_clock_t CYBSP_I2C_CONTROLLER_hal_clock;
 extern const mtb_hal_i2c_configurator_t CYBSP_I2C_CONTROLLER_hal_config;
 #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_I2C) */
 
+extern const cy_stc_scb_uart_config_t CYBSP_UART1_config;
+
+#if defined (COMPONENT_MTB_HAL)
+extern const mtb_hal_peri_div_t CYBSP_UART1_clock_ref;
+extern const mtb_hal_clock_t CYBSP_UART1_hal_clock;
+#endif /* defined (COMPONENT_MTB_HAL) */
+
+#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART)
+extern const mtb_hal_uart_configurator_t CYBSP_UART1_hal_config;
+#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_UART) */
+
 extern const cy_stc_scb_uart_config_t CYBSP_DEBUG_UART_config;
 
 #if defined (COMPONENT_MTB_HAL)
@@ -433,17 +444,6 @@ extern const mtb_hal_clock_t tcpwm_0_group_0_cnt_6_hal_clock;
 extern const mtb_hal_pwm_configurator_t tcpwm_0_group_0_cnt_6_hal_config;
 #endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */
 
-extern const cy_stc_tcpwm_pwm_config_t CYBSP_DEAD_TIME_PWM_config;
-
-#if defined (COMPONENT_MTB_HAL)
-extern const mtb_hal_peri_div_t CYBSP_DEAD_TIME_PWM_clock_ref;
-extern const mtb_hal_clock_t CYBSP_DEAD_TIME_PWM_hal_clock;
-#endif /* defined (COMPONENT_MTB_HAL) */
-
-#if defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM)
-extern const mtb_hal_pwm_configurator_t CYBSP_DEAD_TIME_PWM_hal_config;
-#endif /* defined (COMPONENT_MTB_HAL) && (MTB_HAL_DRIVER_AVAILABLE_PWM) */
-
 extern const cy_stc_tcpwm_pwm_config_t tcpwm_0_group_1_cnt_6_config;
 
 #if defined (COMPONENT_MTB_HAL)
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c
index 84039f5a..dc145194 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.c
@@ -604,11 +604,29 @@ const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_0_config =
     .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE,
     .nonSec = 1,
 };
-const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_2_config =
+const cy_stc_gpio_pin_config_t CYBSP_UART1_TX_config =
 {
     .outVal = 1,
     .driveMode = CY_GPIO_DM_STRONG_IN_OFF,
-    .hsiom = CYBSP_SERIAL_INT_2_HSIOM,
+    .hsiom = CYBSP_UART1_TX_HSIOM,
+    .intEdge = CY_GPIO_INTR_DISABLE,
+    .intMask = 0UL,
+    .vtrip = CY_GPIO_VTRIP_CMOS,
+    .slewRate = CY_GPIO_SLEW_FAST,
+    .driveSel = CY_GPIO_DRIVE_1_2,
+    .vregEn = 0UL,
+    .ibufMode = 0UL,
+    .vtripSel = 0UL,
+    .vrefSel = 0UL,
+    .vohSel = 0UL,
+    .pullUpRes = CY_GPIO_PULLUP_RES_DISABLE,
+    .nonSec = 1,
+};
+const cy_stc_gpio_pin_config_t CYBSP_UART1_RX_config =
+{
+    .outVal = 1,
+    .driveMode = CY_GPIO_DM_HIGHZ,
+    .hsiom = CYBSP_UART1_RX_HSIOM,
     .intEdge = CY_GPIO_INTR_DISABLE,
     .intMask = 0UL,
     .vtrip = CY_GPIO_VTRIP_CMOS,
@@ -1377,7 +1395,8 @@ void init_cycfg_pins(void)
     Cy_GPIO_Pin_Init(CYBSP_PDM_DATA_PORT, CYBSP_PDM_DATA_PIN, &CYBSP_PDM_DATA_config);
     Cy_GPIO_Pin_Init(CYBSP_SW4_PORT, CYBSP_SW4_PIN, &CYBSP_SW4_config);
     Cy_GPIO_Pin_Init(CYBSP_SERIAL_INT_0_PORT, CYBSP_SERIAL_INT_0_PIN, &CYBSP_SERIAL_INT_0_config);
-    Cy_GPIO_Pin_Init(CYBSP_SERIAL_INT_2_PORT, CYBSP_SERIAL_INT_2_PIN, &CYBSP_SERIAL_INT_2_config);
+    Cy_GPIO_Pin_Init(CYBSP_UART1_TX_PORT, CYBSP_UART1_TX_PIN, &CYBSP_UART1_TX_config);
+    Cy_GPIO_Pin_Init(CYBSP_UART1_RX_PORT, CYBSP_UART1_RX_PIN, &CYBSP_UART1_RX_config);
     Cy_GPIO_Pin_Init(CYBSP_BT_UART_RX_PORT, CYBSP_BT_UART_RX_PIN, &CYBSP_BT_UART_RX_config);
     Cy_GPIO_Pin_Init(CYBSP_BT_UART_TX_PORT, CYBSP_BT_UART_TX_PIN, &CYBSP_BT_UART_TX_config);
     Cy_GPIO_Pin_Init(CYBSP_BT_UART_CTS_PORT, CYBSP_BT_UART_CTS_PIN, &CYBSP_BT_UART_CTS_config);
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h
index ebf1cf49..4ae1c3dc 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_pins.h
@@ -484,18 +484,30 @@ extern "C" {
 #endif
 #define CYBSP_SERIAL_INT_0_HSIOM ioss_0_port_9_pin_0_HSIOM
 #define CYBSP_SERIAL_INT_0_IRQ ioss_interrupts_gpio_9_IRQn
-#define CYBSP_SERIAL_INT_2_ENABLED 1U
-#define CYBSP_SERIAL_INT_2_PORT GPIO_PRT9
-#define CYBSP_SERIAL_INT_2_PORT_NUM 9U
-#define CYBSP_SERIAL_INT_2_PIN 2U
-#define CYBSP_SERIAL_INT_2_NUM 2U
-#define CYBSP_SERIAL_INT_2_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
-#define CYBSP_SERIAL_INT_2_INIT_DRIVESTATE 1
+#define CYBSP_UART1_TX_ENABLED 1U
+#define CYBSP_UART1_TX_PORT GPIO_PRT9
+#define CYBSP_UART1_TX_PORT_NUM 9U
+#define CYBSP_UART1_TX_PIN 2U
+#define CYBSP_UART1_TX_NUM 2U
+#define CYBSP_UART1_TX_DRIVEMODE CY_GPIO_DM_STRONG_IN_OFF
+#define CYBSP_UART1_TX_INIT_DRIVESTATE 1
 #ifndef ioss_0_port_9_pin_2_HSIOM
     #define ioss_0_port_9_pin_2_HSIOM HSIOM_SEL_GPIO
 #endif
-#define CYBSP_SERIAL_INT_2_HSIOM ioss_0_port_9_pin_2_HSIOM
-#define CYBSP_SERIAL_INT_2_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_UART1_TX_HSIOM ioss_0_port_9_pin_2_HSIOM
+#define CYBSP_UART1_TX_IRQ ioss_interrupts_gpio_9_IRQn
+#define CYBSP_UART1_RX_ENABLED 1U
+#define CYBSP_UART1_RX_PORT GPIO_PRT9
+#define CYBSP_UART1_RX_PORT_NUM 9U
+#define CYBSP_UART1_RX_PIN 3U
+#define CYBSP_UART1_RX_NUM 3U
+#define CYBSP_UART1_RX_DRIVEMODE CY_GPIO_DM_HIGHZ
+#define CYBSP_UART1_RX_INIT_DRIVESTATE 1
+#ifndef ioss_0_port_9_pin_3_HSIOM
+    #define ioss_0_port_9_pin_3_HSIOM HSIOM_SEL_GPIO
+#endif
+#define CYBSP_UART1_RX_HSIOM ioss_0_port_9_pin_3_HSIOM
+#define CYBSP_UART1_RX_IRQ ioss_interrupts_gpio_9_IRQn
 #define CYBSP_BT_UART_RX_ENABLED 1U
 #define CYBSP_ETH_TXD_3_ENABLED CYBSP_BT_UART_RX_ENABLED
 #define CYBSP_BT_UART_RX_PORT GPIO_PRT10
@@ -1154,7 +1166,8 @@ extern const cy_stc_gpio_pin_config_t CYBSP_SW4_config;
 #define CYBSP_USER_BTN2_config CYBSP_SW4_config
 
 extern const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_0_config;
-extern const cy_stc_gpio_pin_config_t CYBSP_SERIAL_INT_2_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_UART1_TX_config;
+extern const cy_stc_gpio_pin_config_t CYBSP_UART1_RX_config;
 extern const cy_stc_gpio_pin_config_t CYBSP_BT_UART_RX_config;
 
 #define CYBSP_ETH_TXD_3_config CYBSP_BT_UART_RX_config
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h
index 6f8fcf8a..5aeba7e8 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/GeneratedSource/cycfg_routing.h
@@ -51,8 +51,8 @@ extern "C" {
 #define ioss_0_port_8_pin_1_HSIOM P8_1_SCB0_I2C_SDA
 #define ioss_0_port_8_pin_5_HSIOM P8_5_PDM_PDM_CLK3
 #define ioss_0_port_8_pin_6_HSIOM P8_6_PDM_PDM_DATA3
-#define ioss_0_port_9_pin_0_HSIOM P9_0_TCPWM0_LINE7
-#define ioss_0_port_9_pin_2_HSIOM P9_2_TCPWM0_LINE_COMPL7
+#define ioss_0_port_9_pin_2_HSIOM P9_2_SCB1_UART_TX
+#define ioss_0_port_9_pin_3_HSIOM P9_3_SCB1_UART_RX
 #define ioss_0_port_10_pin_0_HSIOM P10_0_SCB4_UART_RX
 #define ioss_0_port_10_pin_1_HSIOM P10_1_SCB4_UART_TX
 #define ioss_0_port_10_pin_2_HSIOM P10_2_SCB4_UART_CTS
diff --git a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus
index 82191937..cdfc720b 100644
--- a/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus
+++ b/projects/libs/TARGET_APP_KIT_PSE84_EVAL_EPC2/config/design.modus
@@ -85,11 +85,6 @@
                         <Alias value="CYBSP_SERIAL_INT_1"/>
                     </Aliases>
                 </Block>
-                <Block location="ioss[0].port[9].pin[3]">
-                    <Aliases>
-                        <Alias value="CYBSP_SERIAL_INT_3"/>
-                    </Aliases>
-                </Block>
                 <Block location="ioss[0].port[10].pin[5]">
                     <Aliases>
                         <Alias value="CYBSP_ARD_D6"/>
@@ -3108,7 +3103,7 @@
                 <Personality template="pin" version="3.0" instance="uympnGhW9g0">
                     <Block location="ioss[0].port[9].pin[2]" locked="true">
                         <Aliases>
-                            <Alias value="CYBSP_SERIAL_INT_2"/>
+                            <Alias value="CYBSP_UART1_TX"/>
                         </Aliases>
                     </Block>
                     <Parameters>
@@ -3126,6 +3121,27 @@
                         <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
                     </Parameters>
                 </Personality>
+                <Personality template="pin" version="3.0" instance="HoMBnAE2OOg">
+                    <Block location="ioss[0].port[9].pin[3]" locked="true">
+                        <Aliases>
+                            <Alias value="CYBSP_UART1_RX"/>
+                        </Aliases>
+                    </Block>
+                    <Parameters>
+                        <Param id="DriveModes" value="CY_GPIO_DM_HIGHZ"/>
+                        <Param id="driveStrength" value="CY_GPIO_DRIVE_1_2"/>
+                        <Param id="driveStrengthTrim" value="CY_GPIO_DRIVE_STRENGTH_DEFAULT"/>
+                        <Param id="extended_drive_sel" value="false"/>
+                        <Param id="inFlash" value="true"/>
+                        <Param id="initialState" value="1"/>
+                        <Param id="isrTrigger" value="CY_GPIO_INTR_DISABLE"/>
+                        <Param id="nonSec" value="1"/>
+                        <Param id="pullUpRes" value="CY_GPIO_PULLUP_RES_DISABLE"/>
+                        <Param id="sioOutputBuffer" value="true"/>
+                        <Param id="slewRate" value="CY_GPIO_SLEW_FAST"/>
+                        <Param id="vtrip" value="CY_GPIO_VTRIP_CMOS"/>
+                    </Parameters>
+                </Personality>
                 <Personality template="pin" version="3.0" instance="z-Nxbt8Ei1g">
                     <Block location="ioss[0].port[10].pin[0]" locked="true">
                         <Aliases>
@@ -4405,7 +4421,7 @@
                 <Personality template="pclk_v2" version="1.1" instance="E5ESJtxKQgk">
                     <Block location="peri[0].group[1].div_8[0]" locked="true">
                         <Aliases>
-                            <Alias value="CYBSP_EZ_I2C_TARGET_CLK_DIV"/>
+                            <Alias value="CYBSP_UART5_CLK_DIV"/>
                         </Aliases>
                     </Block>
                     <Parameters>
@@ -4545,6 +4561,13 @@
                         <Param id="startOnReset" value="true"/>
                     </Parameters>
                 </Personality>
+                <Personality template="pclk_v2" version="1.1" instance="3Q1s3zZxgFg">
+                    <Block location="peri[0].group[8].div_16[0]" locked="true"/>
+                    <Parameters>
+                        <Param id="intDivider" value="174"/>
+                        <Param id="startOnReset" value="true"/>
+                    </Parameters>
+                </Personality>
                 <Personality template="pclk_v2" version="1.1" instance="1uBmbxjOkWE">
                     <Block location="peri[0].group[9].div_8[0]" locked="true">
                         <Aliases>
@@ -4649,6 +4672,60 @@
                         <Param id="inFlash" value="true"/>
                     </Parameters>
                 </Personality>
+                <Personality template="uart" version="3.0" instance="C3q91snHdug">
+                    <Block location="scb[1]" locked="true">
+                        <Aliases>
+                            <Alias value="CYBSP_UART1"/>
+                        </Aliases>
+                    </Block>
+                    <Parameters>
+                        <Param id="ApiMode" value="HIGH_LEVEL"/>
+                        <Param id="BaudRate" value="115200"/>
+                        <Param id="BitsOrder" value="CY_SCB_UART_LSB_FIRST"/>
+                        <Param id="BreakLevel" value="0"/>
+                        <Param id="BreakSignalBits" value="11"/>
+                        <Param id="ComMode" value="CY_SCB_UART_STANDARD"/>
+                        <Param id="CtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
+                        <Param id="DataWidth" value="8"/>
+                        <Param id="DropOnFrameErr" value="false"/>
+                        <Param id="DropOnParityErr" value="false"/>
+                        <Param id="EnableHalfDuplex" value="false"/>
+                        <Param id="EnableInputFilter" value="false"/>
+                        <Param id="EnableTxEn" value="false"/>
+                        <Param id="FlowControl" value="false"/>
+                        <Param id="IntrRxBreakDetected" value="false"/>
+                        <Param id="IntrRxFrameErr" value="false"/>
+                        <Param id="IntrRxFull" value="false"/>
+                        <Param id="IntrRxNotEmpty" value="false"/>
+                        <Param id="IntrRxOverflow" value="false"/>
+                        <Param id="IntrRxParityErr" value="false"/>
+                        <Param id="IntrRxTrigger" value="false"/>
+                        <Param id="IntrRxUnderflow" value="false"/>
+                        <Param id="IntrTxEmpty" value="false"/>
+                        <Param id="IntrTxNotFull" value="false"/>
+                        <Param id="IntrTxOverflow" value="false"/>
+                        <Param id="IntrTxTrigger" value="false"/>
+                        <Param id="IntrTxUartDone" value="false"/>
+                        <Param id="IntrTxUartLostArb" value="false"/>
+                        <Param id="IntrTxUartNack" value="false"/>
+                        <Param id="IntrTxUnderflow" value="false"/>
+                        <Param id="IrdaLowPower" value="false"/>
+                        <Param id="IrdaPolarity" value="NON_INVERTING"/>
+                        <Param id="MpRxAcceptAddress" value="false"/>
+                        <Param id="MpRxAddress" value="0"/>
+                        <Param id="MpRxAddressMask" value="255"/>
+                        <Param id="MultiProc" value="false"/>
+                        <Param id="Oversample" value="10"/>
+                        <Param id="ParityType" value="CY_SCB_UART_PARITY_NONE"/>
+                        <Param id="RtsPolarity" value="CY_SCB_UART_ACTIVE_LOW"/>
+                        <Param id="RtsTriggerLevel" value="63"/>
+                        <Param id="RxTriggerLevel" value="63"/>
+                        <Param id="SmCardRetryOnNack" value="false"/>
+                        <Param id="StopBits" value="CY_SCB_UART_STOP_BITS_1"/>
+                        <Param id="TxTriggerLevel" value="63"/>
+                        <Param id="inFlash" value="true"/>
+                    </Parameters>
+                </Personality>
                 <Personality template="uart" version="3.0" instance="TFNlT-F3wpU">
                     <Block location="scb[2]" locked="true">
                         <Aliases>
@@ -5394,69 +5471,6 @@
                         <Param id="trigger1Event" value="CY_TCPWM_CNT_TRIGGER_ON_DISABLED"/>
                     </Parameters>
                 </Personality>
-                <Personality template="mxs40pwm_ver2" version="1.0" instance="a9L3YpbHpAo">
-                    <Block location="tcpwm[0].group[0].cnt[7]" locked="true">
-                        <Aliases>
-                            <Alias value="CYBSP_DEAD_TIME_PWM"/>
-                        </Aliases>
-                    </Block>
-                    <Parameters>
-                        <Param id="ClockPrescaler" value="CY_TCPWM_PWM_PRESCALER_DIVBY_1"/>
-                        <Param id="Compare0" value="200"/>
-                        <Param id="Compare0MatchDown" value="false"/>
-                        <Param id="Compare0MatchUp" value="true"/>
-                        <Param id="Compare1" value="16384"/>
-                        <Param id="Compare1MatchDown" value="false"/>
-                        <Param id="Compare1MatchUp" value="true"/>
-                        <Param id="Compare2" value="16384"/>
-                        <Param id="Compare3" value="16384"/>
-                        <Param id="CountInput" value="CY_TCPWM_INPUT_DISABLED"/>
-                        <Param id="DeadClocks" value="100"/>
-                        <Param id="DeadClocksBuff" value="0"/>
-                        <Param id="DeadClocksBuff_compl" value="0"/>
-                        <Param id="DeadClocks_compl" value="100"/>
-                        <Param id="Duty_Dithering" value="128"/>
-                        <Param id="EnableCompare0Swap" value="false"/>
-                        <Param id="EnableCompare1Swap" value="false"/>
-                        <Param id="EnablePeriodSwap" value="false"/>
-                        <Param id="ImmediateKill" value="false"/>
-                        <Param id="InterruptCC0" value="false"/>
-                        <Param id="InterruptCC1" value="false"/>
-                        <Param id="InterruptTC" value="false"/>
-                        <Param id="InvertPwm" value="false"/>
-                        <Param id="InvertPwm_n" value="false"/>
-                        <Param id="Kill0Input" value="CY_TCPWM_INPUT_DISABLED"/>
-                        <Param id="Kill1Input" value="CY_TCPWM_INPUT_DISABLED"/>
-                        <Param id="Period0" value="400"/>
-                        <Param id="Period1" value="32768"/>
-                        <Param id="Period_Dithering" value="128"/>
-                        <Param id="PwmAlignment" value="CY_TCPWM_PWM_LEFT_ALIGN"/>
-                        <Param id="PwmDisabledOutput" value="CY_TCPWM_PWM_OUTPUT_HIGHZ"/>
-                        <Param id="PwmMode" value="CY_TCPWM_PWM_MODE_DEADTIME"/>
-                        <Param id="ReloadInput" value="CY_TCPWM_INPUT_DISABLED"/>
-                        <Param id="RunMode" value="CY_TCPWM_PWM_CONTINUOUS"/>
-                        <Param id="StartInput" value="CY_TCPWM_INPUT_DISABLED"/>
-                        <Param id="SwapInput" value="CY_TCPWM_INPUT_DISABLED"/>
-                        <Param id="SwapUnderflowOverflow" value="false"/>
-                        <Param id="TapsEnabled" value="45"/>
-                        <Param id="buff_line_out_source" value="CY_TCPWM_OUTPUT_PWM_SIGNAL"/>
-                        <Param id="buff_linecompl_out_source" value="CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL"/>
-                        <Param id="enable_hrpwm" value="false"/>
-                        <Param id="hrpwm_input_clock" value="CY_TCPWM_HRPWM_FREQ_80MHZ_OR_100MHZ"/>
-                        <Param id="inFlash" value="true"/>
-                        <Param id="kill_line_polarity" value="CY_TCPWM_LINEOUT_AND_LINECMPOUT_IS_LOW"/>
-                        <Param id="limiter" value="CY_TCPWM_DITHERING_LIMITER_7"/>
-                        <Param id="line_out_source" value="CY_TCPWM_OUTPUT_PWM_SIGNAL"/>
-                        <Param id="linecompl_out_source" value="CY_TCPWM_OUTPUT_INVERTED_PWM_SIGNAL"/>
-                        <Param id="pwmstoponkill" value="true"/>
-                        <Param id="pwmsynckill" value="false"/>
-                        <Param id="pwmsynckilldt" value="false"/>
-                        <Param id="pwmtcsynckilldt" value="false"/>
-                        <Param id="reload_line_sel" value="false"/>
-                        <Param id="trigger0Event" value="CY_TCPWM_CNT_TRIGGER_ON_DISABLED"/>
-                        <Param id="trigger1Event" value="CY_TCPWM_CNT_TRIGGER_ON_DISABLED"/>
-                    </Parameters>
-                </Personality>
                 <Personality template="mxs40pwm_ver2" version="1.0" instance="-phUW9E2YkI">
                     <Block location="tcpwm[0].group[1].cnt[6]" locked="true"/>
                     <Parameters>
@@ -6232,12 +6246,12 @@
                     <Port name="pdm[0].pdm_data[3]"/>
                 </Net>
                 <Net>
-                    <Port name="ioss[0].port[9].pin[0].digital_out[0]"/>
-                    <Port name="tcpwm[0].group[0].cnt[7].line[0]"/>
+                    <Port name="ioss[0].port[9].pin[2].digital_inout[0]"/>
+                    <Port name="scb[1].uart_tx[0]"/>
                 </Net>
                 <Net>
-                    <Port name="ioss[0].port[9].pin[2].digital_out[0]"/>
-                    <Port name="tcpwm[0].group[0].cnt[7].line_compl[0]"/>
+                    <Port name="ioss[0].port[9].pin[3].digital_inout[0]"/>
+                    <Port name="scb[1].uart_rx[0]"/>
                 </Net>
                 <Net>
                     <Port name="ioss[0].port[10].pin[0].digital_inout[0]"/>
@@ -6380,17 +6394,13 @@
                     <Port name="tcpwm[0].group[0].cnt[1].clock_counter_en[0]"/>
                 </Net>
                 <Net>
-                    <Port name="peri[0].group[1].div_8[3].clk[0]"/>
-                    <Port name="tcpwm[0].group[0].cnt[7].clock_counter_en[0]"/>
+                    <Port name="peri[0].group[8].div_16[0].clk[0]"/>
+                    <Port name="scb[1].clock_scb_en[0]"/>
                 </Net>
                 <Net>
                     <Port name="peri[0].group[9].div_8[0].clk_pclk_root[0]"/>
                     <Port name="srss[0].clock[0].hfclk[13].root_clk[0]"/>
                 </Net>
-                <Net>
-                    <Port name="peri[0].mmio[0].clk_pclk_root[3]"/>
-                    <Port name="srss[0].clock[0].hfclk[11].root_clk[0]"/>
-                </Net>
                 <Net>
                     <Port name="peri[1].group[1].div_16_5[0].clk[0]"/>
                     <Port name="tdm[0].tdm[0].clk_if_srss[0]"/>
@@ -6428,6 +6438,11 @@
                     <Port name="peri[0].mmio[0].clk_pclk_root[5]"/>
                     <Port name="srss[0].clock[0].hfclk[9].root_clk[0]"/>
                 </Net>
+                <Net>
+                    <Port name="peri[0].group[8].div_16[0].clk_pclk_root[0]"/>
+                    <Port name="peri[0].mmio[0].clk_pclk_root[3]"/>
+                    <Port name="srss[0].clock[0].hfclk[11].root_clk[0]"/>
+                </Net>
                 <Net>
                     <Port name="peri[1].group[1].div_16_5[0].clk_pclk_root[0]"/>
                     <Port name="peri[1].group[1].div_16_5[1].clk_pclk_root[0]"/>