Add multi-channel support and unify Kconfig for xiaozhi project

libraries/HAL_Drivers/drv_adc.c

@@ -11,27 +11,19 @@
 #include <rtthread.h>
 #include "drv_adc.h"
 #include "board.h"
-#include "mtb_hal_adc.h"
+#include "cycfg_peripherals.h"
 
-#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
+#if defined(BSP_USING_ADC1)
 
 //#define DRV_DEBUG
 #define LOG_TAG             "drv.adc"
 #include <drv_log.h>
 
-#ifdef SOC_SERIES_IFX_PSOCE84
-    #define VPLUS_CHANNEL_0     (P15_5)
-    #define SAR_ADC_INDEX               (0U)
-    #define SAR_ADC_SEQENCER            (0U)
-    #define SAR_ADC_CHANNEL             (0U)
-    #define SAR_ADC_VREF_MV             (1800U)
-#endif
-
 struct ifx_adc
 {
     struct rt_adc_device ifx_adc_device;
-    mtb_hal_adc_channel_t *adc_ch;
-    char *name;
+    const struct ifx_sar_adc_config *cfg;
+    const char *name;
 };
 
 static struct ifx_adc ifx_adc_obj[] =
@@ -41,58 +33,217 @@ static struct ifx_adc ifx_adc_obj[] =
 #endif
 };
 
-static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
+static rt_bool_t autonomous_initialized = RT_FALSE;
+
+static uint8_t ifx_resolve_phy_channel(const struct ifx_sar_adc_config *cfg, uint8_t logical_channel)
+{
+#if defined(CYBSP_SAR_ADC_ENABLED)
+    uint8_t sar_channel;
+
+    for (sar_channel = 0; sar_channel < 8; sar_channel++)
+    {
+        const cy_stc_autanalog_sar_hs_chan_t *hs_channel = CYBSP_SAR_ADC_sta_hs_cfg.hsGpioChan[sar_channel];
+
+        if (hs_channel == NULL)
+        {
+            continue;
+        }
+
+        switch (logical_channel)
+        {
+        case ADC_CHANNEL0:
+            if (hs_channel->posPin == CY_AUTANALOG_SAR_PIN_GPIO4)
+            {
+                return sar_channel;
+            }
+            break;
+
+        case ADC_CHANNEL1:
+            if (hs_channel->posPin == CY_AUTANALOG_SAR_PIN_GPIO5)
+            {
+                return sar_channel;
+            }
+            break;
+
+        case ADC_CHANNEL2:
+            if (hs_channel->posPin == CY_AUTANALOG_SAR_PIN_GPIO6)
+            {
+                return sar_channel;
+            }
+            break;
+
+        case ADC_CHANNEL3:
+            if (hs_channel->posPin == CY_AUTANALOG_SAR_PIN_GPIO7)
+            {
+                return sar_channel;
+            }
+            break;
+
+        default:
+            break;
+        }
+    }
+#endif
+
+    return cfg->channel_map[logical_channel];
+}
+
+static rt_err_t ifx_autonomous_analog_init_once(void)
 {
     cy_rslt_t result = CY_RSLT_SUCCESS;
+
+    if (autonomous_initialized)
+    {
+        return RT_EOK;
+    }
+
     result = Cy_AutAnalog_Init(&autonomous_analog_init);
-    if (CY_AUTANALOG_SUCCESS != result)
+    if (result != CY_AUTANALOG_SUCCESS)
     {
-        rt_kprintf("Autonomous control initialization failed!\n");
+        LOG_E("Autonomous analog init failed");
+        return -RT_ERROR;
     }
+
     Cy_AutAnalog_SetInterruptMask(CY_AUTANALOG_INT_SAR0_RESULT);
     Cy_AutAnalog_StartAutonomousControl();
+    autonomous_initialized = RT_TRUE;
+
+    return RT_EOK;
+}
+
+static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_int8_t channel, rt_bool_t enabled)
+{
+    const struct ifx_sar_adc_config *cfg;
+    uint32_t channel_mask;
+
+    RT_UNUSED(enabled);
+
+    if ((device == RT_NULL) || (channel < 0))
+    {
+        return -RT_EINVAL;
+    }
+
+    cfg = (const struct ifx_sar_adc_config *)device->parent.user_data;
+    channel_mask = (uint32_t)(1u << (uint32_t)channel);
+    if ((cfg == RT_NULL) || ((uint32_t)channel >= cfg->max_channels))
+    {
+        return -RT_EINVAL;
+    }
+
+    if ((cfg->channel_mask & channel_mask) == 0u)
+    {
+        return -RT_EINVAL;
+    }
+
+    if (!autonomous_initialized)
+    {
+        return -RT_ERROR;
+    }
 
     return RT_EOK;
 }
 
 
 static rt_err_t ifx_get_adc_value(struct rt_adc_device *device, rt_int8_t channel, rt_uint32_t *value)
 {
-    uint32_t sar_adc_count;
-    uint16_t sar_adc_mv;
-
-    sar_adc_count = Cy_AutAnalog_SAR_ReadResult(SAR_ADC_INDEX,
-                    CY_AUTANALOG_SAR_INPUT_GPIO,
-                    SAR_ADC_CHANNEL);
-
-    sar_adc_mv = Cy_AutAnalog_SAR_CountsTo_mVolts(SAR_ADC_INDEX, false,
-                 SAR_ADC_SEQENCER,
-                 CY_AUTANALOG_SAR_INPUT_GPIO,
-                 SAR_ADC_CHANNEL,
-                 SAR_ADC_VREF_MV,
+    const struct ifx_sar_adc_config *cfg;
+    int32_t sar_adc_count;
+    int32_t sar_adc_mv;
+    uint8_t phy_channel;
+    uint32_t channel_mask;
+
+    if ((device == RT_NULL) || (value == RT_NULL) || (channel < 0))
+    {
+        return -RT_EINVAL;
+    }
+
+    cfg = (const struct ifx_sar_adc_config *)device->parent.user_data;
+    channel_mask = (uint32_t)(1u << (uint32_t)channel);
+    if ((cfg == RT_NULL) || ((uint32_t)channel >= cfg->max_channels))
+    {
+        return -RT_EINVAL;
+    }
+
+    if ((cfg->channel_mask & channel_mask) == 0u)
+    {
+        return -RT_EINVAL;
+    }
+
+    phy_channel = ifx_resolve_phy_channel(cfg, (uint8_t)channel);
+    if ((phy_channel == IFX_ADC_PHY_INVALID) || (phy_channel >= 8))
+    {
+        return -RT_EINVAL;
+    }
+
+    /* Force one fresh conversion result to avoid stale data. */
+    {
+        uint8_t ch_mask = (uint8_t)(1u << phy_channel);
+        uint32_t timeout = 100000U;
+
+        Cy_AutAnalog_SAR_ClearHSchanResultStatus(cfg->sar_idx, ch_mask);
+        Cy_AutAnalog_StartAutonomousControl();
+
+        while (timeout-- > 0U)
+        {
+            if ((Cy_AutAnalog_SAR_GetHSchanResultStatus(cfg->sar_idx) & ch_mask) != 0U)
+            {
+                break;
+            }
+        }
+
+        if (timeout == 0U)
+        {
+            return -RT_ETIMEOUT;
+        }
+    }
+
+    sar_adc_count = Cy_AutAnalog_SAR_ReadResult(cfg->sar_idx,
+                    cfg->input,
+                    phy_channel);
+
+    sar_adc_mv = Cy_AutAnalog_SAR_CountsTo_mVolts(cfg->sar_idx,
+                 cfg->low_power,
+                 cfg->sequencer,
+                 cfg->input,
+                 phy_channel,
+                 cfg->vref_mv,
                  sar_adc_count);
 
-    *value = sar_adc_mv;
+    if (sar_adc_mv < 0)
+    {
+        sar_adc_mv = 0;
+    }
+
+    *value = (rt_uint32_t)sar_adc_mv;
     return RT_EOK;
 }
 
-static const struct rt_adc_ops at_adc_ops =
+static const struct rt_adc_ops ifx_adc_ops =
 {
     .enabled = ifx_adc_enabled,
     .convert = ifx_get_adc_value,
 };
 
 static int rt_hw_adc_init(void)
 {
-    int result = RT_EOK;
-    int i = 0;
+    rt_err_t result = RT_EOK;
+    int i;
+
+    result = ifx_autonomous_analog_init_once();
+    if (result != RT_EOK)
+    {
+        return result;
+    }
 
     for (i = 0; i < sizeof(ifx_adc_obj) / sizeof(ifx_adc_obj[0]); i++)
     {
         /* register ADC device */
-        if (rt_hw_adc_register(&ifx_adc_obj[i].ifx_adc_device, ifx_adc_obj[i].name, &at_adc_ops, ifx_adc_obj[i].adc_ch) == RT_EOK)
+        if (rt_hw_adc_register(&ifx_adc_obj[i].ifx_adc_device,
+                               ifx_adc_obj[i].name,
+                               &ifx_adc_ops,
+                               ifx_adc_obj[i].cfg) == RT_EOK)
         {
-            LOG_D("%s register success", at32_adc_obj[i].name);
+            LOG_D("%s register success", ifx_adc_obj[i].name);
         }
         else
         {
@@ -105,4 +256,4 @@ static int rt_hw_adc_init(void)
 }
 INIT_BOARD_EXPORT(rt_hw_adc_init);
 
-#endif /* BSP_USING_ADC */
+#endif /* BSP_USING_ADC1 */

libraries/HAL_Drivers/drv_adc.h

@@ -12,7 +12,7 @@
 #define __ADC_CONFIG_H__
 
 #include <rtthread.h>
-#include "mtb_hal_adc.h"
+#include "cy_autanalog.h"
 
 
 
@@ -21,21 +21,98 @@ extern "C"
 {
 #endif
 
-#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
+#if defined(BSP_USING_ADC1)
 
+struct ifx_sar_adc_config
+{
+    uint8_t sar_idx;
+    uint8_t sequencer;
+    uint8_t max_channels;
+    uint32_t channel_mask;
+    bool low_power;
+    cy_en_autanalog_sar_input_t input;
+    uint32_t vref_mv;
+    const uint8_t *channel_map;
+};
+
+#endif
+
+#if defined(BSP_USING_ADC1)
+
+/* Logical ADC channels. */
+#define ADC_CHANNEL0    0
+#define ADC_CHANNEL1    1
+#define ADC_CHANNEL2    2
+#define ADC_CHANNEL3    3
+
+#define IFX_ADC_MAX_CHANNELS    4
+#define IFX_ADC_PHY_INVALID     0xFF
+
+/* Logical channel -> SAR result channel mapping (P15[4]..P15[7]). */
+#if defined(BSP_USING_ADC_CHANNEL0)
+#define ADC_CHANNEL0_GPIO  0
+#define ADC_CHANNEL0_MASK  (1u << ADC_CHANNEL0)
+#else
+#define ADC_CHANNEL0_GPIO  IFX_ADC_PHY_INVALID
+#define ADC_CHANNEL0_MASK  0u
+#endif
+
+#if defined(BSP_USING_ADC_CHANNEL1)
+#define ADC_CHANNEL1_GPIO  1
+#define ADC_CHANNEL1_MASK  (1u << ADC_CHANNEL1)
+#else
+#define ADC_CHANNEL1_GPIO  IFX_ADC_PHY_INVALID
+#define ADC_CHANNEL1_MASK  0u
+#endif
 
-mtb_hal_adc_channel_t adc_chan_obj;
+#if defined(BSP_USING_ADC_CHANNEL2)
+#define ADC_CHANNEL2_GPIO  2
+#define ADC_CHANNEL2_MASK  (1u << ADC_CHANNEL2)
+#else
+#define ADC_CHANNEL2_GPIO  IFX_ADC_PHY_INVALID
+#define ADC_CHANNEL2_MASK  0u
+#endif
 
+#if defined(BSP_USING_ADC_CHANNEL3)
+#define ADC_CHANNEL3_GPIO  3
+#define ADC_CHANNEL3_MASK  (1u << ADC_CHANNEL3)
+#else
+#define ADC_CHANNEL3_GPIO  IFX_ADC_PHY_INVALID
+#define ADC_CHANNEL3_MASK  0u
 #endif
 
+static const uint8_t adc1_channel_map[IFX_ADC_MAX_CHANNELS] =
+{
+    ADC_CHANNEL0_GPIO,
+    ADC_CHANNEL1_GPIO,
+    ADC_CHANNEL2_GPIO,
+    ADC_CHANNEL3_GPIO,
+};
+
+#define ADC1_CHANNEL_MASK (ADC_CHANNEL0_MASK | ADC_CHANNEL1_MASK | ADC_CHANNEL2_MASK | ADC_CHANNEL3_MASK)
+
+static const struct ifx_sar_adc_config adc1_cfg =
+{
+    .sar_idx = 0,
+    .sequencer = 0,
+    .max_channels = IFX_ADC_MAX_CHANNELS,
+    .channel_mask = ADC1_CHANNEL_MASK,
+    .input = CY_AUTANALOG_SAR_INPUT_GPIO,
+    .low_power = false,
+    .vref_mv = 1800,
+    .channel_map = adc1_channel_map,
+};
+
 #ifndef ADC1_CONFIG
 #define ADC1_CONFIG                 \
     {                               \
-        .adc_ch = &adc_chan_obj,    \
+        .cfg = &adc1_cfg,           \
         .name = "adc1",             \
     }
 #endif /* ADC1_CONFIG */
 
+#endif
+
 
 #ifdef __cplusplus
 }