update to v0.1.6

Author: dh-04

drivers/baremetal/drv_clk.c

@@ -41,13 +41,13 @@ void system_clock_config(int target_freq_mhz)
     RCC_OscInitStruct.PLL.PLLQ = 2;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Activate the Over-Drive mode
     */
     if (HAL_PWREx_EnableOverDrive() != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Initializes the CPU, AHB and APB busses clocks
     */
@@ -60,7 +60,7 @@ void system_clock_config(int target_freq_mhz)
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
 }
 

drivers/baremetal/drv_usart.c

@@ -212,7 +212,7 @@ static long stm32_gpio_clk_enable(GPIO_TypeDef *gpiox)
     return 0;
 }
 
-char * up_char(char * c)
+static int up_char(char * c)
 {
     if ((*c >= 'a') && (*c <= 'z'))
     {

drivers/nano/SConscript

@@ -32,5 +32,6 @@ include_str = """
 #include <stm32f7xx.h>
 """
 modify_board_h_file(os.path.join(cwd, file_path), include_str)
+os.remove(os.path.join(cwd,"SConscript"))
 
 Return('group')

drivers/nano/drv_clk.c

@@ -39,13 +39,13 @@ void system_clock_config(int target_freq_mhz)
     RCC_OscInitStruct.PLL.PLLQ = 2;
     if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Activate the Over-Drive mode
     */
     if (HAL_PWREx_EnableOverDrive() != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
     /** Initializes the CPU, AHB and APB busses clocks
     */
@@ -58,7 +58,7 @@ void system_clock_config(int target_freq_mhz)
 
     if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK)
     {
-      Error_Handler();
+        Error_Handler();
     }
 }
 

drivers/nano/drv_usart.c

@@ -223,14 +223,15 @@ static rt_err_t stm32_gpio_clk_enable(GPIO_TypeDef *gpiox)
     return RT_EOK;
 }
 
-char * up_char(char * c)
+static int up_char(char * c)
 {
     if ((*c >= 'a') && (*c <= 'z'))
     {
         *c = *c - 32;
     }
     return 0;
 }
+
 static void get_pin_by_name(const char* pin_name, GPIO_TypeDef **port, uint16_t *pin)
 {
     int pin_num = atoi((char*) &pin_name[2]);
@@ -372,4 +373,3 @@ char rt_hw_console_getchar(void)
 }
 #endif /* RT_USING_FINSH */
 #endif /* RT_USING_CONSLONE */
-

drivers/rtt/SConscript

@@ -32,5 +32,6 @@ include_str = """
 #include <stm32f7xx.h>
 """
 modify_board_h_file(os.path.join(cwd, file_path), include_str)
+os.remove(os.path.join(cwd,"SConscript"))
 
 Return('group')

drivers/rtt/drv_usart.c

@@ -1,3 +1,14 @@
+/*
+ * Copyright (c) 2006-2020, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2018-10-30     SummerGift   first version
+ * 2020-05-23     chenyaxing   modify stm32_uart_config
+ */
+
 #include "string.h"
 #include "stdlib.h"
 #include <board.h>
@@ -320,14 +331,15 @@ static rt_err_t stm32_gpio_clk_enable(GPIO_TypeDef *gpiox)
 
     return RT_EOK;
 }
-char * up_char(char * c)
+static int up_char(char * c)
 {
     if ((*c >= 'a') && (*c <= 'z'))
     {
         *c = *c - 32;
     }
     return 0;
 }
+
 static void get_pin_by_name(const char* pin_name, GPIO_TypeDef **port, uint16_t *pin)
 {
     int pin_num = atoi((char*) &pin_name[2]);